a8e re AdLib OCR Evaluation systems Data Sheet, Rev. 3 October 2002 Agere Systems USB 2.0 UTMI USS2X1 A 8-Bit and USS2X1 WA 16-Bit PHY Chips =~ff Introduction Description The USS2X1(W)A PHY chip provides a serial electrical interface that is compliant with the USB specification revision 2 .0. The chip contains sufficient capabilities to allow it to function as a USB 2 .0 device when coupled to an intelligent application through its 8-/16-bit interface . The USS2X1(W)A PHY chip may be used in conjunction with an ASIC to provide a two-chip solution for a USB 2 .0 device . The chip may also be used in conjunction with FPGAs to prototype a USB 2 .0 device . The chip uses a 8-/16-bit parallel interface that is compliant with the Intel(R)USB 2.0 Transceiver Macrocell Interface Specification (UTMI) . In the transmit direction (to the host), the chip performs parallel-to-serial conversion, plus the required bit stuffing and NRZI encoding . It also generates the required SYNC and EOP fields for outgoing packets . In the receive direction (from the host), the chip performs serial-to-parallel conversion, plus the required bit unstuffing and NRZI decoding . It also detects and strips the SYNC and EOP fields from incoming packets . The receive logic also detects bit stuff error (FS mode only), elasticity buffer underrun or overrun (HS mode only), and byte-alignment errors (either mode) . All device terminations required by the USB 2 .0 specification are contained inside the USS2X1(W)A . This includes the DP/DM 45 S2 termination to ground in HS mode, the DP/DM 45 S2 series termination in FS mode, and the 1 .5 kn pull-up resistor on DP when in FS mode. The chip also includes appropriate control for the 1 .5 kn DP pull-up, which is needed when switching between FS and HS modes. The USS2X1(W)A supports the high-speed detection sequence defined in the USB 2 .0 specification, which is performed after USB reset to determine the highestspeed capability of the upstream and downstream entities. The USS2X1(W)A has the ability to transmit a Chirp K and detect a Chirp K/Chirp J pattern, as required by the high-speed detection sequence. The USS2X1(W)A supports test modes defined in the USB 2 .0 specification that are appropriate for upstream-facing ports : Test SEO NAK, Test J, Test K, and Test Packet. The USB 2.0 specification requirements for current draw in suspend mode can be met by asserting the SUSPENDN input pin . This turns off internal clocks and the CLKOUT output, and places the internal analog components into low-power mode. When the SUSPENDN input is deasserted, the USS2X1(W)A turns on internal clocks, begins asserting the CLKOUT output after internal clocks have stabilized, and returns the internal analog components to their operational state . Features . UTMI/USB 2.0 compliant . . Operates in both USB 2 .0 high-speed (HS) (480 Mbits/s) and USB 1 .1 full-speed (FS) (12 Mbits/s) modes . . Performs serial-to-parallel and parallel-to-serial conversions . . All required terminations, including 1 .5 kn pull-up on DP, are internal to chip. . Detects SYNC field and EOP on receive packets . . Generates SYNC field and EOP on transmit packets. . Recovers data and clock recovery from the USB serial stream . . Performs bit stuffing/unstuffing; bit stuff error detection . . Staging register manages data rate variation due to bit stuffing/unstuffing . . 8-bit, 60 MHz (16-bit, 30 MHz) parallel interface . . Ability to switch between full-speed and high-speed terminations and signaling . . 30 MHz external crystal, plus internal oscillator and PILL used to generate higher-speed internal clocks and CLKOUT output. . Supports detection of USB reset, suspend, and resume . . Supports high-speed identification and detection as defined by USB 2.0 specification . . Supports transmission of resume signaling . . Supports test modes defined by USB 2.0 specification . . Available in two packages : USS2X1 A 48-pin TQFP (8-bit) and USS2X1 WA 64-pin TQFP (16-bit) . AdLib OCR Evaluation Agere Systems USB 2 .0 UTMI USS2X1 A 8-Bit and USS2X1 WA 16-Bit PHY Chips Data Sheet, Rev. 3 October 2002 Table of Contents Contents 2 Page ..4 ..5 . .5 ..5 ..5 ..5 ..5 . .5 ..5 .. 6 ..7 ..7 . .7 . .8 .. 9 .. 9 10 10 10 11 11 12 13 13 14 17 18 19 20 21 21 21 23 24 24 26 28 29 30 30 32 33 33 33 35 36 38 38 39 39 Agere Systems Inc . Data Sheet, Rev. 3 October 2002 Agere Systems USB 2 .0 UTMI AdLib OCR Evaluation USS2X1 A 8-Bit and USS2X1 WA 16-Bit PHY Table of Contents (continued) Figure Page Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure 1 . USB 2 .0 USS2X1 A 8-Bit and USS2X1 WA 16-Bit PHY Chips . . . . . . .. . . . .. . . . .. . . .. . . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . .. . . . .. . .. .4 2. 48-Pin TQFP Package Pin Assignments . . . .. . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . . .. . . . .. . . .. . . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. .7 3. 64-Pin TQFP Package Pin Assignments . . . .. . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . . .. . . . .. . . .. . . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. .8 4. HS Transmit Timing for a Data Packet (8-Bit) . . . .. . . . .. . . .. . . . .. . . .. . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . . .. . . . .. . . .. . . . .. . . . .. . . . .. . .13 5. HS Receive Timing for Data with Unstuffing Bits (8-Bit) .. . . . .. . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . . .. . . . .. . . .. . . . .. . . . . . . . .. . . .14 6. HS Receive Timing for Data Packet (with CRC-16) (8-Bit) .. . . .. . . . .. . . . .. . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . . .. . . . .. . . . .. . . .15 7. HS Receive Timing for Setup Packet (8-bit) . . . . . .. . . .. . . . .. . . . .. . . . .. . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . . .. . . . .. . .. .. . . .. . . . . . . . .. . . .16 8. HS Receive Timing for a Handshake Packet (No CRC) (8-bit) . . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . . .. . . . .. . .. . . . .. . . . .. . . .. .. . .16 9. HS Transmit Timing for 16-Bit Data, Even Byte Count . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . . .. . . . .. . . .. . . . .. . . . . . . . .. . . .. . . . . . . . .. . . .18 10 . HS Transmit Timing for 16-Bit Data, Odd Byte Count . . .. . . . .. . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . . .. . . . . . . . . .. . . .18 11 . HS Receive Timing for 16-Bit Data, Even Byte Count . .. . . . .. . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . . .. . . . . . . . . .. . . .19 12 . HS Receive Timing for 16-Bit Data, Odd Byte Count . . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . . .. . . . .. . . .. . . . .. . . . . . . . .. . . .. . . . .. . . . .. . .19 13 . FS CLKOUT Relationship to Receive Data and Control Signals . . . . .. . . . .. . . .. . . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . .. . . . .. . .20 14. FS CLKOUT Relationship to Transmit Data and Control Signals .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . .. . . . .. . . .. . . . .. . . . .. .20 15 . Suspend Timing Behavior (HS Mode) .. . . . .. . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . . .. . . . .. . . .. . . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . .22 16 . Reset Timing Behavior (HS Mode) . . . . .. . . .. . . . .. . . . .. . . .. . . .. . . . .. . . . .. . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . . .. . . . .. . . . .. . . .. . . . . . . . .. . . .23 17. HS Detection Handshake Timing Behavior (FS Mode) . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . . .. . . . .. . . .. . . . .. . . . . . . . .. . . .. . . . . . . . .. . . .25 18 . Chirp K-J-K-J-K-J Sequence Detection State Diagram . .. . . .. . . . . . . . .. . . . .. . . . .. . . .. . . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . .26 19 . HS Detection Handshake Timing Behavior (HS Mode) . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . . .. . . . .. . . .. . . . .. . . . . . . .. . . . .. . . . . . . . .. . . .27 20 . HS Detection Handshake Timing Behavior from Suspend .. . . . . . . . .. . . . .. . . . .. . . .. . . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . .28 21 . Resume Timing Behavior (HS Mode) .. . . .. . . . . . . . .. . . .. . . . .. . . . .. . . . .. . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . . .. . . . .. . .. . . . . .. . . . . . . . .. . . .29 22 . Device Attach Behavior . . . . . . . . .. . . .. . . . .. . . . .. . . . .. . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . . .. . . . .. . . .. . . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . .. . . . .. . .31 23 . Timing Constraints . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . .. . . . .. . . . .. . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . . .. . . . . . . .. .. . . .. . . . . . . . .. . . .. . . . .. . . . .. . .36 Table Page Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table 1 . Control Interface Pins . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . .. . . . .. . . . .. . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . . .. . . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. .9 2 . USB Interface Pins .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . .. . . . .. . . . .. . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . . . . . . .. . . . .. . . . . . . . .. . . .. . . . . . . . .. . . .10 3 . Data Input/Output Pins (8-Bit Transmit and Receive) . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . . .. . . . .. . . .. . . . .. . . . . . . . .. . . .10 4. Data Input/Output Pins (16-Bit Transmit and Receive) . . . . .. . . .. . . . . . . . .. . . . .. . . . .. . . .. . . . .. . . .. . . .. . . . .. . . . . . . . .. . . .. . . . .. . . . .. . .10 5 . Data Input Pins (Transmit) . .. . . . .. . . .. . . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . . .. . . .. . . . .. . . . .. . . .. . . . .. . . .. . . . . . . . .. . . . . .. . . . . . . . .. . . .. . . . . . . . .. . . .11 6 . Data Output Pins (Receive) .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . .. . . . .. . . . .. . . .. . . .. . . . .. . . .. . . . .. . . .. . . . . . . . .. . . .. .. . . . . . . . .. . . .. . . . . . . . .. . . .11 7. Power/Test Pins . . . .. . . . .. . . .. . . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . .. . . . .. . . . .. . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . . .. . . . .. . . . . . . . .. . . .. . . . . . . . .. . . .12 8 . Suspend Timing Values (HS Mode) . . .. . . .. . . . .. . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . . .. . . . .. . . .. . . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . .22 9 . Reset Timing Values (HS Mode) . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . .. . . . .. . . . .. . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . . .. . . . . . . . . .. . . .. . . . . . . . .. . . .23 10. HS Detection Handshake Timing Values (FS Mode) . . . . .. . . . .. . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . . .. . . . .. . . .. . . . .. . . . . . . . .. . . .25 11 . Reset Timing Values .. . . .. . . . . . . . .. . . .. . . . .. . . . .. . . . .. . .. . . . .. . . . .. . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . . .. . . . .. . . .. . . . .. . . . . . . . .. . . .. . . . . . . . .. . . .27 12. HS Detection Handshake Timing Values from Suspend .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . . .. . . . .. . . .. . . . .. . . . . . . . .. . . .. . . . . . . . .. . . .29 13 . Suspend Timing Values (HS Mode) . . . .. . . .. . . . .. . . . .. . . . .. . . .. . . .. . . . .. . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . . .. . . . .. . . . .. . . .. . . . . . . . .. . . .30 14. Attach and Reset Timing Values . . . . .. . . . .. . . . .. . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . . .. . . . .. . . .. . . . .. . . . . . . . .. . . .. . . . .. . . . .. . .31 15. USB 2 .0 Test Mode to USS2X1 Mapping . .. . . . . . . . .. . . .. . . . . . . . .. . . . .. . . . .. . . .. . . . .. . . . . . . .. . . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . .. . . . .. . .32 16 . do Characteristics .. . . . .. . .. . . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . .. . . . .. . . . .. . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . . .. . . . .. . . . . . . . .. . . .. . . . . . . . .. . . .33 17. ac Characteristics .. . . . .. . .. . . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . .. . . . .. . . . .. . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . . .. . . . .. . . . . . . . .. . . .. . . . . . . . .. . . .33 18 . ac Timing (16-Bit) . . . . .. . . .. . . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . .. . . . .. . . . .. . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . . .. . . . .. . . . . . . . .. . . .. . . . . . . . .. . . .34 19 . ac Timing (8-Bit) . .. . . . .. . . .. . . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . . .. . . .. . . . .. . . . .. . . .. . . . .. . . .. . . . . . . . . .. . . . .. . . . . . . . .. . . .. . . . . . . . . .. . .35 20. Timing Constraints for USS2X1 (8-Bit) . . . .. . . . . . . . .. . . .. . . . .. . . . .. . . . .. . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . . .. . . . .. . . . .. . . .. . . . . . . . .. . . .36 21 . Timing Constraints for USS2X1 (8-Bit) . . . .. . . . . . . . .. . . .. . . . .. . . . .. . . . .. . . .. . . . .. . . .. . . . . . . . .. . . .. . . . . . . . .. . . . .. . . . .. . . . .. . . .. . . . . . . . .. . . .37 Agere Systems Inc. 3 AdLib OCR Evaluation Agere Systems USB 2 .0 UTMI USS2X1 A 8-Bit and USS2X1 WA 16-Bit PHY Chips Data Sheet, Rev. 3 October 2002 Functional Block Diagram Figure 1 shows the functional block diagram of the USB 2.0 PHY chip. Each block is described below. It is assumed that the control and data interface pins are externally connected to a logic block that performs the next layer of USB processing, such as packet decoding . In this document, the external logic block that performs this function is referred to as the SIE (serial interface engine) . USB 2.0 USS2X1 A 8-bit AND USS2X1 WA 16-bit PHY CHIP RESETN SUSPENDN CLOCK CONTROL ------- XI XO CLKOUT PLL RREF TXVALID TRANSMIT LOGIC TXREADY BIT STUFF NRZIENCODE DATAf15 :0]* DATA[7 :0]* VALIDHt --I F I I I RECEIVE LOG I C OPMODE[1 :0] RXVALID USB TRANSCEIVER HS/FS ELASTICITY BUI FFER I HS CI I u TERMSELECT BIT UNSTUFF NRZI DECODE RXERROR FS XCVRSELECT RXACTIVE LINESTATE[1 :0] [ DP, DM I LIDETECTE 5-9296(F) .b R.02 * DATA[15 :0] only exists on the 16-bit PHY chip, and DATA[7 :0] only exists on the 8-bit PHY chip . t VALIDH only exists on the 16-bit PHY chip . Figure 1 . USB 2.0 USS2X1A 8-Bit and USS2X1WA 16-Bit PHY Chips 4 Agere Systems Inc . Data Sheet, Rev. 3 October 2002 AdLib OCR Evaluation Agere Systems USB 2.0 UTMI USS2X1 A 8-Bit and USS2X1 WA 16-Bit PHY Chips Functional Block Diagram (continued) Clock Control and PLL The clock control and PILL blocks generate the appropriate internal clocks for the USS2X1(W)A and the CLKOUT output signal (60 MHz for the 8-Bit USS2X1 A and 30 MHz for the 16-Bit USS2X1 WA) . An external 30 MHz crystal must be connected to the XI and XO pins to provide a reference clock for these blocks . All data transfer signals are synchronized with the CLKOUT output . After the deassertion of SUSPENDN, the CLKOUT signal generated by the USS2X1(W)A will behave as follows: . Produce the first CLKOUT transition no later than 5 .6 ms after the deassertion of SUSPENDN . The CLKOUT signal frequency error will be less than 10% . . The CLKOUT signal will fully meet the required accuracy of 500 ppm, no later than 1 .4 ms after the first transition of CLKOUT. In HS mode, there is one CLKOUT cycle per byte time for the 8-Bit USS2X1 A . In FS mode for the USS2X1 A, there are 5 CLKOUT cycles per FS bit time and 40 CLKOUT cycles per FS byte time. If a received byte contains a stuffed bit, then the byte boundary can be stretched to 45 CLKOUT cycles and two stuffed bits would result in a 50 CLKOUT delay between bytes . The frequency of CLKOUT does not change when the USS2X1(W)A is switched between HS and FS modes . The XCVRSELECT signal determines whether the HS or FS timing relationship is applied to the data and control signals . High-Speed (HS) Clock Data Recovery (CDR) The clock data recovery (CDR) block recovers the serial 480 Mbits/s data received by the transceiver when in HS mode, as indicated by the XCVRSELECT input . Elasticity Buffer As defined in the USB 2 .0 specification, the elasticity buffer manages any differences between the local clock frequency (derived from the crystal oscillator) and the rate at which HS data is received. The USB specification defines a maximum clock error of 500 ppm . When the error is calculated over the maximum packet size and when the other system timing margin is taken into consideration, up to 12 bits of drift can occur. At the start of a packet, the elasticity buffer is Agere Systems Inc . filled to a threshold prior to enabling the remainder of the downstream receive logic. Overflow or underflow conditions detected in the elasticity buffer are reported with the RXError signal . Transmit Logic The transmit logic block is responsible for accepting 8-/16-bit parallel data from the parallel application bus (i .e., the SIE) interface upon command and serializing it for transmission over the USB 2.0 interface . This module also includes logic for bit stuffing, NRZI encoding, SYNC field, and EOP generation . This block is used for both HS and FS transmit. Receive Logic The receive logic block is responsible for deserializing received data recovered by the HS CDR or FS CDR, and providing 8-/16-bit parallel data to the application's parallel interface with the SIE . This module also includes logic for bit unstuffing, NRZI decoding, SYNC field and EOP field detection, and stripping . This block is used for both HS and FS receive . USB Transceiver The USB transceiver is capable of transmitting and receiving at the HS or FS bit rates and edge rates, as controlled by the XCVRSELECT input . The transceiver also detects line inactivity (squelch) and the line state in both HS and FS modes . All termination resistors required by the USB 2 .0 specification are located internally, and are controlled by the TERMSELECT input . Full-Speed (FS) Clock Data Recovery (CDR) The full-speed (FS) clock data recovery (CDR) block recovers the serial 12 Mbits/s data received by the transceiver when in FS mode, as indicated by the XCVRSELECT input . This block also accounts for any differences between the local clock frequency, i.e ., crystal oscillator, and the rate at which FS data is received . Line State Detect Reports the logic state received from either the HS or FS output of the transceiver . 5 AdLib OCR Evaluation Agere Systems USB 2 .0 UTMI USS2X1 A 8-Bit and USS2X1 WA 16-Bit PHY Chips Data Sheet, Rev. 3 October 2002 Functional Block Diagram (continued) Speed Selection The XCVRSELECT and TERMSELECT signals determine whether the device is in HS or FS mode, enabling the respective transceiver and termination . The HS detection handshake protocol requires independent control of transceivers and terminations, where the device enables FS terminations but is required to drive and listen to the bus with the HS transceiver. In all other cases, the state of the XCVRSELECT and TERMSELECT signals are identical . Note: Most sections of this document assume that the USS2X1 A is operating with an 8-bit interface . The timings need to be adjusted appropriately for operation using a 16-bit interface . The timing differences will be explained where necessary. Unless differences are specified, it may be assumed that the 16-bit USS2X1 WA functions in the same manner as the 8-bit USS2X1A . Agere Systems Inc . AdLib OCR Evaluation Agere Systems USB 2.0 UTMI Data Sheet, Rev. 3 October 2002 USS2X1 A 8-Bit and USS2X1 WA 16-Bit PHY Chips Pin Information Pin Assignments 48-Pin TQFP 0 TESTGND 1 . Ir } W o o > F (/J c) > F-w W F- > Ir w X or W I X F- 00 V I~ V (O V Ln V V V o 0 J J O J U w w > > X or > X F- F- Q p > N V V O V d1 M 00 M I~ M - D Q X or O M V 36 VSSN 35 TESTGND 34 DATA[l] VSST 2 DM 3 DP 4 33 DATA[2] VDDT 5 32 DATA[3] RREF VDDA PIN #1 IDENTIFIER 6 AGERE USB 2.0 USS2X1 A 8-bit PHY CHIP 7 31 DATA[4] 30 VDD 29 TESTGND VSSA 8 XI 9 28 DATA[5] XO 10 27 DATA[6] VDDX 11 26 DATA[7] SUSPENDN 12 25 VSS CM r cn > V r > Ln r (O r I: r U U W W > w J w J (n (n X F- 00 r w > d1r ON N NN r o r o Q Q Q F- Q F- a W W CMNVN o w w w w > D D F- F- 2 2 O O Z J W W Z J 0564 (F) R.03 Figure 2 . 48-Pin TQFP Package Pin Assignments Agere Systems Inc. 7 AdLib OCR Evaluation Agere Systems USB 2 .0 UTMI USS2X1 A 8-Bit and USS2X1 WA 16-Bit PHY Chips Data Sheet, Rev. 3 October 2002 Pin Information (continued) Pin Assignments (continued) 64-Pin TQFP z z TESTGND C7 0 U) > W F- W F- V (M N (0(0(0 1 o o > F- w z > W F- o > O W (O 0 (O Ln IrC o w U = X or X F- X or O U W Ln M Ln (O Ln w > M Ln V Ln 0 o o_ Q J Q > X or X F- M N Ln Ln Ln Q 0 z o > O W Ln V 48 VSSN 47 DATA[i ] 46 DATA[2] VSST 2 VDDT 3 DM 4 45 DATA[3] DP 5 44 DATA[4] VDDT 6 43 VDD VSST 7 42 8 DATA[5] RREF 41 DATA[6] 40 DATA[7] 39 DATA[8] \",--PIN #1 IDENTIFIER AGERE USB 2 .0 USS2X1 WA 16-bit PHY CHIP VDDA VSSA 10 XI 11 38 VSS XO 12 37 DATA[9] VDDX 13 36 14 DATA[10] VDD 35 DATA[i 1 ] SUSPENDN 15 34 16 DATA[12] VSS 33 VSSN I~ r 00 r d1 r > > > O N N U U U w J -j N N CM N V N can T > 0 0 d d Ln N (O N 11 N W N W N O M o r o o z ~W r_ v h o r_ r_ Q Q 0 0 0 > U) ~ Z J Z J Q M N C') > 0563 (F) R.03 Figure 3. 64-Pin TQFP Package Pin Assignments 8 Agere Systems Inc . Data Sheet, Rev. 3 October 2002 AdLib OCR Evaluation Agere Systems USB 2.0 UTMI USS2X1 A 8-Bit and USS2X1 WA 16-Bit PHY Chips Pin Information (continued) Pin Descriptions Control Interface Pins Table 1 . Control Interface Pins Pin Pin Number Number (48-Pin) (64-Pin) Name Direction Active Level 9 10 42 11 12 55 XI XO CLKOUT Input Output Output NA NA NA 24 16 28 20 RESETN XCVRSELECT Input Input Low NA 17 21 TERMSELECT Input NA 12 15 SUSPENDN Input Low 21,22 25,26 LINESTATE [1 :0] Output NA 19,20 23,24 OPMODE [1 :0] Input NA Agere Systems Inc. Description Oscillator Input. Connect to external 30 MHz crystal . Oscillator Output . Connect to external 30 MHz crystal. Clock . This output is used for clocking receive and transmit parallel data. 60 MHz (8-bit only) . 30 MHz (16-bit only) . Reset . Hardware reset . Transceiver Select . This signal selects between the FS and HS transceivers : 0: HS transceiver enabled . 1 : FS transceiver enabled. Termination Select . This signal selects between the FS and HS terminations: 0: HS termination enabled. 1 : FS termination enabled. Suspend . Places the USS2X1(W)A in a mode that draws minimal power from supplies. Shuts down all blocks not necessary for suspend/resume operation . While suspended, TERMSELECT must always be in FS mode to ensure that the 1 .5 ktl pull-up on DP remains powered . 0: USS2X1(W)A drawing suspend current. 1 : USS2X1(W)A drawing normal current . Line State. While the device is suspended and while the device is resuming from a suspended state, these signals are combinatorial, i.e ., directly reflect the current state of the DM and DP signals . Otherwise, these signals are synchronized to the CLKOUT output . _DM DP Description 0 0 0 : SEO 0 1 1 : J state 1 0 2 : K state 1 1 3 : SE1 Operational Mode. These signals select between various USS2X1(W)A operational modes : OPMODE [1 :0] Description 0 0 0 : Normal operation 0 1 1 : Nondriving all terminations removed 1 0 2 : Disable bit stuffing and NRZI encoding 1 1 3 : Reserved 9 AdLib OCR Evaluation Agere Systems USB 2 .0 UTMI USS2X1 A 8-Bit and USS2X1 WA 16-Bit PHY Chips Data Sheet, Rev. 3 October 2002 Pin Information (continued) Pin Descriptions (continued) USB Interface Pins Table 2. USB Interface Pins Pin Pin Number Number (48-Pin) (64-Pin) 4 3 6 5 4 8 Name DP DM RREF Direction Active Level Bidir Bidir NA NA NA NA Description USB Data Pin Data+ . USB Data Pin Data- . External Reference . Requires 1 % precision 1 k52 resistor to ground. Data Input/Output Pins (8-Bit) Table 3. Data Input/Output Pins (8-Bit Transmit and Receive) Pin Number (48-Pin) Name Direction Active Level 26-28, 31 -34 , 38 DATA [ 7 : 0] Bidir NA Description TXVALID RXVALID 0 0 0 1 1 X DATA[7 :0] Not in use . Data [7 :0] output is valid for receive . Data [7 :0] output is valid for transmit . Data Input/Output Pins (16-Bit) Table 4. Data Input/Output Pins (16-Bit Transmit and Receive) Pin Number (64-Pin) Name Direction Active Level 29-31, 34-37 , 39-42 , 44-47, 50 DATA [ 15 : 0 ] " Bidir NA 53 VALIDH* Bidir Description TXVALID RXVALID 0 0 High 0 1 VALIDH DATA[15 :0] X 0 Not in use . Data [7 :0] output is valid for receive . 0 1 1 Data [15 :0] output is valid for receive . 1 X 0 Data [7:0] output is valid for transmit . 1 X 1 Data [15 :0] output is valid for transmit . If TXVALID = 1, this chip's input, when asserted, indicates that the entire 16-bit DATA input is to be transmitted over USB . If deasserted, it indicates that only DATA [7:0] is to be transmitted . If TXVALID = 0 and RXVALID = 1, this chip's output, when asserted, it indicates that the entire 16-bit DATA output is valid. If deasserted, it indicates that only DATA [7:0] is valid . * Pull-down resistance is 50 kit, nominal . 10 Agere Systems Inc . Data Sheet, Rev. 3 October 2002 AdLib OCR Evaluation Agere Systems USB 2.0 UTMI USS2X1 A 8-Bit and USS2X1 WA 16-Bit PHY Chips Pin Information (continued) Pin Descriptions (continued) Data Input Pins (Transmit) Table 5. Data Input Pins (Transmit) Pin Pin Number Number (48-Pin) (64-Pin) Pin Name Pin Active Direction Level 39 51 TXVALID Input High 44 57 TXREADY Output High Description Transmit Valid. Indicates that the DATA bus is a valid input . The assertion of TXVALID initiates SYNC on the USB . The negation of TXVALID initiates EOP on the USB . Transmit Data Ready. Indicates that the transmitter requires data. The application must have data available for clocking in to the DATA inputs on the rising edge of CLK . If TXVALID is negated, TXREADY can be ignored by the application . Data Output Pins (Receive) Table 6. Data Output Pins (Receive) Pin Pin Number Number (48-Pin) (64-Pin) Pin Name Pin Active Direction Level 40 52 RXVALID Output High 43 56 RXACTIVE Output High 45 58 RXERROR Output High Description Receive Data Valid. Indicates that the DATA bus has valid data. The application is expected to latch the DATA bus on the clock edge. Receive Active . Indicates that the receive state machine has detected SYNC and is active . RXActive is negated after a bit stuff error or an EOP is detected. Receive Error. 0: Indicates no error. 1 : Indicates that a receive error has been detected. Possible sources of errors are as follows : . Bit stuff error has been detected during a FS receive operation . . Elasticity buffer overrun . . Elasticity buffer underrun . . Alignment error, EOP not on a byte boundary. Agere Systems Inc. 11 AdLib OCR Evaluation Agere Systems USB 2 .0 UTMI USS2X1 A 8-Bit and USS2X1 WA 16-Bit PHY Chips Data Sheet, Rev. 3 October 2002 Pin Information (continued) Pin Descriptions (continued) Power/Test Pins Table 7. Power/Test Pins Pin Pin Number Number (48-Pin) (64-Pin) 15, 23, 30,46 18, 25, 41,48 14,37 13,36 8 5 2 7 11 1, 29, 35,47 12 14, 19, 27, 43, 59 16, 22, 38, 54, 61,64 18, 32, 49 17, 33, 48 10 3,6 2,7 9 13 1, 60, 62,63 Pin Name Pin Direction Active Level VDD NA NA Chip Power. VDD = 3 .3 V 5%. Vss NA NA Chip Ground . VDDN NA NA 10 Power. VssN NA NA 10 Ground . VssA NA NA NA NA NA Input NA NA NA NA NA High Analog Ground . Transceiver Power. Transceiver Ground . Analog Power. Oscillator Power. Test Ground . Inputs for hardware test modes . Must be connected to ground . VDDT VssT VDDA VDDX TESTGND Description Agere Systems Inc . Data Sheet, Rev. 3 October 2002 AdLib OCR Evaluation Agere Systems USB 2.0 UTMI USS2X1 A 8-Bit and USS2X1 WA 16-Bit PHY Chips HS Functionality of the USS2X1 A packet ID (PID) or CRC fields . When transmitting, the SIE is always expected to present a PID field as the first byte of the data stream and, if appropriate, a CRC field as the last byte (bytes) of the data stream . HS Transmit (8-Bit) The HS transmit logic for the USS2X1 A is controlled in the following manner: Figure 4 shows the timing relationship in the HS mode between TXValid, DATA input, TXReady, and the transmitted data (DP/DM) . . The SIE asserts TXValid to begin a transmission . The SIE negates TXValid to complete a packet . Once negated, the transmit logic will not reassert TXReady until after the EOP has been generated. Note that although the USS2X1(W)A transmit logic can be ready to start another packet immediately, the SIE must conform to the minimum interpacket delay identified in Section 7 .1 .18 of the USB 2 .0 specification . . The SIE negates TXValid to end a transmission . . After the SIE asserts TXValid, it must assume that the transmission has started when it detects TXReady is asserted . . The SIE must assume that the USS2X1 A has consumed a data byte if TXReady and TXValid are asserted . In HS mode, if an error condition occurs during transmission, the current transmit stream must be terminated by the transmission of a complemented version of the CRC, followed by an EOP. In this case, the SIE will be responsible for presenting the complemented CRC to the DATA input lines before negating TXValid . . The SIE must have valid packet information (PID) asserted on the DATA input bus coincident with the assertion of TXValid . TXReady may be asserted at the same time as TXValid or later. . TXValid and TXReady are sampled on the rising edge of CLKOUT The negation of TXValid will cause the USS2X1(W)A to terminate the packet with the appropriate EOP . . The transmit logic does not automatically generate CLKOUT ' TXVALID DATAIN(7 :0)PID' XDATAXDATAXDATAXDATAX CRC X CRC ~VVVVV~ TXREADY ~ DP/DM SYNC PI D DATA DATA DATA DATA CRC CRC EOP 0899 (F) Figure 4. HS Transmit Timing for a Data Packet (8-Bit) Agere Systems Inc . 13 AdLib OCR Evaluation Agere Systems USB 2 .0 UTMI USS2X1 A 8-Bit and USS2X1 WA 16-Bit PHY Chips HS Functionality of the USS2X1 A (continued) HS Receive (8-Bit) The HS receive logic behavior is controlled/indicated as follows : . RXActive and RXValid are sampled on the rising edge of CLKOUT . The receiver will initially look for SYNC. . The USS2X1 A asserts RXActive when SYNC is detected, and will strip the SYNC field . . The USS2X1 A negates RXActive when an EOP is detected and will strip the EOP field . . When RxActive is asserted, RXValid will be asserted if valid data is available on the data outputs . . RXValid will be negated if valid data is not available on the data outputs . This will occur if 8 stuffed bits have been accumulated . . The SIE must be ready to consume a data byte if RXActive and RXValid are asserted. The possible sources of HS receive errors are as follows : . Bit stuff error has been detected during an FS receive operation . Data Sheet, Rev. 3 October 2002 If any of these receive errors is detected, RXError is asserted. When the last data byte is clocked off the DATA output bus, the SIE must also capture the state of the RXError signal . Note : In HS mode, bit stuff errors are used to generate the EOP signal ; therefore, the RXError signal is not asserted in this case. Figure 6 shows the timing relationship between the received data (DP/DM), RXValid, RXActive, RXError, and DATA output signals . Note that the USS2X1(W)A does not decode packet IDs (PIDs) . They are passed to the SIE for decoding . The receive section of the USS2X1(W)A is disabled when the transmit section is active . The USS2X1(W)A does not respond to downstream USB traffic while the SIE is transmitting . Although the bit rate on USB is constant, the bit rate as presented by the USS2X1(W)A to the SIE is slightly reduced due to the extraction of inserted 1 bits. Normally, a byte of data is presented on the DATA outputs for every 8 bits received . However, after eight stuffed bits are eliminated from the data stream, a byte time is skipped in the DATA output stream . Figure 5 shows how RXValid is used to skip bytes in the DATA output stream . This example shows the timing in HS mode for the 8-bit USS2X1 A . . Elasticity buffer overrun . . Elasticity buffer underrun . . Alignment error, i .e., EOP not on a byte boundary . CLKOUT ' RXACTIVE i i INVALID DATA, I DATAOUT(7 :0) RXVALID i 0892 (F) Figure 5. HS Receive Timing for Data with Unstuffing Bits (8-Bit) 14 Agere Systems Inc . AdLib OCR Evaluation Agere Systems USB 2.0 UTMI Data Sheet, Rev. 3 October 2002 USS2X1 A 8-Bit and USS2X1 WA 16-Bit PHY Chips HS Functionality of the USS2X1 A (continued) Note: Figure 6, Figure 7, and Figure 8 are timing examples of the USS2X1 A when it is in HS mode. When in FS mode, there are approximately 40 CLK cycles every byte time. The receive logic assumes that the SIE captures the data on the DATA output bus if RXActive and RXValid are asserted . In FS mode, RXValid will only be asserted for one CLK per byte time. CLKOUT ' RXACTIVE DATAOUT(7 :0)~( X X )( )( ) I I IYYY~LIL I PID I X DATA X DATA X DATA X DATA 1 I I I I CRC I 11 CRC I~WvI RXVALID RXERROR DP/DM i SYNC PID x DATA x DATA A DATA A DATA CRC x CRC x EOP CRC-16 COMPUTATION 0894 (F) Figure 6. HS Receive Timing for Data Packet (with CRC-16) (8-Bit) In Figure 6, Figure 7, and Figure 8, the SYNC pattern on DP/DIVI is shown as one byte long . In reality, the SYNC pattern received by a USB high-speed device can vary in length . These three figures assume that all but the last 12 bits have been consumed by the hubs between the device and the host controller. It should also be noted that in these three figures, the packet received on DP/DIVI is pipelined by the USS2X1(W)A and may occur several bit times, or even several byte times earlier, relative to the USS2X1(W)A signal transitions (RXActive, DATA output, RXValid, etc .) . Agere Systems Inc. 15 AdLib OCR Evaluation Agere Systems USB 2 .0 UTMI USS2X1 A 8-Bit and USS2X1 WA 16-Bit PHY Chips Data Sheet, Rev. 3 October 2002 HS Functionality of the USS2X1 A (continued) CLKOUT ' RXACTIVE DATAOUT(7 :0) MXWM PID DAT A X DAT A r i r RXVALID RXERROR DP/DM ~~ SYNC x PID x DATA x DATA X EOP CRC-5 COMPUTATION 0895 (F) Figure 7. HS Receive Timing for Setup Packet (8-bit) . CLKOUT . RXACTIVE DATAOUT(7 :0) PID RXVALID RXERROR i DP/DMSYNC X PID EOP YYYYYYYYYY 0896 (F) Figure 8. HS Receive Timing for a Handshake Packet (No CRC) (8-bit) 16 Agere Systems Inc . Data Sheet, Rev. 3 October 2002 AdLib OCR Evaluation Agere Systems USB 2.0 UTMI USS2X1 A 8-Bit and USS2X1 WA 16-Bit PHY Chips Functional Differences Between USS2X1 A (8-Bit Interface) and the USS2X1 WA (16-Bit Interface) . The TXReady signal will drop low for one clock period each time 16 stuffed bits are accumulated . With the 8-bit interface, the TXReady signal will drop low after the accumulation of 8 stuffed bits. The 64-pin package, USS2X1 WA supports a 16-bit data interface . The operation of the 16-bit version dif fers from that of the 8-bit version as follows : . The RXValid signal will drop low for one clock period each time 16 stuffed bits are accumulated . With the 8-bit interface, the RXValid signal will drop low after the accumulation of 8 stuffed bits . . CLKOUT will run at half the rate of the equivalent 8-bit version (30 MHz). . An additional signal (ValidH) is used to identify whether the high byte of the respective 16-bit data word is valid. . Additional data pins are provided (DATA 15:8) . Agere Systems Inc . Note that the other sections of this document assume that the USS2X1A is operating with an 8-bit interface . The timings need to be adjusted appropriately for operation using a 16-bit interface . Examples of the 16-bit USS2X1 WA's operation are shown in Figure 9, Figure 10, Figure 11, and Figure 12. 17 AdLib OCR Evaluation Agere Systems USB 2 .0 UTMI USS2X1 A 8-Bit and USS2X1 WA 16-Bit PHY Chips Data Sheet, Rev. 3 October 2002 Functional Differences Between USS2X1A (8-Bit Interface) and the USS2X1WA (16-Bit Interface) (continued) HS Transmit (16-Bit) CLKOUT TXVALI D VALIDH (INPUT) DATA (INPUT) (7 :0) DATA (INPUT) (15:$) PID i I I TXREADY I I I r I i i r I I I X DATA (1) I DATA (2) I A DATA (3) r I I X DATA (4) r I I A CRC (LO) r I i I CRC (HI) r I r I , I i I I MEN=, i i r I I I I I I I I I I I I I I I I ~ ~ ~ I DP/DM A i I DATA (0) i I I i I SYNC I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I PID DATA DATA 0 DATA 1 2 ' DATA DATA 3 4 CRC LO ' CRC HI EOP ' 1315 (F) R .01 Figure 9. HS Transmit Timing for 16-Bit Data, Even Byte Count CLKOUT TXVALID VALIDH (INPUT) DATA (INPUT) (] :0) i I I DATA (INPUT) i I r I I DATA (0) (15 :8) I TXREADY DP/DM PID I I I ~ A i r I I DATA (2) ~ I ~ I I I I I I ~ I ~ I ~ I I I I I I I DATA (1) SYNC DATA (3) I X A CRC (H I) r r i , I I I I I I I I I I I I I I I I CRC (LO) I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I PID DATA 0 I DATA 1 DATA 2 DATA 3 I CRC LO CRC EOP I HI 1316 (F) R .01 Figure 10. HS Transmit Timing for 16-Bit Data, Odd Byte Count 18 Agere Systems Inc . Data Sheet, Rev. 3 October 2002 Agere Systems USB 2 .0 UTMI AdLib OCR Evaluation USS2X1A 8-Bit and USS2X1 WA 16-Bit PHY Functional Differences Between USS2X1A (8-Bit Interface) and the USS2X1WA (16-Bit Interface) (continued)) HS Receive (16-Bit) CLKOUT RXVALID I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I VALIDH (OUTPUT) I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I DATA (OUTPUT) M VVVVVVVVVVVVVVVV\/VVVVVVVV~ (7 :0) , i i r i I I I I I DATA (OUTPUT) (15 :8) ~VVVVVVVVV\/VVVVVVV1/~ i r I I I RXACTIVE I I I I I I I PID I I I I I I I X I X X r I I i I I I I I I I I I DATA (3) X r I I DATA (4) r I x i I X I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I 1 2 I DATA 3 CRC 4 LO CRC I (J(XJ(~(J(X iYYYYYYYYYYLJ1uu I I I I 0 Y JlL~1u I I I DATA I (~IXX/(XX I I DATA I CRC (HI) r I I DATA I I I I DATA I I I i I PID I I I CRC (LO) I SYNC I I I I DP/DM I I I I I I I I I I I I I i I I I I I I DATA (2) r I I I I I DATA (1) r I DATA (0) I I I I I I EOP I I I I I I HI 1317 (F) R .01 Figure 11 . HS Receive Timing for 16-Bit Data, Even Byte Count CLKOUT RXVALID I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I , i , r VALIDH (OUTPUT) DATA(OUTPUT) (7 :0) I I I I I I RXACTIVE I I I I I i I PID I I I I I I I I I X i I I DATA (2) I I I DATA (3) r X I I I I I I I I I I I I I I I I I I CRC (LO) I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I 0 DATA 1 I DATA 2 I I DATA 3 I CRC LO YYYYYYYYYYYYYYYIYYL' I I I CRC (HI) I I DATA I r I DP/DM ~SYNC~ PID I I I I DATA (1) r DATA (0) I I I I I DATA (OUTPUT) (15 :8) I I CRC I EOP I HI 1318 (F) R .01 Figure 12. HS Receive Timing for 16-Bit Data, Odd Byte Count Agere Systems Inc. 19 AdLib OCR Evaluation Agere Systems USB 2 .0 UTMI USS2X1 A 8-Bit and USS2X1 WA 16-Bit PHY Chips Data Sheet, Rev. 3 October 2002 FS Functionality CLKOUT RXACTIVE X DATAOUT(7 :0) I I DATA I I X I I DATA RXVALID i \ -4 I I I DATA i i i \ I i i DATA BYTE BOUNDARIE S 0891 (F) Figure 13. FS CLKOUT Relationship to Receive Data and Control Signals CLKOUT TXVALID DATAIN(7 :0) TXREADY X I I DATA(n) I i \ I X I DATA(n + 1) I I i i ( i \ I I X ; DATA(n + 2) I i i DATA BYTE BOUNDARIES 0892 (F) Figure 14. FS CLKOUT Relationship to Transmit Data and Control Signals Note: The receive section of the USS2X1(W)A is disabled when the transmit section is active . The USS2X1(W)A does not respond to USB traffic that is transmitting pin information . 20 Agere Systems Inc . Data Sheet, Rev. 3 October 2002 AdLib OCR Evaluation Agere Systems USB 2.0 UTMI USS2X1 A 8-Bit and USS2X1 WA 16-Bit PHY Chips Other Functions The OpMode signals are capable of inhibiting normal operation of the transceiver and evoking special test modes . These modes take effect immediately and take precedence over any pending data operations . The transmission data rate when in any OpMode depends on the state of the XcvrSelect input . There are three valid settings for OpMode : . Normal operation (0) . Nondriving (1) . Disable bit stuffing and NRZI encoding (2) olds when the FS transceiver is enabled (XcvrSelect = 1) . The following sections make a distinction between soft SEO and driven SEO . Soft SEO is the bus signaling that results from the DP and DM signal lines being pulled down exclusively by the 15 k52 pull-down resistors (Rpd) . Driven SEO is the result of generating an SEO condition by enabling the FS transmitter. In this case, the DP and DM signal lines are being pulled down by the 45 52 serial (Rs) termination resistors. Note that Rpd and Rs are defined in Figure 7.1 of the USB 2 .0 specification . Mode 0 allows the transceiver to operate with normal USB data decoding and encoding . SEO Handling Mode 1 allows the transceiver logic to support a soft disconnect feature that 3-states both the HS and FS transmitters, and removes any termination from the USB making it appear to an upstream port that the device has been disconnected from the bus. In this mode, the receive logic is still active . For full-speed operation, idle is a J state on the bus and SEO is used as part of the EOP or to indicate reset. When asserted in an EOP, SEO is never asserted on the bus for more than two low-speed bit times (1 .3 ~ts) . The assertion of SEO for more than 2.5 ~ts is interpreted as a reset by a full-speed device . Mode 2 disables the bit stuff and NRZI encoding logic, therefore, 1 s loaded from the DATA input bus become Js on the DP/DM lines and Os become Ks. Note that this mode effects the automatic SYNC pattern and EOP generation by TXValid, which is disabled so that chirps can be generated on the USB . The operation of the receiver is undefined . Note that the OpMode signals are normally changed only when the transmitter and the receiver are quiescent, i .e ., when entering a test mode or for a device initiated resume, the OPMode is set and then TXValid is asserted . In this case, the SYNC pattern and EOP are not transmitted by the USS2X1 A. The only exception is when the OPMode signals are set to mode 2 while TXValid is asserted (the transceiver is transmitting a packet), in order to flag an FS transmission error. See the Transmit Logic section for more information . In this case, the SYNC pattern has already been transmitted by the USS2X1 A. Therefore, upon the negation of TXValid, the EOP must also be transmitted to properly terminate the packet . Changing the OPMode signals under all other conditions, while the transceiver is receiving or transmitting data, will generate undefined results. Setting OpMode to 3 will also produce undefined results. The LineState signals are used for many functions . The LineState signals reflect the current state of the DP/DM signal lines . The thresholds used by the LineState to determined the state of DP/DM depend on the value of XcvrSelect. LineState uses HS thresholds when the HS termination is enabled (XcvrSelect = 0) and FS threshAgere Systems Inc . For high-speed operation, idle is an SEO state on the bus. SEO is also used to reset a high-speed device . A high-speed device cannot use the 2 .5 ~ts assertion of SEO (as defined for FS operation) to indicate reset since the bus is often in this state between packets . If no bus activity (idle) is detected for more than 3 ms, a highspeed device must determine whether the downstream port is signaling a suspend or a reset . The Suspend Detection and Reset Detection sections detail how this determination is made. If a reset is signaled, the highspeed device will then initiate the HS detection handshake protocol, as defined in the HS Detection Handshake (Chirping) section . Note that the initial assertion of SEO on the bus is referred to in the core specification and this specification as HS Reset TO (see Section 7.1 .7 .5 Reset Signaling of the USB 2.0 specification, Rev . 2) . Suspend Detection If an HS device detects SEO asserted on the bus for more than 3 ms (T1), its USS2X1 A is placed in FS mode (XcvrSelect and TermSelect = 1) . This enables the FS pull-up on the DP line, asserting a continuous FS J state on the bus. The SIE must then check the LineState signals for a J state condition . If J state condition is asserted at time T2, then the upstream port is asserting a soft SEO and the USB is in a J state indicating a suspend condition . By time T4, the device must be fully suspended . 21 AdLib OCR Evaluation Agere Systems USB 2 .0 UTMI USS2X1 A 8-Bit and USS2X1 WA 16-Bit PHY Chips Data Sheet, Rev. 3 October 2002 Other Functions (continued) TIME TO T1 T2 T3 T4 i SUSPENDN XCVR SELECT TERM SELECT DP/DM i SOFT SEO i J STATE LAST ACTIVITY I DEVICE IS SUSPENDED 1319 (F) R .01 Figure 15. Suspend Timing Behavior (HS Mode) Table 8. Suspend Timing Values (HS Mode) Timing Parameter Description HS Reset TO End of last bus activity, signaling either a reset or a suspend . The time at which the device must place itself in FS mode after bus activity stops. SIE samples LineState . If LineState = J, then the initial SEO on the bus (TO-T1) had been due to a suspend state and the SIE remains in HS mode. The earliest time where a device can issue resume signaling . The latest time that a device must actually be suspended, drawing no more than the suspend current from the bus . T1 T2 T3 T4 Value 0 (reference) HS reset TO + 3 .0 ms < T1 {TwTREV} < HS reset TO + 3 .125 ms T1 + 100 gs < T2 {TWTWRSTHS} < T1 + 875 gs HS reset TO + 5 ms {TWTRSM} HS reset TO + 10 ms {T2SUSP} Note : USB 2 .0 core specification timing values are referenced in curly braces {} . 22 Agere Systems Inc . Data Sheet, Rev. 3 October 2002 AdLib OCR Evaluation Agere Systems USB 2.0 UTMI USS2X1 A 8-Bit and USS2X1 WA 16-Bit PHY Chips Other Functions (continued) Reset Detection If a device in HS mode detects bus inactivity for more than 3 ms (T1), its USS2X1 A is placed in FS mode (XcvrSelect = 1 and TermSelect = 1). This enables the FS pull-up on the DP line to attempt to assert a continuous FS J state on the bus (dotted line in Figure 16) . The SIE must then check the LineState signals for the SEO condition . If SEO is asserted at time T2, then the upstream port is forcing the reset state to the device (i .e., driven SEO). The device will then initiate the HS detection handshake protocol . UPSTREAM PORT ACTIONS TO TIME DEVICE ACTIONS T1 XCVR SELECT i TERM SELECT i T2 i DP/DM DRIVEN SEO i, LAST ACTIVITI ~Y HS DETECTION HANDSHAKE 1321 (F) Figure 16. Reset Timing Behavior (HS Mode) Table 9. Reset Timing Values (HS Mode) Timing Parameter HS Reset TO T1 T2 Description Value Bus activity ceases, signaling either a reset or a 0 (reference) suspend . Earliest time at which the device may place HS reset TO + 3.0 ms < T1 {TWTREV} < itself in FS mode after bus activity stops. HS reset TO + 3.125 ms SIE samples LineState . If LineState = SEO, T1 + 100 gs < T2 {TWTWRSTHS} < then the SEO on the bus is due to a reset state . T1 + 875 gs The device now enters the HS detection handshake protocol . Agere Systems Inc. 23 AdLib OCR Evaluation Agere Systems USB 2 .0 UTMI USS2X1 A 8-Bit and USS2X1 WA 16-Bit PHY Chips Other Functions (continued) HS Detection Handshake (Chirping) The high-speed detection handshake process is entered from one of three states : suspend, active FS, or active HS. The downstream port asserting an SEO state on the bus initiates the HS detection handshake . Depending on the initial state, an SEO condition can be asserted from 0 to 4 ms before initiating the HS detection handshake . These states are described in Section 7.1 .7 .5 of the USB 2 .0 specification, Rev. 2 (state 3 of the reset protocol for HS capable hubs and devices) . There are three ways in which a device may enter the HS handshake detection process : 1 . If the device is suspended and it detects an SEO state on the bus, it may immediately enter the HS handshake detection process . 2. If the device is in FS mode and an SEO state is detected for more than 2 .5 ps, it may enter the HS handshake detection process . 3. If the device is in HS mode and an SEO state is detected for more than 3 .0 ms, it may enter the HS handshake detection process . In HS mode, a device must first determine whether the SEO state is signaling a suspend or a reset condition . To do this, the device reverts to FS mode by placing XcvrSelect and TermSelect into FS mode . The device must not wait more than 3 .125 ms before the reversion to FS mode. After reverting to FS mode no less than 100 ps and no more than 875 ps later, the SIE must check the LineState signals . If a J state is detected, the device will enter a suspend state . If an SEO state is detected, then the device will enter the HS handshake detection process . In each case, the assertion of the SEO state on the bus initiates the reset interval (referred to in this section as HS reset TO) . The minimum reset interval is 10 ms. Depending on the previous mode that the bus was in, the delay between the initial assertion of the SEO state (HS reset TO) and entering the HS handshake detection process (TO in Table 10, Table 11, and Table 12) can be from 0 to 4 ms. 24 Data Sheet, Rev. 3 October 2002 The USS2X1 A relies on the SI E to perform much of the event timing, and the SIE requires a stable CLKOUT signal to perform accurate timing . In cases 2 and 3 above, CLKOUT has been running and is stable ; however in case 1, the USS2X1A is reset from a suspend state, and the internal oscillator and clocks of the transceiver are powered down . A device has up to 6 ms after the release of SuspendN (HS reset TO) to assert a minimum of a 1 ms Chirp K. The Clock Control and PLL section describes the behavior of the USS2X1 A which allows it to reliably generate a 1 ms Chirp K . FS Downstream Facing Port The following is an example of the USS2X1 A behavior when the downstream facing port that it is attached to does not support HS operation (a USB 1 .X host/hub) . Upon entering the HS detection process (TO), XcvrSelect and TermSelect are in FS mode. The D+ pull-up is asserted and the HS terminations are disabled . The SIE then sets OpMode to disable bit stuffing and NRZI encoding, and begins the transmission of all Os data, which asserts a HS K (chirp) on the bus (T1) . The device chirp must last at least 1 .0 ms and must end no later than 7 .0 ms after HS reset T0. At time T1, the SIE sets XcvrSelect to HS mode and begins listening for a chirp sequence from the downstream port. If the downstream port is not HS capable, then the HS K asserted by the device is ignored and the alternating sequence of HS chirp Ks and Js is not generated . If the downstream chirps are not detected (T4), the device will enter FS mode by returning XcvrSelect to FS mode. Agere Systems Inc . AdLib OCR Evaluation Agere Systems USB 2.0 UTMI Data Sheet, Rev. 3 October 2002 USS2X1 A 8-Bit and USS2X1 WA 16-Bit PHY Chips Other Functions (continued) UPSTREAM PORT ACTIONS TO DEVICE ACTIONS i T3 T1 T2 i TIME T4 T5 i XCVR SELECT TERM SELECT TXVALID DP/DM i F 'DEVICE' I CHIRP K UPSTREAM I~ ~~ PORT CHIRP T~'I ~SOF SEO NO DOWNSTREAM PORT CHIRPS . FS MODE 'I 1323 (F) Figure 17. HS Detection Handshake Timing Behavior (FS Mode) Table 10. HS Detection Handshake Timing Values (FS Mode) Timing Parameter Description TO* HS handshake begins . D+ pull-up enabled, HS terminations disabled . Device enables HS transceiver and asserts chirp K on the bus. Device removes chirp K from the bus (1 ms minimum width) . Earliest time when downstream port may assert chirp K on the bus . Downstream port chirp not detected by the device . Device reverts to FS default state and waits for end of reset . Earliest time at which downstream port may end reset . T1 T T2 T3 T4 T5 Value 0 (reference) TO < T1 < HS reset TO + 6 .0 ms T1 + 1 .0 ms {TuCH} < T2 < HS reset TO + 7 .0 ms {TUCHEND} T2 < T3 < T2+100 gs {TWTDCH} T2 + 1 .0 ms < T4 {TWTFS} < T2 + 2 .5 ms HS reset TO + 10 ms {TDRST (Min)} * TO may occur to 4 ms after HS reset T0 . t The SIE must assert the chirp K for 66000 CLKOUT cycles to ensure a 1 ms minimum duration . Agere Systems Inc. 25 AdLib OCR Evaluation Agere Systems USB 2 .0 UTMI USS2X1 A 8-Bit and USS2X1 WA 16-Bit PHY Chips Data Sheet, Rev. 3 October 2002 Other Functions (continued) HS Downstream Facing Port The following is an example of the USS2X1 A behavior when the downstream facing port that it is attached to supports HS operation (a USB 2.0 host/hub) . Upon entering the HS detection process (TO), XcvrSelect and TermSelect are in FS mode. The D+ pull-up is asserted, and the HS terminations are disabled . The SIE then sets OpMode to disable bit stuffing and NRZI encoding, and begins the transmission of all Os data, which asserts a HS K (chirp) on the bus (T1) .The device chirp must last at least 1 .0 ms, and must end no later than 7.0 ms after HS reset T0 . At time T1, the SI E sets XcvrSelect to HS mode and begins listening for a chirp sequence from the downstream port. If the downstream port is HS capable, then it will begin generating an alternating sequence of chirp Ks and chirp Js (T3) after the termination of the chirp from the device (T2) . After the device sees the valid downstream port chirp sequence chirp K-J-K-J-K-J (T6), it will enter HS mode by setting TermSelect to HS mode (T7) . Figure 18 provides a state diagram for chirp K-J-K-J-K-J validation . Prior to the end of reset (T9), the upstream port must terminate the sequence of chirp Ks and chirp Js (T8) and assert SEO (T8-T9) . Note that the sequence of chirp Ks and chirp Js constitutes bus activity. IK STATE START CHIRP CHIRP COUNT )4 K-J- CHI J =0 DETECTION DETECT K? IJ STATE DETECT J? K STATE INC CHIRP COUNT /" SEO CHIRP COUNT! = 6 & !SEO - J STATE CHIRP INVALID CHIRP COUNT =6 INC CHIRP COUNT CHIRP VALID CHIRP COUNT! = 6 & !SEO 1325 (F) Figure 18. Chirp K-J-K-J-K-J Sequence Detection State Diagram The SIE must use LineState signal transitions to step through the chirp K-J-K-J-K-J state diagram, where K state is equivalent to LineState = K state and J state is equivalent to LineState = J state . The SIE must employ a counter (chirp count) to count the number of chirp K and chirp J states . Note that LineState does not filter the bus signals, so the requirement that a bus state must be continuously asserted for 2 .5 gs must be verified by the SIE sampling the LineState signals . 26 Agere Systems Inc . AdLib OCR Evaluation Agere Systems USB 2.0 UTMI Data Sheet, Rev. 3 October 2002 USS2X1 A 8-Bit and USS2X1 WA 16-Bit PHY Chips Other Functions (continued) UPSTREAM PORT ACTIONS TO T3 T4 T5 DEVICE ACTIONS XCVR SELECT T1 T21 I I T6 T7 T8 TIME T9 i i i TERM SELECT TXVALID /I DP/DM UPSTREAM PORT CHIRP I I i 1\i i ; 'DEVICE' CHIRP K ~'K'J'K J K J~ i~----A= M --! ------------ AMM I DOWNSTREAM PORT CHIRPS HS MODE 1326 (F) Figure 19. HS Detection Handshake Timing Behavior (HS Mode) Table 11 . Reset Timing Values Timing Parameter TO* T1 T T2 T3 T4 T5 T6 T7 T8 T9 Description HS handshake begins . D+ pull-up enabled, HS terminations disabled . Device asserts chirp K on the bus . Device removes chirp K from the bus (1 ms minimum width) . Downstream port asserts chirp K on the bus . Downstream port toggles chirp K to chirp J on the bus. Downstream port toggles chirp J to chirp K on the bus. Device detects downstream port chirp . Downstream port chirp detected by the device . Device removes D+ pull-up and asserts HS terminations, reverts to HS default state, and waits for end of reset . Terminate downstream port chirp K-J sequence (repeating T4 and T5) . The earliest time at which a downstream port may end reset . The latest time at which the device may remove the D+ pull-up, assert the HS terminations and revert to the HS default state . Value 0 (reference) TO < T1 < HS reset TO + 6 .0 ms {TUCHEND - TuCH} TO + 1 .0 ms {TUCH} < T2 < HS reset TO + 7 .0 ms {TUCHEND} T2 < T3 < T2 + 100 ~ts {TWTDCH} T3 + 40 ~ts {TDCHBIT (min)} < T4 < T3 + 60 ~ts {TDCHBIT (max)} T4 + 40 gs {TDCHBIT (min)} < T5 < T4 + 60 gs {TDCHBIT (max)} T6 T6 < T7 < T6 + 500 gs {TWTHS} T9 - 500 gs {TDCHSEO (max)} < T8 < T9 100 gs {TDCHSEO (min)} HS reset TO + 10 ms {TDRST (min)} * TO may be up to 4 ms after HS reset T0 . t Due to the assertion of the HS termination on the downstream port and FS termination on the upstream port, between T1 and T7 the signaling levels on the bus are higher than HS signaling levels and are less than FS signaling levels . $ The SIE must use LineState to detect the downstream port chirp sequence . Agere Systems Inc. 27 AdLib OCR Evaluation Agere Systems USB 2 .0 UTMI USS2X1 A 8-Bit and USS2X1 WA 16-Bit PHY Chips Other Functions (continued) Suspend Timing If reset is entered from a suspended state, the internal oscillator and clocks of the transceiver have already been powered down . Figure 20 shows how CLKOUT is used to control the duration of the chirp generated by the device . When reset is entered from a suspended state (J to SEO transition reported by LineState), SuspendN is combinatorially negated at time TO by the SIE. The USS2X1 A oscillator and PLL take several milliseconds to stabilize. The USS2X1 A will not generate any transitions of the CLKOUT signal until it is usable, where usable is defined as stable to within 10% of the nominal frequency and the duty cycle accuracy 50 5%. After CLKOUT is usable, the SIE must initialize a timer (T1) and look for SEO to be asserted for at least 2 .5 gs. If the test is true (T1 >_ Tfiltse0), then start the reset handshake protocol . UPSTREAM PORT ACTIONS TO DEVICE ACTIONS If the test is false, the latest time that could successfully start the chirp sequence was exceeded and the SIE never saw SEO for at least 2.5 gs (TO >_ Tuchend Tuch & T1 < Tfiltse0) . Then the SIE must return to the suspend state and assert SuspendN . The first transition of CLKOUT occurs at T1 . The SIE must assert a chirp K for 66000 CLKOUT cycles to ensure a 1 ms minimum duration . If CLKOUT is 10% fast (66 MHz), then chirp K will be 1 .0 ms . If CLKOUT is 10% slow (54 MHz), then chirp K will be 1 .2 ms. The 5.8 ms requirement for the first CLKOUT transition after SuspendN ensures enough time to assert a 1 ms chirp K and still complete before T3. Once the chirp K is completed (T3), the SIE can begin looking for downstream chirps and use CLKOUT to time the process . To detect the assertion of the downstream chirp Ks and chirp Js for 2.5 gs {TFILT}, the SIE must see the appropriate LineState signals asserted continuously for 165 CLKOUT cycles. TIME i i Data Sheet, Rev. 3 October 2002 I I I I T1 T2 I T3 I T4 I XCVR SELECT i SUSPENDN TXVALID CLKOUT i i DEVICE ASSERTED DP/DM i SEO K CLOCK POWERUP TIME UPSTREAM PORT CHIRP SEO I LOOK FOR DOWNSTREAM CHIRPS 1327 (F) R .01 Figure 20. HS Detection Handshake Timing Behavior from Suspend 28 Agere Systems Inc . Data Sheet, Rev. 3 October 2002 AdLib OCR Evaluation Agere Systems USB 2.0 UTMI USS2X1 A 8-Bit and USS2X1 WA 16-Bit PHY Chips Other Functions (continued) Table 12 . HS Detection Handshake Timing Values from Suspend Timing Parameter TO T1 T2 T3 T4 Description Value While in suspend state an SEO is detected on the USB . HS handshake begins . D+ pull-up enabled, HS terminations disabled, SuspendN negated . First transition of CLKOUT CLKOUT usable (frequency accurate to 10%, duty cycle accurate to 50 5%) . Device asserts chirp K on the bus . Device removes chirp K from the bus (1 ms minimum width) and begins looking for downstream chirps . CLKOUT nominal (CLKOUT is frequency accurate to 500 ppm, duty cycle accurate to 50 1 %). 0 (HS reset TO) TO < T1 < TO + 5.6 ms T1 < T2 < TO + 5 .8 ms T2 + 1 .0 ms {TuCH} < T3 < TO + 7 .0 ms {TUCHEND} T1 < T3 < TO + 20 .0 ms TDRST (Min) + TRSMRCV} Assertion of Resume In this case, an event internal to the device initiates the resume process . A device with remote wake-up capability must wait for at least 5 ms after the bus is in the idle state before sending the remote wake-up resume signaling . This allows the hubs to get into their suspend state and prepare for propagating resume signaling . The device has 10 ms where it can draw a nonsuspend current before it must drive resume signaling . At the beginning of this period, the SIE may negate SuspendN, allowing the transceiver, oscillator, and PLL to power up and stabilize . Figure 21 illustrates the behavior of a device returning to HS mode after being suspended . At T4, a device that was previously in FS mode would maintain TermSelect and XcvrSelect high. To generate resume signaling (FS K), the USS2X1A is placed in the disable bit stuffing and NRZI encoding operational mode, TermSelect and XcvrSelect must be in FS mode, TXValid asserted, and all Os data is presented on the DATA input bus for at least 1 ms (T1-T2) . UPSTREAM PORT ACTIONS DEVICE ACTIONS SUSPENDN I I I TO T1 T2 TIME i T3 I i i I T4 XCVR SELECT & TERM SELECT TXVALID DP/DM FS IDLE (J) K STATE FS MODE SEO MODEi 1328 (F) Figure 21 . Resume Timing Behavior (HS Mode) Agere Systems Inc. 29 AdLib OCR Evaluation Agere Systems USB 2 .0 UTMI USS2X1 A 8-Bit and USS2X1 WA 16-Bit PHY Chips Data Sheet, Rev. 3 October 2002 Other Functions (continued) Table 13. Suspend Timing Values (HS Mode) Timing Parameter Description TO T1 Internal device event initiating the resume process . Device asserts FS K on the bus to signal resume request to downstream port. The device releases FS K on the bus; however, by this time the K state is held by downstream port. Downstream port asserts SEO. Latest time at which a device, which was previously in HS mode, must restore HS mode after bus activity stops . T2 T3 T4 Detection of Resume Resume signaling always takes place in FS mode (TermSelect and XcvrSelect = FS enabled), so the behavior for an HS device is identical to that of an FS device . The SIE uses the LineState signals to determine when the USB transitions from the J to the K state and finally to the terminating low-speed EOP (SEO for 1 .25 ~ts-1 .5 ~ts) . The resume signaling (FS K) will be asserted for at least 20 ms. At the beginning of this period, the SIE may negate SuspendN, allowing the transceiver, oscillator, and PLL to powerup and stabilize . The low-speed EOP condition is relatively short. SIEs that simply look for an SEO condition to exit suspend mode do not necessarily give the USS2X1 A's clock generator enough time to stabilize . It is recommended that all SIE implementations key off the J-to-K transition for exiting suspend mode (SuspendN = 1) . And within 1 .25 ~ts after the transition to the SEO state (low-speed EOP), the SIE must enable normal operation, i .e., enter HS or FS mode depending on the mode the device was in when it was suspended . If the device was in FS mode, then the SIE leaves the FS terminations enabled . After the SEO expires, the downstream port will assert a J state for one low-speed bit time, and the bus will enter an FS idle state (maintained by the FS terminations) . If the device was in HS mode, then the SIE must switch to the FS terminations before the SEO expires (<1 .25 ~ts) . Value 0 (reference) TO < T1 < TO + 10 ms {TDRSMDN} T1 + 1 .0 ms {TDRSMUP (min)} < T2 < T1 + 15 ms {TDRSMUP (max)} T1 + 20 ms {TDRSMDN} T3 + 1 .33 gs {two low-speed bit times} Note : Glitches that occur on the USB during suspend are handled as follows . When a device is suspended, a J state is on the bus and the SIE should be looking for a K (resume) or an SEO (reset) . In either case, a glitch that looks like a K or an SEO will cause the USS2X1 A oscillator to start up. The USS2X1 A will hold off any CLKOUT transitions until CLKOUT is usable . Once CLKOUT is running (several milliseconds later), the SIE must check LineState . If a J state is asserted, then the SIE returns to the suspend state ; if a K state is asserted, then the SIE starts the resume process ; and if SEO is asserted, then the SIE starts the reset process . HS Device Attach Figure 22 demonstrates the timing of the USS2X1 A control signals during a device attach event. When an HS device is attached to an upstream port, power is asserted to the device and the device sets XcvrSelect and TermSelect to FS mode (time T1) . VBUS is the 5 V power available on the USB . Device reset in Figure 22 indicates that VBUS is within normal operational range as defined in the USB 2.0 specification. The assertion of device reset (TO) will initialize the device and cause the SIE state machine to set the XcvrSelect and TermSelect signals to FS mode (T1). Note that device reset is not the same as the USS2X1 A reset signal . Device reset is an input to the SIE, which in turn can use it to assert reset to the USS2X1 A. After the SEO expires, the bus will then enter an HS idle state (maintained by the HS terminations) . 30 Agere Systems Inc . Data Sheet, Rev. 3 October 2002 AdLib OCR Evaluation Agere Systems USB 2.0 UTMI USS2X1 A 8-Bit and USS2X1 WA 16-Bit PHY Chips Other Functions (continued) The standard FS technique of using a pull-up on DP to signal the attach of an FS device is employed . The SIE must then check the LineState signals for SEO . If LineState = SEO is asserted at time T2, then the upstream port is forcing the reset state to the device (i.e., driven SEO) . The device will then reset itself before initiating the HS detection handshake protocol . UPSTREAM PORT ACTIONS TO DEVICE ACTIONS i i T1 VBUS i i DEVICE RESET XCVR SELECT TERM SELECT DP/DM T2 TIME i i i i i i i i in N IDLE (FS J) SEO HS DETECTION HANDSHAKE) 1329 (F) Figure 22. Device Attach Behavior Table 14. Attach and Reset Timing Values Timing Parameter TO T1 T2 (HS Reset TO) Description Vbus valid . Maximum time from Vbus valid to when the device must signal attach . Debounce interval . The device now enters the HS detection handshake protocol . Value 0 (reference) TO + 100 ms {TSIGATT} < T1 T1 + 100 ms {TATTDB} < T2 5-3080 .R07 (F) Agere Systems Inc. 31 AdLib OCR Evaluation Agere Systems USB 2 .0 UTMI USS2X1 A 8-Bit and USS2X1 WA 16-Bit PHY Chips Data Sheet, Rev. 3 October 2002 Other Functions (continued) USB 2.0 Test Mode Generation The USB specification defines additional test modes. These are accomplished with the following techniques : . To force an SEO state on the bus, the USS2X1A is placed in OpMode 0 (normal operation) and no data is transmitted . This results in an HS idle mode on the bus, which is SEO . It is the responsibility of the SIE to validate any incoming packets and to transmit a NAK handshake packet, if the received packet is correct . . To force a J state on the bus, the USS2X1A is placed in OpMode 2 (disable bit stuffing and NRZI encoding) and all 1s are transmitted by the SIE . . To force a K state on the bus, the USS2X1A is placed in OpMode 2 (disable bit stuffing and NRZI encoding) and all Os are transmitted by the SIE . . To generate a test packet on the bus, the USS2X1 A is placed in OpMode 0 (normal operation) and all the test packet data (as defined in Chapter 7 of the USB 2 .0 specification) is transmitted by the SIE. Table 15. USB 2 .0 Test Mode to USS2X1A Mapping USB 2.0 Test Modes SEO NAK J K Test-Packet USS2X1A Setup I Operational Mode Transmitted Data XcvrSelect & TermSelect Normal Disable Disable Normal No transmit All 1 s All Os Test packet data HS HS HS HS I I Note : The Test Force-Enable mode described in the USB 2 .0 specification does not apply to upstream facing ports . 32 Agere Systems Inc . Agere Systems USB 2 .0 UTMI AdLib OCR Evaluation USS2X1A 8-Bit and USS2X1 WA 16-Bit PHY Data Sheet, Rev. October 2002 Electrical Characteristics do Characteristics Table 16. do Characteristics Parameter Symbol Condition Min Max Unit 3.135 TO 3 .3 Supply Power Voltage Input High Threshold Input Low Threshold Output High Voltage Output Low Voltage Input Pin Capacitance Bidi Pin Capacitance Output Pin Capacitance Total Power Active Total Power Suspend VDD - 3.465 V Vih - 2 .0 - - V Vil - - - 0 .8 V Voh i<_ -6mA 2 .4 - - V Vol i<_ 6mA - - 0 .4 V Cin - - - 2 .0 pF Cbid - - - 3 .0 pF Cout - - - 2 .5 pF PtotA VDD = 3 .3 V, 25 C VDD = 3 .3 V, 25C - - 445 mW - - 10 mW PtotB ac Characteristics Table 17. ac Characteristics Signal Symbol All All Data Others Data Others Tri Tfi Tro Tro Tfo Tfo Agere Systems Inc. Condition Min 0 .2VDD-0 .6VDD 0 .6VDD-0 .2VDD 0 .2VDD-0 .6VDD, 0 .2VDD-0 .6VDD, 0 .2VDD-0 .6VDD, I 0 .6VDD-0 .2VDD, - 10 10 10 10 pF pF pF pF I I TO 0 .8 0 .8 - I Max Unit 0.8 0.6 0.8 0.6 ns ns ns ns ns ns I Notes Input rise time. Input fall time. Output rise time. Output rise time. Output fall time. I Output fall time. 33 AdLib OCR Evaluation Agere Systems USB 2 .0 UTMI USS2X1 A 8-Bit and USS2X1 WA 16-Bit PHY Chips Data Sheet, Rev. 3 October 2002 Electrical Characteristics (continued) ac Timing (continued) Table 18. ac Timing (8-Bit) Symbol Tsu Thd Tpd 34 Signal DATA[15 :0] TXVALID VALIDH OPMODE[1] OPMODE[0] XCVRSELECT TERMSELECT SUSPENDN DATA[15 :0] TXVALID VALIDH OPMODE[1] OPMODE[0] XCVRSELECT TERMSELECT SUSPENDN DATA[15 :0] RXVALID VALIDH RXERROR RXACTIVE LINESTATE[1 :0] TXREADY Condition Min 3.135 V, 125 C 8 10 NA 10 11 TBD TBD TBD 0 0 NA 0 0 0 0 TBD 0 0 NA 0 0 0 0 3.465 V, 125 C 10 pF Min : 3.135 V, 12 5 OC I Max: 3.465 V, 0 0C I I TO - I Max Unit 4 3 NA 5 3 6 11 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns I Notes Setup from signal to CLKOUT. Hold from signal to CLKOUT. Prop delay from CLKOUT to signal . Agere Systems Inc . Data Sheet, Rev. 3 October 2002 AdLib OCR Evaluation Agere Systems USB 2.0 UTMI USS2X1 A 8-Bit and USS2X1 WA 16-Bit PHY Chips Electrical Characteristics (continued) ac Timing Table 19. ac Timing (16-Bit) Symbol Tsu Thd Tpd Signal DATA[15 :0] TXVALID VALIDH OPMODE[1] OPMODE[0] XCVRSELECT TERMSELECT SUSPENDN DATA[15 :0] TXVALID VALIDH OPMODE[1] OPMODE[0] XCVRSELECT TERMSELECT SUSPENDN DATA[15 :0] RXVALID VALIDH RXERROR RXACTIVE LINESTATE[1 :0] TXREADY Agere Systems Inc. Condition Min 3.135 V, 125 C 8 10 10 10 11 TBD TBD TBD 0 0 0 0 0 0 0 TBD 0 0 0 0 0 0 3.465 V, 125 C 10 pF Min : 3.135 V, 125 O C I Max: 3.465 V, 0 0C I 0 I TO - - I Max Unit 21 20 21 5 18 33 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 27 I Notes Setup from signal to CLKOUT. Hold from signal to CLKOUT. Prop delay from CLKOUT to signal . ns 35 Agere Systems USB 2 .0 UTMI AdLib OCR Evaluation USS2X1A 8-Bit and USS2X1 WA 16-Bit PHY Data Sheet, Rev. 3 October 2002 Electrical Characteristics (continued) Timing Constraints The following figure and Tables 20 and 21 define the timing constraints for the USS2X1 A (8-bit) and USS2X1 WA (16-bit) devices . CLK CONTROL If DATAI N CONTROL Ol DATAOUT Notes : Tcsu = control signal setup time . Tosu = data signal setup time . TCH = control signal hold time . TDH = data signal hold time . Tcco = control signal clock to out time . Toco = data signal clock to out time . Figure 23. Timing Constraints Table 20. Timing Constraints for USS2X1A (8-Bit) and USS2X1 WA (16-Bit) for Control Out Signals Control -Out Signals RXActive RXValid RXError RXVaIidH TXReady LineState DataOut Agere Systems Inc. Tcco (8-bit Implementation) Max Min 3 3 5 NA TBD 6 0 0 0 NA 0 0 Tdco (8-bit Implementation) Tcco (16-bit Implementation) Max Min 18 18 5 19 TBD 6 0 0 0 0 0 0 Tdco (16-bit Implementation) Max Min Max Min 4 0 19 0 Unit ns ns ns ns ns ns ns 36 Data Sheet, Rev. 3 October 2002 AdLib OCR Evaluation Agere Systems USB 2.0 UTMI USS2X1 A 8-Bit and USS2X1 WA 16-Bit PHY Chips Electrical Characteristics (continued) Timing Constraints (continued) Table 21 . Timing Constraints for USS2X1A (8-Bit) and USS2X1 WA (16-Bit) for Control_In Signals Control-In Si g n a l s TXValid TXVaIidH OpMode[1 ] OpMode[0] XCVRSELECT TERMSELECT Dataln Agere Systems Inc. Setup and Hold (8-bit Implementation) Setup and Hold (16-bit Implementation) Unit Tcsu (Max) Tch (Min) Tcsu (Max) Tch (Min) 10 NA 10 11 TBD TBD 0 NA 0 0 0 0 10 10 10 11 TBD TBD 0 0 0 0 0 0 ns ns ns ns ns ns 8 0 8 0 ns 37 AdLib OCR Evaluation Agere Systems USB 2 .0 UTMI USS2X1 A 8-Bit and USS2X1 WA 16-Bit PHY Chips Data Sheet, Rev. 3 October 2002 Outline Diagrams 48-Pin TQFP Dimensions are in millimeters . 9.00 0.20 7.00 0.20 1 .00 REF PIN #1 r IDENTIFIER ZONE 7 4$ 0.25 1 i I I GAGE PLANE 36 ---I 1~ SEATING PLANE I L0.45/0.7 7.00 0.20 DETAIL A 9.00 0 .20 25 2 13 LJ LJ LJ LJ LJ LJ LJ LJ LJ LJ LJ 24 DETAIL A DETAIL B 0.106/0 .20 0.19/0.274 1 .40 0.05 0.08 O 1 .60 MAX DETAIL B SEATING PLANE 0.50 TYP ~ 0.05/0.15 p 0.08 5-2363 .R08 (F) 38 Agere Systems Inc . Data Sheet, Rev. 3 October 2002 Outline Diagrams AdLib OCR Evaluation Agere Systems USB 2.0 UTMI USS2X1 A 8-Bit and USS2X1 WA 16-Bit PHY Chips (continued) 64-Pin TQFP Dimensions are in millimeters . 12 .00 0 .20 1 .00 REF 10 .00+0 .20 PIN #1 IDENTIFIER ZONE 64 49 0.25 GAGE PLANE 48 1 SEATING PLANE 0.45/0.75 DETAIL A 10 .00 +0 .20 12 .00 0 .20 16 0 33 17 DETAIL A 0.106/0 .200 32 0.1 9/0.27 DETAIL B 1 .40+0 .05 ' 0.08 O T 1 .60 MAX DETAIL B SEATING PLANE 0 .50 TYP-J IL p 0 .08 0.05/0.15 5-3080 .R07 (F) Ordering Information Device Code USS2X1 A USS2X1 WA USS2X1 A Evaluation Kit USS2X1 WA Evaluation Kit I Agere Systems Inc. Package 48-Pin 64-Pin 48-Pin 64-Pin TQFP TQFP TQFP TQFP Comcode I 109058537 109058545 7000259930 7000260350 39 AdLib OCR Evaluation The USB-IF logo is a trademark of the Universal Serial Bus Implementers Forum, Inc . Intel is a registered trademark of Intel Corporation . For additional information, contact your Agere Systems Account Manager or the following: INTERNET: http ://www.agere.com E-MAIL: docmaster@agere.com N . AMERICA: Agere Systems Inc., Lehigh Valley Central Campus, Room 10A-301C, 1110 American Parkway NE, Allentown, PA 18109-9138 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA : Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/17, Tower 2, The Gateway, Harbour City, Kowloon Tel. (852) 3129-2000, FAX (852) 3129-2020 CHINA: (86) 21-5047-1212 (Shanghai), (86) 755-25881122 (Shenzhen) JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 6778-8833, TAIWAN : (886) 2-2725-5858 (Taipei) EUROPE : Tel. (44) 1344 296 400 Agere Systems Inc . reserves the right to make changes to the product(s) or information contained herein without notice . No liability is assumed as a result of their use or application . Agere, Agere Systems, and the Agere logo are trademarks of Agere Systems Inc. Copyright (R) 2002 Agere Systems Inc . All Rights Reserved October 2002 DS02-273CMPR-3 (Replaces DS02-273CMPR-2) systems a ' ere 8