L-7000260350 - Agere Systems, Inc.

a8e

re

systems

Agere

Systems

USB

2

.0

UTMI

USS2X1

A

8-Bit

and

USS2X1

WA

16-Bit

PHY

Chips

Data

Sheet,

Rev

.

3

October

2002

=~ff

Introduction

The

USS2X1(W)A

PHY

chip

provides

a

serial

electri-

cal

interface

that

is

compliant

with

the

USB

specifica-

tion

revision

2

.0

.

The

chip

contains

sufficient

capabilities

to

allow

it

to

function

as

a

USB

2

.0

device

when

coupled

to

an

intelligent

application

through

its

8-/16-bit interface

.

Features

.

UTMI/USB

2

.0

compliant

.

Operates

in

both

USB

2

.0

high-speed

(HS)

(480

Mbits/s)

and

USB

1

.1

full-speed

(FS)

(12

Mbits/s)

modes

.

Performs

serial-to-parallel

and

parallel-to-serial

con-

versions

.

All

required

terminations,

including

1

.5

kn

pull-up

on

DP, are

internal

to

chip

.

Detects

SYNC

field

and

EOP

on

receive

packets

.

Generates

SYNC

field

and

EOP

on

transmit

pack-

ets

.

Recovers

data

and

clock

recovery

from

the

USB

serial

stream

.

Performs

bit

stuffing/unstuffing

;

bit

stuff

error

detec-

tion

.

Staging

register

manages

data

rate

variation

due

to

bit

stuffing/unstuffing

.

8-bit,

60

MHz

(16-bit,

30

MHz)

parallel

interface

.

Ability

to

switch

between

full-speed

and

high-speed

terminations

and

signaling

.

30

MHz

external

crystal,

plus

internal

oscillator

and

PILL

used

to

generate

higher-speed

internal

clocks

and

CLKOUT

output

.

Supports

detection

of

USB

reset,

suspend,

and

resume

.

Supports

high-speed

identification

and

detection

as

defined

by

USB

2

.0

specification

.

Supports

transmission

of

resume

signaling

.

Supports

test

modes

defined

by

USB

2

.0

specifica-

tion

.

Available

in

two

packages

:

USS2X1

A

48-pin

TQFP

(8-bit)

and

USS2X1

WA

64-pin

TQFP

(16-bit)

.

Description

The

USS2X1(W)A

PHY

chip

may

be used

in

conjunc-

tion

with

an

ASIC

to

provide

a

two-chip

solution

for

a

USB

2

.0

device

.

The

chip

may

also

be used

in

con-

junction with

FPGAs

to

prototype

a

USB

2

.0

device

.

The

chip

uses a

8-/16-bit

parallel

interface

that

is

com-

pliant

with

the

Intel®USB

2

.0

Transceiver

Macrocell

Interface Specification

(UTMI)

.

In

the

transmit

direction

(to

the

host),

the

chip per-

forms

parallel-to-serial

conversion,

plus

the

required

bit

stuffing

and

NRZI

encoding

.

It

also

generates

the

required

SYNC

and

EOP

fields

for

outgoing

packets

.

In

the

receive

direction

(from

the

host),

the

chip

per-

forms

serial-to-parallel

conversion,

plus

the

required

bit

unstuffing

and

NRZI

decoding

.

It

also

detects

and

strips

the

SYNC

and

EOP

fields

from incoming

pack-

ets

.

The

receive

logic

also

detects

bit

stuff

error

(FS

mode

only),

elasticity

buffer

underrun

or

overrun

(HS

mode

only),

and

byte-alignment

errors

(either

mode)

.

All

device

terminations

required

by

the

USB

2

.0

speci-

fication

are

contained

inside

the

USS2X1(W)A

.

This

includes

the

DP/DM

45

S2

termination

to

ground

in

HS

mode,

the

DP/DM

45

S2

series

termination

in

FS

mode,

and

the

1

.5

kn

pull-up resistor

on

DP

when

in

FS

mode

.

The

chip also

includes

appropriate

control

for

the

1

.5

kn

DP

pull-up,

which

is

needed

when

switching

between

FS

and

HS

modes

.

The

USS2X1(W)A

supports

the

high-speed

detection

sequence

defined

in

the

USB

2

.0

specification,

which

is

performed

after

USB

reset

to

determine

the

highest-

speed

capability

of

the

upstream

and

downstream

entities

.

The

USS2X1(W)A

has

the

ability

to

transmit

a

Chirp

K

and

detect

a

Chirp

K/Chirp

J pattern,

as

required

by

the

high-speed

detection

sequence

.

The

USS2X1(W)A

supports

test

modes

defined

in

the

USB

2

.0

specification

that

are

appropriate

for

upstream-facing

ports

:

Test

SEO

NAK,

Test

J,

Test

K,

and

Test

Packet

.

The

USB

2

.0

specification

requirements

for

current

draw

in

suspend

mode

can

be met

by

asserting

the

SUSPENDN

input

.

This

turns

off

internal

clocks

and

the

CLKOUT

output,

and

places

the

internal

ana-

log

components

into

low-power

mode

.

When

the

SUS-

PENDN

input

is

deasserted,

the

USS2X1(W)A

turns

on

internal

clocks,

begins

asserting

the

CLKOUT

out-

put

after

internal

clocks

have

stabilized,

and

returns

the

internal

analog

components

to

their

operational

state

.

AdLib OCR Evaluation

Agere

Systems

USB

2

.0

UTMI

USS2X1

A

8-Bit

and

USS2X1

WA

16-Bit

PHY

Chips

Data

Sheet,

Rev

.

3

October

2002

Table

of

Contents

Page

.

.4

.

.5

.

.5

.

.5

.

.5

.

.5

.

.5

.

.5

.

.5

. .

6

.

.7

.

.7

.

.7

.

.8

. .

9

. .

9

10

11

12

13

14

17

18

19

20

21

23

24

26

28

29

30

32

33

35

36

38

39

2

Agere

Systems

Inc

.

AdLib OCR Evaluation

Data

Sheet,

Rev

.

3

Agere

Systems

USB

2

.0

UTMI

October

2002

USS2X1

A

8-Bit

and

USS2X1

WA

16-Bit

PHY

Table

of

Contents

(continued)

Figure

Page

Figure

1

.

USB

2

.0

USS2X1

A

8-Bit

and

USS2X1

WA

16-Bit

PHY

Chips

. .

.

...........................

.

............

.

......................

.4

Figure

2

.

48-Pin

TQFP

Package

Assignments

.....................

.

............

.

...........................

.

............

.

............

.

.........

.7

Figure

3

.

64-Pin

TQFP

Package

Assignments

.....................

.

............

.

...........................

.

............

.

............

.

.........

.8

Figure

4

.

HS

Transmit

Timing

for

a Data Packet

(8-Bit)

.......................................

.

............

.

...................................

.13

Figure

5

.

HS

Receive Timing

for

Data

with

Unstuffing

Bits

(8-Bit)

.......................

.

............

.

...........................

.

.......

.14

Figure

6

.

HS

Receive Timing

for

Data Packet

(with

CRC-16)

(8-Bit)

................................

.

............

.

......................

.15

Figure

7

.

HS

Receive Timing

for

Setup Packet

(8-bit)

.

........................................

.

............

.

.................. .........

.

.......

.16

Figure

8

.

HS

Receive Timing

for

a

Handshake

Packet (No

CRC)

(8-bit)

.............

.

............

.

................................ ...

.16

Figure

9

.

HS

Transmit

Timing

for

16-Bit

Data,

Even

Byte

Count

............

.

............

.

...........................

.

............

.

.......

.18

Figure

10

.

HS

Transmit

Timing

for

16-Bit

Data,

Odd

Byte

Count

.........................

.

............

.

............

.

..............

.

.......

.18

Figure

11

.

HS

Receive

Timing

for

16-Bit

Data,

Even

Byte

Count

........................

.

............

.

............

.

..............

.

.......

.19

Figure

12

.

HS

Receive

Timing

for

16-Bit

Data,

Odd

Byte

Count

.

............

.

............

.

...........................

.

....................

.19

Figure

13

.

FS

CLKOUT

Relationship

to

Receive Data

and

Control

Signals

.......................

.

............

.

....................

.20

Figure

14

.

FS

CLKOUT

Relationship

to

Transmit

Data

and

Control

Signals

.........

.

............

.

.................................

.20

Figure

15

.

Suspend

Timing

Behavior

(HS

Mode)

.......................

.

............

.

...........................

.

............

.

............

.

.......

.22

Figure

16

.

Reset

Timing

Behavior

(HS

Mode)

.

.....................................................

.

............

.

...........................

.

.......

.23

Figure

17

.

HS

Detection

Handshake

Timing

Behavior

(FS

Mode)

..........

.

............

.

...........................

.

............

.

.......

.25

Figure

18

.

Chirp

K-J-K-J-K-J

Sequence

Detection

State

Diagram

..........

.

...........................

.

............

.

............

.

.......

.26

Figure

19

.

HS

Detection

Handshake

Timing

Behavior

(HS

Mode)

..........

.

............

.

...........................

.

............

.

.......

.27

Figure

20

.

HS

Detection

Handshake

Timing

Behavior

from

Suspend

.....

.

...........................

.

............

.

............

.

.......

.28

Figure

21

.

Resume

Timing

Behavior

(HS

Mode)

.........

.

........................................

.

............

.

...........................

.

.......

.29

Figure

22

.

Device

Attach

Behavior

....

.

........................................

.

............

.

...........................

.

............

.

....................

.31

Figure

23

.

Timing

Constraints

...........

.

............

.

........................................

.

............

.

............

.

..... .........

.

....................

.36

Table

Page

Table

1

.

Control

Interface

Pins

..........

.

............

.

............

.

........................................

.

............

.

..............

.

............

.

.........

.9

Table

2

.

USB

Interface

Pins

..............

.

............

.

........................................

.

............

.

............

.

..............

.

............

.

.......

.10

Table

3

.

Data

Input/Output Pins

(8-Bit

Transmit

and

Receive)

...............

.

............

.

............

.

...........................

.

.......

.10

Table

4

.

Data

Input/Output Pins

(16-Bit

Transmit

and

Receive)

.

............

.

........................................

.

....................

.10

Table

5

.

Data

Input

Pins

(Transmit)

.............................

.

............

.

........................................

.

..............

.

............

.

.......

.11

Table

6

.

Data

Output

Pins

(Receive)

..............

.

............

.

.....................................................

.

......... .....

.

............

.

.......

.11

Table

7

.

Power/Test

Pins

...............................

.

............

.

........................................

.

............

.

..............

.

............

.

.......

.12

Table

8

.

Suspend

Timing

Values

(HS

Mode)

.............................

.

............

.

...........................

.

............

.

............

.

.......

.22

Table

9

.

Reset

Timing

Values

(HS

Mode)

......

.

............

.

........................................

.

............

.

..............

.

............

.

.......

.23

Table

10

.

HS

Detection

Handshake

Timing

Values (FS

Mode)

...........................

.

............

.

...........................

.

.......

.25

Table

11

.

Reset

Timing

Values

.........

.

.....................................................

.

............

.

...........................

.

............

.

.......

.27

Table

12

.

HS

Detection

Handshake

Timing

Values

from

Suspend

.........

.

............

.

...........................

.

............

.

.......

.29

Table

13

.

Suspend

Timing Values

(HS

Mode)

.....................................................

.

............

.

...........................

.

.......

.30

Table

14

.

Attach

and

Reset Timing

Values

................................

.

............

.

............

.

...........................

.

....................

.31

Table

15

.

USB

2

.0

Test

Mode

to

USS2X1

Mapping

......

.

............

.

...........................

.

............

.

............

.

....................

.32

Table

16

.

do

Characteristics

...........................

.

............

.

........................................

.

............

.

..............

.

............

.

.......

.33

Table

17

.

ac

Characteristics

...........................

.

............

.

........................................

.

............

.

..............

.

............

.

.......

.33

Table

18

.

ac

Timing

(16-Bit)

...........................

.

............

.

........................................

.

............

.

..............

.

............

.

.......

.34

Table

19

.

ac

Timing

(8-Bit)

.............................

.

............

.

............

.

........................................

.

..............

.

............

.

.......

.35

Table

20

.

Timing

Constraints

for

USS2X1

(8-Bit)

........

.

........................................

.

............

.

...........................

.

.......

.36

Table

21

.

Timing

Constraints

for

USS2X1

(8-Bit)

........

.

........................................

.

............

.

...........................

.

.......

.37

Agere

Systems

Inc

.

3

AdLib OCR Evaluation

Agere

Systems

USB

2

.0

UTMI

Data

Sheet,

Rev

.

3

USS2X1

A

8-Bit

and

USS2X1

WA

16-Bit

PHY

Chips

October

2002

Functional

Block

Diagram

Figure

1

shows

the

functional

block

diagram

of

the

USB

2

.0

PHY

chip

.

Each

block

is

described

below

.

It

is

assumed

that

the

control

and

data

interface

pins

are

externally

connected

to a

logic

block

that

performs

the

of

USB

processing,

such

as

packet

decoding

.

In

this

document,

the

external

logic

block

that

performs

this

function

is

referred

to

as

the

SIE

(serial

interface

engine)

.

USB

2

.0

USS2X1

A

8-bit

AND

USS2X1

WA

16-bit

PHY

CHIP

RESETN

SUSPENDN

CLKOUT

XI

CLOCK

PLL

-------

CONTROL

XO

RREF

TXVALID

TRANSMIT

LOGIC

TXREADY

BIT

STUFF

NRZIENCODE

DATAf

15

:0]*

DATA[7

:0]*

II

USB

I

F

TRANSCEIVER

DP,

DM

VALIDHt

--I

HS/FS

ELASTICITY

HS

RECEIVE

BUI

FFER

I

CI

I

LOG

I

u

C

OPMODE[1

:0]

TERMSELECT

RXVALID

BIT

UNSTUFF

RXERROR

NRZI

DECODE

FS

XCVRSELECT

RXACTIVE

LINESTATE[1

:0]

[

I

LIDETECTE

*

DATA[15

:0]

only

exists

on

the

16-bit

PHY

chip,

and

DATA[7

:0]

only

exists

on

the

8-bit

PHY

chip

.

t

VALIDH

only

exists

on

the

16-bit

PHY

chip

.

Figure

1

.

USB

2

.0

USS2X1A

8-Bit

and

USS2X1WA

16-Bit

PHY

Chips

5-9296(F)

.b

R

.02

4

Agere

Systems

Inc

.

AdLib OCR Evaluation

Data

Sheet,

Rev

.

3

October

2002

Agere

Systems

USB

2

.0

UTMI

USS2X1

A

8-Bit

and

USS2X1

WA

16-Bit

PHY

Chips

Functional

Block

Diagram

(continued)

Clock

Control

andPLL

The

clock

control

and

PILL

blocks

generate

the

appropri-

ate

internal

clocks

for

the

USS2X1(W)A

and

the

CLK-

OUT

output

signal

(60

MHz

for

the

8-Bit

USS2X1

A

and

30

MHz

for

the

16-Bit

USS2X1

WA)

.

An

external

30

MHz

crystal

must

be

connected

to

the

XI

and

XO

pins

to

pro-

vide

a

reference clock

for

these

blocks

.

All

data

transfer

signals

are

synchronized

with

the

CLKOUT

output

.

After

the

deassertion

of

SUSPENDN,

the

CLKOUT

sig-

nal

generated

by

the

USS2X1(W)A

will

behave

as

fol-

lows

:

.

Produce

the

first

CLKOUT

transition

no

later

than

5

.6

ms

after

the

deassertion

of

SUSPENDN

.

The

CLKOUT

signal

frequency

error

will

be

less

than

±10%

.

The

CLKOUT

signal

will

fully

meet

the

required

accu-

racy

of

±500 ppm,

no

later

than

1

.4

ms

after

the

first

transition

of

CLKOUT

.

In

HS

mode,

there

is

one

CLKOUT

cycle

per

byte

time

for

the

8-Bit

USS2X1

A

.

In

FS

mode

for

the

USS2X1

A,

there

are

5

CLKOUT

cycles

per

FS

bit

time

and

40

CLK-

OUT

cycles

per

FS

byte

time

.

If

a

received byte contains

a

stuffed

bit,

then

the

byte

boundary

can

be

stretched

to

45

CLKOUT

cycles

and

two

stuffed

bits

would

result

in

a

50

CLKOUT

delay

between

bytes

.

The

frequency

of

CLKOUT

does

not

change

when

the

USS2X1(W)A

is

switched

between

HS

and

FS

modes

.

The

XCVRSELECT

signal

determines

whether

the

HS

or

FS

timing

relationship

is

applied

to

the

data

and

con-

trol

signals

.

High-Speed

(HS)

Clock Data

Recovery(CDR)

The

clock

data

recovery

(CDR)

block

recovers

the

serial

480

Mbits/s

data

received

by

the

transceiver

when

in

HS

mode,

as

indicated

by

the

XCVRSELECT

input

.

Elasticity

Buffer

As

defined

in

the

USB

2

.0

specification,

the

elasticity

buffer

manages

any

differences

between

the

local

clock

frequency

(derived

from

the

crystal

oscillator)

and

the

rate

at

which

HS

data

is

received

.

The

USB

specification

defines

a

maximum

clock

error

of

±500

ppm

.

When

the

error

is

calculated

over

the

maxi-

mum

packet

size

and

when

the

other

system

timing

margin

is

taken

into

consideration,

up

to

±12

bits

of

drift

can

occur

.

At

the

start

of

a

packet,

the

elasticity

buffer

is

filled

to

a

threshold

prior

to

enabling

the

remainder

of

the

downstream

receive

logic

.

Overflow

or

underflow

conditions

detected

in

the

elastic-

ity

buffer

are

reported

with

the

RXError

signal

.

Transmit Logic

The

transmit

logic

block

is

responsible

for

accepting

8-/16-bit

parallel

data from

the

parallel

application

bus

(i

.e

.,

the

SIE)

interface

upon

command

and

serializing

it

for

transmission

over

the

USB

2

.0

interface

.

This

mod-

ule

also

includes

logic

for

bit

stuffing,

NRZI

encoding,

SYNC

field,

and

EOP

generation

.

This

block

is

used

for

both

HS

and

FS

transmit

.

Receive

Logic

The

receive

logic

block

is

responsible

for

deserializing

received

data recovered

by

the

HS

CDR

or

FS

CDR,

and

providing

8-/16-bit parallel

data

to

the

application's

parallel

interface

with

the

SIE

.

This

module

also

includes

logic for

bit

unstuffing,

NRZI

decoding,

SYNC

field

and

EOP

field

detection,

and

stripping

.

This

block

is

used

for

both

HS

and

FS

receive

.

USB

Transceiver

The

USB

transceiver

is

capable

of

transmitting

and

receiving

at

the

HS

or

FS

bit

rates

and

edge

rates,

as

controlled

by

the

XCVRSELECT

input

.

The

transceiver

also

detects

line

inactivity

(squelch)

and

the

line

state

in

both

HS

and

FS

modes

.

All

termination

resistors

required

by

the

USB

2

.0

specification

are

located

inter-

nally,

and

are

controlled

by

the

TERMSELECT

input

.

Full-Speed

(FS)

Clock

Data

Recovery(CDR)

The

full-speed

(FS)

clock

data recovery

(CDR)

block

recovers

the

serial

12

Mbits/s

data

received

by

the

transceiver

when

in

FS

mode,

as

indicated

by

the

XCVRSELECT

input

.

This

block

also

accounts

for

any

differences

between

the

local

clock

frequency,

i

.e

.,

crystal

oscillator,

and

the

rate

at

which

FS

data

is

received

.

Line

State

Detect

Reports

the

logic

state

received

from

either

the

HS

or

FS

output

of

the

transceiver

.

Agere

Systems

Inc

.

5

AdLib OCR Evaluation

Agere

Systems

USB

2

.0

UTMI

Data

Sheet,

Rev

.

3

USS2X1

A

8-Bit

and

USS2X1

WA

16-Bit

PHY

Chips

October

2002

Functional

Block

Diagram

(continued)

Speed

Selection

The

XCVRSELECT

and

TERMSELECT

signals

determine

whether

the

device

is in

HS

or

FS

mode,

enabling

the

respective

transceiver

and

termination

.

The

HS

detection

handshake

protocol requires

independent

control

of

transceivers

and

terminations,

where

the

device

enables

FS

terminations

but

is

required

to

drive

and

listen

to

the

bus

with

the

HS

transceiver

.

In all

other

cases,

the

state

of

the

XCVRSELECT

and

TERMSELECT

signals

are

iden-

tical

.

Note

:

Most

sections

of this

document

assume

that

the

USS2X1

A

is

operating

with

an

8-bit

interface

.

The

timings

need

to

be

adjusted

appropriately

for

operation

using

a

16-bit

interface

.

The

timing

differences

will

be

explained

where

necessary

.

Unless

differences

are

specified,

it

may

be

assumed

that

the

16-bit

USS2X1

WA

functions

in

the

same

manner

as

the

8-bit

USS2X1A

.

Agere

Systems

Inc

.

AdLib OCR Evaluation

Data

Sheet,

Rev

.

3

Agere

Systems

USB

2

.0

UTMI

October

2002

USS2X1

A

8-Bit

and

USS2X1

WA

16-Bit

PHY

Chips

Information

Assignments

48-Pin

TQFP

TESTGND

VSST

DM

DP

VDDT

RREF

VDDA

VSSA

XI

XO

VDDX

SUSPENDN

0

Ir

}W

oo>F o

0

-

DJ

J

O

F--

Ir

W

(/J

w

°

wIQO

w

>

F-

°

c)

W

°

XXXJ

w

X

Q

°

>

F-

>

or F- or

U>

or

F-

p>

00 I~ (O Ln

VM

N

O

d1 00

I~

VVVVVV

V

VV

MM

M

1

.

36

2

35

#1

IDENTIFIER

3

34

4

33

5

32

6

AGERE

USB

2

.0

31

USS2X1

A

8-bit

7

PHY

CHIP

30

8

29

9

28

10 27

11

26

12 25

CM

V

Ln (O

I

:

00

d1r

ON

N

NN

CMNVN

rrrrrr

VSSN

TESTGND

DATA[l]

DATA[2]

DATA[3]

DATA[4]

VDD

TESTGND

DATA[5]

DATA[6]

DATA[7]

VSS

cn

° °

UU

w

r

oro

o

°

>ww>

wwww

>W

>> JJ DD

F-

WW QQQ

Q

F-

W

(n (n

22

aW

W

OOZ

Z

J

X

F-

0564

(F)

R

.03

Figure

2

.

48-Pin

TQFP

Package

Assignments

Agere

Systems

Inc

.

7

AdLib OCR Evaluation

Agere

Systems

USB

2

.0

UTMI

USS2X1

A

8-Bit

and

USS2X1

WA

16-Bit

PHY

Chips

Data

Sheet,

Rev

.

3

October

2002

Information

(continued)

Assignments

(continued)

64-Pin

TQFP

TESTGND

VSST

VDDT

DM

DP

VDDT

VSST

RREF

VDDA

VSSA

XI

XO

VDDX

VDD

SUSPENDN

VSS

zz z >

oo

F-

o

o_

C7

0 0

IrC

o

wU

= 0 Q J z

U)

WW

w

W

o

XXX

O

w

QXXQ

°o

>

F- F-

>

F-

>

or F- or

U

>

or F-

0

>

V

(M

NOWW

M

Ln Ln

(O

MVMN OW

(O

Ln Ln Ln Ln Ln

V

(0(0(0

(O Ln Ln

Ln

1

2

3

\",--PIN

#1

IDENTIFIER

4

5

6

7

8

AGERE

USB

2

.0

USS2X1

WA

16-bit

PHY

CHIP

10

11

12

13

14

15

16 I~ 00 d1

O N

CM

V

Ln

r

NNNNN

N

(O

11

WWON

N

NNNMM

C')

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

UU

can

T

or

o

z

~W

vh

o

>>

r_ r_ r_

>00 >

QQQ

>

J

-j

dd

U)

~ 000

U

wZ

Z

J

VSSN

DATA[i

]

DATA[2]

DATA[3]

DATA[4]

VDD

DATA[5]

DATA[6]

DATA[7]

DATA[8]

VSS

DATA[9]

DATA[10]

DATA[i

1 ]

DATA[12]

VSSN

0563

(F)

R

.03

Figure

3

.

64-Pin

TQFP

Package

Assignments

8

Agere

Systems

Inc

.

AdLib OCR Evaluation

Data

Sheet,

Rev

.

3

Agere

Systems

USB

2

.0

UTMI

October

2002

USS2X1

A

8-Bit

and

USS2X1

WA

16-Bit

PHY

Chips

Information

(continued)

Pin Descriptions

Control

Interface

Pins

Table

1

.

Control

Interface

Pins

Pin Pin

Name

Direction

Active

Description

NumberNumber

Level

(48-Pin) (64-Pin)

9

11

XI

Input

NA

Oscillator

Input

.

Connect

to

external

30

MHz

crystal

.

10 12

XO

Output

NA

Oscillator

Output

.

Connect

to

external

30

MHz

crystal

.

42 55

CLKOUT

Output

NA

Clock

.

This

output

is

used

for

clocking

receive

and

transmit

parallel

data

.

60

MHz

(8-bit

only)

.

30

MHz

(16-bit

only)

.

24 28

RESETN

Input

Low

Reset

.

Hardware

reset

.

16

20

XCVR-

Input

NA

Transceiver

Select

.

This

signal

selects

between

the

FS

SELECT

and

HS

transceivers

:

0

:

HS

transceiver

enabled

.

1

:

FS

transceiver

enabled

.

17

21

TERM-

Input

NA

Termination

Select

.

This

signal

selects

between

the

FS

SELECT

and

HS

terminations

:

0

:

HS

termination

enabled

.

1

:

FS

termination

enabled

.

12 15

SUSPENDN

Input

Low

Suspend

.

Places

the

USS2X1(W)A

in

a

mode

that

draws

minimal

power

from

supplies

.

Shuts

down

all

blocks

not

necessary

for

suspend/resume

operation

.

While

sus-

pended,

TERMSELECT

must

always

be

in

FSmode

to

ensure

that

the

1 .5

ktl

pull-up

on

DP

remains

powered

.

0

:

USS2X1(W)A

drawing

suspend

current

.

1

:

USS2X1(W)A

drawing

normal

current

.

21,22 25,26

LINESTATE

Output

NA

Line

State

.

While

the

device

is

suspendedand

while

the

[1

:0]

device

is

resuming from a

suspended

state,

these

signals

are

combinatorial,

i

.e

.,

directly reflect

the

current

state

of

the

DM

and

DP

signals

.

Otherwise,

these

signals

are

syn-

chronized

to

the

CLKOUT

output

.

_DM

DP

Description

0 0 0

:

SEO

0

1 1

:

J

state

1

0 2

:

K

state

1 1

3

:

SE1

19,20

23,24

OPMODE

Input

NA

Operational

Mode

.

These

signals

select

between

various

[1

:0]

USS2X1(W)A

operational

modes

:

OPMODE

[1

:0]

Description

0

0 0

:

Normal

operation

0

1 1

:

Nondriving

all

terminations

removed

1

0 2

:

Disable

bit

stuffing

and

NRZI

encoding

1

3

:

Reserved

Agere

Systems

Inc

.

9

AdLib OCR Evaluation

Agere

Systems

USB

2

.0

UTMI

Data

Sheet,

Rev

.

3

USS2X1

A

8-Bit

and

USS2X1

WA

16-Bit

PHY

Chips

October

2002

Information

(continued)

Pin Descriptions

(continued)

USB

Interface

Pins

Table

2

.

USB

Interface

Pins

Pin Pin

Name

Direction

Active Description

NumberNumber

Level

(48-Pin) (64-Pin)

45

DP

Bidir

NA

USB

Data

Data+

.

3 4

DM

Bidir

NA

USB

Data

Data-

.

6 8

RREF

NA

External

Reference

.

Requires

1

%

precision

1

k52

resistor

to

ground

.

Data

Input/Output

Pins

(8-Bit)

Table

3

.

Data

Input/Output

Pins

(8-Bit

Transmit

and

Receive)

Name

Direction

Active

Description

Number

Level

(48-Pin)

26-28,

31

34

DATA

7 0

Bidir

NA

TXVALID RXVALID

DATA[7

:0]

-

,

[

:

]

38 0 0 Not

in

use

.

0

1

Data

[7

:0]

output

is

valid

for

receive

.

1

X

Data

[7

:0]

output

is

valid

for

transmit

.

Data

Input/Output

Pins

(16-Bit)

Table

4

.

Data

Input/Output

Pins

(16-Bit

Transmit

and

Receive)

Name

Direction

Active

Description

Number

Level

(64-Pin)

29-31,

DATA

Bidir

NA

TXVALID

RXVALID

VALIDH

DATA[15

:0]

34 37

15

0

"

-

, [ :

]

0

X

Not

in

use

39-42

.

,

44-47,

0

1

0

Data

[7

:0]

output

is

valid

for

50

receive

.

0

1

Data

[15

:0]

output

is

valid

for

receive

.

1

X

0

Data

[7

:0]

output

is

valid

for

transmit

.

1

X

1

Data

[15

:0]

output

is

valid

for

transmit

.

53

VALIDH*

Bidir

High

If

TXVALID

=

1,

this

chip's

input,

when

asserted,

indicates

that

the

entire

16-bit

DATA

input

is

to

be

transmitted

over

USB

.

If

deas-

serted,

it

indicates

that only

DATA

[7

:0]

is to

be

transmitted

.

If

TXVALID

=

0

and

RXVALID

=

1,

this

chip's

output,

when

asserted,

it

indicates

that

the

entire 16-bit

DATA

output

is

valid

.

If

deas-

serted,

it

indicates

that

only

DATA

[7

:0] is

valid

.

*

Pull-down

resistance

is

50

kit,

nominal

.

10

Agere

Systems

Inc

.

AdLib OCR Evaluation

Data

Sheet,

Rev

.

3

Agere

Systems

USB

2

.0

UTMI

October

2002

USS2X1

A

8-Bit

and

USS2X1

WA

16-Bit

PHY

Chips

Information

(continued)

Pin Descriptions

(continued)

Data

Input

Pins

(Transmit)

Table 5

.

Data

Input

Pins

(Transmit)

Number

(48-Pin)

Number

(64-Pin)

Name

Direction

Active

Level

Description

39

51

TXVALID

Input

High

Transmit

Valid

.

Indicates

that

the

DATA

bus

is

a

valid

input

.

The

assertion

of

TXVALID

initiates

SYNC

on

the

USB

.

The

negation

of

TXVALID

initiates

EOP

on

the

USB

.

44 57

TXREADY

Output

High

Transmit

Data

Ready

.

Indicates

that

the

transmitter

requires

data

.

The

application

must

have

data

available

for

clocking

in

to

the

DATA

inputs

on

the

rising

edge

of

CLK

.

If

TXVALID

is

negated,

TXREADY

can be

ignored

by

the

application

.

Data

Output

Pins

(Receive)

Table 6

.

Data

Output

Pins

(Receive)

Pin Pin Pin

Name

Active

Description

NumberNumber

Direction

Level

(48-Pin) (64-Pin)

40 52

RXVALID

Output

High

Receive Data

Valid

.

Indicates

that

the

DATA

bus has

valid

data

.

The

application

is

expected

to latch

the

DATA

bus

on

the

clock

edge

.

43 56

RXACTIVE

Output

High

Receive

Active

.

Indicates

that

the

receive

state

machine

has

detected

SYNC

and

is

active

.

RXActive

is

negated

after

a

bit

stuff

error

or

an

EOP

is

detected

.

45 58

RXERROR

Output High

Receive

Error

.

0

:

Indicates

no

error

.

1

:

Indicates

that a

receive

error

has

been

detected

.

Possible

sources

of

errors

are

as

follows

:

.

Bit

stuff

error

has

been

detected

during

a

FS

receive

operation

.

Elasticity

buffer

overrun

.

Elasticity

buffer

underrun

.

Alignment

error,

EOP

not

on a

byte

boundary

.

Agere

Systems

Inc

.

11

AdLib OCR Evaluation

Agere

Systems

USB

2

.0

UTMI

Data

Sheet,

Rev

.

3

USS2X1

A

8-Bit

and

USS2X1

WA

16-Bit

PHY

Chips

October

2002

Information

(continued)

Pin Descriptions

(continued)

Power/Test

Pins

Table 7

.

Power/Test

Pins

Pin Pin Pin

Name

Active

Description

NumberNumber

Direction

Level

(48-Pin) (64-Pin)

15,

23,

14, 19,

VDD

NA NA

Chip

Power

.

VDD

=

3

.3

V

±

5%

.

30,46

27,

43,

59

18,

25,

16,

22,

Vss

NA NA

Chip

Ground

.

41,48

38,

54,

61,64

14,37

18,

32,

VDDN

NA NA

10

Power

.

49

13,36

17,

33,

VssN

NA NA

10

Ground

.

48

8 10

VssA

NA NA

Analog

Ground

.

5

3,6

VDDT

NA NA

Transceiver

Power

.

2

2,7

VssT

NA NA

Transceiver

Ground

.

7 9

VDDA

NA NA

Analog

Power

.

11

13

VDDX

NA NA

Oscillator

Power

.

1,

29,

1,

60,

TESTGND

Input

High Test

Ground

.

Inputs

for

hardware

test

modes

.

35,47 62,63

Must

be

connected

to

ground

.

12

Agere

Systems

Inc

.

AdLib OCR Evaluation

Data

Sheet,

Rev

.

3

October

2002

Agere

Systems

USB

2

.0

UTMI

USS2X1

A

8-Bit

and

USS2X1

WA

16-Bit

PHY

Chips

HS

Functionality

of

the

USS2X1

A

HS

Transmit

(8-Bit)

The

HS

transmit

logic

for

the

USS2X1

A

is

controlled

in

the

following

manner

:

.

The

SIE

asserts

TXValid

to

begin

a

transmission

.

The

SIE

negates

TXValid

to

end a

transmission

.

. After

the

SIE

asserts

TXValid,

it

must

assume

that

the

transmission

has

started

when

it

detects

TXReady

is

asserted

.

The

SIE

must

assume

that

the

USS2X1

A

has

con-

sumed

a

data

byte

if

TXReady

and

TXValid

are

asserted

.

The

SIE

must

have

valid

packet

information

(PID)

asserted

on

the

DATA

input

bus

coincident

with

the

assertion

of

TXValid

.

TXReady

may

be

asserted

at

the

same

time

as

TXValid

or

later

.

TXValid

and

TXReady

are

sampled

on

the

rising

edge

of

CLKOUT

.

The

transmit

logic

does

not

automatically

generate

packet

ID

(PID)

or

CRC

fields

.

When

transmitting,

the

SIE

is

always expected

to

present

a PID

field

as

the

first

byte

of

the

data

stream

and,

if

appropriate,

a

CRC

field

as

the

last

byte

(bytes) of

the

data

stream

.

Figure

4

shows

the timing

relationship

in

the

HS

mode

between

TXValid,

DATA

input,

TXReady,

and

the

trans-

mitted

data

(DP/DM)

.

The

SIE

negates

TXValid

to

complete a

packet

.

Once

negated,

the

transmit

logic

will

not

reassert

TXReady

until

after

the

EOP

has

been

generated

.

Note

that

although

the

USS2X1(W)A

transmit

logic

can be

ready

to

start

another

packet

immediately,

the

SIE

must

con-

form

to

the

minimum

interpacket

delay

identified

in

Section

7

.1

.18 of

the

USB

2

.0

specification

.

In

HS

mode,

if

an

error

condition

occurs

during

trans-

mission,

the

current

transmit

stream

must

be

termi-

nated

by

the

transmission

of

a

complemented

version

of

the

CRC,

followed

by an

EOP

.

In

this

case,

the

SIE

will

be

responsible

for

presenting

the

complemented

CRC

to

the

DATA

input

lines

before

negating

TXValid

.

The

negation

of

TXValid

will

cause

the

USS2X1(W)A

to

terminate

the packet

with

the

appropriate

EOP

.

CLKOUT

'

TXVALID

DATAIN(7

:0)PID'

XDATAXDATAXDATAXDATAX

CRC

X

CRC

~VVVVV~

TXREADY

~

DP/DM

SYNC

PI

D

DATADATA

DATA DATA

CRC CRC

EOP

0899

(F)

Figure

4

.

HS

Transmit

Timing

for

a Data

Packet

(8-Bit)

Agere

Systems

Inc

.

13

AdLib OCR Evaluation

Agere

Systems

USB

2

.0

UTMI

USS2X1

A

8-Bit

and

USS2X1

WA

16-Bit

PHY

Chips

Data

Sheet,

Rev

.

3

October

2002

HS

Functionality

of

the

USS2X1

A

(continued)

HS

Receive

(8-Bit)

The

HS

receive

logic

behavior

is

controlled/indicated

as

follows

:

.

RXActive and RXValid

are

sampled

on

the

rising

edge

of

CLKOUT

.

The

receiver

will

initially

look

for

SYNC

.

The

USS2X1A

asserts

RXActive

when

SYNC

is

detected,

and

will

strip

the

SYNC

field

.

The

USS2X1A

negates

RXActive

when

an

EOP

is

detected

and

will

strip

the

EOP

field

.

When

RxActive

is

asserted,

RXValid

will

be

asserted

if

valid

data

is

available

on

the

data

outputs

.

RXValid

will

be negated

if

valid

data

is

not available

on

the

data

outputs

.

This

will

occur

if

8

stuffed

bits

havebeen

accumulated

.

The

SIE

must

be

ready

to

consume

a

data

byte

if

RXActive and RXValid

are

asserted

.

The

possible

sources

of

HS

receive

errors

are

as

fol-

lows

:

.

Bit

stuff

error

has

been

detected

during

an

FS

receive operation

.

Elasticity

buffer

overrun

.

Elasticity

buffer

underrun

.

Alignment

error,

i

.e

.,

EOP

not

on a

byte

boundary

.

If

any

of

these

receive

errors

is

detected,

RXError

is

asserted

.

When

the

last

data

byte

is

clocked

off

the

DATA

output

bus,

the

SIE

must

also

capture

the

state

of

the

RXError

signal

.

Note

:

In

HS

mode,

bit

stuff

errors

are

used

to

generate

the

EOP

signal

;

therefore,

the

RXError

signal

is

not

asserted

in

this

case

.

Figure

6

shows

the

timing

relationship

between

the

received

data

(DP/DM),

RXValid,

RXActive,

RXError,

and

DATA

output

signals

.

Note

that

the

USS2X1(W)A

does

not

decode

packet

IDs

(PIDs)

.

They

are

passed

to

the

SIE

for

decoding

.

The

receive section

of

the

USS2X1(W)A

is

disabled

when

the

transmit

section

is

active

.

The

USS2X1(W)A

does

not

respond

to

downstream

USB

traffic

while

the

SIE

is

transmitting

.

Although

the

bit

rate

on

USB

is

constant,

the

bit

rate

as

presented

by

the

USS2X1(W)A

to

the

SIE

is

slightly

reduced

due

to

the

extraction

of

inserted

1

bits

.

Nor-

mally,

a

byte

of

data

is

presented

on

the

DATA

outputs

for

every

8

bits

received

.

However,

after

eight

stuffed

bits

are

eliminated

from

the

data

stream,

a

byte

time

is

skipped

in

the

DATA

output

stream

.

Figure

5

shows

how

RXValid

is

used

to

skip

bytes

in

the

DATA

output

stream

.

This

example

shows

the

timing

in

HS

mode

for

the

8-bit

USS2X1A

.

CLKOUT

'

RXACTIVE

i i

INVALID

DATA,

I

DATAOUT(7

:0)

RXVALID

i

0892

(F)

Figure

5

.

HS

Receive

Timing

for

Data

with

Unstuffing

Bits

(8-Bit)

14

Agere

Systems

Inc

.

AdLib OCR Evaluation

Data

Sheet,

Rev

.

3

Agere

Systems

USB

2

.0

UTMI

October

2002

USS2X1

A

8-Bit

and

USS2X1

WA

16-Bit

PHY

Chips

HS

Functionality

of the

USS2X1

A

(continued)

Note

:

Figure

6,

Figure

7,

and

Figure

8

are

timing

examples

of

the

USS2X1

Awhen

it

is

in

HS

mode

.

When

in

FS

mode,

there

are

approximately

40

CLK

cycles

every

byte

time

.

The

receive

logic

assumes

that

the

SIE

captures

the

data

on

the

DATA

output

bus

if

RXActive and

RXValid

are

asserted

.

In

FS

mode,

RXValid

will

only

be

asserted

for

one

CLK

per

byte

time

.

CLKOUT

'

RXACTIVE

DATAOUT(7

:0)~(

X X

)( )( )

PID

X

DATA

X

DATA

X

DATA

X

DATA

111

CRC

1111

CRC

I I

IYYY~LIL

I I

IIIII

I~

W

vI

RXVALID

RXERROR

i

DP/DM

SYNC

PID

x

DATA

x

DATA

A

DATA

A

DATA

CRC

x

CRC

x

EOP

CRC-16

COMPUTATION

Figure 6

.

HS

Receive

Timing

for

Data

Packet

(with

CRC-16)

(8-Bit)

0894

(F)

In

Figure

6,

Figure

7,

and

Figure

8,

the

SYNC

pattern

on

DP/DIVI

is

shown

as

one

byte

long

.

In

reality,

the

SYNC

pattern

received

by a

USB

high-speed device

can

vary

in

length

.

These

three

figures

assume

that

all

but

the

last

12

bits

havebeen

consumed

by

the

hubs

between

the device

and

the

host

controller

.

It

should

also

be

noted

that

in

these

three

figures,

the

packet

received

on

DP/DIVI

is

pipelined

by

the

USS2X1(W)A

and

may

occur

several

bit

times,

or

even

several

byte

times

earlier,

relative

to

the

USS2X1(W)A

signal transitions

(RXActive,

DATA

output,

RXValid,

etc

.)

.

Agere

Systems

Inc

.

15

AdLib OCR Evaluation

Agere

Systems

USB

2

.0

UTMI

USS2X1

A

8-Bit

and

USS2X1

WA

16-Bit

PHY

Chips

Data

Sheet,

Rev

.

3

October

2002

HS

Functionality

of

the

USS2X1

A

(continued)

CLKOUT

'

RXACTIVE

DATAOUT(7

:0)

MXWM

PID

DATA

X

DATA

r

i

r

RXVALID

RXERROR

DP/DM

~~

SYNC

x

PID

x

DATA

x

DATA

X

EOP

CRC-5

COMPUTATION

0895

(F)

Figure 7

.

HS

Receive

Timing

for

Setup

Packet

(8-bit)

. .

CLKOUT

RXACTIVE

DATAOUT(7

:0)

PID

RXVALID

RXERROR

i

DP/DMSYNC

X

PID

EOP

YYYYYYYYYY

0896

(F)

Figure

8

.

HS

Receive

Timing

for

a

Handshake

Packet(No

CRC)

(8-bit)

16

Agere

Systems

Inc

.

AdLib OCR Evaluation

Data

Sheet,

Rev

.

3

October

2002

Agere

Systems

USB

2

.0

UTMI

USS2X1

A

8-Bit

and

USS2X1

WA

16-Bit

PHY

Chips

Functional

Differences

Between

USS2X1

A

(8-Bit

Interface)

and

the

USS2X1

WA

(16-Bit

Interface)

The

64-pin

package,

USS2X1

WA

supports

a

16-bit

data

interface

.

The

operation

of

the

16-bit

version

dif

fers

from

that of

the

8-bit

version

as

follows

:

.

CLKOUT

will

run

at half

the

rate of

the

equivalent

8-bit

version

(30

MHz)

.

An

additional

signal

(ValidH)

is

used

to

identify

whether

the

high

byte

of

the

respective

16-bit

data

word

is

valid

.

Additional

data

pins

are

provided

(DATA

15

:8)

.

The

TXReady

signal

will

drop low

for

one

clock

period

each

time

16

stuffed

bits

are

accumulated

.

With

the

8-bit

interface,

the

TXReady

signal

will

drop

low

after

the

accumulation

of

8

stuffed

bits

.

The

RXValid

signal

will

drop

low

for

one

clock

period

each

time

16

stuffed

bits

are

accumulated

.

With

the

8-bit

interface,

the

RXValid

signal

will

drop

low

after

the

accumulation

of

8

stuffed

bits

.

Note

that

the

other

sections

of this

document

assume

that

the

USS2X1A

is

operating

with

an

8-bit

interface

.

The

timings

need

to

be

adjusted

appropriately

for

oper-

ation

using

a

16-bit

interface

.

Examples

of

the

16-bit

USS2X1

WA's

operation

are

shown

in

Figure

9,

Figure

10,

Figure

11,

and

Figure

12

.

Agere

Systems

Inc

.

17

AdLib OCR Evaluation

Agere

Systems

USB

2

.0

UTMI

Data

Sheet,

Rev

.

3

USS2X1

A

8-Bit

and

USS2X1

WA

16-Bit

PHY

Chips

October

2002

Functional

Differences

Between

USS2X1A

(8-Bit

Interface)

and

the

USS2X1WA

(16-Bit

Inter-

face)

(continued)

HS

Transmit

(16-Bit)

CLKOUT

TXVALI

D

VALIDH

(INPUT)

DATA

(INPUT) PID

A DATA

(1)

A

DATA

(3)

A

CRC

(LO)

(7

:0)

i

r r r

i

r

, i

I

I I

III

I I

III

I I

I

DATA

(INPUT)

DATA

(0)

X DATA

(2)

X

DATA

(4)

CRC

(HI)

M

EN=

,

(15

:$)

i

r r r

i

r

i

I

I I

III

I I

III

I I

I

TXREADY

I

II

III

I I

III

I I

I

I I

III

I I

III

I I

I

I ~

~~I

I I

III

I I

I

I I

III

I I

DP/DM

SYNC

PID

DATA

DATA DATA DATA

DATA

CRC

EOP

0

1

2

'

3 4

LO

'

HI

'

1315

(F)

R

.01

Figure

9

.

HS

Transmit

Timing

for

16-Bit

Data,

Even

Byte

Count

CLKOUT

TXVALID

VALIDH

(INPUT)

DATA

(INPUT)

PID

DATA

(1)

A DATA

(3)

A

CRC

(H

I)

(]

:0)

i i

r

i

r r r

i

,

III

I I

III

I

DATA

(INPUT)

DATA

(0)

DATA

(2)

X

CRC

(LO)

(15

:8)

I ~

~ ~

I I

III

I

I I

I

TXREADY

II

I

I ~

~ ~

I I

III

I

III

I I

III

I

III

I I

III

I

I I

III

I

DP/DM

SYNC

PID

DATA

DATADATADATA

CRC

CRC EOP

0

1

2 3

LO

HI

1316

(F)

R

.01

Figure 10

.

HS

Transmit

Timing

for

16-Bit

Data,

Odd

Byte

Count

18

Agere

Systems

Inc

.

AdLib OCR Evaluation

Data

Sheet,

Rev

.

3

October

2002

Agere

Systems

USB

2

.0

UTMI

USS2X1A

8-Bit

and

USS2X1

WA

16-Bit

PHY

Functional

Differences

Between

USS2X1A

(8-Bit

Interface)

and

the

USS2X1WA

(16-Bit

Inter-

face)

(continued))

HS

Receive

(16-Bit)

CLKOUT

I

I I

IIII

I

III

I

I I

IIII

I

III

I

I I

IIII

I

III

RXVALID

I

I I I I

I

I I

IIII

I

III

I

I I

III

I

I I

III

I

III

VALIDH

I

I I

I

I I I

I I

I

(OUTPUT)

I

I I

IIIII

I

III

DATA

(OUTPUT)

M

PID

X

DATA

(1)

X DATA

(3)

x

CRC

(LO)

(~IXX/(XX

(7

:0)

VVVVVVVVVVVVVVVV\/VVVVVVVV~

,

i i

r

i

I

I I

III

r

iI

I

r

i

r

i

YYYYYYYYJllL~1uu~

III

DATA

(OUTPUT)

DATA

(0)

~

X

DATA

(2)

X DATA

(4)

X

CRC

(HI)

(J(XJ(~(J(X

(15

:8)

VVVVVVVVV\/VVVVVVV1/~

YYYYYYYYYYLJ1uu

i

r

I

I I

III

r

iI

Ii

r r

III

I

I I I

RXACTIVE

I

I I

I

I I

III

I

I I

III

I

III

I

I I

IIII

I

III

DP/DM

I I

SYNC

PID

DATA DATA DATA

I

DATADATA

III

CRC CRC

EOP

0

1

234

LO

HI

1317

(F)

R

.01

Figure

11

.

HS

Receive

Timing

for

16-Bit

Data,

Even

Byte

Count

CLKOUT

I

IIII

I I

III

I

IIII

I I

III

I

IIII

I I

III

I

RXVALID

I

I I I I

I

IIII

I I

III

I

IIII

I I

III

I

IIII

I I

III

I

I I

III

I

VALIDH

I

I I I I

I

(OUTPUT)

I I I

I

IIII

I I

III

I

DATA(OUTPUT)

PID

DATA

(1)

X DATA

(3)

X

CRC

(HI)

(7

:0)

,

i

,

r

i

r

i

r

YYYYYYYYYYYYYYYIYYL'

I

IIII

I I

III

I

DATA

(OUTPUT)

DATA

(0)

DATA

(2)

CRC

(LO)

(15

:8)

I

IIII

I I

III

I

II

I

RXACTIVE

I

I I I I

I

IIII

I I

III

I

IIII

I I

III

I

IIII

I I

I

III

I I

DP/DM

~SYNC~

PID

DATA DATA

DATADATA

CRC CRC

EOP

0

1

2 3

LO

HI

1318

(F)

R

.01

Figure 12

.

HS

Receive

Timing

for

16-Bit

Data,

Odd

Byte

Count

Agere

Systems

Inc

.

19

AdLib OCR Evaluation

Agere

Systems

USB

2

.0

UTMI

Data

Sheet,

Rev

.

3

USS2X1

A

8-Bit

and

USS2X1

WA

16-Bit

PHY

Chips

October

2002

FS

Functionality

CLKOUT

RXACTIVE

X

III

I

X

IIII

DATAOUT(7

:0)

DATA DATA

DATA

RXVALID

i

\

I i

i i

\

Iii

-4

DATA

BYTE

BOUNDARIE

S

0891

(F)

Figure 13

.

FS

CLKOUT

Relationship

to

Receive

Data

and

Control

Signals

CLKOUT

TXVALID

X

IIII

X

IIII

X

;

DATAIN(7

:0)

DATA(n)

`

DATA(n

+

1) (

DATA(n

+

2)

TXREADY

i

\

I i i i

\

Iii

DATA

BYTE

BOUNDARIE

S

0892

(F)

Figure 14

.

FS

CLKOUT

Relationship

to

TransmitData

and

Control

Signals

Note

:

The

receiv

e

section

of

the

USS2X1(W)A

is

disabled

when

the

transmit

section

is

active

.

The

USS2X1(W)A

does

not

respond

to

USB

traffic

that

is

transmitting

information

.

20

Agere

Systems

Inc

.

AdLib OCR Evaluation

Data

Sheet,

Rev

.

3

October

2002

Agere

Systems

USB

2

.0

UTMI

USS2X1

A

8-Bit

and

USS2X1

WA

16-Bit

PHY

Chips

Other

Functions

The

OpMode

signals

are

capable

of

inhibiting

normal

operation

of

the

transceiver

and

evoking

special

test

modes

.

These

modes

take

effect

immediately

and

take

precedence

over

any

pending

data

operations

.

The

transmission

data

rate

when

in

any

OpMode

depends

on

the

state of

the

XcvrSelect

input

.

There

are

three

valid

settings

for

OpMode

:

.

Normal

operation

(0)

.

Nondriving

(1)

.

Disable

bit

stuffing

and

NRZI

encoding

(2)

Mode

0

allows the

transceiver

to

operate

with

normal

USB

data

decoding

and

encoding

.

Mode

1

allows

the

transceiver

logic to

support

a

soft dis-

connect

feature

that

3-states

both

the

HS

and

FS

trans-

mitters,

and

removes

any

termination

from

the

USB

making

it

appear

to

an upstream

port that

the

device

has been

disconnected from

the

bus

.

In

this

mode,

the

receive

logic

is

still

active

.

Mode

2

disables

the

bit

stuff

and

NRZI

encoding

logic,

therefore,

1

s

loaded

from

the

DATA

input

bus

become

Js

on

the

DP/DM

lines

and

Os

become

Ks

.

Note

that

this

mode

effects

the

automatic

SYNC

pattern

and

EOP

generation

by

TXValid,

which

is

disabled so

that

chirps

can be

generated

on

the

USB

.

The

operation

of

the

receiver

is

undefined

.

Note

that

the

OpMode

signals

are

normally

changed

only

when

the

transmitter

and

the

receiver

are quies-

cent,

i

.e

.,

when

entering

a

test

mode

or for

a

device

initi-

ated

resume,

the

OPMode

is

set

and

then

TXValid

is

asserted

.

In

this

case,

the

SYNC

pattern

and

EOP

are

not

transmitted

by

the

USS2X1

A

.

The

only

exception

is

when

the

OPMode

signals

are set

to

mode

2

while

TXValid

is

asserted

(the

transceiver

is

transmitting

a

packet),

in

order

to

flag

an

FS

transmis-

sion

error

.

See

the

Transmit Logic

section

for

more

information

.

In

this

case,

the

SYNC

pattern

has

already

been

transmitted

by

the

USS2X1

A

.

Therefore,

upon

the

negation

of

TXValid,

the

EOP

must

also

be

transmitted

to

properly

terminate

the

packet

.

Changing

the

OPMode

signals

under

all

other

condi-

tions,

while

the

transceiver

is

receiving

or

transmitting

data,

will

generate

undefined

results

.

Setting

OpMode

to

3

will

also

produce

undefined

results

.

The

LineState

signals

are

used

for

many

functions

.

The

LineState

signals

reflect

the

current

state of

the

DP/DM

signal

lines

.

The

thresholds

used by

the

LineState

to

determined

the

state

of

DP/DM

depend

on

the

value

of

XcvrSelect

.

LineState

uses

HS

thresholds

when

the

HS

termination

is

enabled

(XcvrSelect

=

0)

and

FS

thresh-

olds

when

the

FS

transceiver

is

enabled

(XcvrSelect

=

1)

.

The

following

sections

make

a

distinction

between

soft

SEO

and

driven

SEO

.

Soft

SEO

is

the

bus

signaling

that

results

from

the

DP

and

DM

signal

lines

being

pulled

down

exclusively

by

the

15

k52

pull-down

resistors

(Rpd)

.

Driven

SEO

is

the

result

of

generating

an

SEO

condition

by

enabling

the

FS

transmitter

.

In

this

case,

the

DP

and

DM

signal

lines

are

being

pulled

down

by

the

45

52

serial

(Rs)

termination

resistors

.

Note

that

Rpd

and

Rs

are

defined

in

Figure

7

.1

of

the

USB

2

.0

specification

.

SEO

Handling

For

full-speed operation,

idle

is

a

J state

on

the

bus

and

SEO

is

used as

part

of

the

EOP

or to

indicate

reset

.

When

asserted

in

an EOP,

SEO

is

never asserted

on

the

bus

for

more

than

two

low-speed

bit

times

(1 .3 ~ts)

.

The

assertion

of

SEO

for

more

than

2

.5

~ts

is

interpreted

as a

reset

by a

full-speed

device

.

For

high-speed

operation,

idle

is

an

SEO

state

on

the

bus

.

SEO

is

also

used

to

reset

a

high-speed

device

.

A

high-speed

device

cannot

use

the

2

.5

~ts

assertion

of

SEO

(as

defined

for

FS

operation)

to

indicate

reset

since

the

bus

is

often

in

this

state

between

packets

.

If

no

bus

activity

(idle)

is

detected

for

more

than

3 ms, a

high-

speed

device

must

determine

whether

the

downstream

port

is

signaling

a

suspend

or a

reset

.

The

Suspend

Detection

and

Reset

Detection

sections

detail

how

this

determination

is

made

.

If

a

reset

is

signaled,

the

high-

speed

device

will

then

initiate

the

HS

detection

hand-

shake

protocol,

as

defined

in

the

HS

Detection

Hand-

shake

(Chirping)

section

.

Note

that

the

initial

assertion

of

SEO

on

the

bus

is

referred

to

in

the

core

specification

and

this

specification

as

HS

Reset

TO

(see

Section

7

.1

.7

.5

Reset

Signaling

of

the

USB

2

.0

specification,

Rev

.

2)

.

Suspend

Detection

If

an

HS

device

detects

SEO

asserted

on

the

bus

for

more

than

3

ms

(T1),

its

USS2X1

A

is

placed

in

FS

mode

(XcvrSelect

and

TermSelect

=

1)

.

This

enables

the

FS

pull-up

on

the

DP

line,

asserting

a

continuous

FS

J

state

on

the

bus

.

The

SIE

must

then

check

the

LineState

signals

for

a

J

state

condition

.

If

J

state

condi-

tion

is

asserted

at

time

T2,

then

the

upstream

port

is

asserting

a

soft

SEO

and

the

USB

is in

a J

state

indicat-

ing

a

suspend

condition

.

By

time

T4, the

device

must

be

fully

suspended

.

Agere

Systems

Inc

.

21

AdLib OCR Evaluation

Agere

Systems

USB

2

.0

UTMI

Data

Sheet,

Rev

.

3

USS2X1

A

8-Bit

and

USS2X1

WA

16-Bit

PHY

Chips

October

2002

Other

Functions

(continued)

TIME

TO

T1

T2 T3 T4

i

SUSPENDN

XCVR

SELECT

TERM

SELECT

i

DP/DM

SOFT

SEO

i

J

STATE

LAST

I

ACTIVITY

DEVICE

IS

SUSPENDED

1319

(F)

R

.01

Figure

15

.

Suspend

Timing

Behavior

(HS

Mode)

Table 8

.

Suspend

Timing

Values

(HS

Mode)

Timing

Description

Value

Parameter

HS

Reset

TO

End

of

last

bus

activity,

signaling

either

a 0

(reference)

reset

or

a

suspend

.

T1

The

time

at

which

the device

must

place

HS

reset

TO

+ 3

.0

ms

<

T1

{TwTREV} <

itself

in

FS

mode

after

bus

activity

stops

.

HS

reset

TO

+ 3

.125

ms

T2

SIE

samples

LineState

.

If

LineState

=

J,

T1

+

100 gs <

T2

{TWTWRSTHS}

<

then

the

initial

SEO

on

the

bus

(TO-T1)

T1

+

875

gs

had

been

due

to

a

suspend

state

and

the

SIE

remains

in

HS

mode

.

T3

The

earliest

time

where

a

device

can

issue

HS

reset

TO

+ 5

ms

{TWTRSM}

resume

signaling

.

T4

The

latest

time

that a

device

must

actually

HS

reset

TO

+ 10

ms

{T2SUSP}

be

suspended,

drawing

no

more

than

the

suspend

current

from

the

bus

.

Note

:

USB

2

.0

core

specification

timing

values are

referenced

in

curly

braces

{}

.

22

Agere

Systems

Inc

.

AdLib OCR Evaluation

Data

Sheet,

Rev

.

3

Agere

Systems

USB

2

.0

UTMI

October

2002

USS2X1

A

8-Bit

and

USS2X1

WA

16-Bit

PHY

Chips

Other

Functions

(continued)

Reset

Detection

If

a

device

in

HS

mode

detects

bus

inactivity

for

more

than

3

ms

(T1),

its

USS2X1A

is

placed

in

FS

mode

(XcvrSelect

=

1

and

TermSelect =

1)

.

This

enables

the

FS

pull-up

on

the

DP

line

to

attempt

to

assert

a

continuous

FS

J

state

on

the

bus

(dotted

line

in

Figure

16)

.

The

SIE

must

then

check

the

LineState

signals

for

the

SEO

condi-

tion

.

If

SEO

is

asserted

at

time

T2,

then

the

upstream

port

is

forcing

the

reset state

to

the device

(i

.e

.,

driven

SEO)

.

The

device

will

then

initiate

the

HS

detection

handshake

protocol

.

UPSTREAM

PORT

TO

ACTIONS

TIME

DEVICE

ACTIONS

T1

T2

XCVR

SELECT

i

TERM

SELECT

i

DP/DM DRIVEN

SEO

i,

LAST

ACTIVITI

~Y

HS

DETECTION

HANDSHAKE

Figure

16

.

Reset

Timing

Behavior

(HS

Mode)

Table 9

.

Reset

TimingValues(HS

Mode)

Timing

Description

Value

Parameter

HS

Reset

TO

Bus

activity

ceases,

signaling

either

a

reset

or

a 0

(reference)

suspend

.

T1

Earliest

time

at

which

the

device

may

place

HS

reset

TO

+

3

.0

ms

< T1

{TWTREV}

<

itself

in

FS

mode

after

bus

activity

stops

.

HS

reset

TO

+

3

.125

ms

T2 SIE

samples

LineState

.

If

LineState

=

SEO, T1 + 100 gs

<

T2

{TWTWRSTHS}

<

then

the

SEO

on

the

bus

is

due

to

a

reset state

.

T1 +

875

gs

The

device

now

enters

the

HS

detection

hand-

shake

protocol

.

1321

(F)

Agere

Systems

Inc

.

23

AdLib OCR Evaluation

Agere

Systems

USB

2

.0

UTMI

USS2X1

A

8-Bit

and

USS2X1

WA

16-Bit

PHY

Chips

Data

Sheet,

Rev

.

3

October

2002

Other

Functions

(continued)

HS

Detection

Handshake

(Chirping)

The

high-speed

detection

handshake

process

is

entered

from

one

of

three

states

:

suspend,

active

FS,

or

active

HS

.

The

downstream

port

asserting

an

SEO

state

on

the

bus

initiates

the

HS

detection

handshake

.

Depending

on

the

initial

state,

an

SEO

condition

can be

asserted

from

0 to

4

ms

before

initiating

the

HS

detec-

tion

handshake

.

These

states

are

described

in

Section

7

.1

.7

.5

of

the

USB

2

.0

specification,

Rev

.

2

(state

3

of

the

reset

protocol

for

HS

capable

hubs

and

devices)

.

There

are

three

ways

in

which a

device

may

enter

the

HS

handshake

detection

process

:

1

.

If

the device

is

suspended

and

it

detects

an

SEO

state

on

the

bus,

it

may

immediately

enter

the

HS

handshake

detection

process

.

2

.

If

the device

is in

FS

mode

and an

SEO

state

is

detected

for

more

than

2

.5

ps,

it

may

enter

the

HS

handshake

detection

process

.

3

.

If

the device

is in

HSmode

and

an

SEO

state

is

detected

for

more

than

3

.0

ms,

it

may

enter

the

HS

handshake

detection

process

.

In

HS

mode,

a

device

must

first

determine

whether

the

SEO

state

is

signal-

ing

a

suspend

or

a

reset

condition

.

To

do

this,

the

device

reverts

to

FS

mode

by

placing

XcvrSelect

and

TermSelect

into

FS

mode

.

The

device

must

not

wait

more

than

3

.125

ms

before

the

reversion

to

FS

mode

.

After reverting

to

FSmode

no

less

than

100

ps

and

no

more

than

875

ps

later,

the

SIE

must

check

the

LineState

signals

.

If

a

J

state

is

detected,

the

device

will

enter

a

suspend

state

.

If

an

SEO

state

is

detected,

then

the device

will

enter

the

HS

hand-

shake

detection

process

.

In

each

case,

the

assertion

of

the

SEO

state

on

the

bus

initiates

the

reset

interval

(referred to

in

this

section

as

HS

reset

TO)

.

The

minimum

reset

interval

is

10

ms

.

Depending

on

the

that

the

bus

was

in,

the

delay

between

the

initial

assertion

of

the

SEO

state

(HS

reset

TO)

and

entering

the

HS

handshake

detec-

tion

process

(TO

in

Table

10,

Table

11,

and

Table

12)

can be from

0 to

4

ms

.

The

USS2X1

A

relies

on

the

SI

E

to

perform

much

of

the

event

timing,

and

the

SIE

requires

a

stable

CLKOUT

signal

to

perform

accurate

timing

.

In

cases

2 and 3

above,

CLKOUT

has

been

running

and

is

stable

;

how-

ever

in

case

1,

the

USS2X1A

is

reset

from a

suspend

state,

and

the

internal

oscillator

and

clocks of

the

trans-

ceiver

are

powered

down

.

A

device

has up

to

6

ms

after

the

release

of

SuspendN

(HS

reset

TO)

to

assert

a

minimum

of

a

1

ms

Chirp

K

.

The

Clock

Control

and

PLL

section

describes

the

behavior

of

the

USS2X1A

which

allows

it

to

reliably

generate

a

1

ms

Chirp

K

.

FS

Downstream

Facing

Port

The

following

is

an

example

of

the

USS2X1

A

behavior

when

the

downstream

facing

port

that

it

is

attached

to

does

not

support

HS

operation

(a

USB

1

.X

host/hub)

.

Upon

entering

the

HS

detection

process

(TO),

XcvrSe-

lect

and

TermSelect

are

in

FS

mode

.

The

D+

pull-up

is

asserted

and

the

HS

terminations

are

disabled

.

The

SIE

then

sets

OpMode

to

disable

bit

stuffing

and

NRZI

encoding,

and

begins

the

transmission

of

all

Os

data,

which

asserts

a

HSK

(chirp)

on

the

bus

(T1)

.

The

device

chirp

must

last at

least

1

.0

ms

and

must

end

no

later

than

7

.0

ms

after

HS

reset

T0

.

At

time

T1,

the

SIE

sets

XcvrSelect

to

HS

mode

and

begins

listening

for

a

chirp

sequence

from

the

downstream

port

.

If

the

downstream

port

is

not

HS

capable,

then

the

HS

K

asserted

by

the device

is

ignored

and

the

alternating

sequence

of

HS

chirp

Ks

and

Js

is

not

generated

.

If

the

downstream

chirps are not

detected

(T4),

the device

will

enter

FS

mode

by

returning

XcvrSelect

to

FS

mode

.

24

Agere

Systems

Inc

.

AdLib OCR Evaluation

Data

Sheet,

Rev

.

3

Agere

Systems

USB

2

.0

UTMI

October

2002

USS2X1

A

8-Bit

and

USS2X1

WA

16-Bit

PHY

Chips

Other

Functions

(continued)

UPSTREAM

PORT

TO T3

ACTIONS

TIME

T5

DEVICE

ACTIONS

i

T1

T2

i

T4

i

XCVR

SELECT

TERM

SELECT

TXVALID

F

'DEVICE'

I

CHIRP

K

~SOF

DP/DM

i

SEO

UPSTREAM

I~ ~~

.

FS

MODE

'I

PORT

CHIRP

T~'I

NO

DOWNSTREAM

PORT

CHIRPS

Figure

17

.

HS

Detection

Handshake

Timing

Behavior

(FS

Mode)

Table

10

.

HS

Detection

Handshake

Timing

Values

(FS

Mode)

Timing

Description

Value

Parameter

TO*

HS

handshake

begins

.

D+

pull-up

enabled,

HS

0

(reference)

terminations

disabled

.

T1

T

Device

enables

HS

transceiver

and

asserts

TO <

T1

<

HS

reset

TO

+

6

.0

ms

chirp

K

on

the

bus

.

T2

Device

removes

chirp

K

from

the

bus

(1

ms

T1

+

1

.0

ms

{TuCH}

<

T2

<

minimum

width)

.

HS

reset

TO

+

7

.0

ms

{TUCHEND}

T3

Earliest

time

when

downstream

port

may

T2 < T3 <

T2+100

gs

{TWTDCH}

assert

chirp

K

on

the

bus

.

T4

Downstream

port

chirp

not

detected

by

the

T2 +

1

.0

ms

<

T4

{TWTFS}

<

device

.

Device

reverts

to

FS

default

state

and

T2 +

2

.5

ms

waits

for

end

of

reset

.

T5

Earliest

time

at

which

downstream

port

may

HS

reset

TO

+ 10

ms

{TDRST

(Min)}

end

reset

.

*

TO

may

occur

to

4

ms

after

HS

reset

T0

.

t

The

SIE must

assert

the

chirp

K

for

66000

CLKOUT

cycles

to

ensure

a

1

ms

minimum

duration

.

1323

(F)

Agere

Systems

Inc

.

25

AdLib OCR Evaluation

Agere

Systems

USB

2

.0

UTMI

Data

Sheet,

Rev

.

3

USS2X1

A

8-Bit

and

USS2X1

WA

16-Bit

PHY

Chips

October

2002

Other

Functions

(continued)

HS

Downstream

Facing

Port

The

following

is

an

example

of

the

USS2X1A

behavior

when

the

downstream

facing

port

that

it

is

attached

to

sup-

ports

HS

operation

(a

USB

2

.0

host/hub)

.

Upon

entering

the

HS

detection

process

(TO),

XcvrSelect

and

TermSelect

are

in

FS

mode

.

The

D+

pull-up

is

asserted,

and

the

HS

terminations

are

disabled

.

The

SIE

then sets

OpMode

to

disable

bit

stuffing

and

NRZI

encod-

ing,

and

begins

the

transmission

of

all

Os

data,

which

asserts

a

HS

K

(chirp)

on

the

bus

(T1)

.The

device

chirp

must

last

at least

1

.0

ms, and

must

end

no

later

than

7

.0

ms

after

HS

reset

T0

.

At time

T1,

the

SI

E

sets

XcvrSelect

to

HS

mode

and

begins

listening

for

a

chirp

sequence

from

the

downstream

port

.

If

the

downstream

port

is

HS

capable,

then

it

will

begin

generating

an

alternating

sequence

of

chirp

Ks

and

chirp

Js

(T3)

after

the

termination

of

the

chirp

from

the

device

(T2)

.

After

the

device

sees

the

valid

downstream

port

chirp

sequence

chirp

K-J-K-J-K-J

(T6),

it

will

enter

HS

mode

by

setting

TermSelect

to

HS

mode

(T7)

.

Figure

18

provides

a

state

diagram

for

chirp

K-J-K-J-K-J

validation

.

Prior

to

the

end

of

reset

(T9),

the

upstream

port

must

terminate the

sequence

of

chirp

Ks

and

chirp

Js

(T8)

and

assert

SEO

(T8-T9)

.

Note

that

the

sequence

of

chirp

Ks

and

chirp

Js

constitutes

bus

activity

.

IK

STATE

START

CHIRP

COUNT

)4

K-J-

CHI J = 0

DETECT

K?

DETECTION

K

STATE

INC

CHIRP CHIRP

INVALID

COUNT

/"

IJ

STATE

DETECT

J?

CHIRP

COUNT!

= 6

&

!SEO

-

J

STATE

CHIRP

COUNT!

= 6

& !SEO

SEO

CHIRP

COUNT

=6

INC

CHIRP

COUNT

CHIRP

VALID

1325

(F)

Figure 18

.

Chirp

K-J-K-J-K-J

Sequence

Detection

State

Diagram

The

SIE must

use

LineState

signal

transitions

to

step

through

the

chirp

K-J-K-J-K-J

state

diagram,

where

K

state

is

equivalent

to

LineState

=

K

state

and

J

state

is

equivalent

to

LineState

=

J

state

.

The

SIE

must

employ

a

counter

(chirp

count)

to

count

the

number

of

chirp

K

and

chirp

J

states

.

Note

that

LineState

does

not

filter

the

bus

signals,

so

the

requirement

that

a bus

state

must

be

continuously

asserted

for

2

.5

gs

must be

verified

by

the

SIE

sampling

the

LineState

signals

.

26

Agere

Systems

Inc

.

AdLib OCR Evaluation

Data

Sheet,

Rev

.

3

Agere

Systems

USB

2

.0

UTMI

October

2002

USS2X1

A

8-Bit

and

USS2X1

WA

16-Bit

PHY

Chips

Other

Functions

(continued)

UPSTREAM

PORT

ACTIONS

TO

T3

T4T5 T8 T9

TIME

DEVICE

ACTIONS

T1

T21

I I

T6

T7

i

XCVR

SELECT

i

TERM

SELECT

TXVALID

/I

1\i

i ;

I I i I

'DEVICE'

CHIRP

K

~'K'J'K

J

K

J~

DP/DM

i~-----

A=

M

--!

------------

AMM

UPSTREAM

PORT

CHIRP

DOWNSTREAM

PORT

CHIRPS

HS

MODE

Figure

19

.

HS

Detection

Handshake

Timing

Behavior

(HS

Mode)

Table

11

.

Reset

TimingValues

1326

(F)

Timing

Description

Value

Parameter

TO*

HS

handshake

begins

.

D+

pull-up

enabled,

HS

0

(reference)

terminations

disabled

.

T1

T

Device

asserts

chirp

K

on

the

bus

.

TO

<

T1

<

HS

reset

TO

+

6

.0

ms

{TUCHEND

-

TuCH}

T2

Device

removes

chirp

K

from

the

bus

(1

ms

mini-

TO

+

1

.0

ms

{TUCH}

<

T2

<

HS

reset

TO +

7

.0

ms

mum

width)

.

{TUCHEND}

T3

Downstream

port

asserts

chirp

K

on

the

bus

.

T2

<

T3

<

T2

+ 100

~ts

{TWTDCH}

T4

Downstream

port

toggles

chirp

K

to chirp

J on

the

T3

+ 40

~ts

{TDCHBIT

(min)}

<

T4

<

T3

+ 60

~ts

bus

.

{TDCHBIT

(max)}

T5

Downstream

port

toggles

chirp J to

chirp

K

on

the

T4

+

40 gs

{TDCHBIT

(min)}

<

T5

<

T4

+ 60 gs

bus

.

{TDCHBIT

(max)}

T6

Device

detects

downstream

port

chirp

.

T6

T7

Downstream

port

chirp

detected

by

the

device

.

T6

<

T7

< T6 +

500

gs {TWTHS}

Device

removes

D+

pull-up

and

asserts

HS

ter-

minations,

reverts

to

HS

default

state,

and

waits

for

end

of

reset

.

T8

Terminate

downstream

port chirp

K-J

sequence

T9

- 500 gs

{TDCHSEO

(max)}

<

T8

<

T9

-

(repeating

T4

and

T5)

.

100 gs

{TDCHSEO

(min)}

T9

The

earliest

time

at

which

a

downstream

port

HS

reset

TO

+

10

ms

{TDRST

(min)}

may

end

reset

.

The

latest

time

at

which

the

device

may

remove

the

D+

pull-up,

assert the

HS

terminations

and

revert

to

the

HS

default

state

.

*

TO

may

be up

to

4

ms

after

HS

reset

T0

.

t

Due

to

the

assertion

of

the

HS

termination

on

the

downstream

port

and FS

termination

on

the

upstream

port,

between

T1 and

T7

the

signaling

levels

on

the

bus

are higher

than

HS

signaling

levels

and

are

less

than

FS

signaling

levels

.

$

The

SIE

must

use

LineState

to

detect the

downstream

port

chirp

sequence

.

Agere

Systems

Inc

.

27

AdLib OCR Evaluation

Agere

Systems

USB

2

.0

UTMI

USS2X1

A

8-Bit

and

USS2X1

WA

16-Bit

PHY

Chips

Data

Sheet,

Rev

.

3

October

2002

Other

Functions

(continued)

Suspend

Timing

If

reset

is

entered

from a

suspended

state,

the

internal

oscillator

and

clocks

of

the

transceiver

have

already

been powered

down

.

Figure

20

shows

how

CLKOUT

is

used

to

control

the

duration

of

the

chirp

generated

by

the

device

.

When

reset

is

entered

from

a

suspended

state

(J

to

SEO

transition

reported

by

LineState),

SuspendN

is

combinatorially

negated

at

time

TO

by

the

SIE

.

The

USS2X1

A

oscillator

and PLL

take

several

milliseconds

to

stabilize

.

The

USS2X1

A

will

not

generate

any

transi-

tions of

the

CLKOUT

signal

until

it

is

usable,

where

usable

is

defined

as

stable

to

within

±10%

of

the

nomi-

nal

frequency

and

the

duty

cycle

accuracy

50 ±

5%

.

After

CLKOUT

is

usable,

the

SIE

must

initialize

a

timer

(T1)

and

look

for

SEO

to

be

asserted

for at

least

2

.5

gs

.

If

the

test

is

true (T1

>_

Tfiltse0),

then

start

the

reset

handshake

protocol

.

If

the

test

is

false,

the

latest

time

that

could

successfully

start

the

chirp

sequence

was

exceeded

and

the

SIE

never

sawSEO

for at least

2

.5

gs

(TO

>_

Tuchend

-

Tuch

&

T1

<

Tfiltse0)

.

Then

the

SIE

must

return

to

the

suspend

state

and

assert

SuspendN

.

The

first

transition of

CLKOUT

occurs

at

T1

.

The

SIE

must

assert

a

chirp

K

for

66000

CLKOUT

cycles

to

ensure a

1

ms

minimum

duration

.

If

CLKOUT

is

10%

fast

(66

MHz),

then

chirp

K

will

be

1

.0

ms

.

If

CLKOUT

is

10%

slow

(54

MHz),

then

chirp

K

will

be

1

.2

ms

.

The

5

.8

ms

requirement

for

the

first

CLKOUT

transition

after

SuspendN

ensures

enough

time

to

assert

a

1

ms

chirp

K

and

still

complete

before

T3

.

Once

the

chirp

K

is

completed

(T3),

the

SIE

can

begin

looking

for

down-

stream

chirps

anduse

CLKOUT

to

time

the

process

.

To detect

the

assertion

of

the

downstream

chirp

Ks

and

chirp

Js

for

2

.5

gs

{TFILT},

the

SIE

must

see

the appro-

priate

LineState

signals

asserted

continuously

for

165

CLKOUT

cycles

.

UPSTREAM

PORT

TO

ACTIONS

TIME

I I I I

DEVICE

ACTIONS

i

T1

T2 T3 T4

I I I

i

XCVR

SELECT

i

SUSPENDN

TXVALID

CLKOUT

i

DEVICE

ASSERTED

DP/DM

i

SEO

K

I

SEO

LOOK

FOR

CLOCK

POWERUP

TIME

DOWNSTREAM

UPSTREAM

CHIRPS

PORT

CHIRP

1327

(F)

R

.01

Figure

20

.

HS

Detection

Handshake

Timing

Behaviorfrom

Suspend

28

Agere

Systems

Inc

.

AdLib OCR Evaluation

Data

Sheet,

Rev

.

3

Agere

Systems

USB

2

.0

UTMI

October

2002

USS2X1

A

8-Bit

and

USS2X1

WA

16-Bit

PHY

Chips

Other

Functions

(continued)

Table 12

.

HS

Detection

Handshake

Timing

Values

from

Suspend

Timing

Description

Value

Parameter

TO

While

in

suspend

state

an

SEO

is

detected

on

the

USB

.

0

(HS

reset

TO)

HS

handshake

begins

.

D+

pull-up

enabled,

HS

termina-

tions

disabled,

SuspendN

negated

.

T1

First

transition of

CLKOUT

usable

(frequency

TO

<

T1

<

TO

+

5

.6

ms

accurate

to

±10%,

duty

cycle

accurate

to

50 ±

5%)

.

T2

Device

asserts

chirp

Kon

the

bus

.

T1 <

T2

<TO +

5

.8

ms

T3

Device

removes

chirp

K from

the

bus

(1

ms

minimum

T2

+

1

.0

ms

{TuCH}

<

T3

<

width)

and

begins

looking

for

downstream

chirps

.

TO

+

7

.0

ms

{TUCHEND}

T4

CLKOUT

nominal

(CLKOUT

is

frequency

accurate

to

T1

<

T3

<

TO

+

20

.0

ms

TDRST

±500

ppm,

duty

cycle

accurate

to

50 ±

1

%)

.

(Min)

+

TRSMRCV}

Assertion

of

Resume

In

this

case,

an

event

internal to

the

device

initiates

the

resume

process

.

A

device

with

remote

wake-up

capability

must

wait

for

at

least

5

ms

after

the

bus

is

in

the

idle

state

before

sending

the

remote

wake-up

resume

signaling

.

This

allows the

hubs

to

get

into

their

suspend

state

and

prepare

for

propagating

resume

signaling

.

The

device

has

10

ms

where

it

can

draw

a

nonsuspend

current

before

it

must

drive

resume

signaling

.

At

the

begin-

ning of

this

period,

the

SIE

may

negate

SuspendN,

allowing

the

transceiver,

oscillator,

and

PLL

to

power

up

and

stabilize

.

Figure

21

illustrates

the

behavior

of

a

device

returning

to

HSmode

after

being

suspended

.

At

T4,

a

device

that

was

previously

in

FS

mode

would

maintain

TermSelect

and

XcvrSelect

high

.

To

generate

resume

signaling

(FS

K),

the

USS2X1A

is

placed

in

the

disable

bit

stuffing

and

NRZI

encoding

opera-

tional

mode,

TermSelect

and

XcvrSelect

must

be

in

FS

mode,

TXValid

asserted,

and

all

Os data

is

presented

on

the

DATA

input

bus

for at least

1

ms

(T1-T2)

.

UPSTREAM

PORT

ACTIONS

I I I

TIME T3

I

DEVICE

ACTIONS

TO

T1

T2

i

T4

i

SUSPENDN

XCVR

SELECT

&

TERM

SELECT

TXVALID

DP/DM

FS

IDLE

(J)

K

STATE SEO

FS

MODE

MODEi

Figure

21

.

Resume

Timing

Behavior

(HS

Mode)

1328

(F)

Agere

Systems

Inc

.

29

AdLib OCR Evaluation

Agere

Systems

USB

2

.0

UTMI

USS2X1

A

8-Bit

and

USS2X1

WA

16-Bit

PHY

Chips

Data

Sheet,

Rev

.

3

October

2002

Other

Functions

(continued)

Table

13

.

Suspend

Timing

Values

(HS

Mode)

Timing

Description

Value

Parameter

TO

Internal

device

event

initiating

the

resume

process

.

0

(reference)

T1

Device

asserts

FSK

on

the

bus

to

signal

resume

request

to

TO

<

T1

<

TO

+

10

ms

{TDRSMDN}

downstream

port

.

T2

The

device

releases

FS

K

on

the

bus

;

however,

by

this

time

T1

+

1

.0

ms

{TDRSMUP

(min)}

<

T2

<

the

K

state

is

held

by

downstream

port

.

T1

+

15

ms

{TDRSMUP

(max)}

T3

Downstream

port

asserts

SEO

.

T1

+

20

ms

{TDRSMDN}

T4

Latest time

at

which a

device,

which

was

previously

in

HS

T3

+

1

.33

gs

{two

low-speed

bit

mode,

must

restore

HS

mode

after

bus

activity

stops

.

times}

Detection

of

Resume

signaling

always

takes

place

in

FS

mode

(TermSelect

and

XcvrSelect

=

FS

enabled),

so

the

behavior

for

an

HS

device

is

identical

to that of

an

FS

device

.

The

SIE uses

the

LineState

signals

to

determine

when

the

USB

transitions

from

the

J to

the

K

state

and

finally

to

the

terminating

low-speed

EOP

(SEO

for

1

.25

~ts-1

.5

~ts)

.

The

resume

signaling

(FS

K)

will

be

asserted

for

at least

20

ms

.

At

the

beginning

of this

period,

the

SIE

may

negate

SuspendN,

allowing

the

transceiver,

oscillator,

and

PLL

to

powerup

and

stabilize

.

The

low-speed

EOP

condition

is

relatively

short

.

SIEs

that

simply

look

for

an

SEO

condition

to

exit

suspend

mode

do

not

necessarily

give

the

USS2X1

A's

clock

gen-

erator

enough

time

to

stabilize

.

It

is

recommended

that

all

SIE

implementations

key

off

the J-to-K

transition

for

exiting

suspend

mode

(SuspendN

=

1)

.

And

within

1

.25

~ts

after

the

transition

to

the

SEO

state

(low-speed

EOP),

the

SIE

must

enable

normal

operation,

i

.e

.,

enter

HS

or

FS

mode

depending

on

the

mode

the

device

was

in

when

it

was

suspended

.

If

the

device

was

in

FS

mode,

then

the

SIE

leaves

the

FS

terminations

enabled

.

After

the

SEO

expires,

the

downstream

port

will

assert

a

J state

for

one

low-speed

bit

time,

and

the

bus

will

enter

an

FS

idle

state

(main-

tained

by

the

FS

terminations)

.

If

the

device

was

in

HS

mode,

then

the

SIE

must

switch

to

the

FS

terminations before

the

SEO

expires

(<1 .25

~ts)

.

After

the

SEO

expires,

the

bus

will

then

enter

an

HS

idle

state

(maintained

by

the

HS

terminations)

.

Note

:

Glitches

that

occur

on

the

USB

during

suspend

are

handled

as

follows

.

When

a

device

is

sus-

pended, a

J

state

is

on

the

bus and

the

SIE

should

be

looking

for

a

K

(resume)

or

an

SEO

(reset)

.

In

either

case,

a

glitch

that

looks

like

a

K

or

an

SEO

will

cause

the

USS2X1

A

oscillator

to

start

up

.

The

USS2X1

A

will

hold

off

any

CLKOUT

transitions

until

CLKOUT

is

usable

.

Once

CLK-

OUT

is

running

(several

milliseconds

later),

the

SIE must check

LineState

.

If

a

J

state

is

asserted,

then

the

SIE

returns

to

the

suspend

state

;

if

a

K

state

is

asserted,

then

the

SIE

starts

the

resume

process

;

and

if

SEO

is

asserted,

then

the

SIE

starts

the

reset

process

.

HS

Device Attach

Figure

22

demonstrates

the

timing

of

the

USS2X1

A

control

signals

during

a

device

attach

event

.

When

an

HS

device

is

attached

to

an upstream

port,

power

is

asserted

to

the

device

and

the

device

sets

XcvrSelect

and

TermSelect

to

FS

mode

(time

T1)

.

VBUS

is

the

5

V

power

available

on

the

USB

.

Device

reset

in

Figure

22

indicates

that

VBUS

is

within

normal

operational

range as

defined

in

the

USB

2

.0

specifica-

tion

.

The

assertion

of

device

reset

(TO)

will

initialize

the

device

and

cause

the

SIE

state

machine

to

set the

XcvrSelect

and

TermSelect

signals

to

FS

mode

(T1)

.

Note

that

device

reset

is

not the

same

as

the

USS2X1

A

reset

signal

.

Device

reset

is

an

input

to

the

SIE,

which

in

turn

can use

it

to

assert

reset

to

the

USS2X1

A

.

30

Agere

Systems

Inc

.

AdLib OCR Evaluation

Data

Sheet,

Rev

.

3

Agere

Systems

USB

2

.0

UTMI

October

2002

USS2X1

A

8-Bit

and

USS2X1

WA

16-Bit

PHY

Chips

Other

Functions

(continued)

The

standard

FS

technique

of

using

a

pull-up

on

DP

to

signal

the

attach

of

an

FS

device

is

employed

.

The

SIE

must

then

check

the

LineState

signals

for

SEO

.

If

LineState

=

SEO

is

asserted

at

time

T2,

then

the

upstream

port

is

forcing

the

reset state

to

the device

(i

.e

.,

driven

SEO)

.

The

device

will

then

reset

itself

before

initiating

the

HS

detec-

tion

handshake

protocol

.

UPSTREAM

PORT

ACTIONS

TO T2

TIME

DEVICE

ACTIONS

ii

T1

VBUS

ii

i

ii

DEVICE

RESET

i

XCVR

SELECT

i i

TERM

SELECT

i

DP/DM

i

in

N

IDLE (FS

J)

SEO

HSDETECTION

HANDSHAKE)

Figure

22

.

Device

Attach

Behavior

Table

14

.

Attach

and

Reset

TimingValues

Timing

Description

Value

Parameter

TO

Vbus

valid

.

0

(reference)

T1

Maximum

time from Vbus

valid to

when

the

TO

+

100

ms

{TSIGATT}

<

T1

device

must

signal attach

.

T2 Debounce

interval

.

The

device

now

enters

the

T1

+

100

ms

{TATTDB}

<

T2

(HS

Reset

TO)

HS

detection

handshake

protocol

.

1329

(F)

5-3080.R07

(F)

Agere

Systems

Inc

.

31

AdLib OCR Evaluation

Agere

Systems

USB

2

.0

UTMI

Data

Sheet,

Rev

.

3

USS2X1

A

8-Bit

and

USS2X1

WA

16-Bit

PHY

Chips

October

2002

Other

Functions

(continued)

USB

2

.0

Test

Mode

Generation

The

USB

specification

defines

additional

test

modes

.

These

are

accomplished

with

the following

techniques

:

.

To

force

an

SEO

state

on

the

bus,

the

USS2X1A

is

placed

in

OpMode

0

(normal

operation)

and

no

data

is

trans-

mitted

.

This

results

in

an

HS

idle

mode

on

the

bus,

which

is

SEO

.

It

is

the

responsibility

of

the

SIE

to

validate

any

incoming

packets

and

to

transmit

a

NAK

handshake

packet,

if

the

received

packet

is

correct

.

To

force

a

J

state

on

the

bus,

the

USS2X1A

is

placed

in

OpMode

2

(disable

bit

stuffing

and

NRZI

encoding)

and

all

1s

are

transmitted

by

the

SIE

.

To

force

a

K

state

on

the

bus,

the

USS2X1A

is

placed

in

OpMode

2

(disable

bit

stuffing

and

NRZI

encoding)

and

all

Os

are

transmitted

by

the

SIE

.

To

generate

a

test

packet

on

the

bus,

the

USS2X1

A

is

placed

in

OpMode

0

(normal

operation)

and

all

the

test

packet

data

(as

defined

in

Chapter 7

of

the

USB

2

.0

specification)

is

transmitted

by

the

SIE

.

Table

15

.

USB

2

.0

Test

Mode

to

USS2X1A

Mapping

USB

2

.0

Test

Modes

USS2X1A

Setup

Operational

Mode

Transmitted

Data

XcvrSelect

&

TermSelect

SEO

NAK

Normal

No

transmit

HS

J

Disable

All

1

s

HS

K

Disable

All

Os

HS

Test-Packet

I

Normal

I

Test

packet

data

I

HS

Note

:

The

Test

Force-Enable

mode

described

in

the

USB

2

.0

specification

does

not

apply

to

upstream

facing

ports

.

32

Agere

Systems

Inc

.

AdLib OCR Evaluation

Data

Sheet,

Rev

.

October

2002

Electrical

Characteristics

do

Characteristics

Table

16

.

do

Characteristics

Agere

Systems

USB

2

.0

UTMI

USS2X1A

8-Bit

and

USS2X1

WA

16-Bit

PHY

Parameter

Symbol

Condition

Min

TO

Max

Unit

Supply

VDD

-

3

.135

3

.3

3

.465

V

Power

Voltage

Input

High

Vih

-

2

.0

- -

V

Threshold

Input

Low

Vil

---

0

.8

V

Threshold

Output

High

Voh

i<_

-6mA

2

.4

- -

V

Voltage

Output

Low

Vol

i<_

6mA

- -

0

.4

V

Voltage

Input

Cin

---

2

.0

pF

Capacitance

Bidi

Cbid

---

3

.0

pF

Capacitance

Output

Cout

---

2

.5

pF

Capacitance

Total

Power

PtotA

VDD

=

3

.3 V,

- -

445

mW

Active

25 °C

Total

Power

PtotB

VDD

=

3

.3 V,

- -

10

mW

Suspend

25°C

ac

Characteristics

Table

17

.

ac

Characteristics

Signal

Symbol

Condition

Min

TO

Max

Unit

Notes

All Tri

0

.2VDD-0

.6VDD

-

0

.8

-

ns

Input

rise

time

.

All

Tfi

0

.6VDD-0

.2VDD

-

0

.8

-

ns

Input

fall

time

.

Data

Tro

0

.2VDD-0

.6VDD,

10 pF

-

0

.8

ns Output

rise

time

.

Others

Tro

0

.2VDD-0

.6VDD,

10 pF

-

0

.6

ns Output

rise

time

.

Data

Tfo

0

.2VDD-0

.6VDD,

10 pF

-

0

.8

ns Output

fall

time

.

Others

Tfo

I

0

.6VDD-0

.2VDD,

10 pF

I

-

I

-

I

0

.6

I

ns

I

Output

fall

time

.

Agere

Systems

Inc

.

33

AdLib OCR Evaluation

Agere

Systems

USB

2

.0

UTMI

Data

Sheet,

Rev

.

3

USS2X1

A

8-Bit

and

USS2X1

WA

16-Bit

PHY

Chips

October

2002

Electrical

Characteristics

(continued)

acTiming

(continued)

Table

18

.

ac

Timing

(8-Bit)

Symbol

Signal

Condition

Min

TO

Max

Unit

Notes

Tsu

DATA[15

:0]

3

.135

V,

125 °C

8

- -

ns

Setup

from

signal

TXVALID

10

- -

ns

to

CLKOUT

.

VALIDH

NA

- -

ns

OPMODE[1]

10

- -

ns

OPMODE[0]

11

- -

ns

XCVRSELECT

TBD

- -

ns

TERMSELECT

TBD

- -

ns

SUSPENDN

TBD

- -

ns

Thd

DATA[15

:0]

3

.465

V,

125 °C

0

- -

ns

Hold from

signal

to

TXVALID

0

- -

ns

CLKOUT

.

VALIDH

NA

- -

ns

OPMODE[1]

0

- -

ns

OPMODE[0]

0

- -

ns

XCVRSELECT

0

- -

ns

TERMSELECT

0

- -

ns

SUSPENDN

TBD

- -

ns

Tpd

DATA[15

:0]

10

pF

0

-

4

ns

Prop

delay

from

RXVALID

0

-

3

ns

CLKOUT

to

signal

.

VALIDH

Min

:

3

.135

V,

12

OC

NA

-

NA

ns

RXERROR

5

0

-

5

ns

RXACTIVE Max

:

3

.465

V,

0

-

3

ns

LINESTATE[1

:0]

0

0C

0

-

6

ns

TXREADY

I I

0

I

-

I

11

I

ns

34

Agere

Systems

Inc

.

AdLib OCR Evaluation

Data

Sheet,

Rev

.

3

Agere

Systems

USB

2

.0

UTMI

October

2002

USS2X1

A

8-Bit

and

USS2X1

WA

16-Bit

PHY

Chips

Electrical

Characteristics

(continued)

ac Timing

Table

19

.

ac

Timing

(16-Bit)

Symbol

Signal

Condition

Min

TO

Max

Unit

Notes

Ts

u

DATA[15

:0]

3

.135

V,

125 °C

8

- -

ns

Setup

from

signal

TXVALID

10

- -

ns

to

CLKOUT

.

VALIDH

10

- -

ns

OPMODE[1]

10

- -

ns

OPMODE[0]

11

- -

ns

XCVRSELECT

TBD

- -

ns

TERMSELECT

TBD

- -

ns

SUSPENDN

TBD

- -

ns

Thd

DATA[15

:0]

3

.465

V,

125 °C

0

- -

ns

Hold from

signal

to

TXVALID

0

- -

ns

CLKOUT

.

VALIDH

0

- -

ns

OPMODE[1]

0

- -

ns

OPMODE[0]

0

- -

ns

XCVRSELECT

0

- -

ns

TERMSELECT

0

- -

ns

SUSPENDN

TBD

- -

ns

Tpd

DATA[15

:0]

10

pF

0

-

21 ns

Prop

delay

from

RXVALID

0

-

20

ns

CLKOUT

to

signal

.

VALIDH

Min

:

3

.135

V,

O

0

-

21 ns

RXERROR

125

C

0

-

5

ns

RXACTIVE Max

:

3

.465

V

0

-

18 ns

LINESTATE[1

:0]

,

0

0C

0

-

33

ns

TXREADY

I I

0

I

-

I

27

I

ns

Agere

Systems

Inc

.

35

AdLib OCR Evaluation

Data

Sheet,

Rev

.

3

October

2002

Electrical

Characteristics

(continued)

Timing

Constraints

Agere

Systems

USB

2

.0

UTMI

USS2X1A

8-Bit

and

USS2X1

WA

16-Bit

PHY

The

following

figure

and

Tables

20

and

21 define

the

timing

constraints

for

the

USS2X1A

(8-bit)

and

USS2X1

WA

(16-bit)

devices

.

CLK

CONTROL

If

DATAI

N

CONTROL

Ol

DATAOUT

Notes

:

Tcsu

=

control

signal

setup

time

.

Tosu

= data

signal

setup

time

.

TCH

=

control

signal

hold

time

.

TDH

=

data

signal

hold time

.

Tcco

=

control

signal

clock

to

out

time

.

Toco

=

data

signal

clock

to

out

time

.

Figure

23

.

Timing

Constraints

Table

20

.

Timing

Constraints

for

USS2X1A

(8-Bit)

and

USS2X1

WA

(16-Bit)

for

Control

Out

Signals

Control

-Out

Tcco

(8-bit

Implementation)

Tcco

(16-bit

Implementation)

Unit

Signals

Max

Min

Max

Min

RXActive

3 0 18 0 ns

RXValid

3 0 18 0 ns

RXError 5 0 5 0 ns

RXVaIidH

NA NA

19 0 ns

TXReady

TBD

0

TBD

0 ns

LineState

6 0 6 0 ns

Tdco

(8-bit

Implementation)

Tdco

(16-bit

Implementation)

Max

Min

Max

Min

DataOut

40 19 0

ns

Agere

Systems

Inc

.

36

AdLib OCR Evaluation

Data

Sheet,

Rev

.

3

Agere

Systems

USB

2

.0

UTMI

October

2002

USS2X1

A

8-Bit

and

USS2X1

WA

16-Bit

PHY

Chips

Electrical

Characteristics

(continued)

Timing

Constraints

(continued)

Table

21

.

Timing

Constraints

for

USS2X1A

(8-Bit)

and

USS2X1

WA

(16-Bit)

for

Control_In

Signals

Control

-In

Si

n

l

Setup

and

Hold

(8-bit

Implementation)

Setup

and

Hold

(16-bit

Implementation)

Unit

g a s

Tcsu

(Max)

Tch

(Min)

Tcsu

(Max)

Tch

(Min)

TXValid

10 0 10 0 ns

TXVaIidH

NA NA

10 0 ns

OpMode[1

]

10 0 10 0 ns

OpMode[0]

11

0

11

0 ns

XCVRSELECT

TBD

0

TBD

0 ns

TERMSELECT

TBD

0

TBD

0 ns

Dataln

8080

ns

Agere

Systems

Inc

.

37

AdLib OCR Evaluation

Agere

Systems

USB

2

.0

UTMI

USS2X1

A

8-Bit

and

USS2X1

WA

16-Bit

PHY

Chips

Data

Sheet,

Rev

.

3

October

2002

Outline

Diagrams

48-Pin

TQFP

Dimensions

are

in

millimeters

.

9

.00

±

0

.20

7

.00

±

0

.20

1

.00

REF

PIN #1

4$

r

IDENTIFIER

ZONE

7

0

.25

I

GAGE

PLANE

1~

1

i

I

36

---I

SEATING

PLANE

I

L

0

.45/0

.7

7

.00

±0

.20

DETAIL

A

9

.00

±0

.20

2

25

LJ

LJ LJ LJ LJ LJ LJ LJ LJ

13

24 0

.106/0

.20

DETAIL

A

DETAIL

B

1

.40

0

.05

0

.19/0

.274

±0

.08

O

1

.60

MAX

DETAIL

B

SEATING

PLANE

p

0

.08

0

.50

TYP

~

0

.05/0.15

5-2363.R08

(F)

38

Agere

Systems

Inc

.

AdLib OCR Evaluation

Data

Sheet,

Rev

.

3

October

2002

Outline

Diagrams

(continued)

64-Pin

TQFP

Dimensions

are

in

millimeters

.

12

.00

±

0

.20

10

.00+0

.20

#1

IDENTIFIER

ZONE

64 49

1

Agere

Systems

USB

2

.0

UTMI

USS2X1

A

8-Bit

and

USS2X1

WA

16-Bit

PHY

Chips

1

.00

REF

0

.25

GAGE

PLANE

48

SEATING

PLANE

0

.45/0.75

16

17

DETAIL

A

0

.50

TYP-JIL

10

.00

+0

.20

12

.00

±

0

.20

0

33

32

DETAIL

B

1

.40+0

.05

T

1

.60

MAX

SEATING

PLANE

p

0

.08

0

.05/0.15

0

.106/0

.200

0

.1

9/0

.27

'

0

.08

O

DETAIL

B

5-3080.R07

(F)

DETAIL

A

Ordering

Information

Device

Code

Package

Comcode

USS2X1

A

48-Pin

TQFP

109058537

USS2X1

WA

64-Pin

TQFP

109058545

USS2X1

A

Evaluation

Kit

48-Pin

TQFP

7000259930

USS2X1

WA

Evaluation

Kit

I

64-Pin

TQFP

I

7000260350

Agere

Systems

Inc

.

39

AdLib OCR Evaluation

The USB-IF

logo

is

a trademark

of

the

Universal

Serial

Bus

Implementers Forum,

Inc

.

Intel

is

a

registered

trademark

of

Intel

Corporation

.

For

additional

information,

contact

your

Agere

Systems

Account

Manager

or

the

following

:

INTERNET

:

http

://www

.agere

.com

E-MAIL

:

docmaster@agere

.com

N

.

AMERICA

:

Agere

Systems

Inc

.,

Lehigh

Valley

Central

Campus,

Room

10A-301C,

1110

American

Parkway

NE,

Allentown,

PA

18109-9138

1-800-372-2447,

FAX

610-712-4106

(In

CANADA

:

1-800-553-2448,

FAX

610-712-4106)

ASIA

:

Agere

Systems

Hong

Kong

Ltd

.,

Suites

3201

&

3210-12,

32/17,

Tower

2,

The

Gateway,

Harbour

City,

Kowloon

Tel

.

(852)

3129-2000,

FAX

(852)

3129-2020

CHINA

:

(86)

21-5047-1212

(Shanghai),

(86)

755-25881122

(Shenzhen)

JAPAN

:

(81)

3-5421-1600

(Tokyo),

KOREA

:

(82)

2-767-1850

(Seoul),

SINGAPORE

:

(65)

6778-8833,

TAIWAN

:

(886)

2-2725-5858

(Taipei)

EUROPE

:

Tel

.

(44)

1344

296400

Agere

Systems

Inc

.

reserves

the

right

to

make

changes

to

the

product(s)

or

information

contained

herein

without

notice

.

No

liability is

assumed

as a

result of

their

use

or

application

.

Agere,

Agere Systems, and

the

Agere

logo

are

trademarks

of

Agere

Systems

Inc

.

Copyright

®

2002

Agere

Systems

Inc

.

All

Rights

Reserved

October

2002

DS02-273CMPR-3

(Replaces

DS02-273CMPR-2)

a

8

ere

systems

'

AdLib OCR Evaluation