Enpirion® Power Evaluation Board User Guide
EN5322Q PowrSoC
DESCRIPTION
Thank you for choosing Altera Enpirion power
products!
The EN5322 evaluation board is configured to
provide a 1.2V output at up to 2A from a 2.4 V
to 5.5 V input. The output can be set to 7
different voltages through the three VID output
voltage select pins. It can also be adjusted
from 0.6V to (VIN – 0.2 x ILOAD) through the
external resistor divider option.
The 4 MHz operation allows for the use of tiny
MLCC capacitors. It also enables a very wide
control loop bandwidth providing excellent
transient performance and reduced output
impedance. The internal compensation is
designed for unconditional stability for all
operating conditions. The Power OK signal is
available.
FEATURES
• Input Voltage Range: 2.4 V – 5.5 V
• 7 Output V oltage Options via V ID P ins
• Adjustable Output Voltage via E xternal
Resistor Divider
• 2A Load C urr ent Guaranteed
• Fully As s em bled and Tes ted
Applications
• Area Constrained Applications
• Data Netw orking Applic ations
• Wireless Data Cards
• Embedded/Industrial PC
• Set Top Box/Hom e Gatew ay
• LDO Replacement
• LP uProcessors, DSP, IO, M emory.
EVALUATION BOARD BILL OF MATERIALS
Ref Des
Qty
Description
Manufac turer P/N
C1
1
Ceramic Capacitor, 10 uF, 10 V, X7R, 0805
Murata: GRM21BR71A1 06KE 51L
C2
1
Ceramic Capacitor, 470 pF, 50 V, X7R, 0805
Panasonic: ECJ-2VC1H471J
C3, C4
2
Ceramic Capacitor, 22 uF, 6.3 V, X5R, 0805
Panasonic: ECJ2FB 0J226M
C11
1
Ceramic Capacitor, 1 uF, 6.3 V, X7R, 0603
Panasonic: ECJ1V B0J105K
U1
1
2 A PWM Conver ter
Altera Enpirion: EN5322QI-T
R41
1
Resistor, 2 kOHM, 1%, 1/8 W, 0805
Panasonic: ERJ-6ENF2001V
C82
1
Electrolytic Capacitor, 150 uF, 10 V
Panasonic: EEV FK1A151P
C102
1
Ceramic Capacitor, 10 uF, 10 V, X7R, 0805
Murata: GRM21BR71A1 06KE 51L
D12
1
T VS Unidirect, 600 W, 6.5 V
Littlefuse: SMBJ 6.5A
FB12
1
Multilayer Ferrite Bead, 4000MA, 0805
Wurth: 742792012
J12
1
Connector, Custom, Verti cal Header
Samtec: ASP 12192002
TP5-TP92
5
Connector, T est Point
Keystone: 5016
C5, C6 , C9 , C12
Not Used
R1, R2
Not Used
TP1-TP2
Not Used
Notes:
1. R4 is not required if POK is not used.
2. These components are only for dem ons tr ation purpos es , and are not needed for circuit design.
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Enpirion® Power Evaluation Board User Guide
EN5322Q PowrSoC
EVALUATION BOARD CIRCUIT
Fi gure 1. Custom e r Eval Board Sche m atic
C11
1u
0603
U1
EN5322Q
NC(SW)
1
PGND
2
PGND
3
PVOUT
4
PVOUT
5
PVOUT
6
PVOUT
7
PGND
8
PGND
9
VS2
10
VS1
11
VS0
12
AVIN 16
AGND 15
VFB 14
VSENSE 13
NC(SW) 24
NC(SW) 23
NC(SW) 22
NC(SW) 21
PVIN 20
PVIN 19
ENABLE 18
POK 17
C1 10u
C4 22u
C10
10u
C5 N/U
C6 N/U
FB1
TP2
1
2
TP1
1
2
J1
ASP12192002
1
2
3
5
6
7
9
10
11
13
14
15
17
18
19
PGND
Vout
Vin
Vin PGND
TP5 1
TP6 1
TP7 1
TP81
VS0
ENABLE
VS2
VS1
R1
N/U
R2
N/U
0805 0805
0805
0805
0805
0805
C9
N/U
0805
POK
C2 470p
C3 22u
0805
0805
+
C8
150u
Vin
PGND
Input Protection
D1
SMBJ6V5A
C12 N/U
0805
VOUT
VIN
PGND
POK
TP10
1
TP31
R4
2k
TP9
1
PGND
2
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Enpirion® Power Evaluation Board User Guide
EN5322Q PowerSoC
QUICK START GUIDE
1. P res et P ower Supply to 2.4 V ≤ VIN ≤ 5.5 V.
2. Turn P ower Supply off.
3. P lac e jum per ENABLE at the left pos ition to enable the EN5322. Placing jumper EN A at the
right pos ition w ill dis able the EN5322.
4. P lac e jum per PO K at the left pos ition to c onnec t pull up r es is tor R 4 to VIN. Left the jum per
open if the POK function is not used.
5. P lac e jum pers VS0, VS1, and VS2 ac c ording to the follow ing table to s et the des ir ed output
voltage.
Table 2: V ID Code Setting
VS2 VS1 VS0 Output Voltage
R
R
R
3.3V
R
R
L
2.5V
R
L
R
1.8V
R
L
L
1.5V
L
R
R
1.25V
L
R
L
1.2V
L
L
R
0.8V
L
L
L
External Divider
The output voltage c an als o be s et w ith an external res is tor divider.
Use a 340 kΩ, 1 % resistor for R1. Then the value of the
bottom resistor R2 is given as:
Ω
−
=k
V
R
OUT
6.0
204
2
where VOUT is the output voltage. For example, if the
des ired output voltage is 1 V, R 2 s hould be a 511 kΩ,
1% res is tor.
6. Connect input power supply term inals to +VIN (TP8)
and GND (TP5).
7. Connect load ter m inals to +VOUT (TP7) and GND (TP6).
8. Turn on the P ower Supply after m aking c onnec tions .
9. The EN5322 w ill be enabled. The PO K output c an be
observed at TP9. To observe noise-sensitive waveforms
on input / output ripple and NC( SW), use the measurement
technique as shown in Figure 5. Wrap bus wire around
the GND portion of the bar e probe and br ing it c los e to
the probe tip. Then s older the bus w ire to the near es t
G ND on the board.
Figure 5: Balanced
Im pedanc e Sc ope Pr obe
for Nois e Measurements
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Enpirion® Power Evaluation Board User Guide
EN5322Q PowerSoC
Contact Information
Altera Corporation
101 Innovation Drive
San Jos e, CA 95134
Phone: 408-544-7000
www.altera.com
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