INTEGRATED CIRCUITS DATA SHEET SAA4997H VErtical Reconstruction IC (VERIC) for PALplus Preliminary specification File under Integrated Circuits, IC02 1996 Oct 24 Philips Semiconductors Preliminary specification VErtical Reconstruction IC (VERIC) for PALplus SAA4997H FEATURES GENERAL DESCRIPTION * PALplus decoding The VErtical Reconstruction IC (VERIC) for PALplus (VERIC) is especially designed for use in conjunction with the Motion Adaptive Colour Plus And Control IC (MACPACIC) to decode the transmitted PALplus video signal in PALplus colour TV receivers. It provides the full vertical resolution of a PALplus picture from the letter box part and the decoded helper information. * Vertical reconstruction * Quadrature mirror filter * Luminance and chrominance processing * Controlling. QUICK REFERENCE DATA SYMBOL PARAMETER MIN. MAX. UNIT VDD supply voltage - 5.25 V Tamb operating ambient temperature 0 70 C ORDERING INFORMATION TYPE NUMBER PACKAGE NAME DESCRIPTION VERSION SAA4997H QFP64 plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm SOT319-2 1996 Oct 24 2 1996 Oct 24 3 17 19 4 8 8 8 PIXEL COUNTER DECODER LINE COUNTER DECODER PIXEL SELECT FILM 21 multi-PIP bypass F/C 22 4 8 8 5 F/C TDI 28 TCK 26 TMS 27 BOUNDARY SCAN TEST UV FORMATTER SAA4997H multi-PIP bypass CHROMINANCE PROCESSING (LP-FILTER) mode select 36 CLK_32B3 30 29 40 55 39 56 54 MGE443 4 8 TRSTN TDO_VE RE_FM3 RE_FM2 OE_FM3 OE_FM2 RSTR_FM23 U/V_VE_0/1 Y_VE_0 to 7 VErtical Reconstruction IC (VERIC) for PALplus Fig.1 Block diagram. EVEN_FIELD INTPOL 20 FM-control UV-control UV REFORMATTER Y - UV - FM CONTROL LOGIC Y-control PIXEL SELECT DELAY COMPENSATOR LUMINANCE PROCESSING (QM-FILTER) handbook, full pagewidth HREF_MA VA_AI U/V_FM23_0/1 Y_FM23_0 to 7 23 CLK_16B2 Philips Semiconductors Preliminary specification SAA4997H BLOCK DIAGRAMS 1996 Oct 24 CLK_32 CLK_16 VSS1-5 VDD1-5 4 3 4 U_FM4_0,1 V_FM4_0,1 FM4 TMS4C2970 4 U_TO_FM4_0,1 V_TO_FM4_0,1 - SNERT interface - Sync generation 2 CLK_16B1 TDO_MA INTPOL EVEN_FIELD FILM HREF_MA WE_MA VA_AI WE_FM4, RE_FM4 WE_FM1, RE_FM1 RST_FM14 WE_FM3 V_TO_FM1_1(1) RSTW_FM23 V_TO_FM1_0(1) FILM VA_AI HREF_MA CLK_32B3 CLK_16B2 VDD1-4 VSS1-4 4 8 4 8 NC TEST1-3 TCK TDI TMS TRSTN EVEN_FIELD INTPOL CLK_32B3 FM3 TMS4C2970 FM2 TMS4C2970 CLK_32B1 11 3 4 4 4 8 MGE444 - FM2/FM3 read control - Vertical chrominance SRC - Inverse QMF reconstruction filter U_VE_0,1 V_VE_0,1 Y_VE_0 to 7 U_FM23_0,1 V_FM23_0,1 Y_FM23_0 to 7 VERIC Vertical Reconstruction IC 4 8 RSTR_FM23 RE_FM3 OE_FM2 OE_FM3 RE_FM2 TDO_VE U_VE_[0,1] V_VE_[0,1] Y_VE_[0 to 7] Fig.2 Block diagram of the PALplus decoder module. VErtical Reconstruction IC (VERIC) for PALplus (1) In case of stand alone MACPACIC the output signals are U_TO_FM1_1, V_TO_FM1_0 or V_TO_FM1_1; otherwise the output signals are WE_FM2, RSTW_FM23 or WE_FM3. (2) VERIC available: VERIC_AV_N is connected to VSS. VERIC_AV_N(2) TEST1-3 TMS TCK TDI TRSTN SNERT_RST - Clock generation - PALplus control SNERT_DA - Motion adaptive luminance/chrominance separation - BB-decompanding - Memory control SNERT_CL Y_TO_FM1_0 to 7 4 8 4 WE_FM2 U_TO_FM1_1(1) 2 8 4 8 U_TO_FM1_0 U_MA_0,1 V_MA_0,1 Y_MA_0 to 7 8 CLK_32B1, 2, 3 CLK_16B1, 2, 3 5 U_ADC_0,1 V_ADC_0,1 U_FM1_0,1 V_FM1_0,1 Y_FM1_0 to 7 3 3 5 4 8 MACPACIC Y_ADC_0 to 7 CLAMP VA_FRONT WE_FRONT 4 CLK_16B1 SRCK FM1 SWCK CLK_16 U_FRONT[0,1] V_FRONT[0,1] 8 ook, full pagewidth TMS4C2970 Y_FRONT[0 to 7] Motion Adaptive Colour Plus and Control IC Philips Semiconductors Preliminary specification SAA4997H Philips Semiconductors Preliminary specification VErtical Reconstruction IC (VERIC) for PALplus SAA4997H PINNING SYMBOL PIN TYPE DESCRIPTION Y_VE_1 1 output luminance output data bit 1 Y_VE_0 2 output luminance output data bit 0 U_VE_1 3 output chrominance output data bit 1 U-component U_VE_0 4 output chrominance output data bit 0 U-component V_VE_1 5 output chrominance output data bit 1 V-component V_VE_0 6 output chrominance output data bit 0 V-component VSS1 7 input ground 1 VDD1 8 input positive supply voltage 1 (+5 V) n.c. 9 - not connected n.c. 10 - not connected n.c. 11 - not connected n.c. 12 - not connected n.c. 13 - not connected n.c. 14 - not connected n.c. 15 - not connected n.c. 16 - not connected HREF_MA 17 input horizontal reference n.c. 18 - not connected VA_AI 19 input vertical reference pulse related to output data INTPOL 20 input INTPOL = 1: PALplus interpolation active FILM 21 input FILM = 0: CAMERA mode INTPOL = 0: VERIC switched to bypass mode (standard signal) FILM = 1: FILM mode EVEN_FIELD 22 input EVEN_FIELD = 0: odd field related to MACPACIC input data EVEN_FIELD = 1: even field related to MACPACIC input data CLK_16B2 23 input buffered clock input (16 MHz) VSS2 24 input ground 2 VDD2 25 input positive supply voltage 2 (+5 V) TCK 26 input boundary scan test clock input TMS 27 input boundary scan test mode select input TDI 28 input boundary scan test data input TDO_VE 29 output boundary scan test data output TRSTN 30 input boundary scan test reset input n.c. 31 - not connected n.c. 32 - not connected TEST1 33 tbf test pins TEST2 34 tbf TEST3 35 tbf CLK_32B3 36 input buffered clock input (32 MHz) VSS3 37 input ground 3 1996 Oct 24 5 Philips Semiconductors Preliminary specification VErtical Reconstruction IC (VERIC) for PALplus SYMBOL PIN TYPE SAA4997H DESCRIPTION VDD3 38 input positive supply voltage 3 (+5 V) OE_FM3 39 output output enable field memory 3 RE_FM3 40 output read enable field memory 3 V_FM23_1 41 input chrominance input data bit 1 V-component V_FM23_0 42 input chrominance input data bit 0 V-component U_FM23_1 43 input chrominance input data bit 1 U-component U_FM23_0 44 input chrominance input data bit 0 U-component Y_FM23_7 45 input Y input data bit 7 Y_FM23_6 46 input Y input data bit 6 Y_FM23_5 47 input Y input data bit 5 Y_FM23_4 48 input Y input data bit 4 Y_FM23_3 49 input Y input data bit 3 n.c. 50 - not connected Y_FM23_2 51 input Y input data bit 2 Y_FM23_1 52 input Y input data bit 1 Y_FM23_0 53 input Y input data bit 0 RSTR_FM23 54 output reset read field memory 2 and 3 RE_FM2 55 output read enable field memory 2 OE_FM2 56 output output enable field memory 2 VDD4 57 input positive supply voltage 4 (+5 V) VSS4 58 input ground 4 Y_VE_7 59 output luminance output data bit 7 Y_VE_6 60 output luminance output data bit 6 Y_VE_5 61 output luminance output data bit 5 Y_VE_4 62 output luminance output data bit 4 Y_VE_3 63 output luminance output data bit 3 Y_VE_2 64 output luminance output data bit 2 1996 Oct 24 6 Philips Semiconductors Preliminary specification VErtical Reconstruction IC (VERIC) for PALplus 52 Y_FM23_1 Y_VE_1 1 51 Y_FM23_2 Y_VE_0 2 50 n.c. U_VE_1 3 49 Y_FM23_3 U_VE_0 4 48 Y_FM23_4 V_VE_1 5 47 Y_FM23_5 V_VE_0 6 46 Y_FM23_6 VSS1 7 45 Y_FM23_7 VDD1 8 44 U_FM23_0 n.c. 9 43 U_FM23_1 n.c. 10 42 V_FM23_0 n.c. 11 41 V_FM23_1 n.c. 12 40 RE_FM3 n.c. 13 39 OE_FM3 n.c. 14 38 VDD3 n.c. 15 37 VSS3 n.c 16 36 CLK_32B3 HREF_MA 17 35 TEST3 n.c. 18 34 TEST2 VA_AI 19 33 TEST1 7 n.c. 32 n.c. 31 TRSTN 30 TDO_VE 29 TDI 28 TMS 27 TCK 26 VDD2 25 VSS2 24 CLK_16B2 23 EVEN_FIELD 22 FILM 21 INTPOL 20 SAA4997H Fig.3 Pin configuration. 1996 Oct 24 53 Y_FM23_0 55 RE_FM2 56 OE_FM2 57 VDD4 58 VSS4 59 Y_VE_7 60 Y_VE_6 61 Y_VE_5 62 Y_VE_4 63 Y_VE_3 64 Y_VE_2 handbook, full pagewidth 54 RSTR_FM23 SAA4997H MGE442 Philips Semiconductors Preliminary specification VErtical Reconstruction IC (VERIC) for PALplus SAA4997H The luminance vertical conversion process in the decoder is complementary to that of the encoder. FUNCTIONAL DESCRIPTION Introduction In the decoder the inverse QMF function is implemented to recombine the two separated sub-bands and to generate the original video signal with 576 active lines per frame. As shown in Fig.2 the PALplus module consists of two special integrated circuits: * Motion Adaptive Colour Plus And Control IC (MACPACIC) Each output line is calculated from up to seven input lines stored in line memories containing main or helper information. The various lines are multiplied by switched coefficients, changing every line within a sequence of four lines, depending on the specific mode (CAMERA or FILM). * VErtical Reconstruction IC (VERIC) and four field memories TMS4C2970. The MACPACIC and the VERIC are intended to generate digitally decoded 50 Hz YUV signals. The MACPACIC performs the decompanding function for the helper lines and the motion adaptive luminance/chrominance separation. Furthermore, PALplus system controlling, memory controlling and clock generation are carried out in this circuit. In case of standard PAL reception, the VERIC is switched to bypass mode controlled by the signal INTPOL. For multi-PIP processing the VERIC is also switched to bypass mode, but controlling of FM2/3 is different (see Fig.6). The total signal delay between the MACPACIC input and the VERIC output is one line for this mode. FM2/3 are driven with 32 MHz clock frequency. The non-multiplexed input data are clocked out with 16 MHz. The function of the VERIC is to reconstruct the separated 2 x 72 helper lines and the 430 main lines into a standard 576 lines frame according the PALplus system description "REV 2.0". Chrominance is converted from 430 lines to 576 lines using a vertical sample rate converter. Chrominance processing The data of the VERIC are clocked out with 16 MHz. The Y : U : V bandwidth ratio is 4 : 1 : 1. The chrominance processing is carried out by the vertical interpolation filter (poly phase filter). The functional block diagram of the VERIC is shown in Fig.1. The device consists of 3 main parts: In CAMERA and FILM mode, intra-field vertical sample rate conversion is carried out. * Luminance processing One output line is calculated out of three or four lines in CAMERA or FILM mode using different coefficients or passed through in bypass mode. * Chrominance processing * Controlling. The input data are delivered by the field memories FM2 and FM3, which include multiplexed first and second field data processed by the MACPACIC. The luminance and chrominance input data of the VERIC are clocked with 32 MHz (CLK_32B3). Internally the device operates at 32 or 16 MHz clock frequency. Control functions The VERIC controller generates the necessary internal control signals for the line memories, formatters, reformatters, the selector signals for the multiplexers and the read signals for the field memories FM2/3. The system control input signals EVEN_FIELD, INTPOL and FILM are derived from the control part of the MACPACIC. The field selection information EVEN_FIELD is related to the input data of the MACPACIC and is adapted in the VERIC to its input data. Luminance processing In the PALplus encoder the luminance signal is separated vertically into two sub-bands by a special Quadrature Mirror Filter (QMF). The control functions are described in Tables 1 and 2. A vertical low-pass sub-band consists of the 430 main letter box lines per frame, and a vertical high-pass sub-band includes the 144 helper lines per frame. Table 1 EVEN_FIELD VALUE The used QMF technique has two advantages: STATUS * Essentially loss-free data processing EVEN_FIELD = 1 even field selected * Cancellation of alias components in the main and helper signal in the decoder. EVEN_FIELD = 0 odd field selected 1996 Oct 24 8 Philips Semiconductors Preliminary specification VErtical Reconstruction IC (VERIC) for PALplus Table 2 INTPOL and FILM VALUE SAA4997H Table 3 STATUS Delays MODE INTPOL = 0 FILM = 0 bypass mode; standard signals FILM mode INTPOL = 1 FILM = 0 interpolation active; PALplus CAMERA mode CAMERA mode INTPOL = 0 FILM = 1 bypass mode; multi-PIP INTPOL = 1 FILM = 1 interpolation active; PALplus FILM mode FIELD VERIC I/O DELAY first 2 lines second 3 lines first 3 lines second 4 lines Input/Output formats INPUT FORMATS Modes and delays The luminance input range of the main and helper signal has the following values: The PALplus module can operate in two different hardware configurations: Main signal: black = 16, white = 191 (straight binary) * Full PALplus configuration (MACPACIC and VERIC) Helper signal: 70, mid = 128 (straight binary) * Stand alone MACPACIC. Chrominance format: 90, mid = 0 (two's complement). The vertical interpolation of the VERIC can be activated by the signal INTPOL depending on the PALplus signalling bits, transmitted in line 23 indicating the type of signal being received. OUTPUT FORMATS Luminance format: black = 16, white = 191 (straight binary) Blanking: code 16 However, the delay between input data of the MACPACIC and output data of the VERIC always has to be 1.5 fields. This is achieved with a suitable read timing of the field memories FM2 and FM3 controlled by VA_AI which is derived from the field length measurement in the MACPACIC. Chrominance format: 90, mid = 0 (two's complement) Blanking: code 0. Test activities The pins TEST1, TEST2 and TEST3 are provided to perform the IC test activities, such as scan test. In case of INTPOL = LOW and additionally FILM = HIGH (FILM mode), the VERIC is switched to multi-PIP mode. In case the delay between input of the MACPACIC and output of the VERIC is one line (1024 CLK_16 periods). The pins TRSTN, TDI, TMS, TCK and TDO_VE are intended for a boundary scan test. The line and pixel timings of the VERIC are shown in Figures 5 to 14. 1996 Oct 24 9 Philips Semiconductors Preliminary specification VErtical Reconstruction IC (VERIC) for PALplus SAA4997H DC CHARACTERISTICS Tj = 0 to 125 C SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Supply VDD supply voltage 4.75 5.0 5.25 V IDD supply current VDD = 5 V - - 80 mA IDD(q) quiescent supply current all inputs to VDD or VSS - - 100 A Inputs VIL LOW level input voltage -0.5 - +0.8 V VIH HIGH level input voltage 2.0 - VDD V ILI input leakage current - - 1.0 A - Outputs VOL LOW level output voltage IO = 20 A - 0.1 V VOH HIGH level output voltage IO = 20 A VDD - 0.1 - - V IOL LOW level output current VO = 0.5 V 4.0 - - mA IOH HIGH level output current VO = VDD - 0.5 V 4.0 - - mA AC CHARACTERISTICS Tj = 0 to 125 C SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT Clock timing CLK_32B3 (see Fig.4) TCY(32) cycle time 28.1 31.25 - ns tH HIGH time 9.2 - - ns tL LOW time 9.2 - - ns tr rise time 2.0 - 4.0 ns tf fall time 2.0 - 4.0 ns fclk deviation of clock frequency -10 - +10 % Clock timing CLK_16B2 (see Fig.4) TCY(16) cycle time 56.2 - - ns tH HIGH time 20.5 - - ns tL LOW time 20.5 - - ns tr rise time 2.0 - 4.0 ns tf fall time 4.0 - 4.0 ns duty cycle 40 - 50 % 1996 Oct 24 tH = ---tL 10 Philips Semiconductors Preliminary specification VErtical Reconstruction IC (VERIC) for PALplus SYMBOL PARAMETER SAA4997H CONDITIONS MIN. TYP. MAX. UNIT Input data timing (CLK_32) tsu th(i) input data set-up time CLK_16B2 -4.7 - - ns Y and UV_FM23 -0.8 - - ns CLK_16B2 5.1 - - ns Y and UV_FM23 5.2 - - ns input data hold time Input control timing (CLK_16B2) HREF_MA, VA_AI, FILM, EVEN_FIELD AND INTPOL tsu input data set-up time 4.5 - - ns th(i) input data hold time 0.1 - - ns Output data timing (CLK_16B2) Y AND UV_FM23 th(o) output data hold time CL = 15 pF 8 - - ns td(o) output data delay time CL = 15 pF - - 27 ns Output control timing (CLK_32B3) OE_FM2, OE_FM3, RE_FM2, RE_FM3 AND RSTR_FM23 th(o) output data hold time CL = 15 pF 5 - - ns td(o) output data delay time CL = 15 pF - - 20 ns Delays tw(HREF) HREF_MA pulse width - 60 x TCY(16) - ns td(RE) delay RE_FM2/3 to HREF_MA - 127 x TCY(32) - ns tw(RE) RE_FM2/3 pulse width - 1680 x TCY(32) - ns td(VE)(MA) delay HREF_MA to YUV_VE - 80 x TCY(16) - ns td(VE) delay data input to output - 16 x TCY(16) - ns td(VE) delay data input to output multi-PIP - 2 x TCY(16) - ns td(RSTR) delay RSTR multi-PIP - 2016 x TCY(32) - ns td(FM2) delay FM2 input to output multi-PIP - 2040 x TCY(32) - ns 1996 Oct 24 11 Philips Semiconductors Preliminary specification VErtical Reconstruction IC (VERIC) for PALplus SAA4997H TIMING tr handbook, full pagewidth CLK tf 90% 50% 10% tH DATA/CONTROL tL XX Dn D(n+1) th(i) th(o) td(o) tsu MGE445 Data input: CLK = CLK_32B3 Data output: CLK = CLK_16B2 Control input: CLK = CLK_16B2 Control output: CLK = CLK_32B3 Fig.4 Data/control input/output set-up and hold timing. 1996 Oct 24 12 1996 Oct 24 13 Y(U/V)_VE Y(U/V)_FM23 RE_FM2/3 HREF_MA CLK_16B2 CLK_32B3 td(RE) tw(HREF) td(VE)(MA) handbook, full pagewidth Fig.5 Pixel timing (except multi-PIP mode). td(VE) 1 x TCY(32) tw(RE) MGE446 Philips Semiconductors Preliminary specification VErtical Reconstruction IC (VERIC) for PALplus SAA4997H 1996 Oct 24 14 1 2 td(MA) td(RSTW) 1 2 2 3 1024 pixels td(FM2) 3 handbook, full pagewidth 1 2 td(VE) 1 2 3 Fig.6 Pixel timing multi-PIP mode (MACPACIC input to VERIC output). 1 3 td(RSTR) 1 3 2 3 MGE447 VErtical Reconstruction IC (VERIC) for PALplus WE_FM2 and RE_FM2 are constant HIGH; YUV_MA = MACPACIC input. YUV_VE YUV_FM2 YUV_MA YUV_ADC RSTR_FM2 RSTW_FM2 VA_AI CLK_32B3 CLK_16B2 Philips Semiconductors Preliminary specification SAA4997H 1996 Oct 24 input signal Y4A Y4B Y5A Y5B Y6A Y6B Y7A Y7B Y8A Y8B 15 bit field word V60A Fig.7 Input data timing (except multi-PIP mode). V60A V40A V20A V00A V60B V40B V20B V00B V64A V44A V24A V04A V64B V44B V24B V04B V68A V48A Y3B V_FM23_0 Y3A V70A V50A V30A V10A V70B V50B V30B V10B V74A V54A V34A V14A V74B V54B V34B V14B V78A V58A Y2B V_FM23_1 Y2A U60A U40A U20A U00A U60B U40B U20B U00B U64A U44A U24A U04A U64B U44B U24B U04B U68A U48A Y1B U_FM23_0 Y1A U70A U50A U30A U10A U70B U50B U30B U10B U74A U54A U34A U14A U74B U54B U34B U14B U78A U58A Y0B U_FM23_1 Y0A handbook, full pagewidth Y_FM23(0-7) RE_FM2/3 CLK_32B3 MGE448 V0 836B V1 836B U0 836B U1 836B Y839 B Philips Semiconductors Preliminary specification VErtical Reconstruction IC (VERIC) for PALplus SAA4997H 1996 Oct 24 16 input signal V60 word 0 0 V_VE_1 V_VE_0 bit 0 0 U_VE_1 U_VE_0 16 V60 V70 U60 U70 Y0 V40 V50 U40 U50 Y1 V20 V30 U20 U30 Y2 V00 V10 U00 U10 Y3 V44 V54 U44 U54 Y5 V24 V34 U24 U34 Y6 V04 V14 U04 U14 Y7 V68 V78 U68 U78 Y8 Fig.8 Output data timing. V64 V74 U64 U74 Y4 handbook, full pagewidth Y_VE(0-7) CLK_16B2 0 0 0 V1 836 V0 836 0 U1 836 U0 836 16 Y 839 MGE449 Philips Semiconductors Preliminary specification VErtical Reconstruction IC (VERIC) for PALplus SAA4997H 1996 Oct 24 17 Y/UV_VE RE_FM3 OE_FM3 RE_FM2 146 lines 21 21/333 22 24 25 26 27 166 167 166/478 167/479 145 lines 311 311/623 MGE450 VErtical Reconstruction IC (VERIC) for PALplus Fig.9 Line read timing FM2/3 bypass mode standard signal, first field. 23 multiplexed active lines from FM23 handbook, full pagewidth OE_FM2 YUV_FM23(0-7) VA_AI 20 lines Philips Semiconductors Preliminary specification SAA4997H 1996 Oct 24 18 Y/UV_VE RE_FM3 OE_FM3 RE_FM2 146 lines 333 21/333 335 336 337 338 339 478 479 166/478 167/479 145 lines 623 311/623 MGE451 VErtical Reconstruction IC (VERIC) for PALplus Fig.10 Line read timing FM2/3 bypass mode standard signal, second field. 334 multiplexed active lines from FM23 handbook, full pagewidth OE_FM2 YUV_FM23(0-7) VA_AI 19 lines field B Philips Semiconductors Preliminary specification SAA4997H 1996 Oct 24 UV3,2 U/V_FM23 19 H1,2 22 M7,6 24 M9,8 25 23 24 25 UV5,4 UV7,6 UV9,8 M5,4 23 27 UV11,10 M11,10 27 161 161 162 162 163 163 164 164 165 165 166 166 167 167 302 302 Fig.11 Line read timing FM2/3 CAMERA mode, first field. 26 H3,4 26 303 303 304 304 305 305 306 306 307 307 308 308 309 309 MGE452 310 310 VErtical Reconstruction IC (VERIC) for PALplus (1) M = main line and H = helper line. Y/UV_VE RE_FM2 OE_FM2 RE_FM3 OE_FM3 M3,2 21 full pagewidth Y_FM23 (1) VERIC line counter Philips Semiconductors Preliminary specification SAA4997H 1996 Oct 24 20 H1,2 22 24 336 7,6 337 9,8 338 11,12 M11,10 25 339 H3,4 26 476 160 477 478 479 161 162 163 480 481 164 165 482 166 614 615 616 301 302 303 Fig.12 Line read timing FM2/3 CAMERA mode, second field. M7,6 M9,8 23 617 618 304 305 619 620 621 622 MGE453 623 306 307 308 309 310 VErtical Reconstruction IC (VERIC) for PALplus (1) M = main line and H = helper line. Y/UV_VE RE_FM2 OE_FM2 RE_FM3 OE_FM3 5,4 3,2 U/V_FM23(0-1) 21 M3,2 M5,4 20 handbook, full pagewidth Y_FM23(0-7) (1) VERIC line counter Philips Semiconductors Preliminary specification SAA4997H 1996 Oct 24 UV3,2 U/V_FM23 21 M7,6 M9,8 24 25 26 27 H3,4 28 UV11,10 M11,10 162 163 164 165 166 167 168 Fig.13 Line read timing FM2/3 FILM mode, first field. UV5,4 UV7,6 UV9,8 M5,4 303 304 305 306 307 308 309 310 MGE454 VErtical Reconstruction IC (VERIC) for PALplus (1) M = main line and H = helper line. 23 H1,2 handbook, full pagewidth Y/UV_VE RE_FM2 OE_FM2 RE_FM3 OE_FM3 M3,2 Y_FM23 (1) Philips Semiconductors Preliminary specification SAA4997H 1996 Oct 24 22 H1,2 336 M5,4 337 M7,6 338 M9,8 340 M11,10 474 475 476 477 478 479 480 615 Fig.14 Line read timing FM2/3 FILM mode, second field. 339 H3,4 616 617 618 619 620 621 622 623 MGE455 VErtical Reconstruction IC (VERIC) for PALplus (1) M = main line and H = helper line. M3,2 handbook, full pagewidth Y/UV_VE RE_FM2 OE_FM2 RE_FM3 OE_FM3 Y_FM23(0-7) (1) Philips Semiconductors Preliminary specification SAA4997H Philips Semiconductors Preliminary specification VErtical Reconstruction IC (VERIC) for PALplus SAA4997H PACKAGE OUTLINE QFP64: plastic quad flat package; 64 leads (lead length 1.95 mm); body 14 x 20 x 2.8 mm SOT319-2 c y X 51 A 33 52 32 ZE Q e E HE A A2 (A 3) A1 wM pin 1 index Lp bp L 20 64 detail X 19 1 ZD w M bp e v M A D B HD v M B 0 5 10 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HD HE L Lp Q v w y mm 3.20 0.25 0.05 2.90 2.65 0.25 0.50 0.35 0.25 0.14 20.1 19.9 14.1 13.9 1 24.2 23.6 18.2 17.6 1.95 1.0 0.6 1.4 1.2 0.2 0.2 0.1 Z D (1) Z E (1) 1.2 0.8 1.2 0.8 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION REFERENCES IEC JEDEC EIAJ ISSUE DATE 92-11-17 95-02-04 SOT319-2 1996 Oct 24 EUROPEAN PROJECTION 23 o 7 0o Philips Semiconductors Preliminary specification VErtical Reconstruction IC (VERIC) for PALplus If wave soldering cannot be avoided, the following conditions must be observed: SOLDERING Introduction * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. * The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. Even with these conditions, do not consider wave soldering the following packages: QFP52 (SOT379-1), QFP100 (SOT317-1), QFP100 (SOT317-2), QFP100 (SOT382-1) or QFP160 (SOT322-1). This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Reflow soldering Reflow soldering techniques are suitable for all QFP packages. The choice of heating method may be influenced by larger plastic QFP packages (44 leads, or more). If infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. For more information, refer to the Drypack chapter in our "Quality Reference Handbook" (order code 9398 510 63011). Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. Several techniques exist for reflowing; for example, thermal conduction by heated belt. Dwell times vary between 50 and 300 seconds depending on heating method. Typical reflow temperatures range from 215 to 250 C. Preheating is necessary to dry the paste and evaporate the binding agent. Preheating duration: 45 minutes at 45 C. Wave soldering Wave soldering is not recommended for QFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. 1996 Oct 24 SAA4997H 24 Philips Semiconductors Preliminary specification VErtical Reconstruction IC (VERIC) for PALplus SAA4997H DEFINITIONS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. 1996 Oct 24 25 Philips Semiconductors Preliminary specification VErtical Reconstruction IC (VERIC) for PALplus NOTES 1996 Oct 24 26 SAA4997H Philips Semiconductors Preliminary specification VErtical Reconstruction IC (VERIC) for PALplus NOTES 1996 Oct 24 27 SAA4997H Philips Semiconductors - a worldwide company Argentina: see South America Australia: 34 Waterloo Road, NORTH RYDE, NSW 2113, Tel. +61 2 9805 4455, Fax. +61 2 9805 4466 Austria: Computerstr. 6, A-1101 WIEN, P.O. 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No. 5, 80640 GULTEPE/ISTANBUL, Tel. +90 212 279 2770, Fax. +90 212 282 6707 Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7, 252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461 United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes, MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421 United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409, Tel. +1 800 234 7381 Uruguay: see South America Vietnam: see Singapore Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD, Tel. +381 11 625 344, Fax.+381 11 635 777 For all other countries apply to: Philips Semiconductors, Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 Internet: http://www.semiconductors.philips.com (c) Philips Electronics N.V. 1996 SCA52 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Printed in The Netherlands 537021/1200/01/pp28 Date of release: 1996 Oct 24 Document order number: 9397 750 01423