Pb Py fo | ACT-F512K8 High Speed 4 Megabit Monolithic FLASH (\EROFLEX CIRCUIT TECHNOLOGY www.aeroflex.com Features m= Low Power Monolithic 512K x 8 FLASH = Industry Standard Pinouts = TIL Compatible Inputs and CMOS Outputs sm Packaging Hermetic Ceramic : e@ 32 Lead, 1.6 x .6 x .20 Dual-in-line Package (DIP), m Access Times of 60, 70, 90, 120 and 150ns poet cciet mA" ge (DIP) m +5V Programing, 5V +10% Supply @ 32 Lead, .82" x .41" x .11" Ceramic Flat Package (FP), Aeroflex code# "F6" m 100,000 Erase / Program Cycles e 32 Lead, .82" x .41" x .132" Ceramic Flat Package = Low Standby Current (FP Lead Formed), Aeroflex code#"F7" m Page Program Operation and Internal m= Sector Architecture : e & Equal size sectors of 64K bytes each Program Control Time Any Combination of Sectors cean be erased with one = Supports Full Chip Erase command sequence. m Embedded Erase and Program Algorithms & Commercial, Industrial and Military = Supports Full Chip Erase Temperature Ranges m= MIL-PRF-38534 Compliant Circuits Available " DESC SMD Pending 5962-96692 (P4,F6,F7) Block Diagram DIP (P4) & Flat Packages (F6,F7) General Description __ CE The ACT-F512K8 is a high SE | speed, 4 megabit CMOS Ao-At8-_, | monolithic Flash module 1 designed for full temperature Vss 512Kx8 range military, space, or high Veo 1 * reliability applications. This device is input TTL and output CMOS compatible. The command register is written by V00-7 bringing WE to a logic low level Pin Description (ViL), while CE is low and OE is 1/O0-7 Data I/O at logic high level (VIH). Reading is accomplished by chip Enable (CE) and Output Enable (OE) being logically active, see Ao-18 | Address Inputs WE | Write Enable CE | Chip Enable Figure 9. Access time grades of OE | Output Enable 60ns, 7Ons, 9Ons, 120ns and Vcc | Power Supply 150ns maximum are standard. Vss Ground The ACT-F51 2K8 is NC | Not Connected available in a choice of A\eroflex Circuit Technology - Advanced Multichip Modules SCD1668 REV A 4/28/98General Description, Cont'd. hermetically sealed ceramic packages; a 32 lead .82" x .41" x .11" flat package in both formed or unformed leads or a 32 pin 1.6"x.60" x.20" DIP package for operation over the temperature range -55C to +125C and military environmental conditions. The flash memory is organized as 512Kx8 bits and is designed to be programmed in-system with the standard system 5.0V Vcc supply. A 12.0V VPP is not required for write or erase operations. The device can also be reprogrammed with standard EPROM programmers (with the proper socket). The standard ACT-F512K8 _ offers access times between 60ns and 150ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention, the device has separate chip enable (CE), write enable (WE) and output enable (OE) controls. The ACT-F512K8 is command set compatible with JEDEC standard 1 Mbit EEPROMs. Commands are written to the command register using standard microprocessor write timings. Register contents serve as input to an internal state-machine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the device is similar to reading from 12.0V Flash or EPROM devices. The ACTF512K8 is programmed by executing the program command sequence. This will invoke the Embedded Program Algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. Typically, each sector can be programmed and verified in less than 0.3 second. Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase Algorithm which is an internal algorithm that automatically preprograms the array, (if it is not already programmed before) executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The device is typically erased and verified in 1.5 seconds (if already completely preprogrammed). Also the device features a sector erase architecture. The sector mode allows for 64K byte blocks of memory to be erased and reprogrammed without affecting other blocks. The ACT-F512K8 is erased when shipped from the factory. The device features single 5.0V power supply operation for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. A low Vcc detector automatically inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of D7 or by the Toggle Bit feature on D6. Once the end of a program or erase cycle has been completed, the device internally resets to the read mode. All bits of each die, or all bits within a sector of a die, are erased via Fowler-Nordhiem tunneling. Bytes are programmed one byte at a time by hot electron injection. A DESC Standard Military Drawing (SMD) number is pending. Aeroflex Circuit Technology SCD1668 REV A 4/28/98 Plainview NY (516) 694-6700Absolute Maximum Ratings Parameter Symbol Range Units Case Operating Temperature Tc -55 to +125 C Storage Temperature Range TSTG -65 to +150 C Supply Voltage Range Vcc -2.0 to +7.0 Vv Signal Voltage Range (Any Pin Except A9) Note 1 VG -2.0 to +7.0 Vv Maximum Lead Temperature (10 seconds) 300 C Data Retention 10 Years Endurance (Write/Erase cycles) 100,000 Minimum AQ Voltage for sector protect, Note 2 VID -2.0 to +14.0 Vv Note 1. Minimum DC voltage on input or I/O pins is -0.5V. During voltage transitions, inputs may undershoot Vss to -2.0v for periods of up to 20ns. Maximum DC voltage on input and I/O pins is Vcc + 0.5V. During voltage transitions, inputs and I/O pins may overshoot to Vcc + 2.0V for periods up to 20 ns. Note 2. Minimum DC input voltage on A9 is -0.5V. During voltage transitions, A9 may undershoot Vss to -2.0V for periods of up to 20ns. Maximum DC input voltage on AQ is +12.5V which may overshoot to 14.0V for periods up to 20ns. Normal Operating Conditions Symbol | Parameter Minimum Maximum Units Vec Power Supply Voltage +4.5 +5.5 Vv VIH Input High Voltage +2.0 Veco + 0.5 Vv VIL Input Low Voltage -0.5 +0.8 V Te Operating Temperature (Military) -55 +125 C VID AQ Voltage for sector protect 11.5 12.5 V CAD COE CWE CCE Ci/o Parameter Ao Ais Capacitance OE Capacitance Write Enable Capacitance Chip Enable Capacitance 1/00 l/O7 Capacitance Parameters Guaranteed but not tested Capacitance (VIN= OV, f = 1MHz, Te = 25C) DC Characteristics - CMOS Compatible (Vcc = 5.0V, Vss = OV, Tc = -55C to +125C, unless otherwise indicated) Maximum 15 15 15 15 15 Parameter Sym Conditions Speeds 60, 70, 0, 120 & 1s0ns Minimum | Maximum Units Input Leakage Current IL! | Vcc =5.5V, VIN= GND to Vcc 10 pA Output Leakage Current ILOx32] Vcc = 5.5V, VIN = GND to Vcc 10 pA Active Operating Supply Current for Read (1) Icc1 | CE =ViL, OE = Vin, f= 5MHz 50 mA Active Operating Supply Current for Program or Erase (2)| Icc2 | CE =ViL, OE = Vin 60 mA Operating Standby Supply Current Icc3 | Vcc = 5.5V, CE = Vin, f= 5MHz 1.6 mA Output Low Voltage VOL | loL = +8.0 mA, Vcc = 4.5V 0.45 V Output High Voltage VOH | IOH =-2.5 mA, Vcc = 4.5V 0.85 x Vcc V Low Power Supply Lock-Out Voltage (4) VLKO 3.2 V Note 1. The Icc current listed includes both the DC operating current and the frequency dependent component (At 6 MHz). The frequency component typically is less than 2 mA/MHz, with OE at VIN. Note 2. Icc active while Embedded Algorithm (Program or Erase) is in progress. Note 3. DC Test conditions: VIL = 0.3V, VIH = Vcc - 0.3V, unless otherwise indicated. Note 4. Parameter Guaranteed by design, but not tested. Aeroflex Circuit Technology SCD1668 REV A 4/28/98 Plainview NY (516) 694-6700AC Characteristics Read Only Operations (Vcc = 5.0V, Vss = OV, Tc = -55C to +125C) Parameter Symbol 60 770 90 1 20 a 50 Units JEDEC Standd | Min Max| Min Max] Min Max] Min Max |Min Max Read Cycle Time tavav tre | 60 70 90 120 150 ns Address Access Time tavav tacc 60 70 90 120 150 ns Chip Enable Access Time tELav tce 60 70 90 120 150 ns Output Enable to Output Valid taLav toe 30 35 35 50 55 ns Chip Enable to Output High Z (1) tEHOZ toF 20 20 20 30 35 ns Output Enable High to Output High 2(1) taHaz toF 20 20 20 30 35 ns Output Hold from Address, CE or OE Change, Whichever is First] taxax ton | O 0 0) 0) 0 ns Note 1. Guaranteed by design, but not tested AC Characteristics Write/Erase/Program Operations, WE Controlled (Vcc = 5.0V, Vss = OV, Tc = -55C to +125C) Parameter Symbol 60 770 90 a 20 a 50 Units JEDEC Standd|Min Max|Min Max|Min Max|Min Max|Min Max Write Cycle Time tavac twe | 60 70 90 120 150 ns Chip Enable Setup Time tELWL tcE 0 0 0 0 0 ns Write Enable Pulse Width twLWH twe | 40 45 45 50 50 ns Address Setup Time TAVWL tas 0 0 0 0 0 ns Data Setup Time tDbvwH tps | 40 45 45 50 50 ns Data Hold Time tWHDXx {oH 0 0 0 0 0 ns Address Hold Time tWLAX taH =| 45 45 45 50 50 ns Write Enable Pulse Width High tWHWL tweH | 20 20 20 20 20 ns Bote os osramming Operation twHWHt 14|TYP| 14] TYP] 14] TYP] 14|TYP114]TYP| ps Sector Erase Time tWHWH2 30 30 30 30 30 Sec Read Recovery Time before Write tGHWL 0 0 0 0 0 ys Vcc Setup Time tvce | 50 50 50 50 50 ys Chip Programming Time 50 50 50 50 50 Sec Chip Erase Time tWHWH3 120 120 120 120 120 | Sec AC Characteristics Write/Erase/Program Operations, CE Controlled (Vcc = 5.0V, Vss = OV, Tc = -55C to +125C) Parameter Symbol 60 70 90 1 20 a 50 Units JEDEC Standd| Min Max | Min Max | Min Max | Min Max | Min Max Write Cycle Time tavac twe | 60 70 90 120 150 ns Write Enable Setup Time tWLeL tws 0 0 0 0 0 ns Chip Enable Pulse Width tELEH tcp | 40 45 45 50 55 ns Address Setup Time TAVEL tas 0 0 0 0 0 ns Data Setup Time {DVEH tps | 40 45 45 50 55 ns Data Hold Time tEHDX {oH 0 0 0 0 0 ns Address Hold Time tELAX taH =| 45 45 45 50 55 ns Chip Select Pulse Width High tEHEL tepH | 20 20 20 20 20 ns Duration of Byte Programming twHwH1 14] TYP| 14] TYP] 14] TYP] 14] TYP] 14]TYP] us Sector Erase Time twHwH2 30 30 30 30 30 Sec Read Recovery Time TaHEL ) ) ) ) ) ns Chip Programming Time 50 50 50 50 50 Sec Chip Erase Time tWHWH3 120 120 120 120 120 | Sec Aeroflex Circuit Technology 4 SCD1668 REV A 4/28/98 Plainview NY (516) 694-6700Device Operation The ACTF512K8 Monolithic is composed of One, Four megabit flash device. Programming of the ACT-F512K8 is accomplished by executing the program command sequence. The program algorithm, which is an internal algorithm, automatically times the program pulse widths and verifies proper cell status. Sectors can be pro- gramed and verified in less than 1 second. Erase is accomplished by executing the erase command sequence. The erase algorithm, which is internal, auto- matically preprograms the array if it is not already pro- gramed before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell status. The entire mem- ory is typically erased and verified in 1.5 seconds (if pre-programmed). The sector mode allows for 64K byte blocks of memory to be erased and reprogrammed with- out affecting other blocks. Bus Operation READ The ACT-F512K8 has two control functions, both of which must be logically active, to obtain data at the out- puts. Chip Enable (CE) is the power control and should be used for device selection. Output-Enable (OE) is the output control and should be used to gate data to the output pins of the chip selected. Figure 7 illustrates AC read timing waveforms. OUTPUT DISABLE With Output-Enable at a logic high level (VIH), output from the device is disabled. Output pins are placed in a high impedance state. STANDBY MODE The ACT-F512K8 standby mode consumes less than 6.5 mA. In the standby mode the outputs are in a high impedance state, independent of the OE input. If the device is deselected during erasure or programming, the device will draw active current until the operation is com- pleted. Table 1 Bus Operations Operation CE| OE] WE| AO] A1| AS} =O READ L] LJ] HY Ao] At] Ag} DOUT STANDBY H]| X] X HIGH Z OUTPUT DISABLE] L |] H] H HIGH Z WRITE L] HY] LI Ao] At] Ag DIN ENABLE SECTOR PROTECT L|Vinjp L] X] XJ] Vip xX VERIFY SECTOR PROTECT L] L] H] LY] HY] Vip] Code WRITE Device erasure and programming are accomplished via the command register. The contents of the register serve as input to the internal state machine. The state machine outputs dictate the function of the device. The command register itself does not occupy an addres- sable memory location. The register is a latch used to store the command, along with address and data infor- mation needed to execute the command. The command register is written by bringing WE to a logic low level (ViL), while CE is low and OE is at Vin. Addresses are latched on the falling edge of WE or CE, whichever hap- pens later. Data is latched on the rising edge of the WE or CE whichever occurs first. Standard microprocessor write timings are used. Refer to AC Program Character- istics and Waveforms, Figures 3, 8 and 13. Command Definitions Device operations are selected by writing specific address and data sequences into the command register. Table 3 defines these register command sequences. READ/RESET COMMAND The read or reset operation is initiated by writing the read/reset command sequence into the command regis- ter. Microprocessor read cycles retrieve array data from the memory. The device remains enabled for reads until the command register contents are altered. The device will automatically power-up in the read/reset state. In this case, a command sequence is not required to read data. Standard microprocessor read cycles will retrieve array data. The device will automatically power-up in the read/reset state. In this case, a com- mand sequence is not required to read data. Standard Microprocessor read cycles will retrieve array data. This default value ensures that no spurious alteration of the memory content occurs during the power transition. Refer to the AC Read Characteristics and Figure 7 for the specific timing parameters. BYTE PROGRAMING The device is programmed on a byte-byte basis. Pro- gramming is a four bus cycle operation. There are two "unlock" write cycles. These are followed by the program Table 2 Sector Addresses Table A16]A15| A14 Address Range SAO 0 0 0 00000h O3FFFh SA1 0 0 1 04000h O7FFFh SA2 0 1 0 08000h OBFFFh SA3 0 1 1 0C000h OFFFFh SA4 1 0 0 10000h 13FFFh SA5 1 0 1 14000h 17FFFh SA6 1 1 0 18000h 1BFFFh SA7 1 1 1 1C000h 1FFFFh Aeroflex Circuit Technology SCD1668 REV A 4/28/98 Plainview NY (516) 694-6700Table 3 Commands Definitions Command Wate First Bus Write | Second Bus Write | Third Bus Write Fourth Bus Fifth Bus Write | Sixth Bus Write Sequence Cycles Cycle Cycle Cycle Read/Write Cycle Cycle Cycle Required Addr Data Addr Data Addr Data Addr Data Addr Data | Addr | Data Read/Reset 1 XXXH FOH Read/Reset 4 5555H | AAH | 2AAAH 55H 5555H | FOH RA RD Autoselect 4 5555H | AAH | 2AAAH 55H 5555H | 90H Byte Program 6 5555H | AAH | 2AAAH 55H 5555H | AOH PA PD Chip Erase 6 5555H | AAH | 2AAAH 55H 5555H | 80H 5555H AAH |2AAAH| 55H | 5555H| 10H Sector Erase 6 5555H | AAH | 2AAAH 55H 5555H | 80H 5555H AAH |2AAAH| 55H SA 30H Sector Erase Suspend |Erase can be suspended during sector erase with Address (Dont care), Data (BOH) Sector Erase Resume |Erase can be resumed after suspend with Address (Dont care), Data (30H) NOTES: 1. Address bit A15, A16, A17 and A18 = X = Don't Care. Write Sequences may be initiated with A15 in either state. 2. Address bit A15, A16, A17 and A18 = X = Don't Care for all address commands except for Program Address (PA) and Sector Address (SA). 3. RA= Address of the memory location to be read PA = Address of the memory location to be programmed. Addresses are latched on the falling edge of the WE pulse. SA = Address of the sector to be erased. The combination of A18, A17, A16 will uniquely select any sector. 4. RD = Data read from location RA during read Operation. PD = Data to be programmed at location PA. Data is latched on the rising edge of WE. set-up command and data write cycles. Addresses are latched on the falling edge of CE or WE, whichever occurs later, while the data is latched on the rising edge of CE or WE whichever occurs first. The rising edge of CE or WE begins programming. Upon executing the pro- gram algorithm command sequence the system is not required to provide further controls or timings. The device will automatically provide adequate internally generated program pulses and verity the programmed cell status. The automatic programming operation is completed when the data on D7 is equivalent to data written to this bit at which time the device returns to the read mode and addresses are no longer latched. The device requires a valid address be supplied by the Sys- tem at this time. Data Polling must be performed at the memory location which is being programmed. Programming is allowed in any address sequence and across sector boundaries. Figure 3 illustrates the programming algorithm using typ- ical command strings and bus operations. CHIP ERASE Chip erase is a six bus cycle operation. There are two unlock write cycles. These are followed by writing the set-up command. Two more unlock write cycles are then followed by the chip erase command. Chip erase does not require the user to program the device prior to erase. Upon executing the erase algo- rithm (Figure 4) sequence the device automatically will program and verify the entire memory for an all zero data pattern prior to electrical erase. The system is not required to provide any controls or timings during these operations. The automatic erase begins on the rising edge of the last WE pulse in the command sequence and terminates when the data in D7 is "1" (see Write Operation Status section - Table 4) at which time the device returns to read the mode. See Figures 4 and 9. SECTOR ERASE Sector erase is a six bus cycle operation. There are two "unlock" write cycles. These are followed by writing the "setup" command. Two more "unlock" write cycles are then followed by the sector erase command. The sector address (any address location within the desired sector) is latched on the falling edge of WE, while the command (data) is latched on the rising edge of WE. A time-out of 100s from the rising edge of the last sector erase com- mand will initiate the sector erase command(s). Multiple sectors may be erased concurrently by writing the six bus cycle operations as described above. This sequence is followed with writes of the sector erase com- mand 30H to address in other sectors desired to be con- currently erased. A time-out of 100us from the rising edge of the WE pulse for the last sector erase command will initiate the sector erase. If another sector erase command is written within the 100us time-out window the timer is reset. Any command other than sector erase within the time-out window will reset the device to the read mode, ignoring the previous command string. Loading the sector erase buffer may be done in any sequence and with any number of sectors (0 to 7). Sector erase does not require the user to program the device prior to erase. The device automatically pro- grams all memory locations in the sector(s) to be erased prior to electrical erase. When erasing a sector or sec- tors the remaining unselected sectors are not affected. The system is not required to provide any controls or tim- ings during these operations. Data Protection The ACT-F512k8 is designed to offer protection against accidental erasure or programming caused by spurious system level singles that may exist during power transi- tions. During power up the device automatically resets the internal state machine in the read mode. Also, with Aeroflex Circuit Technology SCD1668 REV A 4/28/98 Plainview NY (516) 694-6700its control register architecture, alteration of the memory content only occurs after successful completion of spe- cific multi-bus cycle command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from Vcc power-up and power-down transitions or system noise. LOW Vcc WRITE INHIBIT To avoid initiation of a write cycle during Vcc power-up and power-down, a write cycle is locked out for Vcc less than 3.2V (typically 3.7V). If Vcc < VLko, the command register is disabled and all internal program/erase cir- cuits are disabled. Under this condition the device will reset to read mode. Subsequent writes will be ignored until the Vcc level is greater than VLko. It is the users responsibility to ensure that the control pins are logically correct to prevent unintentional writes when Vcc is above 3.2V. WRITE PULSE GLITCH PROTECTION Noise pulses of less than 5ns (typical) on OE, CE or WE will not initiate a write cycle. LOGICAL INHIBIT Writing is inhibited by holding anyone of OE = Vi, CE = ViH or WE = Vin. To initiate a write cycle CE and WE must be logical zero while OE is a logical one. POWER-UP WRITE INHIBIT Power-up of the device with WE = CE = Vi and OE= ViH will not accept commands on the rising edge of WE. The internal state machine is automatically reset to the read mode on power-up. Write Operation Status D7 DATA POLLING The ACT-F512K8 features Data Polling as a method to indicate to the host that the internal algorithms are in progress or completed. During the program algorithm, an attempt to read the device will produce compliment data of the data last written to D7. During the erase algorithm, an attempt to read the device will produce a "0" at the D7 Output. Upon completion of the erase algorithm an attempt to read the device will produce a "1" at the D7 Output. For chip Erase, the Data Polling is valid after the rising edge of the sixth WE pulse in the six write pulse sequence. For sector erase, the Data Polling is valid after the last rising edge of the sector erase WE pulse. Data polling must be performed at a sector address within any of the sectors being erased and not a protected sector. Otherwise, the status may not be valid. Once the algo- rithm operation is close to being completed, data pins (D7) change asynchronously while the output enable (QE) is asserted low. This means that the device is driv- ing status information on D7 at one instance of time and then that byte's valid data at the next instant of time. Depending on when the system samples the D7 Output, it may read the status or valid data. Even if the device has completed internal algorithm operation and D7 has a valid data, the data outputs on Do - D6 may be still invalid. The valid data on DO - D7 will be read on the suc- cessive read attempts. The Data Polling feature is only active during the programming algorithm, erase algo- rithm, or sector erase time-out. See Figures 6 and 10 for the Data Polling specifications. D TOGGLE BIT The ACT-F512K8 also features the "Toggle Bit" as a method to indicate to the host system that algorithms are in progress or completed. During a program or erase algorithm cycle, successive attempts to read data from the device will result in D6 toggling between one and zero. Once the program or erase algorithm cycle is completed, D6 Will stop toggling and valid data will be read on successive attempts. Dur- ing programming the Toggle Bit is valid after the rising edge of the fourth WE pulse in the four write pulse sequence. For chip erase the Toggle Bit is valid after the rising edge of the sixth WE pulse in the six write pulse sequence. For Sector erase, the Toggle Bit is valid after the last rising edge of the sector erase WE pulse. The Toggle Bit is active during the sector time out. See Figure 1 and 5. D5 EXCEEDED TIMING LIMITS D5 will indicate if the program or erase time has exceeded the specified limits. Under these conditions D5 will produce a "1". The Program or erase cycle was not successfully completed. Data Polling is the only operation function of the device under this condition. The CE circuit will partially power down the device under these conditions by approximately 2 mA. The OE and WE pins will control the output disable functions as shown in Table 1. To reset the device, write the reset command sequence to the device. This allows the sys- tem to continue to use the other active sectors in the device. D3 SECTOR ERASE TIMER After the completion of the initial sector erase command sequence the sector erase time-out will begin. D3 will remain low until the time-out is complete. Data Polling and Toggle Bit are valid after the initial sector erase com- mand sequence. Aeroflex Circuit Technology SCD1668 REV A 4/28/98 Plainview NY (516) 694-6700lf Data Polling or the Toggle Bit indicates the device has been written with a valid erase command, D3 may be used to determine if the sector erase timer window is still open. If D3 is high ("1") the internally controlled erase cycle has begun; attempts to write subsequent com- mands to the device will be ignored until the erase oper- ation is completed as indicated by Data Polling or Toggle Bit. If D3 is low ("0"), the device will accept additional sector erase commands. To ensure the command has been accepted, the software should check the status of D3 prior to and following each subsequent sector erase command. If D3 were high on the second status check, the command may not have been accepted. See Table 4 Sector Protection Algorithims SECTOR PROTECTION The ACT-F512K8 features hardware sector protection which will disable both program and erase operations to an individual sector or any group of sectors. To activate this mode, the programming equipment must force ViD on control pin OE and address pin A9. The sector addresses should be set using higher address lines A18, A17, and A16. The protection mechanism begins on the falling edge of the WE pulse and is terminated with the rising edge of the same. To verify programming of the protection circuitry, the pro- gramming equipment must_force Vip on address pin AQ with CE and OE at Vit and WE at ViH. Scanning the sec- tor addresses (A16, A17, and A18) while (A6, A1, AO) = (0, 1, 0,) will produce a logical "1" code at device output Do for a protected sector. Otherwise the device will read OOH for unprotected sector. In this mode, the lower order addresses, except for 0, A1, and A6 are don't care. It is also possible to verify if a sector is protected during the sector protection operation. This is done by setting A6 = CE = OE = Vit and WE = Vin (A9 remains high at Vip). Reading the device at address location XXX2H, where the higher order addresses (A18, A17, and A16) define a particular sector, will produce 01H at data out- puts (DO - D7) for a protected sector. SECTOR UNPROTECT The ACT-F512K8 also features a sector unprotect mode, so that a protected sector may be unprotected to incor- porate any changes in the code. All sectors should be protected prior to unprotecting any sector. To activate this mode, the programming equipment must force Vid on control pins OE, CE, and address pin AQ. The address pins A6, A16, and A12 should be set to VIH. The unprotection mechanism begins on the falling edge of the WE pulse and is terminated with the rising edge of the same. It is also possible to determine if a sector is unprotected in the system by writing the autoselect command and A6 is set at ViH. Performing a read operation at address location XXX2H, where the higher order addresses (A18, A17, and A16) define a particular sector address, will pro- duce 00H at data outputs (D0-D7) for an unprotected sector. Aeroflex Circuit Technology SCD1668 REV A 4/28/98 Plainview NY (516) 694-6700Table 4 Hardware Sequence Flags Status D7 D D5] D3 D2 Do In Progress Auto-Programming D7] Toggle | 0 | O D Programming in Auto Erase 0 | Toggle | 0 | 1 Auto-P i D7] Toggle | 1 1 _ Exceeding Time Limits e~ 99 D Programming in Auto Erase 0 | Toggle | 1] 1 Figure 1 AC Waveforms for Toggle Bit During Embedded Algorithm Operations ce \ toEH| WE toEs| OE / q) Data E D6 Do-D7 Do-D7 x D6=Toggle x D6=Toggle x Stop Toggle x valkd x Note: 1. D6 stops toggling (The device has completed the embedded operation) Figure 2 AC Test Circuit Current Source | lot To Device Under Test Vz ~ 1.5 V (Bipolar Supply) CL= 50 pF | lou Current Source Notes: 1) Vz is programmable from -2V to +7V. 2) IOL and IOH programmable from 0 to 16 mA. 3) Tester Impedance ZO = 75Q. 4) VZ is typically the midpoint of VOH and VoL. 5) IOL and IOH are adjusted to simulate a typical Parameter Typical Units Input Pulse Level 0-3.0 Vv Input Rise and Fall 5 ns Input and Output Timing Reference Level 1.5 Vv Output Lead Capacitance 50 pF resistance load circuit. 6) ATE Tester includes jig capacitance. Aeroflex Circuit Technology SCD1668 REV A 4/28/98 Plainview NY (516) 694-6700Figure 3 Programming Algorithm Bus Command . Comments Operations Sequence Standby (1) Write Program Valid Address/Data Sequence Read Data Polling to Verify Programming Standby (1) Compare Data Output to Data Expected Note: 1. Device is either powered-down, erase or program inhibit. Start Write Program Command Sequence (See Below) Data Poll Device Increment Address Last Address ? Yes Programming Complete Program Command Sequence (Address/Commanga): 5555H/AAH 2AAAH/55H 5555H/AOH Programming Address/Program Data Aeroflex Circuit Technology 10 SCD1668 REV A 4/28/98 Plainview NY (516) 694-6700Figure 4 Erase Algorithm Bus Command . Comments Operations Sequence Standby Write Program Valid Address/Data Sequence Read Data Polling to Verify Programming Standby Compare Data Output to Data Expected Start Write Erase Command Sequence (See Below) Data Poll or Toggle Bit Successfully Completed y Erasure Completed Chip Erase Command Sequence Individual Sector/Multiple Sector (Address/Command) Erase Command Sequence (Address/Command) 5555H/AAH 5555H/AAH 2AAAH/55H 2AAAH/55H 5555H/80H 5555H/80H 5555H/AAH 5555H/AAH 2AAAH/55H 2AAAH/55H 5555H/10H Sector Address/30H Sector Address/30H Additional Sect > Erase Commands : are Optional Sector Address/30H Aeroflex Circuit Technology 1 SCD1668 REV A 4/28/98 Plainview NY (516) 694-6700Figure 5 Figure 6 Toggle Bit Algorithm Data Polling Algorithm Start Start { VA = Byte Address for Programming { VA = Byte Address for Programming = Any of the Sector Addresses = Any of the Sector Addresses > Read Byte within the sector being erased > Read Byte within the sector being erased Address = VA during sector erase operation Address = VA during sector erase operation = XXXXH during Chip Erase = XXXXH during Chip Erase D6 = Toggle D7= 2 Toggle? Read Byte Read Byte Do-D7 Do-D7 Address = VA Address = VA Fail Fail Note 1. D is rechecked even if D5 = "1" because D may stop toggling at Note 1. D7 is rechecked even if D5 = "1" because D7 may change the same time as D5 changes to "1". simultaneously with D5. Aeroflex Circuit Technology 12 SCD1668 REV A 4/28/98 Plainview NY (516) 694-6700Figure 7 AC Waveforms for Read Operations tre Addresses x Addresses Stable X tace. > CE / \ oe \ tee yyw me / \ tce > tou High Z Outputs 9 Output Valid Figure 8 Write/Erase/Program Operation, WE Controlled Addresses X Data Polling - tor tou Data tft 5.0V ~| tce Notes: 1. PAis the address of the memory location to be programmed. 2. PD is the data to be programmed at byte address. 3. D7 is the Output of the complement of the data written to the deviced. 4. Dout is the output of the data written to the device. 5. Figure indicates last two bus cycles of four bus cycle sequence. Aeroflex Circuit Technology 13 SCD1668 REV A 4/28/98 Plainview NY (516) 694-6700Figure 9 AC Waveforms Chip/Sector Erase Operations r| je tan Data Polling Addresses X sss 2AAAH 5555H K 5555H X 2AAAH Xx SA X tas>} = [NALINI LILI NN j tenwi+-> OE j \ 5 <twe WE / / N/ \/ \/ \/ \/ a twrHp toe ee bl te ton 7 h / \ / \ / \ / \ / \ Data / *_|_ + AAH \__/ 55H \__/ 80H \__/AAH \__/ 55H \__/10H/30H ~| betpos Vee Lon Notes: 1. SA is the sector address for sector erase. Figure 10 AC Waveforms for Data Polling During Embedded Algorithm Operations __ teu FF CE J | faq DF toEH > DQ7= Valid Data be. twHwH1 or 2. _ > DQO0-DQ6 DQO0-DQ6=Invalid toe * DQ7=Valid Data (The device has completed the Embedded operation). Aeroflex Circuit Technology 14 SCD1668 REV A 4/28/98 Plainview NY (516) 694-6700Figure 11 Sector Protection Algorithm Start Set Up Sector Address (A18, A17, A16) PLSCNT = 1 OE =Vip AQ = Vip, CE = VIL Activate WE Pulse Time Out 100p1s Increment PLSCNT Power Down OE WE = VIH CE =OE=VIH A9 Should Remain Vip Read From Sector Address = SA, AO = 0, Ai = 1, A6 =0 Device Failure Data = 01H ? Protect Another Sector? Yes No Remove Vip from A9 Write Reset Command Sector Protection Complete Aeroflex Circuit Technology SCD1668 REV A 4/28/98 Plainview NY (516) 694-6700Figure 12 Sector Unprotect Algorithm Start Protect All Sectors PLSCNT =1 Set Up Sector Unprotect Mode A12 = A16 = VIH Activate WE Pulse Time Out 10 msms Set OE = CE = VIL AQ = ViD Setup Sector Address SAO Set Ai = 1, AO =0, A6=1 Increment Sector Address Notes: SAO = Sector Address for initial sector SA7 = Sector Address for last sector Please refer to Table 2 Read Data From Device Data = 00H ? Sector Address = SA7 ? Yes Increment PLSCNT No PLSCNT = 1000 ? Device Failure Remove Vip from A9 Sector Unprotect Completed Aeroflex Circuit Technology SCD1668 REV A 4/28/98 Plainview NY (516) 694-6700Figure13_ Alternate CE Controlled Programming Operation Timings Addresses X 5555H X PA e twop] jeetaslee- tarp} cE / , _/ >|__ ae tow Data Polling Data / 5.0V Notes: 1. PA is the address of the memory location to be programmed. 2. PD is the data to be programmed at byte address. 3. D7 is the Output of the complement of the data written to the device. 4. DOUT is the output of the data written to the device. 5. Figure indicates last two bus cycles of four bus cycle sequence. Aeroflex Circuit Technology SCD1668 REV A 4/28/98 Plainview NY (516) 694-6700Pin Numbers & Functions 32 Pins DIP Packa A18 17 1/03 A16 18 1/04 A15 19 1/05 A12 20 1/06 A7 21 1/07 A6 22 cs A5 23 A10 A4 24 OE A3 25 Att A2 26 Ag At 27 A8 Ao 28 29 30 31 32 Package Outline "P4" .590" x 1.67" DIP Package 1.686 1.654 Pin 32-. Ma poop poppe ooo eo eee Pin 1~ -200 -145 605 580 | | OTT an | 012 -{ 100 dt ag - 020 .048 _ ote + 499 "045 016.019 405 610 MIN "590 All dimensions in inches Aeroflex Circuit Technology 18 SCD1668 REV A 4/28/98 Plainview NY (516) 694-6700Pin Numbers & Functions 32 Pins Flat Package Ai8 17 Ai6 18 A15 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Package Outline "F6" 32 Lead, Ceramic Flat Package 20 10 Pin 32 Pin 17 | 5 EE .410 -125 MAX +.005 +.002 -005 "001 | .750_ + All dimensions in inches (15 Spaces at .050) 2 sides Aeroflex Circuit Technology 19 SCD1668 REV A 4/28/98 Plainview NY (516) 694-6700Pin Numbers & Functions 32 Pins Flat Package A18 17 A16 18 A15 19 Ai2 20 A7 21 A6 22 Ad 23 A4 24 A3 25 A2 26 At 27 Ao 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Package Outline "F7" 32 Lead, Ceramic Flat Package id 3 Base Plane -.006 TYP 125 MAX -530 +.005 068 +-||.025 | } Uy. TYP 0.017 , se : _ a / -4 .030 +002 00 +.002 TYP 750 + -005 - 001 (15 spaces at .050 Seating Plane 2 sides All dimensions in inches Aeroflex Circuit Technology 20 SCD1668 REV A 4/28/98 Plainview NY (516) 694-6700(-\EROFLEX CIRCUIT TECHNOLOGY Ordering Information Model Number DESC Drawing Number Speed Package ACT-F512K8N-150F6Q 5962-9669201 HUC* 150 ns Flat Pack ACT-F512K8N120F6Q 5962-9669202HUC* 120 ns Flat Pack ACT-F512K8N090F6Q 5962-9669203HUC* 90 ns Flat Pack ACT-F512K8N-070F6Q 5962-9669204HUC* 7Ons Flat Pack ACT-F512K8N060F6Q 5962-9669205HUC* 60ns Flat Pack ACT-F512K8N-150F7Q 5962-9669201 HTC* 150 ns Flat Pack (Formed) ACT-F512K8N-120F7Q 5962-9669202HTC* 120 ns Flat Pack (Formed) ACT-F512K8N090F7Q 5962-9669203HTC* 90 ns Flat Pack (Formed) ACT-F512K8N-070F7Q 5962-9669204HTC* 70 ns Flat Pack (Formed) ACT-F512K8N060F7Q 5962-9669205HTC* 60ns Flat Pack (Formed) ACT-F512K8N150P4Q 5962-9669201HXC* 150 ns DIP Pack ACT-F512K8N120P4Q 5962-9669202HXC* 120 ns DIP Pack ACT-F512K8N090P4Q 5962-9669203HXC* 90 ns DIP Pack ACT-F512K8N070P4Q 5962-9669204HXC* 70 ns DIP Pack ACT-F512K8N-060P4Q 5962-9669205HXC* 60ns DIP Pack * Pending Part Number Breakdown ACT- F 512K 8 N- 090 F6 Q Aeroflex Circuit a Technology Memory Type F = FLASH EEPROM Memory Depth Memory Wiath, Bits Screening C = Commercial Temp, 0C to +70C | = Industrial Temp, -40C to +85C T = Military Temp, -55C to +125C M = Military Temp, -55C to +125C, Screening * Options Q = MIL-PRF-38534 Compliant / SMD Package Type & Size N = None Memory Speed, ns Surface Mount Packages Thru-Hole Packages F6 = .82" x .40" 32 Lead FP Unformed P4 = 32 Pin DIP F7 = 82" x .40" 32 Lead FP Formed creen d to the individual test methods of MIL-STD-883 * Specifications subject to change without no Aeroflex Circuit Technology 35 South Service Road Plainview New York 11830 Telephone: (516) 694-6700 FAX: (516) 694-6715 Toll Free Inquiries: 1-(800) 843-1553 Aeroflex Circuit Technology 21 SCD1668 REV A 4/28/98 Plainview NY (516) 694-6700