AS1156-BSOU - austriamicrosystems AG

AS1156/AS1154

Single/Dual LVDS Driver

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systems

Data Sheet

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1 General Description

The AS1156/AS115 4 is a Single/Dual Flow-Through

LVDS (Low-Voltage Differential Signaling) Line Driver

which accepts and converts LVTTL/LVCMOS input lev-

els into LVDS output signals. The device is perfect for

low-power low-noise applicati ons requiring high signal-

ing rates and reduced EMI emissions.

The device is guaranteed to transmit data at speeds up

to 800Mbps (400MHz) over controlled impedance media

of approximately 100Ω. Supported transmission media

are PCB traces, backplanes, and cables.

The AS1156 is a single LVDS transmitter, and the

AS1154 is a dual LVDS transmitter.

Outputs conform to the ANSI TIA/EIA-644 LVDS stan-

dards. Flow-through pino ut simplifies PC board layo ut

and reduces crosstalk by separating the LVTTL/LVC-

MOS inputs and LVDS outputs.

The AS1156/AS1154 operates from a single +3.3V sup-

ply and is specified for operation from -40 to +85°C.

Figure 1. Block Diagram

2 Key Features

!Flow-Through Pinout

!Guaranteed 800Mbps Data Rate

!250ps Pulse Skew (Max)

!Conforms to ANSI TIA/EIA-644 LVDS Standards

!Single +3.3V Supply

!Operating Temperatu re Range: -40 to +85°C

!8-Pin SOIC Package

3 Applications

Digital Copiers, Laser Printers, Cellular Phone Base S t a-

tions, Add/Drop Muxes, Digital Cross-Connects,

DSLAMs, Network Switches/Routers, Backplane Inter-

connect, Clock Distribution Computers, Intelligent Instru-

ments, Controllers, Critical Microprocessors and

Microcontrollers, Power Monitoring, and Portable/Bat-

tery-Powered Equipment.

AS1156

VCC

IN1

N/C

GND

OUT1-

OUT1+

N/C

AS1154

VCC

IN1

IN2

GND

OUT1-

OUT1+

OUT2+

OUT2-

Tx Tx

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Data Sheet Pin Assignments

4 Pinout and Packaging

Pin Assignments

Figure 2. AS1156/AS1154 Pin Assignments (Top View)

Pin Descriptions

Table 1. AS1156/AS1154 Pin Descriptions

Pin Number Pin Name Description

AS1154 AS1156

11VCC Power Supply Input. Bypass VCC to GND with 0.1µF and 0.001µF

ceramic capacitors.

22IN1

LVTTL/LVCMOS Driver Input

3IN2

LVTTL/LVCMOS Driver Input

44GND

Ground

5OUT2-

Inverting LVDS Driver Output

6OUT2+

Noninverting LVDS Driver Output

77OUT1+

Noninverting LVDS Driver Output

88OUT1-

Inverting LVDS Driver Output

3, 5, 6 N/C Not connected

OUT1-

OUT1+

N/C

VCC

IN1

N/C

GND

AS1156

OUT1-

OUT1+

OUT2+

OUT2-

VCC

IN1

IN2

GND

AS1154

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Data Sheet Pin Descriptions

5 Absolute Maximum Ratings

Stress es be yo nd those listed in Table 2 ma y cau se permanent damage to the device. These are stress ratings only,

and functional operation of the device at these or any othe r conditions beyond those indicated in the operational sec-

tions of the specifications is no t implied. Exposure to absolute maximum rating conditions for extended periods may

affect device reliability.

Table 2. Absolute Maximum Ratings

Parameter Limits Units Notes

VCC to GND -0.3 to +5.0 V

INx, EN, ENn to GND -0.3 to (VCC + 0.3) V

OUTx+, OUTx- to GND -0.3 to +5 V

Short Circuit Duration (OUTx+, OUTx-) Continuous

Continuous Power Dissipation

(TA = +70 ° C) 755 mW Derate 9.4mW/°C Above +70°C

Storage Temperature Range -65 to +150 ºC

Maximum Junction Temperature +150 ºC

Operating Temperature Range -40 to +85 ºC

Package Body Temperature 260 ºC

The reflow peak soldering temperature

(body temperature) specified is in

compliance with IPC/JEDEC J-STD-

020C “Moisture/ Reflow Sensitivity

Classification for Non-Hermetic So lid

State Surface Mount Devices”.

ESD Protection ±4 kV Human Body Model, INx, OUTx+,

OUTx--

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Data Sheet DC Electrical Characteristics

6 Electrical Characteristics

DC Electrical Characteristics

(VCC = +3.0 to +3 .6 V, TA = -40 to +85°C , RL = 100Ω ±1%

Typical values are at VCC = +3.3V, TA = +25°C, Unless Otherwise Noted.) 1

Notes:

1. Currents into the device are positive, and current out of the device is negative. All vo ltages are referenced to

ground except VOD.

2. Guaranteed by correlation data.

Table 3. DC Electrical Characteristics

Parameter Symbol Conditions Min Typ Max Unit

LVDS Output (OUtx+, OUTx-)

Differential Output Voltage VOD Figure 21 on page 11 250 355 450 mV

Change in Magnitude of VOD

Between Complement ary Output

States ΔVOD Figure 21 on page 11 1 35 mV

Offset Voltage VOS Figure 21 on page 11 1.125 1.25 1.375 V

Change in Magnitude of VOS

Between Complement ary Output

States ΔVOS Figure 21 on page 11 4 25 mV

Output High Voltage VOH 1.6 V

Output Low Voltage VOL 0.90 V

Differential Output Short-Circuit

Current 2IOSD VOD = 0V -9 mA

Output Short-Circuit Current IOS OUTx+ = 0V at INx = VCC or

OUTx- = 0V at INx = 0V -3.7 -9 mA

Power-Off Output Current IOFF VCC = 0V or open, OUTx+ = 0V or 3.6V

OUTx- = 0V or 3.6V, RL = -20 20 µA

Inputs (INx)

High-Level Input Voltage VIH 2.0 VCC V

Low-Level Input Voltage VIL GND 0.8 V

Input Current IIN INx = 0V or VCC -20 20 µA

Supply Current

No-Load Suppl y Current ICC RL = , INx = VCC or 0V for all

channels 2 3.5 mA

Loaded Supply Current ICCL

RL = 100Ω, INx = VCC or 0V for all

channels, AS1156 5.5 7.5 mA

RL = 100Ω, INx = VCC or 0V for all

channels, AS1154 8.5 12 mA

∞

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Data Sheet Switching Characteristics

Switching Characteristics

(VCC = +3.0 to +3.6V, RL = 100Ω ±1%, CL = 2.5pF (differential), TA = -40 to +85°C

Typical values are at VCC = +3.3V, TA = +25ºC, Unless Otherwise Noted.) 1, 2, 3, 10

Notes:

1. Parameters are guaran teed by design and characterizati on.

2. CL includes probe and jig capacitance.

3. Signal generator conditions for dynamic tests: VOL = 0, VOH = 2.4V, f = 100MHz, 50% duty cycle, RO = 50Ω,

tR ≤ 1ns, tF ≤ 1ns (0 to 100%).

4. tSKD1 is the magnitude difference of differential propagation delay. tSKD1 = |tPHLD - tPLHD|.

5. tSKD2 is the magnitude difference of tPHLD or tPLHD of one channel to the tPHLD or tPLHD of another channel on

the same device.

6. tSKD3 is the magnitude difference of any differential propagation delays between devices at the same VCC and

within 5°C of each ot h er.

7. tSKD4 is the magnitude difference of any differential propagation delays between devi ces operating over the

rated supply and temperature ranges.

8. fMAX signal generator conditions: VOL = 0, VOH = 2.4V, 50% duty cycle, RO = 50Ω,

tR ≤ 1ns, tF ≤ 1ns (0 to 100%).

9. Transmitter output criteria: duty cycle = 45 to 55%, VOD ≥ 250mV.

10. For optimum performance matched circuits should be used.

Table 4. Switching Characteristics

Parameter Symbol Conditions Min Typ Max Unit

Differential Propagation Delay,

High-to-Low tPHLD Figure 20 on page 11 and

Figure 21 on page 11 1.1 1.268 1.5 ns

Differential Propagation Delay,

Low-to-High tPLHD Figure 20 on page 11 and

Figure 21 on page 11 1.1 1.267 1.5 ns

Differential Pulse Skew 4 tSKD1 Figure 20 on page 11 and

Figure 21 on page 11 90 200 ps

Differential Channel-to-Channel Skew 5tSKD2 Figure 20 on page 11 and

Figure 21 on page 11 110 250 ps

Differential Part-to-Part Skew 6tSKD3 Figure 20 on page 11 and

Figure 21 on page 11 750 ps

Differential Part-to-Part Skew 7tSKD4 Figure 20 on page 11 and

Figure 21 on page 11 900 ps

Rise Time tTLH Figure 20 on page 11 and

Figure 21 on page 11 200 356 800 ps

Fall Time tTHL Figure 20 on page 11 and

Figure 21 on page 11 200 352 800 ps

Maximum Operating Frequency 8, 9 fMAX 400 MHz

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Data Sheet Switching Characteristics

7 Typical Operating Characteristics

VCC = +3.3V, CLOAD = 2.5pF (differential), Freq = 20MHz, Tamb = + 25ºC, unless otherwise noted

Figure 3. Transition Time vs. VCC Figure 4. Transition Time vs. Temperature

Figure 5. Differential Pulse Skew vs. VCC Figure 6. Pulse Skew vs. Temperature

Figure 7. Differential Propagation Delay vs. VCC; Figure 8. Differential Propagation Delay vs. Temp.

100

150

200

250

300

350

-50 -30 -10 10 30 50 70 90

Ambient T emperature(° C)

T r ans ition T ime ( ps ) .

230

240

250

260

270

3 3.1 3.2 3.3 3.4 3.5 3.6

Supply Volt age( V)

T r ans ition T ime ( ps ) .

tTLH

tTHL

tTLH

tTHL

-50-30-101030507090

Ambient Temper at ur e( °C)

Pulse Skew (ps) .

3 3.1 3.2 3.3 3.4 3.5 3.6

Supply Volt age( V)

Dif ferential Puls e Skew ( ps ) .

0.95

0.97

0.99

1.01

1.03

1.05

3 3.1 3.2 3.3 3.4 3.5 3.6

S upply Voltage(V)

Dif f. P r opagation Delay ( ns ) .

tPLHD

tPHLD

0.98

1.02

1.04

1.06

1.08

1.1

1.12

1.14

-50 -30 -10 10 30 50 70 90

Ambient T emperature(° C)

Dif f. P r opagation Delay ( ns ) .

tPLHD

tPHLD

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Data Sheet Switching Characteristics

Figure 9. Differential Output Voltage vs. VCC Figure 10. Diffe rential Output Voltage vs. Frequency

Figure 11. Offset Voltage vs. VCC Figure 12. Offset Voltage vs. Frequency

Figure 13. Output Voltage vs. VCC; Figure 14. Output Voltage vs. Load Resistance;

325

330

335

340

345

350

3 3.1 3.2 3.3 3.4 3.5 3.6

Supply Volt age ( V)

Dif ferential O ut put Voltage (m V ) .

100

150

200

250

300

350

0 50 100 150 200 250 300 350 400

Frequency ( MHz)

Dif ferential O ut put Voltage (m V ) .

1.1

1.15

1.2

1.25

1.3

1.35

0 50 100 150 200 250

F r equenc y (MHz)

O ff s et Voltage (V ) .

1.2

1.21

1.22

1.23

1.24

3 3.1 3.2 3.3 3.4 3.5 3.6

Supply Volt age ( V)

O ff s et Voltage (V ) .

0.95

1.05

1.15

1.25

1.35

1.45

80 90 100 110 120 130 140 150

Load Resist anc e ( )

Output V oltage (V ) .

0.95

1.05

1.15

1.25

1.35

1.45

3 3.1 3.2 3.3 3.4 3.5 3.6

Supply Volt age ( V)

Output V oltage (V ) .

VOUT+

VOUT-

VOUT+

VOUT-

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Data Sheet Switching Characteristics

Figure 15. ICC vs. VCC Figure 16. ICC vs. Temperature;

Figure 17. Short Circuit Current vs. VCC Figure 18. ICC vs. Frequency

-50-30-101030507090

Ambient Temper at ur e( °C)

Supply Cur r ent ( m A ) .

9.4

9.8

10.2

10.6

3 3.1 3.2 3.3 3.4 3.5 3.6

Supply Volt age ( V)

Supply Cur r ent ( m A ) .

Freq = 100MHz

Freq = 20MHz

3.6

3.65

3.7

3.75

3.8

3.85

3.9

3 3.1 3.2 3.3 3.4 3.5 3.6

S upply Voltage(V)

O utput S hor t Circ uit Cur r ent ( m A )

0 50 100 150 200 250

F r equenc y (MHz)

Supply Cur r ent ( m A ) .

Two Channels

One Channel

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Data Sheet L VDS Interface

8 Detailed Description

LVDS Interface

The LVDS interface standard is a signaling method intended for point-to-point communication over a controlled-imped-

ance medium as defined by the ANSI/TIA/EIA-644 and IEEE 1596.3 standards. The LVDS standard uses a lower volt-

age swing than other common communication standards, achieving higher data rates with reduced power

consumption while reducing EMI emissions and system susceptibility to noise.

The AS1156/AS1154 is an 800Mbps single/dual differential LVDS driver that is designed for high-speed, point-to-point,

low-power applications. This device accepts LVTTL/LVCMOS input levels and translates them to LVDS output signals.

The AS1156/AS1154 gen erates a 2.5mA to 4.5mA output current using a current-steering configuration. This current

steering approach induces less ground bounce and no shoot-through current, enhancing noise margin and system

speed performance. The driver outputs are short-circuit current limited, and enter a high-impedance state when the

device is not powe red or is disabled.

The current-steering architecture of the AS1156/AS1154 requires a resistive load to terminate the signal and complete

the transmission loop. Because the device switches current and not voltage, the actual ou tput voltage swing is deter-

mined by the value of the termination resistor at the input of an LVDS receiver (AS1157, AS1158). Logic states are

determined by the directio n of curren t flow through the termination resistor.

With a typical 3.7mA output current, the AS1156/AS1154 produces an output voltage of 370mV when driving a 100Ω

load.

Termination

Because the AS1156/AS1154 is a current-steering device, no output voltage will be generate d without a termination

resistor. The termination resistors should match the differential impedance of the transmission line. Output voltage lev-

els depend upon the value of the termination resistor.

The AS1156/AS1154 is optimized for point-to-point interface with 100Ω termination resistors at the receiver inputs. Ter-

mination resistance values may range between 90 and132Ω, depending on the characteristic impedance of the trans-

mission medium.

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Data Sheet Power-Supply Bypassing

9 Applications

Figure 19. Typical Application Circuit

Power-Supply Bypassing

To bypass VCC, use high-frequency surface-mount ceramic 0.1µF and 0.001µF capacitors in parallel as close to the

device as possible, with the smaller valued capacitor closest to pin VCC.

Differential Traces

Input trace characteristics can adversely affect the performance of the AS1156/AS1154.

!Use controlled-impedance PC board traces to match the cable characteristic impedance. The termination resistor is

also matched to this characteristic impedance.

!Eliminate reflections and ensure that noise couples as common mode by running the differential traces near each

other.

!Reduce skew by using matched trace lengths. T ight skew control is required to minimize emissions and proper data

recovery of the devices.

!Route each channel’s differential signals very close to each other for optimal cancellation of their respective exter-

nal magnetic fields. Use a constant distance between the differential traces to avoid irregularities in differential

impedance.

!Avoid 90° turns (use two 45° turns).

!Minimize the number of vias to further prevent impedance irregularities.

Cables and Connectors

Supported transmission media include prin ted circuit board traces, backplanes, and cables.

!Use cables and connectors with matched differential impedance (typically 100Ω) to minimize impedance mis-

matches.

!Balanced cables such as twisted pair offer superior signal quality and tend to generate less EMI due to magnetic

field canceling effects. Balanced cables pick up noise as common mode, which is rejected by the LVDS receiver.

!Avoid the use of unbalanced cables such as ribbon cable or simple coaxial cable.

Table 5. Function Table

Input Output

INxOUTx+ OUTx-

LL H

HHL

0.8V < VINx < 2.0V Undetermined Undetermined

LVDS

Signals

107Ω

LVTTL/LVCMOS

Data Inputs LVTTL/LVCMOS

Data Outputs

100Ω Shielded Twisted Cable or Microstrip PC Board Traces

Tx Rx

AS1158

Single LVDS Receiver

AS1156

0.1µF0.001µF

+3.3V

0.1µF0.001µF

+3.3V

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Data Sheet

Board Layout

The device should be placed as close to the interface connector as possible to minimize LVDS trace length.

!Keep the LVDS and any other digital signals separated from each other to reduce crosstalk.

!Use a four-layer PC board that provides separate power, ground, LVDS signals, and input signals.

!Isolate the input LVDS signa ls from each other and the output LVCMOS/LVTTL sign als from each other to prevent

coupling.

!Separate the input LV DS signals from the output signals planes with the power and ground planes for best results.

Figure 20. Driver Propagation Delay and Transition Time Waveforms

Figure 21. Driver Propagation Delay and Transition Time Test Circuit

tTHLtTLH

tPLHD tPHLD

0 Diffe r ential

1.5V

20%

80%

20%

OUTx-

OUTx+

INx

VOH

VOL

1.5V

VDIFF = (VOUTx+) - (VOUTx-)

80%

OUTx-

Generator

50Ω

CLRL

OUTx+

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Data Sheet

Figure 22. Driver VOD and VOS Test Circuit

VOS VOD

OUTx+

OUTx-

RL/2

VCC

GND

INx

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Data Sheet Board Layout

10 Package Drawings and Markings

The AS1156/AS1154 is available in a 8-pin SOIC package.

Figure 23. 8-pin SOIC Package

Symbol Min Max

A1.521.72

A1 0.10 0.25

A2 1.37 1.57

B0.360.46

C0.190.25

D4.804.98

E3.813.99

e1.27BSC

H5.806.20

h0.250.50

L0.411.27

α0º 8º

ZD 0.53REF

Notes:

1. Lead coplanarity should be 0 to 0.10mm (.004”) max.

2. Package surface finishing:

- Top, matte (charmilles #18-30)

- All sides, matte (charmilles +18-30)

- Bottom, smooth or matte (charmilles +18-30)

3. All dimensions excluding mold flashes and end flash from the pack-

age body shall not exceed 0.25mm (.010”) per side.

4. Details of pin #1 mark are optional but must be located within the

area indicated.

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Data Sheet Board Layout

11 Ordering Information

Part Number Description Delivery Form Package

AS1156-BSOU Single Channel LVDS Line Driver Tubes SOIC-8

AS1156-BSOT Single Channel LVDS Line Driver Tape and Reel SOIC-8

AS1154-BSOU Dual Channel LVDS Line Driver Tubes SOIC-8

AS1154-BSOT Dual Channel LVDS Line Driver Tape and Reel SOIC-8

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Data Sheet Board Layout

Copyrights

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All products and companies mentioned are trademarks or registered trademarks of their respective companies.

Disclaimer

Devices sold by austriamicrosystems AG are covered by the warranty and patent indemnification provisions appearing

in its Term of Sale. austriamicrosystems A G makes no warranty , express, statutor y , implied, or by description regarding

the information set forth herein or rega rd i ng th e fre e do m of the described devices from patent infringement. austriami-

crosystems AG reserves the right to change specifications and prices at any time and withou t notice. Therefore, prior

to designing this product into a system, it is necessary to check with austriamicrosystems AG for current information.

This product is intended for use in normal commercial applications. Applicati ons requiring extended temperature

range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-

sustaining equipment are specifically not recommended without additional processing by austriamicrosystems AG for

each application. For shipments of less than 100 parts the manufacturing flow might show deviations from the standard

production flow, such as test flow or test location.

The information furnished here by austriamicrosystems AG is believed to be correct and accurate. However,

austriamicrosystems AG shall not be liable to recipient or any third party for any damages, including but not limited to

personal injury, property damage, loss of profits, loss of use, interruption of business or indirect, special, incidental or

consequential damages, of any kind, in connection with or arising out of the furnishing, performance or use of the tech-

nical data herein. No obligation or liability to recipient or any third party shall arise or flow out of

austriamicrosystems AG rendering of technical or other services.

Cont act Information

Headquarters

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A-8141 Schloss Premstaetten, Austria

Tel: +43 (0 ) 3136 500 0

Fax: +43 (0) 3136 525 01

For Sales Offices, Distributors and Representatives, please visit:

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