CY7C43643V
CY7C43663V/CY7C43683V
PRELIMINARY
3.3V 1K/4K/16K x36 Unidirectional
Synchronous FIFO w/ Bus Matching
Cypress Semiconductor Corporation • 3901 North First Street • San J ose • CA 95134 • 408-943-2600
October 2
,
1998
V
Features
• High-speed, low-power, Unidirectional, first-in first-out
(FIFO) memories w/ bus matching capabilities
• 1Kx36 (CY7C43643V)
• 4Kx36 (CY7C43663V)
• 16Kx36 (CY7C43683V)
• 0.35 -micron CMOS for opti m um speed/power
• High- speed 67-MH z operati on (15 ns read/wr ite cycl e
times)
• Low power
—ICC= 100 mA
—ISB= 5 mA
• Fully asynchronous and simultaneous read and write
operati on permitt ed
• Mailbox bypass regi ster f or each FIFO
• P arallel and Seri al Progr am mable Almost- Full and Al-
most-Empty flags
• Retran s mi t fu ncti o n
• Standard or FWFT mode user sel ectable
• Partial Reset
• Big or Little Endian format for word or byte bus sizes
• 128-pin TQFP packaging
• 3.3V pin-compatible, feature enhanced, density up-
grade to IDT723623/33/43 family
• Easily expandab le in widt h and depth
Logic Block Diagram
Port-A
Control
Logic Port-B
Control
Logic
Mail 1
Register
Input
Register
Output
Register
Write
Pointer Read
Pointer
Status
Flag Logic
Programmable Flag
Offset Registers Timing
Mode
1K/4K/16K
x36
Dual Ported
Memory
Mail 2
Register
FIFO,
Mail1
CLKA
CSA
W/RA
ENA
MBA
RT
MRS1
PRS
FF/IR
AF
SPM
FS0/SD
FS1/SEN
A0–35
MBF2
BE/FWFT
B0–35
CLKB
CSB
W/RB
ENB
MBB
BE
BM
SIZE
EF/OR
AE
MBF1
Mail2
Reset
Logic
Bus Matching
36
36
MRS2
CY7C43643V
CY7C43663V/CY7C43683V
2
PRELIMINARY
CY7C43643V
CY7C43663V
CY7C43683V
TQFP
Top View
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
FS0/SD
MRS2
FS1/SEN
GND
GND
MRS1
MBA
MBF2
NC
AF
VCC
PRS
FF/IR
CSA
ENB
W/RB
CSB
GND
NC
EF/OR
NC
AE
VCC
MBF1
MBB
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
B30
B26
B27
B28
B29
B31
GND
GND
B32
B33
B34
B35
VCC
VCC
CLKB
GND
SIZE
B16
B17
B18
B19
B20
B21
B22
B23
GND
BM
B24
B25
RT
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
A2
B0
GND
A0
A1
VCC
SPM
A3
A4
A5
GND
A6
A7
A8
A9
B9
B8
B7
VCC
B6
GND
B5
B4
B3
B2
B1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
VCC
A29
GND
A30
A31
A32
A34
A35
GND
CLKA
ENA
W/RA
A12
A20
GND
A18
A19
A21
VCC
A22
GND
FWFT/STAN
A23
A24
A25
A26
A27
A28
A33
72
71
70
69
68
67
66
65
B12
B10
B11
GND
B13
B14
B15
VCC
30
31
32
33
34
35
36
37
38
VCC
A10
A11
GND
A13
A14
A15
A16
A17
NC
Pin Configurat ion
CY7C43643V
CY7C43663V/CY7C43683V
3
PRELIMINARY
Functional Description
The CY7C436X3V is a monolithic, high-speed, low-power,
CMOS Unidirectional Synchronous (clocked) FIFO memory
which supports cl ock frequen cies up to 67 MHz a nd has read
access times as fast as 10 ns. Two independent 1K/4K/16K x
36 dual-port SRAM FIFOs on board each chip buffer data in
opposite directions. FIFO data on Port B can be output in
36-bit, 18-bit, or 9- bit form ats with a choice of big- or little-en-
dian configurations.
The CY7C436X3V is a synchronous (clocked) FIFO, mean ing
each port employs a synchronous interface. All dat a tr ansfers
through a port are gated to the LOW-to-HIGH transition of a
port clock by enable signals. The clocks for each por t are in-
dependent of one another and can be asynchronous or coin-
cident. The enables for each port are arranged to provide a
simple Unidirectional interface between microprocessors
and/or buses with synchronous control.
Commu nicati on betw een eac h port ma y b ypas s the FIF Os vi a
two mailbox registers. The mailbox registers’ width matches
the sel ected P ort B bu s width. Each mailbo x register has a flag
(MBF1 and MBF2) to signal when ne w m ail has been stored.
Two ki nds of reset are available on the CY7C436X3 V: Master
Reset and P artial Reset. Mast er Reset in iti aliz es the read and
write point ers to the first location of the memory array, confi g-
ures the FIFO for big- or little-endian byte arrangement and
selects serial fl ag programming, parallel flag programming , or
one of the three possible default flag offset settings, 8, 16, or
64. The FIFO also has a Master Reset pin, MRS1/MRS2.
Par tial Reset al so sets the read and wri te pointers to the first
location of the memory. Unlike Mast er Reset, any settings ex-
ist ing pri or to P artial Reset (i.e ., prog ramming method a nd par-
tial flag default offsets) are retained. Partial Reset is useful
sinc e it permits f lushi ng of th e FIFO m emory witho ut chang in g
any confi guration settings. The FI FO has its own independent
P artial Reset pin, PRS.
The CY7C436X3V have two modes of operation: In the CY
Standard Mode, the f irst word written to an empty FIFO i s de-
posited into th e m emo ry arr ay. A read operation is requi red to
acce ss that word (along with all other words residing in mem -
ory). In the First Word Fall Through Mode
(FWFT), the first
long-word (36-bit wide) written to an empty FIFO appears au-
tomatically on the outputs, no read operation required (never -
theless, accessing subsequent words does necessit ate a for-
mal read request). The state of the FWFT/STAN pin during
FIFO operation determines the mode in use.
The FIFO has a com bined Empty/Out put Ready flag (EF /OR)
and a combined Full/I nput Ready f lag (FF/IR). The EF and FF
function s are sel ected i n the CY Standard Mode. EF i ndicat es
whether the memory is full or not . The IR and OR funct ions are
selected in the First Word Fall Through Mode. IR indicates
whether or not the FIFO has avai lable memory locations. OR
show s whether t he F IFO has data availabl e fo r readin g or not.
It marks the presence of valid data on the outputs.
The FIFO has a programmable Almost Em pty fl ag (AE ) and a
programmable Almost Full f lag (AF). AE indicates when a se-
lected number of words written to FIFO memory achieve a
predetermined “a lmost empty state.” AF in dicates when a se-
lected number of words written to the memory achieve a pr e-
determined “ almost full sta te.”
IR and AF are synchronized to the port clock that writes data
into its array. OR and AE are synchronized to the port clock
that r eads dat a from its arr a y. Progr ammab l e offse t f or AE and
AF are loaded in parallel using Por t A or in serial via the SD
input. Three default of fset settings are also provided. The AE
threshold can be set at 8, 16, or 64 locations from the empty
boundary and AF thr esh old ca n b e se t at 8, 16, or 64 l ocat ions
from the full boundary. All these choices are made using the
FS0 and FS1 inputs during Master Reset .
Two or more devices may be used in parallel to create wider
data paths. If any time, the FIFO is not actively performing a
function, the chip will automatically power down. During the
power down state, supply current consumption (ICC) is at a
minimum . In iti ating any oper ati on ( by act iv at ing cont rol inputs )
will immediatel y take the device out of t he Power Down state.
The CY7C436X3V are characterized f or operati on from 0°C to
70°C. Inpu t ESD prot ection i s great er than 2001V, an d latch- up
is prevented by the use of guard rings.
Selec tion Gu ide
CY7C43643/63/83V–15
Maximum Frequency (MHz) 66.7
Maximum Access Time (ns) 10
Minimum Cycle Time (ns) 15
Minimum Data or Enable Set-Up (ns) 5
Minimum Data or Enable Hold (ns) 0
Maxim u m Flag Delay ( ns) 10
Active Power Supply
Current (ICC1) ( mA ) Commercial 60
Industrial 60
CY7C43643V CY7C43663V CY7C43683V
Density 1K x 36 4K x 36 16K x 36
P ackage 128 TQFP 128 TQFP 128 TQFP
CY7C43643V
CY7C43663V/CY7C43683V
4
PRELIMINARY
Pin Definitions
Signal Name Description I/O Function
A0–35 Port A Data I/O 36-bit Unidi rectional data port for side A.
AE Almost Empty
Flag (Port B) O Programmable almost-em pty flag synchronized to CLKA. It is LOW when the number
of words i n the FI FO 2 is l ess than or equal to the v alue in the almost-empty A o ffset
regist er, X.
AF Almost Full Flag O Programmable almost-full flag synchronized to CLKA. It is LOW when the num ber of
empty lo catio ns i n the FI FO is l ess than or equal to the v alue i n the a lmos t-fu ll A of fset
regist er, Y.
B0–35 Port B Data I/O 36-bit Unidi rectional data port for side B.
BE/FWFT Big Endian/First
Word F all
Through Select
I This is a dual-purpose pin. During Ma ster Reset , a HIGH on BE will se lect Bi g Endian
operat ion. In this case, depe nding on the bus size, the most significant b yte or word on
Port A is read from P ort B first (A-to-B data flow) or written to Port B first (B-to-A data
flo w). A LOW on BE will select Little Endia n operati on. In t his case, the least s ignif icant
byte or word on Port A is read from Port B fir st ( for A-to-B data flow) or written to Port
B fir st (B-to -A da ta flo w). After M aster Reset, this pin se lects the t iming m ode. A HIG H
on FWFT selects CY Standar d mode , a LOW selects First Word Fall Through m ode.
Once the t iming m ode has been se lected, the le vel on FWFT must be static throughout
device operation.
BM Bus Match
Select (Port B) I A HIGH on this pin enab les ei ther b yte or wor d bus widt h on P ort B, depen ding on the
state of SIZE. A LOW selects long word operation. BM works with SIZE and BE to
select the bus siz e and endian arrangement for Port B. Th e lev el of BM must be static
throughout device operation.
CLKA Port A Clock I CLKA is a c ontinuous clock t hat synchr onizes al l data t ransf ers thro ugh Port A and can
be asynchronous or coincident to CLKB. FF /IR and AF are all synchronized to the
LO W-to-HIGH transition of CLKA.
CLKB Port B Clock I CLKB is a c ontinuous clock t hat synchr onizes all data tr ansfer s through P ort B and can
be asynchronous or coincident to CLKA. FB/IR , EF /OR, A F, and AE are all synchro-
nized to the LO W-to-HI GH transition of CLKB.
CSA Port A Chip
Select ICSA must be LOW to enable a LO W-to HIGH transition of CLKA to read or write on
Port A. The A0–35 outputs are in the high-impedance state when CSA is HIG H.
CSB Port B Chip
Select ICSB must be LOW to enable a LO W-to HIGH transition of CLKB to read or write on
Port B. The B0–35 outputs are in the hi gh-impedance stat e when CSB is HI G H .
EF/OR Empty/Output
Ready Flag
(Por t B)
O This is a dual-function pi n. In the CY Stan dard Mode, the EF function is selected. EF
indicates whether or not the FIFO memory is empty. In the FWFT mode, the OR function
is selected. OR indicates the presence of valid data on A0–35 output s, availabl e for
reading . FF/OR is synchro nized to the LOW-to-HIG H transition of CLKB.
ENA P ort A Enab le I ENA must be HI GH to ena ble a L O W -to- HIGH tra nsi tion of CLKA t o read or writ e dat a
on P ort A.
ENB P ort B Enab le I ENB must be HI GH to ena ble a L O W -to- HIGH tra nsi tion of CLKB t o read or writ e dat a
on P ort B.
FF/IR Port B Full/Input
Ready Flag O This is a dual-function pi n. In the CY Stan dard Mode, the FF function is selected. FF
indic ates whether or not the FIFO memory is full. In the F WFT mode, the IR function
is selected. IR indicates whether or not there is space available for writi ng to th e FIFO
memo ry. FF /IR is synchronized to the LOW -to-HIGH transition of CLKA.
FS1/SEN Flag Offset
Select 1/ Seri al
Enable
I FS1/SEN and FS0/SD are dual-purpose inputs used for flag offset register program-
ming. During M aster Re set, FS1/ SEN and FS0/SD, together with SPM , sel ect the flag
offset programming method. Three offset register programming methods are available:
automatically lo ad one of three preset values ( 8, 16, or 64), parallel load from Port A,
and serial load. Whe n serial load is sele cted for flag offset register programming,
FS1/SEN is used as an enable sy nchronous to the LOW -to-HIGH transition of CLKA.
When FS1/SEN is LOW, a rising edge on CLKA loads the bit pr esent on FS0/SD int o
the X and Y register s. The numb er of bit writes requ ired to program the offset regis ters
is 40 f or the CY7C43 643, 48 for the CY7 C43663, and 56 f or t he CY7C 43683. Th e fir st
bit write sto res the Y-register MSB and the last bit write stores the X-register LSB.
FS0/SD Flag Offset
Select 0/ Seri al
Data
I
CY7C43643V
CY7C43663V/CY7C43683V
5
PRELIMINARY
M BA Port A M a i lbox
Select I A HIGH l evel on MBA chooses a mai lbox regi ster for a Port A r ead or write operation.
M BB Port B M a i lbox
Select I A HIGH l evel on MBB chooses a mai lbox regi ster for a Port B r ead or write operation.
When the B 0–35 o utputs are active , a HI GH level on MBB selects data from the Mail1
regist er for output and a LOW level selects FIFO output regi ster data for output.
MBF1 Mail 1 Register
Flag OMBF1 is set LOW by a LOW-to-HIGH trans it ion of CLKA tha t writes dat a to the Mail1
regist er. Writes to t he Ma il 1 register are inhibited whil e MB F1 is LOW. MBF1 is set
HIGH by a LOW-to-HI GH tra nsiti on of CLKB when a Po rt B read is select ed and MBB
is HIGH. MBF1 is set HIGH following eit her a Master or Partial Reset .
MBF2 Mail 2 Register
Flag OMBF2 is set LOW by a LOW-to-HIGH trans it ion of CLKB tha t writes dat a to the Mail2
regist er. Writes to t he Ma il 2 register are inhibited whil e MB F2 is LOW. MBF2 is set
HIGH by a LOW-to-HI GH tra nsiti on of CLKA when a Po rt A read is select ed and MBA
is HIGH. MBF1 is set HIGH following eit her a Master or Partial Reset .
MRS1 Ma ster Reset I A LOW on this pin initializes the FIFO read and writ e point ers to the first location of
memory and sets the Port B output register to all zeroes. A LOW pulse on MRS1 selects
the programming method (serial or parallel) and one of three programmable flag default
offset s. It also conf igures P ort B for bus size and endian arrangement. Four
LOW-to-HIGH transitions of CLKA and four LOW- to-HIGH transitions of CLKB must
occur whil e MRS1 is LOW.
MRS2 M aster Reset I A LOW on t his pin initializes t he Mail2 Register.
PRS P artial Reset I A LOW on this pin ini tializ es the FIFO read and write point ers to the firs t lo cation of
memory and sets the Port B outpu t regis ter to all z eroes. During Partial Reset, the
current ly selected bus size , endian arrangem ent, pro gramming method (serial or par -
allel), and program m able flag settings are all retained.
RT Retransmit I A LOW str obe on this pin will ret ransmit data on FIFO from the location of the write
pointer at the last Partial or Maste r reset.
SIZE Bus Size Sel ect I A HIGH on this pin when BM is HIGH selec ts byte bus (9- bit) size on Port B . A LO W
on this pin when BM is HIGH sele cts word (18-bi t) bus size. SIZE works with BM and
BE to select the bus size and endian arrangem ent for P ort B. The level of SIZE must
be static throughout device operation.
SPM Serial
Programming I A LO W on this pin selec ts serial programming o f partial flag of fsets. A HIGH on this pin
selects paralle l programmi ng or default offsets (8, 16, or 64).
W/RA Port A
Write/Read
Select
I A HIGH selects a write operation and a LOW selects a read operation on Port A for a
LO W-to-HIGH transi tion of CLKA. The A0–35 outputs ar e in the high-i m pedance state
when W/RA is H IGH .
W/RB Port B
Write/Read
Select
I A LOW selects a write ope ration and a HIGH selects a read operation on Port B f or a
LOW-to-HIGH transition of CLKB. The B0–35 outputs are in t he high-imped ance state
when W/RB is LOW.
Pin Definitions (continued)
Signal Name Description I/O Function
CY7C43643V
CY7C43663V/CY7C43683V
6
PRELIMINARY
Maximum Ratings[1]
(Above whi ch the useful life may be impa ired. For use r gui de-
li nes, not tested.)
Storage Temperature .................... .......... .....–65°C to +150°C
Ambient Temperature with
Power Applied...............................................–55°C to +125°C
Supply Voltage to Ground Potent ial...............–0.5V to +7.0V
DC Voltag e Applied to Outputs
in High Z State[2]......................................–0.5V to VCC+0.5V
DC Input Voltage[2]...................................–0.5V to VCC+0.5V
Output Current into Outputs (LOW).............................20 mA
Static Discharge Voltage ..... ...................... ................>2001V
(per MIL- STD-883, Method 3015)
Latch-Up Current..................................................... >200 mA
Operating Range
Range Ambient
Temperature VCC
Commercial 0°C to +70°C 3.3V ± 10%
Industrial –40°C to +85°C 3.3V ± 10%
Electrica l Characte ristics Ov er the Operating Range
Parameter Description Test Conditi ons
CY7C43643/63/83V
UnitMin. Max.
VOH Output HIGH Voltage VCC = 3. 0V,
IOH = –2.0 mA 2.4 V
VOL Output LOW Voltage VCC = 3. 0V,
IOL = 8.0 mA 0.4 V
VIH Input HIGH Voltage 2.0 VCC V
VIL Input LOW Voltage –0.5 0.8 V
IIX Input Leakage Curr ent VCC = Max. –10 +10 mA
IOZL
IOZH Output OFF, High Z
Current VSS < VO< VCC –10 +10 mA
ICC1[3] Active Power Supply
Current Com’l 60 mA
Ind 60 mA
ISB[4] Average Standby
Current Com’l 5mA
Ind 5mA
Capacitance[5]
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance TA = 25°C, f = 1 MHz ,
VCC = 3.3V 4pF
COUT Output Capacitance 8pF
Notes:
1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may aff ect device reliability.
2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed
3. This is the supply current when each input is at least one of the specified TTL voltage levels rather than 0V or VCC.
4. All inputs = VCC – 0.2V, except RCLK and WCLK (which are at frequency = 0 MHz). All outputs are unloaded.
5. Tested initially and after any design or process changes that may affect these parameters.
CY7C43643V
CY7C43663V/CY7C43683V
7
PRELIMINARY
AC Test Loads and Waveforms
Switching Charac teris t ics Ov er the Operating Range
Parameter Description
CY7C43643/63/83V
–15
UnitMin. Max.
fSClock F requency, CLKA or CLKB 67 MHz
tCLK Clock Cycl e Time, CLKA or CLKB 15 ns
tCLKH Pulse Duration, CLKA or CLKB HIG H 6ns
tCLKL Pulse Duration, CLKA or CLKB LOW 6ns
tDS Set-Up Time, A0–35 before CLKA↑ and B0–35 before CLKB↑5ns
tENS Set-Up Time, CSA, W /RA, ENA, and MBA before CLKA↑; CS B,
W/RB, ENB, and MBB before CLKB ↑5ns
tRSTS Set-Up Time, MRS1/MRS2 or PRS LO W before CLKA↑ or
CLKB↑[6] 5ns
tFSS Set- Up Time, FS0 and FS1 before MRS1/MRS2 HIGH 7.5 ns
tBES Set-Up Time, BE/FW FT before MRS1/MRS2 HIGH 7.5 ns
tSPMS Set-Up Time, SPM before MRS1/MRS2 HIGH 7.5 ns
tSDS Set-Up Time, FS0/SD before CLKA↑5ns
tSENS Set-Up Time, FS1/SEN before CLKA↑5ns
tFWS Set-Up Time, FWFT before CLKA↑0ns
tDH Hold Time, A0–35 after CLKA↑ and B0–35 after CLKB↑0ns
tENH Hold Time, CSA, W/RA, ENA, and MBA after CLKA↑; CSB , W/RB ,
ENB, and MBB after CLKB↑0ns
tRSTH Hold Time, MRS1/MRS2 or PR S LOW after CLKA↑ or CLKB↑[6] 4ns
tFSH Hold Time , FS0 and FS1 aft er MRS1/MRS2 HIGH 2ns
tBEH Hold Time, BE/FWFT aft er MRS1/MRS2 HIGH 2ns
tSPMH Hold Time, SPM after MRS1/MRS2 HIGH 2ns
tSDH Hold Ti me, FS0/SD af ter CLKA↑0ns
tSENH Hold Ti me, FS1/SEN af ter CL KA↑0ns
tSPH Hold Time, FS 1/SEN HIGH after MRS1/MRS2 HIGH 2ns
tSKEW1[7] Skew Time between CLKA↑ and CLKB↑ for EF/OR and FF/IR 7.5 ns
Notes:
6. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
7. Skew time is not a timing constraint f or proper device operation and is only included to illustrate the timing relationship between the CLKA cycle and the CLKB
cycle.
3.0V
3.3V
OUTPUT
R2=680Ω
CL=30 pF
INCLUDING
JIG AND
SCOPE
GND
90%
10%
90%
10%
≤3ns ≤3ns
OUTPUT 2.0V
Equivalentto: THÉ VENIN EQUIVALENT
200 Ω
ALL INPUT PULSES
R1=330Ω
CY7C43643V
CY7C43663V/CY7C43683V
8
PRELIMINARY
tSKEW2[7] Skew Time between CLKA↑ and CLKB↑ f or AE and AF 12 ns
tAAccess Time, CLKA↑ to A0–35 and CLKB↑ to B 0–35 310 ns
tWFF Propagati on Delay Ti me, CLKA↑ to FF /IR 210 ns
tREF Propag ati on Delay Time, CLKB↑ to EF /OR 110 ns
tPAE Propag ati on Delay Tim e, CLKB↑ to AE 110 ns
tPAF Propag ati on Delay Tim e, CLKA↑ to AF 110 ns
tPMF Propagation Delay Time, CLKA↑ to MBF1 LO W or MBF2 HIGH
and CLKB ↑ to MBF 2 LOW or MBF1 HIGH 012 ns
tPMR Propag ation Dela y Time, CLKA↑ to B0–35[8] and CLKB↑ to A 0–35[9] 312 ns
tMDV Propag ati on Delay Tim e, MBA to A0–35 Valid and MBB to B0–35
Valid 311 ns
tRSF Propag ation Dela y Time , MRS1 or PRS1 LOW to AEB LO W, AFA
HIGH, and MBF1 HIGH and MRS 2 or PRS2 LOW to AEA LOW,
AFB HIGH, and MBF2 HIGH
115 ns
tEN Enable Time, CSA or W/RA LOW to A0–35 Acti ve and CSB LOW
and W/R B H IG H to B0–35 Active 210 ns
tDIS Disable Time, CSA or W/RA HIGH to A0–35 at High Impedance and
CSB HIGH or W/RB LOW to B0–35 at High Imped ance 1 8 ns
Notes:
8. Writing data to the Mail1 register when the B0–35 outputs are active and MBB is HIGH.
9. Writing data to the Mail2 register when the A0–35 outputs are active and MBA is HIGH.
Switching Charac teris t ics Ov er the Operating Range (continued)
Parameter Description
CY7C43643/63/83V
–15
UnitMin. Max.
CY7C43643V
CY7C43663V/CY7C43683V
9
PRELIMINARY
Switching Wa vef orms
Note:
10. PRS1 must be HIGH during Master Reset.
Master Reset Loading X and Y with a Preset Value of Eight
CLKA
tRSF
tRSF
tRSF
tWFF
tFSS tFSH
tSPMS tSPMH
tBES tBEH
tRSTS
tRSTS
tFWS
CLKB
MRS1
MRS2
BE/FWFT
SPM
FS1, FS0
FF/IR
EF/OR
AE
AF
MBF1
[10]
tRSF
tRSF
CY7C43643V
CY7C43663V/CY7C43683V
10
PRELIMINARY
Notes:
11. MRS1/MRS2 must be HIGH during Partial Reset.
12. CSA=LOW, W/ RA=HIGH, MBA=LOW. It is not necessary to program offset register on consecutive clock cycles.
13. tSKEW1 is the minimum time between the rising CLKA edge and a rising CLK for FFB/IR to transition HIGH in the next cycle. If the time between the rising
edge of CLKA and rising edge of CLKB is less than tSKEW1, then FF/IR may transition HIGH one cycle later than shown.
Switching Wa vef orms (continued)
Parti al Reset ( CY Standard and FWFT Modes)
tRSF
tRSF
tRSF
tRSTS tRSTH
CLKA
CLKB
PRS
FF/IR
EF/OR
AE
AF
MBF1
[11]
tWFF
tRSF
tRSF
Parallel Programming of t he Almost-Full Flag and Almost -Empty Flag Off set Values after Reset
(CY Standard and FWFT Mo des)
tWFF
tFSS
tDS
tFSS tFSH
tFSH
tENS tENH
tDH
tSKEW1[13]
AF Offset (Y) First Word to FIFO
CLKA
MRS1
MRS2
SPM
FS1, FS0
FF/IR
ENA
A0−35
[12]
AE Offset (X)
CY7C43643V
CY7C43663V/CY7C43683V
11
PRELIMINARY
Notes:
14. It is not necessary to program offset register bits on consecutive clock cycles. FIFO write attempts are ignored until IRA is set HIGH.
15. Programmable offsets are written serially to the SD input in the order AF offset (Y) then AE offset (X).
16. Read From FIFO.
Switching Wa vef orms (continued)
Serial Programming of the Almost-Fu ll Flag and Almost-Empty Flag
Offset Values (CY Standard and FWFT Mod es)
tFSS tSPH tSENS tSENH tSENH
tSENS
tSDH
tSDS tSDH
tSDS
tWFF
AF Offset (Y) MSB
tFSS tFSH
CLKA
MRS1
MRS2
SPM
FF/IR
FS1/SEN
[14]
FS0/SD[15]
AE Offset (X) LSB
OR
tCLKH tCLKL
tENS
tDIS
tENS tEN
tCLK
tDIS
tENH
tENS tENH
tA
tA
tA
tA
tEN
tEN
tMDV
tMDV
W1[16] W2[16]
W1[16] W2[16]
W3[16]
Previous Data
No Operation
CLKB
EF/OR
CSB
W/RB
MBB
ENB
B0–35
(Standard
B0–35
(FW FT Mo de)
Port B Long-Word Read Cycle Ti ming for FIFO (CY Standard and FWFT Modes)
CY7C43643V
CY7C43663V/CY7C43683V
12
PRELIMINARY
Notes:
17. Unused word B18–35 contains all zeroes for word-size reads.
18. Unused bytes B9–17, B18–26, and B27–35 contain all zeroes for byte-size reads.
Switching Wa vef orms (continued)
OR
tDIS
tENStENH
tA
tA
tA
tA
tEN
tEN
tMDV
tMDV tDIS
tA
tA
tA
tA
Pre vious Data
Read 1
Read 1
Read 2
Read 2
Read 3
Read 3
Read 4
Read 4
Read 5
No Operation
HIGH
CLKB
EF/OR
CSB
W/RB
MBB
ENB
B0–8
(Standard
B0–8
(FWFT Mode)
Port B Word Read Cycle Timing for FIFO (CY Standard and FWFT Modes)[17]
OR
tDIS
tENS tENH
tA
tA
tA
tA
tEN
tEN
tMDV
tMDV tDIS
Previous Data
Read 1
Read 1
Read 2
Read 2
Read 3
No Operation
CLKB
EF/OR
CSB
W/RB
MBB
ENB
B0–17
(Standard
B0–17
(FWFT Mode)
Port B Byte Read Cycle Timing for FIFO (CY Standard and FWFT Modes) [18]
CY7C43643V
CY7C43663V/CY7C43683V
13
PRELIMINARY
Notes:
19. If Port B size is word or byte, EF is set LOW by the last word or byte read from the FIFO, respectively.
20. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for OR to transition HIGH and to clock the next word to the FIFO output
register in three CLKB cycles. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of OR HIGH and load
of the first word to the output register may occur one CLKB cycle later than sho wn.
Switching Wa vef orms (continued)
tCLKH tCLKL
tENS
tCLK
tEN
tENS
tEN
tA
tDS
W1
LOW
tDH
HIGH
HIGH
FIFO Empty
LOW
HIGH
LOW
Old Data in FIFO Output Register W1
tENS tENH
tREF tREF
tCLKH tCLKL
tCLK
tSKEW[20]
CLKA
CSA
W/RA
MBA
ENA
IR
A0–35
CLKB
OR
CSB
W/RB
MBB
ENB
B0–35
OR Flag Timing and Fir st Data W ord Fal l Through when FIFO is Empty (FWFT Mode) [19]
CY7C43643V
CY7C43663V/CY7C43683V
14
PRELIMINARY
Notes:
21. If Port B size is word or byte, EF is set LOW by the last word or byte read from FIFO, respectively.
22. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EF to transition HIGH in the next CLKB cycle. If the time between the
rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of EF HIGH may occur one CLKB cycle later than shown.
Switching Wa vef orms (continued)
tCLKH tCLKL
tENS
tENH
tENS
tENH
tA
tDS
W1
LOW
tDH
HIGH
HIGH
FIFO Empty
LOW
HIGH
LOW
W1
tENStENH
tREF tREF
tCLKH tCLKL
tCLK
tCLK
tSKEW[22]
CLKA
CSA
W/RA
MBA
ENA
FF
A0–35
CLKB
EF
CSB
W/RB
MBB
ENB
B0–35
EF Flag Timi ng and First Data Read Fall Through when FIFO is Empty (CY Standar d M ode) [21]
CY7C43643V
CY7C43663V/CY7C43683V
15
PRELIMINARY
Notes:
23. If Port B size is word or byte, tSKEW1 is referenced to the rising CLKB edge that reads the last word or byte write of the long word, respectively.
24. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for IR to transition HIGH in the next CLKA cycle. If the time between the
rising CLKB edge and rising CLKA edge is less than tSKEW1, then IR may transition HIGH one CLKA cycle later than shown.
Switching Wa vef orms (continued)
tCLKH tCLKL
tENStENH
tA
LOW
HIGH
HIGH
FIFO Full
LOW
HIGH
tENStENH
tWFF tWFF
tCLKH tCLKL
tCLK
tCLK
tSKEW1[24]
tDH
tDS
tENH
tENS
Pr eviou s Word in FIFO Outp ut Regis ter Next Word From FIFO
To FIFO
CLKB
CSB
W/RB
MBB
ENB
OR
B0–35
CLKA
IR
CSA
W/RA
MBA
ENA
A0–35
IR Flag Timing and Fi rst Av ailable Writ e when FIFO is Full (FWFT Mode ) [23]
CY7C43643V
CY7C43663V/CY7C43683V
16
PRELIMINARY
Notes:
25. If Port B size is word or byte, tSKEW1 is referenced to the rising CLKB edge that reads the last word or byte of the long word, respectively.
26. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for FF to transition HIGH in the next CLKA cycle. If the time between the
rising CLKB edge and rising CLKA edge is less than tSKEW1, then the transition of FF HIGH may occur one CLKA cycle later than shown.
Switching Wa vef orms (continued)
tCLKH tCLKL
tENStENH
tA
LOW
HIGH
HIGH
FIFO Full
LOW
HIGH
tENStENH
tWFF tWFF
tCLKH tCLKL
tCLK
tCLK
tSKEW1[26]
tDH
tDS
tENH
tENS
Previou s W ord in FIFO Output Register Next Word From FIFO
CLKB
CSB
W/RB
MBB
ENB
OR
B0–35
CLKA
IR
CSA
W/RA
MBA
ENA
A0−35
FF Flag Timing and First Available Write when FIFO is Full (CY Standard Mode)[25]
CY7C43643V
CY7C43663V/CY7C43683V
17
PRELIMINARY
Notes:
27. FIFO Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO output register has been
read from the FIFO.
28. D = Maximum FIFO Depth = 1K for the CY7C43643, 4K f or the 43663, and 16K for the CY7C43683.
29. If Port B size is word or byte, tSKEW2 is referenced to the rising CLKB edge that writes the last word or byte of the long word, respectively.
30. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AF to transition HIGH in the next CLKA cycle. If the time between the
rising CLKA edge and rising CLKB edge is less than tSKEW2, then AF may transition HIGH one CLKB cycle later than shown.
31. FIFO Write (CSA = LOW, W/RA = LOW, MBA = LOW), FIFO read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO output register has been
read from the FIFO.
32. If Port B size is word or byte, AE is set LOW by the last word or byte read from FIFO, respectively.
33. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AE to transition HIGH in the next CLKB cycle. If the time between the
rising CLKA edge and rising CLKB edge is less than tSKEW2, then AE may transition HIGH one CLKB cycle later than shown.
Switching Wa vef orms (continued)
Timing for AF when FIFO is Almost Full (CY Standard and FWFT Mo des)
tPAF
tENH
tENS
tPAF
tENS tENH
[D–(Y1+1)] Words in FIFO (D–Y1)Words in FIFO
tSKEW2[30]
CLKA
ENA
AF
CLKB
ENB
[27, 28, 29]
tPAE
tPAE
tENH
tENS
tSKEW2[33]
tENS tENH
X1 Word in FIFO (X1+1)Words in FIFO
CLKA
ENA
CLKB
AE
ENB
Timing for AE when FIFO is Al mos t Empty (CY St andard and FWFT Modes)[31, 32]
CY7C43643V
CY7C43663V/CY7C43683V
18
PRELIMINARY
Note:
34. If P ort B is configured for word size , data can be written to the Mail1 register using A0–17 (A18–35 are don’t care inputs). In this first case B0–17 will have valid
data (B18–35 will be indeterminate). If Port B is configured for byte size, data can be written to the Mail1 Register using A0–8 (A9–35 are don’t care inputs). In
this second case, B0–8 will have valid data (B9–35 wi ll be indeterminate).
Switching Wa vef orms (continued)
tENH
tENS
tENH
tENS
tENH
tENS
tENH
tENS
tDH
tDS
W1
tPMF tPMF
tEN tMDV tPMR
tENS tENH
tDIS
FIFO Output Register W1 (Remains valid in Mail1 Register after read)
CLKA
CSA
W/RA
MBA
ENA
A0–35
CLKB
MBF1
CSB
W/RB
MBB
ENB
Timing for Mail1 Register and MBF1 Flag (CY Standard and FWFT Modes)[34]
CY7C43643V
CY7C43663V/CY7C43683V
19
PRELIMINARY
Notes:
35. If P ort B is configured for word size , data can be written to the Mail2 register using B0–17 (B18–35 are don’t care inputs). In this first case A0–17 will have valid
data (A18–35 will be indeterminate). If Port B is configured for byte size, data can be written to the Mail2 Register using B0–8 (B9–35 are don’t care inputs). In
this second case, A0–8 will have valid data (A9–35 wi ll be indeterminate).
36. Clocks are free running in this case.
37. The flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags will be valid at tRTR.
38. For the synchronous PAE and PAF flags ( SMODE), a n appr opriate c lock cycle i s neces sary after tRTR to upda te the se flags .
Switching Wa vef orms (continued)
tENH
tENS
tENH
tENS
tENH
tENS
tENH
tENS
tDH
tDS
W1
tPMF tPMF
tEN tMDV tPMR
tENS tENH
tDIS
FIFO2 Output Register W1 (Remains valid in Mail2 Register after read)
CLKB
CSB
W/RB
MBB
ENB
B0–35
CLKA
MBF2
CSA
W/RA
MBA
ENA
A0−35
Timing for Mail 2 Register an d MBF2 Flag (CY Standard and FWFT Mod es)[35]
FIFO Retransmit Timing
ENB
RT1
tPRT tRTR
EFB/FFA
[35, 36, 37, 38]
CY7C43643V
CY7C43663V/CY7C43683V
20
PRELIMINARY
Signal Des cription
Master Reset ( MRS1, MRS2)
The FI FO memory of the CY7C43 6X3V under goes a complet e
reset by taking its associated Master Reset (MRS1, MRS2)
input LOW for at least four Port A clock (CLKA) and four Por t
B clock (CLKB) LOW-to-HIGH transitions. The Master Reset
input can switch asy nchronou sly to the clocks. A Master Reset
initializes the internal read and write pointers and forces the
Full/Input Ready flag (FF/IR) LOW, the Empty/Output Ready
flag (EF/OR) LOW, the Alm ost Empty fl ag (AE) LOW, and the
Almost Full flag (AF) HIGH. A Master Reset also forces the
Mailbox flag (MBF1, MBF2) of the parallel mailbox register
HIGH. Aft er a Master Reset, the FIFO’s Full/Input Ready flag
is set HIGH after two clock cycles to begin normal operation.
A Master Reset must be perfor med on the FIFO after power
up, bef ore data is written to i ts memory.
A LOW-to-HIGH transition on a FIFO Master Reset (MRS1,
MRS2) input latches the value of the Big Endian (BE) input,
determini ng the order by which by tes are transfer red through
Port B.
A LOW-to-HIGH transition on a FIFO reset (MRS1, MRS2)
input latches the values of the Flag select (FS0, FS1) and Se-
rial Programmin g M ode (SPM) i nputs f or choosi ng the Almost
Full and Almost Empty offset programming method (see Al-
most Empty and Almost Full f lag offset programming below).
Partia l Reset (PRS)
Each of the t wo FIFO memories of the CY7C436X3V under-
goes a limited reset by taking its associated Partial Reset
(PRS) input LO W f or at leas t four Port A clo c k (CLKA) and f our
P ort B cloc k (CLKB) L O W -to- HIGH tr ansit ions . The P artial Re-
set inputs can switch asynchronously to the clocks. A Partial
Rest in itializ es the int ernal re ad and write pointers and forces
the Full/Input Ready flag (FF/IR) LOW, the Empty/Output
Ready flag (EF/OR) LOW, the Almost Empty flag (AE) LOW,
and th e Almost Full f lag (AF) HIGH. A Partial Reset also forces
the Mai lbo x f lag (MBF1 , MBF2) of th e paral lel mai lbo x regist er
HIGH. Aft er a Par tial Reset, the FIFO’s Full/Input Ready flag
is set HIGH aft er two cloc k cycles to begin normal operation.
Whatever flag offsets, programming method (parallel or seri-
al), and t iming mode (FWFT or CY Standard mode) are cur-
rently selected at the time a Partial Reset is initiated, those
settings will remain unchanged upon completion of the reset
operation. A Partial Reset may be useful in the case where
reprogramming a FIFO following a Master Reset would be in-
convenient.
Big Endian/First Word Fall Through (BE/FWFT)
This i s a dual-p urpose pin. At the time of Master Reset, the BE
select function is active, permi tting a choice of big or little en-
dian byte arrangement for data written to or read from Por t B.
This selection determines the order by whi ch byte s (or wor ds)
of data are trans f err ed thr ough this po rt. F o r the f ol lowi ng illus-
trations, assum e that a byte (or word) bus size has been se-
lected for Port B. (Note that when Port B is configured for a
long wor d siz e , the Big Endi an func tion has n o appli cati on an d
the BE input is a “don’t care”.)
A HIGH on the BE/FWFT input when the Master Reset (MRS1,
MRS2) inputs go from LOW to HIGH will select a Big Endian
arrangement. When dat a is movi ng in the dir ection from Por t
A to Por t B, the most significant byte (word) of the long word
written to Port A will be read from P ort B first; the least signif-
icant b yte ( word) of the l ong word writt en to P o rt A will be r ead
from P ort B last. When data is mo ving in the dir ection from P ort
B to Port A, the byte (word) written to Port B first will be read
from Port A as the most significant byte (word) of the long
word; the byte (word) written to Port B last will be read from
Port A as the least significant byte (word) of the long word.
A LOW on the BE/FWFT in put when t he Master Res et (MRS1 ,
MRS2) inputs g o from LOW to HI G H will sel ect a Li ttle Endian
arrangement. When data is moving in the direction from Port
A to Por t B, the least significant byte (word) of the long word
written to Port A will be read from Port B first; the most signi f-
icant byte ( word) of the l ong word wri tten to P o rt A will be read
from P ort B last. When data is mo ving in the dir ection f rom P o rt
B to Port A, the byte (word) written to Port B first will be read
from port A as the least significant byte (word) of the long word;
the byte (word) wr itten to Port B last will be read from Por t A
as the most si gnificant byte (word) of the long word.
After Master Reset , the FWFT select func tion i s activ e, permit -
ting a choice between two possible timing modes: CY Stan-
dard Mode or First Word Fall Through (FWFT) Mode . On ce the
Master Reset (MRS1, MRS2) input is HIGH, a HIGH on the
BE/FWFT input during the next LOW-to-HIGH transition of
CLKA will select CY Standard Mode. This mode uses the Emp-
ty Flag function (EF) to indicate whether or not there are any
words present in the FIFO memory. It uses the Full Flag func-
tion ( FF) to indicate whether or not the FIFO memory has any
free space for writi ng. In CY Standard mode, ev ery word read
from the FIFO, including the firs t, must be requested using a
for mal read operat ion.
Once t he Master Reset (MRS1, MRS2) input is HIGH, a LOW
on the BE/ FWFT input duri ng the ne xt LO W- to-HIGH tr ansition
of CLKA wil l select FWFT Mode. This mode uses the Output
Ready functi on (OR) to indicate whether or not ther e is valid
data at the dat a output s (B0–35). It also uses the Input Ready
functi on (IR) to indicate whether or not the FIFO memory has
any free space for writing. In the FWFT mode, the first word
written to an empty FIFO goes dir ectly to d ata outputs , no read
request necessary. Subsequent words must be accessed by
performing a formal r ead operation.
Following M aster Reset, the l evel applied to t he BE/FW FT in-
put to choose the desired timing mode must remain static
throughout the FIFO operation.
Programmi ng the Al mos t Empty and Almost Full Flags
Two registers i n the CY7C436X3V are used to hold the offset
values f or the Almost Empty and Almost Full flags . The Port A
Almost Empty f lag (AE) offse t regi ster i s label ed X. The Port B
Almost Full flag (AF) offset regi ster is labeled Y. The index of
each regi ster name cor respond s wi th prese t va lue s during the
reset of a FIFO, prog rammed in parallel using the FIFO’ s Port
A data inputs, or programmed in serial using the Serial Data
(SD) input (see
Table 1
).
To load a FIFO’s Almos t Empty flag and Almost Full flag of fset
regist ers with one of the t hree preset values list ed in
Ta bl e 1
,
the Serial Program Mode (SPM) and at least one of the
flag-select inputs must be HIGH during the LOW -to-HIGH tran-
sition of its Master Reset input (MRS1, M RS2 ). For exa mp le,
to loa d the pr eset v a lue of 64 int o X and Y, SPM, FS0 and FS1
must be HIGH when the FIFO reset (MRS1, MRS2) returns
HIGH. When using one of the preset v alues f or the flag off sets,
the FIFO can be reset sim ultaneou sly or at different ti mes.
CY7C43643V
CY7C43663V/CY7C43683V
21
PRELIMINARY
To program the X and Y registers from Port A, perfo rm a M as-
ter Reset on both FIFOs simultaneously with SPM HIGH and
FS0 and FS1 LOW during the LOW-to-HIGH transition of
MRS1, MRS2. After this reset is complete, the first four writes
to the FIFO do not store data in RAM but load the offset regis-
ters i n the order Y and X. The Por t A data inputs used by the
off set registers a re (A7–0), (A8–0), ( A9–0), (A11–0), or (A13–0),for
the CY7C43 6X3V, respe ctiv ely. The highe st numbered input is
used as the most significant bit of the binary number i n each
case. Valid program m ing values for the registers range from 1
to 1012 f or the CY7C43643V; 1 to 4092 for the CY7C43663V;
1 to 16380 for the CY7C43683V. After all the offset registers
are programmed from Port A, the Port B Full/Input Ready
(FF/IR) is set HIGH and both FIFOs begin normal operati on.
To program the X and Y registers serially, initiate a Master
Reset wit h SPM LO W, FS0/SD LO W and FS1/ SEN HIGH dur-
ing the LOW-to-HIGH transition of MRS1, MRS2. After this
reset is complete, the X and Y register values are loaded
bit -wise through th e FS0/SD input on each LOW -to- HIGH tran-
sit ion of CLKA th at the FS1/SEN i nput i s LO W. Th irty- tw o, t hir-
ty- six, f orty, f orty-eight, or fifty- six bit writes are n eeded to com-
plet e the p rogr amming f or t he CY7C43 6X3V, re specti vel y. Th e
four registers are written in the order Y then finally X. The
fi rst-b it write st ores the most si gnificant bit of the Y reg ister an d
the l ast-bit write stores the least si gnificant bit of the X register .
Each register value can be programmed from 1 to 1020
(CY7C43643V), 1 to 4092 (CY7C43663V), or 1 to 16380
(CY7C43683V).
When the opt ion t o p rogr am t he off set r egist ers seriall y is cho-
sen, the Port A Full/Input Ready (FF/IR) flag remains LOW
until all register bits are written. FF/IR is set HIGH by the
LOW- to-HIGH transition of CLKA after the last bit is loaded to
allow normal FIFO operation. The Port B Full/Input ready
(FF/IR) flag also remai ns LOW throughou t the s eria l program -
ming process, until all register bits are wri tten.
SPM, FS0/SD, and FS1/SEN function the same way in both
CY Standard and FWFT modes.
FIFO Write/Read Operation
The state of the Port A dat a (A0–35) lines is contr olled by Port
A Chip Select (CSA) and Port A Write/Read Select (W/RA).
The A0–35 lines are in the high-im pedance state when either
CSA or W/RA is HIGH. The A0–35 lines are active outputs
when bot h CS A and W/RA are LOW.
Data is loaded into the FIFO from the A0–35 inputs on a
LO W-to-HIG H tr ansition of CLKA when CSA is LOW, W/RA is
HIGH, ENA is HIGH, MBA is LOW, and FF/IR is HIGH. (see
Table 2
). FIFO writes on Por t A are independent of any con-
current Por t B operation.
The Port B control signals a re i dentical to those of Port A with
the exception that the Por t B Write/ Read select (W/RB) is the
invers e of t he Por t A Write/Read select (W/RA). The state of
the Por t B dat a (B0–35) lines is controlled by the Por t B Chip
Selec t (CSB) a nd Port B Write/ Read se lec t (W/RB). The B0–35
lines are in the high-impedance state when either CSB is
HIGH or W/RB is LOW. The B0–35 lines are active outputs
when CSB is LOW and W/RB is HIGH.
Data is read from the FIFO to the B0–35 outputs by a
LO W-to-HIG H tr ansition of CLKB when CSB is LOW, W/RB is
HIGH, ENB i s HIGH, MBB i s LOW, and EF/OR is HIGH (see
Table 3
). FIFO rea ds and writ es on Port B are independent of
any concurren t Port A operation.
The set-up and hold time constr aints to the port clo cks for the
port Chip Selects and Write/read selects are only for ena bling
write and read operations and are not related to high-imped-
ance cont rol of t he data outp uts. If a port enab le is LO W during
a clock cycle, the port’s Chip Select and Write/Read select
ma y change stat es during the set-up and ho ld t ime window of
the cycle.
When operating the FIFO in FWFT Mode and the Output
Ready flag is LOW, the ne xt word written is automatically sent
to the FIFO ’s output reg ister by the LOW-to -HIGH tr ansition of
the port clock that sets the Output Ready flag HIGH, data re-
sidi ng in t he F IFO’s memory arra y i s cl oc ked t o t he out put reg -
ister only when a read i s selec ted usi ng t he port’ s Ch ip Sel ect ,
Write/Rea d select, Enable, and Mailbox select.
When ope rati ng the FIF O in CY St andard M ode, r egardle ss of
whether t he Emp ty Fl ag is LOW or HIGH, data resi ding in the
FIFO’s memory array is clocked to the output register only
when a read is selected using the port’s Chip Select,
Write/Rea d select, Enable, and Mailbox select.
Synchronized FIFO Flags
Each FIFO is synchronized to its port clock through at least
two flip- flop stages . This is done to impro ve flag-s ignal reliabi l-
ity by reducing the probabil ity of the metastable events when
CLKA and CLKB operate asynchronously to one another.
EF/OR and AE are synchronized to CLKA. FF/IR and AF are
synchronized to CLKB.
Table 4
sho ws th e relat ionshi p of each
port fl ag to the FIFO.
Empty/Output Ready Flags (EF/OR)
These are dual purpose flags. In the FW FT M ode, the Output
Ready (OR) fun ction i s select ed. When the O utput Read y flag
is HIGH, new data i s present i n the FIFO ou tput regi ster . When
the Output Ready flag is LOW, the previous data word is
present in the FIFO output register and a ttempted F IFO reads
are ignored.
In the CY Standard Mode, the Empty Flag (EF) function is
selected. When the Empty Flag is HIGH, data is available in
the FIFO’s RAM memory for reading to the output register.
When Empty Flag is LOW, the previous data word is present
in the FIFO output register and att empted FIFO reads are ig-
nored.
The Empty/Out put Ready fla g of a FIFO is synchr onized to t he
port clock that reads data from its array. For both the FWFT
and CY Standard modes, the FIFO read pointer is increment -
ed each time a new word is clocked t o its output register. The
state machi ne t hat controls an Output Ready fl ag m onitors a
write p ointer and read poin ter comparator that indicates when
the FIFO SRAM status is empty, empty+1, or empty+2.
In FWFT Mode, from the ti me a wor d is written to a FI FO , it can
be shifted to the FIFO output register in a minimum of three
cycles of the Output Ready flag synchronizing clock. There-
fore, an Output Ready flag is LOW if a word in memory is the
next data to be sent to t he FIFO output register and three cy-
cles ha ve not elapsed s ince the time t he word was wri tten. The
Output Ready flag of the FIFO remains LOW until the third
LO W-to-HIGH transition of the synchronizing clock oc curs, si-
multa neously forcing th e Outpu t Ready fl ag HIGH and shi fti ng
the word to the FIFO output regi ster.
In the CY Standard Mo de, from the tim e a word is written to a
FIFO, the Empty Flag wil l indicate the presence of data avail-
able f or reading in a minim um of two cyc les of the Em pty Flag
CY7C43643V
CY7C43663V/CY7C43683V
22
PRELIMINARY
synchronizing clock. Therefore, an Empty Flag is LOW if a
w ord in memory is the next data to be sent to the FIFO output
register and two cycles have not elapsed since the time the
word was written. The Em pty Flag of the FIFO remains LOW
until the second LOW-to-HIGH transition of the synchronizing
cloc k occurs , forcing t he Empty Fl ag HIGH ; onl y then can data
be read.
A LOW-to-HIGH transition on an Empty/Output Ready flag
synchronizing clock begins the first synchro nization cycle of a
write if the clock transition occurs at time tSKEW1 or greater
after the write. Otherwise, the subsequent clock cycle can be
the fi rst synchr onization cycle.
Full/ Input Ready Flags (FF/IR)
This is a dual-purpose flag. In FWFT Mode, the Input Ready
(IR) function is selected. In CY St andard Mode, the Full Flag
(FF) function is selected. For both timing modes, when the
Full /Inpu t Ready fl ag is HI GH, a memory l ocatio n is free i n th e
SRAM to receive new data. No memory locations are free
when the Full/Input Ready flag is LOW and attempted writ es
to the FIFO are ignored.
The Full /Input Read y flag of a FIFO is synchr onized to the port
cloc k that writes dat a to its arra y. For both FWFT and CY Stan-
dard modes, each time a word is written to a FIFO, its write
pointer is incremented. The state machine that controls a
Full /Inpu t Ready f l ag monit ors a wri te poi nter an d re ad point er
comp arator that i ndicates when the FIFO SRAM status is f ull ,
full –1, or full–2. Fr om the time a word is read from a FIFO, it s
previous memory location is ready to be written to in a mini-
mum of two cycles of the Full/Input Ready flag synchronizi ng
clock. Therefore, an Full /Input Ready flag is LOW if less than
two cycles of the Full/Input Ready flag synchronizing clock
have elapsed since the next m emory wr ite location has been
read. The second LOW-to-HIGH transition on the Full/Input
Read y fl ag synchroni zing cloc k after the read sets the Full/I n-
put Ready flag HIGH.
A LO W -to -HIGH tr ansiti on on a Full /Input Ready flag s ynchro-
nizing clock begins the first synchronization cycle of a read if
the clock transition occurs at tim e tSKEW1 or greater after the
read. Otherwise, the subsequent clock cycle can be the first
synchronization cycle .
Almost Empty Flags (AE)
The Almost Empty flag of a FIFO is synchronized to the port
clock that reads data from its array. The state machine that
controls an Almost Empty flag monitors a write pointer and
read pointer comparator that indicates when the FIFO SRAM
status is almost empty, almost empty+1, or almost empty+2.
The Alm ost Empty state i s defined by the contents of register
X f or AE. Thes e regi sters are loaded with pr eset values d uring
a FIFO reset, programmed f rom Por t A, or programmed ser i-
ally (see Almost Empty flag and Almost Full flag offset pro-
gramming abov e). An Almost Empty flag is LOW when its FIFO
contains X or less words and is HIGH when its FIFO conta ins
(X+1) or more words. A data word present in the FIFO output
register has been read from memory.
Two LOW-to-HIGH transitions of the Almost Empty flag syn-
chronizing clock are required after a FIFO write for its Almost
Empty flag to reflect the new l evel of fill. Theref ore, the Almost
Full flag of a FIFO containing (X+1) or more words remains
LO W if two cycles of its synchroni zing cloc k have not elapse d
since the write that filled the memory to the (X+1) level. An
Almost Empty flag is set HIGH by the second LOW-to-HIGH
transition of its synchronizing clock after the FIFO write that
fills memory to the ( X+1) le vel. A LOW -to-HIGH t ransition of an
Almost Empty flag synchronizing clock begins the first syn-
chronization cycle if it occurs at time tSKEW2 or greater after
the write that fills the FIFO to (X+1) words. Otherwise, the sub-
sequent synchronizing clock cycle may be the first synchroni-
zation cycle.
Almost Full Flags (AF)
The Almost Full flag of a FIFO is synchron ized to the port cl ock
that writ es da ta to i ts ar ra y. The s tate mac hi ne that contr ols an
Almost Full fla g mon itors a write po inter a nd read po inter c om-
parator that indicates when the FIFO SRAM status is almost
full, almost full–1, or almost full–2. The Almost Full state is
defined by the contents of register Y for AF. These registers
are loaded with preset values during a FIFO reset, pro-
grammed from Port A, or programmed serially (see Almost
Empty f lag and Al most Full f lag offset pr ogr amming above). An
Almost Full fl ag is LOW when the number of words in it s FIFO
is greater than or equal to (1024–Y), (4096–Y), or (16384–Y),
fo r the CY7 C436X3V r espect ive ly. An Alm ost Ful l flag is HIGH
when the number of words in its FIFO is less than or equal to
[1024–(Y+1)], [4096–(Y+1)], or [16384–(Y+1)], for the
CY7C436X3V respectively. Note that a data word present in
the FIFO output registe r has been read fr om memo ry.
Two LOW-to-HIGH transitions of the Almost Full fl ag synchro-
nizing clock are required af ter a FIFO read for its Almost Full
flag to reflect the new level of fill. Therefore, the Almost Full
flag of a FIFO containing [1024/4096/16384–(Y+1)] or less
words remains LOW if two cycles of its synchronizing clock
have not elapsed since the read that reduced the number of
words in memory to [ 102 4/4096/ 16384 –(Y+1)] . An Al most F ull
flag is set HIGH by the second LOW-to-HIGH transition of its
synchro nizin g cloc k after th e FIFO re ad that re duces t he n um-
ber of words in memory to [1024/4096/16384–(Y+1)]. A
LOW-to-HIGH transition of an Almost Full flag synchronizing
clock begins t he first synchronization cycle if it occurs at time
tSKEW2 or greater after the read that reduces the number of
words i n memory to [1024/4096/16384– (Y+1)]. Oth erwise, the
subsequent synchronizing clock cycle may be the first syn-
chronization cycle.
Mailbox Registers
Each FIFO has a 36-bit bypass regi ster to pass command and
control information betw een Port A and Port B without putting
it in queue. The Mailbox Select (MBA, MBB) inputs choose
between a mail register and a FIFO for a port data transfer
operation. The usable widt h of bot h the Mail1 and Ma il 2 regis -
ters matches the selected bus size for Port B.
A LOW-to-HIGH transition on CLKA writes A0−35 data to the
Mail1 Reg ister when a P ort A write is se lecte d b y CSA, W/R A,
and ENA with MBA HIGH. If the selected Port A bus size is
also 36 bit s, then the usable width of the Mail1 Regist er em-
plo ys data li nes A0−35. If the selected P ort A bus size is 18 bit s,
then th e usab le wi dth of the M ail 1 Regist er emp lo ys data l ines
A0−17. (In this case, A18−35 ar e don’t care i nputs .) I f the s elect -
ed Port A bus siz e is 9 bits, then the usable widt h of the Mail1
Register employs data lines B0−B8. (In this case, A9−35 are
don’t care inputs.)
A LOW-to-HIGH transition on CLKB writes B0−35 data to the
Mail2 Regi ster wh en a P ort B write i s selec ted by CSB, W/RB,
and ENB with MBB HIGH. If the selected Port B bus size is
CY7C43643V
CY7C43663V/CY7C43683V
23
PRELIMINARY
also 36 bits, then the usable width of the Mail2 Register em-
plo ys data li nes B0–35. If the se lected P ort B bus siz e is 18 bits ,
then t he us abl e width of the Mai l2 Re gister em plo ys data lines
B0–17. ( In th is case , B 18–35 are don’ t car e input s.) If t he selec t-
ed Port B bus s ize is 9 bits, then t he usable wi dth of the Mail2
Regis ter emplo ys data lin es B0−8. (In this case, B9−35 are don’ t
care i nputs.)
Writing data to a mail register sets its corresponding flag
(MBF1 or MBF2) LOW. Attempted writes t o a mail regi ster ar e
ignored while the mail fl ag is LOW.
When data outputs of a port are active, the data on the bus
comes from the FIFO output register when the port Mailbox
Select input is LOW and from the mail register when the por t
Ma ilbox Sele c t in pu t is HIG H .
The Mail1 Register Flag (MBF1) is set HIGH by a
LOW-to-HIGH transition on CLKB when a Por t B read is se-
lected by CSB, W/RB, and ENB with MBB HIGH. For a 36-bit
bus size, 36 bits of mailbox data are placed on B0–35. For an
18-bi t bus size , 18 bits of mai lbox dat a are placed on B0–17. (In
this case, B18–35 are indet erminate.) F or a 9-bit bus siz e, 9 bits
of mailbox data are placed on B0–8. (In this case, B9–35 are
indeterminate.)
The Mail2 regist er Flag ( MBF2) is set HIGH by a LOW-to-HIGH
transition on CLKA when a Port A read is selected by CSA,
W/RA, and ENA with MBA HIGH.
For a 36-bit bus size, 36 bits of mailbox data are placed on
A0–35. For an 18-bit bu s size, 18 bits of mailb ox data are placed
on A0–17. (I n thi s ca se, A 18–35 are indeterminate.) For a 9-bit
bus size, 9 bits of mailbox data are placed on A0–8. (In this
case, A9–35 are indeterminate.)
The data in a mail register rem ains intact after it is read and
changes only when new data is written to the register. The
Endian Select feature has no effect on the mailbox data.
Bus Sizi ng
The Port B bus can be configured in a 36-bit long word, 18-bit
word, or 9- bit byte for mat for data read from FIFO. The levels
applied to the Port B Bus Size Select (SIZE) and the Bus
Match Se lect (BM) determine the P ort B b us size . These lev els
shoul d be static through out FIF O operati on. Both bus size se-
lections are implemented at the completion of Master Reset,
by the time the Full /Input Ready flag is set HIGH .
Two di fferent methods for sequencing data transfer are avai l-
able for Port B when the bus size selection is either byte-or
word-size. The y are ref erred to as Big Endian (most sign ific ant
byte first) and Little Endian (least significant byte first). The
level applied to the Big Endian Select (BE) input during the
LOW-to-HIGH transition of MRS1/MRS2 selects the endian
method th at wil l be act ive duri ng FIFO oper atio n. BE is a d on’t
care input when the bus size selected for Port B is long word.
The endian me thod is implemented at the completion of Mas-
ter Reset , by the time the Ful l/Input ready flag is set HIGH.
Only 36-bit long word data is written to or read from the two
FIFO memories on the CY7C436X3V. Bus-matching opera-
tions are done after data is read from the FIFO. These
bus-matching operations are not available when transferring
data via mailbox registers. Furthermore, both the word- and
byte -size b us selectio ns limit the width of the data bu s that can
be used for mail register operations. In this case, only those
byte lanes belonging t o the selected word- or byte- size b us can
carry mailbox data. The remaining data outputs will be inde-
terminate . The r em aining data inputs will be don’t care inputs.
For example, when a word-size bus is selected, then mailbox
data can be tr ansmitted only between A 0–17 and B0–17. When
a by te- siz e b us i s sel ected, t hen mail bo x dat a can be t r ansmit -
ted only between A0–8 and B0–8.
Bus-Matchi ng FIFO Reads
Data is read from the FIFO RAM in 36-bit long word incre-
ments. If a long word bus size is implemented, the entire long
word immediately shifts to the FIFO output register. If byte or
word size is implemented on Por t B, onl y the first one or two
byte s appea r on the sel ected portion of the FIFO out put reg is-
ter, with the rest of the long word stored in auxiliary registers.
In this case , subsequent FIFO reads ou tput the re st of the long
word to the FIFO output register.
When reading data from the FIFO in the byte or word format,
the unused B0–35 outputs are indeterminate.
Retransmit (R T)
The retransmit feature is benefici al when transferr ing packets
of data. It enables the recei pt of data to be acknowledged by
the recei ver and retransmit ted if necessary.
The retransmit feature is intended for use when a number of
writes equal to or less than the depth of the FIFO have oc-
curred and at l east one word has been read since the last reset
cycle. A LOW pulse on RT r esets the int er nal read pointer to
the firs t physi cal location of the FIF O. CLKA and CLKB ma y be
free running but must be disabled during and tRTR after the
retransmit pulse. W ith ever y valid read cycle after retransmit,
pre vi ously accessed dat a is r ead a nd the r ead point er is incre -
mented un ti l i t is equal to t he writ e po inter. Fla gs a re go v erned
by the re lati ve lo cation s of the read and write poi nters and are
updated during a retransmit cycle. Data written to the FIFO
after acti vat ion o f R T are t r ansmit ted al so . The full depth of the
FIFO can be repeatedly retransmitted.
CY7C43643V
CY7C43663V/CY7C43683V
24
PRELIMINARY
A
A35–27 B
A26–18 C
A17–9 D
A8–0
A
B35–27 B
B26–18 C
B17–9 D
B8–0
B35–27 A
B17–9 B
B8–0
C
B17–9 D
B8–0
C
B17–9 D
B8–0
A
B17–9 B
B8–0
A
B8–0
B
B8–0
C
B8–0
D
B8–0
B35–27
B35–27
B35–27
B35–27
B35–27
B35–27
B35–27
B26–18
B26–18
B26–18
B26–18
B26–18
B26–18
B26–18
B26–18
B17–9
B17–9
B17–9
B17–9
(a) LONG WORD SIZE
(b) WORD SIZE – BIG ENDIAN
(c) WORD SIZE – LITTLE ENDIAN
(d) BYTE SI ZE – BIG ENDIAN
BE BM SIZE
XLX
BE BM SIZE
HHL
BE BM SIZE
LHL
BE BM SIZE
HHH
Writ e to FI FO
Read from
FIFO
1st: Read from
FIFO
2nd: Read from
FIFO
1st: Read from
FIFO
2nd: Read from
FIFO
1st: Read from
FIFO
2nd: Read from
FIFO
3rd: Read from
FIFO
4th: Read from
FIFO
BYTE ORDER ON
PORT A:
D
B8–0
C
B8–0
B
B8–0
A
B8–0
B35–27
B35–27
B35–27
B35–27
B26–18
B26–18
B26–18
B26–18
B17–9
B17–9
B17–9
B17–9
( e) BYT E SIZE – LITT L E END IAN
BE BM SIZE
LHH
1st: Read from
FIFO
2nd: Read from
FIFO
3rd: Read from
FIFO
4th: Read from
FIFO
CY7C43643V
CY7C43663V/CY7C43683V
25
PRELIMINARY
..a ble
Table 1. Flag Programming
SPM FS1/SEN FS0/SD MRS1/MRS2 X and Y Registers[39]
H H H ↑64
H H L ↑16
H L H ↑8
H L L ↑P arallel prog ramming via Port A
L H L ↑Serial programmi ng via SD
L H H ↑Reserved
L L H ↑Reserved
L L L ↑Reserved
Table 2. Port A Enable Function
CSA W/RA ENA MBA CLKA A0–35 Outputs Port Functi on
H X X X X In high-impedance state None
L H L X X In high-impedance stat e None
L H H L ↑I n high-impedan ce state FIFO write
L H H H ↑I n high-impedan ce state Mail1 write
L L L L X Active , Mail2 registe r None
L L H L ↑Active, Mai l2 register None
L L L H X Active , Mail2 registe r None
L L H H ↑Active, Mail2 register Mail2 read (set MBF2 HIGH)
Table 3. Port B Enable Function
CSB W/RB ENB MBB CLKB B0–35 Outputs Port Function
H X X X X In high-im pedance state None
L L L X X In high-impedance state None
L L H L ↑In high-impedance state None
L L H H ↑I n high-impedan ce state Mail2 write
L H L L X Active, FIFO output register None
L H H L ↑Activ e, FIFO output r egister FIFO read
L H L H X Active , Mail1 regist er None
L H H H ↑Active, Mail1 register Mail1 read (set MBF1 HIGH)
Note:
39. X register holds the offset for AE; Y register holds the offset for AF.
CY7C43643V
CY7C43663V/CY7C43683V
26
PRELIMINARY
Table 4. FIFO Flag Operation (CY Standard and FWFT Modes)
Number of Words in FIFO Memory[40,41,42,43] Sync hron ized to CL K A Synchronized to CLKB
CY7C43643V CY7C43663V CY7C43683V EF/OR AE AF FF/IR
0 0 0 L L H H
1 TO X1 1 TO X1 1 TO X1 H L H H
(X1+1) to
[1024–(Y1+1)] (X1+1) to
[4096–(Y1+1)] (X1+1) to
[16384–(Y1+1)] H H H H
(1024–Y1) to 1023 (4096–Y1) to 4095 (16384–Y1) to
16383 H H L H
1024 4096 16384 H H L L
Table 5. Dat a Size f or FIFO Long-Word Reads
Size Mode [44] Data Writte n to FIFO2 Data Read From FIFO2
BM SIZE BE A35–27 A26–18 A17–9 A8–0 B26–18 B26–18 B17–9 B8–0
LXXABCDABCD
Table 6. Dat a Size f or Word Reads
Size Mode[44] Data Written to FIFO Read No. Da ta Read Fr om FIFO
BM SIZE BE A35–27 A26–18 A17–9 A8–0 B17–9 B8–0
HLHABCD1AB
2CD
HLLABCD1CD
2AB
Table 7. Dat a Size f or byte Reads from FIFO
Size Mode[44] Data Wr itten to FIFO Read No. Data Read Fr om
FIFO
BM SIZE BE A35–27 A26–18 A17–9 A8–0 B8–0
HHHABCD1 A
2B
3C
4D
HHLABCD1 D
2C
3B
4A
Notes:
40. X1 is the almost-empty offset for FIFO used by AE. Y is the almost-full offset for FIFO used by AF. Both X1 and Y1 are selected during a FIFO reset or port
A programming.
41. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
42. Data in the output register does not count as a “word in FIFO memory”. Since in FWFT mode, the first word written to an empty FIFO goes unrequested to
the output register (no read operation necessary), it is not included in the FIFO memory count.
43. The OR and IR functions are active during FWFT mode; the EF and FFA functions are active in CY Standard mode.
44. BE is selected at Master Reset; BM and SIZE must be static throughout device operation.
CY7C43643V
CY7C43663V/CY7C43683V
PRELIMINARY
© Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no res p onsibility for the use
of any circuit ry other than circuitry embodied in a Cypress Semiconduc tor product. Nor does it conv ey or im ply any lice nse under patent or other rights. C ypress Semi condu ctor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in sign ificant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
Document #: 38-00703
3.3V 1K x3 6 Unidirectional Synchronous FIFO w/ bus matching
Speed
(ns) O rde ring C ode Package
Name Package
Type Operating
Range
15 CY7C43643V–15AC A128 128-Lead Thin Quad Flat P ackage Commercial
3.3V 4K x3 6 Unidirectional Synchronous FIFO w/ bus m atching
Speed
(ns) Ordering Code Package
Name Package
Type Operating
Range
15 CY7C43663V–15AC A128 128-Lea d Thin Quad Flat P ackage Commercial
3.3V 16K x36 Unidirectional Synchr onous FIFO w/ bus matching
Speed
(ns) Ordering Code Package
Name Package
Type Operating
Range
15 CY7C43683V–15AC A128 128-Lead Thin Quad Fla t Package Commercial
Package Di ag r am
128-Pin Thin Plastic Quad Flat pack (14 x 20 x 1.4 mm) A128
51-85101
