V PRELIMINARY CY7C43643V CY7C43663V/CY7C43683V 3.3V 1K/4K/16K x36 Unidirectional Synchronous FIFO w/ Bus Matching * Fully asynchronous and simultaneous read and write operation permitted * Mailbox bypass register for each FIFO * Parallel and Serial Programmable Almost-Full and Almost-Empty flags * Retransmit function * Standard or FWFT mode user selectable * Partial Reset * Big or Little Endian format for word or byte bus sizes * 128-pin TQFP packaging * 3.3V pin-compatible, feature enhanced, density upgrade to IDT723623/33/43 family * Easily expandable in width and depth Features * High-speed, low-power, Unidirectional, first-in first-out (FIFO) memories w/ bus matching capabilities * 1Kx36 (CY7C43643V) * 4Kx36 (CY7C43663V) * 16Kx36 (CY7C43683V) * 0.35-micron CMOS for optimum speed/power * High-speed 67-MHz operation (15 ns read/write cycle times) * Low power -- ICC= 100 mA -- ISB= 5 mA Logic Block Diagram MBF1 CLKA W/RA MBA RT MRS1 MRS2 PRS FIFO, Mail1 Mail2 Reset Logic CLKB CSB W/RB ENB MBB BE BM SIZE Port-B Control Logic Read Pointer Write Pointer FF/IR EF/OR AE Status Flag Logic AF SPM FS0/SD FS1/SEN A0-35 1K/4K/16K x36 Dual Ported Memory Input Register ENA Output Register Port-A Control Logic Bus Matching Mail 1 Register CSA 36 Programmable Flag Offset Registers 36 B0-35 Timing Mode BE/FWFT Mail 2 Register MBF2 Cypress Semiconductor Corporation * 3901 North First Street * San Jose * CA 95134 * 408-943-2600 October 2, 1998 CY7C43643V CY7C43663V/CY7C43683V PRELIMINARY TQFP Pin Configuration NC EF/OR NC GND CSB W/RB ENB MBF1 VCC AE VCC AF NC MBF2 MBA MRS1 FS0/SD GND GND FS1/SEN MRS2 MBB 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 CSA FF/IR NC PRS Top View CY7C43683V 2 CLKB VCC VCC B35 B34 B33 B32 GND GND B31 B30 B29 B28 B27 B26 RT 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 B25 B24 BM GND GND B6 VCC B7 B8 B9 B2 B3 B4 B5 GND A11 A10 CY7C43663V GND A5 A4 A3 SPM VCC A2 A1 A0 GND B0 B1 FWFT/STAN GND A22 VCC A21 A20 A19 A18 GND A17 A16 A15 A14 A13 VCC A12 CY7C43643V 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 GND A29 A28 A27 A26 A25 A24 A23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 A9 A8 A7 A6 W/RA ENA CLKA GND A35 A34 A33 A32 VCC A31 A30 B23 B22 B21 B20 B19 B18 GND B17 B16 SIZE VCC B15 B14 B13 B12 GND B11 B10 CY7C43643V CY7C43663V/CY7C43683V PRELIMINARY access that word (along with all other words residing in memory). In the First Word Fall Through Mode (FWFT), the first long-word (36-bit wide) written to an empty FIFO appears automatically on the outputs, no read operation required (nevertheless, accessing subsequent words does necessitate a formal read request). The state of the FWFT/STAN pin during FIFO operation determines the mode in use. Functional Description The CY7C436X3V is a monolithic, high-speed, low-power, CMOS Unidirectional Synchronous (clocked) FIFO memory which supports clock frequencies up to 67 MHz and has read access times as fast as 10 ns. Two independent 1K/4K/16K x 36 dual-port SRAM FIFOs on board each chip buffer data in opposite directions. FIFO data on Port B can be output in 36-bit, 18-bit, or 9-bit formats with a choice of big- or little-endian configurations. The FIFO has a combined Empty/Output Ready flag (EF/OR) and a combined Full/Input Ready flag (FF/IR). The EF and FF functions are selected in the CY Standard Mode. EF indicates whether the memory is full or not. The IR and OR functions are selected in the First Word Fall Through Mode. IR indicates whether or not the FIFO has available memory locations. OR shows whether the FIFO has data available for reading or not. It marks the presence of valid data on the outputs. The CY7C436X3V is a synchronous (clocked) FIFO, meaning each port employs a synchronous interface. All data transfers through a port are gated to the LOW-to-HIGH transition of a port clock by enable signals. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple Unidirectional interface between microprocessors and/or buses with synchronous control. The FIFO has a programmable Almost Empty flag (AE) and a programmable Almost Full flag (AF). AE indicates when a selected number of words written to FIFO memory achieve a predetermined "almost empty state." AF indicates when a selected number of words written to the memory achieve a predetermined "almost full state." Communication between each port may bypass the FIFOs via two mailbox registers. The mailbox registers' width matches the selected Port B bus width. Each mailbox register has a flag (MBF1 and MBF2) to signal when new mail has been stored. IR and AF are synchronized to the port clock that writes data into its array. OR and AE are synchronized to the port clock that reads data from its array. Programmable offset for AE and AF are loaded in parallel using Port A or in serial via the SD input. Three default offset settings are also provided. The AE threshold can be set at 8, 16, or 64 locations from the empty boundary and AF threshold can be set at 8, 16, or 64 locations from the full boundary. All these choices are made using the FS0 and FS1 inputs during Master Reset. Two kinds of reset are available on the CY7C436X3V: Master Reset and Partial Reset. Master Reset initializes the read and write pointers to the first location of the memory array, configures the FIFO for big- or little-endian byte arrangement and selects serial flag programming, parallel flag programming, or one of the three possible default flag offset settings, 8, 16, or 64. The FIFO also has a Master Reset pin, MRS1/MRS2. Partial Reset also sets the read and write pointers to the first location of the memory. Unlike Master Reset, any settings existing prior to Partial Reset (i.e., programming method and partial flag default offsets) are retained. Partial Reset is useful since it permits flushing of the FIFO memory without changing any configuration settings. The FIFO has its own independent Partial Reset pin, PRS. Two or more devices may be used in parallel to create wider data paths. If any time, the FIFO is not actively performing a function, the chip will automatically power down. During the power down state, supply current consumption (ICC) is at a minimum. Initiating any operation (by activating control inputs) will immediately take the device out of the Power Down state. The CY7C436X3V have two modes of operation: In the CY Standard Mode, the first word written to an empty FIFO is deposited into the memory array. A read operation is required to The CY7C436X3V are characterized for operation from 0C to 70C. Input ESD protection is greater than 2001V, and latch-up is prevented by the use of guard rings. Selection Guide CY7C43643/63/83V-15 Maximum Frequency (MHz) 66.7 Maximum Access Time (ns) 10 Minimum Cycle Time (ns) 15 Minimum Data or Enable Set-Up (ns) 5 Minimum Data or Enable Hold (ns) 0 Maximum Flag Delay (ns) Active Power Supply Current (ICC1 ) (mA) 10 Commercial 60 Industrial 60 CY7C43643V CY7C43663V CY7C43683V Density 1K x 36 4K x 36 16K x 36 Package 128 TQFP 128 TQFP 128 TQFP 3 CY7C43643V CY7C43663V/CY7C43683V PRELIMINARY Pin Definitions Signal Name Description I/O Function A0-35 Port A Data I/O 36-bit Unidirectional data port for side A. AE Almost Empty Flag (Port B) O Programmable almost-empty flag synchronized to CLKA. It is LOW when the number of words in the FIFO2 is less than or equal to the value in the almost-empty A offset register, X. AF Almost Full Flag O Programmable almost-full flag synchronized to CLKA. It is LOW when the number of empty locations in the FIFO is less than or equal to the value in the almost-full A offset register, Y. B0-35 Port B Data I/O 36-bit Unidirectional data port for side B. BE/FWFT Big Endian/First Word Fall Through Select I This is a dual-purpose pin. During Master Reset, a HIGH on BE will select Big Endian operation. In this case, depending on the bus size, the most significant byte or word on Port A is read from Port B first (A-to-B data flow) or written to Port B first (B-to-A data flow). A LOW on BE will select Little Endian operation. In this case, the least significant byte or word on Port A is read from Port B first (for A-to-B data flow) or written to Port B first (B-to-A data flow). After Master Reset, this pin selects the timing mode. A HIGH on FWFT selects CY Standard mode, a LOW selects First Word Fall Through mode. Once the timing mode has been selected, the level on FWFT must be static throughout device operation. BM Bus Match Select (Port B) I A HIGH on this pin enables either byte or word bus width on Port B, depending on the state of SIZE. A LOW selects long word operation. BM works with SIZE and BE to select the bus size and endian arrangement for Port B. The level of BM must be static throughout device operation. CLKA Port A Clock I CLKA is a continuous clock that synchronizes all data transfers through Port A and can be asynchronous or coincident to CLKB. FF/IR and AF are all synchronized to the LOW-to-HIGH transition of CLKA. CLKB Port B Clock I CLKB is a continuous clock that synchronizes all data transfers through Port B and can be asynchronous or coincident to CLKA. FB/IR, EF/OR, AF, and AE are all synchronized to the LOW-to-HIGH transition of CLKB. CSA Port A Chip Select I CSA must be LOW to enable a LOW-to HIGH transition of CLKA to read or write on Port A. The A0-35 outputs are in the high-impedance state when CSA is HIGH. CSB Port B Chip Select I CSB must be LOW to enable a LOW-to HIGH transition of CLKB to read or write on Port B. The B0-35 outputs are in the high-impedance state when CSB is HIGH. EF/OR Empty/Output Ready Flag (Port B) O This is a dual-function pin. In the CY Standard Mode, the EF function is selected. EF indicates whether or not the FIFO memory is empty. In the FWFT mode, the OR function is selected. OR indicates the presence of valid data on A0-35 outputs, available for reading. FF/OR is synchronized to the LOW-to-HIGH transition of CLKB. ENA Port A Enable I ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on Port A. ENB Port B Enable I ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on Port B. FF/IR Port B Full/Input Ready Flag O This is a dual-function pin. In the CY Standard Mode, the FF function is selected. FF indicates whether or not the FIFO memory is full. In the FWFT mode, the IR function is selected. IR indicates whether or not there is space available for writing to the FIFO memory. FF/IR is synchronized to the LOW-to-HIGH transition of CLKA. FS1/SEN Flag Offset Select 1/Serial Enable I FS0/SD Flag Offset Select 0/Serial Data I FS1/SEN and FS0/SD are dual-purpose inputs used for flag offset register programming. During Master Reset, FS1/SEN and FS0/SD, together with SPM, select the flag offset programming method. Three offset register programming methods are available: automatically load one of three preset values (8, 16, or 64), parallel load from Port A, and serial load. When serial load is selected for flag offset register programming, FS1/SEN is used as an enable synchronous to the LOW-to-HIGH transition of CLKA. When FS1/SEN is LOW, a rising edge on CLKA loads the bit present on FS0/SD into the X and Y registers. The number of bit writes required to program the offset registers is 40 for the CY7C43643, 48 for the CY7C43663, and 56 for the CY7C43683. The first bit write stores the Y-register MSB and the last bit write stores the X-register LSB. 4 PRELIMINARY CY7C43643V CY7C43663V/CY7C43683V Pin Definitions (continued) Signal Name Description I/O Function MBA Port A Mailbox Select I A HIGH level on MBA chooses a mailbox register for a Port A read or write operation. MBB Port B Mailbox Select I A HIGH level on MBB chooses a mailbox register for a Port B read or write operation. When the B0-35 outputs are active, a HIGH level on MBB selects data from the Mail1 register for output and a LOW level selects FIFO output register data for output. MBF1 Mail1 Register Flag O MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the Mail1 register. Writes to the Mail1 register are inhibited while MBF1 is LOW. MBF1 is set HIGH by a LOW-to-HIGH transition of CLKB when a Port B read is selected and MBB is HIGH. MBF1 is set HIGH following either a Master or Partial Reset. MBF2 Mail2 Register Flag O MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the Mail2 register. Writes to the Mail2 register are inhibited while MBF2 is LOW. MBF2 is set HIGH by a LOW-to-HIGH transition of CLKA when a Port A read is selected and MBA is HIGH. MBF1 is set HIGH following either a Master or Partial Reset. MRS1 Master Reset I A LOW on this pin initializes the FIFO read and write pointers to the first location of memory and sets the Port B output register to all zeroes. A LOW pulse on MRS1 selects the programming method (serial or parallel) and one of three programmable flag default offsets. It also configures Port B for bus size and endian arrangement. Four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must occur while MRS1 is LOW. MRS2 Master Reset I A LOW on this pin initializes the Mail2 Register. PRS Partial Reset I A LOW on this pin initializes the FIFO read and write pointers to the first location of memory and sets the Port B output register to all zeroes. During Partial Reset, the currently selected bus size, endian arrangement, programming method (serial or parallel), and programmable flag settings are all retained. RT Retransmit I A LOW strobe on this pin will retransmit data on FIFO from the location of the write pointer at the last Partial or Master reset. SIZE Bus Size Select I A HIGH on this pin when BM is HIGH selects byte bus (9-bit) size on Port B. A LOW on this pin when BM is HIGH selects word (18-bit) bus size. SIZE works with BM and BE to select the bus size and endian arrangement for Port B. The level of SIZE must be static throughout device operation. SPM Serial Programming I A LOW on this pin selects serial programming of partial flag offsets. A HIGH on this pin selects parallel programming or default offsets (8, 16, or 64). W/RA Port A Write/Read Select I A HIGH selects a write operation and a LOW selects a read operation on Port A for a LOW-to-HIGH transition of CLKA. The A0-35 outputs are in the high-impedance state when W/RA is HIGH. W/RB Port B Write/Read Select I A LOW selects a write operation and a HIGH selects a read operation on Port B for a LOW-to-HIGH transition of CLKB. The B0-35 outputs are in the high-impedance state when W/RB is LOW. 5 CY7C43643V CY7C43663V/CY7C43683V PRELIMINARY Maximum Ratings[1] Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage ........................................... >2001V (per MIL-STD-883, Method 3015) (Above which the useful life may be impaired. For user guidelines, not tested.) Latch-Up Current..................................................... >200 mA Storage Temperature ...................................-65C to +150C Operating Range Ambient Temperature with Power Applied ...............................................-55C to +125C Range Ambient Temperature VCC Commercial 0C to +70C 3.3V 10% -40C to +85C 3.3V 10% Supply Voltage to Ground Potential ............... -0.5V to +7.0V DC Voltage Applied to Outputs in High Z State[2] ......................................-0.5V to VCC+0.5V DC Input Voltage[2]...................................-0.5V to VCC+0.5V Industrial Electrical Characteristics Over the Operating Range CY7C43643/63/83V Parameter Description Test Conditions Min. Max. Unit VOH Output HIGH Voltage VCC = 3.0V, IOH = -2.0 mA VOL Output LOW Voltage VCC = 3.0V, IOL = 8.0 mA VIH Input HIGH Voltage VIL Input LOW Voltage IIX Input Leakage Current VCC = Max. -10 +10 mA IOZL IOZH Output OFF, High Z Current VSS < VO< V CC -10 +10 mA ICC1[3] Active Power Supply Current Com'l 60 mA Ind 60 mA Average Standby Current Com'l 5 mA Ind 5 mA ISB[4] Capacitance 2.4 V 0.4 V 2.0 VCC V -0.5 0.8 V [5] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = 3.3V Max. Unit 4 pF 8 pF Notes: 1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed 3. This is the supply current when each input is at least one of the specified TTL voltage levels rather than 0V or VCC. 4. All inputs = VCC - 0.2V, except RCLK and WCLK (which are at frequency = 0 MHz). All outputs are unloaded. 5. Tested initially and after any design or process changes that may affect these parameters. 6 CY7C43643V CY7C43663V/CY7C43683V PRELIMINARY AC Test Loads and Waveforms R1=330 ALL INPUT PULSES 3.3V OUTPUT 3.0V CL=30 pF R2=680 GND 3 ns INCLUDING JIG AND SCOPE Equivalent to: 90% 10% 90% 10% THEVENIN EQUIVALENT 200 OUTPUT 3 ns 2.0V Switching Characteristics Over the Operating Range CY7C43643/63/83V -15 Parameter Description fS Clock Frequency, CLKA or CLKB Min. Max. Unit 67 MHz tCLK Clock Cycle Time, CLKA or CLKB 15 ns tCLKH Pulse Duration, CLKA or CLKB HIGH 6 ns tCLKL Pulse Duration, CLKA or CLKB LOW 6 ns tDS Set-Up Time, A0-35 before CLKA and B0-35 before CLKB 5 ns tENS Set-Up Time, CSA, W/RA, ENA, and MBA before CLKA; CSB, W/RB, ENB, and MBB before CLKB 5 ns tRSTS Set-Up Time, MRS1/MRS2 or PRS LOW before CLKA or CLKB[6] 5 ns tFSS Set-Up Time, FS0 and FS1 before MRS1/MRS2 HIGH 7.5 ns tBES Set-Up Time, BE/FWFT before MRS1/MRS2 HIGH 7.5 ns Set-Up Time, SPM before MRS1/MRS2 HIGH tSPMS 7.5 ns tSDS Set-Up Time, FS0/SD before CLKA 5 ns tSENS Set-Up Time, FS1/SEN before CLKA 5 ns tFWS Set-Up Time, FWFT before CLKA 0 ns tDH Hold Time, A0-35 after CLKA and B0-35 after CLKB 0 ns tENH Hold Time, CSA, W/RA, ENA, and MBA after CLKA; CSB, W/RB, ENB, and MBB after CLKB 0 ns tRSTH Hold Time, MRS1/MRS2 or PRS LOW after CLKA or CLKB[6] 4 ns tFSH Hold Time, FS0 and FS1 after MRS1/MRS2 HIGH 2 ns tBEH Hold Time, BE/FWFT after MRS1/MRS2 HIGH 2 ns Hold Time, SPM after MRS1/MRS2 HIGH 2 ns tSPMH tSDH Hold Time, FS0/SD after CLKA 0 ns tSENH Hold Time, FS1/SEN after CLKA 0 ns tSPH Hold Time, FS1/SEN HIGH after MRS1/MRS2 HIGH 2 ns 7.5 ns tSKEW1 [7] Skew Time between CLKA and CLKB for EF/OR and FF/IR Notes: 6. Requirement to count the clock edge as one of at least four needed to reset a FIFO. 7. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between the CLKA cycle and the CLKB cycle. 7 PRELIMINARY CY7C43643V CY7C43663V/CY7C43683V Switching Characteristics Over the Operating Range (continued) CY7C43643/63/83V -15 Parameter tSKEW2 [7] Description Min. Max. Unit Skew Time between CLKA and CLKB for AE and AF 12 Access Time, CLKA to A0-35 and CLKB to B0-35 3 10 ns tWFF Propagation Delay Time, CLKA to FF/IR 2 10 ns tREF Propagation Delay Time, CLKB to EF/OR 1 10 ns tPAE Propagation Delay Time, CLKB to AE 1 10 ns tPAF Propagation Delay Time, CLKA to AF 1 10 ns tPMF Propagation Delay Time, CLKA to MBF1 LOW or MBF2 HIGH and CLKB to MBF2 LOW or MBF1 HIGH 0 12 ns tPMR Propagation Delay Time, CLKA to B0-35[8] and CLKB to A0-35[9] 3 12 ns tMDV Propagation Delay Time, MBA to A0-35 Valid and MBB to B0-35 Valid 3 11 ns tRSF Propagation Delay Time, MRS1 or PRS1 LOW to AEB LOW, AFA HIGH, and MBF1 HIGH and MRS2 or PRS2 LOW to AEA LOW, AFB HIGH, and MBF2 HIGH 1 15 ns tEN Enable Time, CSA or W/RA LOW to A0-35 Active and CSB LOW and W/RB HIGH to B0-35 Active 2 10 ns tDIS Disable Time, CSA or W/RA HIGH to A0-35 at High Impedance and CSB HIGH or W/RB LOW to B 0-35 at High Impedance 1 8 ns tA Notes: 8. Writing data to the Mail1 register when the B0-35 outputs are active and MBB is HIGH. 9. Writing data to the Mail2 register when the A0-35 outputs are active and MBA is HIGH. 8 ns CY7C43643V CY7C43663V/CY7C43683V PRELIMINARY Switching Waveforms Master Reset Loading X and Y with a Preset Value of Eight [10] CLKA CLKB t RSTS tRSTS MRS1 MRS2 tBES tBEH t FWS BE/FWFT tSPMS tSPMH SPM tFSS tFSH FS1, FS0 tRSF tWFF FF/IR tRSF EF/OR tRSF AE tRSF AF tRSF MBF1 Note: 10. PRS1 must be HIGH during Master Reset. 9 CY7C43643V CY7C43663V/CY7C43683V PRELIMINARY Switching Waveforms (continued) Partial Reset (CY Standard and FWFT Modes) [11] CLKA CLKB tRSTS tRSTH PRS tWFF tRSF FF/IR tRSF EF/OR tRSF AE tRSF AF tRSF MBF1 Parallel Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset (CY Standard and FWFT Modes) [12] CLKA MRS1 MRS2 tFSS tFSH tFSS t FSH SPM FS1, FS0 tWFF FF/IR tENS tENH tSKEW1[13] ENA tDS tDH A0-35 AF Offset (Y) AE Offset (X) First Word to FIFO Notes: 11. MRS1/MRS2 must be HIGH during Partial Reset. 12. CSA=LOW, W/RA=HIGH, MBA=LOW. It is not necessary to program offset register on consecutive clock cycles. 13. tSKEW1 is the minimum time between the rising CLKA edge and a rising CLK for FFB/IR to transition HIGH in the next cycle. If the time between the rising edge of CLKA and rising edge of CLKB is less than tSKEW1, then FF/IR may transition HIGH one cycle later than shown. 10 CY7C43643V CY7C43663V/CY7C43683V PRELIMINARY Switching Waveforms (continued) Serial Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values (CY Standard and FWFT Modes) [14] CLKA MRS1 MRS2 tFSS tFSH SPM tWFF FF/IR tFSS tSENS tSPH tSENS tSENH tSENH FS1/SEN tSDS tSDH tSDH tSDS FS0/SD[15] AF Offset (Y) MSB AE Offset (X) LSB Port B Long-Word Read Cycle Timing for FIFO (CY Standard and FWFT Modes) tCLK tCLKH tCLKL CLKB EF/OR CSB W/RB MBB tENS tENH tENS tENH t ENS tEN ENB B0-35 (Standard OR B0-35 (FWFT Mode) t EN tMDV tA tA [16] W1 Previous Data tEN t MDV No Operation W2 [16] tDIS tA tA [16] W1 W2 [16] W3 [16] Notes: 14. It is not necessary to program offset register bits on consecutive clock cycles. FIFO write attempts are ignored until IRA is set HIGH. 15. Programmable offsets are written serially to the SD input in the order AF offset (Y) then AE offset (X). 16. Read From FIFO. 11 tDIS CY7C43643V CY7C43663V/CY7C43683V PRELIMINARY Switching Waveforms (continued) Port B Word Read Cycle Timing for FIFO (CY Standard and FWFT Modes) [17] CLKB EF/OR HIGH CSB W/RB MBB tENS tENH ENB B0-8 (Standard OR B0-8 (FWFT Mode) tEN tMDV tA tA Previous Data tEN tMDV Read 2 Read 1 tA tA tA Read 2 Read 1 tA tA Read 3 Read 3 tA Read 4 No OperationtDIS Read 4 tDIS Read 5 Port B Byte Read Cycle Timing for FIFO (CY Standard and FWFT Modes) [18] CLKB EF/OR CSB W/RB MBB tENS tENH ENB B0-17 (Standard OR B0-17 (FWFT Mode) tEN tMDV tA tA Read 1 Previous Data tEN tMDV No Operation Read 2 tA tA Read 2 Read 1 Notes: 17. Unused word B18-35 contains all zeroes for word-size reads. 18. Unused bytes B9-17, B18-26 , and B27-35 contain all zeroes for byte-size reads. 12 tDIS tDIS Read 3 CY7C43643V CY7C43663V/CY7C43683V PRELIMINARY Switching Waveforms (continued) OR Flag Timing and First Data Word Fall Through when FIFO is Empty (FWFT Mode) [19] tCLK tCLKH tCLKL CLKA CSA LOW W/RA HIGH tENS tEN MBA t ENS tEN ENA IR HIGH t DS tDH A0-35 W1 tSKEW[20] CLKB tCLKH tCLKL tREF tCLK OR CSB W/RB MBB tREF FIFO Empty LOW HIGH LOW tENS tENH ENB tA B0-35 W1 Old Data in FIFO Output Register Notes: 19. If Port B size is word or byte, EF is set LOW by the last word or byte read from the FIFO, respectively. 20. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for OR to transition HIGH and to clock the next word to the FIFO output register in three CLKB cycles. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of OR HIGH and load of the first word to the output register may occur one CLKB cycle later than shown. 13 CY7C43643V CY7C43663V/CY7C43683V PRELIMINARY Switching Waveforms (continued) EF Flag Timing and First Data Read Fall Through when FIFO is Empty (CY Standard Mode) [21] tCLK tCLKH t CLKL CLKA CSA W/RA LOW HIGH tENS tENH MBA tENS tENH ENA FF HIGH tDS tDH A0-35 W1 tSKEW[22] tCLKH tCLKL CLKB tCLK EF CSB W/RB MBB tREF tREF FIFO Empty LOW HIGH LOW t ENS tENH ENB tA B0-35 W1 Notes: 21. If Port B size is word or byte, EF is set LOW by the last word or byte read from FIFO, respectively. 22. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for EF to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of EF HIGH may occur one CLKB cycle later than shown. 14 CY7C43643V CY7C43663V/CY7C43683V PRELIMINARY Switching Waveforms (continued) IR Flag Timing and First Available Write when FIFO is Full (FWFT Mode) [23] tCLK tCLKH tCLKL CLKB CSB LOW W/RB HIGH MBB tENS tENH ENB OR HIGH tA B0-35 Next Word From FIFO Previous Word in FIFO Output Register tSKEW1 [24] tCLKH tCLKL CLKA tCLK IR FIFO Full CSA LOW W/RA HIGH tWFF tWFF t ENS tENH MBA tENS tENH ENA tDS tDH A0-35 To FIFO Notes: 23. If Port B size is word or byte, t SKEW1 is referenced to the rising CLKB edge that reads the last word or byte write of the long word, respectively. 24. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for IR to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW1, then IR may transition HIGH one CLKA cycle later than shown. 15 CY7C43643V CY7C43663V/CY7C43683V PRELIMINARY Switching Waveforms (continued) FF Flag Timing and First Available Write when FIFO is Full (CY Standard Mode) [25] tCLK tCLKH tCLKL CLKB CSB LOW W/RB HIGH MBB tENS tENH ENB OR HIGH tA B0-35 Previous Word in FIFO Output Register tSKEW1[26] Next Word From FIFO tCLKH tCLKL CLKA tCLK IR FIFO Full CSA LOW W/RA HIGH tWFF t WFF tENS tENH MBA t ENS tENH ENA tDS tDH A0-35 Notes: 25. If Port B size is word or byte, t SKEW1 is referenced to the rising CLKB edge that reads the last word or byte of the long word, respectively. 26. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for FF to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW1, then the transition of FF HIGH may occur one CLKA cycle later than shown. 16 CY7C43643V CY7C43663V/CY7C43683V PRELIMINARY Switching Waveforms (continued) Timing for AF when FIFO is Almost Full (CY Standard and FWFT Modes) [27, 28, 29] tSKEW2[30] CLKA tENS tENH ENA tPAF AF [D-(Y1+1)] Words in FIFO t PAF (D-Y1)Words in FIFO CLKB tENH tENS ENB [31, 32] Timing for AE when FIFO is Almost Empty (CY Standard and FWFT Modes) CLKA tENS tENH ENA tSKEW2[33] CLKB tPAE tPAE AE (X1+1)Words in FIFO X1 Word in FIFO t ENS tENH ENB Notes: 27. FIFO Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO output register has been read from the FIFO. 28. D = Maximum FIFO Depth = 1K for the CY7C43643, 4K for the 43663, and 16K for the CY7C43683. 29. If Port B size is word or byte, t SKEW2 is referenced to the rising CLKB edge that writes the last word or byte of the long word, respectively. 30. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AF to transition HIGH in the next CLKA cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW2, then AF may transition HIGH one CLKB cycle later than shown. 31. FIFO Write (CSA = LOW, W/RA = LOW, MBA = LOW), FIFO read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO output register has been read from the FIFO. 32. If Port B size is word or byte, AE is set LOW by the last word or byte read from FIFO, respectively. 33. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AE to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW2, then AE may transition HIGH one CLKB cycle later than shown. 17 PRELIMINARY CY7C43643V CY7C43663V/CY7C43683V Switching Waveforms (continued) Timing for Mail1 Register and MBF1 Flag (CY Standard and FWFT Modes) [34] CLKA t ENS tENH CSA tENS t ENH tENS tENH tENS t ENH tDS tDH W/RA MBA ENA A0-35 W1 CLKB tPMF tPMF MBF1 CSB W/RB MBB tENS tENH ENB t EN tMDV tPMR FIFO Output Register tDIS W1 (Remains valid in Mail1 Register after read) Note: 34. If Port B is configured for word size, data can be written to the Mail1 register using A 0-17 (A18-35 are don't care inputs). In this first case B0-17 will have valid data (B18-35 will be indeterminate). If Port B is configured for byte size, data can be written to the Mail1 Register using A0-8 (A9-35 are don't care inputs). In this second case, B0-8 will have valid data (B9-35 will be indeterminate). 18 CY7C43643V CY7C43663V/CY7C43683V PRELIMINARY Switching Waveforms (continued) Timing for Mail2 Register and MBF2 Flag (CY Standard and FWFT Modes) [35] CLKB tENS tENH tENS tENH t ENS tENH tENS tENH tDS t DH CSB W/RB MBB ENB B0-35 W1 CLKA tPMF tPMF MBF2 CSA W/RA MBA tENS tENH ENA tMDV tEN A0-35 FIFO Retransmit Timing tPMR tDIS FIFO2 Output Register W1 (Remains valid in Mail2 Register after read) [35, 36, 37, 38] RT1 tPRT tRTR ENB EFB/FFA Notes: 35. If Port B is configured for word size, data can be written to the Mail2 register using B 0-17 (B18-35 are don't care inputs). In this first case A0-17 will have valid data (A18-35 will be indeterminate). If Port B is configured for byte size, data can be written to the Mail2 Register using B0-8 (B9-35 are don't care inputs). In this second case, A0-8 will have valid data (A9-35 will be indeterminate). 36. Clocks are free running in this case. 37. The flags may change state during Retransmit as a result of the offset of the read and write pointers, but flags will be valid at tRTR. 38. For the synchronous PAE and PAF flags (SMODE), an appropriate clock cycle is necessary after tRTR to update these flags. 19 PRELIMINARY CY7C43643V CY7C43663V/CY7C43683V written to Port A will be read from Port B first; the least significant byte (word) of the long word written to Port A will be read from Port B last. When data is moving in the direction from Port B to Port A, the byte (word) written to Port B first will be read from Port A as the most significant byte (word) of the long word; the byte (word) written to Port B last will be read from Port A as the least significant byte (word) of the long word. Signal Description Master Reset (MRS1, MRS2) The FIFO memory of the CY7C436X3V undergoes a complete reset by taking its associated Master Reset (MRS1, MRS2) input LOW for at least four Port A clock (CLKA) and four Port B clock (CLKB) LOW-to-HIGH transitions. The Master Reset input can switch asynchronously to the clocks. A Master Reset initializes the internal read and write pointers and forces the Full/Input Ready flag (FF/IR) LOW, the Empty/Output Ready flag (EF/OR) LOW, the Almost Empty flag (AE) LOW, and the Almost Full flag (AF) HIGH. A Master Reset also forces the Mailbox flag (MBF1, MBF2) of the parallel mailbox register HIGH. After a Master Reset, the FIFO's Full/Input Ready flag is set HIGH after two clock cycles to begin normal operation. A Master Reset must be performed on the FIFO after power up, before data is written to its memory. A LOW on the BE/FWFT input when the Master Reset (MRS1, MRS2) inputs go from LOW to HIGH will select a Little Endian arrangement. When data is moving in the direction from Port A to Port B, the least significant byte (word) of the long word written to Port A will be read from Port B first; the most significant byte (word) of the long word written to Port A will be read from Port B last. When data is moving in the direction from Port B to Port A, the byte (word) written to Port B first will be read from port A as the least significant byte (word) of the long word; the byte (word) written to Port B last will be read from Port A as the most significant byte (word) of the long word. A LOW-to-HIGH transition on a FIFO Master Reset (MRS1, MRS2) input latches the value of the Big Endian (BE) input, determining the order by which bytes are transferred through Port B. After Master Reset, the FWFT select function is active, permitting a choice between two possible timing modes: CY Standard Mode or First Word Fall Through (FWFT) Mode. Once the Master Reset (MRS1, MRS2) input is HIGH, a HIGH on the BE/FWFT input during the next LOW-to-HIGH transition of CLKA will select CY Standard Mode. This mode uses the Empty Flag function (EF) to indicate whether or not there are any words present in the FIFO memory. It uses the Full Flag function (FF) to indicate whether or not the FIFO memory has any free space for writing. In CY Standard mode, every word read from the FIFO, including the first, must be requested using a formal read operation. A LOW-to-HIGH transition on a FIFO reset (MRS1, MRS2) input latches the values of the Flag select (FS0, FS1) and Serial Programming Mode (SPM) inputs for choosing the Almost Full and Almost Empty offset programming method (see Almost Empty and Almost Full flag offset programming below). Partial Reset (PRS) Each of the two FIFO memories of the CY7C436X3V undergoes a limited reset by taking its associated Partial Reset (PRS) input LOW for at least four Port A clock (CLKA) and four Port B clock (CLKB) LOW-to-HIGH transitions. The Partial Reset inputs can switch asynchronously to the clocks. A Partial Rest initializes the internal read and write pointers and forces the Full/Input Ready flag (FF/IR) LOW, the Empty/Output Ready flag (EF/OR) LOW, the Almost Empty flag (AE) LOW, and the Almost Full flag (AF) HIGH. A Partial Reset also forces the Mailbox flag (MBF1, MBF2) of the parallel mailbox register HIGH. After a Partial Reset, the FIFO's Full/Input Ready flag is set HIGH after two clock cycles to begin normal operation. Once the Master Reset (MRS1, MRS2) input is HIGH, a LOW on the BE/FWFT input during the next LOW-to-HIGH transition of CLKA will select FWFT Mode. This mode uses the Output Ready function (OR) to indicate whether or not there is valid data at the data outputs (B 0-35). It also uses the Input Ready function (IR) to indicate whether or not the FIFO memory has any free space for writing. In the FWFT mode, the first word written to an empty FIFO goes directly to data outputs, no read request necessary. Subsequent words must be accessed by performing a formal read operation. Following Master Reset, the level applied to the BE/FWFT input to choose the desired timing mode must remain static throughout the FIFO operation. Whatever flag offsets, programming method (parallel or serial), and timing mode (FWFT or CY Standard mode) are currently selected at the time a Partial Reset is initiated, those settings will remain unchanged upon completion of the reset operation. A Partial Reset may be useful in the case where reprogramming a FIFO following a Master Reset would be inconvenient. Programming the Almost Empty and Almost Full Flags Two registers in the CY7C436X3V are used to hold the offset values for the Almost Empty and Almost Full flags. The Port A Almost Empty flag (AE) offset register is labeled X. The Port B Almost Full flag (AF) offset register is labeled Y. The index of each register name corresponds with preset values during the reset of a FIFO, programmed in parallel using the FIFO's Port A data inputs, or programmed in serial using the Serial Data (SD) input (see Table 1). Big Endian/First Word Fall Through (BE/FWFT) This is a dual-purpose pin. At the time of Master Reset, the BE select function is active, permitting a choice of big or little endian byte arrangement for data written to or read from Port B. This selection determines the order by which bytes (or words) of data are transferred through this port. For the following illustrations, assume that a byte (or word) bus size has been selected for Port B. (Note that when Port B is configured for a long word size, the Big Endian function has no application and the BE input is a "don't care".) To load a FIFO's Almost Empty flag and Almost Full flag offset registers with one of the three preset values listed in Table 1, the Serial Program Mode (SPM) and at least one of the flag-select inputs must be HIGH during the LOW-to-HIGH transition of its Master Reset input (MRS1, MRS2). For example, to load the preset value of 64 into X and Y, SPM, FS0 and FS1 must be HIGH when the FIFO reset (MRS1, MRS2) returns HIGH. When using one of the preset values for the flag offsets, the FIFO can be reset simultaneously or at different times. A HIGH on the BE/FWFT input when the Master Reset (MRS1, MRS2) inputs go from LOW to HIGH will select a Big Endian arrangement. When data is moving in the direction from Port A to Port B, the most significant byte (word) of the long word 20 PRELIMINARY CY7C43643V CY7C43663V/CY7C43683V To program the X and Y registers from Port A, perform a Master Reset on both FIFOs simultaneously with SPM HIGH and FS0 and FS1 LOW during the LOW-to-HIGH transition of MRS1, MRS2. After this reset is complete, the first four writes to the FIFO do not store data in RAM but load the offset registers in the order Y and X. The Port A data inputs used by the offset registers are (A7-0), (A8-0), (A9-0), (A 11-0), or (A13-0),for the CY7C436X3V, respectively. The highest numbered input is used as the most significant bit of the binary number in each case. Valid programming values for the registers range from 1 to 1012 for the CY7C43643V; 1 to 4092 for the CY7C43663V; 1 to 16380 for the CY7C43683V. After all the offset registers are programmed from Port A, the Port B Full/Input Ready (FF/IR) is set HIGH and both FIFOs begin normal operation. The set-up and hold time constraints to the port clocks for the port Chip Selects and Write/read selects are only for enabling write and read operations and are not related to high-impedance control of the data outputs. If a port enable is LOW during a clock cycle, the port's Chip Select and Write/Read select may change states during the set-up and hold time window of the cycle. To program the X and Y registers serially, initiate a Master Reset with SPM LOW, FS0/SD LOW and FS1/SEN HIGH during the LOW-to-HIGH transition of MRS1, MRS2. After this reset is complete, the X and Y register values are loaded bit-wise through the FS0/SD input on each LOW-to-HIGH transition of CLKA that the FS1/SEN input is LOW. Thirty-two, thirty-six, forty, forty-eight, or fifty-six bit writes are needed to complete the programming for the CY7C436X3V, respectively. The four registers are written in the order Y then finally X. The first-bit write stores the most significant bit of the Y register and the last-bit write stores the least significant bit of the X register. Each register value can be programmed from 1 to 1020 (CY7C43643V), 1 to 4092 (CY7C43663V), or 1 to 16380 (CY7C43683V). When operating the FIFO in CY Standard Mode, regardless of whether the Empty Flag is LOW or HIGH, data residing in the FIFO's memory array is clocked to the output register only when a read is selected using the port's Chip Select, Write/Read select, Enable, and Mailbox select. When operating the FIFO in FWFT Mode and the Output Ready flag is LOW, the next word written is automatically sent to the FIFO's output register by the LOW-to-HIGH transition of the port clock that sets the Output Ready flag HIGH, data residing in the FIFO's memory array is clocked to the output register only when a read is selected using the port's Chip Select, Write/Read select, Enable, and Mailbox select. Synchronized FIFO Flags Each FIFO is synchronized to its port clock through at least two flip-flop stages. This is done to improve flag-signal reliability by reducing the probability of the metastable events when CLKA and CLKB operate asynchronously to one another. EF/OR and AE are synchronized to CLKA. FF/IR and AF are synchronized to CLKB. Table 4 shows the relationship of each port flag to the FIFO. When the option to program the offset registers serially is chosen, the Port A Full/Input Ready (FF/IR) flag remains LOW until all register bits are written. FF/IR is set HIGH by the LOW-to-HIGH transition of CLKA after the last bit is loaded to allow normal FIFO operation. The Port B Full/Input ready (FF/IR) flag also remains LOW throughout the serial programming process, until all register bits are written. Empty/Output Ready Flags (EF/OR) These are dual purpose flags. In the FWFT Mode, the Output Ready (OR) function is selected. When the Output Ready flag is HIGH, new data is present in the FIFO output register. When the Output Ready flag is LOW, the previous data word is present in the FIFO output register and attempted FIFO reads are ignored. SPM, FS0/SD, and FS1/SEN function the same way in both CY Standard and FWFT modes. In the CY Standard Mode, the Empty Flag (EF) function is selected. When the Empty Flag is HIGH, data is available in the FIFO's RAM memory for reading to the output register. When Empty Flag is LOW, the previous data word is present in the FIFO output register and attempted FIFO reads are ignored. FIFO Write/Read Operation The state of the Port A data (A 0-35) lines is controlled by Port A Chip Select (CSA) and Port A Write/Read Select (W/RA). The A0-35 lines are in the high-impedance state when either CSA or W/RA is HIGH. The A0-35 lines are active outputs when both CSA and W/RA are LOW. The Empty/Output Ready flag of a FIFO is synchronized to the port clock that reads data from its array. For both the FWFT and CY Standard modes, the FIFO read pointer is incremented each time a new word is clocked to its output register. The state machine that controls an Output Ready flag monitors a write pointer and read pointer comparator that indicates when the FIFO SRAM status is empty, empty+1, or empty+2. Data is loaded into the FIFO from the A 0-35 inputs on a LOW-to-HIGH transition of CLKA when CSA is LOW, W/RA is HIGH, ENA is HIGH, MBA is LOW, and FF/IR is HIGH. (see Table 2). FIFO writes on Port A are independent of any concurrent Port B operation. The Port B control signals are identical to those of Port A with the exception that the Port B Write/Read select (W/RB) is the inverse of the Port A Write/Read select (W/RA). The state of the Port B data (B0-35) lines is controlled by the Port B Chip Select (CSB) and Port B Write/Read select (W/RB). The B0-35 lines are in the high-impedance state when either CSB is HIGH or W/RB is LOW. The B0-35 lines are active outputs when CSB is LOW and W/RB is HIGH. In FWFT Mode, from the time a word is written to a FIFO, it can be shifted to the FIFO output register in a minimum of three cycles of the Output Ready flag synchronizing clock. Therefore, an Output Ready flag is LOW if a word in memory is the next data to be sent to the FIFO output register and three cycles have not elapsed since the time the word was written. The Output Ready flag of the FIFO remains LOW until the third LOW-to-HIGH transition of the synchronizing clock occurs, simultaneously forcing the Output Ready flag HIGH and shifting the word to the FIFO output register. Data is read from the FIFO to the B0-35 outputs by a LOW-to-HIGH transition of CLKB when CSB is LOW, W/RB is HIGH, ENB is HIGH, MBB is LOW, and EF/OR is HIGH (see Table 3). FIFO reads and writes on Port B are independent of any concurrent Port A operation. In the CY Standard Mode, from the time a word is written to a FIFO, the Empty Flag will indicate the presence of data available for reading in a minimum of two cycles of the Empty Flag 21 PRELIMINARY CY7C43643V CY7C43663V/CY7C43683V Almost Empty flag is set HIGH by the second LOW-to-HIGH transition of its synchronizing clock after the FIFO write that fills memory to the (X+1) level. A LOW-to-HIGH transition of an Almost Empty flag synchronizing clock begins the first synchronization cycle if it occurs at time tSKEW2 or greater after the write that fills the FIFO to (X+1) words. Otherwise, the subsequent synchronizing clock cycle may be the first synchronization cycle. synchronizing clock. Therefore, an Empty Flag is LOW if a word in memory is the next data to be sent to the FIFO output register and two cycles have not elapsed since the time the word was written. The Empty Flag of the FIFO remains LOW until the second LOW-to-HIGH transition of the synchronizing clock occurs, forcing the Empty Flag HIGH; only then can data be read. A LOW-to-HIGH transition on an Empty/Output Ready flag synchronizing clock begins the first synchronization cycle of a write if the clock transition occurs at time tSKEW1 or greater after the write. Otherwise, the subsequent clock cycle can be the first synchronization cycle. Almost Full Flags (AF) The Almost Full flag of a FIFO is synchronized to the port clock that writes data to its array. The state machine that controls an Almost Full flag monitors a write pointer and read pointer comparator that indicates when the FIFO SRAM status is almost full, almost full-1, or almost full-2. The Almost Full state is defined by the contents of register Y for AF. These registers are loaded with preset values during a FIFO reset, programmed from Port A, or programmed serially (see Almost Empty flag and Almost Full flag offset programming above). An Almost Full flag is LOW when the number of words in its FIFO is greater than or equal to (1024-Y), (4096-Y), or (16384-Y), for the CY7C436X3V respectively. An Almost Full flag is HIGH when the number of words in its FIFO is less than or equal to [1024-(Y+1)], [4096-(Y+1)], or [16384-(Y+1)], for the CY7C436X3V respectively. Note that a data word present in the FIFO output register has been read from memory. Full/Input Ready Flags (FF/IR) This is a dual-purpose flag. In FWFT Mode, the Input Ready (IR) function is selected. In CY Standard Mode, the Full Flag (FF) function is selected. For both timing modes, when the Full/Input Ready flag is HIGH, a memory location is free in the SRAM to receive new data. No memory locations are free when the Full/Input Ready flag is LOW and attempted writes to the FIFO are ignored. The Full/Input Ready flag of a FIFO is synchronized to the port clock that writes data to its array. For both FWFT and CY Standard modes, each time a word is written to a FIFO, its write pointer is incremented. The state machine that controls a Full/Input Ready flag monitors a write pointer and read pointer comparator that indicates when the FIFO SRAM status is full, full-1, or full-2. From the time a word is read from a FIFO, its previous memory location is ready to be written to in a minimum of two cycles of the Full/Input Ready flag synchronizing clock. Therefore, an Full/Input Ready flag is LOW if less than two cycles of the Full/Input Ready flag synchronizing clock have elapsed since the next memory write location has been read. The second LOW-to-HIGH transition on the Full/Input Ready flag synchronizing clock after the read sets the Full/Input Ready flag HIGH. A LOW-to-HIGH transition on a Full/Input Ready flag synchronizing clock begins the first synchronization cycle of a read if the clock transition occurs at time tSKEW1 or greater after the read. Otherwise, the subsequent clock cycle can be the first synchronization cycle. Two LOW-to-HIGH transitions of the Almost Full flag synchronizing clock are required after a FIFO read for its Almost Full flag to reflect the new level of fill. Therefore, the Almost Full flag of a FIFO containing [1024/4096/16384-(Y+1)] or less words remains LOW if two cycles of its synchronizing clock have not elapsed since the read that reduced the number of words in memory to [1024/4096/16384-(Y+1)]. An Almost Full flag is set HIGH by the second LOW-to-HIGH transition of its synchronizing clock after the FIFO read that reduces the number of words in memory to [1024/4096/16384-(Y+1)]. A LOW-to-HIGH transition of an Almost Full flag synchronizing clock begins the first synchronization cycle if it occurs at time tSKEW2 or greater after the read that reduces the number of words in memory to [1024/4096/16384-(Y+1)]. Otherwise, the subsequent synchronizing clock cycle may be the first synchronization cycle. Almost Empty Flags (AE) Mailbox Registers The Almost Empty flag of a FIFO is synchronized to the port clock that reads data from its array. The state machine that controls an Almost Empty flag monitors a write pointer and read pointer comparator that indicates when the FIFO SRAM status is almost empty, almost empty+1, or almost empty+2. The Almost Empty state is defined by the contents of register X for AE. These registers are loaded with preset values during a FIFO reset, programmed from Port A, or programmed serially (see Almost Empty flag and Almost Full flag offset programming above). An Almost Empty flag is LOW when its FIFO contains X or less words and is HIGH when its FIFO contains (X+1) or more words. A data word present in the FIFO output register has been read from memory. Each FIFO has a 36-bit bypass register to pass command and control information between Port A and Port B without putting it in queue. The Mailbox Select (MBA, MBB) inputs choose between a mail register and a FIFO for a port data transfer operation. The usable width of both the Mail1 and Mail2 registers matches the selected bus size for Port B. A LOW-to-HIGH transition on CLKA writes A0-35 data to the Mail1 Register when a Port A write is selected by CSA, W/RA, and ENA with MBA HIGH. If the selected Port A bus size is also 36 bits, then the usable width of the Mail1 Register employs data lines A0-35. If the selected Port A bus size is 18 bits, then the usable width of the Mail1 Register employs data lines A0-17. (In this case, A18-35 are don't care inputs.) If the selected Port A bus size is 9 bits, then the usable width of the Mail1 Register employs data lines B 0-B8. (In this case, A9-35 are don't care inputs.) Two LOW-to-HIGH transitions of the Almost Empty flag synchronizing clock are required after a FIFO write for its Almost Empty flag to reflect the new level of fill. Therefore, the Almost Full flag of a FIFO containing (X+1) or more words remains LOW if two cycles of its synchronizing clock have not elapsed since the write that filled the memory to the (X+1) level. An A LOW-to-HIGH transition on CLKB writes B0-35 data to the Mail2 Register when a Port B write is selected by CSB, W/RB, and ENB with MBB HIGH. If the selected Port B bus size is 22 PRELIMINARY CY7C43643V CY7C43663V/CY7C43683V method that will be active during FIFO operation. BE is a don't care input when the bus size selected for Port B is long word. The endian method is implemented at the completion of Master Reset, by the time the Full/Input ready flag is set HIGH. also 36 bits, then the usable width of the Mail2 Register employs data lines B 0-35. If the selected Port B bus size is 18 bits, then the usable width of the Mail2 Register employs data lines B0-17. (In this case, B18-35 are don't care inputs.) If the selected Port B bus size is 9 bits, then the usable width of the Mail2 Register employs data lines B 0-8. (In this case, B9-35 are don't care inputs.) Only 36-bit long word data is written to or read from the two FIFO memories on the CY7C436X3V. Bus-matching operations are done after data is read from the FIFO. These bus-matching operations are not available when transferring data via mailbox registers. Furthermore, both the word- and byte-size bus selections limit the width of the data bus that can be used for mail register operations. In this case, only those byte lanes belonging to the selected word- or byte-size bus can carry mailbox data. The remaining data outputs will be indeterminate. The remaining data inputs will be don't care inputs. For example, when a word-size bus is selected, then mailbox data can be transmitted only between A0-17 and B0-17. When a byte-size bus is selected, then mailbox data can be transmitted only between A0-8 and B0-8. Writing data to a mail register sets its corresponding flag (MBF1 or MBF2) LOW. Attempted writes to a mail register are ignored while the mail flag is LOW. When data outputs of a port are active, the data on the bus comes from the FIFO output register when the port Mailbox Select input is LOW and from the mail register when the port Mailbox Select input is HIGH. The Mail1 Register Flag (MBF1) is set HIGH by a LOW-to-HIGH transition on CLKB when a Port B read is selected by CSB, W/RB, and ENB with MBB HIGH. For a 36-bit bus size, 36 bits of mailbox data are placed on B0-35. For an 18-bit bus size, 18 bits of mailbox data are placed on B0-17. (In this case, B18-35 are indeterminate.) For a 9-bit bus size, 9 bits of mailbox data are placed on B 0-8. (In this case, B9-35 are indeterminate.) Bus-Matching FIFO Reads Data is read from the FIFO RAM in 36-bit long word increments. If a long word bus size is implemented, the entire long word immediately shifts to the FIFO output register. If byte or word size is implemented on Port B, only the first one or two bytes appear on the selected portion of the FIFO output register, with the rest of the long word stored in auxiliary registers. In this case, subsequent FIFO reads output the rest of the long word to the FIFO output register. The Mail2 register Flag (MBF2) is set HIGH by a LOW-to-HIGH transition on CLKA when a Port A read is selected by CSA, W/RA, and ENA with MBA HIGH. For a 36-bit bus size, 36 bits of mailbox data are placed on A0-35. For an 18-bit bus size, 18 bits of mailbox data are placed on A0-17. (In this case, A18-35 are indeterminate.) For a 9-bit bus size, 9 bits of mailbox data are placed on A 0-8. (In this case, A9-35 are indeterminate.) When reading data from the FIFO in the byte or word format, the unused B0-35 outputs are indeterminate. Retransmit (RT) The data in a mail register remains intact after it is read and changes only when new data is written to the register. The Endian Select feature has no effect on the mailbox data. The retransmit feature is beneficial when transferring packets of data. It enables the receipt of data to be acknowledged by the receiver and retransmitted if necessary. Bus Sizing The retransmit feature is intended for use when a number of writes equal to or less than the depth of the FIFO have occurred and at least one word has been read since the last reset cycle. A LOW pulse on RT resets the internal read pointer to the first physical location of the FIFO. CLKA and CLKB may be free running but must be disabled during and tRTR after the retransmit pulse. With every valid read cycle after retransmit, previously accessed data is read and the read pointer is incremented until it is equal to the write pointer. Flags are governed by the relative locations of the read and write pointers and are updated during a retransmit cycle. Data written to the FIFO after activation of RT are transmitted also. The full depth of the FIFO can be repeatedly retransmitted. The Port B bus can be configured in a 36-bit long word, 18-bit word, or 9-bit byte format for data read from FIFO. The levels applied to the Port B Bus Size Select (SIZE) and the Bus Match Select (BM) determine the Port B bus size. These levels should be static throughout FIFO operation. Both bus size selections are implemented at the completion of Master Reset, by the time the Full/Input Ready flag is set HIGH. Two different methods for sequencing data transfer are available for Port B when the bus size selection is either byte-or word-size. They are referred to as Big Endian (most significant byte first) and Little Endian (least significant byte first). The level applied to the Big Endian Select (BE) input during the LOW-to-HIGH transition of MRS1/MRS2 selects the endian 23 CY7C43643V CY7C43663V/CY7C43683V PRELIMINARY BYTE ORDER ON PORT A: BE BM SIZE X L X A35-27 A26-18 A17-9 A B C B35-27 B26-18 B17-9 A B C BM SIZE H H L D Write to FIFO B8-0 D Read from FIFO (a) LONG WORD SIZE B35-27 BE A8-0 B26-18 B17-9 A B35-27 B26-18 B17-9 C B8-0 B 1st: Read from FIFO B8-0 D 2nd: Read from FIFO (b) WORD SIZE - BIG ENDIAN B35-27 BE BM SIZE L H L B26-18 B17-9 C B35-27 B26-18 B17-9 A B8-0 D 1st: Read from FIFO B8-0 B 2nd: Read from FIFO (c) WORD SIZE - LITTLE ENDIAN B35-27 BE BM SIZE H H H B26-18 B17-9 B8-0 A B35-27 B26-18 B17-9 B8-0 B B35-27 B26-18 B17-9 B26-18 B17-9 2nd: Read from FIFO B8-0 C B35-27 1st: Read from FIFO 3rd: Read from FIFO B8-0 D 4th: Read from FIFO (d) BYTE SIZE - BIG ENDIAN B35-27 BE BM SIZE L H H B17-9 B26-18 B8-0 D B35-27 B26-18 B17-9 B8-0 C B35-27 B17-9 B26-18 B17-9 B26-18 2nd: Read from FIFO B8-0 B B35-27 1st: Read from FIFO 3rd: Read from FIFO B8-0 A 4th: Read from FIFO (e) BYTE SIZE - LITTLE ENDIAN 24 CY7C43643V CY7C43663V/CY7C43683V PRELIMINARY ..able Table 1. Flag Programming FS1/SEN FS0/SD MRS1/MRS2 X and Y Registers[39] H H H 64 H H L 16 H L H 8 H L L Parallel programming via Port A L H L Serial programming via SD L H H Reserved L L H Reserved L L L Reserved SPM Table 2. Port A Enable Function W/RA ENA MBA CLKA A0-35 Outputs Port Function H X X X X In high-impedance state None L H L X X In high-impedance state None L H H L In high-impedance state FIFO write L H H H In high-impedance state Mail1 write L L L L X Active, Mail2 register None L L H L Active, Mail2 register None CSA L L L H X Active, Mail2 register None L L H H Active, Mail2 register Mail2 read (set MBF2 HIGH) Table 3. Port B Enable Function W/RB ENB MBB CLKB B0-35 Outputs Port Function H X X X X In high-impedance state None L L L X X In high-impedance state None L L H L In high-impedance state None L L H H In high-impedance state Mail2 write L H L L X Active, FIFO output register None L H H L Active, FIFO output register FIFO read L H L H X Active, Mail1 register None L H H H Active, Mail1 register Mail1 read (set MBF1 HIGH) CSB Note: 39. X register holds the offset for AE; Y register holds the offset for AF. 25 CY7C43643V CY7C43663V/CY7C43683V PRELIMINARY Table 4. FIFO Flag Operation (CY Standard and FWFT Modes) Number of Words in FIFO Memory[40,41,42,43] CY7C43643V CY7C43663V Synchronized to CLKA Synchronized to CLKB CY7C43683V EF/OR AE AF FF/IR 0 0 0 L L H H 1 TO X1 1 TO X1 1 TO X1 H L H H (X1+1) to [16384-(Y1+1)] H H H H (16384-Y1) to 16383 H H L H 16384 H H L L (X1+1) to [1024-(Y1+1)] (X1+1) to [4096-(Y1+1)] (1024-Y1) to 1023 (4096-Y1) to 4095 1024 4096 Table 5. Data Size for FIFO Long-Word Reads Size Mode[44] Data Written to FIFO2 Data Read From FIFO2 BM SIZE BE A35-27 A26-18 A17-9 A8-0 B26-18 B26-18 B17-9 B8-0 L X X A B C D A B C D Table 6. Data Size for Word Reads Size Mode[44] Data Written to FIFO Read No. BM SIZE BE A35-27 A26-18 A17-9 A8-0 H L H A B C D H L L A B C D Data Read From FIFO B17-9 B8-0 1 A B 2 C D 1 C D 2 A B Table 7. Data Size for byte Reads from FIFO Size Mode[44] Data Written to FIFO Read No. BM SIZE BE A35-27 A26-18 A17-9 A8-0 H H H A B C D H H L A B C D Data Read From FIFO B8-0 1 A 2 B 3 C 4 D 1 D 2 C 3 B 4 A Notes: 40. X1 is the almost-empty offset for FIFO used by AE. Y is the almost-full offset for FIFO used by AF. Both X1 and Y1 are selected during a FIFO reset or port A programming. 41. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free. 42. Data in the output register does not count as a "word in FIFO memory". Since in FWFT mode, the first word written to an empty FIFO goes unrequested to the output register (no read operation necessary), it is not included in the FIFO memory count. 43. The OR and IR functions are active during FWFT mode; the EF and FFA functions are active in CY Standard mode. 44. BE is selected at Master Reset; BM and SIZE must be static throughout device operation. 26 PRELIMINARY CY7C43643V CY7C43663V/CY7C43683V 3.3V 1K x36 Unidirectional Synchronous FIFO w/ bus matching Speed (ns) 15 Ordering Code CY7C43643V-15AC Package Name A128 Package Type 128-Lead Thin Quad Flat Package Operating Range Commercial 3.3V 4K x36 Unidirectional Synchronous FIFO w/ bus matching Speed (ns) 15 Ordering Code CY7C43663V-15AC Package Name A128 Package Type 128-Lead Thin Quad Flat Package Operating Range Commercial 3.3V 16K x36 Unidirectional Synchronous FIFO w/ bus matching Speed (ns) 15 Ordering Code CY7C43683V-15AC Package Name A128 Package Type 128-Lead Thin Quad Flat Package Operating Range Commercial Document #: 38-00703 Package Diagram 128-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A128 51-85101 (c) Cypress Semiconductor Corporation, 1998. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.