MC14175BCPG - ON Semiconductor

June, 2011 − Rev. 7

1Publication Order Number:

MC14175B/D

MC14175B

Quad Type D Flip-Flop

The MC14175B quad type D flip−flop is constructed with MOS

P−channel and N−channel enhancement mode devices in a single

monolithic structure. Each of the four flip−flops is positive−edge

triggered by a common clock input (C). An active−low reset input (R)

asynchronously resets all flip−flops. Each flip−flop has independent

Data (D) inputs and complementary outputs (Q and Q). These devices

may be used as shift register elements or as type T flip−flops for

counter and toggle applications.

Features

•Complementary Outputs

•Static Operation

•All Inputs and Outputs Buffered

•Diode Protection on All Inputs

•Supply Voltage Range = 3.0 Vdc to 18 Vdc

•Output Compatible with Two Low−Power TTL Loads or One

Low−Power Schottky TTL Load

•Functional Equivalent to TTL 74175

•These Devices are Pb−Free and are RoHS Compliant

MAXIMUM RATINGS (Voltages Referenced to VSS)

Parameter Symbol Value Unit

DC Supply Voltage Range VDD −0.5 to +18.0 V

Input or Output Voltage Range

(DC or Transient)

Vin, Vout −0.5 to VDD

+ 0.5

V

Input or Output Current (DC or Transient)

per Pin

Iin, Iout ±10 mA

Power Dissipation per Package (Note 1) PD500 mW

Ambient Temperature Range TA−55 to +125 °C

Storage Temperature Range −65 to +150 °C

Lead Temperature (8−Second Soldering) 260 °C

Stresses exceeding Maximum Ratings may damage the device. Maximum

Ratings are stress ratings only. Functional operation above the Recommended

Operating Conditions is not implied. Extended exposure to stresses above the

Recommended Operating Conditions may affect device reliability.

1. Temperature Derating: Plastic “P and D/DW”

Packages: – 7.0 mW/_C From 65_C To 125_C

This device contains protection circuitry to guard against damage due to high

static voltages or electric fields. However, precautions must be taken to avoid

applications of any voltage higher than maximum rated voltages to this

high−impedance circuit. For proper operation, Vin and Vout should be constrained

to the range VSS v (Vin or Vout) v VDD.

Unused inputs must always be tied to an appropriate logic voltage level

(e.g., either VSS or VDD). Unused outputs must be left open.

Device Package Shipping†

ORDERING INFORMATION

http://onsemi.com

†For information on tape and reel specifications,

including part orientation and tape sizes, please

refer to our Tape and Reel Packaging Specifications

Brochure, BRD8011/D.

MC14175BFELG SOEIAJ−16

(Pb−Free)

2000/Tape & Reel

MC14175BDR2G SOIC−16

(Pb−Free)

2500/Tape & Reel

MC14175BDG SOIC−16

(Pb−Free)

48 Units/Rail

MC14175BCPG PDIP−16

(Pb−Free)

500 Units/Rail

A = Assembly Location

WL, L = Wafer Lot

YY, Y = Year

WW, W = Work Week

G = Pb−Free Package

MARKING

DIAGRAMS

PDIP−16

P SUFFIX

CASE 648

SOIC−16

D SUFFIX

CASE 751B 1

16

14175BG

AWLYWW

SOEIAJ−16

F SUFFIX

CASE 966

1

16

MC14175B

ALYWG

16

1

MC14175BCP

AWLYYWWG

1

MC14175B

http://onsemi.com

2

Figure 1. Pin Assignment

13

14

15

16

9

10

11

125

4

3

2

1

8

7

6

D2

D3

Q3

VDD

C

Q2

D0

Q0

R

VSS

Q1

D1

Q3

Figure 2. Block Diagram

9

1

4

5

12

13

2

7

10

15

CLOCK

RESET

D0

D1

D2

D3

VDD = PIN 16

VSS = PIN 8

Q3

Q2

3

Q1

11

Q0

Q3

6

14

Q0

Q1

Q2

TRUTH TABLE

Inputs Outputs

Clock Data Reset QQ

0101

1110

X1QQ

XX001

X = Don’t Care

No

Change

Figure 3. Timing Diagram

Figure 4. Functional Block Diagram

MC14175B

http://onsemi.com

3

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)

ÎÎÎÎÎÎÎÎÎÎ

Characteristic

ÎÎÎÎ

Symbol

ÎÎÎ

VDD

Vdc

ÎÎÎÎÎ

− 55_C

ÎÎÎÎÎÎÎÎÎ

25_C

ÎÎÎÎÎ

125_C

ÎÎÎ

Unit

ÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎÎ

Min

ÎÎÎ

Typ

(Note 2)

ÎÎÎÎ

Max

ÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎÎÎÎÎÎÎÎ

Output Voltage “0” Level

Vin = VDD or 0

“1” Level

Vin = 0 or VDD

ÎÎÎÎ

VOL

ÎÎÎ

5.0

10

15

ÎÎÎ

−

ÎÎÎ

0.05

ÎÎÎÎ

−

ÎÎÎ

0

ÎÎÎÎ

0.05

ÎÎÎ

−

ÎÎÎ

0.05

ÎÎÎ

Vdc

ÎÎÎÎ

VOH

ÎÎÎ

5.0

10

15

ÎÎÎ

4.95

9.95

14.95

ÎÎÎ

−

ÎÎÎÎ

4.95

9.95

14.95

ÎÎÎ

5.0

10

15

ÎÎÎÎ

−

ÎÎÎ

4.95

9.95

14.95

ÎÎÎ

−

ÎÎÎ

Vdc

ÎÎÎÎÎÎÎÎÎÎ

Input Voltage “0” Level

(VO = 4.5 or 0.5 Vdc)

(VO = 9.0 or 1.0 Vdc)

(VO = 13.5 or 1.5 Vdc)

“1” Level

(VO = 0.5 or 4.5 Vdc)

(VO = 1.0 or 9.0 Vdc)

(VO = 1.5 or 13.5 Vdc)

ÎÎÎÎ

VIL

ÎÎÎ

5.0

10

15

ÎÎÎ

−

ÎÎÎ

1.5

3.0

4.0

ÎÎÎÎ

−

ÎÎÎ

2.25

4.50

6.75

ÎÎÎÎ

1.5

3.0

4.0

ÎÎÎ

−

ÎÎÎ

1.5

3.0

4.0

ÎÎÎ

Vdc

ÎÎÎÎ

VIH

ÎÎÎ

5.0

10

15

ÎÎÎ

3.5

7.0

11

ÎÎÎ

−

ÎÎÎÎ

3.5

7.0

11

ÎÎÎ

2.75

5.50

8.25

ÎÎÎÎ

−

ÎÎÎ

3.5

7.0

11

ÎÎÎ

−

ÎÎÎ

Vdc

ÎÎÎÎÎÎÎÎÎÎ

Output Drive Current

(VOH = 2.5 Vdc) Source

(VOH = 4.6 Vdc)

(VOH = 9.5 Vdc)

(VOH = 13.5 Vdc)

(VOL = 0.4 Vdc) Sink

(VOL = 0.5 Vdc)

(VOL = 1.5 Vdc)

ÎÎÎÎ

IOH

ÎÎÎ

5.0

10

15

ÎÎÎ

– 3.0

– 0.64

– 1.6

– 4.2

ÎÎÎ

−

ÎÎÎÎ

– 2.4

– 0.51

– 1.3

– 3.4

ÎÎÎ

– 4.2

– 0.88

– 2.25

– 8.8

ÎÎÎÎ

−

ÎÎÎ

– 1.7

– 0.36

– 0.9

– 2.4

ÎÎÎ

−

ÎÎÎ

mAdc

ÎÎÎÎ

IOL

ÎÎÎ

5.0

10

15

ÎÎÎ

0.64

1.6

4.2

ÎÎÎ

−

ÎÎÎÎ

0.51

1.3

3.4

ÎÎÎ

0.88

2.25

8.8

ÎÎÎÎ

−

ÎÎÎ

0.36

0.9

2.4

ÎÎÎ

−

ÎÎÎ

mAdc

ÎÎÎÎÎÎÎÎÎÎ

Input Current

ÎÎÎÎ

Iin

ÎÎÎ

15

ÎÎÎ

−

ÎÎÎ

± 0.1

ÎÎÎÎ

−

ÎÎÎ

±0.00001

ÎÎÎÎ

± 0.1

ÎÎÎ

−

ÎÎÎ

± 1.0

ÎÎÎ

mAdc

ÎÎÎÎÎÎÎÎÎÎ

Input Capacitance

(Vin = 0)

ÎÎÎÎ

Cin

ÎÎÎ

−

ÎÎÎ

−

ÎÎÎ

−

ÎÎÎÎ

−

ÎÎÎ

5.0

ÎÎÎÎ

7.5

ÎÎÎ

−

ÎÎÎ

−

ÎÎÎ

pF

ÎÎÎÎÎÎÎÎÎÎ

Quiescent Current

(Per Package)

ÎÎÎÎ

IDD

ÎÎÎ

5.0

10

15

ÎÎÎ

−

ÎÎÎ

5.0

10

20

ÎÎÎÎ

−

ÎÎÎ

0.005

0.010

0.015

ÎÎÎÎ

5.0

10

20

ÎÎÎ

−

ÎÎÎ

150

300

600

ÎÎÎ

mAdc

ÎÎÎÎÎÎÎÎÎÎ

Total Supply Current (Note 3, 4)

(Dynamic plus Quiescent,

Per Package)

(CL = 50 pF on all outputs, all

buffers switching)

ÎÎÎÎ

IT

ÎÎÎ

5.0

10

15

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

IT = (1.7 mA/kHz) f + IDD

IT = (3.4 mA/kHz) f + IDD

IT = (5.0 mA/kHz) f + IDD

ÎÎÎ

mAdc

2. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

3. The formulas given are for the typical characteristics only at 25_C.

4. To calculate total supply current at loads other than 50 pF: IT(CL) = IT(50 pF) + (CL – 50) Vfk where: IT is in mA (per package), CL in pF,

V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.004.

MC14175B

http://onsemi.com

4

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

SWITCHING CHARACTERISTICS (Note 5) (CL = 50 pF, TA = 25_C)

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Characteristic

ÎÎÎÎ

Symbol

ÎÎÎÎ

VDD

Vdc

ÎÎÎÎÎÎÎÎ

All Types

ÎÎÎ

Unit

ÎÎÎ

Min

ÎÎÎÎ

Typ

(Note 6)

ÎÎÎ

Max

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Output Rise and Fall Time

tTLH, tTHL = (1.35 ns/pF) CL + 32 ns

tTLH, tTHL = (0.6 ns/pF) CL + 20 ns

tTLH, tTHL = (0.4 ns/pF) CL + 20 ns

ÎÎÎÎ

tTLH, tTHL

ÎÎÎÎ

5.0

10

15

ÎÎÎ

−

ÎÎÎÎ

100

50

40

ÎÎÎ

200

100

80

ÎÎÎ

ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Propagation Delay Time — Clock to Q, Q

tPLH, tPHL = (0.9 ns/pF) CL + 175 ns

tPLH, tPHL = (0.36 ns/pF) CL + 72 ns

tPLH, tPHL = (0.26 ns/pF) CL + 57 ns

ÎÎÎÎ

tPLH, tPHL

ÎÎÎÎ

5.0

10

15

ÎÎÎ

−

ÎÎÎÎ

220

90

70

ÎÎÎ

400

160

120

ÎÎÎ

ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Propagation Delay Time — Reset to Q, Q

tPHL = (0.9 ns/pF) CL + 280 ns

tPHL = (0.36 ns/pF) CL + 112 ns

tPHL = (0.26 ns/pF) CL + 87 ns

ÎÎÎÎ

tPHL, tPLH

ÎÎÎÎ

5.0

10

15

ÎÎÎ

−

ÎÎÎÎ

325

130

100

ÎÎÎ

500

200

150

ÎÎÎ

ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Clock Pulse Width

ÎÎÎÎ

tWH

ÎÎÎÎ

5.0

10

15

ÎÎÎ

250

100

75

ÎÎÎÎ

110

45

35

ÎÎÎ

−

ÎÎÎ

ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Reset Pulse Width

ÎÎÎÎ

tWL

ÎÎÎÎ

5.0

10

15

ÎÎÎ

200

80

60

ÎÎÎÎ

100

40

30

ÎÎÎ

−

ÎÎÎ

ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Clock Pulse Frequency

ÎÎÎÎ

fcl

ÎÎÎÎ

5.0

10

15

ÎÎÎ

−

ÎÎÎÎ

4.5

11

14

ÎÎÎ

2.0

5.0

6.5

ÎÎÎ

mHz

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Clock Pulse Rise and Fall Time

ÎÎÎÎ

tTLH, tTHL

ÎÎÎÎ

5.0

10

15

ÎÎÎ

−

ÎÎÎÎ

−

ÎÎÎ

15

5.0

4.0

ÎÎÎ

ms

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Data Setup Time

ÎÎÎÎ

tsu

ÎÎÎÎ

5.0

10

15

ÎÎÎ

120

50

40

ÎÎÎÎ

60

25

20

ÎÎÎ

−

ÎÎÎ

ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Data Hold Time

ÎÎÎÎ

th

ÎÎÎÎ

5.0

10

15

ÎÎÎ

80

40

30

ÎÎÎÎ

40

20

15

ÎÎÎ

−

ÎÎÎ

ns

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Reset Removal Time

ÎÎÎÎ

trem

ÎÎÎÎ

5.0

10

15

ÎÎÎ

250

100

80

ÎÎÎÎ

125

50

40

ÎÎÎ

−

ÎÎÎ

ns

5. The formulas given are for the typical characteristics only at 25_C.

6. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.

MC14175B

http://onsemi.com

5

PACKAGE DIMENSIONS

NOTES:

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: INCH.

3. DIMENSION L TO CENTER OF LEADS

WHEN FORMED PARALLEL.

4. DIMENSION B DOES NOT INCLUDE

MOLD FLASH.

5. ROUNDED CORNERS OPTIONAL.

−A−

B

FC

S

H

GD

J

L

M

16 PL

SEATING

18

916

K

PLANE

−T−

M

A

M

0.25 (0.010) T

DIM MIN MAX MIN MAX

MILLIMETERSINCHES

A0.740 0.770 18.80 19.55

B0.250 0.270 6.35 6.85

C0.145 0.175 3.69 4.44

D0.015 0.021 0.39 0.53

F0.040 0.70 1.02 1.77

G0.100 BSC 2.54 BSC

H0.050 BSC 1.27 BSC

J0.008 0.015 0.21 0.38

K0.110 0.130 2.80 3.30

L0.295 0.305 7.50 7.74

M0 10 0 10

S0.020 0.040 0.51 1.01

____

PDIP−16

CASE 648−08

ISSUE T

SOEIAJ−16

CASE 966−01

ISSUE A

HE

A1

DIM MIN MAX MIN MAX

INCHES

--- 2.05 --- 0.081

MILLIMETERS

0.05 0.20 0.002 0.008

0.35 0.50 0.014 0.020

0.10 0.20 0.007 0.011

9.90 10.50 0.390 0.413

5.10 5.45 0.201 0.215

1.27 BSC 0.050 BSC

7.40 8.20 0.291 0.323

0.50 0.85 0.020 0.033

1.10 1.50 0.043 0.059

0

0.70 0.90 0.028 0.035

--- 0.78 --- 0.031

A1

HE

Q1

LE

_10 _0

_10 _

LE

Q1

_

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS D AND E DO NOT INCLUDE

MOLD FLASH OR PROTRUSIONS AND ARE

MEASURED AT THE PARTING LINE. MOLD FLASH

OR PROTRUSIONS SHALL NOT EXCEED 0.15

(0.006) PER SIDE.

4. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

5. THE LEAD WIDTH DIMENSION (b) DOES NOT

INCLUDE DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08 (0.003)

TOTAL IN EXCESS OF THE LEAD WIDTH

DIMENSION AT MAXIMUM MATERIAL CONDITION.

DAMBAR CANNOT BE LOCATED ON THE LOWER

RADIUS OR THE FOOT. MINIMUM SPACE

BETWEEN PROTRUSIONS AND ADJACENT LEAD

TO BE 0.46 ( 0.018).

M

L

DETAIL P

VIEW P

c

A

b

e

M

0.13 (0.005) 0.10 (0.004)

1

16 9

8

D

Z

E

A

b

c

D

E

e

L

M

Z

MC14175B

http://onsemi.com

6

PACKAGE DIMENSIONS

SOIC−16

CASE 751B−05

ISSUE K

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE MOLD

PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.

5. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR PROTRUSION

SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D

DIMENSION AT MAXIMUM MATERIAL CONDITION.

18

16 9

SEATING

PLANE

F

J

M

RX 45_

G

8 PLP

−B−

−A−

M

0.25 (0.010) B S

−T−

D

K

C

16 PL

S

B

M

0.25 (0.010) A S

T

DIM MIN MAX MIN MAX

INCHESMILLIMETERS

A9.80 10.00 0.386 0.393

B3.80 4.00 0.150 0.157

C1.35 1.75 0.054 0.068

D0.35 0.49 0.014 0.019

F0.40 1.25 0.016 0.049

G1.27 BSC 0.050 BSC

J0.19 0.25 0.008 0.009

K0.10 0.25 0.004 0.009

M0 7 0 7

P5.80 6.20 0.229 0.244

R0.25 0.50 0.010 0.019

____

6.40

16X

0.58

16X 1.12

1.27

DIMENSIONS: MILLIMETERS

1

PITCH

SOLDERING FOOTPRINT

16

89

8X

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should

Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,

and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death

associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal

Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

N. American Technical Support: 800−282−9855 Toll Free

USA/Canada

Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81−3−5773−3850

MC14175B/D

LITERATURE FULFILLMENT:

Literature Distribution Center for ON Semiconductor

P.O. Box 5163, Denver, Colorado 80217 USA

Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada

Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada

Email: orderlit@onsemi.com

ON Semiconductor Website: www.onsemi.com

Order Literature: http://www.onsemi.com/orderlit

For additional information, please contact your local

Sales Representative