CMOS 16-BIT SINGLE CHIP MICROCONTROLLER S1C17003 Technical Manual Rev. 1.1 NOTICE No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. 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Configuration of product number Devices S1 C 17xxx F 00E1 00 Packing specifications 00 : Besides tape & reel 0A : TCP BL 2 directions 0B : Tape & reel BACK 0C : TCP BR 2 directions 0D : TCP BT 2 directions 0E : TCP BD 2 directions 0F : Tape & reel FRONT 0G : TCP BT 4 directions 0H : TCP BD 4 directions 0J : TCP SL 2 directions 0K : TCP SR 2 directions 0L : Tape & reel LEFT 0M: TCP ST 2 directions 0N : TCP SD 2 directions 0P : TCP ST 4 directions 0Q : TCP SD 4 directions 0R : Tape & reel RIGHT 99 : Specs not fixed Specification Package D: die form; F: QFP, B: BGA Model number Model name C: microcomputer, digital products Product classification S1: semiconductor Development tools S5U1 C 17000 H2 1 00 Packing specifications 00: standard packing Version 1: Version 1 Tool type Hx : ICE Dx : Evaluation board Ex : ROM emulation board Mx : Emulation memory for external ROM Tx : A socket for mounting Cx : Compiler package Sx : Middleware package Corresponding model number 17xxx: for S1C17xxx Tool classification C: microcomputer use Product classification S5U1: development tool for semiconductor products CONTENTS - CONTENTS 1 Overview........................................................................................................................1-1 1.1 Features ..........................................................................................................................1-2 1.2 Block Diagram .................................................................................................................1-3 1.3 Pins .................................................................................................................................1-4 1.3.1 Pinout Diagram ..................................................................................................1-4 1.3.2 Pin Descriptions .................................................................................................1-8 2 CPU ................................................................................................................................2-1 2.1 2.2 2.3 2.4 2.5 2.6 S1C17 Core Features .....................................................................................................2-1 CPU Registers ................................................................................................................2-2 Instruction Set .................................................................................................................2-3 Vector Table .....................................................................................................................2-7 PSR Readout ..................................................................................................................2-8 Processor Information .....................................................................................................2-9 3 Memory Map and Bus Control.....................................................................................3-1 3.1 Bus Cycle ........................................................................................................................3-2 3.1.1 Access Size Restrictions....................................................................................3-2 3.1.2 Instruction Execution Cycle Restrictions ............................................................3-2 3.2 Mask ROM Area ...............................................................................................................3-3 3.2.1 Mask ROM .........................................................................................................3-3 3.2.2 ROM read access cycle settings........................................................................3-3 0x5320: ROM Control Register (MISC_FL) ............................................................................... 3-3 3.3 Internal RAM Area............................................................................................................3-4 3.3.1 Internal RAM ......................................................................................................3-4 0x5326: IRAM Size Select Register (MISC_IRAMSZ)............................................................... 3-4 3.4 Internal Peripheral Circuit Area .......................................................................................3-5 3.4.1 Internal Peripheral Circuit Area 1 (0x4000 onward) ...........................................3-5 3.4.2 Internal Peripheral Circuit Area 2 (0x5000 onward) ...........................................3-5 3.5 Core I/O Reserved Area ..................................................................................................3-6 4 Power Supply Voltage...................................................................................................4-1 4.1 4.2 4.3 4.4 4.5 Power Supply Pins ...........................................................................................................4-1 Operating Voltage (LVDD, VSS) ..........................................................................................4-2 Power Supply for I/O Interface (HVDD) .............................................................................4-2 Power Supply for Analog Circuits (AVDD) .........................................................................4-2 Precautions on Power Supply ..........................................................................................4-3 5 Initial Reset....................................................................................................................5-1 5.1 Initial Reset Factors .........................................................................................................5-1 5.1.1 #RESET pin .......................................................................................................5-1 5.1.2 P0 Port Key-Entry Reset ....................................................................................5-2 5.1.3 Reset by Watchdog Timer ..................................................................................5-2 5.2 Initial Reset Sequence ....................................................................................................5-3 5.3 Initial Settings at Initial Resetting ....................................................................................5-4 6 Interrupt Controller .......................................................................................................6-1 6.1 ITC Configuration ............................................................................................................6-1 6.2 Vector Table .....................................................................................................................6-2 6.3 Maskable Interrupt Control ..............................................................................................6-3 6.3.1 Peripheral Module Interrupt Control Bit..............................................................6-3 S1C17003 TECHNICAL MANUAL Seiko Epson Corporation i CONTENTS 6.3.2 ITC Interrupt Request Processing .....................................................................6-3 6.3.3 S1C17 Core Interrupt Processing ......................................................................6-4 6.4 NMI ..................................................................................................................................6-5 6.5 Software Interrupts ..........................................................................................................6-6 6.6 HALT and SLEEP Mode Cancellation .............................................................................6-7 6.7 Control Register Details ..................................................................................................6-8 0x4306: Interrupt Level Setup Register 0 (ITC_LV0) ................................................................. 6-9 0x4308: Interrupt Level Setup Register 1 (ITC_LV1) ................................................................ 6-10 0x430a: Interrupt Level Setup Register 2 (ITC_LV2) ................................................................ 6-11 0x430c: Interrupt Level Setup Register 3 (ITC_LV3) ................................................................ 6-12 0x430e: Interrupt Level Setup Register 4 (ITC_LV4) ................................................................ 6-13 0x4310: Interrupt Level Setup Register 5 (ITC_LV5) ................................................................ 6-14 0x4312: Interrupt Level Setup Register 6 (ITC_LV6) ................................................................ 6-15 0x4314: Interrupt Level Setup Register 7 (ITC_LV7) ................................................................ 6-16 0x4316: Interrupt Level Setup Register 8 (ITC_LV8) ................................................................ 6-17 0x4318: Interrupt Level Setup Register 9 (ITC_LV9) ................................................................ 6-18 6.8 Precautions ....................................................................................................................6-19 7 Oscillator Circuit (OSC)................................................................................................7-1 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 OSC Module Configuration .............................................................................................7-1 OSC3 Oscillator Circuit ...................................................................................................7-2 OSC1 Oscillator Circuit ...................................................................................................7-3 Clock Switching ...............................................................................................................7-4 8-bit OSC1 Timer Clock Control ......................................................................................7-5 Clock External Output (FOUTH, FOUT1).........................................................................7-6 RESET and NMI Input Noise Filters.................................................................................7-8 Control Register Details ...................................................................................................7-9 0x5060: Clock Source Select Register (OSC_SRC) ................................................................ 7-10 0x5061: Oscillation Control Register (OSC_CTL) .................................................................... 7-11 0x5062: Noise Filter Enable Register (OSC_NFEN) ................................................................ 7-12 0x5064: FOUT Control Register (OSC_FOUT) ........................................................................ 7-13 0x5065: T8OSC1 Clock Control Register (OSC_T8OSC1) ...................................................... 7-14 7.9 Precautions .....................................................................................................................7-15 8 Clock Generator (CLG) .................................................................................................8-1 8.1 8.2 8.3 8.4 Clock Generator Configuration ........................................................................................8-1 CPU Core Clock (CCLK) Control ....................................................................................8-2 Peripheral Module Clock (PCLK) Control ........................................................................8-3 Control Register Details ..................................................................................................8-4 0x5080: PCLK Control Register (CLG_PCLK) .......................................................................... 8-5 0x5081: CCLK Control Register (CLG_CCLK) .......................................................................... 8-6 8.5 Precautions .....................................................................................................................8-7 9 Prescaler (PSC) .............................................................................................................9-1 9.1 Prescaler Configuration ...................................................................................................9-1 9.2 Control Register Details ..................................................................................................9-2 0x4020: Prescaler Control Register (PSC_CTL) ....................................................................... 9-2 9.3 Precautions .....................................................................................................................9-3 10 Input/Output Port (P) .................................................................................................10-1 10.1 10.2 10.3 10.4 ii Input/Output Port Configuration ....................................................................................10-1 Input/Output Pin Function Selection (Port MUX) ...........................................................10-2 Data Input/Output ..........................................................................................................10-3 Pull-up Control ..............................................................................................................10-5 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL CONTENTS 10.5 P0 and P1 Port Chattering Filter Function ....................................................................10-6 10.6 Port Input Interrupt ........................................................................................................10-7 10.7 Control Register Details ................................................................................................10-9 0x5200/0x5210/0x5220/0x5230/0X5240: Px Port Input Data Registers (Px_IN) .................... 10-10 0x5201/0x5211/0x5221/0x5231/0X5241: Px Port Output Data Registers (Px_OUT) ............. 10-11 0x5202/0x5212/0x5222/0x5232/0x5242: Px Port Output Enable Registers (Px_OEN) .......... 10-12 0x5203/0x5213/0x5223/0x5233/0x5234: Px Port Pull-up Control Registers (Px_PU) ............ 10-13 0x5205/5215: Px Port Interrupt Mask Registers (Px_IMSK) ................................................... 10-14 0x5206/5216: Px Port Interrupt Edge Select Registers (Px_EDGE) ....................................... 10-15 0x5207/5217: Px Port Interrupt Flag Registers (Px_IFLG) ..................................................... 10-16 0x5208/0x5218: Px Port Chattering Filter Control Register (Px_CHAT) ................................. 10-17 0x5209: P0 Port Key-Entry Reset Configuration Register (P0_KRST) .................................... 10-19 0x520a/0x521a/0x522a/0x523a/0x524a: Px Port Input Enable Registers (Px_IEN)............... 10-20 0x52a0: P0 Port Function Select Register (P0_PMUX)........................................................... 10-21 0x52a1: P0 Port Function Select Register (P0_PMUX)........................................................... 10-22 0x52a2: P1 Port Function Select Register (P1_PMUX)........................................................... 10-23 0x52a3: P1 Port Function Select Register (P1_PMUX)........................................................... 10-24 0x52a4: P2 Port Function Select Register (P2_PMUX)........................................................... 10-25 0x52a5: P2 Port Function Select Register (P2_PMUX)........................................................... 10-26 0x52a6: P3 Port Function Select Register (P3_PMUX)........................................................... 10-27 0x52a7: P3 Port Function Select Register (P3_PMUX)........................................................... 10-28 0x52a8: P4 Port Function Select Register (P4_PMUX)........................................................... 10-29 10.8 Precautions ..................................................................................................................10-30 11 16-bit Timer (T16) .......................................................................................................11-1 11.1 16-bit Timer Overview ...................................................................................................11-1 11.2 16-bit Timer Operating Modes .......................................................................................11-2 11.2.1 Internal Clock Mode ........................................................................................11-2 11.2.2 External Clock Mode .......................................................................................11-3 11.2.3 Pulse Width Measurement Mode ....................................................................11-4 11.3 Count Mode...................................................................................................................11-5 11.4 16-bit Timer Reload Register and Underflow Cycle ......................................................11-6 11.5 16-bit Timer Reset .........................................................................................................11-7 11.6 11.7 11.8 11.9 16-bit Timer RUN/STOP Control ...................................................................................11-8 16-bit Timer Output Signal ............................................................................................11-9 16-bit Timer Interrupts ..................................................................................................11-10 Control Register Details ...............................................................................................11-11 0x4220/0x4240/0x4260: 16-bit Timer Ch.x Input Clock Select Registers (T16_CLKx) ........... 11-12 0x4222/0x4242/0x4262: 16-bit Timer Ch.x Reload Data Registers (T16_TRx) ...................... 11-13 0x4224/0x4244/0x4264: 16-bit Timer Ch.x Counter Data Registers (T16_TCx) ..................... 11-14 0x4226/0x4246/0x4266: 16-bit Timer Ch.x Control Registers (T16_CTLx)............................. 11-15 0x4228/0x4248/0x4268: 16-bit Timer Ch.x Interrupt Control Registers (T16_INTx) ............... 11-17 11.10 Precautions ................................................................................................................11-18 12 8-bit Timer (T8F) .........................................................................................................12-1 12.1 12.2 12.3 12.4 12.5 12.6 12.7 12.8 12.9 8-bit Timer Overview .....................................................................................................12-1 8-bit Timer Count Mode.................................................................................................12-2 Count Clock ...................................................................................................................12-3 8-bit Timer Reload Register and Underflow Cycle ........................................................12-4 8-bit Timer Reset ...........................................................................................................12-5 8-bit Timer RUN/STOP Control .....................................................................................12-6 8-bit Timer Output Signal ..............................................................................................12-7 Fine Mode .....................................................................................................................12-8 8-bit Timer Interrupts .....................................................................................................12-9 S1C17003 TECHNICAL MANUAL Seiko Epson Corporation iii CONTENTS 12.10 Control Register Details .............................................................................................12-10 0x4200/0x4280: 8-bit Timer Ch.x Input Clock Select Register (T8F_CLKx) ........................... 12-11 0x4202/0x4282: 8-bit Timer Ch.x Reload Data Register (T8F_TRx)....................................... 12-12 0x4204/0x4284: 8-bit Timer Ch.x Counter Data Register (T8F_TCx) ..................................... 12-13 0x4206/0x4286: 8-bit Timer Ch.x Control Register (T8F_CTLx) ............................................. 12-14 0x4208/0x4288: 8-bit Timer Ch.x Interrupt Control Register (T8F_INTx) ............................... 12-16 12.11 Precautions ................................................................................................................12-17 13 PWM Timer (T16E)......................................................................................................13-1 13.1 13.2 13.3 13.4 13.5 13.6 13.7 13.8 PWM Timer Overview ...................................................................................................13-1 PWM Timer Operating Modes .......................................................................................13-2 Setting and Resetting Counter Value ............................................................................13-3 Compare Data Settings .................................................................................................13-4 PWM Timer RUN/STOP Control....................................................................................13-5 Clock Output Control .....................................................................................................13-6 PWM Timer Interrupts ...................................................................................................13-9 Control Register Details ...............................................................................................13-11 0x5300: PWM Timer Compare Data A Register (T16E_CA) ................................................... 13-12 0x5302: PWM Timer Compare Data B Register (T16E_CB) ................................................... 13-13 0x5304: PWM Timer Counter Data Register (T16E_TC)......................................................... 13-14 0x5306: PWM Timer Control Register (T16E_CTL) ................................................................ 13-15 0x5308: PWM Timer Input Clock Select Register (T16E_CLK) ............................................... 13-17 0x530a: PWM Timer Interrupt Mask Registers (T16E_IMSK) ................................................. 13-18 0x530c: PWM Timer Interrupt Flag Registers (T16E_IFLG) .................................................... 13-19 13.9 Precautions ..................................................................................................................13-20 14 8-bit OSC1 Timer (T8OSC1).......................................................................................14-1 14.1 8-bit OSC1 Timer Overview ..........................................................................................14-1 14.2 8-bit OSC1 Timer Count Mode ......................................................................................14-2 14.3 Count Clock ...................................................................................................................14-3 14.4 Resetting 8-bit OSC1 Timer ..........................................................................................14-4 14.5 Compare Data Settings .................................................................................................14-5 14.6 8-bit OSC1 Timer RUN/STOP Control...........................................................................14-6 14.7 8-bit OSC1 Timer Interrupts ..........................................................................................14-7 14.8 PWM output ..................................................................................................................14-8 14.9 Control Register Details .................................................................................................14-9 0x50c0: 8-bit OSC1 Timer Control Register (T8OSC1_CTL) .................................................. 14-10 0x50c1: 8-bit OSC1 Timer Counter Data Register (T8OSC1_CNT) ........................................ 14-11 0x50c2: 8-bit OSC1 Timer Compare Data Register (T8OSC1_CMP) ..................................... 14-12 0x50c3: 8-bit OSC1 Timer Interrupt Mask Register (T8OSC1_IMSK) ..................................... 14-13 0x50c4: 8-bit OSC1 Timer Interrupt Flag Register (T8OSC1_IFLG) ....................................... 14-14 0x50c5: 8-bit OSC1 Timer PWM Duty Data Register (T8OSC1_DUTY) ................................. 14-15 14.10 Precautions ................................................................................................................14-16 15 Clock Timer (CT) ........................................................................................................15-1 15.1 Clock Timer Overview ...................................................................................................15-1 15.2 Operation Clock.............................................................................................................15-2 15.3 15.4 15.5 15.6 Clock Timer Resetting ...................................................................................................15-3 Clock Timer RUN/STOP Control ...................................................................................15-4 Clock Timer Interrupts ...................................................................................................15-5 Control Register Details ................................................................................................15-6 0x5000: Clock Timer Control Register (CT_CTL) ..................................................................... 15-7 0x5001: Clock Timer Counter Register (CT_CNT) ................................................................... 15-8 0x5002: Clock Timer Interrupt Mask Register (CT_IMSK)........................................................ 15-9 iv Seiko Epson Corporation S1C17003 TECHNICAL MANUAL CONTENTS 0x5003: Clock Timer Interrupt Flag Register (CT_IFLG) ......................................................... 15-10 15.7 Precautions ..................................................................................................................15-11 16 Stopwatch Timer (SWT) .............................................................................................16-1 16.1 16.2 16.3 16.4 16.5 16.6 16.7 Stopwatch Timer Overview............................................................................................16-1 BCD Counters ...............................................................................................................16-2 Operation Clock.............................................................................................................16-3 Stopwatch Timer Resetting ...........................................................................................16-4 Stopwatch Timer RUN/STOP Control............................................................................16-5 Stopwatch Timer Interrupts ...........................................................................................16-6 Control Register Details ................................................................................................16-7 0x5020: Stopwatch Timer Control Register (SWT_CTL) .......................................................... 16-8 0x5021: Stopwatch Timer BCD Counter Register (SWT_BCNT) ............................................. 16-9 0x5022: Stopwatch Timer Interrupt Mask Register (SWT_IMSK)............................................ 16-10 0x5023: Stopwatch Timer Interrupt Flag Register (SWT_IFLG) .............................................. 16-11 16.8 Precautions ..................................................................................................................16-12 17 Watchdog Timer (WDT)..............................................................................................17-1 17.1 Watchdog Timer Overview ............................................................................................17-1 17.2 Operation Clock.............................................................................................................17-2 17.3 Watchdog Timer Control ................................................................................................17-3 17.3.1 NMI/Reset Mode Selection .............................................................................17-3 17.3.2 Watchdog Timer Run/Stop Control .................................................................17-3 17.3.3 Watchdog Timer Resetting ..............................................................................17-3 17.3.4 Operation in Standby Mode ............................................................................17-3 17.4 Control Register Details ................................................................................................17-4 0x5040: Watchdog Timer Control Register (WDT_CTL)........................................................... 17-5 0x5041: Watchdog Timer Status Register (WDT_ST) .............................................................. 17-6 17.5 Precautions ...................................................................................................................17-7 18 UART ...........................................................................................................................18-1 18.1 18.2 18.3 18.4 18.5 18.6 18.7 18.8 18.9 UART Configuration ......................................................................................................18-1 UART Pin ......................................................................................................................18-2 Transfer Clock ................................................................................................................18-3 Transfer Data Settings ...................................................................................................18-4 Data Transfer Control ....................................................................................................18-5 Receive Errors...............................................................................................................18-8 UART Interrupts ............................................................................................................18-9 IrDA Interface ...............................................................................................................18-11 Control Register Details ...............................................................................................18-13 0x4100: UART Status Register (UART_ST) ............................................................................ 18-14 0x4101/0x4121: UART Ch.x Transmit Data Registers (UART_TXDx) ..................................... 18-16 0x4102/0x4122: UART Ch.x Receive Data Registers (UART_RXDx) ..................................... 18-17 0x4103/0x4123: UART Ch.x Mode Registers (UART_MODx) ................................................ 18-18 0x4104/0x4124: UART Ch.x Control Registers (UART_CTLx) ............................................... 18-19 0x4105/0x4125: UART Ch.x Expansion Registers (UART_EXPx) .......................................... 18-20 18.10 Precautions ................................................................................................................18-21 19 SPI ...............................................................................................................................19-1 19.1 19.2 19.3 19.4 SPI Configuration ..........................................................................................................19-1 SPI Input/Output Pins....................................................................................................19-2 SPI Clock ......................................................................................................................19-3 Data Transfer Condition Settings ...................................................................................19-4 S1C17003 TECHNICAL MANUAL Seiko Epson Corporation v CONTENTS 19.5 Data Transfer Control ....................................................................................................19-5 19.6 SPI Interrupts ................................................................................................................19-8 19.7 Control Register Details ................................................................................................19-9 0x4320: SPI Status Register (SPI_ST) .................................................................................... 19-10 0x4322: SPI Transmit Data Register (SPI_TXD) ..................................................................... 19-11 0x4324: SPI Receive Data Register (SPI_RXD) ..................................................................... 19-12 0x4326: SPI Control Register (SPI_CTL) ................................................................................ 19-13 19.8 Precautions ..................................................................................................................19-15 20 I2C Master (I2CM) ........................................................................................................20-1 20.1 20.2 20.3 20.4 20.5 20.6 20.7 I2C Master Configuration ...............................................................................................20-1 I2C Master Input/Output Pins ........................................................................................20-2 I2C Master Clock ...........................................................................................................20-3 Settings Before Data Transfer .......................................................................................20-4 Data Transfer Control ....................................................................................................20-5 I2C Master Interrupts ...................................................................................................20-10 Control Register Details ...............................................................................................20-11 0x4340: I2C Enable Register (I2C_EN) ................................................................................... 20-12 0x4342: I2C Control Register (I2C_CTL) ................................................................................. 20-13 0x4344: I2C Data Register (I2C_DAT) ..................................................................................... 20-15 0x4346: I2C Interrupt Control Register (I2C_ICTL) .................................................................. 20-17 21 I2C Slave (I2CS) ..........................................................................................................21-1 Configuration of the I2C Slave Module ..........................................................................21-1 I2C Slave I/O Pins..........................................................................................................21-2 I2C Slave Clock .............................................................................................................21-3 Initializing the I2C Slave.................................................................................................21-4 21.4.1 Reset ..............................................................................................................21-4 21.4.2 Setting the Slave Address ...............................................................................21-4 21.4.3 Optional Functions ..........................................................................................21-4 21.5 Data Transmit/Receive Control ......................................................................................21-6 21.1 21.2 21.3 21.4 21.6 I2C Slave Interrupt ........................................................................................................21-11 21.7 Details of Control Registers .........................................................................................21-13 0x4360: I2C Slave Transmit Data Register (I2CS_TRNS)........................................................ 21-14 0x4362: I2C Slave Receive Data Register (I2CS_RECV) ........................................................ 21-15 0x4364: I2C Slave Address Setup Register (I2CS_SADRS) ................................................... 21-16 0x4366: I2C Slave Control Register (I2CS_CTL) ..................................................................... 21-17 0x4368: I2C Slave Status Register (I2CS_STAT) ..................................................................... 21-20 0x436a: I2C Slave Access Status Register (I2CS_ASTAT) ...................................................... 21-23 0x436c: I2C Slave Interrupt Control Register (I2CS_ICTL)...................................................... 21-24 21.8 Precautions ..................................................................................................................21-25 22 Remote Controller (REMC) .......................................................................................22-1 22.1 22.2 22.3 22.4 22.5 REMC Configuration .....................................................................................................22-1 REMC Input/output Pin .................................................................................................22-2 Carrier Generation ........................................................................................................22-3 Data Length Counter Clock Settings .............................................................................22-4 Data Transfer Control ....................................................................................................22-5 22.6 REMC Interrupts ...........................................................................................................22-8 22.7 Control Register Details ...............................................................................................22-10 0x5340: REMC Configuration Register (REMC_CFG) ............................................................ 22-11 0x5342: REMC Carrier Length Setup Register (REMC_CAR) ................................................ 22-13 0x5344: REMC Length Counter Register (REMC_LCNT) ....................................................... 22-14 0x5346: REMC Interrupt Control Register (REMC_INT) ......................................................... 22-15 vi Seiko Epson Corporation S1C17003 TECHNICAL MANUAL CONTENTS 22.8 Precautions ..................................................................................................................22-17 23 A/D Converter (ADC10SA) ........................................................................................23-1 23.1 23.2 23.3 23.4 23.5 23.6 Outline of A/D Converter ...............................................................................................23-1 ADC Terminal ................................................................................................................23-2 A/D Converter Settings .................................................................................................23-3 A/D Conversion Control and Operations .......................................................................23-6 A/D Converter interrupt .................................................................................................23-9 Controlling Register Details..........................................................................................23-11 0x5380: ADC10 Conversion Result Register (ADC10_ADD) .................................................. 23-12 0x5382: ADC10 Trigger/Channel Selection Register (ADC10_TRG) ...................................... 23-13 0x5384: ADC10 Control/Status Register (ADC10_CTL) ......................................................... 23-15 0x5386: ADC10 Divided Frequency Register (ADC10_DIV) ................................................... 23-17 23.7 Notes ............................................................................................................................23-18 24 On-chip Debugger (DBG) ..........................................................................................24-1 24.1 24.2 24.3 24.4 Resource Requirements and Debugging Tool ...............................................................24-1 Debug Break Operation Status .....................................................................................24-2 Additional Debugging Function .....................................................................................24-3 Control Register Details ................................................................................................24-4 0x5322: OSC1 Peripheral Control Register (MISC_OSC1) ..................................................... 24-5 0x5326: IRAM Size Select Register (MISC_IRAMSZ).............................................................. 24-6 0xffff90: Debug RAM Base Register (DBRAM) ....................................................................... 24-7 0xffffa0: Debug Control Register (DCR) ................................................................................... 24-8 0xffffb8: Instruction Break Address Register 2 (IBAR2) .......................................................... 24-10 0xffffbc: Instruction Break Address Register 3 (IBAR3) ........................................................... 24-11 0xffffd0: Instruction Break Address Register 4 (IBAR4) .......................................................... 24-12 25 Multiplier/Divider........................................................................................................25-1 25.1 25.2 25.3 25.4 25.5 25.6 Overview .......................................................................................................................25-1 Operating Mode and Output Mode ................................................................................25-2 Multiplication .................................................................................................................25-3 Division..........................................................................................................................25-4 Product-sum Operation .................................................................................................25-5 Arithmetic Results Reading ...........................................................................................25-7 26 Electrical Characteristics ..........................................................................................26-1 26.1 26.2 26.3 26.4 26.5 26.6 26.7 26.8 26.9 Absolute Maximum Ratings ..........................................................................................26-1 Recommended Operating Conditions ...........................................................................26-1 Current Consumption ....................................................................................................26-2 Input/Output Terminal Characteristics ...........................................................................26-3 A/D Converter Characteristics.......................................................................................26-4 SPI Characteristics........................................................................................................26-5 I2C Characteristics ........................................................................................................26-5 Oscillation Circuit Characteristics..................................................................................26-6 External Clock Input Characteristics .............................................................................26-6 27 Basic External Connection Diagram ........................................................................27-1 28 Package ......................................................................................................................28-1 28.1 28.2 28.3 28.4 TQFP12-64 pin package ...............................................................................................28-1 WCSP-48 package ........................................................................................................28-2 Thermal Resistance of the Package..............................................................................28-3 Pad Layout ....................................................................................................................28-4 S1C17003 TECHNICAL MANUAL Seiko Epson Corporation vii CONTENTS 28.4.1 Diagram of Pad Layout ...................................................................................28-4 Appendix A: I/O Register List ....................................................................................... AP-1 0x4020 0x4100-0x4125 0x4200-0x4208 0x4220-0x4268 0x4280-0x4288 0x4306-0x4318 0x4320-0x4326 0x4340-0x4346 0x4360-0x436c 0x5000-0x5003 0x5020-0x5023 0x5040-0x5041 0x5060-0x5065 0x5080-0x5081 0x50c0-0x50c5 0x5200-0x52a8 0x5300-0x530c 0x5320-0x532c 0x5340-0x5346 0x5380-0x5386 0xffff84-0xffffd0 Prescaler .................................................................................. AP-5 UART (with IrDA)...................................................................... AP-6 8-bit Timer (with Fine Mode) Ch.0............................................ AP-8 16-bit Timer .............................................................................. AP-9 8-bit Timer (with Fine Mode) Ch.1........................................... AP-11 Interrupt Controller .................................................................. AP-12 SPI .......................................................................................... AP-13 I2C Master ............................................................................... AP-14 I2C Slave ................................................................................. AP-15 Clock Timer ............................................................................. AP-16 Stopwatch Timer ..................................................................... AP-17 Watchdog Timer ...................................................................... AP-18 Oscillator ................................................................................. AP-19 Clock Generator ...................................................................... AP-20 8-bit OSC1 Timer .................................................................... AP-21 P Port & Port MUX .................................................................. AP-22 PWM & Capture Timer ............................................................ AP-26 MISC Registers ....................................................................... AP-27 Remote Controller ................................................................... AP-28 ADC10SA................................................................................ AP-29 S1C17 Core I/O ...................................................................... AP-30 Appendix B: Power Saving .......................................................................................... AP-31 B.1 Clock Control Power Saving.......................................................................................... AP-31 Appendix C: Mounting Precautions ............................................................................ AP-34 Appendix D: Developing S1C17003 Mask ROM Code ............................................... AP-38 Revision History viii Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 1 Overview 1 Overview The S1C17003 is a 16-bit MCU featuring high-speed low-power operations, compact dimensions, wide address space and on-chip ICE. A/D converter is built in and sensor of various analog I/F can be connected. It is suitable for the application of health care product, sports watch and meter module etc. with sensor that is required a small size and micro display in the battery driven. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 1-1 1 Overview 1.1 Features The main features of the S1C17003 are listed below. CPU * Epson original 16-bit RISC CPU core S1C17 * 16 bit x 16 bit + 32 bit product-sum operation, 16 bit / 16bit division arithmetic unit OSC3 oscillator circuit OSC1 oscillator circuit Internal Mask ROM Internal RAM A/D Converter Input/output port * * * * * * Serial interface * * * * * * * * * * * * * * * * * * * * * * * * Timer Interrupt Power supply voltage Operating temperatures Current consumption Configuration as shipped * 1-2 Crystal oscillator circuit or ceramic oscillator circuit, 20 MHz (max.) Crystal oscillator circuit 32.786 kHz (typ.) 64 Kbytes (for both instructions and data) 4 Kbytes 10 bit resolution 4ch. Max. 30-bit general purpose input/output port, 4-bit input only port SPI (master/slave) 1ch. I2C (master) 1ch. I2C (slave) 1ch. UART (460,800bps, IrDA1.0 compatible) 2ch. Remote controller (REMC) 1ch. 8-bit timer (T8F) 2ch. 16-bit timer (T16) 3ch. PWM timer (T16E) 1ch. Clock timer (CT) 1ch. Stopwatch timer (SWT) 1ch. Watchdog timer (WDT) 1ch. 8-bit OSC1 PWM timer (T8OSC1) 1ch. NMI, P Port Input interrupt 3ch. Serial Interface interrupt 5ch. Timer interrupt 9ch. HVDD(I/O) : 1.65 to 3.6V LVDD(Core) : 1.65 to 1.95V AVDD(I/O) : 2.7V to 3.6V -40C to 85C SLEEP mode: 1 A (typ.) off/1.8V HALT mode: 3.3 A (typ.) 32kHz/1.8V When operating: 4.0 mA (typ.) 20MHz/1.8V TQFP12-64pin (7 mm x 7 mm x 1.2 mm, 0.4 mm pin pitch) WCSP-48pin (3.124 mm x 3.124 mm x 0.78 mm, 0.4 mm ball pitch) Chip (3.124 mm x 3.124 mm x 0.40 mm) Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 1 Overview 1.2 Block Diagram DCLK, DST2, DSIO(P41-43) CPU Core S1C17 32 bits 1 cycle 8/16 bits 1 cycle Internal RAM (4K bytes) I/O 2 (0x5000-) A/D converter Mask ROM (64K bytes) 16 bits 1-5 cycles AIN0-3,#ADTRG (P22-20, P17) MISC register #RESET Test circuit Oscillator/ Clock generator Reset circuit 8/16 bits 1 cycle I/O 1 (0x4000-) Interrupt system TEST Interrupt controller 8-bit OSC1 PWM timer Prescaler Clock timer 8-bit timer Stopwatch timer EXCL0-2 (P02, P13, P14) 16-bit timer Watchdog timer SIN0, SOUT0, SCLK0(P12-10), SIN1, SOUT1, SCLK1(P30-29,P16) UART (2ch) 16-bit PWM timer SPI Remote controller SDA0, SCL0(P32-31) or (P34-33) I2C master (1ch) I/O port/ I/O MUX SDA1, SCL1(P34-33) #BFR(P35) I2C slave (1ch) SDI, SDO, SPICLK(P06-04) #SPISS(P07) OSC1-2, OSC3-4 FOUT1(P35), FOUTH(P40) TOUT4(P37) EXCL3(P15), TOUT3(P36), TOUTN3(P37) REMI(P01), REMO(P00) P00-07, P10-17, P20-24, P27, P30-37, P40-43 Figure 1.2.1: Block diagram S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 1-3 1 Overview 1.3 Pins 1.3.1 Pinout Diagram The S1C17003 comes in a TQFP12-64 pin or a WCSP-48 package. 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VSS P03 (#ADTRG) P02 (EXCL0) P01 (REMI) P00 (REMO) N.C. #RESET LVDD TEST DCLK (P43) LVDD DST2 (P42) HVDD VSS DSIO (P41) P40 (FOUTH) P23 VSS P24 (SOUT1) P27 (SIN1) P30 LVDD HVDD (SCL0) P31 (SDA0) P32 (SCL1/SCL0) P33 (SDA1/SDA0) P34 (FOUT1/#BFR) P35 HVDD (TOUT3) P36 (TOUTN3) P37 VSS (SCLK) P10 LVDD (SOUT) P11 (SIN) P12 (EXCL1) P13 (EXCL2) P14 HVDD VSS (EXCL3) P15 (SCLK1) P16 N.C. AVDD (AIN3) P17 (AIN2) P20 (AIN1) P21 (AIN0) P22 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 LVDD N.C. P07 (#SPISS) P06 (SDI) HVDD P05 (SDO) P04 (SPICLK) VSS OSC4 VSS N.C. OSC3 VSS OSC2 VSS OSC1 TQFP12-64pin Figure 1.3.1.1: Pinout diagramTQFP12-64pin 1-4 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 1 Overview WCSP-48 package A1 Corner Top View A1 Corner Bottom View A A Index B B C C D D E E F F G G 1 2 3 4 5 6 7 7 6 5 4 3 2 1 Top View 2 5 P34 SDA1 SDA0 6 P36 TOUT3 7 P40 FOUTH P32 SDA0 P35 FOUT1 #BFR P37 TOUTN3 DSIO P41 HVDD P33 SCL1 SCL0 VSS DST2 P42 AVDD VSS LVDD DCLK P43 TEST P13 EXCL1 P12 SIN HVDD P01 REMI P00 REMO #RESET P11 SOUT LVDD P06 SDI P04 SPICLK VSS P03 #ADTRG P02 EXCL0 P10 SCLK P07 #SPISS P05 SDO OSC4 OSC3 OSC2 OSC1 1 3 P24 P30 SIN1 P31 SCL0 P21 AIN1 P22 AIN0 P27 SOUT1 P17 AIN3 P20 AIN2 P15 EXCL3 P16 SCLK1 P14 EXCL2 A B C D E F G 4 P23 Figure 1.3.1.2: Pinout diagramWCSP-48 S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 1-5 1 Overview CHIP-88pad 66 60 55 50 45 67 89 44 70 40 35 (0, 0) X 80 3.124mm Y 75 30 85 25 88 23 1 5 10 15 20 22 90 3.124mm Opening of Pad Pad No. 110, 13 22, 45 54, 57 66 : 90mx88m Pad No. 11, 12, 55, 56 : 115mx88m Pad No. 23 32, 35 44, 67 76, 79 88 : 88mx90m Pad No. 33, 34, 77, 78 : 88mx115m Chip thickness 400m 1-6 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 1 Overview Pad Coordinates PAD No. X (mm) Y (mm) Assignment PAD No. X (mm) Y (mm) Assignment 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 -1.075 -0.975 -0.875 -0.775 -0.675 -0.575 -0.475 -0.375 -0.275 -0.175 -0.063 0.063 0.175 0.275 0.375 0.475 0.575 0.675 0.775 0.875 0.975 1.075 1.433 1.433 1.433 1.433 1.433 1.433 1.433 1.433 1.433 1.433 1.433 1.433 1.433 1.433 1.433 1.433 1.433 1.433 1.433 1.433 1.433 1.433 -1.433 -1.433 -1.433 -1.433 -1.433 -1.433 -1.433 -1.433 -1.433 -1.433 -1.433 -1.433 -1.433 -1.433 -1.433 -1.433 -1.433 -1.433 -1.433 -1.433 -1.433 -1.433 -1.075 -0.975 -0.875 -0.775 -0.675 -0.575 -0.475 -0.375 -0.275 -0.175 -0.063 0.063 0.175 0.275 0.375 0.475 0.575 0.675 0.775 0.875 0.975 1.075 P23 VSS VSS P24 NC P27 P30 LVDD LVDD HVDD HVDD P31 P32 P33 P34 P35 HVDD P36 P37 VSS VSS NC NC P40 NC DSIO VSS VSS HVDD DST2 LVDD DCLK TEST LVDD LVDD #RESET NC P00 P01 P02 NC P03 VSS VSS 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 1.433 1.075 0.975 0.875 0.775 0.675 0.475 0.375 0.275 0.175 0.063 -0.063 -0.175 -0.275 -0.375 -0.475 -0.575 -0.675 -0.775 -0.875 -0.975 -1.075 -1.433 -1.433 -1.433 -1.433 -1.433 -1.433 -1.433 -1.433 -1.433 -1.433 -1.433 -1.433 -1.433 -1.433 -1.433 -1.433 -1.433 -1.433 -1.433 -1.433 -1.433 -1.433 1.075 1.433 1.433 1.433 1.433 1.433 1.433 1.433 1.433 1.433 1.433 1.433 1.433 1.433 1.433 1.433 1.433 1.433 1.433 1.433 1.433 1.433 1.075 0.975 0.875 0.775 0.675 0.575 0.475 0.375 0.275 0.175 0.063 -0.063 -0.175 -0.275 -0.375 -0.475 -0.575 -0.675 -0.775 -0.875 -0.975 -1.075 NC OSC1 VSS VSS OSC2 NC VSS OSC3 NC VSS OSC4 VSS NC P04 P05 HVDD P06 P07 NC LVDD NC NC P10 NC LVDD LVDD P11 P12 P13 P14 HVDD VSS P15 VSS P16 AVDD NC AVDD P17/AIN3 P20/AIN2 AVDD P21/AIN1 P22/AIN0 NC S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 1-7 1 Overview 1.3.2 Pin Descriptions Table 1.3.2.1: Pin descriptions PAD/Pin/Ball No. CHIP TQFP WCSP 1 1 2 A1 3 4 5 6 A2 B3 A3 *4 7 *4 12 13 14 15 16 8 9 10 11 12 13 A4 B4 C5 A5 B5 14 15 16 A6 B6 17 18 19 A7 B7 *4 20 *4 30 21 22 C7 23 24 25 D6 D7 26 27 E7 28 29 30 31 32 E6 E5 F7 F6 33 34 G7 35 G6 *2 4 6 7 *3 *4 18 19 *2 24 26 *2 *3 32 33 *3 36 38 39 40 42 *2 46 *2 49 1-8 *2 *3 *4 *2 *2 *3 *3 - *2 *2 I/O Default status P23 VSS I/O I(Pull-UP) - - P24 P27/SOUT1 P30/SIN1 LVDD I/O I/O I/O I(Pull-UP) I(Pull-UP) I(Pull-UP) - - P31/SCL0 P32/SDA0 P33/SCL1/SCL0 P34/SDA1/SDA0 P35/FOUT1/#BFR HVDD I/O I/O I/O I/O I/O I(Pull-UP) I(Pull-UP) I(Pull-UP) I(Pull-UP) I(Pull-UP) - - P36/TOUT3 P37/TOUTN3 VSS I/O I/O I(Pull-UP) I(Pull-UP) - - P40/FOUTH DSIO/P41 VSS I/O I/O I(Pull-UP) I(Pull-UP) - - DST2/P42 LVDD I/O O(L) - - DCLK/P43 TEST LVDD I/O I O(H) I(Pull-UP) Name HVDD HVDD #RESET -NC P00/REMO P01/REMI P02/EXCL0 P03/#ADTRG VSS - - I I(Pull-UP) - - I/O I/O I/O I/O I(Pull-UP) I(Pull-UP) I(Pull-UP) I(Pull-UP) - - Function (Default/Shared by setting) I/O common port Power supply (-) I/O common port I/O common port*1/UART Ch1 data output I/O common port*1/UART Ch1 data input Core power supply (+) I/O Power supply (+) I/O common port*1/I2C master clock output I/O common port*1/I2C master data I/O I/O common port*1/I2C slave clock input/I2C master clock output I/O common port*1/I2C slave data I/O /I2C master data I/O I/O common port*1/OSC1 external clock output/I2C slave bus open I/O Power supply (+) I/O common port*1/T16E Ch0 PWM signal output (non-inverted) I/O common port*1/T16E Ch0 PWM signal output (inverted) Power supply (-) I/O common port*1/HSCLK clock output (with divide) On-chip debugger data I/O*1/I/O common port Power supply (-) I/O Power supply (+) On-chip debugger status output*1/I/O common port Core power supply (+) On-chip debugger clock output*1/I/O common port Test pin (fixed to VSS) Core power supply (+) Initial set input (with the noise filter) I/O common port (with inturrupt) *1/REMC output I/O common port (with inturrupt)*1/REMC input I/O common port (with inturrupt)*1/T16 Ch0 external clock input I/O common port (with inturrupt)*1/ A/D convert external trigger Power supply (-) OSC1 VSS I I - - OSC1 oscillator input*6 Power supply (-) OSC2 O O OSC1 oscillator output Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 1 Overview CHIP PAD/Pin/Ball No. TQFP WCSP *2 36 *2 52 37 38 G5 *2 39 *2 55 40 41 G4 42 43 44 F4 G3 F3 G2 - 45 46 47 *3 48 *3 67 - *2 58 59 *4 61 62 - *2 *4 - I/O Default status VSS - - Power supply (-) OSC3 -NC I I OSC3 oscillator input*6 VSS - - Power supply (-) OSC4 O O VSS - - I/O I/O I(Pull-UP) I(Pull-UP) Name P04/SPICLK P05/SDO HVDD P06/SDI P07/#SPISS -NC LVDD P10/SCLK 49 G1 *3 50 *3 LV 71 72 73 74 51 52 53 54 55 F1 E3 E2 E1 P11/SOUT P12/SIN P13/EXCL1 P14/EXCL2 *4 *2 56 *2 HVDD VSS 77 79 D1 D2 - 57 58 59 *5 60 D3 83 84 86 87 61 62 63 64 C1 C2 B1 B2 *4 - DD - - I/O I/O I(Pull-UP) I(Pull-UP) I/O - I(Pull-UP) - Function (Default/Shared by setting) OSC3 oscillator output Power supply (-) I/O common port (with inturrupt)*1/SPI clock I/O I/O common port (with inturrupt)*1/SPI data output I/O Power supply (+) I/O common port (with inturrupt)*1/SPI data input I/O common port (with inturrupt)*1/SPI slave select input Core power supply (+) I/O common port (with inturrupt)*1/UART Ch0 clock input Core power supply (+) I/O common port (with inturrupt)*1/UART Ch0 data output I/O common port (with inturrupt)*1/UART Ch0 data input I/O common port (with inturrupt)*1/T16 Ch1 external clock input I/O common port (with inturrupt)*1/T16 Ch2 external clock input I/O Power supply (+) I/O I/O I/O I/O I(Pull-UP) I(Pull-UP) I(Pull-UP) I(Pull-UP) - - I/O I/O I(Pull-UP) I(Pull-UP) AVDD - - Analog power supply (+) P17/AIN3 P20/AIN2 P21/AIN1 P22/AIN0 I I I I I I I I I/O common port (with inturrupt)*1/ A/D converter Ch3 input I/O common port*1/ A/D converter Ch2 input I/O common port*1/ A/D converter Ch1 input I/O common port*1/ A/D converter Ch0 input P15/EXCL3 P16/SCLK1 -NC Power supply (-) I/O common port (with inturrupt)*1/T16E Ch0 external clock input I/O common port (with inturrupt)*1/UART Ch1 clock input - *1: Default function settings *2: VSS PAD numbers : 2, 3, 20, 21, 27, 28, 43, 44, 47, 48, 51, 54, 56, 76 78 VSS ball numbers : C6, D4, F5 *3: LVDD PAD numbers : 8, 9, 31, 34, 35, 64, 69, 70 LVDD ball numbers : D5, F2 *4: HVDD PAD numbers : 10, 11, 17, 29, 60, 75 HVDD ball numbers : C4, E4 *5: AVDD PAD numbers : 80, 82, 85 *6: When an external clock is input to the OSC3 or OSC1 pin, the clock signal level must be LVDD. Note: Do not put bonding on NC pins. (The pins for which "NC" is specified for TQFP, and no number is described for CHIP/WCSP.) S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 1-9 1 Overview This page intentionally left blank. 1-10 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 2 CPU 2 CPU The S1C17003 uses an S1C17 core as the core processor. The S1C17 core is an original Seiko Epson 16-bit RISC processor. It features low power consumption, high-speed operation, wide address space, main instruction single-clock execution, and gate-saving design. It is ideal for use in controllers or sequencers, in which 8-bit CPUs are widely used. For detailed information on the S1C17 core, refer to the S1C17 Family S1C17 Core Manual. 2.1 S1C17 Core Features Processor type * Seiko Epson original 16-bit RISC processor * 0.35 m to 0.15 m low-power CMOS process technology Instruction set * Code length Fixed 16-bit length * Number of instructions 111 basic instructions (184 in total) * Execution cycle Main instructions executed in one cycle * Immediate expansion instructions Expansion of immediate to 24 bits * Compact, high-speed instruction set optimized for development with C Register set * 24-bit general purpose register x 8 * 24-bit special register x 2 * 8-bit special register x 1 Memory space, buses * Up to 16 Mbytes of memory space (24-bit address) * Harvard architecture with separate instruction bus (16-bit) and data bus (32-bit) Interrupt * Supports reset, NMI, and 32 different types of external interrupt * Irregular address interrupt * Debug interrupt * Reading vector from vector table and direct branching to interrupt processing routines * Permits software interrupts using vector numbers (all vector numbers can be specified) Power saving * HALT (halt instruction) * SLEEP (slp instruction) Coprocessor interface * 16 bits x 16 bits + 32 bits product-sum arithmetic unit * 16 bits/16 bits division arithmetic unit S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 2-1 2 CPU 2.2 CPU Registers The S1C17 core contains eight general purpose registers and three special registers. Special registers General purpose registers Bit 23 Bit 0 PC SP PSR 7 6 IL[2:0] 5 4 IE 3 C 2 V 1 Z 0 N Bit 23 7 6 5 4 3 2 1 0 Bit 0 R7 R6 R5 R4 R3 R2 R1 R0 Figure 2.2.1: Registers 2-2 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 2 CPU 2.3 Instruction Set The S1C17 core instruction codes are all 16-bit and fixed-length. Major instructions are executed in a single cycle using pipeline processing. For more information on the various instructions, refer to the S1C17 Family S1C17 Core Manual. Table 2.3.1: S1C17 core instruction list Type Data transfer ld.b ld.ub ld ld.a Mnemonic %rd,%rs %rd,[%rb] %rd,[%rb]+ %rd,[%rb]%rd,-[%rb] %rd,[%sp+imm7] %rd,[imm7] [%rb],%rs [%rb]+,%rs [%rb]-,%rs -[%rb],%rs [%sp+imm7],%rs [imm7],%rs %rd,%rs %rd,[%rb] %rd,[%rb]+ %rd,[%rb]%rd,-[%rb] %rd,[%sp+imm7] %rd,[imm7] %rd,%rs %rd,sign7 %rd,[%rb] %rd,[%rb]+ %rd,[%rb]%rd,-[%rb] %rd,[%sp+imm7] %rd,[imm7] [%rb],%rs [%rb]+,%rs [%rb]-,%rs -[%rb],%rs [%sp+imm7],%rs [imm7],%rs %rd,%rs %rd,imm7 %rd,[%rb] %rd,[%rb]+ %rd,[%rb]%rd,-[%rb] %rd,[%sp+imm7] %rd,[imm7] [%rb],%rs [%rb]+,%rs [%rb]-,%rs -[%rb],%rs [%sp+imm7],%rs [imm7],%rs %rd,%sp %rd,%pc %rd,[%sp] %rd,[%sp]+ %rd,[%sp]%rd,-[%sp] S1C17003 TECHNICAL MANUAL Function General purpose register (byte) General purpose register (sign extension) Memory (byte) General purpose register (sign extension) Memory address post-increment/post-decrement A pre-decrement function can be used Stack (byte) General purpose register (sign extension) Memory (byte) General purpose register (sign extension) General purpose register (byte) Memory Memory address post-increment/post-decrement A pre-decrement function can be used General purpose register (byte) Stack General purpose register (byte) Memory General purpose register (byte) General purpose register (zero extension) Memory (byte) General purpose register (zero extension) Memory address post-increment/post-decrement A pre-decrement function can be used Stack (byte) General purpose register (zero extension) Memory (byte) General purpose register (zero extension) General purpose register (16 bits) General purpose register Immediate General purpose register (sign extension) Memory (16 bits) General purpose register Memory address post-increment/post-decrement A pre-decrement function can be used Stack (16 bits) General purpose register Memory (16 bits) General purpose register General purpose register (16 bits) Memory Memory address post-increment/post-decrement A pre-decrement function can be used General purpose register (16 bits) Stack General purpose register (16 bits) Memory General purpose register (24 bits) General purpose register Immediate General purpose register (zero extension) Memory (32 bits) General purpose register (*1) Memory address post-increment/post-decrement A pre-decrement function can be used Stack (32 bits) General purpose register (*1) Memory (32 bits) General purpose register (*1) General purpose register (32 bits, zero extension) Memory (*1) Memory address post-increment/post-decrement A pre-decrement function can be used General purpose register (32 bits, zero extension) Stack (*1) General purpose register (32 bits, zero extension) Memory (*1) SP General purpose register PC General purpose register Stack (32 bits) General purpose register (*1) Stack pointer post-increment/post-decrement A pre-decrement function can be used Seiko Epson Corporation 2-3 2 CPU Type Data transfer ld.a Mnemonic [%sp],%rs [%sp]+,%rs [%sp]-,%rs -[%sp],%rs %sp,%rs %sp,imm7 %rd,%rs Integer arithmetic add add/c add/nc add %rd,imm7 add.a %rd,%rs add.a/c add.a/nc add.a %sp,%rs %rd,imm7 %sp,imm7 adc %rd,%rs adc/c adc/nc adc %rd,imm7 sub %rd,%rs sub/c sub/nc sub %rd,imm7 sub.a %rd,%rs sub.a/c sub.a/nc sub.a %sp,%rs %rd,imm7 %sp,imm7 sbc %rd,%rs sbc/c sbc/nc sbc %rd,imm7 cmp %rd,%rs cmp/c cmp/nc cmp %rd,sign7 cmp.a %rd,%rs cmp.a/c cmp.a/nc cmp.a %rd,imm7 cmc %rd,%rs cmc/c cmc/nc cmc %rd,sign7 %rd,%rs Logic operations and and/c and/nc and %rd,sign7 or %rd,%rs or/c or/nc or %rd,sign7 xor %rd,%rs xor/c xor/nc xor %rd,sign7 not %rd,%rs not/c not/nc not %rd,sign7 2-4 Function General purpose register (32 bits, zero extension) Stack (*1) Stack pointer post-increment/post-decrement A pre-decrement function can be used General purpose register (24 bits) SP Immediate SP Adds 16 bits between general purpose registers Supports conditional execution (/c: Executed when C = 1, /nc: Executed when C = 0) Adds general purpose register and immediate 16 bits Adds 24 bits between general purpose registers Supports conditional execution (/c: Executed when C = 1, /nc: Executed when C = 0) Adds SP and general purpose register 24 bits Adds general purpose register and immediate 24 bits Adds SP and immediate 24 bits Adds 16 bits with carry between general purpose registers Supports conditional execution (/c: Executed when C = 1, /nc: Executed when C = 0) Adds general purpose register and immediate 16 bits with carry Subtracts 16 bits between general purpose registers Supports conditional execution (/c: Executed when C = 1, /nc: Executed when C = 0) Subtracts general purpose register and immediate 16 bits Subtracts 24 bits between general purpose registers Supports conditional execution (/c: Executed when C = 1, /nc: Executed when C = 0) Subtracts SP and general purpose register 24 bits Subtracts general purpose register and immediate 24 bits Subtracts SP and immediate 24 bits Subtracts 16 bits with carry between general purpose registers Supports conditional execution (/c: Executed when C = 1, /nc: Executed when C = 0) Subtracts general purpose register and immediate 16 bits with carry Compares 16 bits between general purpose registers Supports conditional execution (/c: Executed when C = 1, /nc: Executed when C = 0) Compares general purpose registers and immediate 16 bits Compares 24 bits between general purpose registers Supports conditional execution (/c: Executed when C = 1, /nc: Executed when C = 0) Compares general purpose registers and immediate 24 bits Compares 16 bits with carry between general purpose registers Supports conditional execution (/c: Executed when C = 1, /nc: Executed when C = 0) Compares general purpose register and immediate 16 bits with carry AND operation between general purpose registers Supports conditional execution (/c: Executed when C = 1, /nc: Executed when C = 0) AND operation for general purpose register and immediate OR operation between general purpose registers Supports conditional execution (/c: Executed when C = 1, /nc: Executed when C = 0) OR operation for general purpose register and immediate EXCLUSIVE OR between general purpose registers Supports conditional execution (/c: Executed when C = 1, /nc: Executed when C = 0) EXCLUSIVE OR for general purpose register and immediate NOT operation between general purpose registers (1 complement) Supports conditional execution (/c: Executed when C = 1, /nc: Executed when C = 0) NOT operation for general purpose register and immediate (1 complement) Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 2 CPU Type Shift & swap sr sa sl swap Immediate extension ext cv.ab Conversion cv.as cv.al cv.la cv.ls jpr Branch jpr.d jpa jpa.d jrgt jrgt.d jrge jrge.d jrlt jrlt.d jrle jrle.d jrugt jrugt.d jruge jruge.d jrult jrult.d jrule jrule.d jreq jreq.d jrne jrne.d call call.d calla calla.d ret ret.d int intl reti reti.d brk retd nop System control halt slp ei di ld.cw Coprocessor control ld.ca ld.cf Mnemonic %rd,%rs %rd,imm7 %rd,%rs %rd,imm7 %rd,%rs %rd,imm7 %rd,%rs imm13 %rd,%rs %rd,%rs %rd,%rs %rd,%rs %rd,%rs sign10 %rb imm7 %rb sign7 sign7 sign7 sign7 sign7 sign7 sign7 sign7 sign7 sign7 sign10 %rb imm7 %rb imm5 imm5,imm3 %rd,%rs %rd,imm7 %rd,%rs %rd,imm7 %rd,%rs %rd,imm7 Function Right logic shift (shift bit number specified by register) Right logic shift (shift bit number specified by immediate) Right operation shift (shift bit number specified by register) Right operation shift (shift bit number specified by immediate) Left logic shift (shift bit number specified by register) Left logic shift (shift bit number specified by immediate) Byte swap at 16-bit boundary Extend operand for next instruction Convert 8-bit coded data to 24 bits Convert 16-bit coded data to 24 bits Convert 32-bit data to 24 bits Convert 24-bit data to 32 bits Convert 16-bit data to 32 bits PC-relative jump Allows delayed branching Absolute jump Allows delayed branching Conditional PC-relative jump Branch conditions: !Z & !(N ^ V) Allows delayed branching Conditional PC-relative jump Branch conditions: !(N ^ V) Allows delayed branching Conditional PC-relative jump Branch conditions: N ^ V Allows delayed branching Conditional PC-relative jump Branch conditions: Z | N ^ V Allows delayed branching Conditional PC-relative jump Branch conditions: !Z & !C Allows delayed branching Conditional PC-relative jump Branch conditions: !C Allows delayed branching Conditional PC-relative jump Branch conditions: C Allows delayed branching Conditional PC-relative jump Branch conditions: Z | C Allows delayed branching Conditional PC-relative jump Branch conditions: Z Allows delayed branching Conditional PC-relative jump Branch conditions: !Z Allows delayed branching PC-relative subroutine call Allows delayed branching Absolute subroutine call Allows delayed branching Return from subroutine Allows delayed branching Software interrupt Software interrupt with interrupt level specification Return from interrupt Allows delayed branching Debug interrupt Return from debug processing No operation HALT SLEEP Permits interrupt Prevents interrupt Transfer data to coprocessor Transfer data to coprocessor and obtain results and flag status Transfer data to coprocessor and obtain flag status *1 Instruction ld.a accesses 32-bit memory. When data is transferred from register to memory, 32 bits of data with the first 8 bits set to 0 are written to memory. When data is read from memory, the first 8 bits are ignored. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 2-5 2 CPU The codes used in this table are explained below. Table 2.3.2: Code meanings Code %rs %rd [%rb] [%rb]+ [%rb]-[%rb] %sp [%sp],[%sp+imm7] [%sp]+ [%sp]-[%sp] imm3,imm5,imm7,imm13 sign7,sign10 2-6 Description General purpose source register General purpose destination register Memory specified indirectly by general purpose register Memory specified indirectly by general purpose register (with address post-increment) Memory specified indirectly by general purpose register (with address post-decrement) Memory specified indirectly by general purpose register (with address pre-decrement) Stack pointer Stack Stack (with address post-increment) Stack (with address post-decrement) Stack (with address pre-decrement) Immediate without code (number indicates bit length) Immediate with code (number indicates bit length) Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 2 CPU 2.4 Vector Table The vector table contains the vectors (processing routine start addresses) for interrupt processing routines. When an interrupt occurs, the S1C17 core reads the vector corresponding to the interrupt and executes that processing routine. The boot address for starting program execution must be written at the top of the vector table after resetting. The S1C17003 vector table starts from address 0x8000. The vector table base address can be read from the TTBR (vector table base register) at address 0xffff80. For more information on Vector Table, refer to "6. Interrupt Controller" The base (top) address for the vector table for writing interrupt vectors can be set using the MISC_TTBRL and MISC_TTBRH registers (0x5328 and 0x532a). The MISC_TTBRL and MISC_TTBRH registers are set to the 0x8000 address after initial resetting. This means only the reset vector must be written to the above address, even when changing the vector table location. Bits 7 to 0 in the MISC_TTBRL register are fixed to 0; the initial address of the vector table normally starts from the 256 byte boundary. 0x5328-0x532a: Vector Table Address Low/High Registers (MISC_TTBRL, MISC_TTBRH) Setting Init. R/W Vector Table Address Low Register (MISC_TTBRL) Register name Address 0x5328 (16 bits) D15-8 TTBR[15:8] Vector table base address A[15:8] D7-0 TTBR[7:0] Vector table base address A[7:0] (fixed at 0) Bit Name Function 0x0-0xff 0x0 0x80 R/W 0x0 R Remarks Vector Table Address High Register (MISC_TTBRH) 0x532a (16 bits) D15-8 - reserved D7-0 TTBR[23:16] Vector table base address A[23:16] - 0x0-0xff - - 0 when being read. 0x0 R/W Note: The MISC_TTBRL and MISC_TTBRH registers are write-protected. To write to these registers, write-protection must be overridden by writing 0x96 to the MISC Protect Register (0x5324). Normally, the MISC Protect Register (0x5324) should be set to a value other than 0x96, except when writing to the MISC_TTBRL and MISC_TTBRH registers, since unnecessary writes may result in system malfunctions. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 2-7 2 CPU 2.5 PSR Readout The S1C17003 incorporates a PSR register (0x532c) for reading out the contents of the PSR (Processor Status Register) in the S1C17 core. Reading out the contents of this register makes it possible to check the contents of the PSR using application software. Note that data cannot be written to the PSR. 0x532c: PSR Register (MISC_PSR) Register name Address PSR Register (MISC_PSR) 0x532c (16 bits) Bit D15-8 D7-5 D4 D3 D2 D1 D0 Name - PSRIL[2:0] PSRIE PSRC PSRV PSRZ PSRN Function reserved PSR interrupt level (IL) bits PSR interrupt enable (IE) bit PSR carry (C) flag PSR overflow (V) flag PSR zero (Z) flag PSR negative (N) flag Setting 1 1 1 1 1 D[7:5] PSRIL[2:0]: PSR Interrupt Level (IL) Bits Read out the value (interrupt level) of the IL bit of the PSR. (default: 0x0) D4 PSRIE: PSR Interrup Enable (IE) Bit Read out the value (interrupt enable) of the PSR IE bit. 1(R): 1 (Interrupt permitted) 0(R): 0 (Interrupt prohibited) (default) D3 PSRC: PSR Carry (C) Flag Read out the value of the PSR C (carry) flag. 1(R): 1 0(R): 0 (default) D2 PSRV: PSR Overflow (V) Flag Read out the value of the PSR V (overflow) flag. 1(R): 1 0(R): 0 (default) D1 PSRZ: PSR Zero (Z) Flag Read out the value of the PSR Z (zero) flag. 1(R): 1 0(R): 0 (default) D0 PSRN: PSR Negative (N) Flag Read out the value of the PSR N (negative) flag. 1(R): 1 0(R): 0 (default) 2-8 Init. R/W - 0x0 to 0x7 1 (enable) 0 0 (disable) 1 (set) 0 0 (cleared) 1 (set) 0 0 (cleared) 1 (set) 0 0 (cleared) 1 (set) 0 0 (cleared) Seiko Epson Corporation - 0x0 0 0 0 0 0 - R R R R R R Remarks 0 when being read. S1C17003 TECHNICAL MANUAL 2 CPU 2.6 Processor Information The S1C17003 contains a processor ID register (0xffff84) to allow specification of the CPU core type by the application software. 0xffff84: Processor ID Register (IDIR) Register name Address Processor ID Register (IDIR) 0xffff84 (8 bits) Bit Name D7-0 IDIR[7:0] Function Processor ID 0x10: S1C17 Core Setting 0x10 Init. R/W 0x10 Remarks R This is the read-only register containing the ID code indicating the processor type. The S1C17 core ID code is 0x10. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 2-9 3 Memory Map and Bus Control 3 Memory Map and Bus Control Figure 3.1 shows the S1C17003 memory map. 0xff ffff 0xff fc00 0xff fbff Core I/O reserved area (1 Kbyte, 1 cycle) reserved 0x01 8000 0x01 7fff Mask ROM area (64 Kbytes) Vector table 0x00 0x00 0x00 0x00 8000 7fff 6000 5fff 0x00 0x00 0x00 0x00 5000 4fff 4400 43ff 0x00 0x00 0x00 0x00 0x00 4000 3fff 1000 0fff 0fc0 reserved Internal peripheral circuit area 2 (4 Kbytes, 1 cycle) reserved Internal peripheral circuit area 1 (1 Kbyte, 1 cycle) reserved Debug RAM area (64 bytes) Internal RAM area (4 Kbytes, 1 cycle) (Device size: 32 bits) 0x00 0000 Peripheral functions 0x5400~0x5fff reserved 0x53c0~0x53ff reserved 0x53a0~0x53bf reserved 0x5380~0x539f A/D Converter 0x5360~0x537f reserved 0x5340~0x535f Remote controller 0x5320~0x533f MISC register 0x5300~0x531f PWM & capture timer Ch.0 0x52c0~0x52ff reserved 0x52a0~0x52bf Port MUX 0x5280~0x529f reserved 0x5200~0x527f P port 0x5140~0x51ff reserved 0x5120~0x513f reserved 0x5100~0x511f reserved 0x50e0~0x50ff reserved 0x50c0~0x50df 8-bit OSC1 timer 0x50a0~0x50bf reserved 0x5080~0x509f Clock generator 0x5060~0x507f Oscillator circuit 0x5040~0x505f Watchdog timer 0x5020~0x503f Stopwatch timer 0x5000~0x501f Clock timer 0x4380~0x43ff 0x4360~0x437f 0x4340~0x435f 0x4320~0x433f 0x42c0~0x431f 0x4280~0x42ff 0x4260~0x427f 0x4240~0x425f 0x4220~0x423f 0x4200~0x421f 0x4120~0x41ff 0x4100~0x411f 0x4040~0x40ff 0x4020~0x403f 0x4000~0x401f reserved I2C (Slave) I2C (Master) SPI Interrupt controller 8-bit timer Ch.1 16-bit timer Ch.2 16-bit timer Ch.1 16-bit timer Ch.0 8-bit timer Ch.0 UART Ch.1 UART Ch.0 reserved Prescaler reserved (Device size) - - - (16 bits) - (16 bits) (16 bits) (16 bits) - (8 bits) - (8 bits) - - - (8 bits) (8 bits) - (8 bits) (8 bits) (8 bits) (8 bits) (8 bits) - (16 bits) (16 bits) (16 bits) (16 bits) (16 bits) (16 bits) (16 bits) (16 bits) (16 bits) (8 bits) (8 bits) - (8 bits) - Figure 3.1: S1C17003 memory map S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 3-1 3 Memory Map and Bus Control 3.1 Bus Cycle The CPU operates using CCLK as a datum. For more information on CCLK, refer to "8.2 CPU Core Clock (CCLK) Control." The time from one CCLK rise-up to the next forms 1 CCLK, defined as one bus cycle. As shown in Figure 3.1, the number of cycles required for a single bus access depends on the peripheral circuits and memory. The number of bus accesses also varies and depends on the CPU instruction (access size) and device size. Table 3.1.1: Bus access numbers Device size 8 bits CPU access size 8 bits 16 bits 32 bits * 8 bits 16 bits 32 bits * 8 bits 16 bits 32 bits * 16 bits 32 bits Bus access number 1 2 4 1 1 2 1 1 1 * First 8 bits of data for 32-bit data access The first 8 bits of 32-bit data are written to memory as 0. The first 8 bits are ignored when read from memory. Interrupt processing stack operation involves reading and writing 32 bits with the PSR value in the first 8 bits and the return address in the last 24 bits. 3.1.1 Access Size Restrictions All modules can be accessed using 8-bit, 16-bit, and 32-bit instructions. Where possible, we recommend matching access to device size. Reading from non-essential registers may alter the state of peripheral circuits and cause problems. 3.1.2 Instruction Execution Cycle Restrictions In the event of any of the conditions listed below, instruction fetch and data access will not be performed simultaneously, and the instruction fetch cycle will be extended by the amount of access cycles for the areas in which data exists. * If an instruction is executed for an internal RAM area accessing internal RAM area data 3-2 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 3 Memory Map and Bus Control 3.2 Mask ROM Area 3.2.1 Mask ROM The 64 Kbyte area from 0x8000 to 0x17fff contains ROM enabling data or application programs to be written. Address 0x8000 is defined as the vector table base address. The vector table (see "2.4 Vector Table") must be placed at the start of this area. The vector table base address can be modified with the MISC_TTBRL/MISC_TTBRH registers (0x5328 and 0x532a). The ROM is read in 1 to 5 cycles. 3.2.2 ROM read access cycle settings To maintain compatibility with the S1C17602, the read access cycle in ROM area can be set with the FLCYC[2:0] (D[2:0]/MISC_FL register). Set the FLCYC[2:0] to 0x4 in usual circumstances. 0x5320: ROM Control Register (MISC_FL) Register name Address ROM Control Register (MISC_FL) D[2:0] 0x5320 (16 bits) Bit Name Function D15-3 - reserved D2-0 FLCYC[2:0] FLASHC read access cycle Setting Init. R/W - FLCYC[2:0] 0x7-0x5 0x4 0x3 0x2 0x1 0x0 Read cycle reserved 1 cycles 5 cycles 4 cycles 3 cycles 2 cycles Remarks - - 0 when being read. 0x3 R/W FLCYC[2:0]: FLASHC Read Access Cycle Setup Bits Sets the number of read access cycles for the ROM. Table 3.2.2.1: ROM read access cycle settings FLCYC[2:0] 0x7 to 0x5 0x4 0x3 0x2 0x1 0x0 Read access cycles Reserved 1 cycle 5 cycles 4 cycles 3 cycles 2 cycles CCLK frequency - 20 MHz max. 20 MHz max. 20 MHz max. 20 MHz max. 20 MHz max. (Default: 0x3) Note: * Do not set the read access cycles to a value exceeding the CCLK maximum permissible frequency. This will cause malfunctions. * Set FLCYC[2:0]=0x4 in order to maximize the performance. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 3-3 3 Memory Map and Bus Control 3.3 Internal RAM Area 3.3.1 Internal RAM RAM exists in a 4-Kbyte area from address 0x0 to 0xfff. This RAM can be accessed in one cycle for reading or writing. In addition to storing variables, it can also be used to copy instruction codes and execute them rapidly in RAM. Note: The last 64 bytes of the internal RAM (0xfc0 to 0xfff) are reserved for on-chip debugging. This area should not be accessed by application programs when using debug functions (for example, during application development). It can be used for applications in mass-produced products that do not require debugging. The S1C17003 enables the RAM size used to apply restrictions to 4 KB or 2 KB. For example, when using the S1C17003 to develop products with internal ROM, you can set the RAM size to match that of the target product, preventing creating programs that seek to access areas outside the RAM areas of the target product. The RAM size is selected using IRAMSZ[1:0] (D[1:0]/MISC_IRAMSZ register). 0x5326: IRAM Size Select Register (MISC_IRAMSZ) Register name Address IRAM Size 0x5326 Select Register (16 bits) (MISC_IRAMSZ) D[1:0] Bit Name Function D15-2 - reserved D1-0 IRAMSZ[1:0] IRAM size select Setting Init. R/W - IRAMSZ[1:0] 0x3 0x2 0x1 0x0 Read cycle reserved reserved reserved reserved Remarks - - 0 when being read. 0x2 R/W IRAMSZ[1:0]: IRAM Size Select Bits Select the internal RAM size used. Table 3.3.1.1: Internal RAM size selection IRAMSZ[1:0] 0x3 0x2 0x1 0x0 Internal RAM size reserved reserved reserved reserved (Default: 0x2) Notes: * The IRAM Size Select Register is write-protected. The write-protection must be overridden by writing 0x96 to the MISC Protect Register (0x5324). Note that MISC Protect Register (0x5324) should normally be set to a value other than 0x96, except when writing to the IRAM Size Select Register. Unnecessary writes may result in system malfunctions. * Please do not change the setting of IRAMSZ[2:0]/MISC_IRAMSZ Register from a default value. 3-4 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 3 Memory Map and Bus Control 3.4 Internal Peripheral Circuit Area The 1 Kbyte area starting at address 0x4000 and the 4 Kbyte area from 0x5000 are assigned for use as internal peripheral circuit I/O and control registers. 3.4.1 Internal Peripheral Circuit Area 1 (0x4000 onward) The internal peripheral circuit area 1 starting at address 0x4000 is assigned for use as the following internal peripheral function I/O memory and can be accessed in a single cycle. * * * * * * * * Prescaler (PSC, 8-bit device) UART (UART, 8-bit device) 8-bit timer (T8F, 16-bit device) 16-bit timer (T16, 16-bit device) Interrupt controller (ITC, 16-bit device) SPI (SPI, 16-bit device) I2C master (I2C, 16-bit device) I2C slave (I2C, 16-bit device) 3.4.2 Internal Peripheral Circuit Area 2 (0x5000 onward) The internal peripheral circuit area 2 starting at address 0x5000 is assigned for use as the following internal peripheral function I/O memory, and can be accessed in one cycle. * * * * * * * * * * * Clock timer (CT, 8-bit device) Stopwatch timer (SWT, 8-bit device) Watchdog timer (WDT, 8-bit device) Oscillator circuit (OSC, 8-bit device) Clock generator (CLG, 8-bit device) 8-bit OSC1 PWM timer (T8OSC1, 8-bit device) Input/output port & port MUX (P, 8-bit device) PWM timer (T16E, 16-bit device) MISC register (MISC, 16-bit device) Remote controller (REMC, 16-bit device) A/D converter (ADC10, 16-bit device) S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 3-5 3 Memory Map and Bus Control 3.5 Core I/O Reserved Area The 1 Kbyte area from 0xfffc00 to 0xffffff is used as the CPU core I/O area, and the following I/O registers are assigned. Table 3.5.1: I/O map (Core I/O reserved area) Peripheral circuit S1C17 core I/O Address 0xffff84 0xffff90 0xffffa0 0xffffb8 0xffffbc 0xffffd0 Register name IDIR DBRAM DCR IBAR2 IBAR3 IBAR4 Processor ID Register Debug RAM Base Register Debug Control Register Instruction Break Address Register 2 Instruction Break Address Register 3 Instruction Break Address Register 4 Function Processor ID display Debugging RAM base address display Debug control Instruction break address #2 setting Instruction break address #3 setting Instruction break address #4 setting See "2.6 Processor Information" for more information on IDIR and "24. On-chip Debugger (DBG)" for more information on other registers. This area incorporates S1C17 core registers, in addition to those described above. For more information on these registers, refer to the S1C17 Core Manual. 3-6 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 4 Power Supply Voltage 4 Power Supply Voltage This section explains the operating voltage of the S1C17003. 4.1 Power Supply Pins The S1C17003 has the power supply pins shown in Table 4.1.1. Table 4.1.1 Power Supply Pins Pin name HVDD LVDD VSS AVDD Pin No. TQFP 7, 13, 20, 44, 55 6, 22, 25, 48, 50 2, 16, 19, 32, 34, 36, 39, 41, 56 60 1.8 V Typ. (1.65 to 1.95 V) WCSP C4, E4 D5, F2 D4, C6, F5 D3 LVDD GND VSS 1.65 to 3.60 V HVDD 2.70 to 3.60 V I/O Type PU/PD Description - - - 3.3 V 1.8 V GND - - - I/O power supply (+) (1.8 V/2.5 V/3.3 V) Core power supply (+) (1.8 V) GND - 3.3 V - Analog power supply (3.0 V/3.3 V) CPU core Oscillator circuits Internal logic circuits I/O interface circuit AVDD Analog circuits (A/D converter) Figure 4.1.1 Power Supply System S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 4-1 4 Power Supply Voltage 4.2 Operating Voltage (LVDD, VSS) The core CPU and internal logic circuits of the S1C17003 operate with a voltage supplied between the LVDD and VSS pins. The following operating voltage can be used: LVDD = 1.65 V to 1.95 V (1.80 V 0.15 V, VSS = GND) Note: The S1C17003 TQFP package has five LVDD pins and nine VSS pins; the WCSP package has two LVDD pins and three VSS pins. Be sure to supply the operating voltage to all the pins. Do not open any of them. 4.3 Power Supply for I/O Interface (HVDD) The HVDD voltage is used for interfacing with external I/O signals. For the output interface of the S1C17003, the HVDD voltage is used as high level and the VSS voltage as low level. The VSS pin is used for the ground common with LVDD. The following voltage is enabled for HVDD: HVDD = 1.65 V to 3.60 V (VSS = GND) Notes: * The S1C17003 TQFP package has five HVDD pins; the WCSP package has two HVDD pins. Be sure to supply the operating voltage to all the pins. Do not open any of them. * When an external clock is input to the OSC3 or OSC1 pin, the clock signal level must be LVDD. 4.4 Power Supply for Analog Circuits (AVDD) The analog power supply pin (AVDD) is provided separately from the LVDD and HVDD pins in order that the digital circuits do not affect the analog circuit (A/D converter). The AVDD pin is used to supply an analog power voltage and the VSS pin is used as the analog ground. The following voltage is enabled for AVDD: AVDD = 2.70 V to 3.60 V or 1.65 V to 3.60 V (Note) (VSS = GND) Notes: * Be sure to supply a voltage within the range from 1.65 to 3.60 V to the AVDD pin even if the analog circuit is not used. It is not necessary to supply a voltage same as the HVDD level. * The AVDD voltage range can be changed to 1.65 to 3.60 V only when the ADC is not used and the P0x pins are used as digital signal input pins, not analog input pins. However, the high and low level input voltages of the digital signals must be AVDD and GND, respectively. Noise on the analog power lines decrease the A/D converting precision, so use a stabilized power supply and make the board pattern with consideration given to that. 4-2 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 4 Power Supply Voltage 4.5 Precautions on Power Supply Power-on sequence In order to operate the device normally, supply power in accordance with the following timing. HVDD, AVDD LVDD min. LVDD OSC3 tSTA3 tRST tLVDD #RESET Figure 4.5.1 Power-On Sequence (1) tLVDD: Elapsed time until the power supply stabilizes after power-on Supply power in the following sequence: Power-on: LVDD HVDD (I/O), AVDD (A/D) Apply the input signal or LVDD, HVDD (I/O), AVDD (A/D) Apply the input signal (See Notes in "Power-off sequence" below.) (2) tSTA3: Time at which OSC3 oscillation starts (3) tRST: Minimum reset pulse width Time at which the clock supplied to the chip stabilizes plus at least six clocks; Keep the #RESET signal low. Note: When the HVDD power is turned on from off status, stable internal circuit statuses cannot be guaranteed due to noise in the power line. Therefore, the circuit statuses must be initialized (reset) after the power is turned on. Power-off sequence Shut off the power supply in the following sequence: Power-off: Turn off the input signal HVDD (I/O), AVDD (A/D) LVDD or Turn off the input signal HVDD (I/O), AVDD (A/D), LVDD (See Notes below.) Notes: * Applying only LVDD with other power voltage turned off makes a diode circuit on the path from LVDD to HVDD (AVDD) that results current flowing to the HVDD (AVDD) power supply. In order to avoid this statue, the power supplies should be turned off simultaneously. * Be sure to avoid applying HVDD or AVDD for a duration of one second or more when the LVDD power is off, as a breakdown may occur in the device or the characteristics may be degraded due to flow-through current of the HVDD or AVDD. Latch-up The CMOS device may be in the latch-up condition. This is the phenomenon caused by conduction of the parasitic PNPN junction (thyristor) contained in the CMOS IC, resulting in a large current between HVDD and VSS and leading to breakage. Latch-up occurs when the voltage applied to the input / output exceeds the rated value and a large current flows into the internal element, or when the voltage at the HVDD pin exceeds the rated value and the internal element is in the breakdown condition. In the latter case, even if the application of a voltage exceeding the rated value is instantaneous, the current remains high between HVDD and VSS once the device is in the latch-up condition. As this may result in heat generation or smoking, the following points must be taken into consideration: (1) The voltage level at the input/output must not exceed the range specified in the electrical characteristics. In other words, it must be below the power-supply voltage and above VSS. The power-on timing should also be taken into consideration. (2) Abnormal noise must not be applied to the device. (3) The potential at the unused input should be fixed at HVDD, AVDD, or VSS. (4) No outputs should be shorted. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 4-3 5 Initial Reset 5 Initial Reset 5.1 Initial Reset Factors Shown below are the three different initial reset factors for initializing S1C17003 internal circuits. (1) External initial reset via #RESET pin (2) External initial reset via P0 port (pins P00 to P03) key entry (set by software) (3) Internal initial reset via watchdog timer (set by software) Figure 5.1.1 illustrates the initial reset circuit configuration. VDD Oscillation stabilization standby circuit #RESET P00 P01 P02 P03 S Q Internal reset R Chattering filter circuit Key reset control circuit Digital noise filter P0KRST Watchdog timer WDTMD Figure 5.1.1: Initial reset circuit configuration The CPU and peripheral circuits are initialized by initial reset factors. The CPU begins reset processing once the factors are canceled. This causes the reset vector to be read from the start of the vector table, and the program (initialization routine) starting at that address to be executed. 5.1.1 #RESET pin Initial resetting is possible by inputting external Low level to the #RESET pin. To initialize the S1C17003 reliably, the #RESET pin must be maintained at Low level for at least the specified duration after the power supply voltage rises. (Refer to "26.4 Input/Output Terminal Characteristics") Initial resetting is canceled if the #RESET input changes from Low to High, and the CPU begins reset interrupt processing. The #RESET pin incorporates a pull-up resistance. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 5-1 5 Initial Reset 5.1.2 P0 Port Key-Entry Reset Initial resetting is possible by inputting external Low level simultaneously to the ports (P00 to P03) selected by software. The ports can be selected by P0KRST[1:0] (D[1:0]/P0_KRST register). * P0KRST[1:0]: P0 Port Key-Entry Reset Configuration Bits in the P0 Port Key-Entry Reset Configuration (P0_KRST) Register (D[1:0]/0x5209) Table 5.1.2.1: P0 port key-entry reset settings P0KRST[1:0] 0x3 0x2 0x1 0x0 Port used P00, P01, P02, P03 P00, P01, P02 P00, P01 Not used For example, initial reset is applied when input to the four ports P00 to P03 is Low level simultaneously if P0KRST[1:0] is set to 0x3. Note: * Make sure the specified ports are not simultaneously switched to Low during normal operations when using the P0 port key-entry reset function. * The P0 port key-entry reset function is enabled by software and cannot be used to perform a reset at power-on. * The P0 port key-entry reset function cannot be used in SLEEP state. 5.1.3 Reset by Watchdog Timer The S1C17003 incorporates a watchdog timer to detect runaway CPU. If the watchdog timer is not reset by software every 4 seconds (with this failure indicating a runaway CPU), the timer overflows, generating an NMI or reset. A reset is generated by writing "1" to WDTMD (D1/WDT_ST register). (NMI is generated if WDTMD is 0.) *WDTMD: NMI/Reset Mode Select Bit in the Watchdog Timer Status (WDT_ST) Register (D1/0x5041) For detailed information on the watchdog timer, refer to "17 Watchdog Timer (WDT)." Note: * When using the reset function with the watchdog timer, to prevent accidental resetting, take care to program so that the watchdog timer is reset every four seconds. * The watchdog timer reset function is enabled by software and cannot be used to perform a reset at power-on. 5-2 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 5 Initial Reset 5.2 Initial Reset Sequence CPU startup waits for the oscillation stabilization standby time to expire after resetting is cancelled via the #RESET pin at power-on. Figure 5.2.1 illustrates the sequence of operations after canceling the initial reset. The CPU starts up in sync with the fosc3 (internal oscillation circuit) clock after the reset is canceled. *fOSC3: OSC3 clock frequency Note: The oscillation stabilization standby time does not include the oscillation start time. The time may be longer than that shown between power-on or SLEEP cancellation and instruction execution. OSC3 clock #RESET Reset cancellation Reset cancellation Internal reset cancellation Internal data request Boot vector Internal data address Oscillation stabilization standby time Boot operation start Figure 5.2.1: Sequence of operations after initial reset cancellation S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 5-3 5 Initial Reset 5.3 Initial Settings at Initial Resetting The CPU internal register is initialized by initial resetting, as shown below. R0 to R7: PSR: SP: PC: 0x0 0x0 (interrupt level = 0, interrupt prohibited) 0x0 Reset vector at start of vector table is loaded by reset processing. The internal RAM should be initialized via software, since it is not initialized by initial resetting. The internal peripheral circuits are initialized in accordance with their particular specifications. They should be reset via software, if necessary. For detailed information on initial values after initial resetting, refer to the I/O register list in the Appendix or the respective peripheral circuit descriptions. 5-4 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 6 Interrupt Controller 6 Interrupt Controller 6.1 ITC Configuration The ITC enables the interrupt level (priority) for determining the processing sequence when multiple maskable interrupts occur simultaneously to be set for each interrupt type separately. For details on the maskable interrupt types, refer to the vector table shown in the next page. Each interrupt type has the number of interrupt factors as shown in parentheses in the table mentioned above. Settings to permit or prohibit interrupt for different factors are set by the respective peripheral module registers. For specific information on interrupt factors and their control, refer to the peripheral module explanations. Figure 6.1.1 illustrates the interrupt system configuration. Interrupt controller Peripheral module Vector number Interrupt factor n Interrupt flag Interrupt enable * * * Peripheral module ** * * * * * Interrupt request Interrupt flag Vector number Interrupt factor 1 Interrupt enable * * Interrupt level NMI Interrupt enable Interrupt level Interrupt level Vector number Interrupt factor 1 Interrupt flag * * Interrupt request Interrupt control Interrupt request ** S1C17 core Interrupt flag Interrupt factor n Interrupt enable Watchdog timer Debug signal Reset signal Figure 6.1.1: Interrupt system S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 6-1 6 Interrupt Controller 6.2 Vector Table The vector table contains the vectors (processing routine start addresses) for interrupt processing routines. When an interrupt occurs, the S1C17 core reads the vector corresponding to the interrupt and executes that processing routine. The base (top) address for the vector table can be set using the MISC_TTBRL and MISC_TTBRH registers (0x5328 and 0x532a) (See "2.4 Vector Table"). "TTBR" in Table 6.2.1 indicates the values set for these registers. The MISC_TTBRL and MISC_TTBRH registers are set to the 0x8000 address after initial resetting. Table 6.2.1 shows the S1C17003 vector table. Table 6.2.1: Vector table Vector No./ SoftVector Hardware interrupt name ware interrupt No. address 0 (0x00) TTBR + 0x00 Reset 1 (0x01) - 2 (0x02) 3 (0x03) 4 (0x04) 5 (0x05) 6 (0x06) TTBR + 0x04 (0xfffc00) TTBR + 0x08 TTBR + 0x0c TTBR + 0x10 TTBR + 0x14 TTBR + 0x18 Irregular address interrupt Debug interrupt NMI Compiler (reserved) P0 port interrupt P1 port interrupt Stopwatch timer interrupt 7 (0x07) TTBR + 0x1c Clock timer interrupt 8 (0x08) 9 (0x09) 10 (0x0a) 11 (0x0b) TTBR + 0x20 8-bit OSC1 timer interrupt TTBR + 0x24 reserved TTBR + 0x28 reserved TTBR + 0x2c PWM timer Ch. 0 interrupt 12 (0x0c) 13 (0x0d) 14 (0x0e) 15 (0x0f) 16 (0x10) TTBR + 0x30 TTBR + 0x34 TTBR + 0x38 TTBR + 0x3c TTBR + 0x40 17 (0x11) TTBR + 0x44 UART Ch.1 interrupt/ I2C (slave) 18 (0x12) TTBR + 0x48 SPI interrupt 19 (0x13) TTBR + 0x4c I2C (master) interrupt 20 (0x14) TTBR + 0x50 Remote controller interrupt 21 (0x15) 22 (0x16) TTBR + 0x54 reserved TTBR + 0x58 A/D converter interrupt 23 (0x17) : 31 (0x1f) TTBR + 0x5c : TTBR + 0x7c 8-bit timer Ch.0/Ch.1 interrupt 16-bit timer Ch.0 interrupt 16-bit timer Ch.1 interrupt 16-bit timer Ch.2 interrupt UART Ch.0 interrupt reserved : reserved Hardware interrupt factor * Low input to #RESET pin * Watchdog timer overflow *2 Memory access instruction brk instruction etc. Watchdog timer overflow *2 Use simulation library of C compiler P00 to P07 port input P10 to P17 port input * Timer 100 Hz signal * Timer 10 Hz signal * Timer 1 Hz signal * Timer 32 Hz signal * Timer 8 Hz signal * Timer 2 Hz signal * Timer 1 Hz signal Compare match - - * Compare A * Compare B Timer underflow Timer underflow Timer underflow Timer underflow * Transmit buffer empty * Receive buffer full * Receive error * UART Ch.1 transmit buffer empty * UART Ch.1 receive buffer full * UART Ch.1 receive error * I2C (slave) transmit buffer empty * I2C (slave) receive buffer full * I2C (slave) bus status change * Transmit buffer empty * Receive buffer full * Transmit buffer empty * Receive buffer full * Data length counter underflow * Input rising edge detection * Input falling edge detection - * Conversion finish * Conversion result override - : - Priority Mask 1 impossible 2 3 4 - High *1 Possible Low *1 *1: When same interrupt level is set *2: Watchdog timer interrupt selects reset or NMI using software. Vector numbers 4 to 8, 11 to 20, 22 are assigned maskable interrupts supported by the S1C17003. 6-2 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 6 Interrupt Controller 6.3 Maskable Interrupt Control 6.3.1 Peripheral Module Interrupt Control Bit The peripheral module causing the interrupt includes interrupt enable bits and interrupt flags for each interrupt cause. Setting the interrupt enable bit to 1 (interrupt permitted) sets the interrupt flag to 1, depending on the cause of the interrupt. The flag state is sent to the ITC as an interrupt request signal, generating an interrupt request to the S1C17 core. The corresponding interrupt enable bits should be set to 0 for those causes for which interrupts are not desired. In this case, the interrupt flag will not be set to 1, even if the interrupt cause occurs, and the interrupt request signal will not be activated to the ITC. Interrupt flags set to 1 must be reset within the interrupt processing routine after the interrupt has occurred. The ITC will generate the same interrupt again once the interrupt processing routine has been ended by the reti instruction with the interrupt flag still set to 1, since it detects interrupt requests using the signal level. For specific information on interrupt causes, interrupt flags, and interrupt enable bits, refer to the individual peripheral module descriptions. 6.3.2 ITC Interrupt Request Processing On receiving an interrupt signal from a peripheral module, the ITC sends interrupt request, interrupt level, and vector number signals to the S1C17 core. Vector numbers are determined by the ITC internal hardware for each interrupt cause, as shown in Table 6.2.1. The interrupt level is a value used by the S1C17 core to compare with the IL bit (PSR). This interrupt level is used in the S1C17 core to prohibit subsequently occurring interrupts with the same or lower level. (See section 6.3.3.) The default ITC settings are level 0 for all maskable interrupts. Interrupt requests are not accepted by the S1C17 core if the level is 0. The ITC includes control bits for selecting the interrupt level, and these can be set to between 0 (low) and 7 (high) interrupt levels for each interrupt type. Table 6.3.2.1: Interrupt level setting bits Hardware interrupt P0 port interrupt P1 port interrupt Stopwatch timer interrupt Clock timer interrupt 8-bit OSC1 timer interrupt reserved reserved PWM timer Ch.0 interrupt 8-bit timer Ch.0/Ch.1 interrupt 16-bit timer Ch.0 interrupt 16-bit timer Ch.1 interrupt 16-bit timer Ch.2 interrupt UART Ch.0 interrupt UART Ch.0/I2C (slave) interrupt SPI interrupt I2C (master) interrupt Remote controller interrupt reserved A/D Conveter interrupt reserved S1C17003 TECHNICAL MANUAL Interrupt level setting bit ILV0[2:0] (D[2:0]/ITC_LV0 register) ILV1[2:0] (D[10:8]/ITC_LV0 register) ILV2[2:0] (D[2:0]/ITC_LV1 register) ILV3[2:0] (D[10:8]/ITC_LV1 register) ILV4[2:0] (D[2:0]/ITC_LV2 register) ILV5[2:0] (D[10:8]/ITC_LV2 register) ILV6[2:0] (D[2:0]/ITC_LV3 register) ILV7[2:0] (D[10:8]/ITC_LV3 register) ILV8[2:0] (D[2:0]/ITC_LV4 register) ILV9[2:0] (D[10:8]/ITC_LV4 register) ILV10[2:0] (D[2:0]/ITC_LV5 register) ILV11[2:0] (D[10:8]/ITC_LV5 register) ILV12[2:0] (D[2:0]/ITC_LV6 register) ILV13[2:0] (D[10:8]/ITC_LV6 register) ILV14[2:0] (D[2:0]/ITC_LV7 register) ILV15[2:0] (D[10:8]/ITC_LV7 register) ILV16[2:0] (D[2:0]/ITC_LV8 register) ILV17[2:0] (D[10:8]/ITC_LV8 register) ILV18[2:0] (D[2:0]/ITC_LV9 register) ILV19[2:0] (D[10:8]/ITC_LV9 register) Seiko Epson Corporation Register address 0x4306 0x4306 0x4308 0x4308 0x430a 0x430a 0x430c 0x430c 0x430e 0x430e 0x4310 0x4310 0x4312 0x4312 0x4314 0x4314 0x4316 0x4316 0x4318 0x4318 6-3 6 Interrupt Controller If interrupt requests are input to the ITC simultaneously from multiple peripheral modules, the ITC outputs the interrupt request with the highest priority to the S1C17 core in accordance with the following conditions. 1. Interrupts with the highest interrupt level take precedence. 2. If multiple interrupt requests are input with the same interrupt level, the interrupt with the lowest vector number takes precedence. The other interrupts occurring at the same time are held until all have been accepted by the S1C17 core, in descending order of priority. If an interrupt cause with higher priority occurs while the ITC is outputting an interrupt request signal to the S1C17 core (before being accepted by the S1C17 core), the ITC alters the vector number and interrupt level signal to the setting information on the more recent interrupt. The previously occurring interrupt is held. No interrupt is generated if the interrupt flag is reset via software within the peripheral module outputting an interrupt request held. 6.3.3 S1C17 Core Interrupt Processing Maskable interrupts for the S1C17 core occur when all of the following conditions are met: * Interrupts are permitted by the interrupt control bit inside the peripheral module. * The PSR (S1C17 core internal processor status register) IE (interrupt enable) bit has been set to 1. * The interrupt factor has a higher interrupt level set than that set for the PSR IL (interrupt level). * No other interrupt factors having higher procedence (e.g., NMI) are present. If an interrupt cause permitted inside the peripheral module occurs, the corresponding interrupt flag is set to 1, and this state is maintained until it is reset by the program. This means the interrupt cause is not cleared even if the conditions listed above are not met when the interrupt cause occurs. An interrupt occurs if the above conditions are met. If multiple maskable interrupt causes arise simultaneously, the interrupt cause with the highest interrupt level and lowest vector number becomes the subject of the interrupt request to the S1C17 core. Interrupts with lower levels are held until the above conditions are subsequently met. The S1C17 core samples interrupt requests for each cycle. On accepting an interrupt request, the S1C17 core switches to interrupt processing when execution of the current instruction is complete. Interrupt processing involves the following steps: (1) (2) (3) (4) The PSR and current program counter (PC) value is moved to the stack. The PSR IE bit is reset to 0 (preventing subsequent maskable interrupts). The PSR IL is set to the received interrupt level. (The NMI does not affect interrupt levels.) The vector for the interrupt factor occurring is loaded to the PC to execute the interrupt processing routine. When an interrupt is received, (2) prevents subsequent maskable interrupts. Setting the IE bit to 1 within the interrupt processing routine allows handling of multiple interrupts. In this case, IL is changed by (3), and only interrupts with higher levels than those already being processed will be accepted. Ending interrupt processing routines using a reti instruction returns the PSR to the state before the interrupt. The program resumes processing following the instruction being executed at the time the interrupt occurred via the next branch. 6-4 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 6 Interrupt Controller 6.4 NMI The S1C17003 can generate NMIs (non-maskable interrupts) using the watchdog timer. The vector number for NMIs is 2, and the vector address is set in the vector table initial address + 8 bytes. These interrupts take precedence over other interrupt factors and are accepted unconditionally by the S1C17 core. For detailed information on generating NMIs, refer to "17 Watchdog Timer (WDT)." S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 6-5 6 Interrupt Controller 6.5 Software Interrupts Interrupts can be generated via software with S1C17 core int imm5 or intl imm5 and imm3 instructions. The vector table vector number (0 to 31) is specified by the operand immediate imm5. With the intl instruction, imm3 can be used to specify an interrupt level (0 to 7) for the PSR IL fields. Details of the processor interrupt processing are the same as for when an interrupt generated by hardware occurs. 6-6 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 6 Interrupt Controller 6.6 HALT and SLEEP Mode Cancellation HALT or SLEEP mode is released by the following signals, and the CPU starts up. * Interrupt requests from the ITC to the CPU. * The NMI from the watchdog timer. * Device interrupts * Reset Note: When HALT or SLEEP mode is released by an interrupt request from the ITC to the CPU, the process branches to an interrupt routine immediately after the release if the CPU can permit interrupts. Otherwise, the process executes an instruction following the halt or slp instruction. The ITC interrupt level setting cannot mask the release of HALT or SLEEP mode. For details, refer to "B.1 Clock Control Power Saving" in Appendix B. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 6-7 6 Interrupt Controller 6.7 Control Register Details Table 6.7.1: ITC registers Address 0x4306 0x4308 0x430a 0x430c 0x430e 0x4310 0x4312 0x4314 0x4316 0x4318 Register name ITC_LV0 ITC_LV1 ITC_LV2 ITC_LV3 ITC_LV4 ITC_LV5 ITC_LV6 ITC_LV7 ITC_LV8 ITC_LV9 Function Interrupt Level Setup Register 0 Interrupt Level Setup Register 1 Interrupt Level Setup Register 2 Interrupt Level Setup Register 3 Interrupt Level Setup Register 4 Interrupt Level Setup Register 5 Interrupt Level Setup Register 6 Interrupt Level Setup Register 7 Interrupt Level Setup Register 8 Interrupt Level Setup Register 9 P0 and P1 interrupt level setting SWT and CT interrupt level setting T8OSC1 interrupt level setting T16E Ch.0 interrupt level setting T8F Ch.0/Ch.1 and T16 Ch.0 interrupt level setting T16 Ch.1 and Ch.2 interrupt level setting UART Ch.0 and Ch.1/I2C (slave) interrupt level setting SPI and I2C (master) interrupt level setting REMC interrupt level setting A/D interrupt level setting The ITC registers are described in detail below. These are 16-bit registers. Note: When data is written to the registers, the "Reserved" bits must always be written as 0 and not 1. 6-8 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 6 Interrupt Controller 0x4306: Interrupt Level Setup Register 0 (ITC_LV0) Register name Address Bit Name Interrupt Level 0x4306 D15-11 - Setup Register 0 (16 bits) D10-8 ILV1[2:0] (ITC_LV0) D7-3 - D2-0 ILV0[2:0] Function reserved P1 interrupt level reserved P0 interrupt level Setting - 0 to 7 - 0 to 7 Init. R/W Remarks - - 0 when being read. 0x0 R/W - - 0 when being read. 0x0 R/W D[15:11] Reserved D[10:8] ILV1[2:0]: P1 Port Interrupt Level Bits Set the P1 port interrupt level (0 to 7). (Default: 0) The S1C17 core does not accept interrupts with levels set lower than the PSR IL value. The ITC uses the interrupt level when multiple interrupt factors occur simultaneously. If multiple interrupts occur at the same time permitted by the interrupt enable bit, the ITC sends the interrupt request with the highest level set by the ITC_LVx registers (0x4306 to 0x4316) to the S1C17 core. If multiple interrupt factors with the same interrupt level occur simultaneously, the interrupt with the lowest vector number is processed first. The other interrupts are held until all have been accepted by the S1C17 core in descending order of priority. If an interrupt factor of higher priority occurs while the ITC outputs an interrupt request signal to the S1C17 core (before acceptance by the S1C17 core), the ITC alters the vector number and interrupt level signal to the setting details of the most recent interrupt. The immediately preceding interrupt is held. D[7:3] Reserved D[2:0] ILV0[2:0]: P0 Port Interrupt Level Bits Set the P0 port interrupt level (0 to 7). (Default: 0) Refer to the ILV1[2:0] (D[10:8]) description. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 6-9 6 Interrupt Controller 0x4308: Interrupt Level Setup Register 1 (ITC_LV1) Register name Address Bit Name Interrupt Level 0x4308 D15-11 - Setup Register 1 (16 bits) D10-8 ILV3[2:0] (ITC_LV1) D7-3 - D2-0 ILV2[2:0] Function reserved CT interrupt level reserved SWT interrupt level Setting - 0 to 7 - 0 to 7 Init. R/W Remarks - - 0 when being read. 0x0 R/W - - 0 when being read. 0x0 R/W D[15:11] Reserved D[10:8] ILV3[2:0]: Clock Timer Interrupt Level Bits Set the clock timer interrupt level (0 to 7). (Default: 0) Refer to the ITC_LV0 register (0x4306) ILV1[2:0] (D[10:8]) description. D[7:3] Reserved D[2:0] ILV2[2:0]: Stopwatch Timer Interrupt Level Bits Set the stopwatch timer interrupt level (0 to 7). (Default: 0) Refer to the ITC_LV0 register (0x4306) ILV1[2:0] (D[10:8]) description. 6-10 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 6 Interrupt Controller 0x430a: Interrupt Level Setup Register 2 (ITC_LV2) Register name Address Interrupt Level 0x430a Setup Register 2 (16 bits) (ITC_LV2) Bit Name D15-3 - D2-0 ILV4[2:0] Function reserved T8OSC1 interrupt level Setting - 0 to 7 D[15:3] Reserved D[2:0] ILV4[2:0]: 8-bit OSC1 Timer Interrupt Level Bits Set the 8-bit OSC1 timer interrupt level (0 to 7). (Default: 0) Refer to the ITC_LV0 register (0x4306) ILV1[2:0] (D[10:8]) description. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation Init. R/W Remarks - - 0 when being read. 0x0 R/W 6-11 6 Interrupt Controller 0x430c: Interrupt Level Setup Register 3 (ITC_LV3) Register name Address Bit Name Interrupt Level 0x430c D15-11 - Setup Register 3 (16 bits) D10-8 ILV7[2:0] (ITC_LV3) D7-0 - Function reserved T16E Ch.0 interrupt level reserved Setting - 0 to 7 - Init. R/W Remarks - - 0 when being read. 0x0 R/W - - 0 when being read. D[15:11] Reserved D[10:8] ILV7[2:0]: PWM & Capture Timer Interrupt Level Bits Set the PWM timer interrupt level (0 to 7). (Default: 0) Refer to the ITC_LV0 register (0x4306) ILV1[2:0] (D[10:8]) description. D[7:0] Reserved 6-12 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 6 Interrupt Controller 0x430e: Interrupt Level Setup Register 4 (ITC_LV4) Register name Address Bit Name Interrupt Level 0x430e D15-11 - Setup Register 4 (16 bits) D10-8 ILV9[2:0] (ITC_LV4) D7-3 - D2-0 ILV8[2:0] Function reserved T16 Ch.0 interrupt level reserved T8F Ch.0/Ch.1 interrupt level Setting - 0 to 7 - 0 to 7 Init. R/W Remarks - - 0 when being read. 0x0 R/W - - 0 when being read. 0x0 R/W D[15:11] Reserved D[10:8] ILV9[2:0]: 16-bit Timer Ch.0 Interrupt Level Bits Set the 16-bit timer Ch.0 interrupt level (0 to 7). (Default: 0) Refer to the discussion of ITC_LV0 register (0x4306) ILV1[2:0] (D[10:8]). D[7:3] Reserved D[2:0] ILV8[2:0]: 8-bit Timer Ch.0/Ch.1 Interrupt Level Bits Set the 8-bit timer interrupt level (0 to 7). (Default: 0) Refer to the ITC_LV0 register (0x4306) ILV1[2:0] (D[10:8]) description. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 6-13 6 Interrupt Controller 0x4310: Interrupt Level Setup Register 5 (ITC_LV5) Register name Address Bit Name Interrupt Level 0x4310 D15-11 - Setup Register 5 (16 bits) D10-8 ILV11[2:0] (ITC_LV5) D7-3 - D2-0 ILV10[2:0] Function reserved T16 Ch.2 interrupt level reserved T16 Ch.1 interrupt level Setting - 0 to 7 - 0 to 7 Init. R/W Remarks - - 0 when being read. 0x0 R/W - - 0 when being read. 0x0 R/W D[15:11] Reserved D[10:8] ILV11[2:0]: 16-bit Timer Ch.2 Interrupt Level Bits Set the 16-bit timer Ch.2 interrupt level (0 to 7). (Default: 0) Refer to the ITC_LV0 register (0x4306) ILV1[2:0] (D[10:8]) description. D[7:3] Reserved D[2:0] ILV10[2:0]: 16-bit Timer Ch.1 Interrupt Level Bits Set the 16-bit timer Ch.1 interrupt level (0 to 7). (Default: 0) Refer to the ITC_LV0 register (0x4306) ILV1[2:0] (D[10:8]) description. 6-14 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 6 Interrupt Controller 0x4312: Interrupt Level Setup Register 6 (ITC_LV6) Register name Address Bit Name Interrupt Level 0x4312 D15-11 - Setup Register 6 (16 bits) D10-8 ILV13[2:0] (ITC_LV6) D7-3 - D2-0 ILV12[2:0] Function reserved UART Ch.1 (slave) interrupt level reserved UART Ch.0 interrupt level Setting - 0 to 7 - 0 to 7 Init. R/W Remarks - - 0 when being read. 0x0 R/W - - 0 when being read. 0x0 R/W D[15:11] Reserved D[10:8] ILV13[2:0]: UART Ch.1/I2C (slave) Interrupt Level Bits Set the UART Ch.1 or I2C (slave) interrupt level (0 to 7). (Default: 0) Refer to the ITC_LV0 register (0x4306) ILV1[2:0] (D[10:8]) description. D[7:3] Reserved D[2:0] ILV12[2:0]: UART Ch.0 Interrupt Level Bits Set the UART Ch.0 interrupt level (0 to 7). (Default: 0) Refer to the ITC_LV0 register (0x4306) ILV1[2:0] (D[10:8]) description. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 6-15 6 Interrupt Controller 0x4314: Interrupt Level Setup Register 7 (ITC_LV7) Register name Address Bit Name Interrupt Level 0x4314 D15-11 - Setup Register 7 (16 bits) D10-8 ILV15[2:0] (ITC_LV7) D7-3 - D2-0 ILV14[2:0] Function reserved I2C (master) interrupt level reserved SPI interrupt level Setting - 0 to 7 - 0 to 7 Init. R/W Remarks - - 0 when being read. 0x0 R/W - - 0 when being read. 0x0 R/W D[15:11] Reserved D[10:8] ILV15[2:0]: I2C (master) Interrupt Level Bits Set the I2C interrupt level (0 to 7). (Default: 0) Refer to the ITC_LV0 register (0x4306) ILV1[2:0] (D[10:8]) description. D[7:3] Reserved D[2:0] ILV14[2:0]: SPI Interrupt Level Bits Set the SPI interrupt level (0 to 7). (Default: 0) Refer to the ITC_LV0 register (0x4306) ILV1[2:0] (D[10:8]) description. 6-16 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 6 Interrupt Controller 0x4316: Interrupt Level Setup Register 8 (ITC_LV8) Register name Address Interrupt Level 0x4316 Setup Register 8 (16 bits) (ITC_LV8) Bit Name D15-3 - D2-0 ILV16[2:0] Function reserved REMC interrupt level Setting - 0 to 7 D[15:3] Reserved D[2:0] ILV16[2:0]: REMC Interrupt Level Bits Set the remote controller interrupt level (0 to 7). (Default: 0) Refer to the discussion of ITC_LV0 register (0x4306) ILV1[2:0] (D[10:8]). S1C17003 TECHNICAL MANUAL Seiko Epson Corporation Init. R/W Remarks - - 0 when being read. 0x0 R/W 6-17 6 Interrupt Controller 0x4318: Interrupt Level Setup Register 9 (ITC_LV9) Register name Address Interrupt Level 0x4318 Setup Register 9 (16 bits) (ITC_LV9) Bit Name D15-3 - D2-0 ILV18[2:0] Function reserved A/D converter interrupt level Setting - 0 to 7 D[15:3] Reserved D[2:0] ILV18[2:0]: A/D Convertere Interrupt Level Bits Set the A/D converter interrupt level (0 to 7). (Default: 0) Refer to the discussion of ITC_LV0 register (0x4306) ILV1[2:0] (D[10:8]). 6-18 Seiko Epson Corporation Init. R/W Remarks - - 0 when being read. 0x0 R/W S1C17003 TECHNICAL MANUAL 6 Interrupt Controller 6.8 Precautions To prevent the recurrence of interrupts due to the same interrupt factor, always reset the interrupt flag before permitting interrupts, resetting PSR, or executing the reti instruction. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 6-19 7 Oscillator Circuit (OSC) 7 Oscillator Circuit (OSC) 7.1 OSC Module Configuration The S1C17003 contains two internal oscillator circuits (OSC3 and OSC1). The OSC3 oscillator circuit generates the main clock for high-speed operation of the S1C17 core and peripheral circuits. The OSC1 oscillator circuit generates a sub-clock for timer and low-power operations. The OSC3 clock is selected as the system clock after initial resetting. Oscillator circuit on/off switching and system clock selection (between OSC3 and OSC1) is controlled by software. External clock output is also possible. HSCLK (high-speed clock) can be used hereafter as an equivalent term as OSC3. Figure 7.1.1 illustrates the clock system and OSC module configuration. OSC CLG Clock source selection System HSCLK clock OSC3 OSC3 oscillator circuit OSC4 20MHz FOUTH Wait circuit for wakeup Clock gear (1/1 to 1/8) HALT Gate CCLK S1C17 core Gate BCLK Internal bus, RAM, ROM OSC1 SLEEP, on/off control FOUTH Division circuit output circuit (1/1 to 1/4) On/off control SLEEP, on/off control OSC1 OSC2 wakeup Gear selection On/off control HALT Gate PCLK Division ratio selection OSC1 oscillator circuit PSC 32.768kHz FOUT1 RESET NMI T16, T8F, UART, SPI, I2C (master), T16E, P, MISC, REMC, ADC, I2C(slave) On/off control FOUT1 output circuit Gate Division circuit (1/1 to 1/16K) On/off control Noise filter S1C17 core On/off control Noise filter S1C17 core On/off control OSC1 Division circuit CLK_256Hz CT, SWT, WDT (1/128) (1/1 to 1/32) T8F, T16, T16E, REMC, P, UART, SPI, I2C(maser), ADC Gate T8OSC1 Division ratio selection On/off control Figure 7.1.1: OSC module configuration To reduce power consumption, control the clock in conjunction with processing and use standby mode. For more information on reducing power consumption, refer to "Appendix B: Power Saving." S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 7-1 7 Oscillator Circuit (OSC) 7.2 OSC3 Oscillator Circuit OSC3 is a high-precision, high-speed oscillator circuit using crystal or ceramic oscillator. It generates the clock for S1C17 and peripheral circuits during initialization. Figure 7.2.1 illustrates the OSC3 oscillator circuit configuration. CG3 OSC3 Rf CD3 V SS fOSC3 X'tal3 or Ceramic Oscillator circuit control signal OSC4 SLEEP status Figure 7.2.1: OSC3 oscillator circuit A crystal oscillator (X'tal3) or ceramic oscillator (Ceramic) and feedback resistor (Rf) should be connected between the OSC3 and OSC4 pins. Additionally, two capacitors (CG3 and CD3) should be connected between the OSC3/ OSC4 pins and VSS. OSC3 oscillation on/off The OSC3 oscillator circuit stops oscillating if OSC3EN (D0/OSC_CTL register) is set to 0 and starts oscillating if set to 1. The OSC3 oscillator circuit stops oscillating even in SLEEP mode. * OSC3EN: OSC3 Enable Bit in the Oscillation Control (OSC_CTL) Register (D0/0x5061) After the initial resetting, OSC3EN is set to 1 and the OSC3 oscillator circuit is on. To use the OSC3 clock, the clock must also be switched, in addition to the on/off controls described above. For specific information on switching, see "7.4 Clock Switching." Stabilization wait time at start of OSC3 oscillation When using the OSC3 clock, the OSC3 oscillator circuit incorporates an oscillation stabilization wait timer to prevent malfunctions due to unstable clock operations at the start of OSC3 oscillation--e.g., when waking from SLEEP, or when the OSC3 oscillation circuit is switched on via software. The OSC3 clock is not fed to the system until the time set for this timer has elapsed. Use the OSC3WT[1:0] (D[5:4]/OSC_CTL register) to select among four different oscillation stabilization wait times. * OSC3WT[1:0]: OSC3 Wait Cycle Select Bits in the Oscillation Control (OSC_CTL) Register (D[5:4]/0x5061) Table 7.2.1: OSC3 oscillation stabilization wait time settings OSC3WT[1:0] 0x3 0x2 0x1 0x0 Oscillation stabilization wait time 128 cycles 256 cycles 512 cycles 1,024 cycles (Default: 0x0) This is set to 1,024 cycles (OSC3 clock) after initial resetting. Note: The stability of oscillation depends on the oscillator and external add-on components. Full evaluation is required for configuring shorter stabilization wait time. OSC3 clock system supply wait time =< OSC3 oscillation start time (max.) + OSC3 oscillation stabilization wait time. External clock input of OSC3 The clock can be input to the OSC3 pin from external. To stop the external clock, stop it at the VSS level. For information about input clock waveforms, refer to "26 Electrical Characteristics." 7-2 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 7 Oscillator Circuit (OSC) 7.3 OSC1 Oscillator Circuit OSC1 is a high-precision, low-speed oscillator circuit using a 32.768 kHz crystal oscillator. The OSC1 clock is generally used as the timer operation clock (for the clock timer, stopwatch timer, watchdog timer, and 8-bit OSC1 timer). It reduces power consumption and can be used as the system clock instead of the OSC3 clock when no high-speed processing is required. Figure 7.3.1 illustrates the OSC1 oscillator circuit configuration. SLEEP status OSC1 fOSC1 CG1 X'tal1 OSC2 V SS V SS Figure 7.3.1: OSC1 oscillator circuit A crystal oscillator (X'tal1) (typ. 32.768 kHz) should be connected between the OSC1 and OSC2 pins. Additionally, trimmer capacitor CG1 (0 to 25 pF) should be connected between the OSC1 pin and VSS. OSC1 oscillation on/off The OSC1 oscillator circuit stops oscillating if OSC1EN (D1/OSC_CTL register) is set to 0 and starts oscillating if set to 1. The OSC1 oscillator circuit stops oscillating even in SLEEP mode. * OSC1EN: OSC1 Enable Bit in the Oscillation Control (OSC_CTL) Register (D1/0x5061) Following initial resetting, OSC1EN is set to 0, and the OSC1 oscillator circuit is halted. Stabilization wait time at start of OSC1 oscillation The OSC1 oscillator circuit incorporates an oscillation stabilization wait timer to prevent malfunctions due to unstable clock operations at the start of OSC1 oscillation--for example, when power is first turned on, on awaking from SLEEP, or when the OSC1 oscillation circuit is turned on via software. The OSC1 clock does not feed the system for a period of 256 cycles after the start of oscillation. OSC clock system supply wait time =< IOSC oscillation start time (max.) + OSC1 oscillation stabilization wait time. Pin settings when OSC1 is not used Keep the OSC1 and OSC2 pins open. Note: Set OSC1EN (the D1/OSC_CTL register) to 0 while the OSC1 and OSC2 pins are kept open. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 7-3 7 Oscillator Circuit (OSC) 7.4 Clock Switching The system clock select section of the S1C17003 consists of OSC1-HSCLK select. Figure 7.4.1 shows the configuration of the system clock select section. CLKSRC OSC3 =HSCLK System clock OSC1 Figure 7.4.1: System clock select section OSC1 HSCLK selection The S1C17003 includes the OSC1 oscillator circuit to generate low-speed clocks. Either of the OSC1 or HSCLK can be selected for the system clock. HSCLK is selected when operation starts after the initial reset. To select OSC1 for the system clock, turn on the OSC1 oscillator circuit (see section 7.4), and then write 1 to CLKSRC (D1/OSC_SRC register). To select HSCLK for the system clock, write 0 to SRCSRC while HSCLK is operating. * CLKSRC: System Clock Source Select Bit in the Clock Source Select (OSC_SRC) Register (D0/0x5060) Oscillator circuits other than selected for the system clock and are not used as the operating clock for peripheral circuits can be stopped to reduce current consumption. Notes: * To select OSC1_HSCLK, both of the OSC1 and HSCLK must be operating. Writing to HSCLKSEL while one of them is not operating does not switch the system clock, and does not change the CLKSRC value. * The oscillator circuit selected for the system clock cannot be turned off. * Sequential access of write/read to the CLKSRC register is prohibited. Between write and read access instructions to CLKSRC, insert at least one instruction unrelated to access to the CLKSRC register. * It takes one HSCLK cycle at minimum or one OSC1 cycle at maximum to switch clocks from OSC1 to HSCLK and vice versa. 7-4 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 7 Oscillator Circuit (OSC) 7.5 8-bit OSC1 Timer Clock Control The OSC module consists of a division circuit for generating the 8-bit OSC1 timer operation clock and a device for controlling the feed. The 8-bit OSC1 timer is a programmable timer that operates only using the OSC1 division clock. For detailed information, refer to "14 8-bit OSC1 Timer (T8OSC1)." OSC1 clock Division circuit (1/1 to 1/32) Division ratio selection Gate 8-bit OSC1 timer On/off control Figure 7.5.1: 8-bit OSC1 timer clock control circuit Clock division ratio selection Select the OSC1 clock division ratio using T8O1CK[2:0] (D[3:1]/OSC_T8OSC1 register) * T8O1CK[2:0]: T8OSC1 Clock Division Ratio Select Bits in the T8OSC1 Clock Control (OSC_T8OSC1) Register (D[3:1]/0x5065) Table 7.5.1: T8OSC1 clock division ratio selection T8O1CK[2:0] 0x7 to 0x6 0x5 0x4 0x3 0x2 0x1 0x0 Division ratio Reserved OSC1-1/32 OSC1-1/16 OSC1-1/8 OSC1-1/4 OSC1-1/2 OSC1-1/1 (Default: 0x0) Clock feed control The clock feed to the 8-bit OSC1 timer is controlled using T8O1CE (D0/OSC_T8OSC1 register). The T8O1CE default setting is 0, which stops the clock feed. Setting T8O1CE to 1 sends the clock generated as above to the 8-bit OSC1 timer. Stop the clock feed to reduce power consumption if 8-bit OSC1 timer operation is not required. * T8O1CE: T8OSC1 Clock Enable Bit in the T8OSC1 Clock Control (OSC_T8OSC1) Register (D0/0x5065) Note: Change of clock division ratio selection (T8O1CK [2:0](D[3:1]/0x5063)) should be executed when T8O1CE(D0/0x5065) is 0 and the clock to 8-bit OSC1 timer is in "Stop" state. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 7-5 7 Oscillator Circuit (OSC) 7.6 Clock External Output (FOUTH, FOUT1) The HSCLKdivision clock (FOUTH) and OSC1 clock (FOUT1) can be output to devices outside the chip. P40 port HSCLK clock Division circuit (1/1 to 1/4) FOUTH(P40) FOUTH Output circuit Division ratio selection On/off control P40 function selection P35 port FOUT1(P35) FOUT1 Output circuit OSC1 clock On/off control P35 function selection Figure 7.6.1: Clock output circuit FOUTH output FOUTH is the HSCLK division clock. Output pin setting The FOUTH output pin is combined with the P40 port. This functions as the P40 port pin by default, so the pin function should be changed by writing 1 to P40MUX (D0/P4_PMUX register) if use is required for FOUTH output. * P40MUX: P40 Port Function Select Bit in the P4 Port Function Select (P4_PMUX) Register (D0/0x52a8) FOUTH clock frequency selection Three different clock output frequencies can be selected. Select the division ratio for the OSC3 clock using FOUTHD[1:0] (D[3:2]/OSC_FOUT register). * FOUTHD[1:0]: FOUTH Clock Division Ratio Select Bits in the FOUT Control (OSC_FOUT) Register (D[3:2]/0x5064) Table 7.6.1: FOUTH clock division ratio selection FOUTHD[1:0] 0x3 0x2 0x1 0x0 Division ratio Reserved OSC3-1/4 OSC3-1/2 OSC3-1/1 (Default: 0x0) Clock output control The clock output is controlled using the FOUTHE (D1/OSC_FOUT register). Setting FOUTHE to 1 outputs the FOUTH clock from the FOUTH pin. Setting it to 0 halts output. * FOUTHE: FOUTH Output Enable Bit in the FOUT Control (OSC_FOUT) Register (D1/0x5064) FOUT3E 0 1 0 FOUTH output (P30) Figure 7.6.2: FOUTH output Notes: * Since the FOUTH signal is asynchronized with FOUTHE writing, switching output on or off will generate certain hazards. * Change of the single selection (FOUTHD [1:0] (D[3:2]/0x5064) of FOUTH clock frequency should be executed when FOUTHE (D1/0x5064) is 0 and clock output is in "Stop" status. 7-6 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 7 Oscillator Circuit (OSC) FOUT1 output FOUT1 is the OSC1 clock. Output pin setting The FOUT1 output pin is combined with the P35 port. This functions as the P35 port pin by default, so the pin function should be changed by writing 1 to P35MUX (D3/P1_PMUX register) if use is required for FOUT1 output. * P35MUX: P35 Port Function Select Bit in the P3 Port Function Select (P3_PMUX) Register (D3-2/0x52a7) Clock output control The clock output is controlled using the FOUT1E (D0/OSC_FOUT register). Setting FOUT1E to 1 outputs the FOUT1 clock from the FOUT1 pin. Setting it to 0 halts output. * FOUT1E: FOUT1 Output Enable Bit in the FOUT Control (OSC_FOUT) Register (D1/0x5064) FOUT1E 0 1 0 FOUT1 output (P13) Figure 7.6.3: FOUT1 output Note: Since the FOUT1 signal is asynchronized with FOUT1E writing, switching output on or off will generate certain hazards. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 7-7 7 Oscillator Circuit (OSC) 7.7 RESET and NMI Input Noise Filters Since accidental activation of RESET or NMI by noise in the S1C17 core input signal will cause unintended resetting or NMI processing, the OSC module incorporates noise filters operated by the system clock. The filters remove noise from these signals before they reach the S1C17 core. Separate noise filters are used for each signal. You can select to use or bypass them individually. All are active immediately after the initial resetting. RESET input noise filter: Filters noise when RSTFE (D1/OSC_NFEN register) = 1; bypassed when RSTFE = 0 NMI input noise filter: Filters noise when NMIFE (D0/OSC_NFEN register) = 1; bypassed when NMIFE = 0 * RSTFE: Reset Noise Filter Enable Bit in the Noise Filter Enable (OSC_NFEN) Register (D1/0x5062) * NMIFE: NMI Noise Filter Enable Bit in the Noise Filter Enable (OSC_NFEN) Register (D0/0x5062) Notes: 7-8 * All noise filters should normally be enabled. * The S1C17003 does not feature external NMI input pins, but the watchdog timer NMI request signal passes through these filters. Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 7 Oscillator Circuit (OSC) 7.8 Control Register Details Table 7.8.1: OSC register list Address 0x5060 0x5061 0x5062 0x5063 0x5064 0x5065 0x5066 0x5067 Register name OSC_SRC OSC_CTL OSC_NFEN reserved OSC_FOUT OSC_T8OSC1 reserved reserved Function Clock Source Select Register Oscillation Control Register Noise Filter Enable Register reserved FOUT Control Register T8OSC1 Clock Control Register reserved reserved Clock source selection Oscillation control Noise filter on/off reserved Clock external output control 8-bit OSC1 timer clock setting reserved reserved The OSC module registers are described in detail below. These are 8-bit registers. Note: When data is written to the registers, the "Reserved" bits must always be written as 0 and not 1. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 7-9 7 Oscillator Circuit (OSC) 0x5060: Clock Source Select Register (OSC_SRC) Register name Address Clock Source Select Register (OSC_SRC) 0x5060 (8 bits) Bit Name Function D7-2 - reserved HSCLKSEL High-speed clock select D1 CLKSRC D0 System clock source select D[7:2] Reserved D1 HSCLKSEL: High-speed Clock Select Bit Selects the high-speed clock (HSCLK). 1 (R): OSC3 (fixed) D0 CLKSRC: System Clock Source Select Bit Selects the system clock source. 1 (R/W): OSC1 0 (R/W): HSCLK (default) Setting - 1 OSC3 1 OSC1 0 HSCLK Init. R/W - 1 0 Remarks - 0 when being read. R 1 when being read. R/W HSCLK (OSC3) is selected for normal (high-speed) operations. If the HSCLK clock is not required, OSC1 can be set as the system clock and HSCLK (OSC3) stopped to reduce power consumption. Notes: 7-10 * If the system clock is switched from HSCLK to OSC1 immediately after starting OSC1 oscillation, the system clock will stop until the OSC1 clock starts up (for the OSC1 clock 256-cycle period). * Continuous access of write and read to CLKSRC register (DO/Ox5060) is prohibited. Enter at least one instruction that is not related to access to CLKSRC register between write and read. Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 7 Oscillator Circuit (OSC) 0x5061: Oscillation Control Register (OSC_CTL) Register name Address 0x5061 Oscillation Control Register (8 bits) (OSC_CTL) Bit D3-2 D1 D0 D[5:4] Name Function Setting D7-6 - reserved D5-4 OSC3WT[1:0] OSC3 wait cycle select - OSC1EN OSC3EN reserved OSC1 enable OSC3 enable - OSC3WT[1:0] 0x3 0x2 0x1 0x0 Wait cycle 128 cycles 256 cycles 512 cycles 1024 cycles - 1 Enable 1 Enable 0 Disable 0 Disable Init. R/W Remarks - - 0 when being read. 0x0 R/W - 0 1 - 0 when being read. R/W R/W OSC3WT[1:0]: OSC3 Wait Cycle Select Bits An oscillation stabilization wait timer is set to prevent malfunctions due to unstable clock operation at the start of OSC3 oscillation. The OSC3 clock is not fed to the system immediately after OSC3 oscillation starts--for example, when power is first turned on, on awaking from SLEEP, or when the OSC3 oscillation circuit is turned on via software--until the time set here has elapsed. Table 7.8.2: OSC3 oscillation stabilization wait time settings OSC3WT[1:0] 0x3 0x2 0x1 0x0 Oscillation stabilization wait time 128 cycles 256 cycles 512 cycles 1,024 cycles (Default: 0x0) This is set to 1,024 cycles (OSC3 clock) after initial resetting. The CPU does not begin operating immediately after resetting until this time has elapsed. Note: The OSC3 oscillation start time depends on the oscillator and externally connected components. The time should be set with an adequate oscillation stabilization wait time. Refer to the typical oscillation start times specified in "26 Electrical Characteristics." D[3:2] Reserved D1 OSC1EN: OSC1 Enable Bit Permits or prohibits OSC1 oscillator circuit operation. 1 (R/W): Permitted (on) 0 (R/W): Prohibited (off) (default) Notes: D0 * The OSC1 oscillator circuit cannot be stopped if the OSC1 clock is being used as the system clock. * The OSC1 clock is not fed to the system for 256 cycles to prevent malfunctions immediately after OSC1 oscillation is started by changing the OSC1EN setting from 0 to 1. OSC3EN: OSC3 Enable Bit Permits or prohibits OSC3 oscillator circuit operation. 1 (R/W): Permitted (on) (default) 0 (R/W): Prohibited (off) Note: The OSC3 oscillator circuit cannot be stopped if the OSC3 clock is being used as the system clock. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 7-11 7 Oscillator Circuit (OSC) 0x5062: Noise Filter Enable Register (OSC_NFEN) Register name Address 0x5062 Noise Filter Enable Register (8 bits) (OSC_NFEN) Bit Name D7-2 - RSTFE D1 NMIFE D0 Function reserved Reset noise filter enable NMI noise filter enable D[7:2] Reserved D1 RSTFE: Reset Noise Filter Enable Bit Enables or disables the RESET input noise filter. 1 (R/W): Enabled (noise filtering) (default) 0 (R/W): Disabled (bypass) Setting - 1 Enable 1 Enable 0 Disable 0 Disable Init. R/W - 1 0 Remarks - 0 when being read. R/W R/W This noise filter inputs only RESET pulses of not less than 16 cycles of the system clock (OSC3 or OSC1 clock) to the S1C17 core. This should normally be enabled. D0 NMIFE: NMI Noise Filter Enable Bit Enables or disables the NMI input noise filter. 1 (R/W): Enabled (noise filtering) 0 (R/W): Disabled (bypass) (default) This noise filter inputs only NMI pulses of not less than 16 cycles of the system clock (OSC3 or OSC1 clock) to the S1C17 core. Pulses having widths of less than 16 cycles are filtered out as noise. This should normally be enabled. Note: The S1C17003 does not feature external NMI input pins, but the watchdog timer NMI request signal passes through these filters. 7-12 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 7 Oscillator Circuit (OSC) 0x5064: FOUT Control Register (OSC_FOUT) Register name Address FOUT Control Register (OSC_FOUT) 0x5064 (8 bits) Bit D7-4 D3-2 D1 D0 Name Function Setting - reserved FOUTHD[1:0] FOUTH clock division ratio select FOUTHE FOUT1E FOUTH output enable FOUT1 output enable - FOUTHD[1:0] Division ratio reserved 0x3 HSCLK-1/4 0x2 HSCLK-1/2 0x1 HSCLK-1/1 0x0 1 Enable 0 Disable 1 Enable 0 Disable D[7:4] Reserved D[3:2] FOUTHD[1:0]: FOUTH Clock Division Ratio Select Bits Select the HSCLK clock division ratio to set the FOUTH clock frequency. Init. R/W Remarks - - 0 when being read. 0x0 R/W 0 0 R/W R/W Table 7.8.3: FOUTH clock division ratio selection FOUTHD[1:0] 0x3 0x2 0x1 0x0 Division ratio Reserved OSC3-1/4 OSC3-1/2 OSC3-1/1 (Default: 0x0) D1 FOUTHE: FOUTH Output Enable Bit Permits or prohibits FOUTH clock (HSCLK division clock) external output. 1 (R/W): Permitted (on) 0 (R/W): Prohibited (off) (default) Setting FOUTHE to 1 outputs the FOUTH clock from the FOUTH pin. Setting it to 0 stops the output. D0 FOUT1E: FOUT1 Output Enable Bit Permits or prohibits FOUT1 clock (OSC1 clock) external output. 1 (R/W): Permitted (on) 0 (R/W): Prohibited (off) (default) Setting FOUT1E to 1 outputs the FOUT1 clock from the FOUT1 pin. Setting it to 0 stops the output. Note: Change of the single selection (FOUTHD [1:0] (D[3:2]/0x5064) of FOUTH clock frequency should be executed when FOUTHE (D1/0x5064) is 0 and clock output is in "Stop" status. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 7-13 7 Oscillator Circuit (OSC) 0x5065: T8OSC1 Clock Control Register (OSC_T8OSC1) Register name Address T8OSC1 Clock 0x5065 Control Register (8 bits) (OSC_T8OSC1) Bit D7-4 D3-1 D0 Name Function Setting Init. R/W - reserved - T8O1CK[2:0] T8OSC1 clock division ratio select T8O1CK[2:0] Division ratio reserved 0x7-0x6 OSC1-1/32 0x5 OSC1-1/16 0x4 OSC1-1/8 0x3 OSC1-1/4 0x2 OSC1-1/2 0x1 OSC1-1/1 0x0 T8O1CE T8OSC1 clock output enable 1 Enable 0 Disable Remarks - - 0 when being read. 0x0 R/W 0 D[7:4] Reserved D[3:1] T8O1CK[2:0]: T8OSC1 Clock Division Ratio Select Bits Select the OSC1 clock division ratio and set the 8-bit OSC1 timer operation clock. R/W Table 7.8.4: T8OSC1 clock division ratio selection T8O1CK[2:0] 0x7 to 0x6 0x5 0x4 0x3 0x2 0x1 0x0 Division ratio Reserved OSC1-1/32 OSC1-1/16 OSC1-1/8 OSC1-1/4 OSC1-1/2 OSC1-1/1 (Default: 0x0) D0 T8O1CE: T8OSC1 Clock Output Enable Bit Permits or prohibits clock feed to the 8-bit OSC1 timer. 1 (R/W): Permitted (on) 0 (R/W): Prohibited (off) (default) The T8O1CE default setting is 0, which stops the clock feed. Setting T8O1CE to 1 sends the clock selected by the above bit to the 8-bit OSC1 timer. Stop the clock feed to reduce power consumption if 8-bit OSC1 timer operation is not required. Note: Change of clock division ratio selection (T8O1CK [2:0](D[3:1]/0x5063)) should be executed when T8O1CE(D0/0x5065) is 0 and the clock to 8-bit OSC1 timer is in "Stop" state. 7-14 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 7 Oscillator Circuit (OSC) 7.9 Precautions * The oscillation start time depends on the oscillator and externally connected components. The time should be set with an adequate OSC3 oscillation stabilization wait time. Refer to the typical oscillation start times specified in "26 Electrical Characteristics." * Switching the system clock from HSCLK to OSC1 immediately after starting OSC1 oscillation will stop the system clock until the OSC1 clock starts up (for the OSC1 clock 256-cycle period). * The OSC3 oscillator circuit cannot be stopped if the OSC3 clock is being used as the system clock. * The OSC1 oscillator circuit cannot be stopped if the OSC1 clock is being used as the system clock. * Since the FOUTH/FOUT1 signal is asynchronized with FOUTHE/FOUT1E writing, switching output on or off will generate certain hazards. * Continuous access of write and read to CLKSRC register (D0/0x5060) is prohibited. Enter at least one instruction that is not related to access to CLKSRC register between write and read. * Change of clock division ratio selection (T8O1CK [2:0](D[3:1]/0x5065)) should be executed when T8O1CE(D0/ 0x5065) is 0 and the clock to 8-bit OSC1 timer is in "Stop" state. * Change of the single selection (FOUTHD [1:0] (D[3:2]/0x5064) of FOUTH clock frequency should be executed when FOUTHE (D1/0x5064) is 0 and clock output is in "Stop" status. * The stability of oscillation depends on the oscillator and external add-on components. Full evaluation is required for configuring shorter stabilization wait time. OSC3 clock system supply wait time =< OSC3 oscillation start time (max.) + OSC3 oscillation stabilization wait time. * Set OSC3EN (the D0/OSC_CTL register) to 0 while the OSC3 and OSC4 pins are kept open. * Set OSC1EN (the D1/OSC_CTL register) to 0 while the OSC1 and OSC2 pins are kept open. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 7-15 8 Clock Generator (CLG) 8 Clock Generator (CLG) 8.1 Clock Generator Configuration The clock generator controls the system clock feed to the S1C17 core and peripheral modules. Figure 8.1.1 illustrates the clock system and CLG module configuration. OSC CLG Clock source selection System (HSCLK) clock wakeup OSC3 OSC4 FOUTH OSC3 oscillator circuit FOUT1 RESET NMI HALT Gate CCLK S1C17 core Gate BCLK Internal bus, RAM, ROM OSC1 SLEEP, on/off control FOUTH Division circuit output circuit (1/1 to 1/4) On/off control SLEEP, on/off control OSC1 OSC2 Wait circuit for wakeup Gear selection Clock gear (1/1 to 1/8) On/off control HALT Gate PCLK Division ratio selection OSC1 oscillator circuit T16, T8F, UART, SPI, I2C (master), T16E, P, MISC, REMC, ADC, I2C(slave) PSC On/off control FOUT1 output circuit Gate Division circuit (1/1 to 1/16K) On/off control Noise filter S1C17 core On/off control Noise filter S1C17 core On/off control OSC1 Division circuit CLK_256Hz CT, SWT, WDT (1/128) (1/1 to 1/32) T8F, T16, T16E, REMC, P, UART, SPI, I2C(maser), ADC Gate T8OSC1 Division ratio selection On/off control Figure 8.1.1: CLG module configuration To reduce power consumption, control the clock in conjunction with processing and use standby mode. For more information on reducing power consumption, refer to "Appendix B: Power Saving." S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 8-1 8 Clock Generator (CLG) 8.2 CPU Core Clock (CCLK) Control The CLG module incorporates a clock gear to slow down the system clock to send to the S1C17 core. To reduce power consumption, operate the S1C17 core with the slowest possible clock speed. The halt instruction can be executed to stop the clock feed from the CLG to the S1C17 core for power savings. Gear selection HSCLK System clock OSC1 Cock gear (1/1 to 1/8) HALT Gate CCLK S1C17 core Figure 8.2.1: CCLK feed system Clock gear settings CCLKGR[1:0] (D[1:0]/CLG_CCLK register) is used to select the gear ratio to reduce system clock speeds. * CCLKGR[1:0]: CCLK Clock Gear Ratio Select Bits in the CCLK Control (CLG_CCLK) Register (D[1:0]/0x5081) Table 8.2.1: CCLK gear ratio selection CCLKGR[1:0] 0x3 0x2 0x1 0x0 Gear ratio 1/8 1/4 1/2 1/1 (Default: 0x0) Clock feed control The CCLK clock feed is stopped by executing the halt instruction. Since this does not stop the system clock, peripheral modules will continue to operate. HALT mode is cleared by resetting, NMI, or other interrupts. The CCLK feed resumes when HALT mode is cleared. Executing the slp instruction suspends system clock feed to the CLG, thereby halting the CCLK feed as well. Clearing SLEEP mode with an external interrupt restarts the system clock feed and the CCLK feed. For more information on system clock control, refer to "7 Oscillator Circuit (OSC)." 8-2 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 8 Clock Generator (CLG) 8.3 Peripheral Module Clock (PCLK) Control The CLG module also controls the clock feed to peripheral modules. The system clock is used unmodified for the peripheral module clock (PCLK). On/off control HSCLK System clock Gate PCLK OSC1 Internal peripheral circuits * Prescaler * UART Ch.0, Ch.1 * 8-bit timer Ch.0, Ch.1 * 16-bit timer Ch.0 to 2 * SPI * I2C (master/slave) * P port & port MUX * PWM & capture timer * MISC register * Remote controller * A/D converter Figure 8.3.1: Peripheral module clock control circuit Clock feed control PCLK feed is controlled by PCKEN[1:0] (D[1:0]/CLG_PCLK register). * PCKEN[1:0]: PCLK Enable Bits in the PCLK Control (CLG_PCLK) Register (D[1:0]/0x5080) Table 8.3.1: PCLK control PCKEN[1:0] 0x3 0x2 0x1 0x0 PCLK feed Permitted (on) Setting prohibited Setting prohibited Prohibited (off) (Default: 0x3) The default setting is 0x3, which enables the clock feed. Stop the clock feed to reduce power consumption unless all peripheral modules (modules listed above) within the internal peripheral circuit area need to be running. Note: Do not set PCKEN[1:0] (D[1:0]/CLG_PCLK register) to 0x2 or 0x1, since doing so will stop the operation of certain peripheral modules. Peripheral modules not operating on PCLK The OSC1 peripheral module operates using a clock other than PCLK. Therefore, PCLK is not required. OSC1 peripheral module The clock timer, stopwatch timer, watchdog timer, and 8-bit OSC1 timer operate using the OSC1 division clock. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 8-3 8 Clock Generator (CLG) 8.4 Control Register Details Table 8.4.1 CLG register list Address 0x5080 0x5081 Register name CLG_PCLK CLG_CCLK PCLK Control Register CCLK Control Register Function PCLK feed control CCLK division ratio setting The CLG module registers are described in detail below. These are 8-bit registers. Note: When data is written to the registers, the "Reserved" bits must always be written as 0 and not 1. 8-4 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 8 Clock Generator (CLG) 0x5080: PCLK Control Register (CLG_PCLK) Register name Address PCLK Control Register (CLG_PCLK) 0x5080 (8 bits) Bit D7-2 D1-0 Name Function Setting - reserved PCKEN[1:0] PCLK enable - PCKEN[1:0] 0x3 0x2 0x1 0x0 PCLK supply Enable Not allowed Not allowed Disable D[7:2] Reserved D[1:0] PCKEN[1:0]: PCLK Enable Bits Permit or prohibit clock (PCLK) feed to internal peripheral modules. Init. R/W Remarks - - 0 when being read. 0x3 R/W Table 8.4.2: PCLK control PCKEN[1:0] 0x3 0x2 0x1 0x0 PCLK feed Permitted (on) Setting prohibited Setting prohibited Prohibited (off) (Default: 0x3) The PCKEN[1:0] default setting is 0x3, which enables clock feed. Stop the clock feed to reduce power consumption if the peripheral modules listed below are not required. Peripheral modules operated using PCLK * Prescaler (PWM timer, remote controller, P port) * UART Ch.0 to 1 * 8-bit timer Ch.0 to 1 * 16-bit timer Ch.0 to 2 * SPI * I2C (master/slave) * P port & port MUX * PWM & capture timer * MISC register * Remote controller * A/D converter The following peripheral modules operate, including access to control registers, using a clock other than PCLK. Therefore, PCLK does not need to be turned on. * Clock timer * Stopwatch timer * Watchdog timer * 8-bit OSC1 timer Note: Do not set PCKEN[1:0] to 0x2 or 0x1, since doing so will stop the operation of certain peripheral modules. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 8-5 8 Clock Generator (CLG) 0x5081: CCLK Control Register (CLG_CCLK) Register name Address CCLK Control Register (CLG_CCLK) 0x5081 (8 bits) Bit D7-2 D1-0 Name Function - reserved CCLKGR[1:0] CCLK clock gear ratio select Setting Init. R/W - CCLKGR[1:0] 0x3 0x2 0x1 0x0 Gear ratio 1/8 1/4 1/2 1/1 Remarks - - 0 when being read. 0x0 R/W D[7:2] Reserved D[1:0] CCLKGR[1:0]: CCLK Clock Gear Ratio Select Bits Select the gear ratio for reducing system clock speed and set the CCLK clock speed for operating the S1C17 core. To reduce power consumption, operate the S1C17 core using the slowest possible clock speed. Table 8.4.3: CCLK gear ratio selection CCLKGR[1:0] 0x3 0x2 0x1 0x0 Gear ratio 1/8 1/4 1/2 1/1 (Default: 0x0) 8-6 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 8 Clock Generator (CLG) 8.5 Precautions (1) The default settings enable PCLK feed to peripheral modules. To reduce power consumption, stop the clock feed if the peripheral modules listed below are not used. Peripheral modules operated using PCLK * Prescaler (PWM timer, remote controller, P port) * UART Ch.0 to 1 * 8-bit timer Ch.0 to 1 * 16-bit timer Ch.0 to 2 * SPI * I2C (master/slave) * P port & port MUX * PWM & capture timer * MISC register * Remote controller * A/D converter The following peripheral modules operate, including access to control registers, using a clock other than PCLK. Therefore, PCLK does not need to be turned on. * Clock timer * Stopwatch timer * Watchdog timer * 8-bit OSC1 timer (2) Do not set PCKEN[1:0] (D[1:0]/CLG_PCLK register) to 0x2 or 0x1, since doing so will stop the operation of certain peripheral modules. * PCKEN[1:0]: PCLK Enable Bits in the PCLK Control (CLG_PCLK) Register (D[1:0]/0x5080) S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 8-7 9 Prescaler (PSC) 9 Prescaler (PSC) 9.1 Prescaler Configuration The S1C17003 incorporates a prescaler to generate a clock for timer operations. The prescaler generates 15 different frequencies by dividing the PCLK clock fed from the clock generator into 1/1 to 1/16K. The peripheral modules to which the clock is fed include clock selection registers enabling selection of one as a count or operation clock. PSC PCLK 1/1 1/2 1/4 1/8 1/16 1/32 1/64 1/128 Debug status signal 1/256 1/512 1/1K 1/2K 1/4K 1/8K 1/16K 8-bit timer Ch.0 8-bit timer Ch.1 16-bit timer Ch.0 16-bit timer Ch.1 16-bit timer Ch.2 PWM timer Ch.0 Remote controller P port UART Ch.0 UART Ch.1 ADC SPI I2C (master) Figure 9.1.1: Prescaler The prescaler is controlled by the PRUN bit (D0/PSC_CTL register). To operate the prescaler, write 1 to PRUN. Writing 0 to PRUN stops the prescaler. Stopping the prescaler while the timer and interface module are halted enables the current consumption to be reduced. The prescaler is stopped immediately after initial resetting. * PRUN: Prescaler Run/Stop Control Bit in the Prescaler Control (PSC_CTL) Register (D0/0x4020) Note: PCLK must be fed from the clock generator to use the prescaler. The prescaler features another control bit, PRUND (D1/PSC_CTL register), which specifies prescaler operations in Debug mode. Setting PRUND to 1 also operates the prescaler in Debug mode. Setting it to 0 stops the prescaler once the S1C17 core switches to Debug mode. Set PRUND to 1 if the timer and interface module are to be used during debugging. * PRUND: Prescaler Run/Stop Setting Bit in Debug Mode in the Prescaler Control (PSC_CTL) Register (D1/0x4020) S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 9-1 9 Prescaler (PSC) 9.2 Control Register Details Table 9.2.1: Prescaler register Address 0x4020 Register name PSC_CTL Function Prescaler Control Register Prescaler start/stop control The prescaler register is an 8-bit register. Note: When data is written to the registers, the "Reserved" bits must always be written as 0 and not 1. 0x4020: Prescaler Control Register (PSC_CTL) Register name Address Prescaler Control Register (PSC_CTL) 0x4020 (8 bits) Bit D7-2 D1 D0 Name - PRUND PRUN Function Setting reserved Prescaler run/stop in debug mode 1 Run Prescaler run/stop control 1 Run D[7:2] Reserved D1 PRUND: Prescaler Run/Stop Setting Bit for Debug Mode Selects prescaler operations in Debug mode. 1 (R/W): Operate 0 (R/W): Stop (default) - 0 Stop 0 Stop Init. R/W - 0 0 Remarks - 0 when being read. R/W R/W Setting PRUND to 1 operates the prescaler even in Debug mode. Setting it to 0 stops the prescaler once the S1C17 core switches to Debug mode. Set PRUND to 1 to use the timer and interface module during debugging. D0 PRUN: Prescaler Run/Stop Control Bit Starts or stops prescaler operation. 1 (R/W): Start operation 0 (R/W): Stop (default) Write 1 to PRUN to operate the prescaler. Write 0 to PRUN to stop the prescaler. To reduce current consumption, stop the prescaler if the timer and interface module are already stopped. 9-2 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 9 Prescaler (PSC) 9.3 Precautions PCLK must be fed from the clock generator to use the prescaler. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 9-3 10 Input/Output Port (P) 10 Input/Output Port (P) 10.1 Input/Output Port Configuration The S1C17003 includes 30 input/output ports (P0[7:0], P1[6:0], P2[7,4,3], P3[7:0], P4[3:0]) and four input only ports (P17, P2[2:0]) to allow software switching of input/output direction. These share internal peripheral module input/output pins (with certain exceptions), but pins not used for peripheral modules can be used as general purpose input/output ports. Figure 10.1.1 illustrates the input/output port configuration. Internal data bus Pull-up enable PxPUy VDD Output enable PxOENy Peripheral module I/O control Function selection PxyMUX Output data PxOUTy Peripheral module output Pxy VSS Input enable PxIENy Peripheral module input Figure 10.1.1: Input/output port configuration The P0 and P1 ports can generate input interrupts. The P0[3:0] port can be used for key entry resets. (For more information, refer to "5.1.2 P0 Port Key Entry Reset.") Note: The PCLK clock must be fed from the clock generator to access the input/output port. The prescaler output clock is also needed to operate the P0/P1 port chattering filter. Switch on the prescaler when using this function. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 10-1 10 Input/Output Port (P) 10.2 Input/Output Pin Function Selection (Port MUX) The input/output port pins share peripheral module input/output pins (with certain exceptions). Each pin can be set for use as an input/output port or for peripheral modules via the corresponding port function selection bits for each port. Pins not used for peripheral modules can be used as general purpose input/output ports. Table 10.2.1: Input/output pin function selection Pin function 1 PxxMUX = 0 Pin function 2 PxxMUX = 01 Pin function 3 PxxMUX = 10 P00 REMOREMC P01 REMIREMC P02/EXCL0T16 P03 #ADTRGADC10SA P04 SPICLKSPI P05 SDOSPI P06 SDISPI P07 #SPISSSPI P10 SCLK0UART P11 SOUT0UART P12 SIN0UART P13/EXCL1T16 P14/EXCL2T16 P15/EXCL3T16E P16 SCLK1UART P17 AIN3ADC10SA P20 AIN2ADC10SA P21 AIN1ADC10SA P22 AIN0ADC10SA P23 P24 P27 SOUT1(UART) P30 SIN1(UART) P31 SCL0I2CM P32 SDA0I2CM P33 SCL1I2CS SCL0I2CM P34 SDA1I2CS SDA0I2CM P35 FOUT1CLG #BFRI2CS P36 TOUT3T16E P37 TOUTN3T16E P40 FOUTHCLG DSIODBG P41 DST2DBG P42 DCLKDBG P43 Pin function 4 PxxMUX = 11 Port function selection bit TOUT4(T8OSC1) P00MUXD1-0 P01MUXD3-2 P02MUXD5-4 P03MUXD7-6 P04MUXD1-0 P05MUXD3-2 P06MUXD5-4 P07MUXD7-6 P10MUXD1-0 P11MUXD3-2 P12MUXD5-4 P13MUXD7-6 P14MUXD1-0 P15MUXD3-2 P16MUXD5-4 P17MUXD7-6 P20MUXD1-0 P21MUXD3-2 P22MUXD5-4 P23MUXD7-6 P24MUXD1-0 P27MUXD7-6 P30MUXD1-0 P31MUXD3-2 P32MUXD5-4 P33MUXD7-6 P34MUXD1-0 P35MUXD3-2 P36MUXD5-4 P37MUXD7-6 P40MUXD1-0 P41MUXD3-2 P42MUXD5-4 P43MUXD7-6 Control register P0 Port Function Select (P0_PMUX) Register (0x52a0) P0 Port Function Select (P0_PMUX) Register (0x52a1) P1 Port Function Select (P1_PMUX) Register (0x52a2) P1 Port Function Select (P1_PMUX) Register (0x52a3) P2 Port Function Select (P2_PMUX) Register (0x52a4) P2 Port Function Select (P2_PMUX) Register (0x52a5) P3 Port Function Select (P3_PMUX) Register (0x52a6) P3 Port Function Select (P3_PMUX) Register (0x52a7) P4 Port Function Select (P4_PMUX) Register (0x52a8) Resetting the input/output port pins (Pxx) resets them to their default functions (pin function 1 in Table 10.2.1). P02, P13, P14, P15, P16 Pins can be used as external clock input pin of 16 bit timer by setting them to input mode. P17, P20, P21, P22 Pins are input only. For information on functions other than the input/output ports, refer to the discussion of the peripheral modules indicated in parentheses. The sections below discuss port functions with the pins set as general purpose input/output ports. 10-2 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 10 Input/Output Port (P) 10.3 Data Input/Output The input/output ports permit selection of the data input/output direction for each bit using PxOEN[7:0] (Px_OEN register) and PxIEN[7:0] (Px_IEN register). PxOEN[7:0] executes on/off control of data output, while PxIEN[7:0] executes on/off control of data input. P0OEN[7:0]: P0[7:0] Port Output Enable Bits in the P0 Port Output Enable (P0_OEM) Register (D[7:0]/0x5202) P1OEN[7:0]: P1[7:0] Port Output Enable Bits in the P1 Port Output Enable (P1_OEM) Register (D[7:0]/0x5212) P2OEN[7:0]: P2[7:0] Port Output Enable Bits in the P2 Port Output Enable (P2_OEM) Register (D[7:0]/0x5222) P3OEN[7:0]: P3[7:0] Port Output Enable Bits in the P3 Port Output Enable (P3_OEM) Register (D[7:0]/0x5232) P4OEN[3:0]: P4[3:0] Port Output Enable Bits in the P4 Port Output Enable (P4_OEM) Register (D[3:0]/0x5242) P0IEN[7:0]: P0[7:0] Port Input Enable Bits in the P0 Port Input Enable (P0_IEN) Register (D[7:0]/0x520a) P1IEN[7:0]: P1[7:0] Port Input Enable Bits in the P1 Port Input Enable (P1_IEN) Register (D[7:0]/0x521a) P2IEN[7:0]: P2[7:0] Port Input Enable Bits in the P2 Port Input Enable (P2_IEN) Register (D[7:0]/0x522a) P3IEN[7:0]: P3[7:0] Port Input Enable Bits in the P3 Port Input Enable (P3_IEN) Register (D[7:0]/0x523a) P4IEN[3:0]: P4[3:0] Port Input Enable Bits in the P4 Port Input Enable (P4_IEN) Register (D[3:0]/0x524a) Table 10.3.1: Data Input/Output list PxOEN[7:0] Output control PxIEN[7:0] Input control PxPU[7:0] Pull-up control 0 1 0 0 1 1 1 0 1 or 0 1 1 1 or 0 0 0 0 0 0 1 Port status Functions as input port (with pull-up off). Port pin (external input signal) value can be read from PxIN[7:0] (input data). Output is disabled. Functions as input port (with pull-up on). (Default) port pin (external input signal) value can be read from PxIN[7:0] (input data). Output is disabled. Functions as output port (with pull-up off). Input is disabled, and the value read from PxIN[7:0] (input data) is 0. Functions as output port (with pull-up off). Input is also enabled, and the port pin value (output value) can be read from PxIN[7:0] (input data). The pin is in high impedance state (with pull-up off), causing the I/O buffer to be in floating gate state. Therefore, this setting is prohibited. The pin is in high impedance state (with pull-up on). Output is disabled, and the value read from PxIN[7:0] (input data) is 0. The input/output direction for the port selecting the peripheral module function is controlled by the peripheral module. The PxIO[7:0] setting is ignored. Data input When set to input mode, PxIO[7:0] is set to 0 (default). The input/output port set to input mode switches to high-impedance state, and functions as the input port. If pull-up is enabled by the Px_PU register, the port will be pulled up. In input mode, the input pin state can be read out directly from PxIN[7:0] (Px_IN register). The value read will be 1 when the input pin is at High (VDD) level and 0 when it is at Low (VSS) level. P0IN[7:0]: P0[7:0] Port Input Data Bits in the P0 Port Input Data (P0_IN) Register (D[7:0]/0x5200) P1IN[7:0]: P1[7:0] Port Input Data Bits in the P1 Port Input Data (P1_IN) Register (D[7:0]/0x5210) P2IN[7:0]: P2[7:0] Port Input Data Bits in the P2 Port Input Data (P2_IN) Register (D[7:0]/0x5220) P3IN[7:0]: P3[7:0] Port Input Data Bits in the P3 Port Input Data (P3_IN) Register (D[7:0]/0x5230) P4IN[3:0]: P4[7:0] Port Input Data Bits in the P4 Port Input Data (P4_IN) Register (D[3:0]/0x5240) S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 10-3 10 Input/Output Port (P) Data output When set to output mode, PxOEN[7:0] is set to 1. The input/output port set to output mode functions as the output port, while the port pin outputs High (VDD) level if PxOUT[7:0] (Px_OUT register) is written as 1 and outputs Low (VSS) level if written as 0. Note that the port will not be pulled up in output mode even if pull-up is enabled by the Px_PU register. P0OUT[7:0]: P0[7:0] Port Output Data Bits in the P0 Port Output Data (P0_OUT) Register (D[7:0]/0x5201) P1OUT[7:0]: P1[7:0] Port Output Data Bits in the P1 Port Output Data (P1_OUT) Register (D[7:0]/0x5211) P2OUT[7:0]: P2[7:0] Port Output Data Bits in the P2 Port Output Data (P2_OUT) Register (D[7:0]/0x5221) P3OUT[7:0]: P3[7:0] Port Output Data Bits in the P3 Port Output Data (P3_OUT) Register (D[7:0]/0x5231) P4OUT[3:0]: P4[3:0] Port Output Data Bits in the P4 Port Output Data (P4_OUT) Register (D[3:0]/0x5241) Writing to PxOUT[7:0] is possible without affecting pin status, even in input mode. 10-4 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 10 Input/Output Port (P) 10.4 Pull-up Control The input/output port contains a pull-up resistor, which you can choose to use or not use individually for each bit using the PxPU[7:0] (Px_PU register). P0PU[7:0]: P0[7:0] Port Pull-up Enable Bits in the P0 Port Pull-up Control (P0_PU) Register (D[7:0]/0x5203) P1PU[7:0]: P1[7:0] Port Pull-up Enable Bits in the P1 Port Pull-up Control (P1_PU) Register (D[7:0]/0x5213) P2PU[7:0]: P2[7:0] Port Pull-up Enable Bits in the P2 Port Pull-up Control (P2_PU) Register (D[7:0]/0x5223) P3PU[7:0]: P3[7:0] Port Pull-up Enable Bits in the P3 Port Pull-up Control (P3_PU) Register (D[7:0]/0x5233) P4PU[3:0]: P4[3:0] Port Pull-up Enable Bits in the P4 Port Pull-up Control (P4_PU) Register (D[3:0]/0x5243) Setting PxPU[7:0] to 1 (default) enables the pull-up resistor and pulls up the port pin in input mode. It will not be pulled up if set to 0. The PxPU[7:0] setting is disabled in output mode, and the pin is not pulled up. Input/output ports that are not used should be set with pull-up enabled. This pull-up setting is also enabled for ports for which the peripheral module function has been selected. A delay will occur in the waveform rise-up depending on time constants such as pull-up resistance and pin load capacitance if the port pin is switched from Low level to High level by the internal pull-up resistor. Therefore, an appropriate wait time must be set for loading an input/output port. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 10-5 10 Input/Output Port (P) 10.5 P0 and P1 Port Chattering Filter Function The P0 and P1 port include a chattering filter circuit for key entry, which you can select to use or not use (and for which you can select a verification time if used) individually for the four P0[3:0] and P0[7:4], P1 [3:0], P1 [7:4] ports using PxCF1[2:0] (D[2:0]/Px_CHAT register), PxCF2[2:0] (D[6:4]/Px_CHAT register). * P0CF1[2:0]: P0[3:0] Chattering Filter Time Select Bits in the P0 Port Chattering Filter Control (P0_CHAT) Register (D[2:0]/0x5208) * P0CF2[2:0]: P0[7:4] Chattering Filter Time Select Bits in the P0 Port Chattering Filter Control (P0_CHAT) Register (D[6:4]/0x5208) * P1CF1[2:0]: P1[3:0] Chattering Filter Time Select Bits in the P1 Port Chattering Filter Control (P1_CHAT) Register (D[2:0]/0x5218) * P1CF2[2:0]: P1[7:4] Chattering Filter Time Select Bits in the P1 Port Chattering Filter Control (P1_CHAT) Register (D[6:4]/0x5218) Table 10.5.1: Chattering filter function settings PxCF1[2:0]/PxCF2[2:0] 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 Verification time * 16384/fPCLK (8ms) 8192/fPCLK (4ms) 4096/fPCLK (2ms) 2048/fPCLK (1ms) 1024/fPCLK (512s) 512/fPCLK (256s) 256/fPCLK (128s) No verification time (Off) (Default: 0x0, *when HSCLK = 2 MHz and PCLK = HSCLK) Note: * The chattering filter verification time refers to the maximum pulse width that can be filtered. Generating an input interrupt requires a minimum input time of the verification time and a maximum input time of twice the verification time. * Input interrupts will not be accepted for a transition into SLEEP mode with the chattering filter left on. The chattering filter should be set off (no verification time) before executing the slp instruction. * P0/P1 port interrupts must be blocked when Px_CHAT register (0x5208/0x5218) settings are being changed. Changing the setting while interrupts are permitted may generate inadvertent P0/P1 interrupts. * A phenomenon may occur in which the internal signal oscillates due to the time elapsed until the signal reaches the threshold value if the input signal rise-up/drop-off time is delayed. Since input interrupts will malfunction under these conditions, the input signal rise-up/dropoff time should normally be set to 25 ns or less. 10-6 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 10 Input/Output Port (P) 10.6 Port Input Interrupt Ports P0 and P1 include input interrupt functions. Select which of the 16 ports are to be used for interrupts based on requirements. You can also select whether interrupts are generated for either the rising edge or falling edge of input signals. Figure 10.6.1 illustrates the port input interrupt circuit configuration. Chattering filter PxCF1[2:0] Interrupt edge selection PxEDGE0 Interrupt enable PxIE0 Interrupt flag PxIF0 Px port interrupt request (to ITC) *** Px0 Px7 Chattering filter PxCF2[2:0] Interrupt edge selection PxEDGE7 Interrupt enable PxIE7 Interrupt flag PxIF7 Figure 10.6.1: Port input interrupt circuit configuration Interrupt port selection Select the port generating an interrupt using PxIE[7:0] (Px_IMSK register). P0IE[7:0]: P0[7:0] Port Interrupt Enable Bits in the P0 Port Interrupt Mask (P0_IMSK) Register (D[7:0]/0x5205) P1IE[7:0]: P1[7:0] Port Interrupt Enable Bits in the P1 Port Interrupt Mask (P1_IMSK) Register (D[7:0]/0x5215) Setting PxIE[7:0] to 1 enables interrupt generation by the corresponding port. Setting to 0 (default) disables interrupt generation. Interrupt edge selection Port input interrupts can be generated at either the rising edge or falling edge of the input signal. Select the edge used to generate interrupts using PxEDGE[7:0] (Px_EDGE register). P0EDGE[7:0]: P0[7:0] Port Interrupt Edge Select Bits in the P0 Port Interrupt Edge Select (P0_EDGE) Register (D[7:0]/0x5206) P1EDGE[7:0]: P1[7:0] Port Interrupt Edge Select Bits in the P1 Port Interrupt Edge Select (P1_EDGE) Register (D[7:0]/0x5216) Setting PxEDGE[7:0] to 1 generates port input interrupts at the input signal falling edge. Setting it to 0 (default) generates interrupts at the rising edge. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 10-7 10 Input/Output Port (P) Interrupt flags The ITC is able to accept interrupt requests for both P0 and P1 port interrupts, and the P port module contains interrupt flags PxIF[7:0] corresponding to the individual 16 ports to enable individual control of the 16 P0[7:0] and P1[7:0] port interrupts. PxIF[7:0] will be set to 1 at the specified edge (rising or falling edge) of the input signal. A P0 or P1 port interrupt request signal is also output to the ITC at the same time if the corresponding PxIE[7:0] is set to 1. Meeting the ITC and S1C17 core interrupt conditions generates an interrupt. P0IF[7:0]: P0[7:0] Port Interrupt Flags in the P0 Port Interrupt Flag (P0_IFLG) Register (D[7:0]/0x5207) P1IF[7:0]: P1[7:0] Port Interrupt Flags in the P1 Port Interrupt Flag (P1_IFLG) Register (D[7:0]/0x5217) PxIF[7:0] is reset by writing as 1. Note: * The P port module interrupt flag PxIF[7:0] must be reset within the interrupt processing routine following a port interrupt to prevent recurring interrupts. * To prevent generating unnecessary interrupts, reset the relevant PxIF[7:0] before permitting interrupts for the required port using PxIE[7:0] (Px_IMSK register). Interrupt vector The port interrupt vector numbers and vector addresses are as shown below. Table 10.6.1: Port interrupt vectors Port Vector number Vector address P0 P1 4 (0x04) 5 (0x05) TTBR + 0x10 TTBR + 0x14 Other interrupt settings The ITC allows the precedence of P0 and P1 port interrupts to be set between level 0 (default) and level 7. The PSR (S1C17 core internal processor status register) IE (interrupt enable) bit must be set to 1 to generate actual interrupts. For specific information on interrupt processing, see "6 Interrupt Controller (ITC)." 10-8 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 10 Input/Output Port (P) 10.7 Control Register Details Table 10.7.1: Input/output port control register list Address 0x5200 0x5201 0x5202 0x5203 0x5205 0x5206 0x5207 0x5208 0x5209 0x520a 0x5210 0x5211 0x5212 0x5213 0x5215 0x5216 0x5217 0x5218 0x521a 0x5220 0x5221 0x5222 0x5223 0x522a 0x5230 0x5231 0x5232 0x5233 0x523a 0x5240 0x5241 0x5242 0x5243 0x524a 0x52a0 0x52a1 0x52a2 0x52a3 0x52a4 0x52a5 0x52a6 0x52a7 0x52a8 Register name P0_IN P0_OUT P0_OEN P0_PU P0_IMSK P0_EDGE P0_IFLG P0_CHAT P0_KRST P0_IEN P1_IN P1_OUT P1_OEN P1_PU P1_IMSK P1_EDGE P1_IFLG P1_CHAT P1_IEN P2_IN P2_OUT P2_OEN P2_PU P2_IEN P3_IN P3_OUT P3_OEN P3_PU P3_IEN P4_IN P4_OUT P4_OEN P4_PU P4_IEN P0_PMUX P0_PMUX P1_PMUX P1_PMUX P2_PMUX P2_PMUX P3_PMUX P3_PMUX P4_PMUX Function P0 Port Input Data Register P0 Port Output Data Register P0 Port Output Enable Register P0 Port Pull-up Control Register P0 Port Interrupt Mask Register P0 Port Interrupt Edge Select Register P0 Port Interrupt Flag Register P0 Port Chattering Filter Control Register P0 Port Key-Entry Reset Configuration Register P0 Port Input Enable Register P1 Port Input Data Register P1 Port Output Data Register P1 Port Output Enable Register P1 Port Pull-up Control Register P1 Port Interrupt Mask Register P1 Port Interrupt Edge Select Register P1 Port Interrupt Flag Register P1 Port Chattering Filter Control Register P1 Port Input Enable Register P2 Port Input Data Register P2 Port Output Data Register P2 Port Output Enable Register P2 Port Pull-up Control Register P2 Port Input Enable Register P3 Port Input Data Register P3 Port Output Data Register P3 Port Output Enable Register P3 Port Pull-up Control Register P3 Port Input Enable Register P4 Port Input Data Register P4 Port Output Data Register P4 Port Output Enable Register P4 Port Pull-up Enable Register P4 Port Input Enable Register P0 Port Function Select Register P0 Port Function Select Register P1 Port Function Select Register P1 Port Function Select Register P2 Port Function Select Register P2 Port Function Select Register P3 Port Function Select Register P3 Port Function Select Register P4 Port Function Select Register P0 port input data P0 port output data P0 port output enable P0 port pull-up control P0 port interrupt mask setting P0 port interrupt edge selection P0 port interrupt occurrence status display/reset P0 port chattering filter control P0 port key entry reset setting P0 port input enable P1 port input data P1 port output data P1 port output enable P1 port pull-up control P1 port interrupt mask setting P1 port interrupt edge selection P1 port interrupt occurrence status display/reset P1 port chattering filter control P1 port input enable P2 port input data P2 port output data P2 port output enable P2 port pull-up control P2 port input enable P3 port input data P3 port output data P3 port output enable P3 port pull-up control P3 port input enable P4 port input data P4 port output data P4 port output enable P4 port pull-up control enable P4 port input enable P0 port function selection P0 port function selection P1 port function selection P1 port function selection P2 port function selection P2 port function selection P3 port function selection P3 port function selection P4 port function selection The input/output port registers are described in detail below. These are 8-bit registers. Note: When data is written to the registers, the "Reserved" bits must always be written as 0 and not 1. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 10-9 10 Input/Output Port (P) 0x5200/0x5210/0x5220/0x5230/0X5240: Px Port Input Data Registers (Px_IN) Name Function P0 Port Input Data Register (P0_IN) Register name Address 0x5200 (8 bits) D7-0 P0IN[7:0] Bit P0[7:0] port input data 1 1 (H) Setting 0 0 (L) x R P1 Port Input Data Register (P1_IN) 0x5210 (8 bits) D7-0 P1IN[7:0] P1[7:0] port input data 1 1 (H) 0 0 (L) x R P2 Port Input Data Register (P2_IN) 0x5220 (8 bits) D7-0 P2IN[7:0] P2[7:0] port input data 1 1 (H) 0 0 (L) x R P3 Port Input Data Register (P3_IN) 0x5230 (8 bits) D7-0 P3IN[7:0] P3[7:0] port input data 1 1 (H) 0 0 (L) x R P4 Port Input Data Register (P4_IN) 0x5240 (8 bits) D7-4 - D3-0 P4IN[3:0] reserved P4[3:0] port input data 1 1 (H) 0 0 (L) - x - R - Init. R/W Remarks P25, P26 : 0 when being read. x when being read. Note: The "x" in the bit names indicates the port number (0 to 4). D[7:0] PxIN[7:0]: Px[7:0] Port Input Data Bits (P4 port is P4IN[3:0]) Read out the P port pin status. (Default: external pin status) 1(R): High level 0(R): Low level PxIN[7:0] correspond directly to the Px[7:0] pins and read the pin voltage level regardless of input/ output mode. 1 is read when the pin voltage is High; 0 is read when the voltage is Low. Writing operations to the read-only PxIN[7:0] are disabled. The read-out value of P2IN[6:5] is fixed to 0. 10-10 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 10 Input/Output Port (P) 0x5201/0x5211/0x5221/0x5231/0X5241: Px Port Output Data Registers (Px_OUT) Register name Address Bit Name Function Setting Init. R/W Remarks P0 Port Output Data Register (P0_OUT) 0x5201 (8 bits) D7-0 P0OUT[7:0] P0[7:0] port output data 1 1 (H) 0 0 (L) 0 R/W P1 Port Output Data Register (P1_OUT) 0x5211 (8 bits) D7-0 P1OUT[7:0] P1[7:0] port output data 1 1 (H) 0 0 (L) 0 R/W P2 Port Output Data Register (P2_OUT) 0x5221 (8 bits) D7-0 P2OUT[7:0] P2[7:0] port output data 1 1 (H) 0 0 (L) 0 R/W P3 Port Output Data Register (P3_OUT) 0x5231 (8 bits) D7-0 P3OUT[7:0] P3[7:0] port output data 1 1 (H) 0 0 (L) 0 R/W P4 Port Output Data Register (P4_OUT) 0x5241 (8 bits) D7-4 - reserved D3-0 P4OUT[3:0] P4[3:0] port output data 1 1 (H) 0 0 (L) - 0 - 0 when being read. R/W - Note: The "x" in the bit names indicates the port number (0 to 4). D[7:0] PxOUT[7:0]: Px[7:0] Port Output Data Bits (P4 port is P4OUT[3:0]) Set the data to be output from the port pin. 1(R/W): High level 0(R/W): Low level (default) PxOUT[7:0] correspond directly to the Px[7:0] pins and output data from the port pin as written. Setting the data bit to 1 sets the port pin to High; setting it to 0 sets it to Low. Port data can also be written in input mode. The P25 and P26 pins are not present. Settings onto the register are therefore disabled. The P17, and P20 to P22 pins are assigned exclusively for input. Settings onto the register are therefore disabled. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 10-11 10 Input/Output Port (P) 0x5202/0x5212/0x5222/0x5232/0x5242: Px Port Output Enable Registers (Px_OEN) Register name Address Bit Name Function Setting Init. R/W Remarks P0 Port Output Enable Register (P0_OEN) 0x5202 (8 bits) D7-0 P0OEN[7:0] P0[7:0] port output enable select 1 Output Enable 0 Output Disable 0 R/W P1 Port Output Enable Register (P1_OEN) 0x5212 (8 bits) D7-0 P1OEN[7:0] P1[7:0] port output enable select 1 Output Enable 0 Output Disable 0 R/W P2 Port Output Enable Register (P2_OEN) 0x5222 (8 bits) D7-0 P2OEN[7:0] P2[7:0] port output enable select 1 Output Enable 0 Output Disable 0 R/W P3 Port Output Enable Register (P3_OEN) 0x5232 (8 bits) D7-0 P3OEN[7:0] P3[7:0] port output enable select 1 Output Enable 0 Output Disable 0 R/W P4 Port Output Enable Register (P4_OEN) 0x5242 (8 bits) D7-4 - reserved D3-0 P4OEN[3:0] P4[3:0] port output enable select - 0 - 0 when being read. R/W - 1 Output Enable 0 Output Disable Note: The "x" in the bit names indicates the port number (0 to 3). D[7:0] PxIO[7:0]: Px[7:0] Port Output Enable Select Bits (P3 port is P3IN[3:0]) Set Port Output to enable/disable 1(R/W): Enable 0(R/W): Disable (default) PxIO[7:0] are the output enable bits corresponding directly to the Px[7:0] ports. Setting to 1 selects output mode, while setting to 0 selects high inpedence. The peripheral module function determines the input/output direction for when a pin is used for peripheral modules. For the input/output control by each register, refer to "Table 10.3.1 Data input/output list." The P25 and P26 pins are not present. Settings onto the register are therefore disabled. The P17, and P20 to P22 pins are assigned exclusively for input. Settings onto the register are therefore disabled. 10-12 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 10 Input/Output Port (P) 0x5203/0x5213/0x5223/0x5233/0x5234: Px Port Pull-up Control Registers (Px_PU) Register name Address Bit Name Function Setting Init. R/W P0 Port Pull-up 0x5203 Control Register (8 bits) (P0_PU) D7-0 P0PU[7:0] P0[7:0] port pull-up enable 1 Enable 0 Disable 1 R/W (0xff) P1 Port Pull-up 0x5213 Control Register (8 bits) (P1_PU) D7-0 P1PU[7:0] P1[7:0] port pull-up enable 1 Enable 0 Disable 1 R/W (0xff) P2 Port Pull-up 0x5223 Control Register (8 bits) (P2_PU) D7-0 P2PU[7:0] P2[7:0] port pull-up enable 1 Enable 0 Disable 1 R/W (0xff) P3 Port Pull-up 0x5233 Control Register (8 bits) (P3_PU) D7-0 P3PU[7:0] P3[7:0] port pull-up enable 1 Enable 0 Disable 1 R/W (0xff) P4 Port Pull-up 0x5243 Control Register (8 bits) (P4_PU) D7-4 - D3-0 P4PU[3:0] reserved P4[3:0] port pull-up enable 1 Enable - 0 Disable Remarks - - 1 when being read. 1 R/W (0xff) Note: The "x" in the bit names indicates the port number (0 to 4). D[7:0] PxPU[7:0]: Px[7:0] Port Pull-up Enable Bits (P4 port is P4PU[3:0]) Enable or disable the pull-up resistor included in each port. 1 (R/W): Enabled (default) 0 (R/W): Disabled PxPU[7:0] are the pull-up control bits that correspond directly to the Px[7:0] ports. Setting to 1 enables the pull-up resistor and pulls up the port pin in input mode. It will not be pulled up if set to 0. The PxPU[7:0] setting is disabled in output mode, and the pin is not pulled up. Input/output ports that are not used should be set with pull-up enabled. This pull-up setting is also enabled for ports for which the peripheral module function has been selected. A delay will occur in the waveform rise-up depending on time constants such as pull-up resistance and pin load capacitance if the port pin is switched from Low level to High level by the internal pull-up resistor. Therefore, an appropriate wait time must be set for loading an input/output port. The P25 and P26 pins are not present. Settings onto the register are therefore disabled. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 10-13 10 Input/Output Port (P) 0x5205/5215: Px Port Interrupt Mask Registers (Px_IMSK) Register name Address Bit Name Function Setting Init. R/W P0 Port Interrupt Mask Register (P0_IMSK) 0x5205 (8 bits) D7-0 P0IE[7:0] P0[7:0] port interrupt enable 1 Enable 0 Disable 0 R/W P1 Port Interrupt Mask Register (P1_IMSK) 0x5215 (8 bits) D7-0 P1IE[7:0] P1[7:0] port interrupt enable 1 Enable 0 Disable 0 R/W Remarks Note: The "x" in the bit names indicates the port number (0 or 1). D[7:0] PxIE[7:0]: Px[7:0] Port Interrupt Enable Bits Permit or prohibit P0[7:0] and P1[7:0] port interrupt. 1 (R/W): Interrupt permitted 0 (R/W): Interrupt prohibited (default) Setting PxIE[7:0] to 1 permits the corresponding interrupt, while setting to 0 blocks interrupts. Status changes for the input pin with interrupt blocked do not affect interrupt occurrence. 10-14 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 10 Input/Output Port (P) 0x5206/5216: Px Port Interrupt Edge Select Registers (Px_EDGE) Register name Address Bit 0x5206 P0 Port (8 bits) Interrupt Edge Select Register (P0_EDGE) D7-0 P0EDGE[7:0] P0[7:0] port interrupt edge select Name Function 1 Falling edge 0 Rising edge Setting Init. R/W 0 R/W 0x5216 P1 Port (8 bits) Interrupt Edge Select Register (P1_EDGE) D7-0 P1EDGE[7:0] P1[7:0] port interrupt edge select 1 Falling edge 0 Rising edge 0 R/W Remarks Note: The "x" in the bit names indicates the port number (0 or 1). D[7:0] PxEDGE[7:0]: Px[7:0] Port Interrupt Edge Select Bits Select the input signal edge for generating P0[7:0] and P1[7:0] port interrupts. 1 (R/W): Falling edge 0 (R/W): Rising edge (default) Port interrupts are generated at the input signal falling edge if PxEDGE[7:0] are set to 1 and at the rising edge if set to 0. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 10-15 10 Input/Output Port (P) 0x5207/5217: Px Port Interrupt Flag Registers (Px_IFLG) Register name Address Bit Name Function Setting Init. R/W Remarks P0 Port Interrupt Flag Register (P0_IFLG) 0x5207 (8 bits) D7-0 P0IF[7:0] P0[7:0] port interrupt flag 1 Cause of interrupt occurred 0 Cause of interrupt not occurred 0 R/W Reset by writing 1. P1 Port Interrupt Flag Register (P1_IFLG) 0x5217 (8 bits) D7-0 P1IF[7:0] P1[7:0] port interrupt flag 1 Cause of interrupt occurred 0 Cause of interrupt not occurred 0 R/W Reset by writing 1. Note: The "x" in the bit names indicates the port number (0 or 1). D[7:0] PxIF[7:0]: Px[7:0] Port Interrupt Flags These are interrupt flags indicating the interrupt factor occurrence status. 1(R): Interrupt factor present 0(R): No interrupt factor (default) 1(W): Reset flag 0(W): Disabled PxIF[7:0] are interrupt flags corresponding to the individual 16 ports of P0[7:0] and P1[7:0]. PxIF[7:0] will be set to 1 at the specified edge (rising or falling edge) of the input signal. A P0 or P1 port interrupt request signal is also output to the ITC at the same time if the corresponding PxIE[7:0] is set to 1. This interrupt request signal causes the P0/P1 port interrupt flag inside the ITC to be set to 1. Meeting the ITC and S1C17 core interrupt conditions generates an interrupt. PxIF[7:0] is reset by writing as 1. Note: * The P port module interrupt flag PxIF[7:0] must be reset within the interrupt processing routine following a port interrupt to prevent recurring interrupts. * To prevent genarating unnecessary interrupts, reset the relevant PxIF[7:0] before permitting interrupts for the required port using PxIE[7:0] (Px_IMSK register). P0IE[7:0]: P0[7:0] Port Interrupt Enable Bits in the P0 Port Interrupt Mask (P0_IMSK) Register (D[7:0]/0x5205) P1IE[7:0]: P1[7:0] Port Interrupt Enable Bits in the P1 Port Interrupt Mask (P1_IMSK) Register (D[7:0]/0x5215) 10-16 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 10 Input/Output Port (P) 0x5208/0x5218: Px Port Chattering Filter Control Register (Px_CHAT) Register name Address P0 Port Chattering Filter Control Register (P0_CHAT) 0x5208 (8 bits) Bit Name Function - D7 reserved D6-4 P0CF2[2:0] P0[7:4] chattering filter time select - D3 reserved D2-0 P0CF1[2:0] P0[3:0] chattering filter time select P1 Port Chattering Filter Control Register (P1_CHAT) 0x5218 (8 bits) - D7 reserved D6-4 P1CF2[2:0] P1[7:4] chattering filter time select - D3 reserved D2-0 P1CF1[2:0] P1[3:0] chattering filter time select Setting - P0CF2[2:0] 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 Filter time 16384/fPCLK 8192/fPCLK 4096/fPCLK 2048/fPCLK 1024/fPCLK 512/fPCLK 256/fPCLK None - P0CF1[2:0] 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 Filter time 16384/fPCLK 8192/fPCLK 4096/fPCLK 2048/fPCLK 1024/fPCLK 512/fPCLK 256/fPCLK None - P0CF2[2:0] 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 Filter time 16384/fPCLK 8192/fPCLK 4096/fPCLK 2048/fPCLK 1024/fPCLK 512/fPCLK 256/fPCLK None - P0CF1[2:0] 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 Filter time 16384/fPCLK 8192/fPCLK 4096/fPCLK 2048/fPCLK 1024/fPCLK 512/fPCLK 256/fPCLK None Init. R/W Remarks - - 0 when being read. 0 R/W 0x0 R/W - - 0 when being read. 0x0 R/W - - 0 when being read. 0 R/W 0x0 R/W - - 0 when being read. 0x0 R/W Note: The "x" in the bit names indicates the port number (0 or 1). D7 Reserved D[6:4] PxCF2[2:0]: Px[7:4] Chattering Filter Time Select Bits Set the chattering filter circuit included in the P0[7:4] or P1[7:4] ports. D3 Reserved D[2:0] PxCF1[2:0]: Px[3:0] Chattering Filter Time Select Bits Set the chattering filter circuit included in the P0[3:0] or P1[3:0]ports. The P0 or P1 port includes a chattering filter circuit for key entry or port interrupt. You can select whether to use this function respectively for P0[3:0], P0[7:4], P1[3:0] and P1[7:4] ports using PxCF1/2[2:0]. You can also select relevant verification time accordingly. Table 10.7.2: Chattering filter function settings PxCF1[2:0], PxCF2[2:0] Verification time * 0x7 16384/fPCLK (8ms) 0x6 8192/fPCLK (4ms) 0x5 4096/fPCLK (2ms) 0x4 2048/fPCLK (1ms) 0x3 1024/fPCLK (512s) 0x2 512/fPCLK (256s) 0x1 256/fPCLK (128s) No verification time (Off) 0x0 (Default: 0x0, *when OSC3 = 2 MHz and PCLK = OSC3) S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 10-17 10 Input/Output Port (P) Note: * The chattering filter verification time refers to the maximum pulse width that can be filtered. Generating an input interrupt requires a minimum input time of the verification time and a maximum input time of twice the verification time. * Input interrupts will not be accepted for a transition into SLEEP mode with the chattering filter left on. The chattering filter should be set off (no verification time) before executing the slp instruction. * P0/P1 port interrupts must be blocked when Px_CHAT register settings are being changed. Changing the setting while interrupts are permitted may generate inadvertent P0/P1 interrupts. * A phenomenon may occur in which the internal signal oscillates due to the time elapsed until the signal reaches the threshold value if the input signal rise-up/drop-off time is delayed. Since input interrupts will malfunction under these conditions, the input signal rise-up/drop-off time should normally be set to 25 ns or less. 10-18 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 10 Input/Output Port (P) 0x5209: P0 Port Key-Entry Reset Configuration Register (P0_KRST) Register name Address P0 Port KeyEntry Reset Configuration Register (P0_KRST) 0x5209 (8 bits) Bit D7-2 D1-0 Name Function - reserved P0KRST[1:0] P0 port key-entry reset configuration Setting - P0KRST[1:0] 0x3 0x2 0x1 0x0 D[7:2] Reserved D[1:0] P0KRST[1:0]: P0 Port Key-Entry Reset Configuration Bits Select the port combination used for P0 port key entry resetting. Configuration P0[3:0] = 0 P0[2:0] = 0 P0[1:0] = 0 Disable Init. R/W Remarks - - 0 when being read. 0x0 R/W Table 10.7.3: P0 port key entry input reset settings P0KRST[1:0] 0x3 0x2 0x1 0x0 Ports used P00, P01, P02, P03 P00, P01, P02 P00, P01 Not used (Default: 0x0) The key entry reset function performs an initial reset by inputting Low level simultaneously from externally to the port selected here. For example, if P0KRST[1:0] is set to 0x3, an initial reset is performed when the four ports P00 to P03 are simultaneously set to Low level. Set P0KRST[1:0] to 0x0 when this reset function is not used. Note: * Make sure the specified ports are not simultaneously switched to Low during normal operations when using the P0 port key-entry reset function. * The P0 port key entry reset function is disabled on initial resetting and cannot be used for resetting at power-on. * The P0 port key-entry reset function cannot be used in SLEEP state. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 10-19 10 Input/Output Port (P) 0x520a/0x521a/0x522a/0x523a/0x524a: Px Port Input Enable Registers (Px_IEN) Register name Address Bit Name Function Setting Init. R/W Remarks 0x520a P0 Port Input Enable Register (8 bits) (P0_IEN) D7-0 P0IEN[7:0] P0[7:0] port input enable 1 Enable 0 Disable 0xff R/W 0x521a P1 Port Input Enable Register (8 bits) (P1_IEN) D7-0 P1IEN[7:0] P1[7:0] port input enable 1 Enable 0 Disable 0xff R/W 0x522a P2 Port Input Enable Register (8 bits) (P2_IEN) D7-0 P2IEN[7:0] P2[7:0] port input enable 1 Enable 0 Disable 0xff R/W 0x523a P3 Port Input Enable Register (8 bits) (P3_IEN) D7-0 P3IEN[7:0] P3[7:0] port input enable 1 Enable 0 Disable 0xff R/W 0x524a P4 Port Input Enable Register (8 bits) (P4_IEN) D7-4 - reserved D3-0 P4IEN[3:0] P4[3:0] port input enable 1 Enable 0 Disable - - 1 when being read. 0xff R/W - Note: The "x" in the bit names indicates the port number (0 to 4). D[7:0] PxIEN[7:0]: Px[7:0] Port Input Enable Bits (P4 port is P4IEN[3:0]) Permits or prevents port input. 1(R/W): Permit (Default) 0(R/W): Prohibit PxIEN[7:0] are input enable bits that correspond directly to the Px[7:0] ports. Setting to 1 enables the input signal level to be read from the Px_IN register, while setting to 0 prevents signal input and fixes the input data values read out to 0. 10-20 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 10 Input/Output Port (P) 0x52a0: P0 Port Function Select Register (P0_PMUX) Register name Address 0x52a0 P0 Port Function Select (8 bits) Register (P0_PMUX) Bit Name D7 D6 D5 D4 D3 D2 D1 D0 - P03MUX - P02MUX - P01MUX - P00MUX Function reserved P03 port function select reserved P02 port function select reserved P01 port function select reserved P00 port function select Setting - 1 #ADTRG 0 P03 - 1 Reserved 0 P02/EXCL0 - 1 REMI 0 P01 - 1 REMO 0 P00 Init. R/W - 0 - 0 - 0 - 0 - R/W - R/W - R/W - R/W Remarks 0 when being read. 0 when being read. 0 when being read. 0 when being read. The P00 to P03 input/output port pins are shared with the peripheral module pins. This register is used to select how the pins are used. D7 Reserved D6 P03MUX: P03 Port Function Select Bit 1 (R/W): #ADTRGADC10SA 0 (R/W): P03 port (default) D5 Reserved D4 P02MUX: P02 Port Function Select Bit 1 (R/W): Reserved 0 (R/W): P02 port / EXCL0 (T16 Ch. 0) (default) *For EXCL0, input status can be selected as PxOEN[7:0]=0, PxIEN=1. D3 Reserved D2 P01MUX: P01 Port Function Select Bit 1 (R/W): REMI (REMC) 0 (R/W): P01 port (default) D1 Reserved D0 P00MUX: P00 Port Function Select Bit 1 (R/W): REMO (REMC) 0 (R/W): P00 port (default) S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 10-21 10 Input/Output Port (P) 0x52a1: P0 Port Function Select Register (P0_PMUX) Register name Address 0x52a1 P0 Port Function Select (8 bits) Register (P0_PMUX) Bit Name D7 D6 D5 D4 D3 D2 D1 D0 - P07MUX - P06MUX - P05MUX - P04MUX Function reserved P07 port function select reserved P06 port function select reserved P05 port function select reserved P04 port function select Setting - 1 #SPISS 0 P07 - 1 SDI 0 P06 - 1 SDO 0 P05 - 1 SPICLK 0 P04 Init. R/W - 0 - 0 - 0 - 0 - R/W - R/W - R/W - R/W Remarks 0 when being read. 0 when being read. 0 when being read. 0 when being read. The P04 to P07 input/output port pins are shared with the peripheral module pins. This register is used to select how the pins are used. D7 Reserved D6 P07MUX: P07 Port Function Select Bit 1 (R/W): #SPISSSPI slave 0 (R/W): P07 port (default) D5 Reserved D4 P06MUX: P06 Port Function Select Bit 1 (R/W): SDI (SPI) 0 (R/W): P06 port (default) D3 Reserved D2 P05MUX: P05 Port Function Select Bit 1 (R/W): SDO (SPI) 0 (R/W): P05 port (default) D1 Reserved D0 P04MUX: P04 Port Function Select Bit 1 (R/W): SPICLK (REMC) 0 (R/W): P04 port (default) 10-22 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 10 Input/Output Port (P) 0x52a2: P1 Port Function Select Register (P1_PMUX) Register name Address 0x52a2 P1 Port Function Select (8 bits) Register (P1_PMUX) Bit Name Function D7-6 P13MUX [1:0] P13 port function select D5 D4 D3 D2 D1 D0 - P12MUX - P11MUX - P10MUX reserved P12 port function select reserved P11 port function select reserved P10 port function select Setting P13MUX[1:0] 0x3 0x2 0x1 0x0 Port Reserved Reserved Reserved P13/EXCL1 - 1 SIN 0 P12 - 1 SOUT 0 P11 - 1 SCLK 0 P10 Init. R/W Remarks 0 R/W - 0 - 0 - 0 - 0 when being read. R/W - 0 when being read. R/W - 0 when being read. R/W The P10 to P13 input/output port pins are shared with the peripheral module pins. This register is used to select how the pins are used. D[7:6] P13MUX: P13 Port Function Select Bit 0x3 (R/W): Reserved 0x2 (R/W): Reserved 0x1 (R/W): Reserved 0x0 (R/W): P13 port / EXCL1 (T16 Ch.1) (default) *For EXCL1, input status can be selected as PxOEN[7:0]=0, PxIEN=1. D5 Reserved D4 P12MUX: P12 Port Function Select Bit 1 (R/W): SIN (UART Ch.0) 0 (R/W): P12 port (default) D3 Reserved D2 P11MUX: P11 Port Function Select Bit 1 (R/W): SOUT (UART Ch.0) 0 (R/W): P11 port (default) D1 Reserved D0 P10MUX: P10 Port Function Select Bit 1 (R/W): SCLK (UART Ch.0) 0 (R/W): P10 port (default) S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 10-23 10 Input/Output Port (P) 0x52a3: P1 Port Function Select Register (P1_PMUX) Register name Address 0x52a3 P1 Port Function Select (8 bits) Register (P1_PMUX) Bit Name Function D7 D6 D5-4 - P17MUX P16MUX [1:0] reserved P17 port function select P16 port function select D3-2 P15MUX [1:0] P15 port function select D1-0 P14MUX [1:0] P14 port function select Setting Init. R/W - 1 AIN3 0 P17 P16MUX[1:0] Port Reserved 0x3 Reserved 0x2 SCLK1 0x1 P16/EXCL4 0x0 P15MUX[1:0] Port Reserved 0x3 Reserved 0x2 Reserved 0x1 P15/EXCL3 0x0 P14MUX[1:0] Port Reserved 0x3 Reserved 0x2 Reserved 0x1 P14/EXCL2 0x0 Remarks - 0 0 - 0 when being read. R/W R/W 0 R/W 0 R/W The P14 to P17 input/output port pins are shared with the peripheral module pins. This register is used to select how the pins are used. D7 Reserved D6 P17MUX: P17 Port Function Select Bit 1 (R/W): AIN3 (ADC10SA Ch.3) 0 (R/W): P17 port (default) D[5:4] P16MUX[1:0]: P16 Port Function Select Bit 0x3 (R/W): Reserved 0x2 (R/W): Reserved 0x1 (R/W): SCLK1 (UART Ch.1) 0x0 (R/W): P16 port (default) D[3:2] P15MUX[1:0]: P15 Port Function Select Bit 0x3 (R/W): Reserved 0x2 (R/W): Reserved 0x1 (R/W): Reserved 0x0 (R/W): P15 port / EXCL3 (T16E Ch.0) (default) *For EXCL3, input status can be selected as PxOEN[7:0]=0, PxIEN=1. D[1:0] P14MUX[1:0]: P14 Port Function Select Bit 0x3 (R/W): Reserved 0x2 (R/W): Reserved 0x1 (R/W): Reserved 0x0 (R/W): P14 port / EXCL2 (T16 Ch.2) (default) *For EXCL2, input status can be selected as PxOEN[7:0]=0, PxIEN=1. 10-24 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 10 Input/Output Port (P) 0x52a4: P2 Port Function Select Register (P2_PMUX) Register name Address 0x52a4 P2 Port Function Select (8 bits) Register (P2_PMUX) Bit Name D7 D6 D5 D4 D3 D2 D1 D0 - P23MUX - P22MUX - P21MUX - P20MUX Function reserved P23 port function select reserved P22 port function select reserved P21 port function select reserved P20 port function select Setting - 1 SENB0 0 P23 - 1 AIN0 0 P22 - 1 AIN1 0 P21 - 1 AIN2 0 P20 Init. R/W - 0 - 0 - 0 - 0 - R/W - R/W - R/W - R/W Remarks 0 when being read. 0 when being read. 0 when being read. 0 when being read. The P20 to P23 input/output port pins are shared with the peripheral module pins. This register is used to select how the pins are used. D7 Reserved D6 P23MUX: P23 Port Function Select Bit 1 (R/W): Reserved 0 (R/W): P23 port (default) D5 Reserved D4 P22MUX: P22 Port Function Select Bit 1 (R/W): AIN0 (ADC Ch.0) 0 (R/W): P22 port (default) D3 Reserved D2 P21MUX: P21 Port Function Select Bit 1 (R/W): AIN1 (ADC Ch.1) 0 (R/W): P21 port (default) D1 Reserved D0 P20MUX: P20 Port Function Select Bit 1 (R/W): AIN2 (ADC Ch.2) 0 (R/W): P20 port (default) S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 10-25 10 Input/Output Port (P) 0x52a5: P2 Port Function Select Register (P2_PMUX) Register name Address 0x52a5 P2 Port Function Select (8 bits) Register (P2_PMUX) Bit Name Function D7-6 P27MUX [1:0] P27 port function select D5-1 D0 - P24MUX reserved P24 port function select Setting P27MUX[1:0] 0x3 0x2 0x1 0x0 - 1 SENA0 Init. R/W Port Reserved Reserved SOUT1 P27 0 P24 Remarks 0 R/W - 0 - 0 when being read. R/W The P24 to P27 input/output port pins are shared with the peripheral module pins. This register is used to select how the pins are used. D[7:6] P27MUX[1:0]: P27 Port Function Select Bit 0x3 (R/W): Reserved 0x2 (R/W): Reserved 0x1 (R/W): SOUT1 (UART Ch.1) 0x0 (R/W): P27 port (default) D[5:1] Reserved D0 P24MUX: P24 Port Function Select Bit 1 (R/W): Reserved 0 (R/W): P24 port (default) 10-26 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 10 Input/Output Port (P) 0x52a6: P3 Port Function Select Register (P3_PMUX) Register name Address 0x52a6 P3 Port Function Select (8 bits) Register (P3_PMUX) Bit Name Function D7-6 P33MUX [1:0] P33 port function select D5-4 P32MUX [1:0] P32 port function select D3-2 P31MUX [1:0] P31 port function select D1-0 P30MUX [1:0] P30 port function select Setting P33MUX[1:0] 0x3 0x2 0x1 0x0 P32MUX[1:0] 0x3 0x2 0x1 0x0 P31MUX[1:0] 0x3 0x2 0x1 0x0 P30MUX[1:0] 0x3 0x2 0x1 0x0 Port Reserved SCL0 SCL1 P33 Port Reserved Reserved SDA0 P32 Port Reserved Reserved SCL0 P31 Port Reserved Reserved SIN1 (UART) P30 Init. R/W 0 R/W 0 R/W 0 R/W 0 R/W Remarks The P30 to P33 input/output port pins are shared with the peripheral module pins. This register is used to select how the pins are used. D[7:6] P33MUX: P33 Port Function Select Bit 0x3 (R/W): Reserved 0x2 (R/W): SCL0 (I2C master) 0x1 (R/W): SCL1 (I2C slave) 0x0 (R/W): P33 port (default) D[5:4] P32MUX: P32 Port Function Select Bit 0x3 (R/W): Reserved 0x2 (R/W): Reserved 0x1 (R/W): SDA0 (I2C master) 0x0 (R/W): P32 port (default) D[3:2] P31MUX: P31 Port Function Select Bit 0x3 (R/W): Reserved 0x2 (R/W): Reserved 0x1 (R/W): SCL0 (I2C master) 0x0 (R/W): P31 port (default) D[1:0] P34MUX: P34 Port Function Select Bit 0x3 (R/W): Reserved 0x2 (R/W): Reserved 0x1 (R/W): SIN1 (UART Ch.1) 0x0 (R/W): P30 port (default) S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 10-27 10 Input/Output Port (P) 0x52a7: P3 Port Function Select Register (P3_PMUX) Register name Address 0x52a7 P3 Port Function Select (8 bits) Register (P3_PMUX) Bit Name Function D7-6 P37MUX [1:0] P37 port function select D5-4 P36MUX [1:0] P36 port function select D3-2 P35MUX [1:0] P35 port function select D1-0 P34MUX [1:0] P34 port function select Setting P37MUX[1:0] 0x3 0x2 0x1 0x0 P36MUX[1:0] 0x3 0x2 0x1 0x0 P35MUX[1:0] 0x3 0x2 0x1 0x0 P34MUX[1:0] 0x3 0x2 0x1 0x0 Init. R/W Port TOUT4 Reserved TOUTN3 P37 Port Reserved Reserved TOUT3 P36 Port Reserved #BFR FOUT1 P35 Port Reserved SDA0 SDA1 P34 0 R/W 0 R/W 0 R/W 0 R/W Remarks The P34 to P37 input/output port pins are shared with the peripheral module pins. This register is used to select how the pins are used. D[7:6] P37MUX: P37 Port Function Select Bit 0x3 (R/W): TOUT4 (T8OSC1) 0x2 (R/W): Reserved 0x1 (R/W): TOUTN3 (T16E Ch.0) 0x0 (R/W): P37 port (default) D[5:4] P36MUX: P36 Port Function Select Bit 0x3 (R/W): Reserved 0x2 (R/W): Reserved 0x1 (R/W): TOUT3 (T16E Ch.0) 0x0 (R/W): P36 port (default) D[3:2] P31MUX: P31 Port Function Select Bit 0x3 (R/W): Reserved 0x2 (R/W): #BFR (I2C slave) 0x1 (R/W): FOUT1 (OSC1) 0x0 (R/W): P35 port (default) D[1:0] P34MUX: P34 Port Function Select Bit 0x3 (R/W): Reserved 0x2 (R/W): SDA0 (I2C master) 0x1 (R/W): SDA1 (I2C slave) 0x0 (R/W): P34 port (default) 10-28 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 10 Input/Output Port (P) 0x52a8: P4 Port Function Select Register (P4_PMUX) Register name Address 0x52a8 P4 Port Function Select (8 bits) Register (P4_PMUX) Bit Name D7 D6 D5 D4 D3 D2 D1 D0 - P43MUX - P42MUX - P41MUX - P40MUX Function reserved P43 port function select reserved P42 port function select reserved P41 port function select reserved P40 port function select Setting - 1 P43 0 DCLK - 1 P42 0 DST2 - 1 P41 0 DSIO - 1 FOUTH 0 P40 Init. R/W - 0 - 0 - 0 - 0 - R/W - R/W - R/W - R/W Remarks 0 when being read. 0 when being read. 0 when being read. 0 when being read. The P40 to P43 input/output port pins are shared with the peripheral module pins. This register is used to select how the pins are used. D7 Reserved D6 P43MUX: P43 Port Function Select Bit 1 (R/W): P43 port 0 (R/W): DCLK (DBG) (default) D5 Reserved D4 P42MUX: P42 Port Function Select Bit 1 (R/W): P42 port 0 (R/W): DST2 (DBG) (default) D3 Reserved D2 P41MUX: P41 Port Function Select Bit 1 (R/W): P41 port 0 (R/W): DSIO (OBG) (default) D1 Reserved D0 P40MUX: P40 Port Function Select Bit 1 (R/W): FOUTH (HSCLK) 0 (R/W): P40 port (default) S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 10-29 10 Input/Output Port (P) 10.8 Precautions Operation clock * The PCLK clock must be fed from the clock generator to access the input/output port. The prescaler output clock is also needed to operate the P0 and P1 port chattering filter. Switch on the prescaler when using this function. Pull-up * A delay will occur in the waveform rise-up depending on time constants such as pull-up resistance and pin load capacitance if the port pin is switched from Low level to High level by the internal pull-up resistor. Therefore, an appropriate wait time must be set for loading an input/output port. * Input/output ports that are not used should be set with pull-up resistance enabled. P0 and P1 port interrupts * Reset the corresponding interrupt flags P0IF[7:0] (0x5207) and P1IF[7:0] (0x5217) within the interrupt processing routine following a port interrupt to prevent recurring interrupts. * To prevent generating unnecessary interrupts, reset the corresponding interrupt flag--P0IF[7:0] (0x5207) or P1IF[7:0] (0x5217)--before permitting interrupts for the required port with the P0_IMSK register (0x5205) or P1_IMSK register (0x5215). P0/P1 Port chattering filter circuit * Input interrupts will not be accepted for a transition into SLEEP mode with the chattering filter left on. The chattering filter should be set off (no verification time) before executing the slp instruction. * P0/P1 port interrupts must be blocked when Px_CHAT register (0x5208/0x5218) settings are being changed. Changing the setting while interrupts are permitted may generate inadvertent P0/P1 interrupts. * The chattering filter verification time refers to the maximum pulse width that can be filtered. Generating an input interrupt requires a minimum input time of the verification time and a maximum input time of twice the verification time. * A phenomenon may occur in which the internal signal oscillates due to the time elapsed until the signal reaches the threshold value if the input signal rise-up/drop-off time is delayed. Since input interrupts will malfunction under these conditions, the input signal rise-up/drop-off time should normally be set to 25 ns or less. P0 port key-entry reset * Make sure the specified ports are not simultaneously switched to Low during normal operations when using the P0 port key-entry reset function. * The P0 port key entry reset function is disabled on initial resetting and cannot be used for resetting at poweron. * The P0 port key-entry reset function cannot be used in SLEEP state. 10-30 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 11 16-bit Timer (T16) 11 16-bit Timer (T16) 11.1 16-bit Timer Overview The S1C17003 incorporates a 3-channel 16-bit timer (T16). The 16-bit timer consists of a 16-bit presettable down counter and a 16-bit reload data register holding the preset values. The timer counts down from the initial value set in the reload data register and outputs an underflow signal when the counter underflows. The underflow signal is used to generate an interrupt and an internal serial interface clock. The underflow cycle can be programmed by selecting the prescaler clock and reload data, enabling the application program to obtain time intervals and serial transfer speeds as required. The timer also combines an event counter function via the input/output port pins and the external input signal pulse width measurement function. Figure 11.1.1 illustrates the 16-bit timer configuration. P02 (Ch.0) P13 (Ch.1) P14 (Ch.2) Prescaler To ITC ADC (conversion trigger) (from Ch.0) To SPI (from Ch.1) To I2CM (from Ch.2) 16-bit timer Ch.x TRMD Operating mode selection CKSL[1:0] External input signal polarity selection CKACTV Count clock selection DF[3:0] PCLK-1/1 to 1/16 K PRESER Timer reset PRUN Control circuit RUN/STOP control Reload data register T16_TRx Interrupt request Serial transfer clock Down counter T16_TCx Internal data bus Count mode selection Underflow Figure 11.1.1: 16-bit timer configuration (1-channel) Note: The 3-channel 16-bit timer module has the same functions except for the control register address. The description in this section applies to all channels of the 16-bit timer. The "x" in the register name refers to the channel number (0 to 2). The register addresses are referenced as "Ch.0," "Ch.1," and "Ch.2." Example: T16_CTLx register (0x4226/0x4246/0x4266) Ch.0: T16_CTL0 register (0x4226) Ch.1: T16_CTL1 register (0x4246) Ch.2: T16_CTL2 register (0x4266) S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 11-1 11 16-bit Timer (T16) 11.2 16-bit Timer Operating Modes The 16-bit timer has the following three operating modes: 1. Internal clock mode (Normal timer counting internal clock) 2. External clock mode (Functions as event counter) 3. Pulse width measurement mode (Counts external input pulse width using internal clock) The operating mode is selected using CKSL[1:0] (D[9:8]/T16_CTLx register). * CKSL[1:0]: Input Clock and Pulse Width Count Mode Select Bits in the 16-bit Timer Ch.x Control (T16_CTLx) Register (D[9:8]/0x4226/0x4246/0x4266) Table 11.2.1: Operating mode selection CKSL[1:0] 0x3 0x2 0x1 0x0 Operating mode Reserved Pulse width measurement mode External clock mode Internal clock mode (Default: 0x0) 11.2.1 Internal Clock Mode Internal clock mode uses the prescaler output clock as the count clock. The timer counts down from the initial value set in the reload data register and outputs an underflow signal when the counter underflows. The underflow signal is used to generate an interrupt and an internal serial interface clock. The time until underflow occurs can be finely programmed by selecting the prescaler clock and initial counter value, making it useful for serial transfer clock generation and sporadic time measurement. Count clock selection The count clock is selected by the DF[3:0] (D[3:0]/T16_CLKx register) from the 15 types generated by the prescaler dividing the PCLK clock into 1/1 to 1/16 K divisions. * DF[3:0]: Timer Input Clock Select Bits in the 16-bit Timer Ch.x Input Clock Select (T16_CLKx) Register (D[3:0]/0x4220/0x4240/0x4260) Table 11.2.1.1: Count clock selection DF[3:0] 0xf 0xe 0xd 0xc 0xb 0xa 0x9 0x8 Prescaler output clock Reserved PCLK-1/16384 PCLK-1/8192 PCLK-1/4096 PCLK-1/2048 PCLK-1/1024 PCLK-1/512 PCLK-1/256 DF[3:0] 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 Prescaler output clock PCLK-1/128 PCLK-1/64 PCLK-1/32 PCLK-1/16 PCLK-1/8 PCLK-1/4 PCLK-1/2 PCLK-1/1 (Default: 0x0) Note: * The prescaler must run before operating the 16-bit timer in internal clock mode. * Make sure the 16-bit timer count is halted before changing count clock settings. For detailed information on the prescaler control, see "9 Prescaler (PSC)." 11-2 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 11 16-bit Timer (T16) 11.2.2 External Clock Mode External clock mode uses the clock and pulses input via the input/output port as a count clock. These inputs can also be used as an event counter. Timer operations other than the input clock are the same as for internal clock mode. External clock input port The following input ports are used for external clock or pulse input. Table 11.2.2.1: External clock input port Timer channel Ch.0 Ch.1 Ch.2 Input signal name EXCL0 EXCL1 EXCL2 Input/output port pin P02 P13 P14 Confirm that the input/output ports used for external clock or pulse input are set to input mode (the default setting). No pin function selection is needed. While the input/output ports function as general purpose inputs, the input signal is also sent to the 16-bit timer. The P02, P13, and P14 ports used by 16-bit timer Ch.0, Ch.1 and Ch.2 incorporate chattering filter circuits and can also be used as EXCLx inputs. For instructions on controlling chattering filter circuits, see "10.5 P0 and P1 Port Chattering Filter Function." Signal polarity selection CKACTV (D10/T16_CTLx register) is used in this mode to select the falling edge or rising edge of the input signal for counting. * CKACTV: External Clock Active Level Select Bit in the 16-bit Timer Ch.x Control (T16_CTLx) Register (D10/0x4226/0x4246/0x4266) Counting down uses the rising edge when CKACTV is 1 (default) and uses the falling edge when set to 0. External input clock PRUN Counter (CKACTV = 1) Counter (CKACTV = 0) n n-1 n-2 n-3 n-4 n-5 n-6 n-7 n-8 n-9 n-10 n n-1 n-2 n-3 n-4 n-5 n-6 n-7 n-8 n-9 n-10 Figure 11.2.2.1: External clock mode count The 16-bit timer does not use the prescaler in this mode. If no other peripheral modules use the prescaler clock, the prescaler can be stopped to reduce current consumption. (The prescaler clock is used for P0, P1 port chattering filtering.) S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 11-3 11 16-bit Timer (T16) 11.2.3 Pulse Width Measurement Mode In pulse width measurement mode, when pulses with the specified polarity are input from the external clock port, the internal clock is fed only while the signal is active, enabling counting. This enables interrupt generation and input pulse width measurements for pulse inputs of the specified width or greater. Pulse input port The Input/output port used for external pulse input is the same as for external clock mode (see Table 11.2.2.1). Input pulses using the input/output port corresponding to the timer channel in input mode. Count clock selection Counting uses the prescaler output clock selected by DF[3:0] (D[3:0]/T16_CLKx register) in the same way as for internal clock mode. Select the clock to suit approximate input pulse widths and counting accuracy. Signal polarity selection CKACTV (D10/T16_CTLx register) is used to select the active level for the pulses counted. The High period is measured when CKACTV is 1 (default) and the Low period is measured when CKACTV is set to 0. Example 1: Pulse width measurement Internal count clock PRUN External input signal Counter (CKACTV = 1) 0x0 0xff 0xfe 0xfd n+3 n+2 n+1 n n-1 n-2 n-3 0x2 0x1 0x0 n Example 2: Detecting pulses over specified width Internal count clock PRUN External input signal Counter (CKACTV = 1) n Underflow interrupt Figure 11.2.3.1: Pulse width measurement mode count operation 11-4 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 11 16-bit Timer (T16) 11.3 Count Mode The 16-bit timer features two count modes: Repeat mode and One-shot mode. These modes are selected using the TRMD (D4/T16_CTLx register). * TRMD: Count Mode Select Bit in the 16-bit Timer Ch.x Control (T16_CTLx) Register (D4/0x4226/0x4246/0x4266) Repeat mode (TRMD = 0, default) Setting TRMD to 0 sets the 16-bit timer to Repeat mode. In this mode, once the count starts, the 16-bit timer continues running until stopped by the application program. If the counter underflows, the timer presets the reload data register value into the counter and continues the count. Thus, the timer periodically outputs an underflow pulse. The 16-bit timer should be set to this mode to generate periodic interrupts at desired intervals or to generate a serial transfer clock. One-shot mode (TRMD = 1) Setting TRMD to 1 sets the 16-bit timer to One-shot mode. In this mode, the 16-bit timer stops automatically as soon as the counter underflows. This means only one interrupt can be generated after the timer starts. Note that the timer presets the reload data register value to the counter, then stops after an underflow has occurred. The 16-bit timer should be set to this mode to set a specific wait time or for pulse width measurement. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 11-5 11 16-bit Timer (T16) 11.4 16-bit Timer Reload Register and Underflow Cycle The reload data register T16_TRx (0x4222/0x4242/0x4262) is used to set the initial value for the down counter. The initial counter value set in the reload data register is preset to the down counter if the 16-bit timer is reset or the counter underflows. If the 16-bit timer is started after resetting, the timer counts down from the reload value (initial value). This means this reload value and the input clock frequency. determines the time elapsed from the point at which the timer starts until the underflow occurs (or between underflows). The time determined is used to obtain the specified wait time, the intervals between periodic interrupts, and the programmable serial interface transfer clock. One-shot mode Counter Timer start n n-1 Underflow 1 Preset by timer reset 0 n Auto preset (n = reload data) Repeat mode Counter Timer start n n-1 Underflow 1 0 n Preset by timer reset Auto preset Figure 11.4.1: Preset timing Underflow n-1 1 0 n Auto preset The underflow cycle can be calculated as follows: TR + 1 clk_in Underflow interval = ------ [s] Underflow cycle = ------ [Hz] clk_in TR + 1 clk_in: Count clock (prescaler output clock) frequency [Hz] TR: Reload data (0 to 65535) 11-6 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 11 16-bit Timer (T16) 11.5 16-bit Timer Reset The 16-bit timer is reset by writing 1 to PRESER (D1/T16_CTLx register). The reload data is preset and the counter is initialized. * PRESER: Timer Reset Bit in the 16-bit Timer Ch.x Control (T16_CTLx) Register (D1/0x4226/0x4246/0x4266) S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 11-7 11 16-bit Timer (T16) 11.6 16-bit Timer RUN/STOP Control Make the following settings before starting the 16-bit timer. (1) Select the operating mode (Internal clock, External clock, or Pulse width measurement). See Section 11.2. (2) For Internal clock or Pulse width measurement mode, select the count clock (prescaler output clock). See Section 11.2.1. (3) Set the count mode (One-shot or Repeat). See Section 11.3. (4) Calculate the initial counter value and set the reload data register. See Section 11.4. (5) Reset the timer and preset the counter to the initial value. See Section 11.5. (6) If using timer interrupts, set the interrupt level and allow interrupts for the relevant timer channel. See Section 11.8. To start the 16-bit timer, write 1 to PRUN (D0/T16_CTLx register). * PRUN: Timer Run/Stop Control Bit in the 16-bit Timer Ch.x Control (T16_CTLx) Register (D0/0x4226/0x4246/0x4266) The timer starts counting down from the initial value or from the current counter value if no initial value was preset. When the counter underflows, the timer outputs an underflow pulse and presets the counter to the initial value. An interrupt request is sent simultaneously to the interrupt controller (ITC). If One-shot mode is set, the timer stops the count. If Repeat mode is set, the timer continues to count from the reloaded initial value. Write 0 to PRUN to stop the 16-bit timer via the application program. The counter stops counting and retains the current counter value until either the timer is reset or restarted. To restart the count from the initial value, the timer should be reset before writing 1 to PRUN. One-shot mode Count clock PRESER writing PRUN Counter Set by software n n-1 1 Reset by hardware 0 n Interrupt request Repeat mode Count clock PRESER writing PRUN Counter Set by software n n-1 1 Reset by software 0 n n-1 1 0 n n-1 Interrupt request Figure 11.6.1: Count operation In Pulse width measurement mode, the timer counts only while PRUN is set to 1 and the external input signal is at the specified active level. When the external input signal becomes inactive, the 16-bit timer stops counting and retains the counter value until the next active level input. (See Figure 11.2.3.1.) 11-8 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 11 16-bit Timer (T16) 11.7 16-bit Timer Output Signal The 16-bit timer outputs underflow pulses when the counter underflows. These pulses are used for timer interrupt requests. These pulses are also used to generate the internal serial interface serial transfer clock. The clock generated and underflow signal are sent to the internal serial interface, as shown below. 16-bit timer Ch.0 output underflow signal ADC/10SA (conversion trigger) 16-bit timer Ch.1 output clock SPI 16-bit timer Ch.2 output clock I2C Use the following equations to calculate the reload data register value for obtaining the desired transfer rate: clk_in SPI TR = -------- - 1 bps x 2 clk_in TR = -------- - 1 I2CM bps x 4 clk_in: Count clock (prescaler output clock) frequency [Hz] TR: Reload data (0 to 65535) bps: Transfer rate (bit/s) S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 11-9 11 16-bit Timer (T16) 11.8 16-bit Timer Interrupts The 16-bit timer outputs interrupt requests to the interrupt controller (ITC) when the counter underflows. Underflow interrupt Generated by a counter underflow, this interrupt request sets the interrupt flag T16IF (D0/T16_INTx register) to 1 inside the T16 module provided for each channel. T16IF: 16-bit Timer Interrupt Flag in the 16-bit Timer Ch.x Interrupt Control (T16_INTx) Register (D0/0x4228/0x4248/0x4268) To use this interrupt, set T16IE (D8/T16_INTx register) to 1. If T16IE is set to 0 (default), T16IF will not be set to 1, and the interrupt request for this cause will not be sent to the ITC. T16IE: 16-bit Timer Interrupt Enable Bit in the 16-bit Timer Ch.x Interrupt Control (T16_INTx) Register (D8/0x4228/0x4248/0x4268) If T16IF is set to 1, the T16 module outputs an interrupt request to the ITC. An interrupt is generated if interrupt conditions are satisfied for the ITC and S1C17 core. Note: * The T16 module interrupt flag T16IF must be reset within the interrupt processing routine following a 16-bit timer interrupt to prevent recurring interrupts. * Reset T16IF before permitting 16-bit timer interrupts with T16IE to prevent unwanted interrupts occurring. Interrupt vectors The timer interrupt vector numbers and vector addresses are listed below. Table 11.8.1: Timer interrupt vectors Timer channel 16-bit Timer Ch.0 16-bit Timer Ch.1 16-bit Timer Ch.2 Vector number 13 (0x0d) 14 (0x0e) 15 (0x0f) Vector address TTBR + 0x34 TTBR + 0x38 TTBR + 0x3c Other interrupt settings The ITC allows the precedence of 16-bit timer interrupts to be set between level 0 (default) and level 7 for each channel. The PSR (S1C17 core internal processor status register) IE (interrupt enable) bit must be set to 1 to generate actual interrupts. For specific information on interrupt processing, see "6 Interrupt Controller (ITC)." 11-10 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 11 16-bit Timer (T16) 11.9 Control Register Details Table 11.9.1: 16-bit timer register list Address 0x4220 0x4222 0x4224 0x4226 0x4228 0x4240 0x4242 0x4244 0x4246 0x4248 0x4260 0x4262 0x4264 0x4266 0x4268 Register name T16_CLK0 T16_TR0 T16_TC0 T16_CTL0 T16_INT0 T16_CLK1 T16_TR1 T16_TC1 T16_CTL1 T16_INT1 T16_CLK2 T16_TR2 T16_TC2 T16_CTL2 T16_INT2 Function 16-bit Timer Ch.0 Input Clock Select Register 16-bit Timer Ch.0 Reload Data Register 16-bit Timer Ch.0 Counter Data Register 16-bit Timer Ch.0 Control Register 16-bit Timer Ch.0 Interrupt Control Register 16-bit Timer Ch.1 Input Clock Select Register 16-bit Timer Ch.1 Reload Data Register 16-bit Timer Ch.1 Counter Data Register 16-bit Timer Ch.1 Control Register 16-bit Timer Ch.1 Interrupt Control Register 16-bit Timer Ch.2 Input Clock Select Register 16-bit Timer Ch.2 Reload Data Register 16-bit Timer Ch.2 Counter Data Register 16-bit Timer Ch.2 Control Register 16-bit Timer Ch.2 Interrupt Control Register Prescaler output clock selection Reload data setting Counter data Timer mode setting and timer RUN/STOP Interrupt Control Prescaler output clock selection Reload data setting Counter data Timer mode setting and timer RUN/STOP Interrupt Control Prescaler output clock selection Reload data setting Counter data Timer mode setting and timer RUN/STOP Interrupt Control The 16-bit timer registers are described in detail below. These are 16-bit registers. Note: When data is written to the registers, the "Reserved" bits must always be written as 0 and not 1. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 11-11 11 16-bit Timer (T16) 0x4220/0x4240/0x4260: 16-bit Timer Ch.x Input Clock Select Registers (T16_CLKx) Register name Address 16-bit Timer Ch.x Input Clock Select Register (T16_CLKx) 0x4220 0x4240 0x4260 (16 bits) Bit Name D15-4 - D3-0 DF[3:0] Function reserved Timer input clock select (Prescaler output clock) Setting Init. R/W - DF[3:0] 0xf 0xe 0xd 0xc 0xb 0xa 0x9 0x8 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 Clock reserved PCLK-1/16384 PCLK-1/8192 PCLK-1/4096 PCLK-1/2048 PCLK-1/1024 PCLK-1/512 PCLK-1/256 PCLK-1/128 PCLK-1/64 PCLK-1/32 PCLK-1/16 PCLK-1/8 PCLK-1/4 PCLK-1/2 PCLK-1/1 Remarks - - 0 when being read. 0x0 R/W Note: The "x" in the register names indicates the channel number (0 to 2). D[15:4] Reserved D[3:0] DF[3:0]: Timer Input Clock Select Bits Select the 16-bit timer count clock from the 15 different prescaler output clocks. Table 11.9.2: Count clock selection DF[3:0] 0xf 0xe 0xd 0xc 0xb 0xa 0x9 0x8 Prescaler output clock Reserved PCLK-1/16384 PCLK-1/8192 PCLK-1/4096 PCLK-1/2048 PCLK-1/1024 PCLK-1/512 PCLK-1/256 DF[3:0] 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 Prescaler output clock PCLK-1/128 PCLK-1/64 PCLK-1/32 PCLK-1/16 PCLK-1/8 PCLK-1/4 PCLK-1/2 PCLK-1/1 (Default: 0x0) Note: Make sure the 16-bit timer count is halted before changing count clock settings. 11-12 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 11 16-bit Timer (T16) 0x4222/0x4242/0x4262: 16-bit Timer Ch.x Reload Data Registers (T16_TRx) Register name Address 16-bit Timer Ch.x Reload Data Register (T16_TRx) 0x4222 0x4242 0x4262 (16 bits) Bit Name D15-0 TR[15:0] Function 16-bit timer reload data TR15 = MSB TR0 = LSB Setting Init. R/W 0x0 to 0xffff 0x0 R/W Remarks Note: The "x" in the register names indicates the channel number (0 to 2). 0x4222: 16-bit Timer Ch.0 Reload Data Register (T16_TR0) 0x4242: 16-bit Timer Ch.1 Reload Data Register (T16_TR1) 0x4262: 16-bit Timer Ch.2 Reload Data Register (T16_TR2) D[15:0] TR[15:0]: 16-bit Timer Reload Data Sets the counter initial value. (Default: 0x0) The reload data set in this register is preset to the counter if the timer is reset or the counter underflows. If the 16-bit timer is started after resetting, the timer counts down from the reload value (initial value). This means this reload value and the input clock frequency determine the time elapsed from the point at which the timer starts until the underflow occurs (or between underflows). The time determined is used to obtain the desired wait time, the intervals between periodic interrupts, and the programmable serial interface transfer clock. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 11-13 11 16-bit Timer (T16) 0x4224/0x4244/0x4264: 16-bit Timer Ch.x Counter Data Registers (T16_TCx) Register name Address 16-bit Timer Ch.x Counter Data Register (T16_TCx) 0x4224 0x4244 0x4264 (16 bits) Bit Name D15-0 TC[15:0] Function 16-bit timer counter data TC15 = MSB TC0 = LSB Setting 0x0 to 0xffff Init. R/W 0xffff Remarks R Note: The "x" in the register names indicates the channel number (0 to 2). 0x4224: 16-bit Timer Ch.0 Counter Data Register (T16_TC0) 0x4244: 16-bit Timer Ch.1 Counter Data Register (T16_TC1) 0x4264: 16-bit Timer Ch.2 Counter Data Register (T16_TC2) D[15:0] 11-14 TC[15:0]: 16-bit Timer Counter Data Reads out the counter data. (Default: 0xffff) This register is read-only and cannot be written to. Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 11 16-bit Timer (T16) 0x4226/0x4246/0x4266: 16-bit Timer Ch.x Control Registers (T16_CTLx) Register name Address 16-bit Timer Ch.x Control Register (T16_CTLx) Bit Name 0x4226 D15-11 - 0x4246 D10 CKACTV 0x4266 D9-8 CKSL[1:0] (16 bits) D7-5 D4 D3-2 D1 D0 - TRMD - PRESER PRUN Function reserved External clock active level select Input clock and pulse width measurement mode select reserved Count mode select reserved Timer reset Timer run/stop control Setting - 1 High CKSL[1:0] 0x3 0x2 0x1 0x0 0 Low Mode reserved Pulse width External clock Internal clock - 1 One shot 0 Repeat - 1 Reset 1 Run 0 Ignored 0 Stop Init. R/W Remarks - - 0 when being read. 1 R/W 0x0 R/W - 0 - 0 0 - 0 when being read. R/W - 0 when being read. W R/W Note: The "x" in the register names indicates the channel number (0 to 2). 0x4226: 16-bit Timer Ch.0 Control Register (T16_CTL0) 0x4246: 16-bit Timer Ch.1 Control Register (T16_CTL1) 0x4266: 16-bit Timer Ch.2 Control Register (T16_CTL2) D[15:11] Reserved D10 CKACTV: External Clock Active Level Select Bit Selects the external input pulse polarity or external clock counting edge. 1 (R/W): Active High/Rising edge (default) 0 (R/W): Active Low/Falling edge This setting determines whether the external input clock rising edge or falling edge is used for counting in external clock mode (when CKSL[1:0] = 0x1). In pulse width measurement mode (when CKSL[1:0] = 0x2), this setting determines external input pulse polarity. D[9:8] CKSL[1:0]: Input Clock and Pulse Width Measurement Mode Select Bits Select the 16-bit timer operating mode. Table 11.9.3: Operating mode selection CKSL[1:0] 0x3 0x2 0x1 0x0 Operating mode Reserved Pulse width measurement mode External clock mode Internal clock mode (Default: 0x0) Internal clock mode uses the prescaler output clock as the count clock. The timer counts down from the initial value set in the reload data register and outputs an underflow signal when the counter underflows. The underflow signal is used to generate an interrupt and an internal serial interface clock. The time until underflow occurs can be finely programmed by selecting the prescaler clock and initial counter value, allowing its use for serial transfer clock generation and sporadic time measurement. External clock mode uses the clock and pulses input via the input/output ports (Ch.0: P02, Ch.1: P13, Ch.2: P14) as a count clock and can also be used as an event counter. Timer operations other than the input clock are the same as for internal clock mode. In pulse width measurement mode, when pulses with the specified polarity are input from the external clock port, the internal clock is fed only while the signal is active, enabling counting. This enables interrupt generation and input pulse width measurements for pulse inputs of the specified width or greater. D[7:5] Reserved S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 11-15 11 16-bit Timer (T16) D4 TRMD: Count Mode Select Bit Selects the 16-bit timer count mode. 1 (R/W): One-shot mode 0 (R/W): Repeat mode (default) Setting TRMD to 0 sets the 16-bit timer to Repeat mode. In this mode, once the count starts, the 16-bit timer continues to run until stopped by the application. If the counter underflows, the timer presets the counter to the reload data register value and continues the count. Thus, the timer periodically outputs an underflow pulse. Set the 16-bit timer to this mode to generate periodic interrupts at desired intervals or to generate a serial transfer clock. Setting TRMD to 1 sets the 16-bit timer to One-shot mode. In this mode, the 16-bit timer stops automatically as soon as the counter underflows. This means only one interrupt can be generated after the timer starts. Note that the timer presets the counter to the reload data register value, then stops when an underflow occurs. Set the 16-bit timer to this mode to set a specific wait time or for pulse width measurement. D[3:2] Reserved D1 PRESER: Timer Reset Bit Resets the 16-bit timer. 1 (W): Reset 0 (W): Disabled 0 (R): Normally 0 when read out (default) Writing 1 to this bit presets the counter to the reload data value. D0 PRUN: Timer Run/Stop Control Bit Controls the timer RUN/STOP. 1 (R/W): Run 0 (R/W): Stop (default) The timer starts counting when PRUN is written as 1 and stops when written as 0. When the timer is stopped, the counter data is retained until reset or until the next RUN state. 11-16 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 11 16-bit Timer (T16) 0x4228/0x4248/0x4268: 16-bit Timer Ch.x Interrupt Control Registers (T16_INTx) Register name Address 16-bit Timer Ch.x Interrupt Control Register (T16_INTx) 0x4228 0x4248 0x4268 (16 bits) Bit D15-9 D8 D7-1 D0 Name - T16IE - T16IF Function reserved 16-bit timer interrupt enable reserved 16-bit timer interrupt flag Setting - 1 Enable 0 Disable - 1 Cause of interrupt occurred 0 Cause of interrupt not occurred Init. R/W - 0 - 0 Remarks - 0 when being read. R/W - 0 when being read. R/W Reset by writing 1. Note: The "x" in register names indicates the channel number (0 to 2). 0x4228: 16-bit Timer Ch.0 Interrupt Control Register (T16_INT0) 0x4248: 16-bit Timer Ch.1 Interrupt Control Register (T16_INT1) 0x4268: 16-bit Timer Ch.2 Interrupt Control Register (T16_INT2) D[15:9] Reserved D8 T16IE: 16-bit Timer Interrupt Enable Bit Permits or prevents interrupts caused by counter underflows for each channel. 1 (R/W): Permit interrupt 0 (R/W): Prevent interrupt (default) Setting T16IE to 1 enables 16-bit timer interrupt requests to the ITC; setting to 0 prevents interrupts. D[7:1] Reserved D0 T16IF: 16-bit Timer Interrupt Flag Interrupt flag indicating the counter underflow interrupt cause occurrence status for each channel. 1 (R): Interrupt cause present 0 (R): No interrupt cause (default) 1 (W): Reset flag 0 (W): Disable T16IF is the T16 module interrupt flag. Setting T16IE (D8) to 1 sets the counter to 1 if an underflow occurs during counting. A 16-bit timer interrupt request signal is output to the ITC at the same time. An interrupt is generated if interrupt conditions are satisfied for the ITC and S1C17 core. Writing 1 to this bit resets T16IF. Note: * To prevent interrupt recurrences, the T16 module interrupt flag T16IF must be reset within the interrupt processing routine following a 16-bit timer interrupt. * To prevent unwanted interrupts, reset T16IF before permitting 16-bit timer interrupts with T16IE. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 11-17 11 16-bit Timer (T16) 11.10 Precautions * The prescaler must run before the 16-bit timer. * Set the count clock and count mode only while the 16-bit timer count is stopped. * To prevent interrupt recurrences, the T16 module interrupt flag T16IF (D0/T16_INTx register) must be reset within the interrupt processing routine following a 16-bit timer interrupt. T16IF: 16-bit Timer Interrupt Flag in 16-bit Timer Ch.x Interrupt Control (T16_INTx) Register (D0/0x4228/0x4248/0x4268) * To prevent unwanted interrupts, reset T16IF before permitting 16-bit timer interrupts with T16IE (D8/T16_INTx register). T16IE: 16-bit Timer Interrupt Enable Bit in 16-bit Timer Ch.x Interrupt Control (T16_INTx) Register (D8/0x4228/ 0x4248/0x4268) 11-18 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 12 8-bit Timer (T8F) 12 8-bit Timer (T8F) 12.1 8-bit Timer Overview The S1C17003 incorporates a Dual channel 8-bit timer with Fine mode. The 8-bit timer consists of an 8-bit presettable down counter and an 8-bit reload data register holding the preset values. The timer counts down from the initial value set in the reload data register and outputs an underflow signal when the counter underflows. The underflow signal is used to generate an interrupt and UART clock. The underflow cycle can be programmed by selecting the prescaler clock and reload data, enabling the application program to obtain time intervals and serial transfer speeds as required. Fine mode provides a function that minimizes transfer rate errors. Figure 12.1.1 illustrates the 8-bit timer configuration. Count clock selection Prescaler PRESER Reload data register T8F_TRx DF[3:0] PCLK-1/1 to 1/16 K RUN/STOP control To ITC To UART Ch.0 (from T8F Ch.0) UART Ch.1 (from T8FCh.1) Timer reset Down counter T8F_TCx PRUN Underflow Interrupt request Internal data bus 8-bit timer Ch.x Control circuit Serial transfer clock Fine mode setting TFMD[3:0] Figure 12.1.1: 8-bit timer configuration (Single channel) Note: The 2-channel 8-bit timer modules have the same functions for both channels. Only the control register addresses are different. The description in this section applies to all 8-bit timer channels. The "x" in the register name indicates the channel number (0 or 1). Register addresses are given in the format (Ch.0/Ch.1). Example: T8F_CTLx register (0x4206/0x4286) Ch.0: T8F_CTL0 register (0x4206) Ch.1: T8F_CTL1 register (0x4286) S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 12-1 12 8-bit Timer (T8F) 12.2 8-bit Timer Count Mode The 8-bit timer features two count modes: Repeat mode and One-shot mode. These modes are selected using the TRMD bit (D4/T8F_CTL register). * TRMD: Count Mode Select Bit in the 8-bit Timer Ch.x Control (T8F_CTLx) Register (D4/0x4206/0x4286)) Repeat mode (TRMD = 0, default) Setting TRMD to 0 sets the 8-bit timer to Repeat mode. In this mode, once the count starts, the 8-bit timer continues running until stopped by the application program. If the counter underflows, the timer presets the reload data register value into the counter and continues the count. Thus, the timer periodically outputs an underflow pulse. The 8-bit timer should be set to this mode to generate periodic interrupts at desired intervals or to generate a serial transfer clock. One-shot mode (TRMD = 1) Setting TRMD to 1 sets the 8-bit timer to One-shot mode. In this mode, the 8-bit timer stops automatically as soon as the counter underflows. This means only one interrupt can be generated after the timer starts. Note that the timer presets the reload data register value to the counter, then stops after an underflow has occurred. The 8-bit timer should be set to this mode to set a specific wait time. Note: Make sure the 8-bit timer count is halted before changing count mode settings. 12-2 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 12 8-bit Timer (T8F) 12.3 Count Clock The 8-bit timer uses the prescaler output clock as the count clock. The prescaler generates 15 different clocks by dividing the PCLK clock into 1/1 to 1/16 K divisions. One of these is selected by the DF[3:0] bit (D[3:0]/T8F_CLK register). * DF[3:0]: Timer Input Clock Select Bits in the 8-bit Timer Ch.x Input Clock Select (T8F_CLKx) Register (D[3:0]/ 0x4200/0x4280) Table 12.3.1: Count clock selection DF[3:0] 0xf 0xe 0xd 0xc 0xb 0xa 0x9 0x8 Prescaler output clock Reserved PCLK-1/16384 PCLK-1/8192 PCLK-1/4096 PCLK-1/2048 PCLK-1/1024 PCLK-1/512 PCLK-1/256 DF[3:0] 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 Prescaler output clock PCLK-1/128 PCLK-1/64 PCLK-1/32 PCLK-1/16 PCLK-1/8 PCLK-1/4 PCLK-1/2 PCLK-1/1 (Default: 0x0) Note: * The prescaler must run before the 8-bit timer. * Make sure the 8-bit timer count is halted before changing count clock settings. For detailed information on the prescaler control, see "9 Prescaler (PSC)." S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 12-3 12 8-bit Timer (T8F) 12.4 8-bit Timer Reload Register and Underflow Cycle The reload data register T8F_TR (0x4202/0x4282) is used to set the initial value for the down counter. The initial counter value set in the reload data register is preset to the down counter if the 8-bit timer is reset or the counter underflows. If the 8-bit timer is started after resetting, the timer counts down from the reload value (initial value). This means this reload value and the input clock frequency. determines the time elapsed from the point at which the timer starts until the underflow occurs (or between underflows). The time determined is used to obtain the specified wait time, the intervals between periodic interrupts, and the programmable serial interface transfer clock. One-shot mode Counter Timer start n n-1 Underflow 1 Preset by timer reset 0 n Auto preset (n = reload data) Repeat mode Counter Timer start n n-1 Underflow 1 0 n Preset by timer reset Auto preset Figure 12.4.1: Preset timing Underflow n-1 1 0 n Auto preset The underflow cycle can be calculated as follows: T8F_TR + 1 clk_in Underflow interval = ------------ [s] Underflow cycle = ------------ [Hz] clk_in T8F_TR + 1 clk_in: T8F_TR: Count clock (prescaler output clock) frequency [Hz] Reload data (0 to 255) Note: The UART generates a sampling clock that divides the 8-bit timer output into 1/16 divisions. Be careful when setting the transfer rate. 12-4 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 12 8-bit Timer (T8F) 12.5 8-bit Timer Reset The 8-bit timer is reset by writing 1 to PRESER bit (D1/T8F_CTLx register). The reload data is preset and the counter is initialized. * PRESER: Timer Reset Bit in the 8-bit Timer Ch.x Control (T8F_CTLx) Register (D1/0x4206/0x4286) S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 12-5 12 8-bit Timer (T8F) 12.6 8-bit Timer RUN/STOP Control Make the following settings before starting the 8-bit timer: (1) Set the count mode (One-shot or Repeat). See Section 12.2. (2) Select the count clock (prescaler output clock). See Section 12.3. (3) Calculate the initial counter value and set it to the reload data register. See Section 12.4. (4) Reset the timer and preset the initial value to the counter. See Section 12.5. (5) If using timer interrupts, set the interrupt level and permit interrupts. See Section 12.9. To start the 8-bit timer, write 1 to PRUN (D0/T8F_CTLx register). * PRUN: Timer Run/Stop Control Bit in the 8-bit Timer Ch.x Control (T8F_CTLx) Register (D0/0x4206/0x4286) The timer starts counting down from the initial value or from the current counter value if no initial value was preset. When the counter underflows, the timer outputs an underflow pulse and presets the counter to the initial value. An interrupt request is sent simultaneously to the interrupt controller (ITC). If One-shot mode is set, the timer stops the count. If Repeat mode is set, the timer continues to count from the reloaded initial value. Write 0 to PRUN bit to stop the 8-bit timer via the application program. The counter stops counting and retains the current counter value until either the timer is reset or restarted. To restart the count from the initial value, the timer should be reset before writing 1 to PRUN. Resetting the timer while counting is underway sets the counter to the reload register value and continues the count. One-shot mode Count clock PRESER writing PRUN Counter Set by software n n-1 1 Reset by hardware 0 n Interrupt request Repeat mode Count clock PRESER writing PRUN Counter Set by software n n-1 1 Reset by software 0 n n-1 1 0 n n-1 Interrupt request Figure 12.6.1: Count operation 12-6 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 12 8-bit Timer (T8F) 12.7 8-bit Timer Output Signal The 8-bit timer outputs underflow pulses when the counter underflows. These pulses are used for timer interrupt requests. The underflow pulses are also used to generate the serial transfer clock and are transmitted to the UART. 8-bit timer Ch.0 output clock UART Ch.0 8-bit timer Ch.1 output clock UART Ch.1 Use the following equations to calculate the reload data register value for obtaining the desired transfer rate. clk_in bps = -------------------------- {(T8F_TR + 1) x 16 + TFMD} ( ) clk_in T8F_TR = ------ - TFMD - 16 / 16 bps clk_in: T8F_TR: bps: TFMD: Count clock (prescaler output clock) frequency [Hz] Reload data (0 to 255) Transfer rate (bit/s) Fine mode setting (0 to15) S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 12-7 12 8-bit Timer (T8F) 12.8 Fine Mode Fine mode provides a function that minimizes transfer rate errors. The 8-bit timer can output a programmable clock signal for use as the UART Ch.0 serial transfer clock. The timer output clock can be set to the required frequency by selecting the appropriate prescaler output clock and reload data. Note that errors may occur, depending on the transfer rate. Fine mode extends the output clock cycle by delaying the underflow pulse from the counter. This delay can be specified with the TFMD[3:0] bit (D[11:8]/ T8F_CTL register). * TFMD[3:0]: Fine Mode Setup Bits in the 8-bit Timer Chx Control (T8F_CTLx) Register (D[11:8]/0x4206/0x4286) The TFMD[3:0] bit specifies the delay pattern to be inserted into the 16 underflow intervals. Inserting one delay extends the output clock cycle by one count clock cycle. This setting delays the interrupt timing in the same way. Table 12.8.1: Delay patterns specified by TFMD[3:0] TFMD[3:0] 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf 1 - - - - - - - - - - - - - - - - 2 - - - - - - - - D D D D D D D D 3 - - - - - - - - - - - - D D D D 4 - - - - D D D D D D D D D D D D 5 - - - - - - - - - - - - - - D D 6 - - - - - - D D D D D D D D D D Underflow number 7 8 9 10 - - - - - - - - - D - - - D - - - D - - - D - - - D - - - D - D - D - D - D - D D D - D D D - D D D - D D D - D D D - D D D D D 11 - - - - - - - - - - - D D D D D 12 - - - D D D D D D D D D D D D D 13 - - - - - - - - - - - - - D D D 14 - - - - - D D D D D D D D D D D 15 - - - - - - - - - D D D D D D D 16 - D D D D D D D D D D D D D D D D: Indicates the insertion of a delay cycle. Count clock Underflow signal (no correction) Underflow signal (with correction) 15 15 16 1 16 1 Delay Output clock (no correction) Output clock (with correction) Figure 12.8.1: Delay cycle insertion in Fine mode After the initial resetting, TFMD[3:0] is set to 0x0, preventing insertion of delay cycles. 12-8 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 12 8-bit Timer (T8F) 12.9 8-bit Timer Interrupts The 8-bit timer outputs interrupt requests to the interrupt controller (ITC) when the counter underflows. Underflow interrupt This interrupt request generated by a counter underflow sets the interrupt flag T8IF (D0/T8F_INT register) to 1 within the T8F module. T8IF: 8-bit Timer Interrupt Flag in the 8-bit Timer Chx Interrupt Control (T8F_INTx) Register (D0/0x4208/ 0x4288)) To use this interrupt, set T8IE (D8/T8F_INT register) to 1. If T8IE is set to 0 (the default value), T8IF will not be set to 1, and interrupt request for this interrupt cause will not be sent to the ITC. T8IE: 8-bit Timer Interrupt Enable Bit in the 8-bit Timer Chx Interrupt Control (T8F_INTx) Register (D8/ 0x4208/0x4288) If T8IF is set to 1, the T8F module outputs an interrupt request to the ITC. An interrupt is generated if interrupt conditions are satisfied for the ITC and S1C17 core. Note: * To prevent interrupt recurrences, the T8F module interrupt flag T8IF must be reset within the interrupt processing routine following an 8-bit timer interrupt. * To prevent unwanted interrupts, reset T8IF before permitting 8-bit timer interrupts with T8IE. * The 8-bit timer uses one interrupt signal for Ch.0 and Ch.1 interrupt requests to the ITC. The same interrupt processing routine is performed regardless of which interrupt is generated. When using both channel interrupts, read out the interrupt flag in the T8F module as part of the interrupt processing routine and check which channel generates the interrupt. Interrupt vectors The 8-bit timer interrupt vector numbers and vector addresses are listed below. Vector number: 12 (0x0c) Vector address: TTBR + 0x30 Other interrupt settings The ITC allows the priority of 8-bit timer interrupts to be set between level 0 (the default value) and level 7 for each channel. To generate actual interrupts, the PSR (S1C17 core internal processor status register) IE (interrupt enable) bit must be set to 1. For more information on interrupt processing, see "6 Interrupt Controller (ITC)." S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 12-9 12 8-bit Timer (T8F) 12.10 Control Register Details Table 12.10.1: 8-bit timer register list Address 0x4280 0x4282 0x4284 0x4286 0x4288 Register name T8F_CLK1 T8F_TR1 T8F_TC1 T8F_CTL1 T8F_INT1 8-bit Timer Ch.1 Input Clock Select Register 8-bit Timer Ch.1 Reload Data Register 8-bit Timer Ch.1 Counter Data Register 8-bit Timer Ch.1 Control Register 8-bit Timer Ch.1 Interrupt Control Register Function Prescaler output clock selection Reload data setting Counter data Timer mode setting and timer RUN/STOP Interrupt control The 8-bit timer registers are described in detail below. These are 16-bit registers. Note: When data is written to the registers, the "Reserved" bits must always be written as 0 and not 1. 12-10 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 12 8-bit Timer (T8F) 0x4200/0x4280: 8-bit Timer Ch.x Input Clock Select Register (T8F_CLKx) Register name Address 8-bit Timer Chx 0x4200 0x4280 Input Clock Select Register (16 bits) (T8F_CLKx) Bit Name D15-4 - D3-0 DF[3:0] Function reserved Timer input clock select (Prescaler output clock) Setting - DF[3:0] 0xf 0xe 0xd 0xc 0xb 0xa 0x9 0x8 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 Clock reserved PCLK-1/16384 PCLK-1/8192 PCLK-1/4096 PCLK-1/2048 PCLK-1/1024 PCLK-1/512 PCLK-1/256 PCLK-1/128 PCLK-1/64 PCLK-1/32 PCLK-1/16 PCLK-1/8 PCLK-1/4 PCLK-1/2 PCLK-1/1 Init. R/W Remarks - - 0 when being read. 0x0 R/W Note: The indication "x" in the register name indicates the channel number (0 or 1). 0x4200: 8-bit Timer Ch.0 Input Clock Select Register (T8F_CLK0) 0x4280: 8-bit Timer Ch.1 Input Clock Select Register (T8F_CLK1) D[15:4] Reserved D[3:0] DF[3:0]: Timer Input Clock Select Bits Select the 8-bit timer count clock from the 15 different prescaler output clocks. Table 12.10.2: Count clock selection DF[3:0] 0xf 0xe 0xd 0xc 0xb 0xa 0x9 0x8 Prescaler output clock Reserved PCLK-1/16384 PCLK-1/8192 PCLK-1/4096 PCLK-1/2048 PCLK-1/1024 PCLK-1/512 PCLK-1/256 DF[3:0] 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 Prescaler output clock PCLK-1/128 PCLK-1/64 PCLK-1/32 PCLK-1/16 PCLK-1/8 PCLK-1/4 PCLK-1/2 PCLK-1/1 (Default: 0x0) Note: Make sure the 8-bit timer count is halted before changing count clock settings. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 12-11 12 8-bit Timer (T8F) 0x4202/0x4282: 8-bit Timer Ch.x Reload Data Register (T8F_TRx) Register name Address 8-bit Timer Chx 0x4202 0x4282 Reload Data (16 bits) Register (T8F_TRx) Bit Name D15-8 - D7-0 TR[7:0] Function reserved 8-bit timer reload data TR7 = MSB TR0 = LSB Setting - 0x0 to 0xff Init. R/W Remarks - - 0 when being read. 0x0 R/W Note: The indication "x" in the register name indicates the channel number (0 or 1). 0x4202: 8-bit Timer Ch.0 Reload Data Register (T8F_TR0) 0x4282: 8-bit Timer Ch.1 Reload Data Register (T8F_TR1) D[15:8] Reserved D[7:0] TR[7:0]: 8-bit Timer Reload Data Sets the counter initial value. (Default: 0x0) The reload data set in this register is preset to the counter if the timer is reset or the counter underflows. If the 8-bit timer is started after resetting, the timer counts down from the reload value (initial value). This means this reload value and the input clock frequency determine the time elapsed from the point at which the timer starts until the underflow occurs (or between underflows). The time determined is used to obtain the desired wait time, the intervals between periodic interrupts, and the programmable serial interface transfer clock. 12-12 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 12 8-bit Timer (T8F) 0x4204/0x4284: 8-bit Timer Ch.x Counter Data Register (T8F_TCx) Register name Address 8-bit Timer Chx 0x4204 0x4284 Counter Data (16 bits) Register (T8F_TCx) Bit Name D15-8 - D7-0 TC[7:0] Function reserved 8-bit timer counter data TC7 = MSB TC0 = LSB Setting - 0x0 to 0xff Init. R/W - 0xff - R Remarks 0 when being read. Note: The indication "x" in the register name indicates the channel number (0 or 1). 0x4204: 8-bit Timer Ch.0 Counter Data Register (T8F_TC0) 0x4284: 8-bit Timer Ch.1 Counter Data Register (T8F_TC1) D[15:8] Reserved D[7:0] TC[7:0]: 8-bit Timer Counter Data Reads out the counter data. (Default: 0xff) This register is read-only and cannot be written to. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 12-13 12 8-bit Timer (T8F) 0x4206/0x4286: 8-bit Timer Ch.x Control Register (T8F_CTLx) Register name Address Bit Name 8-bit Timer Chx 0x4206 D15-12 - Control Register (16 bits) D11-8 TFMD[3:0] (T8F_CTLx) D7-5 D4 D3-2 D1 D0 - TRMD - PRESER PRUN Function Setting reserved Fine mode setup Init. R/W - 0x0 to 0xf reserved Count mode select reserved Timer reset Timer run/stop control - 1 One shot 0 Repeat - 1 Reset 1 Run Remarks - - 0 when being read. 0x0 R/W Set a number of times to insert delay into a 16-underflow period. - - 0 when being read. 0 R/W - - 0 when being read. 0 W 0 R/W 0 Ignored 0 Stop Note: The indication "x" in the register name indicates the channel number (0 or 1). 0x4206: 8-bit Timer Ch.0 Control Register (T8F_CTL0) 0x4286: 8-bit Timer Ch.1 Control Register (T8F_CTL1) D[15:12] Reserved D[11:8] TFMD[3:0]: Fine Mode Setup Bits Correct the transfer rate error. (Default: 0x0) The TFMD[3:0] bit specifies the delay pattern to be inserted into the 16 underflow intervals. Inserting one delay extends the output clock cycle by one count clock cycle. This setting delays the interrupt timing in the same way. Table 12.10.3: Delay patterns specified by TFMD[3:0] TFMD[3:0] 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa 0xb 0xc 0xd 0xe 0xf 1 - - - - - - - - - - - - - - - - 2 - - - - - - - - D D D D D D D D 3 - - - - - - - - - - - - D D D D 4 - - - - D D D D D D D D D D D D 5 - - - - - - - - - - - - - - D D 6 - - - - - - D D D D D D D D D D Underflow number 7 8 9 10 - - - - - - - - - D - - - D - - - D - - - D - - - D - - - D - D - D - D - D - D D D - D D D - D D D - D D D - D D D - D D D D D 11 - - - - - - - - - - - D D D D D 12 - - - D D D D D D D D D D D D D 13 - - - - - - - - - - - - - D D D 14 - - - - - D D D D D D D D D D D 15 - - - - - - - - - D D D D D D D 16 - D D D D D D D D D D D D D D D D: Indicates the insertion of a delay cycle. Count clock Underflow signal (no correction) Underflow signal (with correction) 15 15 16 1 16 Delay 1 Output clock (no correction) Output clock (with correction) Figure 12.10.1: Delay cycle insertion in Fine mode D[7:5] 12-14 Reserved Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 12 8-bit Timer (T8F) D4 TRMD: Count Mode Select Bit Selects the 8-bit timer count mode. 1 (R/W): One-shot mode 0 (R/W): Repeat mode (default) Setting TRMD to 0 sets the 8-bit timer to Repeat mode. In this mode, once the count starts, the 8-bit timer continues to run until stopped by the application. If the counter underflows, the timer presets the counter to the reload data register value and continues the count. Thus, the timer periodically outputs an underflow pulse. Set the 8-bit timer to this mode to generate periodic interrupts at desired intervals or to generate a serial transfer clock. Setting TRMD to 1 sets the 8-bit timer to One-shot mode. In this mode, the 8-bit timer stops automatically as soon as the counter underflows. This means only one interrupt can be generated after the timer starts. Note that the timer presets the counter to the reload data register value, then stops when an underflow occurs. Set the 8-bit timer to this mode to set a specific wait time. Note: Make sure the 8-bit timer count is halted before changing count mode settings. D[3:2] Reserved D1 PRESER: Timer Reset Bit Resets the 8-bit timer. 1 (W): Reset 0 (W): Disabled 0 (R): Normally 0 when read out (default) Writing 1 to this bit presets the counter to the reload data value. D0 PRUN: Timer Run/Stop Control Bit Controls the timer RUN/STOP. 1 (R/W): Run 0 (R/W): Stop (default) The timer starts counting when PRUN is written as 1 and stops when written as 0. When the timer is stopped, the counter data is retained until reset or until the next RUN state. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 12-15 12 8-bit Timer (T8F) 0x4208/0x4288: 8-bit Timer Ch.x Interrupt Control Register (T8F_INTx) Register name Address Bit 8-bit Timer Chx 0x4208 0x4288 Interrupt Control Register (16 bits) (T8F_INTx) D15-9 D8 D7-1 D0 Name - T8IE - T8IF Function reserved 8-bit timer interrupt enable reserved 8-bit timer interrupt flag Setting Init. R/W - 1 Enable 0 Disable - 1 Cause of interrupt occurred 0 Cause of interrupt not occurred - 0 - 0 Remarks - 0 when being read. R/W - 0 when being read. R/W Reset by writing 1. Note: The indication "x" in the register name indicates the channel number (0 or 1). 0x4208: 8-bit Timer Ch.0 Interrupt Control Register (T8F_INT0) 0x4288: 8-bit Timer Ch.1 Interrupt Control Register (T8F_INT1) D[15:9] Reserved D8 T8IE: 8-bit Timer Interrupt Enable Bit Permits or prevents interrupts caused by counter underflows for each channel. 1 (R/W): Permit interrupt 0 (R/W): Prevent interrupt (default) Setting T8IE to 1 permits 8-bit timer interrupt requests to the ITC; setting to 0 prevents interrupts. D[7:1] Reserved D0 T8IF: 8-bit Timer Interrupt Flag Interrupt flag indicating the counter underflow interrupt cause occurrence status for each channel. 1 (R): Interrupt cause present 0 (R): No interrupt cause (default) 1 (W): Reset flag 0 (W): Disable T8IF is the T8F module interrupt flag. Setting T8IE (D8) to 1 sets the counter to 1 if an underflow occurs during counting. An 8-bit timer interrupt request signal is output to the ITC at the same time. An interrupt is generated if interrupt conditions are satisfied for the ITC and S1C17 core. Writing 1 to this bit resets T8IF. Note: * To prevent interrupt recurrences, the T8 module interrupt flag T8IF must be reset within the interrupt processing routine following an 8-bit timer interrupt. * To prevent unwanted interrupts, reset T8IF before permitting 8-bit timer interrupts with T8IE. * The 8-bit timer uses one interrupt signal for Ch.0 and Ch.1 interrupt requests to the ITC. The same interrupt processing routine is performed regardless of which interrupt is generated. When using both channel interrupts, read out the interrupt flag in the T8F module as part of the interrupt processing routine and check which channel generates the interrupt. 12-16 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 12 8-bit Timer (T8F) 12.11 Precautions * The prescaler must run before the 8-bit timer. * Set the count clock and count mode only while the 8-bit timer count is stopped. * To prevent interrupt recurrences, the T8F module interrupt flag T8IF (D0/T8F_INT register) must be reset within the interrupt processing routine following an 8-bit timer interrupt. T8IF: 8-bit Timer Chx Interrupt Flag in the 8-bit Timer Chx Interrupt Control (T8F_INTx) Register (D0/0x4208/ 0x4288) * To prevent unwanted interrupts, reset T8IF before permitting 8-bit timer interrupts with T8IE (D8/T8F_INT register). T8IE: 8-bit Timer Chx Interrupt Enable Bit in the 8-bit Timer Chx Interrupt Control (T8F_INTx) Register (D8/0x4208/0x4288) * The 8-bit timer uses one interrupt signal for Ch.0 and Ch.1 interrupt requests to the ITC. The same interrupt processing routine is performed regardless of which interrupt is generated. When using both channel interrupts, read out the interrupt flag in the T8F module as part of the interrupt processing routine and check which channel generates the interrupt. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 12-17 13 PWM Timer (T16E) 13 PWM Timer (T16E) 13.1 PWM Timer Overview The S1C17003 incorporates a channel PWM Timer. Figure 13.1.1 illustrates the PWM Timer configuration. PWM timer CBUFEN Timer reset T16ERST RUN/STOP control T16ERUN Input clock selection P15/EXCL3 Compare data A buffer (T16E_CA) CLKSEL Compare A signal Prescaler clock selection T16EDF[3:0] Prescaler PCLK-1/1 to 1/16K Fine mode selection SELFM Inverted output INVOUT Initial output level selection INITOL Clock output enable OUTEN P36/TOUT3 Count control circuit Compare B signal Output control circuit Compare data A register T16E_CA Comparator Up-counter T16E_TC Comparator Internal data bus Compare buffer enable Compare data B register T16E_CB Compare data B buffer (T16E_CB) PWM output P37/TOUTN3 ITo ITC Compare A interrupt request Compare B interrupt request Interrupt control circuit CAIE Compare A interrupt enable CBIE Compare B interrupt enable Figure 13.1.1: PWM Timer configuration The PWM Timer includes a 16-bit up-counter (T16E_TC register), two 16-bit compare data registers (T16E_CA and T16E_CB registers), and the corresponding buffers. Software can configure the count value of the 16-bit counter, and reset it to 0, while an external signal from the input/output port pin (EXCL3) or the Prescaler output clock counts up the 16-bit counter. Software can read the count value. The compare data A and B registers hold data for comparison against the up-counter contents. Data can be read or written directly to or from the compare data registers. The compare data buffers enables loading to the compare data registers of comparison values set when the counter is reset by software or by a compare B match signal. Software can be used to set which of the compare data register and buffer the comparison values are written to. If the counter value matches the contents of each compare data register, the comparator outputs a signal to control interrupts and output signals. These registers can be used to program the interrupt occurrence cycle and output clock frequency and duty ratio. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 13-1 13 PWM Timer (T16E) 13.2 PWM Timer Operating Modes The PWM Timer has the following two operating modes: 1. Internal clock mode (Timer counting internal clock) 2. External clock mode (Functions as event counter) The operating mode is selected using CLKSEL (D3/T16E_CTL register). * CLKSEL: Input Clock Select Bit in the PWM Timer Control (T16E_CTL) Register (D3/0x5306) Setting CLKSEL to 0 (default) selects internal clock mode, while setting to 1 selects external clock mode. Internal clock mode Internal clock mode uses the prescaler output clock as the count clock. The count clock is selected by the T16EDF[3:0] (D[3:0]/T16E_CLK register) from the 15 types generated by the prescaler dividing the PCLK clock into 1/1 to 1/16 K divisions. * T16EDF[3:0]: Timer Input Clock Select Bits in the PWM Timer Input Clock Select (T16E_CLK) Register (D[3:0]/0x5308) Table 13.2.1: Prescaler clock selection T16EDF[3:0] 0xf 0xe 0xd 0xc 0xb 0xa 0x9 0x8 Prescaler output clock Reserved PCLK-1/16384 PCLK-1/8192 PCLK-1/4096 PCLK-1/2048 PCLK-1/1024 PCLK-1/512 PCLK-1/256 T16EDF[3:0] 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 Prescaler output clock PCLK-1/128 PCLK-1/64 PCLK-1/32 PCLK-1/16 PCLK-1/8 PCLK-1/4 PCLK-1/2 PCLK-1/1 (Default: 0x0) Note: * The prescaler must run before operating the PWM Timer in internal clock mode. * Make sure the PWM Timer count is halted before changing count clock settings. For detailed information on the prescaler control, see "9 Prescaler (PSC)." External clock mode In external clock mode, channel 0 uses a clock or pulse input via the P15(EXCL3) port for the count clock. Therefore it can be used as an event counter. Timer operations other than input clock are the same as those in the internal clock mode. To input the EXCL3 clock via the P15 port, write 0 to the P15MUX (D3-2/P1_PMUX register) to change the pin function, and set it to the input mode. * T15MUX: P15 Port Function Select bit in the P0 Port Function Select (P1_PMUX) Register (D3-2/0x52a3) The PWM Timer increments counts based on the input signal rising edge. The PWM Timer does not use the prescaler in this mode. If no other peripheral modules are using the prescaler clock, the prescaler can be stopped to reduce current consumption. 13-2 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 13 PWM Timer (T16E) 13.3 Setting and Resetting Counter Value The PWM Timer counter can be reset to 0 by writing 1 to the T16ERST bit (D1/T16E_CTL register). * T16ERST: Timer Reset Bit in the PWM Timer Control (T16E_CTL) Register (D1/0x5306) Normally, the counter should be reset by writing 1 to this bit before starting the count. The counter is reset by hardware if the counter matches compare data B after the count starts. The counter can also be set to any desired value by writing data to T16ETC[15:0] (D[15:0]/T16E_TC register). * T16ETC[15:0]: Counter Data in the PWM Timer Counter Data (T16E_TC) Register (D[15:0]/0x5304) S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 13-3 13 PWM Timer (T16E) 13.4 Compare Data Settings Compare data register/buffer selection The PWM Timer incorporates a data comparator allowing comparison of counter data against any desired value. This comparison data is stored in the compare data A and B registers. Data can be read or written directly to or from the compare data registers. The compare data buffers enable automatic loading to the compare data registers of the comparison values set in the buffers when the counter is reset by software (writing 1 to T16ERST) or by a compare B match signal. The CBUFEN (D5/T16E_CTL register) is used to set which of the compare data register and buffer the comparison values are written to. CBUFEN: Comparison Buffer Enable Bit in the PWM Timer Control (T16E_CTL) Register (D5/0x5306) Writing 1 to CBUFEN selects the compare data buffer. Writing 0 to it selects the compare data register. The compare data register is selected after initial resetting. Compare data writing Compare data A is written to T16ECA[15:0] (D[15:0]/T16E_CA register). Compare data B is written to T16ECB[15:0] (D[15:0]/T16E_CB register). T16ECA[15:0]: Compare Data A in the PWM Timer Compare Data A (T16E_CA) Register (D[15:0]/0x5300) T16ECB[15:0]: Compare Data B in the PWM Timer Compare Data B (T16E_CB) Register (D[15:0]/0x5302) When CBUFEN is set to 0, the compare data register values can be read or written directly by these registers. When CBUFEN is set to 1, data is read from and written to these registers via the compare data buffers. The buffer contents are loaded into the compare data registers when the counter is reset. The compare data registers and buffers are set to 0x0 after initial resetting. The timer compares the count data against the compare data registers and generates a compare match signal if the values are equal. This compare match signal generates an interrupt and controls the clock (TOUT3/ TOUTN3 signal) output externally. Compare data B also determines the counter reset cycle. The counter reset cycle can be calculated as follows: CB + 1 Counter reset interval= -------- [s] clk_in clk_in Counter reset cycle = -------- [Hz] CB + 1 CB: Compare data B (T16E_CB register value) clk_in: Prescaler output clock frequency 13-4 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 13 PWM Timer (T16E) 13.5 PWM Timer RUN/STOP Control Set the following before starting the PWM Timer. (1) Set the operating mode (input clock). See Section 13.2. (2) Set the clock output. See Section 13.6. (3) If using interrupts, set the interrupt level and permit interrupts for the PWM Timer. See Section 13.7. (4) Set the counter value or reset to 0. See Section 13.3. (5) Set the compare data. See Section 13.4. The PWM Timer includes T16ERUN (D0/T16E_CTL register) to control Run/Stop. * T16ERUN: Timer Run/Stop Control Bit in the PWM Timer Control (T16E_CTL) Register (D0/0x5306) The timer starts counting when T16ERUN is written as 1. Writing 0 to T16ERUN prevents clock input and stops the count. This control does not affect the counter data. The counter data is retained even when the count is halted, allowing resumption of the count from that data. If T16ERUN and T16ERST are written as 1 simultaneously, the timer starts counting after the reset. If the counter matches the compare data A register setting during counting, a compare A match signal is output and a compare A interrupt factor generated. Likewise, if the counter matches the compare data B register setting, a compare B match signal is output and a compare B interrupt factor generated. The counter is reset to 0 at the same time. If CBUFEN is set to 1, the value set in the compare data buffers is loaded into the compare data registers. If interrupts are permitted, an interrupt request is sent to the interrupt controller (ITC). In either case, counting continues unaffected. For compare B, counting starts from the counter value 0. T16ERUN T16ERST T16E_CA 0x2 T16E_CB 0x5 Input clock T16E_TC 0 Reset 1 2 3 Compare A interrupt 4 5 0 1 Reset and compare B interrupt 2 3 Compare A interrupt 4 5 0 1 Reset and compare B interrupt Figure 13.5.1: Basic counter operation timing S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 13-5 13 PWM Timer (T16E) 13.6 Clock Output Control The PWM Timer can generate a TOUT3/TOUTN3 signal using the compare match signal. Figure 13.6.1 shows the PWM Timer clock output circuit. TOUT3 (P36) INITOL Compare A Compare B Logic D Q TOUTN3 (P37) Q Clock OUTEN INVOUT Figure 13.6.1: PWM Timer clock output circuit Initial output level settings The default output level is 0 (Low level) while the TOUT3 clock output is Off (TOUTN3 output is High level). This can be changed to 1 (TOUT3 = High level, TOUTN3 = Low level) with INITOL (D8/T16E_CTL register). INITOL: Initial Output Level Select Bit in the PWM Timer Ch.x Control (T16E_CTL) Register (D8/0x5306) When INITOL is 0 (default), TOUT3 initial output level is low (TOUT3 output is High). When INITOL is set to 1, the initial output level should be high (TOUT3 output is Low). Output signal polarity selection By default, an active High (normal Low) TOUT3 output signal is generated (TOUTN3 output signal is active Low). This logic can be inverted by INVOUT (D4/T16E_CTL register). Writing 1 to INVOUT causes the timer to generate an active Low (normal High) TOUT3 signal (TOUTN3 signal is active High). INVOUT: Inverse Output Control Bit in the PWM Timer Control (T16E_CTL) Register (D4/0x5306) Setting INVOUT to 1 also inverts the initial output level set for INITOL. See Figure 13.6.2 for more information on output waveforms. Output pin settings The TOUT3/TOUTN3 signal generated here can be output from the following pins and can provide a programmable clock and PWM signal to external devices. TOUT3 output TOUT3 (P36) pin, TOUTN3 output TOUTN3 (P37) pin The pin used for output is set for input/output port use after initial resetting and switches to input mode. The pin then becomes high-impedance. Switching the pin function to TOUT3/TOUTN3 output outputs the level set by INITOL and INVOUT. After the timer output starts, the output is maintained at this level until changed by the counter value. Table 13.6.1: Initial output level INITOL 1 1 0 0 13-6 INVOUT 1 0 1 0 Initial output level Low High High Low Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 13 PWM Timer (T16E) Clock output start To output the TOUT3 clock, write 1 to OUTEN (D2/T16E_CTL register). Writing 0 to OUTEN switches the output to the initial output level as set by INITOL and INVOUT. OUTEN: Clock Output Enable Bit in the PWM Timer Control (T16E_CTL) Register (D2/0x5306) Figure 13.6.2 illustrates the output waveform. Input clock T16ERST OUTEN T16ERUN Counter value 0 1 2 3 4 5 0 1 2 3 4 5 0 1 2 3 4 5 0 1 Compare A signal Compare B signal TOUT3 output (INITOL = 0, INVOUT = 0) TOUT3 output (INITOL = 0, INVOUT = 1) TOUT3 output (INITOL = 1, INVOUT = 0) TOUT3 output (INITOL = 1, INVOUT = 1) (When T16E_CA = 3 and T16E_CB = 5) Figure 13.6.2: PWM Timer output waveform TOUT3 output when INVOUT = 0 (Active High) The timer outputs Low level (initial output level at output start) until the counter matches the compare data A set in the T16E_CA register (0x5300). When the counter reaches the next compare data A value, the output pin switches to High level, and a compare A interrupt factor is generated. If the counter subsequently counts up to compare data B set in the T16E_CB register (0x5302), the counter is reset and the output pin is returned to the Low level. A compare B interrupt factor is also generated at the same time. The TOUTN3 pins output the inverted signals described above. TOUT3 output when INVOUT = 1 (Active High) The timer outputs High level (inverted value of the initial output level at output start) until the counter matches the compare data A set in the T16E_CA register (0x5300). When the counter reaches the next compare data A value, the output pin switches to Low level, and a compare A interrupt factor is generated. If the counter subsequently counts up to compare data B set in the T16E_CB register (0x5302), the counter is reset and the output pin is returned to the High level. A compare B interrupt factor is also generated at the same time. The TOUTN3 pins output the inverted signals described above. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 13-7 13 PWM Timer (T16E) Clock output Fine mode settings With the default settings, the clock output changes at the input clock rise-up if the counter value matches the compare data A. If the counter data register T16ETC[14:0] matches the compare data A register T16ECA0[15:1], the Fine mode clock output changes in accordance with the compare data A bit 0 (T16ECA0) value. When T16ECA0 is 0: Changes at input clock rise-up. When T16ECA0 is 1: Changes at half-cycle delayed input clock drop-off. Input clock Counter value 0 1 2 3 4 5 0 1 2 3 4 5 0 1 2 3 4 5 0 1 2 3 4 5 0 1 2 3 T16E_CA 2 3 4 5 6 5 T16E_CB Compare A signal Compare B signal TOUT output (INVOUT = 0) TOUT output (INVOUT = 1) Figure 13.6.3: Fine mode clock output The output duty can thus be adjusted in Fine mode in input clock half-cycle steps. Note that a pulse will be output with an input clock 1-cycle width when compare data A = 0 (same as for default). The maximum value for compare data B in Fine mode is 215 - 1 = 32,767, and the compare data A range will be 0 to (2 x compare data B - 1). Fine mode is set by SELFM (D6/T16E_CTL register). SELFM: Fine Mode Select Bit in the PWM Timer Control (T16E_CTL) Register (D6/0x5306) Writing 1 to SELFM sets Fine mode. Fine mode is disabled after initial resetting. Precautions (1) Compare data should be set with A 0 and B 1 when using the timer output. The minimum settings are A = 0 and B = 1, and the timer output cycle is half the input clock. (2) Setting compare data with A > B (A > B x 2 for Fine mode) generates a compare B match signal only. It does not generate a compare A match signal. In this case, the TOUT3 output is fixed at Low (High when INVOUT = 1), and the TOUTN3 output is fixed at High (Low when INVOUT = 1). 13-8 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 13 PWM Timer (T16E) 13.7 PWM Timer Interrupts The T16E module includes functions for generating the following two kinds of interrupts: * Compare A match interrupt * Compare B match interrupt The T16E module outputs a single interrupt signal shared by the above two interrupt factors to the interrupt controller (ITC). The interrupt flag within the T16E module should be read to identify the interrupt factor that occurred. Compare A match interrupt This interrupt request is generated when the counter matches the compare data A register setting during counting. It sets the interrupt flag CAIF (D0/T16E_INT register) within the T16E module to 1. CAIF: Compare A Interrupt Flag in the PWM Timer Interrupt Flag (T16E_IFLG) Register (D0/0x530c) To use this interrupt, set CAIE (D0/T16E_IMSK register) to 1. If CAIE is set to 0 (default), CAIF is not set to 1, and the interrupt request for this factor is not sent to the ITC. CAIE: Compare A Interrupt Enable Bit in the PWM Timer Interrupt Mask (T16E_IMSK) Register (D0/0x530a) If CAIF is set to 1, the T16E module outputs an interrupt request to the ITC. An interrupt is generated if the ITC and S1C17 core interrupt conditions are satisfied. CAIF should be read and checked within the PWM Timer interrupt processing routine to determine whether the PWM Timer interrupt is attributable to compare A matching. Compare B match interrupt This interrupt request is generated when the counter matches the compare data B register setting during counting. It sets the interrupt flag CBIF (D1/T16E_INT register) within the T16E module to 1. CBIF: Compare B Interrupt Flag in the PWM Timer Interrupt Flag (T16E_IFLG) Register (D1/0x530c) To use this interrupt, set CBIE (D1/T16E_INT register) to 1. If CBIE is set to 0 (default), CBIF is not set to 1, and the interrupt request for this factor is not sent to the ITC. CBIE: Compare B Interrupt Enable Bit in the PWM Timer Interrupt Mask (T16E_IMSK) Register (D1/0x530a) If CAIF is set to 1, the T16E module outputs an interrupt request to the ITC. An interrupt is generated if the ITC and S1C17 core interrupt conditions are satisfied. CAIF should be read and checked within the PWM Timer interrupt processing routine to determine whether the PWM Timer interrupt is attributable to compare A matching. Note: * To prevent interrupt recurrences, the T16E module interrupt flags CAIF and CBIF must be reset within the interrupt processing routine following a PWM Timer interrupt. * To prevent generating unnecessary interrupts, reset the corresponding CAIF or CBIF before permitting compare A or compare B interrupts from CAIE or CBIE. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 13-9 13 PWM Timer (T16E) Interrupt vectors The PWM Timer interrupt vector numbers and vector addresses are listed below. Table 13.7.1: PWM Timer interrupt vectors Timer channel T16E Vector number 110x0b Vector address TTBR + 0x2c Other interrupt settings The ITC allows the priority of PWM Timer interrupts to be set between level 0 (the default value) and level 7 for each channel. To generate actual interrupts, the PSR (S1C17 core internal processor status register) IE (interrupt enable) bit must be set to 1. For more information on interrupt processing, see "6 Interrupt Controller (ITC)." 13-10 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 13 PWM Timer (T16E) 13.8 Control Register Details Table 13.8.1: PWM Timer register list Address 0x5300 0x5302 0x5304 0x5306 0x5308 0x530a 0x530c Register name T16E_CA T16E_CB T16E_TC T16E_CTL T16E_CLK T16E_IMSK T16E_IFLG PWM Timer Ch.0 Compare Data A Register PWM Timer Ch.0 Compare Data B Register PWM Timer Ch.0 Counter Data Register PWM Timer Ch.0 Control Register PWM Timer Ch.0 Input Clock Select Register PWM Timer Ch.0 Interrupt Mask Register PWM Timer Ch.0 Interrupt Flag Register Function Compare data A setting Compare data B setting Counter data Timer mode setting and timer RUN/STOP Prescaler output clock selection Interrupt factor mask selection Interrupt factor checking The PWM Timer registers are described in detail below. These are 16-bit registers. Note: When data is written to the registers, the "Reserved" bits must always be written as 0 and not 1. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 13-11 13 PWM Timer (T16E) 0x5300: PWM Timer Compare Data A Register (T16E_CA) Register name Address PWM Timer Compare Data A Register (T16E_CA) D[15:0] 13-12 0x5300 (16 bits) Bit Name Function D15-0 T16ECA[15:0] Compare data A T16ECA15 = MSB T16ECA0 = LSB Setting Init. R/W 0x0 to 0xffff 0x0 R/W Remarks T16ECA[15:0]: Compare Data A Sets the PWM Timer compare data A. (Default: 0x0) When CBUFEN (D5/T16E_CTL register) is set to 0, this register can be used to directly read from or directly write to the compare data A register. When CBUFEN is set to 1, data is read from and written to these registers via the compare data A buffer. The buffer contents are loaded into the compare data A register when the counter is reset. The data set is compared against the counter data, and a compare A interrupt factor is generated if the contents match. The timer output waveform changes at the same time (rising when INVOUT (D4/ T16E_CTL register) = 0 and trailing when INVOUT = 1). These processes do not affect the counter data or the count process. Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 13 PWM Timer (T16E) 0x5302: PWM Timer Compare Data B Register (T16E_CB) Register name Address PWM Timer Compare Data B Register (T16E_CB) D[15:0] 0x5302 (16 bits) Bit Name Function D15-0 T16ECB[15:0] Compare data B T16ECB15 = MSB T16ECB0 = LSB Setting Init. R/W 0x0 to 0xffff 0x0 R/W Remarks T16ECB[15:0]: Compare Data B Sets the PWM Timer compare data B. (Default: 0x0) When CBUFEN (D5/T16E_CTL register) is set to 0, this register can be used to directly read from or directly write to the compare data B register. When CBUFEN is set to 1, data is read from and written to these registers via the compare data B buffer. The buffer contents are loaded into the compare data B register when the counter is reset. The data set is compared against the counter data, and a compare B interrupt factor is generated if the contents match. The timer output waveform changes at the same time (rising when INVOUT (D4/ T16E_CTL register) = 0 and trailing when INVOUT = 1). The counter is reset to 0. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 13-13 13 PWM Timer (T16E) 0x5304: PWM Timer Counter Data Register (T16E_TC) Register name Address PWM Timer Counter Data Register (T16E_TC) D[15:0] 13-14 0x5304 (16 bits) Bit Name Function D15-0 T16ETC[15:0] Counter data T16ETC15 = MSB T16ETC0 = LSB Setting Init. R/W 0x0 to 0xffff 0x0 R/W Remarks T16ETC[15:0]: Counter Data Counter data can be read out. (Default: 0x0) The counter value can also be set by writing data to this register. Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 13 PWM Timer (T16E) 0x5306: PWM Timer Control Register (T16E_CTL) Register name Address Bit 0x5306 PWM Timer Control Register (16 bits) (T16E_CTL) D15-9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name - INITOL - SELFM CBUFEN INVOUT CLKSEL OUTEN T16ERST T16ERUN Function reserved Initial output level reserved Fine mode select Comparison buffer enable Inverse output Input clock select Clock output enable Timer reset Timer run/stop control D[15:9] Reserved D8 INITOL: Initial Output Level Bit Sets the timer output initial output level. 1 (R/W): TOUT3 = High, TOUTN3 = Low 0 (R/W): TOUT3 = Low, TOUTN3 = High (default) Setting - 0 Low 1 High - 1 1 1 1 1 1 1 Fine mode Enable Invert External Enable Reset Run 0 0 0 0 0 0 0 Normal mode Disable Normal Internal Disable Ignored Stop Init. R/W - 0 - 0 0 0 0 0 0 0 Remarks - 0 when being read. R/W - 0 when being read. R/W R/W R/W R/W R/W W 0 when being read. R/W The timer output pin switches to the initial output level set here when the clock output is switched off by writing 0 to OUTEN (D2). Note that this level will be inverted when INVOUT (D4) is 1. D7 Reserved D6 SELFM: Fine Mode Select Bit Sets the clock output to Fine mode. 1 (R/W): Fine mode 0 (R/W): Normal output (default) When SELFM is set to 1, the clock output is set to Fine mode, and the output clock duty becomes adjustable in input clock half-cycle steps. When SELFM is set to 0, normal clock output is used. D5 CBUFEN: Comparison Buffer Enable Bit Permits and prevents writing to the compare data buffer. 1 (R/W): Permitted 0 (R/W): Prohibited (default) When CBUFEN is set to 1, compare data is read and written via the compare data buffer. The buffer contents are loaded into the compare data register when the counter is reset by software or compare B signal. When CBUFEN is set to 0, compare data is read and written directly to and from the compare data register. D4 INVOUT: Inverse Output Control Bit Selects the timer output signal polarity. 1 (R/W): Inverted (TOUT3 = active Low, TOUTN3 = active High) 0 (R/W): Normal (TOUT3 = active High, TOUTN3 = active Low) (default) Writing 1 to INVOUT generates a TOUT3 output active Low signal (Off level = High). When INVOUT is 0, an active High signal (Off level = Low) is generated. Writing 1 to this bit also inverts the initial output level set by INITOL (D8). The signal level above is inverted for TOUTN3 output. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 13-15 13 PWM Timer (T16E) D3 CLKSEL: Input Clock Select Bit Selects the timer input clock. 1 (R/W): External clock 0 (R/W): Internal clock (default) Writing 0 to CLKSEL selects the internal clock (Prescaler output) for the timer input clock, while writing 1 selects the external clock (a clock input via the EXCL3 (P15) pin) and it functions as an event counter. D2 OUTEN: Clock Output Enable Bit Controls the TOUT3/TOUTN3 signal (timer output clock) output. 1 (R/W): Permitted 0 (R/W): Prohibited (default) Writing 1 to OUTEN outputs the TOUT3/TOUTN3 signal from the corresponding output pin. TOUT3 output TOUT3 (P36) pin, TOUTN3 output TOUTN3 (P37) pin Writing 0 to OUTEN stops the output, and switches to the Off level corresponding to the settings for INVOUT (D4). The above pins must be set to TOUT3/TOUTN3 output using the port function selection register before outputting the TOUT3/TOUTN3 signals. D1 T16ERST: Timer Reset Bit Resets the counter. 1 (W): Reset 0 (W): Disabled 0 (R): Normally 0 when read out (default) Writing 1 to T16ERST resets the PWM Timer counter. D0 T16ERUN: Timer Run/Stop Control Bit Controls the timer Run/Stop. 1 (R/W): Run 0 (R/W): Stop (default) The PWM Timer starts the count when T16ERUN is written as 1 and stops when written as 0. The counter data is retained when stopped until the subsequent reset or run. Counting can be resumed when switched from Stop to Run from the data retained. 13-16 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 13 PWM Timer (T16E) 0x5308: PWM Timer Input Clock Select Register (T16E_CLK) Register name Address 0x5308 PWM Timer (16 bits) Input Clock Select Register (T16E_CLK) Bit Name Function D15-4 - reserved D3-0 T16EDF[3:0] Timer input clock select (Prescaler output clock) Setting - T16EDF[3:0] 0xf 0xe 0xd 0xc 0xb 0xa 0x9 0x8 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 Clock reserved PCLK-1/16384 PCLK-1/8192 PCLK-1/4096 PCLK-1/2048 PCLK-1/1024 PCLK-1/512 PCLK-1/256 PCLK-1/128 PCLK-1/64 PCLK-1/32 PCLK-1/16 PCLK-1/8 PCLK-1/4 PCLK-1/2 PCLK-1/1 Init. R/W Remarks - - 0 when being read. 0x0 R/W D[15:4] Reserved D[3:0] T16EDF[3:0]: Timer Input Clock Select Bits Select the PWM Timer count clock from the 15 different prescaler output clocks. Table 13.8.2: Count clock selection T16EDF[3:0] 0xf 0xe 0xd 0xc 0xb 0xa 0x9 0x8 Prescaler output clock Reserved PCLK-1/16384 PCLK-1/8192 PCLK-1/4096 PCLK-1/2048 PCLK-1/1024 PCLK-1/512 PCLK-1/256 T16EDF[3:0] 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 Prescaler output clock PCLK-1/128 PCLK-1/64 PCLK-1/32 PCLK-1/16 PCLK-1/8 PCLK-1/4 PCLK-1/2 PCLK-1/1 (Default: 0x0) Note: Make sure the PWM Timer count is halted before changing count clock settings. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 13-17 13 PWM Timer (T16E) 0x530a: PWM Timer Interrupt Mask Registers (T16E_IMSK) Register name Address PWM Timer Interrupt Mask Register (T16E_IMSK) 0x530a (16 bits) Bit Name D15-2 - D1 D0 CBIE CAIE Function Setting reserved Compare B interrupt enable Compare A interrupt enable D[15:2] Reserved D1 CBIE: Compare B Interrupt Enable Bit Permits or prohibits compare B match interrupts. 1 (R/W): Interrupt permitted 0 (R/W): Interrupt prohibited (default) - 1 Enable 1 Enable 0 Disable 0 Disable Init. R/W - - 0 0 R/W R/W Remarks 0 when being read. Setting CBIE to 1 permits compare B interrupt requests to the ITC. Setting it to 0 prohibits interrupts. D0 CAIE: Compare A Interrupt Enable Bit Permits or prohibits compare A match interrupts. 1 (R/W): Interrupt permitted 0 (R/W): Interrupt prohibited (default) Setting CAIE to 1 permits compare A interrupt requests to the ITC. Setting it to 0 prohibits interrupts. 13-18 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 13 PWM Timer (T16E) 0x530c: PWM Timer Interrupt Flag Registers (T16E_IFLG) Register name Address PWM Timer Interrupt Flag Register (T16E_IFLG) 0x530c (16 bits) Bit Name Function D15-2 - CBIF D1 reserved Compare B interrupt flag CAIF Compare A interrupt flag D0 Setting - 1 Cause of interrupt occurred 0 Cause of interrupt not occurred D[15:2] Reserved D1 CBIF: Compare B Interrupt Flag Interrupt flag indicating the compare B interrupt factor occurrence status. 1(R): Interrupt factor present 0(R): No interrupt factor (default) 1(W): Reset flag 0(W): Disabled Init. R/W Remarks - 0 - 0 when being read. R/W Reset by writing 1. 0 R/W CBIF is the interrupt flag corresponding to compare B interrupts. Setting CBIE (D1/T16E_IMSK register) to 1 sets this to 1 when the counter matches the compare data B register setting during counting. A PWM Timer interrupt request signal is output to the ITC at the same time. This interrupt request signal generates an interrupt if the ITC and S1C17 core interrupt conditions are satisfied. CBIF is reset by writing 1. D0 CAIF: Compare A Interrupt Flag Interrupt flag indicating the compare A interrupt factor occurrence status. 1(R): Interrupt factor present 0(R): No interrupt factor (default) 1(W): Reset flag 0(W): Disabled CAIF is the interrupt flag corresponding to compare A interrupts. Setting CAIE (D0/T16E_IMSK register) to 1 sets this to 1 when the counter matches the compare data A register setting during counting. A PWM Timer interrupt request signal is output to the ITC at the same time. This interrupt request signal generates an interrupt if the ITC and S1C17 core interrupt conditions are satisfied. CAIF is reset by writing 1. Note: * To prevent interrupt recurrences, T16E module interrupt flags CAIF and CBIF must be reset within the interrupt processing routine following a PWM Timer interrupt. * To prevent generating unnecessary interrupts, reset the corresponding CAIF or CBIF before permitting compare A or compare B interrupts from CAIE (D0/T16E_IMSK register) or CBIE (D1/T16E_IMSK register). S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 13-19 13 PWM Timer (T16E) 13.9 Precautions * The prescaler must run before operating the PWM Timer. * Make sure the PWM Timer count is halted before changing count clock settings. * Compare data should be set with A 0 and B 1 when using the timer output. The minimum settings are A = 0 and B = 1, and the timer output cycle is half the input clock. * Setting compare data with A > B (A > B x 2 for Fine mode) generates a compare B match signal only. It does not generate a compare A match signal. In this case, the timer output is fixed at Low (High when INVOUT = 1). * To prevent interrupt recurrences, the T16E module interrupt flags CAIF (D0/T16E_IFLG register) and CBIF (D1/ T16E_IFLG register) must be reset within the interrupt processing routine following a PWM Timer interrupt. * To prevent generating unnecessary interrupts, reset the corresponding CAIF (D0/T16E_IFLG register) or CBIF (D1/T16E_IFLG register) before permitting compare A or compare B interrupts from CAIE (D0/T16E_IMSK register) or CBIE (D1/T16E_IMSK register). 13-20 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 14 8-bit OSC1 Timer (T8OSC1) 14 8-bit OSC1 Timer (T8OSC1) 14.1 8-bit OSC1 Timer Overview The S1C17003 incorporates a single-channel 8-bit OSC1 timer that uses the OSC1 clock as its oscillation source. Figure 14.1.1 illustrates the 8-bit OSC1 timer configuration. 8-bit OSC1 timer Division ratio selection OSC1 oscillator/ division circuit Compare match signal Gate OSC1-1/1 to 1/32 P37/TOUT4 Timer reset T8ORST RUN/STOP control T8ORUN Count mode selection T8ORMD Count control circuit Duty match signal PWM output Compare data register T8OSC1_CMP Comparator Up counter T8OSC1_CNT Comparator Internal data bus OSC PWM duty data register T8OSC1_DUTY To ITC Compare match interrupt request Interrupt control circuit T8OIE Interrupt enable Figure 14.1.1: 8-bit OSC1 timer configuration The 8-bit OSC1 timer includes an 8-bit up-counter (T8OOSC1_CNT register), an 8-bit compare data register (T8OSC1_CMP register), and an 8-bit PWM duty data register (T8OSC1_DUTY register). The 8-bit counter can be reset to 0 by software and counts up using the OSC1 division clock (OSC1-1/1 to OSC1-1/32). The count value can be read by software. The compare data and PWM duty registers store the data used for comparisons against up-counter contents. If the counter values match the contents of each data register, the comparator outputs a signal to control the interrupts and the PWM output signal. The compare data register can be used to set the interrupt generating and PWM output clock frequencies. The PWM duty data register can be used to set the PWM output clock duty ratio. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 14-1 14 8-bit OSC1 Timer (T8OSC1) 14.2 8-bit OSC1 Timer Count Mode The 8-bit OSC1 timer features two count modes: Repeat mode and One-shot mode. These modes are selected using the T8ORMD bit (D1/T8OSC1_CT register). * T8ORMD: Count Mode Select Bit in the 8-bit OSC1 Timer Control (T8OSC1_CTL) Register (D1/0x50c0) Repeat mode (T8ORMD = 0, default) Setting T8ORMD to 0 sets the 8-bit OSC1 timer to Repeat mode. In this mode, once the count starts, the 8-bit OSC1 timer continues running until stopped by the application program. If the counter matches the compare data, the timer resets the counter and continues counting. The interrupt signal is output at the same time. The 8-bit OSC1 timer should be set to this mode to generate periodic interrupts at desired intervals or to perform PWM output. One-shot mode (T8ORMD = 1) Setting T8ORMD to 1 sets the 8-bit OSC1 timer to One-shot mode. In this mode, the 8-bit OSC1 timer stops automatically as soon as the counter matches the compare data. This means only one interrupt can be generated after the timer starts. Note that the timer resets the counter, then stops after a complete match has occurred. The 8-bit OSC1 timer should be set to this mode to set a specific wait time. Note: * Make sure the 8-bit OSC1 timer count is halted before changing count mode settings. * If count operation is activated while the count mode is set to one-shot mode, and the CPU enters halt state, the counter does not stop even when a compare match occurs, disabling one-shot operation. 14-2 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 14 8-bit OSC1 Timer (T8OSC1) 14.3 Count Clock The 8-bit OSC1 timer uses the OSC1 division clock output by the OSC module as the count clock. The OSC module generates 6 different clocks by dividing the OSC1 clock into 1/1 to 1/32 divisions. One of these is selected by T8O1CK[2:0] (D[3:1]/OSC_T8OSC1 register). * T8O1CK[2:0]: T8OSC1 Clock Division Ratio Select Bits in the T8OSC1 Clock Control (OSC_T8OSC1) Register (D[3:1]/0x5065) Table 14.3.1: Count clock selection T8O1CK[2:0] 0x7 to 0x6 0x5 0x4 0x3 0x2 0x1 0x0 Division ratio Reserved OSC1-1/32 OSC1-1/16 OSC1-1/8 OSC1-1/4 OSC1-1/2 OSC1-1/1 (Default: 0x0) The clock feed to the 8-bit OSC1 timer is controlled using T8O1CE (D0/OSC_T8OSC1 register). The T8O1CE default setting is 0, which stops the clock feed. Setting T8O1CE to 1 sends the clock generated as above to the 8-bit OSC1 timer. If 8-bit OSC1 timer operation is not required, the clock feed should be stopped to reduce power consumption. * T8O1CE: T8OSC1 Clock Enable Bit in the T8OSC1 Clock Control (OSC_T8OSC1) Register (D0/0x5065) Note: Make sure the 8-bit OSC1 timer count is halted before changing count clock settings. For detailed information on clock control, refer to "7 Oscillator Circuit (OSC)." S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 14-3 14 8-bit OSC1 Timer (T8OSC1) 14.4 Resetting 8-bit OSC1 Timer The 8-bit OSC1 Timer can be reset to 0 by writing 1 to the T8ORS bit (D4/T8OSC1_CTL register). * T8ORST: Timer Reset Bit in the 8-bit OSC1 Timer Control (T8OSC1_CTL) Register (D4/0x50c0) Normally, the counter should be reset by writing 1 to this bit before starting the count. The counter is reset by hardware if the counter matches compare data after the count starts. 14-4 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 14 8-bit OSC1 Timer (T8OSC1) 14.5 Compare Data Settings Compare data is written to T8OCMP[7:0] (D[7:0]/T8OSC1_CMP register). T8OCMP[7:0]: Compare Data Bits in the 8-bit OSC1 Timer Compare Data (T8OSC1_CMP) Register (D[7:0]/0x50c2) After initial resetting, the compare data register is set to 0x0. The timer compares the count data against the compare data register and generates a compare match signal as well as resets the counter if the values are equal. This compare match signal can generate an interrupt. The compare match cycle can be calculated as follows: CMP + 1 Compare match interval = ---------- [s] clk_in clk_in Compare match cycle = ---------- [Hz] CMP + 1 CMP: Compare data (T8OSC1_CMP register value) clk_in: 8-bit OSC1 timer count clock frequency When the 8-bit OSC1 timer is used to generate a PWM signal, the compare data determines the frequency of the output signal. (For a discussion of PWM output, refer to Section 14.8.) S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 14-5 14 8-bit OSC1 Timer (T8OSC1) 14.6 8-bit OSC1 Timer RUN/STOP Control Set the following items before starting the 8-bit OSC1 timer. (1) Set the count mode (One-shot or Repeat). See Section 14.2. (2) Select the operation clock. See Section 14.3. (3) If using interrupts, set the interrupt level and permit interrupts for the 8-bit OSC1 timer. See Section 14.7. (4) Reset the timer. See Section 14.4. (5) Set the compare data. See Section 14.5. (6) To output PWM signals, set the PWM duty data. See Section 14.8. The 8-bit OSC1 timer includes T8ORUN (D0/T8OSC1_CTL register) to control Run/Stop. * T8ORUN: Timer Run/Stop Control Bit in the 8-bit OSC1 Timer Control (T8OSC1_CTL) Register (D0/0x50c0) The timer starts counting when T8ORUN is written as 1. Writing 0 to T8ORUN prevents clock input and stops the count. This control does not affect the counter data. The counter data is retained even when the count is halted, allowing resumption of the count from that data. If T8ORUN and T8ORST are written as 1 simultaneously, the timer starts counting after the reset. If the counter matches the compare data register setting during counting, a compare match signal is output and a compare interrupt factor generated. Likewise, if the counter matches the compare data B register setting, a compare B match signal is output and a compare B interrupt factor generated. The counter is reset to 0 at the same time. If interrupts are permitted, an interrupt request is sent to the interrupt controller (ITC). If One-shot mode is set, the timer stops the count. If Repeat mode is set, the timer continues to count from 0. One-shot mode T8ORUN T8ORST T8OCMP 0x5 Input clock 0 T8OCNT 1 2 3 Reset 4 5 0 Reset & compare match interrupt Repeat mode T8ORUN T8ORST T8OCMP 0x5 Input clock 0 T8OCNT Reset 1 2 3 4 5 0 1 2 Reset & compare match interrupt 3 4 5 0 1 Reset & compare match interrupt Figure 14.6.1: Basic counter operation timing 14-6 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 14 8-bit OSC1 Timer (T8OSC1) 14.7 8-bit OSC1 Timer Interrupts The T8OSC1 module outputs an interrupt request to the interrupt controller (ITC) by compare match. Compare match interrupt This interrupt request is generated when the counter matches the compare data register setting during counting. It sets the interrupt flag T8OIF (D0/T8OSC1_IFLG register) within the T8OSC1 module to 1. T8OIF: 8-bit OSC1 Timer Interrupt Flag in the 8-bit OSC1 Timer Interrupt Flag (T8OSC1_IFLG) Register (D0/0x50c4) To use this interrupt, set T8OIE (D0/T8OSC1_IMSK register) to 1. If T8OIE is set to 0 (default), T8OIE is not set to 1, and the interrupt request for this factor is not sent to the ITC. T8OIE: 8-bit OSC1 Timer Interrupt Enable Bit in the 8-bit OSC1 Timer Interrupt Mask (T8OSC1_IMSK) Register (D0/0x50c3) If T8OIF is set to 1, the T8OSC1 module outputs an interrupt request to the ITC. This interrupt request signal generates an interrupt if the ITC and S1C17 core interrupt conditions are satisfied. Note: * To prevent interrupt recurrences, the T8OSC1 module interrupt flag T8OIF must be reset within the interrupt handler routine following an 8-bit OSC1 timer interrupt. * To prevent generating unnecessary interrupts, reset the corresponding T8OIF before permitting compare 8-bit OSC1 interrupts from T8OIE. Interrupt vectors The 8-bit OSC timer interrupt vector numbers and vector addresses are listed below. Vector number: 8 (0x08) Vector address: TTBR + 0x20 Other interrupt settings The ITC allows the priority of 8-bit OSC1 timer interrupts to be set between level 0 (the default value) and level 7. To generate actual interrupts, the PSR (S1C17 core internal processor status register) IE (interrupt enable) bit must be set to 1. For more information on interrupt processing, see "6 Interrupt Controller (ITC)." S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 14-7 14 8-bit OSC1 Timer (T8OSC1) 14.8 PWM output The 8-bit OSC1 timer can generate a PWM signal in accordance with the compare data and PWM duty data settings and output it from the TOUT4 (P37) pin. Output pin setting The PWM output pin (TOUT4) also acts as a pin (P37) for a general-purpose input/output port. In the default state, this pin is set as a general-purpose input/output port pin. To use it as a PWM output pin, change the function by setting the value 3 in the P37MUX (D7-6/P3_PMUX register). * P37MUX: P37 Port Function Select Bit in the P3 Port Function Select (P3_PMUX) Register (D7-6/0x52a7) PWM waveform control The PWM waveform frequency can be set by the compare data register (0x50c2) (see Section 14.5). The duty ratio can be adjusted by the PWM duty data register (0x50c5). The timer outputs a Low level signal until the counter value matches the value of the PWM duty data register. When the counter value exceeds the value of the PWM duty data, the output pin changes to High. Once the counter counts up to the compare data register value, the counter is reset and the output pin returns to Low. Figure 14.8.1 shows the output waveform. Input clock T8ORUN Counter value 0 1 2 3 4 5 0 1 2 3 4 5 0 1 2 3 4 5 0 1 2 3 Duty match signal Compare match signal TOUT4 output (when T8OSC1_DUTY = 3 and T8OSC1_CMP = 5) Figure 14.8.1 PWM output waveform Precautions (1) When using the timer output, set the following: PWM duty data 0, compare data 1. The minimum setting value is 0 for PWM duty data and 1 for compare data. The timer output cycle is 1/2 of the input clock. (2) When the PWM duty data is set greater than the compare data, only the compare match signal will be generated. No duty match signal will be generated. In that case, the TOUT4 output is fixed to Low. 14-8 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 14 8-bit OSC1 Timer (T8OSC1) 14.9 Control Register Details Table 14.9.1: 8-bit OSC1 timer register list Address 0x50c0 0x50c1 0x50c2 0x50c3 0x50c4 0x50c5 Register name T8OSC1_CTL T8OSC1_CNT T8OSC1_CMP T8OSC1_IMSK T8OSC1_IFLG T8OSC1_DUTY 8-bit OSC1 Timer Control Register 8-bit OSC1 Timer Counter Data Register 8-bit OSC1 Timer Compare Data Register 8-bit OSC1 Timer Interrupt Mask Register 8-bit OSC1 Timer Interrupt Flag Register 8-bit OSC1 Timer PWM Duty Data Register Function Timer mode setting and timer RUN/STOP Counter data Compare data setting Interrupt mask setting Interrupt occurrence status display/resetting PWM output data setting The 8-bit OSC1 timer registers are described in detail below. These are 8-bit registers. Note: When data is written to the registers, the "Reserved" bits must always be written as 0 and not 1. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 14-9 14 8-bit OSC1 Timer (T8OSC1) 0x50c0: 8-bit OSC1 Timer Control Register (T8OSC1_CTL) Register name Address 8-bit OSC1 Timer Control Register (T8OSC1_CTL) 0x50c0 (8 bits) Bit D7-5 D4 D3-2 D1 D0 Name Function - T8ORST - T8ORMD T8ORUN reserved Timer reset reserved Count mode select Timer run/stop control D[7:5] Reserved D4 T8ORST: Timer Reset Bit Resets the 8-bit OSC1 timer. 1 (W): Reset 0 (W): Disabled 0 (R): Normally 0 when read out (default) Setting - 1 Reset 0 Ignored - 1 One shot 1 Run 0 Repeat 0 Stop Init. R/W - 0 - 0 0 Remarks - 0 when being read. W - R/W R/W Writing 1 to this bit resets the counter to 0. D[3:2] Reserved D1 T8ORMD: Count Mode Select Bit Selects the 8-bit OSC1 timer count mode. 1 (R/W): One-shot mode 0 (R/W): Repeat mode (default) Setting T8ORMD to 0 sets the 8-bit OSC1 timer to Repeat mode. In this mode, once the count starts, the 8-bit timer continues to run until stopped by the application. If the counter matches the compare data register value, the timer resets the counter and continues counting. This means the timer periodically outputs a compare match signal. Set the 8-bit OSC1 timer to this mode to generate periodic interrupts at the desired interval or to perform PWM output. Setting T8ORMD to 1 sets the 8-bit OSC1 timer to One-shot mode. In this mode, the 8-bit OSC1 timer stops automatically when the counter matches the compare data register value. This means an interrupt can be generated only once after the timer has been started. Note that the timer resets the counter and then stops after a compare match has occurred. Set the 8-bit OSC1 timer to this mode to create a specific wait time. Note: Set the count mode only while the 8-bit OSC1 timer count is stopped. D0 T8ORUN: Timer Run/Stop Control Bit Controls the timer RUN/STOP. 1 (R/W): Run 0 (R/W): Stop (default) The timer starts counting when T8ORUN is written as 1 and stops when written as 0. When the timer is stopped, the counter data is retained until reset or until the next RUN state. 14-10 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 14 8-bit OSC1 Timer (T8OSC1) 0x50c1: 8-bit OSC1 Timer Counter Data Register (T8OSC1_CNT) Register name Address 8-bit OSC1 Timer Counter Data Register (T8OSC1_CNT) D[7:0] 0x50c1 (8 bits) Bit D7-0 Name Function T8OCNT[7:0] Timer counter data T8OCNT7 = MSB T8OCNT0 = LSB Setting 0x0 to 0xff Init. R/W 0x0 Remarks R T8OCNT[7:0]: Counter Data Reads out the counter data. (Default: 0x0) This register is read-only and cannot be written to. Note: The correct counter value may not be read out (reading is unstable) if the register is read while counting is underway. Obtain the counter value by one of the following methods: * Read the counter value while the counter is halted. * Read the counter twice in succession. Treat the value as valid if the values read are identical. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 14-11 14 8-bit OSC1 Timer (T8OSC1) 0x50c2: 8-bit OSC1 Timer Compare Data Register (T8OSC1_CMP) Register name Address Bit 0x50c2 8-bit OSC1 Timer Compare (8 bits) Data Register (T8OSC1_CMP) D7-0 D[7:0] 14-12 Name Function T8OCMP[7:0] Compare data T8OCMP7 = MSB T8OCMP0 = LSB Setting Init. R/W 0x0 to 0xff 0x0 R/W Remarks T8OCMP[7:0]: Compare Data Sets the 8-bit OSC1 timer compare data. (Default: 0x0) The data set is compared against the counter data, and a compare match interrupt factor is generated if the contents match. And the counter is reset to 0. Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 14 8-bit OSC1 Timer (T8OSC1) 0x50c3: 8-bit OSC1 Timer Interrupt Mask Register (T8OSC1_IMSK) Register name Address Bit 8-bit OSC1 0x50c3 Timer Interrupt (8 bits) Mask Register (T8OSC1_IMSK) D7-1 D0 Name - T8OIE Function reserved 8-bit OSC1 timer interrupt enable 1 Enable D[7:1] Reserved D0 T8OIE: 8-bit OSC1 Timer Interrupt Enable Bit Permits or prohibits compare match interrupts. 1 (R/W): Interrupt permitted 0 (R/W): Interrupt prohibited (default) Setting - 0 Disable Init. R/W - 0 Remarks - 0 when being read. R/W Setting T8OIE to 1 permits 8-bit OSC1 timer interrupt requests to the ITC. Setting it to 0 prohibits interrupts. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 14-13 14 8-bit OSC1 Timer (T8OSC1) 0x50c4: 8-bit OSC1 Timer Interrupt Flag Register (T8OSC1_IFLG) Register name Address 8-bit OSC1 Timer Interrupt Flag Register (T8OSC1_IFLG) 0x50c4 (8 bits) Bit D7-1 D0 Name - T8OIF Function reserved 8-bit OSC1 timer interrupt flag Setting Init. R/W - 1 Cause of interrupt occurred 0 Cause of interrupt not occurred D[7:1] Reserved D0 T8OIF: 8-bit OSC1 Timer Interrupt Flag Interrupt flag indicating the compare match interrupt factor occurrence status. 1(R): Interrupt factor present 0(R): No interrupt factor (default) 1(W): Reset flag 0(W): Disabled - 0 Remarks - 0 when being read. R/W Reset by writing 1. T8OIF is the T8OSC1 module interrupt flag. Setting T8OIE (D0/T8OSC1_IMSK register) to 1 sets this to 1 when the counter matches the compare data register setting during counting. An 8-bit OSC1 timer interrupt request signal output simultaneously to the ITC generates an interrupt if the ITC and S1C17 core interrupt conditions are met. T8OIF is reset by writing as 1. Note: * To prevent interrupt recurrences, the T8OSC1 module interrupt flag T8OIF must be reset within the interrupt handler routine following an 8-bit OSC1 timer interrupt. * To prevent generating unnecessary interrupts, reset T8OIF before permitting compare match interrupts using T8OIE (D0/T8OSC1_IMSK register). 14-14 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 14 8-bit OSC1 Timer (T8OSC1) 0x50c5: 8-bit OSC1 Timer PWM Duty Data Register (T8OSC1_DUTY) Register name Address 8-bit OSC1 0x50c5 Timer PWM (8 bits) Duty Data Register (T8OSC1_DUTY) D[7:0] Bit Name Function D7-0 T8ODTY[7:0] PWM output duty data T8ODTY7 = MSB T8ODTY0 = LSB Setting Init. R/W 0x0 to 0xff 0x0 R/W Remarks T8ODTY[7:0]: PWM Output Duty Data Sets the data that determines the duty ratio of PWM waveform. (default: 0x0) The set data is compared against the counter data. If the contents match, the timer output waveform rises. If the counter data matches the compare data, the timer output waveform falls. These processes do not affect the counter data or count process. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 14-15 14 8-bit OSC1 Timer (T8OSC1) 14.10 Precautions * The 8-bit OSC1 timer clock must be output from the OSC module before the 8-bit OSC1 timer begins running. * Set the count clock and count mode only while the 8-bit OSC1 timer count is stopped. * To prevent interrupt recurrences, the T8OSC1 module interrupt flag T8OIF (D0/T8OSC1_IFLG register) must be reset within the interrupt handler routine following an 8-bit OSC1 timer interrupt. * To prevent generating unnecessary interrupts, reset T8OIF (D0/T8OSC1_IFLG register) before permitting compare match interrupts using T8OIE (D0/T8OSC1_IMSK register). * The correct counter value may not be read out (reading is unstable) if the counter data register is read while counting is underway. To obtain the counter value, read the counter data register while the counter is halted or read the counter data register twice in succession. Treat the value as valid if the values read are identical. * When using the PWM output, set the following: PWM duty data 0, compare data 1. The minimum setting value is 0 for PWM duty data and 1 for compare data. The timer output cycle is 1/2 of the input clock. * When the PWM duty data is set greater than the compare data, only the compare match signal is generated. No duty match signal is generated. In that case, the TOUT4 output is fixed to Low. 14-16 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 15 Clock Timer (CT) 15 Clock Timer (CT) 15.1 Clock Timer Overview The S1C17003 incorporates a single-channel clock timer that uses the OSC1 clock as its oscillation source. The clock timer consists of an 8-bit binary counter that uses the 256 Hz signal divided from the OSC1 clock as the input clock and allows data for each bit (128 Hz to 1 Hz) to be read out by software. The clock timer can also generate interrupts using the 32 Hz, 8 Hz, 2 Hz, and 1 Hz signals. This clock timer is normally used for various timing functions, such as clocks. Figure 15.1.1 illustrates the clock timer configuration. Clock timer OSC1 oscillator/ 256Hz division circuit To ITC Timer reset CTRST RUN/STOP control CTRUN Interrupt enable CTIE32 CTIE8 CTIE2 CTIE1 Count control circuit D0 D1 D2 128 Hz 64 Hz 32 Hz Interrupt control circuit CT_CNT D3 D4 D5 D6 D7 16 Hz 8 Hz 4 Hz 2 Hz 1 Hz Internal data bus OSC Clock timer interrupt request Figure 15.1.1: Clock timer configuration S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 15-1 15 Clock Timer (CT) 15.2 Operation Clock The clock timer uses the 256 Hz clock output by the OSC module as the operation clock. The OSC module generates this operation clock by dividing the OSC1 clock into 1/128, resulting in a frequency of 256 Hz when the OSC1 clock frequency is 32.768 kHz. The frequency described in this section will vary accordingly for other OSC1 clock frequencies. The OSC module does not include a 256 Hz clock output control bit. The 256 Hz clock is normally fed to the clock timer when the OSC1 oscillation is on. For detailed information on OSC1 oscillator circuit control, refer to "7 Oscillator Circuit (OSC)." 15-2 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 15 Clock Timer (CT) 15.3 Clock Timer Resetting Reset the clock timer by writing 1 to the CTRST bit (D4/CT_CTL register). This clears the counter to 0. * CTRST: Clock Timer Reset Bit in the Clock Timer Control (CT_CTL) Register (D4/0x5000) Apart from this operation, the counter is also cleared by initial resetting. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 15-3 15 Clock Timer (CT) 15.4 Clock Timer RUN/STOP Control Set the following items before starting the clock timer. (1) If using interrupts, set the interrupt level and permit interrupts for the clock timer. See Section 15.5. (2) Reset the timer. See Section 15.3. The clock timer includes CTRUN (D0/CT_CTL register) to control Run/Stop. * CTRUN: Clock Timer Run/Stop Control Bit in the Clock Timer Control (CT_CTL) Register (D0/0x5000) The clock timer starts operating when CTRUN is written as 1. Writing 0 to CTRUN prevents clock input and stops the operation. This control does not affect the counter (CT_CNT register) data. The counter data is retained even when the count is halted, allowing resumption of the count from that data. If CTRUN and CTRST are written as 1 simultaneously, the clock timer starts counting after the reset. Interrupt factors are generated during counting at the corresponding 32 Hz, 8 Hz, 2 Hz, and 1 Hz signal falling edges. If interrupts are permitted, interrupt requests are sent to the interrupt controller (ITC). OSC1-1/128 256Hz CTCNT0 128Hz CTCNT1 64Hz CTCNT2 32Hz CTCNT3 16Hz CTCNT4 8Hz CTCNT5 4Hz CTCNT6 2Hz CTCNT7 1Hz 32 Hz interrupt 8 Hz interrupt 2 Hz interrupt 1 Hz interrupt Figure 15.4.1: Clock timer timing chart Note: The clock timer switches to Run/Stop mode when data is written to CTRUN synchronized with the 256 Hz signal falling edge. When 0 is written to CTRUN, the timer switches to Stop state after counting an additional "+1." 1 is retained for CTRUN reading until the timer actually stops. Figure 15.4.2 shows the Run/Stop control timing chart. 256Hz CTRUN(RD) CTRUN(WR) CT_CNT register 0x57 0x58 0x59 0x5a 0x5b 0x5c Figure 15.4.2: Run/Stop control timing chart 15-4 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 15 Clock Timer (CT) 15.5 Clock Timer Interrupts The CT module includes functions for generating the following four kinds of interrupts: 32 Hz, 8 Hz, 2 Hz, 1 Hz interrupts The CT module outputs a single interrupt signal shared by the above four interrupt factors to the interrupt controller (ITC). The interrupt flag within the CT module should be read to identify the interrupt factor that occurred. 32 Hz, 8 Hz, 2 Hz, 1 Hz interrupts Generated at the 32 Hz, 8 Hz, 2 Hz, and 1 Hz signal falling edges, these interrupt requests set the following interrupt flags in the CT module to 1. CTIF32: 32 Hz Interrupt Flag in the Clock Timer Interrupt Flag (CT_IFLG) Register (D3/0x5003) CTIF8: 8 Hz Interrupt Flag in the Clock Timer Interrupt Flag (CT_IFLG) Register (D2/0x5003) CTIF2: 2 Hz Interrupt Flag in the Clock Timer Interrupt Flag (CT_IFLG) Register (D1/0x5003) CTIF1: 1 Hz Interrupt Flag in the Clock Timer Interrupt Flag (CT_IFLG) Register (D0/0x5003) To use these interrupts, set the following interrupt enable bits to 1 for the corresponding interrupt flags. If the interrupt enable bits are set to 0 (default), the interrupt flag will not be set to 1, and the interrupt requests for this factor will not be sent to the ITC. CTIE32: 32 Hz Interrupt Enable Bit in the Clock Timer Interrupt Mask (CT_IMSK) Register (D3/0x5002) CTIE8: 8 Hz Interrupt Enable Bit in the Clock Timer Interrupt Mask (CT_IMSK) Register (D2/0x5002) CTIE2: 2 Hz Interrupt Enable Bit in the Clock Timer Interrupt Mask (CT_IMSK) Register (D1/0x5002) CTIE1: 1 Hz Interrupt Enable Bit in the Clock Timer Interrupt Mask (CT_IMSK) Register (D0/0x5002) The CT module outputs an interrupt request to the ITC if the CTIF* is set to 1. This interrupt request signal sets the clock timer interrupt flag inside the ITC to 1 and generates an interrupt if the ITC and S1C17 core interrupt conditions are met. Check the frequency of a clock timer interrupt by reading CTIF* as part of the clock timer interrupt processing routine. Note: * To prevent interrupt recurrences, the CT module interrupt flag CTIF*must be reset within the interrupt processing routine following a clock timer interrupt. * To prevent generating unnecessary interrupts, reset the corresponding CTIF* before permitting clock timer interrupts from CTIE*. Interrupt vectors The clock timer interrupt vector numbers and vector addresses are listed below. Vector number: 7 (0x07) Vector address: TTBR + 0x1c Other interrupt settings The ITC allows the priority of clock timer interrupts to be set between level 0 (the default value) and level 7. To generate actual interrupts, the PSR (S1C17 core internal processor status register) IE (interrupt enable) bit must be set to 1. For more information on interrupt processing, see "6 Interrupt Controller (ITC)." S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 15-5 15 Clock Timer (CT) 15.6 Control Register Details Table 15.6.1: Clock timer registers list Address 0x5000 0x5001 0x5002 0x5003 Register name CT_CTL CT_CNT CT_IMSK CT_IFLG Clock Timer Control Register Clock Timer Counter Register Clock Timer Interrupt Mask Register Clock Timer Interrupt Flag Register Function Timer resetting and Run/Stop control Counter data Interrupt mask setting Interrupt occurrence status display/resetting The clock timer registers are described in detail below. These are 8-bit registers. Note: When data is written to the registers, the "Reserved" bits must always be written as 0 and not 1. 15-6 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 15 Clock Timer (CT) 0x5000: Clock Timer Control Register (CT_CTL) Register name Address Bit 0x5000 Clock Timer Control Register (8 bits) (CT_CTL) D7-5 D4 D3-1 D0 Name - CTRST - CTRUN Function reserved Clock timer reset reserved Clock timer run/stop control D[7:5] Reserved D4 CTRST: Clock Timer Reset Bit Resets the clock timer. 1 (W): Reset 0 (W): Disabled 0 (R): Normally 0 when read out (default) Setting - 1 Reset 0 Ignored - 1 Run 0 Stop Init. R/W - 0 - 0 Remarks - 0 when being read. W - R/W Writing 1 to this bit resets the counter to 0x0. When reset in Run state, the clock timer restarts immediately after resetting. The reset data 0x0 is retained when in Stop state. D[3:1] Reserved D0 CTRUN: Clock Timer Run/Stop Control Bit Controls the clock timer Run/Stop. 1 (R/W): Run 0 (R/W): Stop (default) The clock timer starts counting when CTRUN is written as 1 and stops when written as 0. The counter data is retained at Stop state until a reset or the next Run state. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 15-7 15 Clock Timer (CT) 0x5001: Clock Timer Counter Register (CT_CNT) Register name Address Bit 0x5001 Clock Timer Counter Register (8 bits) (CT_CNT) D7-0 D[7:0] Name Function CTCNT[7:0] Clock timer counter value Setting 0x0 to 0xff Init. R/W 0 Remarks R CTCNT[7:0]: Clock Timer Counter Value Reads out the counter data. (Default: 0xff) This register is read-only and cannot be written to. The bits correspond to various frequencies, as follows: D7: 1Hz D6: 2Hz D5: 4Hz D4: 8Hz D3: 16Hz D2: 32Hz D1: 64Hz D0: 128Hz Note: The correct counter value may not be read out (reading is unstable) if the register is read while counting is underway. Obtain the counter value by one of the following methods: * Read the counter value while the counter is halted. * Read the counter twice in succession. Treat the value as valid if the values read are identical. 15-8 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 15 Clock Timer (CT) 0x5002: Clock Timer Interrupt Mask Register (CT_IMSK) Register name Address Clock Timer Interrupt Mask Register (CT_IMSK) 0x5002 (8 bits) Bit D7-4 D3 D2 D1 D0 Name - CTIE32 CTIE8 CTIE2 CTIE1 Function reserved 32 Hz interrupt enable 8 Hz interrupt enable 2 Hz interrupt enable 1 Hz interrupt enable Setting - 1 1 1 1 Enable Enable Enable Enable 0 0 0 0 Disable Disable Disable Disable Init. R/W - 0 0 0 0 Remarks - 0 when being read. R/W R/W R/W R/W This register permits or prohibits interrupt requests individually for the clock timer 32 Hz, 8 Hz, 2 Hz, and 1 Hz signals. Setting the CTIE*bit to 1 permits clock timer interrupts for the corresponding frequency signal falling edge, while setting to 0 prohibits interrupts. To enable interrupt generation, the ITC clock timer interrupt enable bits must also be set to permit interrupts. D[7:4] Reserved D3 CTIE32: 32 Hz Interrupt Enable Bit Permits or prohibits 32 Hz signal interrupts. 1 (R/W): Interrupt permitted 0 (R/W): Interrupt prohibited (default) D2 CTIE8: 8 Hz Interrupt Enable Bit Permits or prohibits 8 Hz signal interrupts. 1 (R/W): Interrupt permitted 0 (R/W): Interrupt prohibited (default) D1 CTIE2: 2 Hz Interrupt Enable Bit Permits or prohibits 2 Hz signal interrupts. 1 (R/W): Interrupt permitted 0 (R/W): Interrupt prohibited (default) D0 CTIE1: 1 Hz Interrupt Enable Bit Permits or prohibits 1 Hz signal interrupts. 1 (R/W): Interrupt permitted 0 (R/W): Interrupt prohibited (default) S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 15-9 15 Clock Timer (CT) 0x5003: Clock Timer Interrupt Flag Register (CT_IFLG) Register name Address Clock Timer Interrupt Flag Register (CT_IFLG) 0x5003 (8 bits) Bit D7-4 D3 D2 D1 D0 Name - CTIF32 CTIF8 CTIF2 CTIF1 Function reserved 32 Hz interrupt flag 8 Hz interrupt flag 2 Hz interrupt flag 1 Hz interrupt flag Setting Init. R/W - 1 Cause of interrupt occurred 0 Cause of interrupt not occurred - 0 0 0 0 Remarks - 0 when being read. R/W Reset by writing 1. R/W R/W R/W This register indicates the occurrence state of interrupt factors due to clock timer 32 Hz, 8 Hz, 2 Hz, and 1 Hz signals. If a clock timer interrupt occurs, identify the interrupt factor (frequency) by reading the interrupt flag in this register. CTIF* are CT module interrupt flags corresponding to the individual 32 Hz, 8 Hz, 2 Hz, and 1 Hz interrupts. It is set to 1 at the falling edge of each signal if CTIE* (CT_IMSK register) is set to 1. The clock timer interrupt request signal is output to the ITC at the same time. This interrupt request signal generates an interrupt if the ITC and S1C17 core interrupt conditions are met. CTIF* is reset by writing as 1. Note: * To prevent interrupt recurrences, the CT module interrupt flag CTIF*must be reset within the interrupt processing routine following a clock timer interrupt. * To prevent generating unnecessary interrupts, CTIF* must be reset before permitting clock timer interrupts using CTIE.* D[7:4] Reserved D3 CTIF32: 32 Hz Interrupt Flag Interrupt flag indicating the 32 Hz interrupt factor occurrence status. 1(R): Interrupt factor present 0(R): No interrupt factor (default) 1(W): Reset flag 0(W): Disabled Setting CTIE32 (D3/CT_IMSK register) to 1 sets CTIF32 to 1 at the 32 Hz signal falling edge. D2 CTIF8: 8 Hz Interrupt Flag Interrupt flag indicating the 8 Hz interrupt factor occurrence status. 1(R): Interrupt factor present 0(R): No interrupt factor (default) 1(W): Reset flag 0(W): Disabled Setting CTIE8 (D2/CT_IMSK register) to 1 sets CTIF8 to 1 at the 8 Hz signal falling edge. D1 CTIF2: 2 Hz Interrupt Flag Interrupt flag indicating the 2 Hz interrupt factor occurrence status. 1(R): Interrupt factor present 0(R): No interrupt factor (default) 1(W): Reset flag 0(W): Disabled Setting CTIE2 (D1/CT_IMSK register) to 1 sets CTIF2 to 1 at the 2 Hz signal falling edge. D0 CTIF1: 1 Hz Interrupt Flag Interrupt flag indicating the 1 Hz interrupt factor occurrence status. 1(R): Interrupt factor present 0(R): No interrupt factor (default) 1(W): Reset flag 0(W): Disabled Setting CTIE1 (D0/CT_IMSK register) to 1 sets CTIF1 to 1 at the 1 Hz signal falling edge. 15-10 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 15 Clock Timer (CT) 15.7 Precautions * The OSC1 oscillator circuit must be set to On before operating the clock timer. * To prevent generating unnecessary interrupts, reset the CT_IFLG register interrupt flag before permitting clock timer interrupts by the CT_IMSK register. * The clock timer switches to Run/Stop mode when data is written to CTRUN synchronized with the 256 Hz signal falling edge. When 0 is written to CTRUN (D0/CT_CTL register), the timer switches to Stop state after counting an additional "+1." 1 is retained for CTRUN reading until the timer actually stops. Figure 15.7.1 shows the Run/Stop control timing chart. 256Hz CTRUN(RD) CTRUN(WR) CT_CNT register 0x57 0x58 0x59 0x5a 0x5b 0x5c Figure 15.7.1: Run/Stop control timing chart * Executing the slp instruction will destabilize a running clock timer (CTRUN = 1) during recovery from SLEEP state. When switching to SLEEP state, set the clock timer to STOP (CTRUN = 0) before executing the slp instruction. * The correct counter value may not be read out (reading is unstable) if the counter register is read while counting is underway. Read the counter register while the counter is halted or read the counter register twice in succession. Treat the value as valid if the values read are identical. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 15-11 15 Clock Timer (CT) This page intentionally left blank. 15-12 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 16 Stopwatch Timer (SWT) 16 Stopwatch Timer (SWT) 16.1 Stopwatch Timer Overview The S1C17003 incorporates a 1/100-second and 1/10-second stopwatch timer. The stopwatch timer consists of a 4-bit 2-stage BCD counter (1/100 and 1/10 second) that uses the 256 Hz signal divided from the OSC1 clock as the input clock and allows count data to be read out by software. The stopwatch timer can also generate interrupts using the 100 Hz (approximately 100 Hz), 10 Hz (approximately 10 Hz), and 1 Hz signals. Figure 16.1.1 illustrates the stopwatch timer configuration. Stopwatch timer OSC1 oscillator/ 256Hz division circuit Reset SWTRST RUN/STOP control SWTRUN Interrupt enable To ITC SIE100 SIE10 SIE1 Count control circuit Interrupt control circuit Feedback division circuit 1/100-second 4-bit BCD counter Approximate 100 Hz Approximate 10 Hz 1Hz 1/10-second 4-bit BCD counter Internal data bus OSC Interrupt request Figure 16.1.1: Stopwatch timer configuration S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 16-1 16 Stopwatch Timer (SWT) 16.2 BCD Counters The stopwatch counter consists of 1/100-second and 1/10-second 4-bit BCD counters. The count value can be read from the SWT_BCNT register. 1/100-second counter * BCD100[3:0]: 1/100 Sec. BCD Counter Value in the Stopwatch Timer BCD Counter (SWT_BCNT) Register (D[3:0]/0x5021) 1/10-second counter * BCD10[3:0]: 1/10 Sec. BCD Counter Value in the Stopwatch Timer BCD Counter (SWT_BCNT) Register (D[7:4]/0x5021) Count-up Pattern A feedback division circuit is used to generate 100 Hz, 10 Hz, and 1 Hz signals from the 256 Hz clock. The counter count-up pattern varies as shown in Figure 16.2.1. 1/100-second counter count-up pattern 1 1/100-second counter count-up pattern 2 256Hz Approximate 100 Hz (Feedback division circuit output) 1/100-second counter 3 256 2 256 3 256 2 256 3 256 2 256 3 256 2 256 3 256 2 256 3 256 3 256 3 256 2 256 3 256 2 256 3 256 2 256 3 256 2 256 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 25 seconds 256 Approximate 10 Hz (1/100-second counter output) 26 seconds 256 1/10-second counter count-up pattern 26 seconds 256 26 seconds 256 25 seconds 256 25 seconds 256 26 seconds 256 26 seconds 256 25 seconds 256 25 seconds 256 26 seconds 256 26 seconds 256 0 1 2 3 4 5 6 7 8 9 Approximate 10 Hz (1/100-second counter output) 1/10-second counter 1Hz (1/10-second counter output) 26 x 6 + 25 x 4 = 1 second 256 256 Figure 16.2.1: Stopwatch timer count-up patterns The feedback division circuit generates an approximate 100 Hz signal at 2/256-second and 3/256-second intervals from the 256 Hz signal fed from the OSC module. The 1/100-second counter counts the approximate 100 Hz signal output by the feedback division circuit and generates an approximate 10 Hz signal at 25/256-second and 26/256-second intervals. Count-up will be pseudo 1/100-second counting at 2/256-second and 3/256-second intervals. The 1/10-second counter counts the approximate 10 Hz signal generated by the 1/100-second counter at a ratio of 4:6, and generates a 1 Hz signal. Count-up will be pseudo 1/10-second counting at 25/256-second and 26/256-second intervals. 16-2 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 16 Stopwatch Timer (SWT) 16.3 Operation Clock The stopwatch timer uses the 256 Hz clock output by the OSC module as the operation clock. The OSC module generates this operation clock by dividing the OSC1 clock into 1/128, resulting in a frequency of 256 Hz when the OSC1 clock frequency is 32.768 kHz. The frequency described in this section will vary accordingly for other OSC1 clock frequencies. The OSC module does not include a 256 Hz clock output control bit. The 256 Hz clock is normally fed to the stopwatch timer when the OSC1 oscillation is on. For detailed information on OSC1 oscillator circuit control, refer to "7 Oscillator Circuit (OSC)." S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 16-3 16 Stopwatch Timer (SWT) 16.4 Stopwatch Timer Resetting Reset the stopwatch timer by writing 1 to the SWTRST bit (D4/SWT_CTL register). This clears the counter to 0. * SWTRST: Stopwatch Timer Reset Bit in the Stopwatch Timer Control (SWT_CTL) Register (D4/0x5020) Apart from this operation, the counter is also cleared by initial resetting. 16-4 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 16 Stopwatch Timer (SWT) 16.5 Stopwatch Timer RUN/STOP Control Set the following items before starting the stopwatch timer. (1) If using interrupts, set the interrupt level and permit interrupts for the stopwatch timer. See Section 16.6. (2) Reset the timer. See Section 16.4. The stopwatch timer includes SWTRUN (D0/SWT_CTL register) to control Run/Stop. * SWTRUN: Stopwatch Timer Run/Stop Control Bit in the Stopwatch Timer Control (SWT_CTL) Register (D0/0x5020) The stopwatch timer starts counting when SWTRUN is written as 1. Writing 0 to SWTRUN prevents clock input and stops the count. This control does not affect the counter (SWT_BCNT register) data. The counter data is retained even when the count is halted, allowing resumption of the count from that data. If SWTRUN and SWTRST are written as 1 simultaneously, the stopwatch timer starts counting after the reset. Interrupt factors are generated during counting at the corresponding 100 Hz (approximate 100 Hz), 10 Hz (approximate 10 Hz), and 1 Hz signal falling edges. If interrupts are permitted, interrupt requests are sent to the interrupt controller (ITC). 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 BCD100[0] 1/100BCD100[1] second counter BCD100[2] BCD data BCD100[3] 100 Hz interrupt 10 Hz interrupt 1/10second counter BCD data BCD10[0] BCD10[1] BCD10[2] BCD10[3] 1 Hz interrupt Figure 16.5.1: Stopwatch timer timing chart Note: The stopwatch timer switches to Run/Stop mode when data is written to SWTRUN synchronized with the 256 Hz signal falling edge. When 0 is written to SWTRUN, the timer switches to Stop state after counting an additional "+1." 1 is retained for SWTRUN reading until the timer actually stops. Figure 16.5.2 shows the Run/Stop control timing chart. 256Hz SWTRUN(RD) SWTRUN(WR) SWT_BCNT register 27 28 29 30 31 32 Figure 16.5.2: Run/Stop control timing chart S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 16-5 16 Stopwatch Timer (SWT) 16.6 Stopwatch Timer Interrupts The SWT module includes functions for generating the following three kinds of interrupts: * 100 Hz interrupt * 10 Hz interrupt * 1 Hz interrupt The SWT module outputs a single interrupt signal shared by the above three interrupt factors to the interrupt controller (ITC). The interrupt flag within the SWT module should be read to identify the interrupt factor that occurred. 100 Hz, 10 Hz, 1 Hz interrupts Generated at the 100 Hz (approximate 100 Hz), 10 Hz (approximate 10 Hz), and 1 Hz signal falling edges, these interrupt requests set the following interrupt flags in the SWT module to 1. SIF1: 1 Hz Interrupt Flag in the Stopwatch Timer Interrupt Flag (SWT_IFLG) Register (D2/0x5023) SIF10: 10 Hz Interrupt Flag in the Stopwatch Timer Interrupt Flag (SWT_IFLG) Register (D1/0x5023) SIF100: 100 Hz Interrupt Flag in the Stopwatch Timer Interrupt Flag (SWT_IFLG) Register (D0/0x5023) To use these interrupts, set the following interrupt enable bits to 1 for the corresponding interrupt flags. If the interrupt enable bits are set to 0 (default), the interrupt flag will not be set to 1, and the interrupt requests for this factor will not be sent to the ITC. SIE1: 1 Hz Interrupt Enable Bit in the Stopwatch Timer Interrupt Mask (SWT_IMSK) Register (D2/0x5022) SIE10: 10 Hz Interrupt Enable Bit in the Stopwatch Timer Interrupt Mask (SWT_IMSK) Register (D1/0x5022) SIE100: 100 Hz Interrupt Enable Bit in the Stopwatch Timer Interrupt Mask (SWT_IMSK) Register (D0/0x5022) The SWT module outputs an interrupt request to the ITC if the SIF* is set to 1. This interrupt request signal generates an interrupt if the ITC and S1C17 core interrupt conditions are met. Check the frequency of a stopwatch timer interrupt by reading SIF* as part of the stopwatch timer interrupt processing routine. Note: * To prevent interrupt recurrences, the SWT module interrupt flag SIF*must be reset within the interrupt processing routine following a stopwatch timer interrupt. * To prevent generating unnecessary interrupts, reset the corresponding SIF* before permitting stopwatch timer interrupt from SIE*. Interrupt vectors The stopwatch timer interrupt vector numbers and vector addresses are listed below. Vector number: 6 (0x06) Vector address: TTBR + 0x18 Other interrupt settings The ITC allows the priority of stopwatch timer interrupts to be set between level 0 (the default value) and level 7. To generate actual interrupts, the PSR (S1C17 core internal processor status register) IE (interrupt enable) bit must be set to 1. For more information on interrupt processing, see "6 Interrupt Controller (ITC)." 16-6 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 16 Stopwatch Timer (SWT) 16.7 Control Register Details Table 16.7.1 Stopwatch timer register list Address 0x5020 0x5021 0x5022 0x5023 Register name SWT_CTL SWT_BCNT SWT_IMSK SWT_IFLG Stopwatch Timer Control Register Stopwatch Timer BCD Counter Register Stopwatch Timer Interrupt Mask Register Stopwatch Timer Interrupt Flag Register Function Timer resetting and Run/Stop control BCD counter data Interrupt mask setting Interrupt occurrence status display/resetting The stopwatch timer registers are described in detail below. These are 8-bit registers. Note: When data is written to the registers, the "Reserved" bits must always be written as 0 and not 1. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 16-7 16 Stopwatch Timer (SWT) 0x5020: Stopwatch Timer Control Register (SWT_CTL) Register name Address Stopwatch Timer Control Register (SWT_CTL) 0x5020 (8 bits) Bit D7-5 D4 D3-1 D0 Name - SWTRST - SWTRUN Function Setting reserved Stopwatch timer reset reserved Stopwatch timer run/stop control - D[7:5] Reserved D4 SWTRST: Stopwatch Timer Reset Bit Resets the stopwatch timer. 1 (W): Reset 0 (W): Disabled 0 (R): Normally 0 when read out (default) 1 Reset 0 Ignored - 1 Run 0 Stop Init. R/W - 0 - 0 Remarks - 0 when being read. W - R/W Writing 1 to this bit resets the counter to 0x0. When reset in Run state, the stopwatch timer restarts immediately after resetting. The reset data 0x0 is retained when in Stop state. D[3:1] Reserved D0 SWTRUN: Stopwatch Timer Run/Stop Control Bit Controls the stopwatch timer Run/Stop. 1 (R/W): Run 0 (R/W): Stop (default) The stopwatch timer starts counting when SWTRUN is written as 1 and stops when written as 0. The counter data is retained at Stop state until a reset or the next Run state. 16-8 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 16 Stopwatch Timer (SWT) 0x5021: Stopwatch Timer BCD Counter Register (SWT_BCNT) Register name Address Stopwatch Timer BCD Counter Register (SWT_BCNT) 0x5021 (8 bits) Bit Name Function Setting Init. R/W D7-4 BCD10[3:0] 1/10 sec. BCD counter value 0 to 9 0 R D3-0 BCD100[3:0] 1/100 sec. BCD counter value 0 to 9 0 R D[7:4] BCD10[3:0]: 1/10 Sec. BCD Counter Value Read the 1/10-second counter BCD data. (Default: 0) This register is read-only and cannot be written to. D[3:0] BCD100[3:0]: 1/100 Sec. BCD Counter Value Read the 1/100-second counter BCD data. (Default: 0) This register is read-only and cannot be written to. Remarks Note: The correct counter value may not be read out (reading is unstable) if the register is read while counting is underway. Obtain the counter value by one of the following methods: * Read the counter value while the counter is halted. * Read the counter twice in succession. Treat the value as valid if the values read are identical. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 16-9 16 Stopwatch Timer (SWT) 0x5022: Stopwatch Timer Interrupt Mask Register (SWT_IMSK) Register name Address Stopwatch Timer Interrupt Mask Register (SWT_IMSK) 0x5022 (8 bits) Bit D7-3 D2 D1 D0 Name - SIE1 SIE10 SIE100 Function reserved 1 Hz interrupt enable 10 Hz interrupt enable 100 Hz interrupt enable Setting - 1 Enable 1 Enable 1 Enable 0 Disable 0 Disable 0 Disable Init. R/W - 0 0 0 Remarks - 0 when being read. R/W R/W R/W This register permits or prohibits interrupt requests individually for the stopwatch timer 100 Hz, 10 Hz, and 1 Hz signals. Setting the SIE*bit to 1 permits stopwatch timer interrupts for the corresponding frequency signal falling edge, while setting to 0 prohibits interrupts. To enable interrupt generation, the ITC stopwatch timer interrupt enable bits must also be set to permit interrupts. D[7:3] Reserved D2 SIE1: 1 Hz Interrupt Enable Bit Permits or prohibits 1 Hz signal interrupts. 1 (R/W): Interrupt permitted 0 (R/W): Interrupt prohibited (default) D1 SIE10: 10 Hz Interrupt Enable Bit Permits or prohibits 10 Hz signal interrupts. 1 (R/W): Interrupt permitted 0 (R/W): Interrupt prohibited (default) D0 SIE100: 100 Hz Interrupt Enable Bit Permits or prohibits 100 Hz signal interrupts. 1 (R/W): Interrupt permitted 0 (R/W): Interrupt prohibited (default) 16-10 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 16 Stopwatch Timer (SWT) 0x5023: Stopwatch Timer Interrupt Flag Register (SWT_IFLG) Register name Address Stopwatch Timer Interrupt Flag Register (SWT_IFLG) 0x5023 (8 bits) Bit D7-3 D2 D1 D0 Name - SIF1 SIF10 SIF100 Function reserved 1 Hz interrupt flag 10 Hz interrupt flag 100 Hz interrupt flag Setting - 1 Cause of interrupt occurred 0 Cause of interrupt not occurred Init. R/W - 0 0 0 Remarks - 0 when being read. R/W Reset by writing 1. R/W R/W This register indicates the occurrence state of interrupt factors due to stopwatch timer 100 Hz, 10 Hz, and 1 Hz signals. If a stopwatch timer interrupt occurs, identify the interrupt factor (frequency) by reading the interrupt flag in this register. SIF* are SWT module interrupt flags corresponding to the individual 100 Hz, 10 Hz, and 1 Hz interrupts. It is set to 1 at the falling edge of each signal if SIE* (SWT_IMSK register) is set to 1. The stopwatch timer interrupt request signal is output to the ITC at the same time. This interrupt request signal generates an interrupt if the ITC and S1C17 core interrupt conditions are met. SIF* is reset by writing as 1. Note: * To prevent interrupt recurrences, the SWT module interrupt flag SIF*must be reset within the interrupt processing routine following a stopwatch timer interrupt. * To prevent generating unnecessary interrupts, SIF* must be reset before permitting clock timer interrupts using SIE.* D[7:3] Reserved D2 SIF1: 1 Hz Interrupt Flag Interrupt flag indicating the 1 Hz interrupt factor occurrence status. 1(R): Interrupt factor present 0(R): No interrupt factor (default) 1(W): Reset flag 0(W): Disabled Setting SIE1 (D2/SWT_IMSK register) to 1 sets SIF1 to 1 at the 1 Hz signal falling edge. D1 SIF10: 10 Hz Interrupt Flag Interrupt flag indicating the 10 Hz interrupt factor occurrence status. 1(R): Interrupt factor present 0(R): No interrupt factor (default) 1(W): Reset flag 0(W): Disabled Setting SIE10 (D1/SWT_IMSK register) to 1 sets SIF10 to 1 at the 10 Hz signal falling edge. D0 SIF100: 100 Hz Interrupt Flag Interrupt flag indicating the 100 Hz interrupt factor occurrence status. 1(R): Interrupt factor present 0(R): No interrupt factor (default) 1(W): Reset flag 0(W): Disabled Setting SIE100 (D0/SWT_IMSK register) to 1 sets SIF100 to 1 at the 100 Hz signal falling edge. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 16-11 16 Stopwatch Timer (SWT) 16.8 Precautions * The OSC1 oscillator circuit must be set to On before operating the stopwatch timer. * To prevent interrupt recurrences, the SWT_IFLG register interrupt flag must be reset within the interrupt processing routine following a stopwatch timer interrupt. * To prevent generating unnecessary interrupts, reset the SWT_IFLG register interrupt flag before permitting stopwatch timer interrupts by the SWT_IMSK register. * The stopwatch timer switches to Run/Stop mode when data is written to SWTRUN (D0/SWT_CTL resister) synchronized with the 256 Hz signal falling edge. When 0 is written to SWTRUN, the timer switches to Stop state after counting an additional "+1." 1 is retained for SWTRUN reading until the timer actually stops. Figure 16.8.1 shows the Run/Stop control timing chart. 256Hz SWTRUN(RD) SWTRUN(WR) SWT_BCNT register 27 28 29 30 31 32 Figure 16.8.1: Run/Stop control timing chart * Executing the slp instruction will destabilize a running stopwatch timer (SWTRUN = 1) during recovery from SLEEP state. When switching to SLEEP state, set the stopwatch timer to STOP (SWTRUN = 0) before executing the slp instruction. * The correct counter value may not be read out (reading is unstable) if the counter register is read while counting is underway. To obtain the counter value, read the counter register while the counter is halted or read the counter register twice in succession. Treat the value as valid if the values read are identical. 16-12 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 17 Watchdog Timer (WDT) 17 Watchdog Timer (WDT) 17.1 Watchdog Timer Overview The S1C17003 incorporates a watchdog timer that uses the OSC1 oscillator circuit as its oscillation source. The watchdog timer generates an NMI or reset (selectable via software) to the CPU if not reset within 131,072/fOSC1 seconds (4 seconds when fOSC1 = 32.768 kHz). Reset the watchdog timer via software within this cycle to prevent NMI/resets, which in turn enables runaway detection for programs that do not pass through the processing routine. Figure 17.1.1 illustrates the watchdog timer block diagram. OSC Watchdog timer reset OSC1 oscillation/ 256Hz division circuit Reset NMI 10-bit counter WDTRUN[3:0] Run/Stop control Watchdog timer WDTRST Interrupt control circuit WDTMD NMI/Reset mode selection Figure 17.1.1: Watchdog timer block diagram S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 17-1 17 Watchdog Timer (WDT) 17.2 Operation Clock The watchdog timer uses the 256 Hz clock output by the OSC module as the operation clock. The OSC module generates this operation clock by dividing the OSC1 clock into 1/128, resulting in a frequency of 256 Hz when the OSC1 clock frequency is 32.768 kHz. The frequency described in this section will vary accordingly for other OSC1 clock frequencies. The OSC module does not include a 256 Hz clock output control bit. The 256 Hz clock is normally fed to the watchdog timer when the OSC1 oscillation is on. For detailed information on OSC1 oscillator circuit control, refer to "7 Oscillator Circuit (OSC)." 17-2 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 17 Watchdog Timer (WDT) 17.3 Watchdog Timer Control 17.3.1 NMI/Reset Mode Selection WDTMD (D1/WDT_ST register) is used to select whether an NMI signal or a reset signal is output when the watchdog timer has not been reset within the NMI/Reset occurrence cycle. WDTMD: NMI/Reset Mode Select Bit in the Watchdog Timer Status (WDT_ST) Register (D1/0x5041) To generate an NMI, set WDTMD to 0 (default). Set to 1 to generate a reset. 17.3.2 Watchdog Timer Run/Stop Control The watchdog timer starts counting when a value other than 0b1010 is written to WDTRUN[3:0] (D[3:0]/ WDT_CTL register) and stops when 0b1010 is written. WDTRUN[3:0]: Watchdog Timer Run/Stop Control Bits in the Watchdog Timer Control (WDT_CTL) Register (D[3:0]/0x5040) Initial resetting sets WDTRUN[3:0] to 0b1010 and stops the watchdog timer. Since an NMI or Reset may be generated immediately after running depending on the counter value, the watchdog timer should also be reset concurrently (before running the watchdog timer), as explained in the following section. 17.3.3 Watchdog Timer Resetting To reset the watchdog timer, write 1 to WDTRST (D4/WDT_CTL register). * WDTRST: Watchdog Timer Reset Bit in the Watchdog Timer Control (WDT_CTL) Register (D4/0x5040) A location should be provided for periodically processing the routine for resetting the watchdog timer before an NMI or Reset is generated when using the watchdog timer. Process this routine within 131,072/fOSC1 second (4 seconds when fOSC1 = 32.768 kHz) cycle. After resetting, the watchdog timer starts counting with a new NMI/Reset generation cycle. If the watchdog timer is not reset within the NMI/Reset generation cycle for any reason, the CPU is switched to interrupt processing by NMI or resetting, an interrupt vector is read out, and an interrupt processing routine is executed. The reset and NMI vector addresses are TTBR + 0x0 and TTBR + 0x08. If the counter overflows and generates an NMI without the watchdog timer being reset, WDTST (D0/WDT_ST register) is set to 1. WDTST: NMI Status Bit in the Watchdog Timer Status (WDT_ST) Register (D0/0x5041) This bit is provided to confirm that the watchdog timer was the source of the NMI. The WDTST set to 1 is cleared to 0 by resetting the watchdog timer. 17.3.4 Operation in Standby Mode HALT mode The watchdog timer operates in HALT mode, as the clock is fed. HALT mode is therefore canceled by an NMI or Reset if it continues for more than the NMI/Reset cycle. To disable the watchdog timer while in HALT mode, stop the watchdog timer by writing 0b1010 to WDTRUN[3:0] before executing the halt instruction. Reset the watchdog timer before resuming operations after HALT mode is canceled. SLEEP mode The clock fed from the OSC module is stopped in SLEEP mode, which also stops the watchdog timer. To prevent generation of an unnecessary NMI or Reset after canceling SLEEP mode, reset the watchdog timer before executing the slp instruction. The watchdog should also be stopped as required using WDTRUN[3:0]. WDTRUN[3:0]. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 17-3 17 Watchdog Timer (WDT) 17.4 Control Register Details Table 17.4.1 Watchdog timer register list Address 0x5040 0x5041 Register name WDT_CTL WDT_ST Watchdog Timer Control Register Watchdog Timer Status Register Function Timer reset and Run/Stop control Timer mode setting and NMI status display The watchdog timer registers are described in detail below. These are 8-bit registers. Note: When data is written to the registers, the "Reserved" bits must always be written as 0 and not 1. 17-4 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 17 Watchdog Timer (WDT) 0x5040: Watchdog Timer Control Register (WDT_CTL) Register name Address Watchdog Timer Control Register (WDT_CTL) 0x5040 (8 bits) Bit D7-5 D4 D3-0 Name Function - reserved WDTRST Watchdog timer reset WDTRUN[3:0] Watchdog timer run/stop control D[7:5] Reserved D4 WDTRST: Watchdog Timer Reset Bit Resets the watchdog timer. 1 (W): Reset 0 (W): Disabled 0 (R): Normally 0 when read out (default) Setting - 1 Reset 0 Ignored Other than 1010 1010 Run Stop Init. R/W Remarks - - 0 when being read. 0 W 1010 R/W To use the watchdog timer, it must be reset by writing 1 to this bit within the NMI/Reset generation cycle (4 seconds when fOSC1 = 32.768 kHz). This resets the up-counter to 0 and starts counting with a new NMI/Reset generation cycle. D[3:0] WDTRUN[3:0]: Watchdog Timer Run/Stop Control Bits Controls the watchdog timer Run/Stop. Values other than 0b1010 (R/W): Run 0b1010 (R/W): Stop (default) The watchdog timer must also be reset to prevent generation of an unnecessary NMI or Reset while the watchdog timer operates. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 17-5 17 Watchdog Timer (WDT) 0x5041: Watchdog Timer Status Register (WDT_ST) Register name Address Watchdog Timer Status Register (WDT_ST) 0x5041 (8 bits) Bit D7-2 D1 D0 Name Function - reserved WDTMD WDTST NMI/Reset mode select NMI status D[7:2] Reserved D1 WDTMD: NMI/Reset Mode Select Bit Selects NMI or Reset generation on counter overflow. 1 (R/W): Reset 0 (R/W): NMI (default) Setting Init. R/W - - - 1 Reset 0 NMI 1 NMI occurred 0 Not occurred 0 0 R/W R Remarks 0 when being read. Setting this bit to 1 outputs a reset signal when the counter overflows. Setting to 0 outputs an NMI signal. D0 WDTST: NMI Status Bit Indicates a counter overflow and NMI occurrence. 1 (R): NMI occurred (counter overflow) 0 (R): NMI did not occur (default) This bit confirms that the watchdog timer was the source of the NMI. The WDTST set to 1 is cleared to 0 by resetting the watchdog timer. This is also set by a counter overflow if reset output is selected, but is cleared by initial resetting and cannot be confirmed. 17-6 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 17 Watchdog Timer (WDT) 17.5 Precautions * When the watchdog timer is running, this must be reset by software within a 131,072 fOSC1 seconds (4 seconds when fOSC1 = 32.768 kHz) cycle. * The watchdog timer must also be reset to prevent generation of an unnecessary NMI or Reset while the watchdog timer operates. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 17-7 18 UART 18 UART 18.1 UART Configuration The S1C17003 includes dual channel UART. The UART transfers data asynchronously with external serial devices at a rate of 150 to 460800bps. It includes 2-byte receive data buffer and one-byte transmit data buffer enabling full-duplex communication. For the transfer clock, either a clock internally generated by the timer module or an external clock input via the SCLKx can be used. Software should be used to select the data length (7 or 8 bits), stop bit length (1 or 2 bits) and parity mode (even, odd, or no parity). The start bit is fixed to 1 bit. Overrun errors, flaming errors and parity errors are detectable during data reception. The UART generates 3 types of interrupts, i.e., transmit buffer empty, receive buffer full, and receive error for each channel, enabling the interrupt handling to process serial data transfer efficiently. This UART module also incorporates an RZI modulation/demodulation circuit that enables IrDA 1.0-compatible infrared communications simply by adding basic external circuits. Figure 18.1.1 illustrates the UART configuration. Receive data buffer (2 bytes) Internal bus Bus I/F and control register RZI demodulation circuit Shift register Ch.0: SIN0 (P12) Ch.1: SIN1 (P30) Ch.0: SCLK0 (P10) Ch.1: SCLK1 (P16) Clock/transfer control Transmit data buffer (1 byte) ITC Shift register RZI modulation circuit Ch.0: SOUT0 (P11) Ch.1: SOUT1 (P27) Interrupt control Ch.0: from 8-bit timer Ch.0 sclk Ch.1: from 8-bit timer Ch.1 UART Ch.x Figure 18.1.1: UART configuration Note: The UART modules for the two channels have the same functions except for control register addresses. For this reason, the description in this section applies to all UART channels. The "x" in the register name indicates the channel number (0 or 1). Register addresses are indicated either as Ch.0" or "Ch.1". E.g.:UART_CTLx register (0x4104/0x4124) Ch.0: UART_CTL0 register (0x4104) Ch.1: UART_CTL1 register (0x4124) S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 18-1 18 UART 18.2 UART Pin Table 18.2.1 lists the UART input/output pins. Table 18.2.1: UART pin list Pin name SIN0 (P12) I/O I Qty 1 SOUT0 (P11) O 1 SCLK0 (P10) I 1 SIN1 (P30) I 1 SOUT1 (P27) O 1 SCLK1 (P16) I 1 Function UART Ch.0 data input pin Inputs serial data sent from an external device. UART Ch.0 data output pin Outputs serial data sent to an external device. UART Ch.0 clock input pin Inputs the external clock when used for the transfer clock. UART Ch.1 data input pin Inputs serial data sent from an external device. UART Ch.1 data output pin Outputs serial data sent to an external device. UART Ch.1 clock input pin Inputs the external clock when used for the transfer clock. The UART input/output pins (SINx, SOUTx, SCLKx) are shared with general purpose input/output port pins (P1[2:0], P30, P27, P16) and are initially set as general purpose input/output port pins. The function must be switched using the P3_PMUX, P2_PMUX, P1_PMUX register setting to use general purpose input/output port pins as UART input/output pins. Switch the pins to serial interface mode by setting the following control bits to 1. UART Ch.0 P12 SIN0 * P12MUX: P12 Port Function Select Bit in the P1 Port Function Select (P1_PMUX) Register (D4/0x52a2) P11 SOUT0 * P11MUX: P11 Port Function Select Bit in the P1 Port Function Select (P1_PMUX) Register (D2/0x52a2) P10 SCLK0 (only when using external clock) * P10MUX: P10 Port Function Select Bit in the P1 Port Function Select (P1_PMUX) Register (D0/0x52a2) UART Ch.1 P30 SIN1 * P30MUX: P30 Port Function Select Bit in the P3 Port Function Select (P3_PMUX) Register (D1-0/0x52a6) P27 SOUT1 * P27MUX: P27 Port Function Select Bit in the P2 Port Function Select (P2_PMUX) Register (D7-6/0x52a5) P16 SCLK1 (only when using external clock) * P16MUX: P16 Port Function Select Bit in the P1 Port Function Select (P1_PMUX) Register (D5-4/0x52a3) For detailed information on pin function switching, refer to "10.2 Input/output Pin Function Selection (Port MUX)." 18-2 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 18 UART 18.3 Transfer Clock The UART transfer clock can be set to internal or external using SSCK (D0/UART_MODx register). * SSCK: Input Clock Select Bit in the UART Ch.x Mode (UART_MODx) Register (D0/0x4103/0x4123) Note: Make sure the UART is halted (when RXEN/UART_CTLx register = 0) before changing SSCK. * RXEN: UART Enable Bit in the UART Control (UART_CTLx) Register (D0/0x4104/0x4124) Internal clock Setting SSCK to 0 (the default value) selects the internal clock. UART Ch.0 uses the 8-bit timer Ch.0 output clock as the transfer timer, while UART Ch.1 uses the 8-bit timer Ch.1 output clock. Thus, bit timers must be programmed to output a clock suited to the transfer rate. For more information on 8-bit timer control, see "12 8-bit Timer (T8F)." External clock Setting SSCK to 1 selects the external clock. In this case, set P10 (Ch.0), P16 (Ch.1) to the SCLK0, SCLK1 pin (see Section 18.2) to input the external clock. Note: * The UART generates a sampling clock that divides the 8-bit timer output into 1/16 divisions. Be careful when setting the transfer rate. * To input the external clock via the SCLK pin, the clock frequency must be less than half of the PCLK and have a duty ratio of 50%. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 18-3 18 UART 18.4 Transfer Data Settings Set the following conditions to set the transfer data format. * Data length: 7 or 8 bits * Start bit: Fixed at 1 bit * Stop bit: 1 or 2 bits * Parity bit: Even, odd, no parity Note: Make sure the UART is halted (when RXEN/UART_CTLx register = 0) before changing transfer data format settings. * RXEN: UART Enable Bit in the UART Ch.x Control (UART_CTLx) Register (D0/0x4104/0x4124) Data length The data length is selected by CHLN (D4/UART_MODx register). Setting CHLN to 0 (default) sets the data length to 7 bits. Setting CHLN to 1 sets the data length to 8 bits. * CHLN: Character Length Select Bit in the UART Ch.x Mode (UART_MODx) Register (D4/0x4103/0x4123) Stop bit The stop bit length is selected by STPB (D1/UART_MODx register). Setting STPB to 0 (default) sets the stop bit length to 1 bit. Setting STPB to 1 sets the stop bit length to 2 bits. * STPB: Stop Bit Select Bit in the UART Ch.x Mode (UART_MODx) Register (D1/0x4103/0x4123) Parity bit Whether the parity function is enabled or disabled is selected by PREN (D3/UART_MODx register). Setting PREN to 0 (default) disables the parity function. In this case, no parity bit is added to the transfer data and the data is not checked for parity when received. Setting PREN to 1 enables the parity function. In this case, a parity bit is added to the transfer data and the data is checked for parity when received. When the parity function is enabled, the parity mode is selected by PMD (D2/UART_MODx register). Setting PMD to 0 (default) adds a parity bit and checks for even parity. Setting PMD to 1 adds a parity bit and checks for odd parity. * PREN: Parity Enable Bit in the UART Ch.x Mode (UART_MODx) Register (D3/0x4103/0x4123) * PMD: Parity Mode Select Bit in the UART Ch.x Mode (UART_MODx) Register (D2/0x4103/0x4123) Sampling clock (sclk-1/16) CHLN = 0, PREN = 0, STPB = 0 s1 D0 D1 D2 D3 D4 D5 D6 s2 CHLN = 0, PREN = 1, STPB = 0 s1 D0 D1 D2 D3 D4 D5 D6 p s2 CHLN = 0, PREN = 0, STPB = 1 s1 D0 D1 D2 D3 D4 D5 D6 s2 s3 CHLN = 0, PREN = 1, STPB = 1 s1 D0 D1 D2 D3 D4 D5 D6 p s2 CHLN = 1, PREN = 0, STPB = 0 s1 D0 D1 D2 D3 D4 D5 D6 D7 s2 CHLN = 1, PREN = 1, STPB = 0 s1 D0 D1 D2 D3 D4 D5 D6 D7 p s2 CHLN = 1, PREN = 0, STPB = 1 s1 D0 D1 D2 D3 D4 D5 D6 D7 s2 s3 CHLN = 1, PREN = 1, STPB = 1 s1 D0 D1 D2 D3 D4 D5 D6 D7 p s2 s3 s3 s1: Start bit, s2 & s3: Stop bits, p: Parity bit Figure 18.4.1: Transfer data format 18-4 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 18 UART 18.5 Data Transfer Control Make the following settings before starting data transfers. (1) Select input clock. (See Section 18.3.) To use the internal clock, program the 8-bit timer to output the transfer clock. See Section 12. (2) Set the transfer data format. (See Section 18.4.) (3) To use the IrDA interface, set IrDA mode. (See Section 18.8.) (4) Set interrupt conditions to use UART interrupts. (See Section 18.7.) Note: Make sure the UART is halted (when RXEN/UART_CTLx register = 0) before changing the above settings. * RXEN: UART Enable Bit in the UART Ch.x Control (UART_CTLx) Register (D0/0x4104/0x4124) Permitting data transfers Set the RXEN bit (D0/UART_CTLx register) to 1 to permit data transfers. This switches transfer circuits to enable transfers. Note: Do not set the RXEN bit to 0 while the UART is sending or receiving data. Data transfer control To start data transmission, program the transmission data to the UART_TXDx register (0x4101/0x4121). * UART_TXDx: UART Ch.x Transmit Data Register (0x4101/0x4121) The data is written to the transmit data buffer, and the transmission circuit starts sending data. The buffer data is sent to the transmit shift register, and the start bit is output from the SOUT pin. The data in the shift register is then output from the LSB. The transfer data bit is shifted in sync with the sampling clock rising edge and output in sequence via the SOUT pin. Following output of MSB, the parity bit (if parity is enabled) and stop bit are output. The transmission circuit includes the TDBE (D0/UART_STx register) and TRBS (D2/UART_STx register) status flags. * TDBE: Transmit Data Buffer Empty Flag in the UART Ch.x Status (UART_STx) Register (D0/0x4100/0x4120) * TRBS: Transmit Busy Flag in the UART Ch.x Status (UART_STx) Register (D2/0x4100/0x4120) The TDBE flag indicates the transmit data buffer status. This flag switches to 0 when the application program programs data to the transmit data buffer and reverts to 1 when the buffer data is sent to the transmit shift register. Interrupts can be generated when this flag is 1 (see Section 18.7). Subsequent data is sent after confirming that the transmit data buffer is empty either by using this interrupt or by inspecting the TDBE flag. The transmission buffer size is 1 byte, but a shift register is provided separately to allow data to be written while the previous data is being sent. Always confirm that the transmit data buffer is empty before writing transmission data. Writing data while the TDBE flag is 0 will overprogram earlier transmission data inside the transmit data buffer. The TRBS flag indicates the shift register status. This flag switches to 1 when transmission data is loaded from the transmit data buffer to the shift register and reverts to 0 once the data is sent. Read this flag to check whether the transmission circuit is operating or at standby. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 18-5 18 UART Sampling clock SOUT TDBE S1 D0 D1 D2 D3 D4 D5 D6 D7 P S2 S1 D0 D1 Wr Wr D7 P S2 S1 D0 D1 D7 P S2 Wr TRBS Interrupt S1: Start bit, S2: Stop bit, P: Parity bit, Wr: data writing to transmit data buffer Figure 18.5.1: Data transmission timing chart Data reception control The receiving circuit is launched by setting the RXEN bit to 1, enabling data to be received from an external serial device. When the external serial device sends the start bit, the receiving circuit detects its Low level and starts sampling the following data bits. The data bits are sampled at the sampling clock rising edge, and the lead bit is loaded into the receive shift register as LSB. Once the MSB has been received into the shift register, the received data is loaded into the receive data buffer. If parity checking is enabled, the receiving circuit checks parity at the same time by checking the parity bit received immediately after the MSB. The receive data buffer, a 2-byte FIFO, receives data until full. Received data in the buffer can be read from the UART_RXDx register (0x4102/0x4122). The oldest data is read out first, clearing the register. * UART_RXDx: UART Ch.x Receive Data Register (0x4102/0x4122) The receiving circuit includes the RDRY (D1/UART_STx register) and RD2B (D3/UART_STx register) buffer status flags. * RDRY: Receive Data Ready Flag in the UART Ch.x Status (UART_STx) Register (D1/0x4100/0x4120) * RD2B: Second Byte Receive Flag in the UART Ch.x Status (UART_STx) Register (D3/0x4100/0x4120) The RDRY flag indicates that the receive data buffer still contains data. The RD2B flag indicates that the receive data buffer is full. (1) RDRY = 0, RD2B = 0 The receive data buffer contents need not be read, since no data has been received. (2) RDRY = 1, RD2B = 0 One data has been received. Read the receive data buffer once. This reading resets the RDRY flag. The buffer reverts to state (1) above. If the receive data buffer contents are read twice, the second data read will be invalid. (3) RDRY = 1, RD2B = 1 Two data items have been received. Read the receive data buffer contents twice. The receive data buffer outputs the oldest data first. This reading resets the RD2B flag. The buffer then reverts to the state in (2) above. The second read outputs the most recent received data, after which the buffer reverts to the state in (1) above. Even when the receive data buffer is full, the shift register can start receiving one more 8-bit data. An overrun error will occur if receiving is finished before the receive data buffer has been read. In this case, the last received data cannot be read. The contents of the receive data buffer must be read out before an overrun error occurs. For detailed information on overrun errors, refer to Section 18.6. The volume of data received can be checked by reading these flags. 18-6 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 18 UART The UART allows receive buffer full interrupts to be generated once data has been received in the receive data buffer. These interrupts can be used to read the receive data buffer. With default settings, a receive buffer full interrupt occurs when the receive data buffer receives one item of data (status (2) above). This can be changed by setting the RBFI bit (D1/UART_CTLx register) to 1 so that an interrupt occurs when the receive data buffer receives two items of data. * RBFI: Receive Buffer Full Interrupt Condition Setup Bit in the UART Ch.x Control (UART_CTLx) Register (D1/0x4104/0x4124) Three error flags are also provided in addition to the flags previously mentioned. See Section 18.6 for detailed information on flags and receive errors. Sampling clock data 1 SIN data 2 data 3 data 4 data 5 data 6 S1 D0 *** P S2 S1 D0 *** P S2 S1 D0 *** P S2 S1 D0 *** P S2 S1 D0 *** P S2 S1 D0 *** P S2 Receive data buffer RDRY data 1 - data 2 data 2, 3 data 3 Rd Rd RD2B RXD[7:0] data 3, 4 data 1 data 2 data 3 Interrupt Receive buffer full interrupt request (RBFI = 0) Overrun error interrupt request S1: Start bit, S2: Stop bit, P: Parity bit, Rd: Data bits from RXD[7:0] Figure 18.5.2: Data receiving timing chart Blocking data transfers After a data transfer is completed (both transmission and reception), data transfers are blocked by writing 0 to the RXEN bit. Confirm that the TDBE flag is 1 and the TRBS and RDRY flags are both 0 before blocking data transfer. Setting the RXEN bit to 0 empties the transmission data buffers, clearing any remaining data. The data being transferred cannot be guaranteed if RXEN is set to 0 while data is being sent or received. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 18-7 18 UART 18.6 Receive Errors Three different receive errors may be detected while receiving data. Since receive errors are interrupt factors, they can be processed by generating interrupts. For more information on UART interrupt control, refer to Section 18.7. Parity error If PREN (D3/UART_MODx register) has been set to 1 (parity enabled), data received is checked for parity. Data received in the shift register is checked for parity when sent to the receive data buffer. The matching is checked against the PMD (D2/UART_MODx register) setting (odd or even parity). If the result is a non-match, a parity error is issued, and the parity error flag PER (D5/UART_STx register) is set to 1. Even if this error occurs, the data received is sent to the receive data buffer, and the receiving operation continues. However, the received data cannot be guaranteed if a parity error occurs. The PER flag (D5/UART_STx register) is reset to 0 by writing as 1. * PREN: Parity Enable Bit in the UART Ch.x Mode (UART_MODx) Register (D3/0x4103/0x4123) * PMD: Parity Mode Select Bit in the UART Ch.x Mode (UART_MODx) Register (D2/0x4103/0x4123) * PER: Parity Error Flag in the UART Ch.x Status (UART_STx) Register (D5/0x4100/0x4120) Framing error A framing error occurs if the stop bit is received as 0 and the UART determines sync offset. If the stop bit is set to two bits, only the first bit is checked. The framing error flag FER (D6/UART_STx register) is set to 1 if this error occurs. The received data is still transferred to the receive data buffer if this error occurs and the receiving operation continues, but the data cannot be guaranteed, even if no framing error occurs for subsequent data receiving. The FER flag (D6/UART_STx register) is reset to 0 by writing as 1. * FER: Framing Error Flag in the UART Ch.x Status (UART_STx) Register (D6/0x4100/0x4120) Overrun error Even if the receive data buffer is full (two data items already received), a third item of data can be received in the shift register. However, if the receive data buffer is not emptied (by reading out data received) by the time this data has been received, the third data received in the shift register will not be sent to the buffer and generate an overrun error. If an overrun error occurs, the overrun error flag OER (D4/UART_STx register) is set to 1. The receiving operation continues even if this error occurs. The OER flag (D4/UART_STx register) is reset to 0 by writing as 1. * OER: Overrun Error Flag in the UART Ch.x Status (UART_STx) Register (D4/0x4100/0x4120) 18-8 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 18 UART 18.7 UART Interrupts The UART includes a function for generating the following three different interrupt types. * Transmit buffer empty interrupt * Receive buffer full interrupt * Receive error interrupt The UART outputs one interrupt signal shared by the three above interrupt factor types to the interrupt controller (ITC). Inspect the status flag or error flag to determine the interrupt factor occurring. Transmit buffer empty interrupt To use this interrupt, set TIEN (D4/UART_CTLx register) to 1. If TIEN is set to 0 (default), interrupt requests for this factor will not be sent to the ITC. * TIEN: Transmit Buffer Empty Interrupt Enable Bit in the UART Ch.x Control (UART_CTLx) Register (D4/0x4104/0x4124) When transmission data written to the transmit data buffer is transferred to the shift register, the UART sets the TDBE bit (D0/UART_STx register) to 1, indicating that the transmit data buffer is empty. If transmit buffer empty interrupts are permitted (TIEN = 1), an interrupt request pulse is sent simultaneously to the ITC. * TDBE: Transmit Data Buffer Empty Flag in the UART Ch.x Status (UART_STx) Register (D0/0x4100/0x4120) An interrupt occurs if other interrupt conditions are met. You can inspect the TDBE flag in the UART interrupt handler routine to determine whether the UART interrupt is attributable to a transmit buffer empty. If TDBE is 0, the next transmission data can be written to the transmit data buffer by the interrupt handler routine. Receive buffer full interrupt To use this interrupt, set RIEN (D5/UART_CTLx register) to 1. If RIEN is set to 0 (default), interrupt requests for this factor will not be sent to the ITC. * RIEN: Receive Buffer Full Interrupt Enable Bit in the UART Ch.x Control (UART_CTLx) Register (D5/0x4104/0x4124) If the specified volume of received data is loaded into the receive data buffer when a receive buffer full interrupt is permitted (RIEN = 1), the UART outputs an interrupt request pulse to the ITC. If RBFI (D1/UART_CTLx register) is 0, an interrupt request pulse is output as soon as one item of received data is loaded into the receive data buffer (RDRY flag (D1/UART_STx register) is set to 1). If RBFI (D1/UART_CTLx register) is 1, an interrupt request pulse is output as soon as two items of received data are loaded into the receive data buffer (RD2B flag (D3/UART_STx register) is set to 1). * RBFI: Receive Buffer Full Interrupt Condition Ch.x Setup Bit in the UART Control (UART_CTLx) Register (D1/0x4104/0x4124) * RDRY: Receive Data Ready Flag in the UART Ch.x Status (UART_STx) Register (D1/0x4100/0x4120) * RD2B: Second Byte Receive Flag in the UART Ch.x Status (UART_STx) Register (D3/0x4100/0x4120) An interrupt occurs if other interrupt conditions are met. You can inspect the RDRY and RD2B flags in the UART interrupt handler routine to determine whether the UART interrupt is attributable to a receive buffer full. If RDRY or RD2B is 1, the received data can be read from the receive data buffer by the interrupt handler routine. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 18-9 18 UART Receive error interrupt To use this interrupt, set REIEN (D6/UART_CTL register) to 1. If REIEN is set to 0 (default), interrupt requests will not be sent to the ITC for this factor. * REIEN: Receive Error Interrupt Enable Bit in the UART Control (UART_CTL) Register (D6/0x4104) The UART sets the error flags shown below to 1 if a parity error, framing error, or overrun error is detected when receiving data. If receive error interrupts are permitted (REIEN = 1), an interrupt request pulse is output at the same time to the ITC. * PER: Parity Error Flag in the UART Ch.x Status (UART_STx) Register (D5/0x4100/0x4120) * FER: Framing Error Flag in the UART Ch.x Status (UART_STx) Register (D6/0x4100/0x4120) * OER: Overrun Error Flag in the UART Ch.x Status (UART_STx) Register (D4/0x4100/0x4120) If other interrupt conditions are satisfied, an interrupt occurs. Inspect the error flags above as part of the UART interrupt handler routine to determine whether the UART interrupt was caused by a receive error. If any of the error flags has the value 1, the interrupt handler routine will proceed with error recovery. Interrupt vectors The UART interrupt vector numbers and vector addresses are as listed below. Table 18.7.1: UART interrupt vector Channel Ch.0 Ch.1 Vector number 160x10 170x11 Vector address TTBR + 0x40 TTBR + 0x44 Other interrupt settings The ITC allows the priority of UART interrupts to be set between level 0 (the default value) and level 7 for each channel. To generate actual interrupts, the PSR (S1C17 core internal processor status register) IE (interrupt enable) bit must be set to 1. For more information on interrupt processing, see "6 Interrupt Controller (ITC)." 18-10 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 18 UART 18.8 IrDA Interface This UART module incorporates an RZI modulation/demodulation circuit enabling implementation of IrDA 1.0-compatible infrared communication simply by adding basic external circuits. The transmission data output from the UART transmit shift register is input to the modulation circuit and output from the SOUT pin after the Low pulse has been modulated to a 3/16 sclk cycle. (S1: Start bit, S2 & S3: Stop bits, P: Parity bit) S1 Modulation circuit input (shift register output) D0 D1 D2 D3 D4 D5 D6 D7 P S2 S3 Modulation circuit output (SOUT) sclk 1 2 3 8 9 10 11 16 Modulation circuit input (shift register output) Modulation circuit output (SOUT) 3 x sclk Figure 18.8.1: Transmission signal waveform The received IrDA signal is input to the demodulation circuit and the Low pulse width is converted to 16 sclk cycles before entry to the receive shift register. The demodulation circuit uses the pulse detection clock selected from the prescaler output clock separately from the transfer cock to detect Low pulses input (when minimum pulse width = 1.41 s/115,200 bps). (S1: Start bit, S2 & S3: Stop bits, P: Parity bit) Demodulation circuit input (SIN) Demodulation circuit output (shift register input) S1 sclk D0 D1 D2 D3 D4 1 2 3 4 D5 D6 D7 P S2 S3 16 irclk Demodulation circuit input (SIN) Demodulation circuit output (shift register input) At least 2 x irclk 16 x sclk Figure 18.8.2: Receive signal waveform IrDA enable To use the IrDA interface function, set IRMD (D0/UART_EXPx register) to 1. This enables the RZI modulation/demodulation circuit. * IRMD: IrDA Mode Select Bit in the UART Ch.x Expansion (UART_EXPx) Register (D0/0x4105/0x4125) Note: This must be set before setting other UART conditions. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 18-11 18 UART IrDA receive detection clock selection The input pulse detection clock is selected from among the prescaler output clock PCLK-1/1 to PCLK-1/128 using IRCLK[2:0] (D[6:4]/UART_EXPx register). * IRCLK[2:0]: IrDA Receive Detection Clock Select Bits in the UART Ch. Expansion (UART_EXPx) Register (D[6:4]/0x4105/0x4125) Table 18.8.1: IrDA receive detection clock selection IRCLK[2:0] 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 Prescaler output clock PCLK-1/128 PCLK-1/64 PCLK-1/32 PCLK-1/16 PCLK-1/8 PCLK-1/4 PCLK-1/2 PCLK-1/1 (Default: 0x0) This clock must be selected as a clock faster than the 8-bit timer or transfer clock sclk input via the SCLKx pin. The demodulation circuit treats Low pulses with a width of at least 2 IrDA receive detection clock cycles as valid and converts them to 16 sclk cycle width Low pulses. Select the prescaler output clock to enable detection of input pulses with a minimum width of 1.41 s. Serial data transfer control Data transfer control in IrDA mode is identical to that for normal interfaces. For detailed information on data format settings and data transfer and interrupt control methods, refer to the previous discussions. 18-12 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 18 UART 18.9 Control Register Details Table 18.9.1: UART register list Address 0x4100 0x4101 0x4102 0x4103 0x4104 0x4105 0x4120 0x4121 0x4122 0x4123 0x4124 0x4125 Register name UART_ST0 UART_TXD0 UART_RXD0 UART_MOD0 UART_CTL0 UART_EXP0 UART_ST1 UART_TXD1 UART_RXD1 UART_MOD1 UART_CTL1 UART_EXP1 UART Ch.0 Status Register UART Ch.0 Transmit Data Register UART Ch.0 Receive Data Register UART Ch.0 Mode Register UART Ch.0 Control Register UART Ch.0 Expansion Register UART Ch.1 Status Register UART Ch.1 Transmit Data Register UART Ch.1 Receive Data Register UART Ch.1 Mode Register UART Ch.1 Control Register UART Ch.1 Expansion Register Function Transfer, buffer, error status display Transmission data Received data Transfer data format setting Data transfer control IrDA mode setting Transfer, buffer, error status display Transmission data Received data Transfer data format setting Data transfer control IrDA mode setting The UART registers are described in detail below. These are 8-bit registers. Note: When data is written to the registers, the "Reserved" bits must always be written as 0 and not 1. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 18-13 18 UART 0x4100: UART Status Register (UART_ST) Register name Address UART Status Register (UART_ST) 0x4100 (8 bits) Bit D7 D6 D5 D4 D3 D2 D1 D0 Name - FER PER OER RD2B TRBS RDRY TDBE Function reserved Framing error flag Parity error flag Overrun error flag Second byte receive flag Transmit busy flag Receive data ready flag Transmit data buffer empty flag Setting Init. R/W - 1 1 1 1 1 1 1 Error Error Error Ready Busy Ready Empty 0 0 0 0 0 0 0 Normal Normal Normal Empty Idle Empty Not empty - 0 0 0 0 0 0 1 Remarks - 0 when being read. R/W Reset by writing 1. R/W R/W R R Shift register status R R The "x" in register names indicates the channel number (0 or 1). 0x4100: UART Ch.0 Status Register (UART_ST0) 0x4120: UART Ch.1 Status Register (UART_ST1) D7 Reserved D6 FER: Framing Error Flag Indicates whether a framing error has occurred. 1 (R): Error occurred 0 (R): No error (default) 1 (W): Reset to 0 0 (W): Disabled FER is set to 1 when a framing error occurs. Framing errors occur when data is received with the stop bit set to 0. FER is reset by writing 1. D5 PER: Parity Error Flag Indicates whether a parity error has occurred. 1 (R): Error occurred 0 (R): No error (default) 1 (W): Reset to 0 0 (W): Disabled PER is set to 1 when a parity error occurs. Parity checking is enabled only when PREN (D3/ UART_MODx register) is set to 1 and is performed when received data is transferred from the shift register to the receive data buffer. PER is reset by writing 1. D4 OER: Overrun Error Flag Indicates whether an overrun error has occurred. 1 (R): Error occurred 0 (R): No error (default) 1 (W): Reset to 0 0 (W): Disabled OER is set to 1 when an overrun error occurs. Overrun errors occur when data is received in the shift register when the receive data buffer is already full and additional data is sent. The receive data buffer is not overwritten if this error occurs. The shift register is overwritten as soon as the error occurs. OER is reset by writing 1. D3 RD2B: Second Byte Received Flag Indicates that the receive data buffer contains two items of received data. 1 (R): Second byte can be read 0 (R): Second byte not received (default) RD2B is set to 1 when the second byte of data is loaded into the receive data buffer and is reset to 0 when the first data is read from the receive data buffer. 18-14 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 18 UART D2 TRBS: Transmit Busy Flag Indicates the transmit shift register status. 1 (R): Operating 0 (R): Standby (default) TRBS is set to 1 when transmission data is loaded from the transmit data buffer into the shift register and is reset to 0 when the data transfer is complete. Inspect TRBS to determine whether the transmit circuit is operating or at standby. D1 RDRY: Receive Data Ready Flag Indicates that the receive data buffer contains valid received data. 1 (R): Data can be read 0 (R): Buffer empty (default) RDRY is set to 1 when received data is loaded into the receive data buffer and is reset to 0 when all data has been read from the receive data buffer. D0 TDBE: Transmit Data Buffer Empty Flag Indicates the state of the transmit data buffer. 1 (R): Buffer empty (default) 0 (R): Data exists TDBE is reset to 0 when transmit data is written to the transmit data buffer and is set to 1 when the data is transferred to the shift register. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 18-15 18 UART 0x4101/0x4121: UART Ch.x Transmit Data Registers (UART_TXDx) Register name Address UART Ch.x Transmit Data Register (UART_TXDx) 0x4101 0x4121 (8 bits) Bit D7-0 Name TXD[7:0] Function Transmit data TXD7(6) = MSB TXD0 = LSB Setting Init. R/W 0x0 to 0xff (0x7f) 0x0 R/W Remarks The "x" in register names indicates the channel number (0 or 1). 0x4101: UART Ch.0 Transmit Data Register (UART_TXD0) 0x4121: UART Ch.1 Transmit Data Register (UART_TXD1) D[7:0] 18-16 TXD[7:0]: Transmit Data Program transmit data to be set in the transmit data buffer. (Default: 0x0) The UART begins transmitting when data is written to this register. Data written to TXD[7:0] is retained until sent to the transmit data buffer. Transmitting data from within the transmit data buffer generates a transmit buffer empty interrupt factor. TXD7 (MSB) is invalid in 7-bit mode. Serial converted data is output from the SOUT pin, with the LSB first bits set to 1 as High level and bits set to 0 as Low level. This register can also be read from. Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 18 UART 0x4102/0x4122: UART Ch.x Receive Data Registers (UART_RXDx) Register name Address UART Ch.x Receive Data Register (UART_RXDx) 0x4102 0x4122 (8 bits) Bit D7-0 Name RXD[7:0] Function Receive data in the receive data buffer RXD7(6) = MSB RXD0 = LSB Setting 0x0 to 0xff (0x7f) Init. R/W 0x0 R Remarks Older data in the buffer is read out first. The "x" in register names indicates the channel number (0 or 1). 0x4102: UART Ch.0 Receive Data Register (UART_RXD0) 0x4122: UART Ch.1 Receive Data Register (UART_RXD1) D[7:0] RXD[7:0]: Receive Data Data in the receive data buffer is read out in sequence, starting with the oldest. Received data is placed in the receive data buffer. The receive data buffer is a 2-byte FIFO that allows proper data receipt until it fills, even if data is not read out. If the buffer is full and the shift register also contains received data, an overrun error will occur, unless the data is read out before receipt of the subsequent data starts. The receive circuit includes two receive buffer status flags: RDRY (D1/UART_STx register) and RD2B (D3/UART_STx register). The RDRY flag indicates the presence of valid received data in the receive data buffer, while RD2B flag indicates the presence of two items of received data in the receive data buffer. A receive buffer full interrupt occurs when the received data in the receive data buffer reaches the number specified by RBFI (D1/UART_CTLx register). 0 is loaded into RXD7 in 7-bit mode. Serial data input via the SIN pin is converted to parallel, with the initial bit as LSB, the High level bit as 1, and the Low level bit as 0. This data is then loaded into the receive data buffer. This register is read-only. (Default: 0x0) S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 18-17 18 UART 0x4103/0x4123: UART Ch.x Mode Registers (UART_MODx) Register name Address UART Ch.x Mode Register (UART_MODx) 0x4103 0x4123 (8 bits) Bit D7-5 D4 D3 D2 D1 D0 Name - CHLN PREN PMD STPB SSCK Function reserved Character length Parity enable Parity mode select Stop bit select Input clock select Setting Init. R/W - 1 1 1 1 1 8 bits With parity Odd 2 bits External 0 0 0 0 0 7 bits No parity Even 1 bit Internal - 0 0 0 0 0 Remarks - 0 when being read. R/W R/W R/W R/W R/W The "x" in register names indicates the channel number (0 or 1). 0x4103: UART Ch.0 Mode Register (UART_MOD0) 0x4123: UART Ch.1 Mode Register (UART_MOD1) D[7:5] Reserved D4 CHLN: Character Length Select Bit Selects the serial transfer data length. 1 (R/W): 8 bits 0 (R/W): 7 bits (default) D3 PREN: Parity Enable Bit Enables the parity function. 1 (R/W): With parity 0 (R/W): No parity (default) PREN is used to select receive data parity checking and to determine whether a parity bit is added to transmitted data. Setting PREN to 1 parity-checks the received data. A parity bit is automatically added to the transmitted data. If PREN is set to 0, no parity bit is checked or added. D2 PMD: Parity Mode Select Bit Selects the parity mode. 1 (R/W): Odd parity 0 (R/W): Even parity (default) Writing 1 to PMD selects odd parity; writing 0 to it selects even parity. Parity checking and parity bit addition are enabled only when PREN (D3) is set to 1. The PMD setting is disabled if PREN (D3) is 0. D1 STPB: Stop Bit Select Bit Selects the stop bit length. 1 (R/W): 2 bits 0 (R/W): 1 bit (default) Writing 1 to STPB selects two stop bits; writing 0 to it selects one bit. The start bit is fixed at one bit. D0 SSCK: Input Clock Select Bit Selects the input clock. 1 (R/W): External clock (SCLKx) 0 (R/W): Internal clock (default) Selects whether the internal clock (8-bit timer output clock) or external clock (input via SCLKx pin) is used. Writing 1 to SSCK selects the external clock; Writing 0 to it selects the internal clock. 18-18 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 18 UART 0x4104/0x4124: UART Ch.x Control Registers (UART_CTLx) Register name Address Bit 0x4104 UART Ch.x Control Register 0x4124 (8 bits) (UART_CTLx) D7 D6 D5 D4 D3-2 D1 D0 Name - REIEN RIEN TIEN - RBFI RXEN Function reserved Receive error int. enable Receive buffer full int. enable Transmit buffer empty int. enable reserved Receive buffer full int. condition UART enable Setting - 1 Enable 1 Enable 1 Enable 0 Disable 0 Disable 0 Disable - 1 2 bytes 1 Enable 0 1 byte 0 Disable Init. R/W - 0 0 0 - 0 0 Remarks - 0 when being read. R/W R/W R/W - 0 when being read. R/W R/W The "x" in register names indicates the channel number (0 or 1). 0x4104: UART Ch.0 Control Register (UART_CTL0) 0x4124: UART Ch.1 Control Register (UART_CTL1) D7 Reserved D6 REIEN: Receive Error Interrupt Enable Bit Permits interrupt requests to the ITC when a receive error occurs. 1 (R/W): Permitted 0 (R/W): Prohibited (default) Set this bit to 1 to process receive errors using interrupts. D5 RIEN: Receive Buffer Full Interrupt Enable Bit Permits interrupt requests to the ITC caused when the received data quantity in the receive data buffer reaches the quantity specified in RBFI (D1). 1 (R/W): Permitted 0 (R/W): Prohibited (default) Set this bit to 1 to read receive data using interrupts. D4 TIEN: Transmit Buffer Empty Interrupt Enable Bit Permits interrupt requests to the ITC caused when transmission data in the transmit data buffer is sent to the shift register (i.e. when data transmission begins). 1 (R/W): Permitted 0 (R/W): Prohibited (default) Set this bit to 1 to program data to the transmit data buffer using interrupts. D[3:2] Reserved D1 RBFI: Receive Buffer Full Interrupt Condition Setup Bit Sets the quantity of data in the receive buffer to generate a receive buffer full interrupt. 1 (R/W): 2 bytes 0 (R/W): 1 byte (default) If receive buffer full interrupts are permitted (RIEN = 1), the UART outputs an interrupt request pulse to the ITC when the quantity of received data specified by RBFI is loaded into the receive data buffer. If the RBFI bit is 0, an interrupt request pulse is output as soon as one item of received data is loaded into the receive data buffer (when the RDRY flag (D1/UART_STx register) is set to 1). If RBFI is 1, an interrupt request pulse is output as soon as two items of received data are loaded into the receive data buffer (when the RD2B flag (D3/UART_STx register) is set to 1). D0 RXEN: UART Enable Bit Permits data transfer by the UART. 1 (R/W): Permitted 0 (R/W): Prohibited (default) Set RXEN to 1 before starting UART transfers. Setting RXEN to 0 will stop data transfers. Set the transfer conditions while RXEN is 0. Preventing transfers by writing 0 to RXEN also clears transmit data buffer. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 18-19 18 UART 0x4105/0x4125: UART Ch.x Expansion Registers (UART_EXPx) Register name Address UART Ch.x Expansion Register (UART_EXPx) 0x4105 0x4125 (8 bits) Bit Name Function Setting D7 D6-4 - reserved IRCLK[2:0] IrDA receive detection clock select D3-1 D0 - IRMD reserved IrDA mode select Init. R/W - IRCLK[2:0] 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 Clock PCLK-1/128 PCLK-1/64 PCLK-1/32 PCLK-1/16 PCLK-1/8 PCLK-1/4 PCLK-1/2 PCLK-1/1 - 1 On - 0 0 Off Remarks - - 0 when being read. 0x0 R/W - 0 when being read. R/W The "x" in register names indicates the channel number (0 or 1). 0x4105: UART Ch.0 Expansion Register (UART_EXP0) 0x4125: UART Ch.1 Expansion Register (UART_EXP1) D7 Reserved D[6:4] IRCLK[2:0]: IrDA Receive Detection Clock Select Bits Select the prescaler output clock used as the IrDA input pulse detection clock. Table 18.9.2: IrDA receive detection clock selection IRCLK[2:0] 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 Prescaler output clock PCLK-1/128 PCLK-1/64 PCLK-1/32 PCLK-1/16 PCLK-1/8 PCLK-1/4 PCLK-1/2 PCLK-1/1 (Default: 0x0) This clock must be selected as a clock faster than the 8-bit timer or transfer clock sclk input via the SCLK pin. The demodulation circuit treats Low pulses with a width of at least 2 IrDA receive detection clock cycles as valid. Select the appropriate prescaler output clock to enable detection of input pulses with a minimum width of 1.41 s. D[3:1] Reserved D0 IRMD: IrDA Mode Select Bit Switches the IrDA interface function on and off. 1 (R/W): On 0 (R/W): Off (default) Set this to 1 to use the IrDA interface. When this bit is set to 0, this module functions as a normal UART, with no IrDA functions. 18-20 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 18 UART 18.10 Precautions * The following UART bits should be set with transfers blocked (RXEN = 0). - All UART_MODx register (0x4103/0x4123) bits (SSCK, STPB, PMD, PREN, CHLN) - RBFI bit in the UART_CTLx register - All UART_EXPx register (0x4105/0x4125) bits (IRMD, IRCLK[2:0]) * RXEN: UART Enable Bit in the UART Ch.x Control (UART_CTLx) Register (D0/0x4104/0x4124) * Do not set RXEN to 0 while the UART is transmitting or receiving data. * The UART transfer rate is capped at 460,800 bps. Do not set faster transfer rates. * Preventing transfer by setting RXEN to 0 clears (initializes) transfer data buffers. Before writing 0 to RXEN, confirm the absence of data in the buffers awaiting transmission. * The IrDA receive detection clock must be selected as a clock faster than the 8-bit timer or transfer clock sclk input via the SCLK pin. * The IrDA interface demodulation circuit treats Low pulses with a width of at least 2 IrDA receive detection clock cycles as valid. Select the appropriate prescaler output clock to enable detection of input pulses with a minimum width of 1.41 s as a 2 IrDA receive detection clock. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 18-21 19 SPI 19 SPI 19.1 SPI Configuration The S1C17003 incorporates a synchronized serial interface module (SPI). This SPI module supports both Master and Slave modes and is used for 8-bit data transfers. Four different data transfer timing patterns (clock phase and polarity) can be selected. The SPI module includes a transmit data buffer and receive data buffer separate from the shift register, and is capable of generating two different interrupt types (transmit buffer empty and receive buffer full). This allows easy processing of continuous serial data transfer using interrupts. Figure 19.1.1 illustrates the SPI module configuration. Receive data buffer (1 byte) Internal bus Bus I/F and control register ITC SPICLK #SPISS Clock/transfer control Interrupt control PCLK SDI Shift register Transmit data buffer (1 byte) SDO Shift register 1/4 16-bit timer Ch.1 output clock SPI Figure 19.1.1: SPI module configuration S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 19-1 19 SPI 19.2 SPI Input/Output Pins Table 19.2.1 lists the SPI pins. Table 19.2.1: SPI pin list Pin name SDI (P06) I/O I Qty 1 SDO (P05) O 1 SPICLK (P04) I/O 1 #SPISS (P07) I 1 Function SPI data input pin Inputs serial data from SPI bus. SPI data output pin Outputs serial data to SPI bus. SPI external clock input/output pin Outputs SPI clock when SPI is in Master mode. Inputs external clock when SPI is used in Slave mode. SPI slave selection signal (active Low) input pin SPI (Slave mode) is selected as slave device by Low input to this pin. The SPI input/output pins (SDI, SDO, SPICLK, #SPISS) are shared with general purpose input/output port pins (P06, P05, P04, P07) and are initially set as general purpose input/output port pins. The function must be switched using the P0_PMUX register settings to use general purpose input/output port pins as SPI input/output pins. Switch the pins to SPI mode by setting the following control bits to 1. P06 SDI * P06MUX: P06 Port Function Select Bit in the P0 Port Function Select (P0_PMUX) Register (D4/0x52a1) P05 SDO * P05MUX: P05 Port Function Select Bit in the P0 Port Function Select (P0_PMUX) Register (D2/0x52a1) P04 SPICLK * P04MUX: P04 Port Function Select Bit in the P0 Port Function Select (P0_PMUX) Register (D0/0x52a1) P07 #SPISS * P07MUX: P07 Port Function Select Bit in the P0 Port Function Select (P0_PMUX) Register (D6/0x52a1) For detailed information on pin function switching, refer to "10.2 Input/Output Pin Function Selection (Port MUX)." 19-2 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 19 SPI 19.3 SPI Clock The Master mode SPI uses the internal clock output by the 16-bit timer Ch.1 as the SPI clock. This clock is output from the SPICLK pin to the slave device while also driving the shift register. Use the MCLK (D9/SPI_CTL register) to select to use the 16-bit timer Ch.1 output clock or PCLK-1/4 clock is used. Setting MCLK to 1 selects the 16-bit timer Ch.1 output clock; setting to 0 selects the PCLK-1/4 clock. * MCLK: SPI Clock Source Select Bit in the SPI Control (SPI_CTL) Register (D9/0x4326) Using the 16-bit timer Ch.1 output clock enables programmable transfer rates. For more information on 16-bit timer control, see "11 16-bit Timer (T16)." PCLK 16-bit timer Ch.1 output clock or PCLK-1/4 SPI clock (SPICLK output) Figure 19.3.1: Master mode SPI clock In Slave mode, the SPI clock is input via the SPICLK pin. Note: The duty ratio of the clock input via the SPICLK pin must be 50%. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 19-3 19 SPI 19.4 Data Transfer Condition Settings The SPI module can be set to Master or Slave modes. The SPI clock polarity and phase can also be set via the SPI_CTL register. The data length is fixed at 8 bits. Note: Make sure the SPI module is halted (when SPEN/SPI_CTL register = 0) before Master/Slave mode selection and clock condition settings. * SPEN: SPI Enable Bit in the SPI Control (SPI_CTL) Register (D0/0x4326) Master/Slave mode selection MSSL (D1/SPI_CTL register) is used to set the SPI module to Master mode or Slave mode. Setting MSSL to 1 sets Master mode; setting it to 0 (default) sets Slave mode. In Master mode, data is transferred using the internal clock. In Slave mode, data is transferred by inputting the master device clock. * MSSL: Master/Slave Mode Select Bit in the SPI Control (SPI_CTL) Register (D1/0x4326) SPI clock polarity and phase settings The SPI clock polarity is selected by CPOL (D2/SPI_CTL register). Setting CPOL to 1 treats the SPI clock as active Low; setting it to 0 (default) treats it as active High. * CPOL: Clock Polarity Select Bit in the SPI Control (SPI_CTL) Register (D2/0x4326) The SPI clock phase is selected by CPHA (D3/SPI_CTL register). * CPHA: Clock Phase Select Bit in the SPI Control (SPI_CTL) Register (D3/0x4326) As shown below, these control bits set transfer timing. SPICLK(CPOL = 1, CPHA = 1) SPICLK(CPOL = 1, CPHA = 0) SPICLK(CPOL = 0, CPHA = 1) SPICLK(CPOL = 0, CPHA = 0) SDI/SDO D7 (MSB) D0 (LSB) Receive data load timing to shift register Figure 19.4.1: Clock and data transfer timing Note: When the SPI module is used in master mode with CPHA set to 0, the clock may change a minimum of one system clock cycle time from change of the first transmit data bit. PCLK 16-bit timer output write SPI_TXD register SPICLKx SDOx Minimum 1/fsysclk Figure 19.4.2 SDOx and SPICLKx Change Timings when CPHA = 0 The half SPICLKx cycle will be secured from change of data to change of the clock for the second and following transmit data bits and the second and following bytes during continuous transfer. 19-4 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 19 SPI MSB initial/LSB initial settings Use MLSB (D8/SPI_CTL register) to select whether the data MSB or LSB is input or output first. MSB initial is set when MLSB is 0 (the default value); LSB initial is set when MLSB is 1. MLSB: LSB/MSB First Mode Select Bit in the SPI Control (SPI_CTL) Register (D8/0x4326) 19.5 Data Transfer Control Make the following settings before starting data transfers. (1) Set the 16-bit timer Ch.1 to output the SPI clock. (See Section 11.) (2) Select Master mode or Slave mode. (See Section 19.4.) (3) Set clock conditions. (See Section 19.4.) (4) Set the interrupt conditions to use SPI interrupts. (See Section 19.6.) Note: Make sure the SPI is halted (when SPEN/SPI_CTL register = 0) before changing the above settings. * SPEN: SPI Enable Bit in the SPI Control (SPI_CTL) Register (D0/0x4326) Permitting data transfers Set the SPEN bit (D0/SPI_CTL register) to 1 to permit SPI operations. This enables SPI transfers and permits clock input/output. Note: Do not set SPEN to 0 when the SPI module is transferring data. Data transfer control To start data transmission, write the transmission data to the SPI_TXD register (0x4322). * SPI_TXD: SPI Transmit Data Register (0x4322) The data is written to the transmit data buffer, and the SPI module begins sending data. The buffer data is sent to the transmit shift register. In Master mode, the module starts clock output from the SPICLK pin. In Slave mode, the module awaits clock input from the SPICLK pin. The data in the shift register is shifted in sequence at the clock rising or falling edge, as determined by CPHA (D3/SPI_CTL register) and CPOL (D2/SPI_CTL register) (see Figure 19.4.1) and sent from the SDO pin with MSB leading. * CPHA: Clock Phase Select Bit in the SPI Control (SPI_CTL) Register (D3/0x4326) * CPOL: Clock Polarity Select Bit in the SPI Control (SPI_CTL) Register (D2/0x4326) The SPI module includes the SPTBE (D0/SPI_ST register) and SPBSY (D2/SPI_ST register) status flags for transfer control. * SPTBE: Transmit Data Buffer Empty Flag in the SPI Status (SPI_ST) Register (D0/0x4320) * SPBSY: Transfer Busy Flag in the SPI Status (SPI_ST) Register (D2/0x4320) The SPTBE flag indicates the transmit data buffer status. This flag switches to 0 when the application program writes data to the SPI_TXD register (transmit data buffer) and reverts to 1 when the buffer data is sent to the transmit shift register. Interrupts can be generated when this flag is 1 (see Section 19.6). Subsequent data is sent after confirming that the transmit data buffer is empty either by using this interrupt or by inspecting the SPTBE flag. The transmission buffer size is 1 byte, but a shift register is provided separately to allow data to be written while the previous data is being sent. Always confirm that the transmit data buffer is empty before writing transmission data. Writing data while the SPTBE flag is 0 will overwrite earlier transmission data inside the transmit data buffer. In Master mode, the SPBSY flag indicates the shift register status. This flag switches to 1 when transmission data is loaded from the transmit data buffer to the shift register and reverts to 0 once the data is sent. Read this flag to check whether the SPI module is operating or at standby. The Slave mode SPBSY flag indicates the SPI slave selection signal (#SPISS pin) status. The flag has the value 1 when the SPI module is selected in Slave mode and the value 0 when the module is not selected. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 19-5 19 SPI Data receipt control In Master mode, dummy data is written to the SPI_TXD register (0x4322). Writing to the SPI TXD register creates the trigger for receipt as well as transmission start. Writing actual transmission data enables simultaneous transfers. This starts the SPI clock output from SPICLK. In Slave mode, the module waits until the clock is input from SPICLK. Slave mode involves only data receipt. There is no need to write to the SPI_TXD register if no transmission is required. The receiving operation is started by clock input from the master device. If data is transferred simultaneously, the transmission data is written to the SPI_TXD register before the clock is input. The data is contained in sequence in the shift register at the rising or falling edge for the clock determined by CPHA (D3/SPI_CTL register) and CPOL (D2/SPI_CTL register). (See Figure 19.4.1.) The received data is loaded into the receive data buffer once the 8 bits of data are received in the shift register. Received data in the buffer can be read from the SPI_RXD register (0x4324) * SPI_RXD: SPI Receive Data Register (0x4324) The SPI module includes an SPRBF flag (D1/SPI_ST register) for receipt control. * SPRBF: Receive Data Buffer Full Flag in the SPI Status (SPI_ST) Register (D1/0x4320) The SPRBF flag indicates the receive data buffer status. This flag is set to 1 when the data received in the shift register is loaded into the receive data buffer, indicating that the receive data can be read out. It reverts to 0 when the buffer data is read out from the SPI_RXD register. An interrupt can be generated as soon as the flag is set to 1 (see Section 19.6). The received data should be read out either by using this interrupt or by inspecting the SPRBF flag to confirm that the receive data buffer contains valid receive data. The receive data buffer is 1 byte in size, but a shift register is also provided, enabling received data to be retained in the buffer even while the subsequent data is being received. Note that the receive data buffer should be read out before receiving the subsequent data is complete. If receiving the subsequent data is complete before the receive data buffer contents are read out, the newly received data will overwrite the previous received data in the buffer. In Master mode, the SPBSY flag indicating the shift register state can be used in the same way while transferring data. 19-6 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 19 SPI PCLK SPEN SPI_TXDx register Write Data A Write Write Data C Data B Shift register SPICLKx pin (CPOL = 0, CPHA = 1) SPICLKx pin (CPOL = 0, CPHA = 0) SDOx SDIx AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 BD7 BD6 BD5 BD4 BD3 BD2 BD1 BD0 A'D7 A'D6 A'D5 A'D4 A'D3 A'D2 A'D1 A'D0 B'D7 B'D6 B'D5 B'D4 B'D3 B'D2 B'D1 B'D0 SPI_RXD register Data A' Data B' SPBSY SPTBE Read Read SPRBF Figure 19.5.1: Data Transmission/Receiving Timing Chart (MSB first) Blocking data transfers After a data transfer is completed (both transmission and reception), data transfers are blocked by writing 0 to the SPEN bit. Confirm that the SPTBE flag is 1 and the SPBSY flag is 0 before blocking data transfer. The data being transferred cannot be guaranteed if SPEN is set to 0 while data is being sent or received. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 19-7 19 SPI 19.6 SPI Interrupts The SPI module includes a function for generating the following two different interrupt types. * Transmit buffer empty interrupt * Receive buffer full interrupt The SPI module outputs one interrupt signal shared by the three above interrupt factor types to the interrupt controller (ITC). Inspect the status flag to determine the interrupt factor occurring. Transmit buffer empty interrupt To use this interrupt, set SPTIE (D4/SPI_CTL register) to 1. If SPTIE is set to 0 (default), interrupt requests for this factor will not be sent to the ITC. * SPTIE: Transmit Data Buffer Empty Interrupt Enable Bit in the SPI Control (SPI_CTL) Register (D4/0x4326) When transmission data written to the transmit data buffer is transferred to the shift register, the SPI module sets the SPTBE bit (D0/SPI_ST register) to 1, indicating that the transmit data buffer is empty. If transmit buffer empty interrupts are permitted (SPTIE = 1), an interrupt request pulse is sent simultaneously to the ITC. * SPTBE: Transmit Data Buffer Empty Flag in the SPI Status (SPI_ST) Register (D0/0x4320) An interrupt occurs if other interrupt conditions are met. You can inspect the SPTBE flag in the SPI interrupt processing routine to determine whether the SPI interrupt is attributable to a transmit buffer empty. If SPTBE is 1, the next transmission data can be written to the transmit data buffer by the interrupt processing routine. Receive buffer full interrupt To use this interrupt, set SPRIE (D5/SPI_CTL register) to 1. If SPRIE is set to 0 (default), interrupt requests for this factor will not be sent to the ITC. * SPRIE: Receive Data Buffer Full Interrupt Enable Bit in the SPI Control (SPI_CTL) Register (D5/0x4326) When data received in the shift register is loaded into the receive data buffer, the SPI module sets the SPRBF bit (D1/SPI_ST register) to 1, indicating that the receive data buffer contains readable received data. If receive buffer full interrupts are permitted (SPRIE = 1), an interrupt request pulse is output to the ITC at the same time. * SPRBF: Receive Data Buffer Full Flag in the SPI Status (SPI_ST) Register (D1/0x4320) An interrupt occurs if other interrupt conditions are met. You can inspect the SPRBF flag in the SPI interrupt processing routine to determine whether the SPI interrupt is attributable to a receive buffer full. If SPRBF is 1, the received data can be read from the receive data buffer by the interrupt processing routine. Interrupt vectors The SPI interrupt vector numbers and vector addresses are as listed below. Vector number: Vector address: 18 (0x12) TTBR + 0x48 Other interrupt settings The SPI interrupt priority can be set for the ITC between level 0 (default) and level 7. The PSR (S1C17 core internal processor status register) IE (interrupt enable) bit must be set to 1 to generate actual interrupts. For specific information on interrupt processing, refer to "6 Interrupt Controller (ITC)." 19-8 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 19 SPI 19.7 Control Register Details Table 19.7.1: SPI register list Address 0x4320 0x4322 0x4324 0x4326 Register name SPI_ST SPI_TXD SPI_RXD SPI_CTL SPI Status Register SPI Transmit Data Register SPI Receive Data Register SPI Control Register Function Transfer, buffer status display Transmission data Received data SPI mode and data transfer permission setting The SPI registers are described in detail below. These are 16-bit registers. Note: * When data is written to the registers, the "Reserved" bits must always be written as 0 and not 1. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 19-9 19 SPI 0x4320: SPI Status Register (SPI_ST) Register name Address SPI Status Register (SPI_ST) 0x4320 (16 bits) Bit Name D15-3 - D2 SPBSY D1 D0 SPRBF SPTBE Function reserved Transfer busy flag (master) ss signal low flag (slave) Receive data buffer full flag Transmit data buffer empty flag Setting Init. R/W - 1 1 1 1 Busy ss = L Full Empty 0 0 0 0 Idle ss = H Not full Not empty - 0 - R 0 1 R R D[15:3] Reserved D2 SPBSY: Transfer Busy Flag (Master Mode)/ss Signal Low Flag (Slave Mode) Remarks 0 when being read. Master mode Indicates the SPI transfer status. 1 (R): Operating 0 (R): Standby (default) SPBSY is set to 1 when the SPI starts data transfer in Master mode and is maintained at 1 while transfer is underway. It is cleared to 0 once the transfer is complete. Slave mode Indicates the slave selection (#SPISS) signal status. 1 (R): Low level (this SPI is selected) 0 (R): High level (this SPI is not selected) (default) SPBSY is set to 1 when the master device sets the #SPISS signal to active to select this SPI module (slave device). It is returned to 0 when the master device clears the SPI module selection by returning the #SPISS signal to inactive. D1 SPRBF: Receive Data Buffer Full Flag Indicates the receive data buffer status. 1 (R): Data full 0 (R): No data (default) SPRBF is set to 1 when data received in the shift register is sent to the receive data buffer (when receiving is complete), indicating that the data can be read. It reverts to 0 once the buffer data is read from the SPI_RXD register (0x4324). D0 SPTBE: Transmit Data Buffer Empty Flag Indicates the state of the transmit data buffer. 1 (R): Empty (default) 0 (R): Data exists SPTBE is set to 0 when transmit data is written to the SPI_TXD register (transmit data buffer, 0x4322), and is set to 1 when the data is transferred to the shift register (when transmission starts). Transmission data is written to the SPI_TXD register when this bit is 1. 19-10 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 19 SPI 0x4322: SPI Transmit Data Register (SPI_TXD) Register name Address SPI Transmit Data Register (SPI_TXD) 0x4322 (16 bits) Bit Name Function D15-8 - reserved D7-0 SPTDB[7:0] SPI transmit data buffer SPTDB7 = MSB SPTDB0 = LSB Setting - 0x0 to 0xff Init. R/W Remarks - - 0 when being read. 0x0 R/W D[15:8] Reserved D[7:0] SPTDB[7:0]: SPI Transmit Data Buffer Bits Set the transmission data to be written to the transmit data buffer. (Default: 0x0) In Master mode, transmission is started by writing data to this register. In Slave mode, the contents of this register are sent to the shift register and transmission begins when the clock is input from the master. SPTBE (D0/SPI_ST register) is set to 1 (empty) as soon as data written to this register has been transferred to the shift register. A transmit buffer empty interrupt is generated at the same time. The subsequent transmit data can then be written, even while data is being transmitted. Serial converted data is output from the SDO pin with MSB leading, with the bit set to 1 as High level and the bit set to 0 as Low level. Note: Make sure that SPEN is set to 1 before writing data to the SPI_TXD register to start data transmission/reception. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 19-11 19 SPI 0x4324: SPI Receive Data Register (SPI_RXD) Register name Address SPI Receive Data Register (SPI_RXD) Bit 0x4324 D15-8 (16 bits) D7-0 Name Function - reserved SPRDB[7:0] SPI receive data buffer SPRDB7 = MSB SPRDB0 = LSB Setting - 0x0 to 0xff Init. R/W - 0x0 - R Remarks 0 when being read. D[15:8] Reserved D[7:0] SPRDB[7:0]: SPI Receive Data Buffer Bits Contain the received data. (Default: 0x0) SPRBF (D1/SPI_ST register) is set to 1 (data full) as soon as data is received and the shift register data has been transferred to the receive data buffer. A receive buffer full interrupt is generated at the same time. Data can then be read until subsequent data is received. If receiving the subsequent data is complete before the register has been read out, the new received data overwrites the contents. Serial data input from the SDI pin with MSB leading is converted to parallel, with the High level bit set to 1 and the Low level bit set to 0. The data is the loaded into this register. This register is read-only. 19-12 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 19 SPI 0x4326: SPI Control Register (SPI_CTL) Register name Address SPI Control Register (SPI_CTL) Bit Name 0x4326 D15-10 - (16 bits) MCLK D9 MLSB D8 D7-6 - SPRIE D5 SPTIE D4 CPHA D3 CPOL D2 MSSL D1 SPEN D0 Function Setting reserved SPI clock source select LSB/MSB first mode select reserved Receive data buffer full int. enable Transmit data buffer empty int. enable Clock phase select Clock polarity select Master/slave mode select SPI enable - 1 T16 Ch.1 1 LSB 0 PCLK-1/4 0 MSB - 1 1 1 1 1 1 Enable Enable Data out Active L Master Enable 0 0 0 0 0 0 Disable Disable Data in Active H Slave Disable Init. R/W - 0 0 - 0 0 0 0 0 0 - R/W R/W - R/W R/W R/W R/W R/W R/W Remarks 0 when being read. 0 when being read. These bits must be set before setting SPEN to 1. D[15:10] Reserved D9 MCLK: SPI Clock Source Select Bit Selects the SPI clock source. 1 (R/W): 16-bit timer Ch.1 0 (R/W): PCLK-1/4 (default) D8 MLSB: LSB/MSB First Mode Select Bit Selects whether data is transferred with MSB first or LSB first. 1 (R/W): LSB first 0 (R/W): MSB first (default) D[7:6] Reserved D5 SPRIE: Receive Data Buffer Full Interrupt Enable Bit Permits or prohibits receive data buffer full SPI interrupts. 1 (R/W): Permitted 0 (R/W): Prohibited (default) Setting SPRIE to 1 permits the output of SPI interrupt requests to the ITC due to a receive data buffer full. These interrupt requests are generated when the data received in the shift register is transferred to the receive data buffer (when receipt is complete). SPI interrupts are not generated by receive data buffer full if SPRIE is set to 0. D4 SPTIE: Transmit Data Buffer Empty Interrupt Enable Bit Permits or prohibits transmit data buffer empty SPI interrupts. 1 (R/W): Permitted 0 (R/W): Prohibited (default) Setting SPTIE to 1 permits the output of SPI interrupt requests to the ITC due to a transmit data buffer empty. These interrupt requests are generated when the data written to the transmit data buffer is transferred to the shift register (when transmission starts). SPI interrupts are not generated by transmit data buffer empty if SPTIE is set to 0. D3 CPHA: SPI Clock Phase Select Bit Selects the SPI clock phase. (Default: 0) Sets the data transfer timing together with CPOL (D2). (See Figure 19.7.1.) D2 CPOL: SPI Clock Polarity Select Bit Selects the SPI clock polarity. 1 (R/W): Active Low 0 (R/W): Active High (default) Sets the data transfer timing together with CPHA (D3). (See Figure 19.7.1.) S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 19-13 19 SPI SPICLK(CPOL = 1, CPHA = 1) SPICLK(CPOL = 1, CPHA = 0) SPICLK(CPOL = 0, CPHA = 1) SPICLK(CPOL = 0, CPHA = 0) SDI/SDO D7 (MSB) D0 (LSB) Receive data load timing to shift register Figure 19.7.1: Clock and data transfer timing D1 MSSL: Master/Slave Mode Select Bit Sets the SPI module to Master or Slave mode. 1 (R/W): Master mode 0 (R/W): Slave mode (default) Setting MSSL to 1 selects Master mode; setting it to 0 selects Slave mode. Master mode performs data transfer with the clock generated by the 16-bit timer Ch.1. In Slave mode, data is transferred by inputting the clock from the master device. D0 SPEN: SPI Enable Bit Permits or prohibits SPI module operation. 1 (R/W): Permitted 0 (R/W): Prohibited (default) Setting SPEN to 1 starts the SPI module operation, enabling data transfer. Setting SPEN to 0 stops the SPI module operation. Note: The SPEN bit should be set to 0 before setting the CPHA, CPOL, and MSSL bits. 19-14 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 19 SPI 19.8 Precautions * Do not access the SPI_CTL register (0x4326) while the SPBY flag (D2/SPI_ST register) is set to 1, or the SPRBF flag (D1/SPI_ST register) is set to 1 (while sending or receiving data). * SPBSY: Transfer Busy Flag in the SPI Status (SPI_ST) Register (D2/0x4320) * SPRBF: Receive Data Buffer Full Flag in the SPI Status (SPI_ST) Register (D1/0x4320) * Do not gain write access to read registers (the SPI_ST and SPI_RXD registers) while sending/receiving data via SPI. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 19-15 20 I2C Master (I2CM) 20 I2C Master (I2CM) 20.1 I2C Master Configuration The S1C17003 incorporates an I2C bus interface module for high-speed synchronized serial communications. The I2C master module operates as a master device (as single master only) using the clock fed from the 16-bit timer Ch.2. It supports standard (100 kbps) and fast (400 kbps) modes as well as 7-bit/10-bit slave address mode. It incorporates a noise filter function to help improve the reliability of data transfers. This module is capable of generating two different types of interrupts (transmit buffer empty and receive buffer full interrupts) for easy and continuous processing of serial data transfers with interrupts. Figure 20.1.1 shows the I2C master module configuration. SCL0 Clock/transfer control Shift register I2C master clock (from 16-bit timer Ch.2) I2C master SDA Interrupt control Noise filter SCL Bus I/F and control register ITC SDA0 Shift register Internal bus Figure 20.1.1: I2C master module configuration S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 20-1 20 I2C Master (I2CM) 20.2 I2C Master Input/Output Pins Table 20.2.1 lists the I2C master pins. Table 20.2.1: I2C master pin list Pin name SDA0 (P32 or P34) I/O I/O Qty SCL0 (P31 or P33) I/O 1 1 Function I2C master data input/output pin Inputs serial data from the I2C bus. Also outputs serial data to the I2C bus. I2C master clock input/output pin Inputs SCL line status. Also outputs a serial clock. I2C master input/output pins (SDA0 and SCL0) are shared with general purpose input/output pins (P32 and P31, or P34 and P33), and initially set as general purpose input/output pins. To use them as I2C master input/output pins, the P3_PMUX register must be set to change the function. Set the following control bit to 1 to switch the pins function to I2C master mode. Only 1 channel of I2C master is included. Therefore either SDA0(P32)/SCL0(P31) or SDA0(P34)/ SCL0(P33) combination must be selected. P32 SDA0 * P32MUX: P32 Port Function Select Bit in the P3 Port Function Select (P3_PMUX) Register (D5-4/0x52a6) P31 SCL0 * P31MUX: P31 Port Function Select Bit in the P3 Port Function Select (P3_PMUX) Register (D3-2/0x52a6) P34 SDA0 * P34MUX: P34 Port Function Select Bit in the P3 Port Function Select (P3_PMUX) Register (D1-0/0x52a7) P33 SCL0 * P33MUX: P33 Port Function Select Bit in the P3 Port Function Select (P3_PMUX) Register (D3-2/0x52a6) For detailed information on pin function switching, refer to "10.2 Input/Output Pin Function Selection (Port MUX)." 20-2 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 20 I2C Master (I2CM) 20.3 I2C Master Clock The I2C master module uses the internal clock output by the 16-bit timer Ch.2 as the synchronizing clock. This clock is output from the SCL0 pin to the slave device while also driving the shift register. The clock should be programmed to output a signal matching the transfer rate from the 16-bit timer Ch.2. For more information on 16bit timer control, refer to "11 16-bit Timer (T16)." If the I2C master module communicates with a slave device which has clock stretching, Transfer rates are limited up to 50 kbits/s in the Standard-mode, up to 200 kbits in the Fast-mode. The I2C master module does not function as a slave device. The SCL0 input pin is used to check the I2C bus SCL signal status. It is not used for synchronization clock input. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 20-3 20 I2C Master (I2CM) 20.4 Settings Before Data Transfer The I2C master module includes an optional noise filter function that can be selected via the application program. Noise filter function The I2C master module incorporates a function for filtering noise from the SDA0 and SCL0 pin input signals. This function is enabled by setting NSERM (D4/I2C_CTL register) to 1. Note that using this function requires setting the I2C master clock (16-bit timer Ch.2 output clock) frequency to 1/6 or less of PCLK. * NSERM: Noise Remove On/Off Bit in the I2C Control (I2C_CTL) Register (D4/0x4342) 20-4 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 20 I2C Master (I2CM) 20.5 Data Transfer Control Make the following settings before starting data transfers. (1) Set the 16-bit timer Ch.2 to output the I2C master clock. (See Section 11.) (2) Select the option function. (See section 20.4.) (3) Set the interrupt conditions to use I2C master interrupts. (See Section 20.6.) Note: Make sure the I2C module is halted (when I2CEN/I2C_EN register = 0) before changing the above settings. * I2CEN: I2C Enable Bit in the I2C Enable (I2C_EN) Register (D0/0x4340) Permitting data transfers Set the I2CEN (D0/I2C_EN register) to 1 to permit I2C operations. This enables I2C master transfers and permits clock input/output. Note: Do not set I2CEN to 0 when the I2C master module is transferring data. Data transfer start To start data transfers, the I2C master (this module) must generate the start condition. The slave address is then sent to establish communications. (1) Generate start condition The start condition applies when the SCL line is maintained at High and the SDA line is maintained at Low. SDA0 (output) SCL0 (output) Start condition Figure 20.5.1: Start condition The start condition is generated by setting STRT (D0/I2C_CTL register) to 1. * STRT: Start Control Bit in the I2C Control (I2C_CTL) Register (D0/0x4342) STRT is automatically reset to 0 once the start condition is generated. The I2C bus is busy from this point on. 2Slave address transmission Once the start condition has been generated, the I2C master (this module) sends a bit indicating the slave address and transfer direction for communications. I2C slave addresses are either 7-bit or 10-bit. This module uses an 8-bit transfer data register to send the slave address and transfer direction bit, enabling single transfers in 7-bit address mode. In 10-bit mode, data is sent twice under software control. Figure 20.5.2 gives the configuration of the address data. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 20-5 20 I2C Master (I2CM) 7-bit address D7 D6 D5 D4 D3 D2 D1 D0 A6 A5 A4 A3 A2 A1 A0 DIR Transfer direction 0: Master Slave (data transmission) 1: Slave Master (data recept) Slave address 10-bit address First data sent D7 D6 D5 D4 D3 D2 D1 D0 1 1 1 1 0 A9 A8 0 Slave address first 2 bits Second data sent D7 D6 D5 D4 D3 D2 D1 D0 A7 A6 A5 A4 A3 A2 A1 A0 Slave address last 8 bits Data reception After Second data sent, generate repeated START condition and send third data Third data sent D7 D6 D5 D4 D3 D2 D1 D0 1 1 1 1 0 A9 A8 1 Slave address first 2 bits Figure 20.5.2: Slave address and transmission data specifying transfer direction Transfer direction indicates the data transfer direction after the slave address. This is set to 0 when sending data from the master to the slave and to 1 when receiving data from the slave. To send a slave address, set the transmission address to RTDT[7:0] (D[7:0]/I2C_DAT register). At the same time, set the TXE (D9/I2C_DAT register) transmitting the address to 1. * RTDT[7:0]: Receive/Transmit Data Bits in the I2C Data (I2C_DAT) Register (D[7:0]/0x4344) * TXE: Transmit Execution Bit in the I2C Data (I2C_DAT) Register (D9/0x4344) After the slave address has been output, data can be sent and received as many times as required. Data must be sent or received according to the transfer direction set together with the slave address. Data transmission control The procedure for transmitting data is described below. Data transmission is performed by the same procedure as for slave address transmission. To send byte data, set the transmission data to RTDT[7:0] (D[7:0]/I2C_DAT register). Set TXE (D9/I2C_DAT register) to 1 to transmit 1 byte. When TXE is set to 1, the I2C master module begins data transmission in sync with the clock. If the previous data is currently being transmitted, data transmission starts after this has been completed. The I2C master module first transfers the data written to the shift register, then starts outputting the clock from SCL0. Resetting TXE to 0 at this point generates an interrupt, enabling the subsequent transmission data and TXE to be reset. The data bits in the shift register are shifted in sequence at the clock falling edge and output via the SDA0 pin with the MSB leading. The I2C master module outputs 9 clocks with each data transmission. In the 9th clock cycle, an ACK or NAK is received from the slave device with the SDA0 signal as high impedance. The slave device returns ACK(0) to the master if the data is received. If the data is not received, SDA is not pulled down, which the I2C master module interprets to mean an NAK(1) (transmission failed). 20-6 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 20 I2C Master (I2CM) SDA0 (output) D7 D6 D0 SDA0 (input) ACK NAK SCL0 (output) 1 2 8 9 Start condition Figure 20.5.3: ACK and NAK The I2C master module includes two status bits, TBUSY (D8/I2C_CTL register) and RTACK (D8/I2C_DAT register), for transmission control. * TBUSY: Transmit Busy Flag in the I2C Control (I2C_CTL) Register (D8/0x4342) * RTACK: Receive/Transmit ACK Bit in the I2C Data (I2C_DAT) Register (D8/0x4344) The TBUSY flag indicates the data transmission status. This flag becomes 1 when transmission starts (including slave address transmission) and reverts to 0 once data transmission ends. Inspect the flag to check whether the I2C master module is currently transmitting or at standby. The RTACK bit indicates whether or not the slave device returned an ACK for the previous transmission. RTACK is 0 if an ACK was returned and 1 if ACK was not returned. Data receipt control The procedure for receiving data is described below. To receive data, the slave address must be sent with the transfer direction bit set to 1. To receive data, set RXE (D10/I2C_DAT register) to 1 for receiving 1 byte. TXE (D9/I2C_DAT register) is set to 1 when sending the slave address, but RXE can also be set to 1 at the same time. If both TXE and RXE are set to 1, TXE takes priority. * RXE: Receive Execution Bit in the I2C Data (I2C_DAT) Register (D10/0x4344) When the RXE bit is set to 1, allowing receiving to start, the I2C master module starts outputting the clock from the SCL0 pin with the SDA line at high impedance. The data is shifted into the shift register with the clock pulses, with the MSB leading. RXE is reset to 0 when D7 is loaded. The receive data is loaded to RTDT[7:0] once the 8-bit data has been received in the shift register. The I2C master module includes two status bits for receive control: RBRDY (D11/I2C_DAT register) and RBUSY (D9/ I2C_CTL register). * RBRDY: Receive Buffer Ready Bit in the I2C Data (I2C_DAT) Register (D11/0x4344) * RBUSY: Receive Busy Flag in the I2C Control (I2C_CTL) Register (D9/0x4342) The RBRDY flag indicates the receive data status. This flag becomes 1 when the data received in the shift register is loaded to RTDT[7:0] and reverts to 0 when the receive data is read out from RTDT[7:0]. Interrupts can also be generated once the flag value becomes 1. The RBUSY flag indicates the receiving operation status. This flag is 1 when receiving starts and reverts to 0 when the data is received. It also reverts to 0 for the Wait state. Inspect the flag to determine whether the I2C master module is currently receiving or in standby. To wait for reception using polling, follow the procedures given below using the RBUSY flag. Interrupts to the CPU are prohibited because polling accurately determines the two state transitions 3 and 4. 1. Prohibits CPU interrupts using di instruction. 2. Writes 1 to RXE to prepare for receiving. 3. Waits for RBUSY to become 1 (reception start). 4. Waits for RBUSY to become 0 (reception end). 5. Reads out RTDT (received data). 6. Returns to CPU interrupt permitted state using ei instruction. The I2C master module outputs 9 clocks with each data receipt. In the 9th clock cycle, an ACK or NAK is sent to the slave from the SDA0 pin. The bit state sent can be set in RTACK (D8/I2C_DAT register). To send ACK, set RTACK to 0. To send NAK, set RTACK to 1. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 20-7 20 I2C Master (I2CM) Data transfer end (Stop condition generation) To end data transfers after all data has been transferred, the I2C master (this module) must generate a stop condition. This stop condition applies when the SCL line is maintained at High and the SDA line changes from Low to High. SDA0 (output) SCL0 (output) Stop condition Figure 20.5.4: Stop condition The stop condition is generated by setting STP (D1/I2C_CTL register) to 1. * STP: Stop Control Bit in the I2C Control (I2C_CTL) Register (D1/0x4342) When STP is set to 1, the I2C master module switches the SDA line from Low to High and generates a stop condition while maintaining the I2C bus SCL line at High. The I2C bus subsequently switches to free state. When transmission or reception ends, TBUSY or RBUSY is cleared. Then, after a period longer than the 1/4 cycle of I2C clock, STP can set to 1. If I2C master communicate with slave device which has clock stretch function, STP can not be set to 1 until slave device finishes clock stretching. For this case, wait time is necessary before STP is set to 1. STP is reset to 0 when the stop condition is generated. Continuing data transfer (Repeated start condition generation) To make it possible to continue with a different data transfer after data transfer completion, the I2C master (this module) can generate a repeated start condition. SDA0 (output) SCL0 (output) Repeated start condition Figure 20.5.5: Repeated start condition The repeated start condition is generated by setting STRT (D0/I2C_CTL register) to 1 when the I2C bus is busy. * STRT: Start Control Bit in the I2C Control (I2C_CTL) Register (D0/0x4342) STRT is automatically reset to 0 once the repeated start condition is generated. Slave address transmission is subsequently possible with the I2C bus remaining in the busy state. Disabling data transfer After STOP condition generation, write 0 to I2CMEN to disable data transfers. For this case, the STP may be polled to determine the end of STOP condition generation when it is cleared. If I2CEN is set to 0 when I2C bus is busy, SCL0, SDA0 output level nor no information is guaranteed. 20-8 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 20 I2C Master (I2CM) Timing chart STRT setting Start condition I2C bus busy PCLK T16 Ch.2 output SCL0 SDA0 STRT Figure 20.5.6: Start condition generation TXE setting Transmit data setting Transmission start Transmission end ACK receiving PCLK T16 Ch.2 output SCL0 SDA0 A6/D7 A5/D6 DIR/D0 ACK TXE TBUSY RTACK RTDT[7:0] D[7:0] D[7:0] Interrupt Figure 20.5.7: Slave address transmission/data transmission RXE setting ACK transmitting Receiving start Receiving end PCLK T16 Ch.2 output SCL0 SDA0 D7 D6 D0 ACK RXE RBUSY RTACK RTDT[7:0] D[7:0] RBRDY/ Interrupt Figure 20.5.8: Data receiving S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 20-9 20 I2C Master (I2CM) STP setting Stop condition I2C bus free PCLK T16 Ch.2 output SCL0 SDA0 STP Figure 20.5.9: Stop condition generation 20.6 I2C Master Interrupts The I2C master module includes a function for generating the following two different interrupt types. * Transmit buffer empty interrupt * Receive buffer full interrupt The I2C master module outputs one interrupt signal shared by the two above interrupt factor types to the interrupt controller (ITC). Transmit buffer empty interrupt To use this interrupt, set TINTE (D0/I2C_ICTL register) to 1. If TINTE is set to 0 (default), interrupt requests for this factor will not be sent to the ITC. * TINTE: Transmit Interrupt Enable Bit in the I2C Interrupt Control (I2C_ICTL) Register (D0/0x4346) If transmit buffer empty interrupts are permitted (TINTE = 1), an interrupt request pulse is output to the ITC as soon as the transmit data set in RTDT[7:0] (D[7:0]/I2C_DAT register) is transferred to the shift register. * RTDT[7:0]: Receive/Transmit Data Bits in the I2C Data (I2C_DAT) Register (D[7:0]/0x4344) An interrupt occurs if other interrupt conditions are satisfied. Transmit buffer empty interrupt occurs when the data was only sent. * The clear method of transmit buffer empty flag Write the data to RTDT/I2CM_DAT. When TXE/I2CM_DAT is 0, the data doesn't send and the flag is only cleared. Receive buffer full interrupt To use this interrupt, set RINTE (D1/I2C_ICTL register) to 1. If RINTE is set to 0 (default), interrupt requests for this factor will not be sent to the ITC. * RINTE: Receive Interrupt Enable Bit in the I2C Interrupt Control (I2C_ICTL) Register (D1/0x4346) If receive buffer full interrupts are permitted (RINTE = 1), an interrupt request pulse is output to the ITC as soon as the data received in the shift register is loaded to RTDT[7:0]. An interrupt occurs if other interrupt conditions are met. Receive buffer full interrupt occurs when the data was only received. * The clear method of receive buffer full flag Read the data from RTDT/I2CM_DAT. Note: When I2CM interrupt occurs, decide the transmit buffer empty interrupt or the receive buffer full interrupt by the program sequence of the I2C master. There're not registers to decide which interrupt occurred. 20-10 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 20 I2C Master (I2CM) Interrupt vectors The I2C master module interrupt vector numbers and vector addresses are as listed below. Vector number: 19 (0x13) Vector address: TTBR + 0x4c Other interrupt settings The ITC allows the priority of I2C master module interrupts to be set between level 0 (the default value) and level 7. To generate actual interrupts, the PSR (S1C17 core internal processor status register) IE (interrupt enable) bit must be set to 1. For more information on interrupt processing, see "6 Interrupt Controller (ITC)." 20.7 Control Register Details Table 20.7.1: I2CM register list Address 0x4340 0x4342 0x4344 0x4346 Register name I2C_EN I2C_CTL I2C_DAT I2C_ICTL I2C Enable Register I2C Control Register I2C Data Register I2C Interrupt Control Register Function I2C master module enable I2C master control and transfer status display Transfer data I2C master interrupt control The I2C master module registers are described in detail below. These are 16-bit registers. Note: * When data is written to the registers, the "Reserved" bits must always be written as 0 and not 1. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 20-11 20 I2C Master (I2CM) 0x4340: I2C Enable Register (I2C_EN) Register name Address I2C Enable Reg- 0x4340 (16 bits) ister (I2C_EN) Bit Name D15-1 - D0 I2CEN Function Setting reserved I2C enable D[15:1] Reserved D0 I2CEN: I2C Enable Bit Permits or prohibits I2C master module operation. 1 (R/W): Permitted 0 (R/W): Prohibited (default) - 1 Enable 0 Disable Init. R/W - - 0 R/W Remarks 0 when being read. Setting I2CEN to 1 starts the I2C master module operation, enabling data transfer. Setting I2CEN to 0 stops the I2C master module operation. 20-12 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 20 I2C Master (I2CM) 0x4342: I2C Control Register (I2C_CTL) Register name Address I2C Control Register (I2C_CTL) Bit Name 0x4342 D15-10 - (16 bits) D9 RBUSY D8 TBUSY D7-5 - D4 NSERM D3-2 - D1 STP D0 STRT Function reserved Receive busy flag Transmit busy flag reserved Noise remove on/off reserved Stop control Start control Setting - 1 Busy 1 Busy 0 Idle 0 Idle - 1 On 0 Off - 1 Stop 1 Start 0 Ignored 0 Ignored Init. R/W - 0 0 - 0 - 0 0 Remarks - 0 when being read. R R - 0 when being read. R/W - 0 when being read. R/W R/W D[15:10] Reserved D9 RBUSY: Receive Busy Flag Indicates I2C master module receive operation status. 1 (R): Busy 0 (R): Idle (Default) The RBUSY bit is set to 1 when I2C master module has started data reception, and the value is retained during the reception. When the receive process has been completed, the RBUSY bit is cleared to 0. D8 TBUSY: Transmit Busy Flag Indicates I2C master transmit operation status. 1 (R): Busy 0 (R): Idle (Default) The RBUSY bit is set to 1 when I2C master module has started data transmissin, and the value is retained during the transmission. When the transmit process has been completed, the RBUSY bit is cleared to 0. D[7:5] Reserved D4 NSERM: Noise Remove On/Off Bit Turns the noise filter function on or off. 1 (R/W): On 0 (R/W): Off (default) The I2C master module incorporates a function for filtering noise from the SDA0 and SCL0 pin input signals. This function is enabled by setting NSERM to 1. Note that using this function requires setting the I2C master clock (16-bit timer Ch.2 output clock) frequency to 1/6 or less of PCLK. D[3:2] Reserved D1 STP: Stop Control Bit Generates the stop condition. 1 (R/W): Stop condition generated 0 (R/W): Disabled (default) Setting the STP bit 1 makes the I2C master module generate the stop condition by switching the SDA line from Low to High while keeping the I2CM bus SCL line in High state. The I2C bus is in free status in the subsequent processes. When transmission or reception ends, TBUSY or RBUSY is cleared. Then, after a period longer than the 1/4 cycle of I2C clock, STP can set to 1. The generation of the stop condition automatically resets the STP bit to 0. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 20-13 20 I2C Master (I2CM) D0 STRT: Start Control Bit Generates the start condition. 1 (R/W): Start condition generated 0 (R/W): Disabled (default) With STRT set at 1, the I2C master module generates the start condition by changing the SDA line to Low while maintaining the I2C bus SCL line at High. The I2C bus subsequently becomes busy. Set STRT to 1 when data transfer starts. Registers should be set in the following sequence to generate start conditions: 1. Set the slave address in RTDT[7:0] (D[7:0]/I2C_DAT register). (First transmission data for 10-bit addresses, see Figure 20.5.2) 2. Set TXE (D9/I2C_DAT register) to 1. 3. Set STRT to 1. STRT is automatically reset to 0 once the start condition is generated. 20-14 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 20 I2C Master (I2CM) 0x4344: I2C Data Register (I2C_DAT) Register name Address I2C Data Register (I2C_DAT) Bit Name 0x4344 D15-12 - (16 bits) D11 RBRDY D10 RXE D9 TXE D8 RTACK D7-0 RTDT[7:0] Function reserved Receive buffer ready Receive execution Transmit execution Receive/transmit ACK Receive/transmit data RTDT7 = MSB RTDT0 = LSB Setting - 1 1 1 1 Ready 0 Empty Receive 0 Ignored Transmit 0 Ignored Error 0 ACK 0x0 to 0xff Init. R/W - 0 0 0 0 0x0 Remarks - 0 when being read. R R/W R/W R/W R/W D[15:12] Reserved D11 RBRDY: Receive Buffer Ready Flag Indicates the receive buffer status. 1 (R): Receive data ready 0 (R): Receive data empty (default) The RBRDY flag is turned to 1 when data received by a shift register is loaded to RTDT[7:0] (D[7:0]), and returned to 0 when the received data is read from RTDT[7:0]. An interrupt can be generated once this flag is turned to 1. Note: Use the RBUSY flag to wait for reception in the polling process. The RBRDY flag cannot be used for the polling standby. Refer to the description related to data reception control. D10 RXE: Receive Execution Bit Receives 1 byte of data. 1 (R/W): Data receipt start 0 (R/W): Disabled (default) Setting RXE to 1 and TXE (D9) to 0 starts receiving for 1 byte of data. RXE can be set to 1 for subsequent receipt, even if the slave address is being sent or data is being received. RXE is reset to 0 as soon as D6 is loaded to the shift register. D9 TXE: Transmit Execution Bit Transmits 1 byte of data. 1 (R/W): Data transmission start 0 (R/W): Disabled (default) Transmission is started by setting the transmission data to RTDT[7:0] (D[7:0]) and writing 1 to TXE. TXE can be set to 1 for subsequent transmission, even if the slave address or data is being sent. TXE is reset to 0 as soon as the data set in RTDT[7:0] is transferred to the shift register. D8 RTACK: Receive/Transmit ACK Bit When transmitting data Indicates the response bit status. 1 (R/W): Error (NAK) 0 (R/W): ACK (default) RTACK becomes 0 when ACK is returned from the slave after 1 byte of data is sent, indicating that the slave has received the data correctly. If RTACK is 1, the slave device is not operating or the data was not received correctly. When receiving data Sets the response bit sent to the slave. 1 (R/W): Error (NAK) 0 (R/W): ACK (default) To return an ACK after data has been received, RTACK should be set to 0 before the I2C master module sends the response bit. To return an NAK, set RTACK to 1. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 20-15 20 I2C Master (I2CM) D[7:0] RTDT[7:0]: Receive/Transmit Data Bits When sending data Set the transmission data. (Default: 0x0) Data transmission is started by setting TXE (D9) to 1. If a slave address or data is currently being transmitted, transmission begins once the previous transmission is completed. Serial converted data is output from the SDA0 pin with MSB leading and bits set to 0 as Low level. A transmit buffer empty interrupt factor is generated as soon as the data written to this register is transferred to the shift register, after which the subsequent transmission data can be written. When receiving data Read the receive data. (Default: 0x0) Data receipt is started by setting RXE (D10) to 1. If a slave address is currently being transmitted or data is currently being received, the new receipt starts once the previous data has been transferred. The RBRDY flag (D11) is set and a receive buffer full interrupt factor generated as soon as receipt is complete and the shift register data is transferred to this register. Data can then be read until the subsequent data has been received. If the subsequent data is received before this register is read out, the contents are overwritten by the most recent received data. Serial data input from the SDA0 pin with MSB leading is converted to parallel, with the High level bit set to 1 and the Low level bit set to 0, then loaded to this register. 20-16 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 20 I2C Master (I2CM) 0x4346: I2C Interrupt Control Register (I2C_ICTL) Register name Address 0x4346 I2C Interrupt Control Register (16 bits) (I2C_ICTL) Bit Name D15-2 - D1 RINTE D0 TINTE Function reserved Receive interrupt enable Transmit interrupt enable Setting - 1 Enable 1 Enable 0 Disable 0 Disable D[15:2] Reserved D1 RINTE: Receive Interrupt Enable Bit Permits or prohibits receive buffer full I2C master module interrupts. 1 (R/W): Permitted 0 (R/W): Prohibited (default) Init. R/W - 0 0 Remarks - 0 when being read. R/W R/W Setting RINTE to 1 permits the output of I2C master interrupt requests to the ITC due to a receive data buffer full. These interrupt requests are generated when the data received in the shift register is transferred to RTDT[7:0] (D[7:0]/I2C_DAT register) (when receipt is complete). I2C master interrupts are not generated by receive data buffer full if RINTE is set to 0. D0 TINTE: Transmit Interrupt Enable Bit Permits or prohibits transmit buffer empty I2C master module interrupts. 1 (R/W): Permitted 0 (R/W): Prohibited (default) Setting TINTE to 1 permits the output of I2C master module interrupt requests to the ITC due to a transmit buffer empty. These interrupt requests are generated when the data written to RTDT[7:0] (D[7:0]/I2C_DAT register) is transferred to the shift register. I2C master interrupts are not generated by transmit buffer empty if TINTE is set to 0. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 20-17 21 I2C Slave (I2CS) 21 I2C Slave (I2CS) 21.1 Configuration of the I2C Slave Module The S1C17003 equipped with an I2C slave module for high-speed synchronous serial communication. This I2C slave module operates as an I2C slave device using the clock supplied from the I2C master. It supports standard (100 kbps) and fast (400 kbps) modes, 7-bit slave addressing, and a clock stretch function. The I2C slave module includes a noise remove function to secure reliable data transfer. Also it can generate three types of interrupts (transmit, receive, and bus status interrupts), this makes it possible to process continuous serial data transfer simply in an interrupt handler. Figure 21.1.1 shows the structure of the I2C slave module. SDA1 Shift register Internal bus Bus I/F and control registers Noise filter SCL1 Clock/transfer control #BFR Shift register I2C Slave SDA Interrupt control SCL ITC Figure 21.1.1 Structure of I2C Slave Module Note: The I2C slave module does not support general call address and 10-bit address mode. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 21-1 21 I2C Slave (I2CS) 21.2 I2C Slave I/O Pins Table 21.2.1 lists the I2C slave pins. Table 21.2.1 List of I2C Slave Pins Pin name I/O Size Function SDA1 (P34) I/O 1 SCL1 (P33) I/O 1 #BFR (P35) I 1 I2C slave data input/output pin This pin inputs serial data from the I2C bus and outputs serial data to the I2C bus. I2C slave clock input/output pin This pin inputs the SCL line status and outputs low level to the I2C bus when clock stretch. I2C slave bus free request input pin A low pulse input to this pin requests the I2C slave to release the I2C bus. When the bus free request input has been enabled with software, a low pulse initializes the communication process of the I2C slave module and sets the SDA1 and SCL1 pins to high impedance state. The I2C slave input/output pins (SDA1, SCL1, and #BFR) are shared with the I/O ports and they are initialized as general-purpose I/O port pins by default. Before using these pins for the I2C slave, the pin functions must be switched using the Port Function Select Register. For details on switching pin function, "10.2 Input/Output Pin Function Selection (Port MUX)" P34 SDA1 * P34MUX: P34 Port Function Select Bit in the P3 Port Function Select (P3_PMUX) Register (D1-0/0x52a7) P33 SCL1 * P33MUX: P33 Port Function Select Bit in the P3 Port Function Select (P3_PMUX) Register (D7-6/0x52a6) P35 #BFR * P35MUX: P35 Port Function Select Bit in the P3 Port Function Select (P3_PMUX) Register (D3-2/0x52a7) 21-2 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 21 I2C Slave (I2CS) 21.3 I2C Slave Clock The I2C slave module inputs via the SCL1 pin a clock that has been ouput from the external I2C master device, and use the clock to send/receive data. The I2C slave module also uses the system clock (PCLK) for its operations. The PCLK frequency must be set eight-times or higher than the SCL1 input clock frequency during data transfer. In standby status, use of the asynchronous address detection function allows the application to lower the PCLK clock frequency to reduce current consumption. See "Asynchronous address detection" in "21.4.3 Optional Functions" for details. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 21-3 21 I2C Slave (I2CS) 21.4 Initializing the I2C Slave 21.4.1 Reset The I2C slave module must be reset to initialize the communication process and to set the I2C bus into free status (high impedance). The following shows two methods for resetting the module: (1) Software reset The I2C slave module can be reset by altering SOFTRESET (D6/I2CS_CTL register). * SOFTRESET: Software Reset Bit in the I2C Slave Control (I2CS_CTL) Register (D6/0x4366) To reset the I2C slave module, write 1 to SOFTRESET to place the I2C slave module into reset status, then write 0 to SOFTRESET to release it from reset status. It is not necessary to insert a waiting time between writing 1 and 0. The I2C slave module initializes the I2C slave communication process and put the SDA1 and SCL1 pins into high-impedance state to be ready to detect a start condition. Furthermore, the I2C slave control bits except for SOFTRESET are initialized. Perform the software reset in the initial setting process before staring communication. (2) Bus free request with an input from the #BFR pin The I2C slave module can accept bus free requests using the #BFR pin input. The bus free request support is disabled by default. To enable this function, set BFREQ_EN (D4/I2CS_CTL register) to 1. * BFREQ_EN: Bus Free Request Enable Bit in the I2C Slave Control (I2CS_CTL) Register (D4/0x4366) When this function is enabled, a low pulse (one system clock (PCLK) cycle is required. Two PCLK cycles or more pulse width is recommended) input to the #BFR pin sets BFREQ (D4/I2CS_STAT register) to 1. This initializes the I2C slave communication process and puts the SDA1 and SCL1 pins into high-impedance state. The control registers will not be initialized as distinct from the software reset described above. * BFREQ: Bus Free Request Bit in the I2C Slave Status (I2CS_STAT) Register (D4/0x4368) Note: When BFREQ is set to 1 (an interrupt can be used for this check), perform the software reset and set the registers again. 21.4.2 Setting the Slave Address I2C slave devices have a unique slave address to identify each device. The I2C slave module supports 7-bit address (does not support 10-bit address), and the address of this module must be set to the I2CS_SADRS register (0x4364). 21.4.3 Optional Functions The I2C slave module has a clock stretch, asynchronous address detection, and noise remove optional functions selectable in the application program. Clock stretch function After data and ACK are transmitted or received, the slave device may issue a wait request to the master device until it is ready to transmit/receive by pulling the SCL1 line down to low. The I2C slave module supports this clock stretch function. The master device enters a standby state until the wait request is canceled (the SCL1 input goes high). The clock stretch function in this module is disabled by default. When using the clock stretch function, set CLKSTR_EN (D3/I2CS_CTL register) to 1 before starting data communication. Note: When I2C slave module is slave transceiver mode, the data setup time with clock stretching (= the period from outputting the MSB of SDATA[7:0] on I2CS_SDA pin to ending I2CS_SCL Low hold) depends on the PCLK frequency. * CLKSTR_EN: Clock Stretch On/Off Bit in the I2C Slave Control (I2CS_CTL) Register (D3/0x4366) 21-4 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 21 I2C Slave (I2CS) Asynchronous address detection The I2C slave module operation clock (PCLK) frequency must be set eight-times or higher than the transfer rate during data transfer. However, the PCLK frequency can be lowered to reduce current consumption if no other processing is required during standby for data transfer. The asynchronous address detection function is provided to detect the I2C slave address sent from the master in this status. The asynchronous address detection function in this module is disabled by default. When using the asynchronous address detection function, set ASDET_EN (D1/I2CS_CTL register) to 1. * ASDET_EN: Async. Address Detection On/Off Bit in the I2C Slave Control (I2CS_CTL) Register (D1/0x4366) If the slave address sent from the master has matched with one that has been set in this I2C slave module when the asynchronous address detection function has been enabled, the I2C slave module generates a bus status interrupt and returns NAK to the I2C master to request for resending the slave address. Set the PCLK frequency to eight-times or higher than the transfer rate and reset ASDET_EN to 0 in the interrupt handler routine. Data transfer will be able to resume normally after the master retries transmission. After the master generates a STOP condition to put the I2C bus into free status, the asynchronous address detection function can be enabled again to lower the operating speed. Notes: * When the asynchronous address detection function is enabled, the I2C signals are input without passing through the noise filter. Therefore, the slave address may not be detected in a high-noise environment. * When the asynchronous address detection function is enabled, data transfer cannot be performed even if the PCLK frequency is eight-times or higher than the transfer rate. Be sure to disable the asynchronous address detection function during normal operation. Noise filter The I2C slave module contains a function to remove noise from the SDA1 and SCL1 input signals. This function is enabled by setting NF_EN (D2/I2CS_CTL register) to 1. * NF_EN: Noise Filter On/Off Bit in the I2C Slave Control (I2CS_CTL) Register (D2/0x4366) S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 21-5 21 I2C Slave (I2CS) 21.5 Data Transmit/Receive Control Before starting data transfer, set up the conditions by the procedure below. (1) Initialize the I2C slave module. See Section 21.4. (2) Set up the interrupt conditions if the I2C slave interrupt is used. See Section 21.6. Note: Make sure that the I2C slave module is disabled (I2C_EN/I2CS_CTL register = 0) before setting the conditions above. * I2C_EN: I2C Slave Enable Bit in the I2C Slave Control (I2CS_CTL) Register (D7/0x4366) Enabling data transmission/reception First, set the I2C_EN bit (D7/I2CS_CTL register) to 1 to enable I2C slave operation. This makes the I2C slave in ready-to-transmit/receive status in which a START condition can be detected. Note: Do not set the I2C_EN bit to 0 while the I2C slave module is transmitting/receiving data. Starting data transmission/reception To start data transmission/reception, set COM_MODE (D0/I2CS_CTL register) to 1 to enable the data communication. * COM_MODE: I2C Slave Communication Mode Bit in the I2C Slave Control (I2CS_CTL) Register (D0/0x4366) When the slave address for this module that has been sent from the master is received after a START condition is detected, the I2C slave module returns an ACK (SDA1 = low) and starts operating for data reception or data transmission according to the transfer direction bit that has been received with the slave address. When COM_MODE is 0 (default), the I2C slave module does not send back a response if the master has sent the slave address of this module (it is regarded as that the I2C module has returned a NAK to the master). Transfer direction 0: master slave (data reception) 1: slave master (data transmission) 7-bit slave address SDA1 (input) D7 D6 D5 D4 D3 D2 D1 A6 A5 A4 A3 A2 A1 A0 R/W D0 SDA1 (output) ACK NAK SCL1 (input) 1 2 3 4 5 6 7 8 9 START condition Figure 21.5.1 Receiving Slave Address and Data Direction Bit When a START condition is detected, BUSY (D2/I2CS_ASTAT register) is set to 1 to indicate that the I2C bus is put into busy status. When the slave address of this module is received, SELECTED (D1/I2CS_ASTAT register) is set to 1 to indicate that this module has been selected as the I2C slave device. STOP condition detection clears BUSY. STOP or Repeated START condition detection clears SELECTED. Furthermore, the value of the transfer direction bit is set to R/W (D0/I2CS_ASTAT register), so use R/W to select the transmitor receive-handling. * BUSY: I2C Bus Status Bit in the I2C Slave Access Status (I2CS_ASTAT) Register (D2/0x436a) * SELECTED: I2C Slave Select Status Bit in the I2C Slave Access Status (I2CS_ASTAT) Register (D1/0x436a) * R/W: Read/Write Direction Bit in the I2C Slave Access Status (I2CS_ASTAT) Register (D0/0x436a) If the slave address of this module is detected when the asynchronous address detection function has been enabled, ASDET (D2/I2CS_STAT register) is set to 1. The I2C slave module generates a bus status interrupt and returns NAK to the I2C master to request for resending the slave address. Set the PCLK frequency to eighttimes or higher than the transfer rate and disable the asynchronous address detection function in the interrupt handler routine. Data transfer will be able to resume normally after the master retries transmission. ASDET can be cleared by writing 1. * ASDET: Async. Address Detection Status Bit in the I2C Slave Status (I2CS_STAT) Register (D2/0x4368) 21-6 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 21 I2C Slave (I2CS) Data transmission The following describes a data transmission procedure. The I2C slave module starts data transmit process when both SELECTED and R/W are set to 1. It sets TXEMP (D3/I2CS_ASTAT register) to 1 to issue a request to the application program to write transmit data. Write transmit data to SDATA[7:0] (D[7:0]/I2CS_TRNS register). * TXEMP: Transmit Data Empty Bit in the I2C Slave Access Status (I2CS_ASTAT) Register (D3/0x436a) * SDATA[7:0]: I2C Slave Transmit Data Bits in the I2C Slave Transmit Data (I2CS_TRNS) Register (D[7:0]/0x4360) When setting the first transmit data after this module has been selected as the slave device, follow the precautions described below. When the clock stretch function is disabled (default) Transmit data must be written to SDATA[7:0] within 1 cycle of the I2C slave clock (SCL1) after TXEMP has been set to 1. This time is not enough for data preparation, so write transmit data before TXEMP has been set to 1. If the previous transmit data is still stored in SDATA[7:0], it is overwritten with the new data to be transferred. Therefore, the clear operation (see below) using TBUF_CLR is unnecessary. When the asynchronous address detection function is used, the data written before ASDET_EN is reset in 0 becomes invalid. Therefore, the transmission data must be written, after TXEMP has been set to 1. When the clock stretch function is enabled The master device is placed into wait status by the clock stretch function, so transmit data can be written after TXEMP is set. However, if the previous transmit data is still stored in SDATA[7:0], it will be sent immediately after TXEMP has been set. In order to avoid this problem, clear the I2CS_TRNS register using TBUF_CLR (D8/I2CS_CTL register) before this module is selected as the slave device. The I2CS_TRNS register is cleared by writing 1 to TBUF_CLR then writing 0 to it. * TBUF_CLR: I2CS_TRNS Register Clear Bit in the I2C Slave Control (I2CS_CTL) Register (D8/0x4366) It is not necessary to clear the I2CS_TRNS register if the first transmit data is written before TXEMP has been set. When the asynchronous address detection function is used, the data written before ASDET_EN is reset in 0 becomes invalid. Therefore, the transmission data must be written, after TXEMP has been set to 1. For writing transmit data other than the first time, use an interrupt that can be generated when TXEMP is set to 1.TXEMP is also set to 1 when the transmit data written to SDATA[7:0] is loaded to the sift register during transmission. TXEMP is cleared by writing transmit data to SDATA[7:0]. When the clock stretch function is disabled (default) When the clock stretch function has been disabled, data must be written to the I2CS_TRNS register within 7 cycles of the I2C slave clock (SCL1) from TXEMP being set to 1. If data has not been written in this period, the current register value (previous transmit data) will be sent. In this case, TXUDF (D5/I2CS_STAT register) is set to 1 to indicate that invalid data has been sent. An interrupt can be generated when TXUDF is set to 1, so an error handling should be performed in the interrupt handler routine. TXUDF is cleared by writing 1. * TXUDF: Transmit Data Underflow Bit in the I2C Slave Status (I2CS_STAT) Register (D5/0x4368) When the clock stretch function is enabled When the clock stretch function has been enabled, the I2C slave module pulls down the SCL1 pin to low to generate a clock stretch (wait) status until transmit data is written to the I2CS_TRNS register. Transmit data bits are output from the SDA1 pin in sync with the SCL1 input clock sent from the master. The MSB is output first. After the eight bits has been output, the master sends back an ACK or NAK in the ninth clock cycle. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 21-7 21 I2C Slave (I2CS) SDA1 (output) D7 D6 D0 SDA1 (input) ACK NAK SCL1 (input) 1 2 8 9 Figure 21.5.2 ACK and NAK The ACK bit indicates that the master could receive data. It is also a transmit request bit, therefore, the next transmit data must be written in advance. Receiving ACK generates a clock stretch status when the clock stretch function has been enabled, so data can be written after an ACK is received. An NAK will be returned from the master if the master could not receive data or when the master terminates data reception. In this case a clock stretch status is not generated even if the clock stretch function has been enabled. Read DA_NAK (D1/I2CS_STAT register) to check if an ACK is returned or if a NAK is returned. DA_NAK is set to 0 when an ACK is returned or set to 1 when a NAK is returned. An interrupt can be generated when DA_NAK is set to 1, so an error or termination handling can be performed in the interrupt handler routine. DA_NAK is cleared by writing 1. * DA_NAK: NAK Receive Status Bit in the I2C Slave Status (I2CS_STAT) Register (D1/0x4368) The SDA1 line status during data transmission is input in the module and is compare with the output data. The comparison results are set to DMS (D3/I2CS_STAT register). DMS is set to 0 when data is output correctly. If the SDA1 line status is different from the output data, DMS is set to 1. This may be caused by a low pull-up resistor value or another device that is controlling the SDA1 line. An interrupt can be generated when DMS is set to 1, so an error handling can be performed in the interrupt handler routine. DMS is cleared by writing 1. Note: If the I2CS module has sent back a NAK as the response to the address sent by the master when the conditions shown below are all met, the master must wait for 33 s or more before it can send another slave address (except when the master sends the I2CS slave address again). 1. The transfer rate is set to 320 kbps or higher. 2. The asynchronous address detection function is enabled. 3. The I2CS module is placed into transfer standby state and OSC1 is used as the operating clock (PCLK). * DMS: Output Data Mismatch Bit in the I2C Slave Status (I2CS_STAT) Register (D3/0x4368) Data reception The following describes a data receive procedure. The I2C slave module starts data receive process when SELECTED is set to 1 and R/W is set to 0. The receive data bits are input from the SDA1 pin in sync with the SCL1 input clock sent from the master. When the eight-bit data (MSB first) is received in the shift register, the received data is loaded to RDATA[7:0] (D[7:0]/ I2CS_RECV register). * RDATA[7:0]: I2C Slave Receive Data Bits in the I2C Slave Receive Data (I2CS_RECV) Register (D[7:0]/0x4362) When the received data is loaded to RDATA[7:0], RXRDY (D4/I2CS_ASTAT register) is set to 1 to issue a request to the application program to read RDATA[7:0]. An interrupt can be generated when RXRDY is set to 1, so the received data should be read in the interrupt handler routine. RXRDY is cleared by writing 1. * RXRDY: Receive Data Ready Bit in the I2C Slave Access Status (I2CS_ASTAT) Register (D4/0x436a) When the clock stretch function is disabled (default) When the clock stretch function has been disabled, data must be read from the I2CS_RECV register within 7 cycles of the I2C slave clock (SCL1) from RXRDY being set to 1. When the clock stretch function is enabled When the clock stretch function has been enabled, the I2C slave module pulls down the SCL1 pin to low to generate a clock stretch (wait) status until the received data is read from the I2CS_RECV register. 21-8 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 21 I2C Slave (I2CS) If the next data has been received without reading the received data, RDATA[7:0] will be overwritten. In this case, RXOVF (D5/I2CS_STAT register) is set to 1 to indicate that the received data has been overwritten. An interrupt can be generated when RXOVF is set to 1, so an error handling should be performed in the interrupt handler routine. RXOVF is cleared by writing 1. * RXOVF: Receive Data Overflow Bit in the I2C Slave Status (I2CS_STAT) Register (D5/0x4368) To return NAK during data reception During data reception (master transmission), the I2C slave module sends back an ACK (SDA1 = low) every time an 8-bit data has been received (by default setting). The response code can be changed to NAK (SDA1 = Hi-Z) by setting NAK_ANS (D5/I2CS_CTL register). ACK will be sent when NAK_ANS is 0 or NAK will be sent when NAK_ANS is set to 1. * NAK_ANS: NAK Answer Bit in the I2C Slave Control (I2CS_CTL) Register (D5/0x4366) NAK_ANS should be set within 7 cycles of the I2C slave clock (SCL1) after RXRDY has been set to 1 by receiving data just prior to one required for returning NAK. SCL1 (input) 6 7 8 SDA1 (input) D2 D1 D0 SDA1 (output) 9 1 2 3 4 5 6 7 8 D7 D6 D5 D4 D3 D2 D1 D0 ACK 9 NAK RXRDY NAK_ANS NAK_ANS setting period Receive interrupt Figure 21.5.3 Setting NAK_ANS and NAK Response Timing Terminating data transmission/reception (detecting a STOP condition) Data transfer will be terminated when the master generates a STOP condition. The STOP condition is a state in which the SDA line is pulled up from low to high with the SCL line held at high. SDA1 (input) SCL1 (input) STOP condition Table 21.5.4 STOP Condition If a STOP condition is detected while the I2C slave module is selected as the slave device (SELECTED = 1), the I2C slave module sets DA_STOP (D0/I2CS_STAT register) to 1. At the same time, it puts the SDA1 and SCL1 pins into high-impedance state and initializes the I2C slave communication process to enter standby state that is ready to detect the next START condition. Also SELECTED and BUSY are reset to 0. * DA_STOP: Stop Condition Detect Bit in the I2C Slave Status (I2CS_STAT) Register (D0/0x4368) An interrupt can be generated when DA_STOP is set to 1, so a communication terminating process should be performed in the interrupt handler routine. DA_STOP is cleared by writing 1. Disabling data transmission/reception After data transfer has finished, write 0 to the COM_MODE (D0/I2CS_CTL register) to disable data transmission/ reception. Always make sure that the BUSY and SELECTED flags are 0 before data transmission/reception is disabled. To deactivate the I2C slave module, set I2C_EN (D7/I2CS_CTL register) to 0. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 21-9 21 I2C Slave (I2CS) Timing charts Start condition Clock stretch Data transmission Transmit data setting Slave address reception PCLK SCL1(input) PCLK x 6 SCL1(output) SDA1(input) A6 A5 A4 A3 A2 A1 A0 R/W = 1 SDA1(output) H/L ACK D7 D6 R/W BUSY SELECTED TXEMP TXUDF DA_NAK DA_STOP valid Transmit shift register SDATA[7:0] shift D[7:0] Interrupt Transmit interrupt Transmit interrupt Figure 21.5.5 I2C Slave Timing Chart 1 (START condition data transmission) Clock stretch Transmit data setting Stop condition Data transmission PCLK SCL1(input) PCLK x 6 SCL1(output) SDA1(input) SDA1(output) NAK ACK D0' D0' D7 D6 D5 D4 valid shift shift shift D3 D2 D1 D0 shift shift shift shift R/W BUSY SELECTED TXEMP TXUDF DA_NAK DA_STOP Transmit shift register D[7:0] SDATA[7:0] Interrupt Transmit interrupt Bus status interrupt Bus status interrupt Figure 21.5.6 I2C Slave Timing Chart 2 (data transmission STOP condition) Start condition Slave address reception Data reception PCLK SCL1 (input) SCL1 (output) SDA1 (input) A6 A5 A4 A3 A2 A1 A0 R/W = 0 SDA1 (output) D7 D6 D5 D4 ACK R/W BUSY SELECTED RXRDY RXOVF DA_STOP Receive shift register shift shift shift shift shift shift shift shift shift shift shift RDATA[7:0] Interrupt Figure 21.5.7 I2C Slave Timing Chart 3 (START condition data reception) 21-10 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 21 I2C Slave (I2CS) Data reception Clock stretch Read reception data Stop condition Data reception PCLK SCL1(input) SCL1(output) SDA1(input) D0 D7 D6 D5 D4 D3 D2 D1 D0 ACK SDA1(output) NAK R/W BUSY SELECTED RXRDY RXOVF DA_STOP Receive shift register shift shift Interrupt shift shift shift shift shift shift D[7:0] RDATA[7:0] D[7:0] Receive interrupt Bus status interrupt Receive interrupt Figure21.5.8 I2C Slave Timing Chart 4 (data reception STOP condition) 21.6 I2C Slave Interrupt The I2C slave module can generate the following three types of interrupts: * Transmit interrupt * Receive interrupt * Bus status interrupt Transmit interrupt When the transmit data written to SDATA[7:0] (D[7:0]/I2CS_TRNS register) is sent to the shift register, TXEMP (D3/I2CS_ASTAT register) is set to 1 and an interrupt signal is output to the ITC. This interrupt can be used to write the next transmit data to SDATA[7:0]. * SDATA[7:0]: I2C Slave Transmit Data Bits in the I2C Slave Transmit Data (I2CS_TRNS) Register (D[7:0]/0x4360) * TXEMP: Transmit Data Empty Bit in the I2C Slave Access Status (I2CS_ASTAT) Register (D3/0x436a) Set TXEMP_IEN (D0/I2CS_ICTL register) to 1 when using this interrupt. If TXEMP_IEN is set to 0 (default), an interrupt request by this cause will not be sent to the ITC. * TXEMP_IEN: Transmit Interrupt Enable Bit in the I2C Slave Interrupt Control (I2CS_ICTL) Register (D0/0x436c) Receive interrupt When the received data is loaded to RDATA[7:0] (D[7:0]/I2CS_RECV register), RXRDY (D4/I2CS_ASTAT register) is set to 1 and an interrupt signal is output to the ITC. This interrupt can be used to read the received data from RDATA[7:0]. * RDATA[7:0]: I2C Slave Receive Data Bits in the I2C Slave Receive Data (I2CS_RECV) Register (D[7:0]/0x4362) * RXRDY: Receive Data Ready Bit in the I2C Slave Access Status (I2CS_ASTAT) Register (D4/0x436a) Set RXRDY_IEN (D1/I2CS_ICTL register) to 1 when using this interrupt. If RXRDY_IEN is set to 0 (default), an interrupt request by this cause will not be sent to the ITC. * RXRDY_IEN: Receive Interrupt Enable Bit in the I2C Slave Interrupt Control (I2CS_ICTL) Register (D1/0x436c) Bus status interrupt The I2C slave module provides the status bits listed below to represent the transmit/receive and I2C bus statuses (see Section 21.5 for details of each function). 1. ASDET: set to 1 when the slave address is detected by the asynchronous address detection function * ASDET: Async. Address Detection Status Bit in the I2C Slave Status (I2CS_STAT) Register (D2/0x4368) 2. TXUDF: set to 1 when a transmit operation has started before transmit data is written (when the clock stretch function is disabled) * TXUDF: Transmit Data Underflow Bit in the I2C Slave Status (I2CS_STAT) Register (D5/0x4368) S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 21-11 21 I2C Slave (I2CS) 3. DA_NAK: set to 1 when a NAK is returned from the master during transmission * DA_NAK: NAK Receive Status Bit in the I2C Slave Status (I2CS_STAT) Register (D1/0x4368) 4. DMS: set to 1 when the SDA1 line status is different from transfer data * DMS: Output Data Mismatch Bit in the I2C Slave Status (I2CS_STAT) Register (D3/0x4368) DMA will also be set to 1 when another slave device issues ACK to this I2C slave address (when ASDET_EN (D1/I2CS_CTL register) = 0). Note: When the master device of the I2C bus, which has multiple slave devices connected including this IC, starts communication with another slave device, the I2C slave module of this IC issues NAK in response to the sent slave address. On the other hand, the selected slave device issues ACK. Therefore, DMS may be set due to a difference between the output value of this IC and the SDA line status. When SELECTED (D1/I2CS_ASTAT register) is set to 0, you can ignore DMS without a problem even if it is set to 1 as there is a difference in the response code (ACK/NAK) from the selected slave device. When the I2C slave is placed into asynchronous address detection mode, a DMS does not occur as in the condition above. 5. RXOVF: set to 1 when the next data has been received before the received data is read (the received data is overwritten) (when the clock stretch function is disabled) * RXOVF: Receive Data Overflow Bit in the I2C Slave Status (I2CS_STAT) Register (D5/0x4368) 6. BFREQ: set to 1 when a bus free request is accepted * BFREQ: Bus Free Request Bit in the I2C Slave Status (I2CS_STAT) Register (D4/0x4368) 7. DA_STOP: set to 1 if a stop condition or a repeated start condition is detected while this module is selected as the slave device * DA_STOP: Stop Condition Detect Bit in the I2C Slave Status (I2CS_STAT) Register (D0/0x4368) When one of the bits shown above is set to 1, BSTAT (D7/I2CS_STAT register) is set to 1 and an interrupt signal is output to the ITC. This interrupt can be used to perform an error or terminate handling. * BSTAT: Bus Status Transition Bit in the I2C Slave Status (I2CS_STAT) Register (D7/0x4368) Set BSTAT_IEN (D2/I2CS_ICTL register) to 1 when using this interrupt. If BSTAT_IEN is set to 0 (default), an interrupt request by this cause will not be sent to the ITC. * BSTAT_IEN: Bus Status Interrupt Enable Bit in the I2C Slave Interrupt Control (I2CS_ICTL) Register (D2/0x436c) ITC registers for I2C slave interrupts When a cause of interrupt that has been enabled occurs, the I2C slave module asserts the interrupt signal sent to the ITC. To generate an I2C slave interrupt, set the interrupt level and enable the interrupt using the ITC registers. Table 21.6.1 shows the control bits for the I2C slave interrupt in the ITC. Table 21.6.1 ITC Registers Cause of interrupt Bus status/Transmit/receive Interrupt level setup bits ILV13[2:0] (D[10:8]/ITC_ILV6) ITC_ILV6 register (0x4312) The ITC sends an interrupt request to the S1C17 Core. The interrupt level setup bits set the interrupt level (0 to 7) of the I2C slave interrupt. An interrupt request to the S1C17 Core is accepted only when all the conditions described below are met. * The interrupt enable bit of I2C slave module (peripheral module) is set to 1. * The IE (Interrupt Enable) bit of the PSR (Processor Status Register) in the S1C17 Core is set to 1. * The I2C slave interrupt has a higher interrupt level than the value that is set in the IL field of the PSR. * No other cause of interrupt having higher priority, such as NMI, has occurred. For details on these interrupt control registers, as well as the device operation when an interrupt has occurred, see "6. Interrupt Controller (ITC)." 21-12 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 21 I2C Slave (I2CS) Interrupt vector The following shows the vector number and vector address for the I2C slave interrupt: Table 21.6.2 I2C Slave Interrupt Vectors Cause of interrupt Vector number Vector address Bus status/Transmit/receive 17 (0x11) TTBR + 0x44 21.7 Details of Control Registers Table 21.7.1 List of I2C Slave Registers Address 0x4360 0x4362 0x4364 0x4366 0x4368 0x436a 0x436c Register name I2CS_TRNS I2CS_RECV I2CS_SADRS I2CS_CTL I2CS_STAT I2CS_ASTAT I2CS_ICTL Function I2C Slave Transmit Data Write Register I2C Slave Receive Data Read Register I2C Slave Address Setup Register I2C Slave Control Register I2C Slave Status Register I2C Slave Access Status Register I2C Slave Interrupt Control Register I2C slave transmit data I2C slave receive data Sets the I2C slave address. Controls the I2C slave module. Indicates the I2C slave bus status. Indicates the I2C slave access status. Controls the I2C slave interrupt. The following describes each I2C slave register. These are all 16-bit registers. Note: When setting the registers, be sure to write a 0, and not a 1, for all "reserved bits." S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 21-13 21 I2C Slave (I2CS) 0x4360: I2C Slave Transmit Data Register (I2CS_TRNS) Register name Address I2C Slave Transmit Data Register (I2CS_TRNS) 0x4360 (16 bits) Bit Name Function D15-8 - reserved D7-0 SDATA[7:0] I2C slave transmit data Setting - 0-0xff Init. R/W Remarks - - 0 when being read. 0x0 R/W D[15:8] Reserved D[7:0] SDATA[7:0]: I2C Slave Transmit Data Bits Set a transmit data in this register. (Default: 0x0) The serial-converted data is output from the SDA1 pin beginning with the MSB, in which the bits set to 0 are output as low-level signals. When the data set in this register is sent to the shift register, a transmit interrupt occurs. The next transmit data can be written to the register after that. If the clock stretch function has been disabled, data must be written to this register within 7 cycles of the I2C slave clock (SCL1) after a transmit interrupt has been occurred. However, when setting the first transmit data after this module has been selected as the slave device, follow the precautions described below. When the clock stretch function is disabled (default) Transmit data must be written to SDATA[7:0] within 1 cycle of the I2C slave clock (SCL1) after TXEMP has been set to 1. This time is not enough for data preparation, so write transmit data before TXEMP has been set to 1. If the previous transmit data is still stored in SDATA[7:0], it is overwritten with the new data to be transferred. Therefore, the clear operation (see below) using TBUF_CLR is unnecessary. When the clock stretch function is enabled The master device is placed into wait status by the clock stretch function, so transmit data can be written after TXEMP is set. However, if the previous transmit data is still stored in SDATA[7:0], it will be sent immediately after TXEMP has been set. In order to avoid this problem, clear the I2CS_TRNS register using TBUF_CLR (D8/I2CS_CTL register) before this module is selected as the slave device. The I2CS_TRNS register is cleared by writing 1 to TBUF_CLR then writing 0 to it. It is not necessary to clear the I2CS_TRNS register if the first transmit data is written before TXEMP has been set. 21-14 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 21 I2C Slave (I2CS) 0x4362: I2C Slave Receive Data Register (I2CS_RECV) Register name Address I2C Slave Receive Data Register (I2CS_RECV) 0x4362 (16 bits) Bit Name Function D15-8 - reserved D7-0 RDATA[7:0] I2C slave receive data Setting - 0-0xff Init. R/W - 0x0 - R Remarks 0 when being read. D[15:8] Reserved D[7:0] RDATA[7:0]: I2C Slave Receive Data Bits The received data can be read from this register. (Default: 0x0) The serial data input from the SDA1 pin is converted into parallel data beginning with the MSB, with the high-level signals changed to 1 and the low-level signals changed to 0. The resulting data is stored in this register. When a receive operation is completed and the data received in the shift register is loaded to this register, RXRDY (D4/I2CS_ASTAT register) is set and a receive interrupt occurs. Thereafter, the data can be read out. When the clock stretch function has been disabled, data must be read from this register within 7 cycles of the I2C slave clock (SCL1) after RXRDY is set to 1. If the next data has been received without reading the received data, this register will be overwritten with the newly received data. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 21-15 21 I2C Slave (I2CS) 0x4364: I2C Slave Address Setup Register (I2CS_SADRS) Register name Address I2C Slave Address Setup Register (I2CS_SADRS) 0x4364 (16 bits) Bit Name Function D15-7 - reserved D6-0 SADRS[6:0] I2C slave address Setting Init. R/W - 0-0x7f - - 0 when being read. 0x0 R/W D[15:7] Reserved D[6:0] SADRS[6:0]: I2C Slave Address Bits Set the slave address of the I2C slave module to this register. (Default: 0x0) 21-16 Seiko Epson Corporation Remarks S1C17003 TECHNICAL MANUAL 21 I2C Slave (I2CS) 0x4366: I2C Slave Control Register (I2CS_CTL) Register name Address Bit 0x4366 I2C Slave Control Register (16 bits) (I2CS_CTL) D15-9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name Function - reserved TBUF_CLR I2CS_TRNS register clear I2C_EN I2C slave enable SOFTRESET Software reset NAK_ANS NAK answer BFREQ_EN Bus free request enable CLKSTR_EN Clock stretch On/Off NF_EN Noise filter On/Off ASDET_EN Async.address detection On/Off COM_MODE I2C slave communication mode Setting - 1 1 1 1 1 1 1 1 1 Clear state Enable Reset NAK Enable On On On Active D[15:9] Reserved D8 TBUF_CLR: I2CS_TRNS Register Clear Bit Clears the I2CS_TRNS register (0x4360). 1 (R/W): Clear state 0 (R/W): Normal state (clear state cancellation) (default) 0 0 0 0 0 0 0 0 0 Normal Disable Cancel ACK Disable Off Off Off Standby Init. R/W - 0 0 0 0 0 0 0 0 0 Remarks - 0 when being read. R/W R/W R/W R/W R/W R/W R/W R/W R/W NAK responsee when standby When TBUF_CLR is set to 1, the I2CS_TRNS register enters clear state. After that writing 0 to TBUF_CLR returns the I2CS_TRNS register to normal state. It is not necessary to insert a waiting time between writing 1 and 0. If a new transmission is started when the I2CS_TRNS register still stores data for the previous transmission that has already finished, the data will be sent when TXEMP (D3/I2CS_ASTAT register) is set. In order to avoid this problem, clear the I2CS_TRNS register using TBUF_CLR before starting transmission (before slave selection). The clear operation is not required if transmit data is written to the I2CS_TRNS register before TXEMP is set to 1. Data can be written to the I2CS_TRNS register even if it is placed into clear state (TBUF_CLR = 1). However, this writing does not reset TXEMP to 0. Note that TXEMP is not reset to 0 when TBUF_CLR is set back to 0. Therefore, data must be written to the I2CS_TRNS register when TBUF_CLR = 0. D7 I2C_EN: I2C Slave Enable Bit Enables/disables operation of the I2C slave module. 1 (R/W): Enable 0 (R/W): Disable (default) When I2C_EN is set to 1, the I2C slave module is activated and data transfer is enabled. When I2C_EN is set to 0, the I2C slave module goes off. D6 SOFTRESET: Software Reset Bit Resets the I2C slave module. 1 (R/W): Reset 0 (R/W): Cancel reset state (default) To reset the I2C slave module, write 1 to SOFTRESET to place the I2C slave module into reset status, then write 0 to SOFTRESET to release it from reset status. It is not necessary to insert a waiting time between writing 1 and 0. The I2C slave module initializes the I2C slave communication process and put the SDA1 and SCL1 pins into high-impedance state to be ready to detect a start condition. Furthermore, the I2C slave control bits except for SOFTRESET are initialized. Perform the software reset in the initial setting process before staring communication. D5 NAK_ANS: NAK Answer Bit Specifies the acknowledge bit to be sent after data reception. 1 (R/W): NAK 0 (R/W): ACK (default) When an eight-bit data is received, the I2C slave module sends back an ACK (SDA1 = low) or a NAK (SDA1 = Hi-Z). Either ACK or NAK should be specified using NAK_ANS within 7 cycles of the I2C slave clock (SCL1) after RXRDY has been set to 1 by receiving the previous data. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 21-17 21 I2C Slave (I2CS) D4 BFREQ_EN: Bus Free Request Enable Bit Enables/disables I2C bus free requests by inputting a low pulse to the #BFR pin. 1 (R/W): Enable 0 (R/W): Disable (default) To accept I2C bus free requests, set BFREQ_EN to 1. When a bus free request is accepted, BFREQ (D4/I2CS_STAT register) is set to 1. This initializes the I2C slave communication process and puts the SDA1 and SCL1 pins into high-impedance state. The control registers will not be initialized in this process. When BFREQ_EN is set to 0, low pulse inputs to the #BFR pin are ignored and BFREQ is not set to 1. D3 CLKSTR_EN: Clock Stretch On/Off Bit Turns the clock stretch function on or off. 1 (R/W): On 0 (R/W): Off (default) After data and ACK are transmitted or received, the slave device may issue a wait request to the master device until it is ready to transmit/receive by pulling the SCL1 line down to low. The I2C slave module supports this clock stretch function. The master device enters a standby state until the wait request is canceled (the SCL1 input goes high). When using the clock stretch function, set CLKSTR_EN to 1 before starting data communication. D2 NF_EN: Noise Filter On/Off Bit Turns the noise filter on or off. 1 (R/W): On 0 (R/W): Off (default) The I2C slave module contains a function to remove noise from the SDA1 and SCL1 input signals. This function is enabled by setting NF_EN to 1. D1 ASDET_EN: Async. Address Detection On/Off Bit Turns the asynchronous address detection function on or off. 1 (R/W): On 0 (R/W): Off (default) The I2C slave module operation clock (PCLK) frequency must be set eight-times or higher than the transfer rate during data transfer. However, the PCLK frequency can be lowered to reduce current consumption if no other processing is required during standby for data transfer. The asynchronous address detection function is provided to detect the I2C slave address sent from the master in this status. This function is enabled by setting ASDET_EN to 1. If the slave address sent from the master has matched with one that has been set in this I2C slave module when the asynchronous address detection function has been enabled, the I2C slave module generates a bus status interrupt and returns NAK to the I2C master to request for resending the slave address. Set the PCLK frequency to eight-times or higher than the transfer rate and reset ASDET_EN to 0 in the interrupt handler routine. Data transfer will be able to resume normally after the master retries transmission. After the master generates a STOP condition to put the I2C bus into free status, the asynchronous address detection function can be enabled again to lower the operating speed. Notes: * When the asynchronous address detection function is enabled, the I2C signals are input without passing through the noise filter. Therefore, the slave address may not be detected in a high-noise environment. * When the asynchronous address detection function is enabled, data transfer cannot be performed even if the PCLK frequency is eight-times or higher than the transfer rate. Be sure to disable the asynchronous address detection function during normal operation. 21-18 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 21 I2C Slave (I2CS) D0 COM_MODE: I2C Slave Communication Mode Bit Enables/disables data communication. 1 (R/W): Enable 0 (R/W): Disable (default) Set COM_MODE to 1 to enable data communication after setting the I2C_EN bit (D7) to 1 to enable I2C slave operation. When COM_MODE is 0 (default), the I2C slave module does not send back a response if the master has sent the slave address of this module (it is regarded as that the I2C module has returned a NAK to the master). S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 21-19 21 I2C Slave (I2CS) 0x4368: I2C Slave Status Register (I2CS_STAT) Register name Address Bit 0x4368 I2C Slave Status Register (16 bits) (I2CS_STAT) D15-8 D7 D6 D5 D4 D3 D2 D1 D0 Name - BSTAT - TXUDF RXOVF BFREQ DMS ASDET DA_NAK DA_STOP Function reserved Bus status transition reserved Transmit data underflow Receive data overflow Bus free request Output data mismatch Async. address detection status NAK receive status STOP condition detect D[15:8] Reserved D7 BSTAT: Bus Status Transition Bit Indicates transition of the bus status. 1 (R): Changed 0 (R): Unchanged (default) Setting Init. R/W - 1 Occurred 0 Not occurred - 0 - 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 Changed 0 Unchanged - Occurred Error Detected NAK Detected Not occurred Normal Not detected ACK Not detected Remarks - 0 when being read. R - 0 when being read. R/W Reset by writing 1. R/W R/W R/W R/W R/W When one of the TXUDF/RXOVF (D5), BFREQ (D4), DMS (D3), ASDET (D2), DA_NAK (D1), and DA_STOP (D0) bits is set to 1, BSTAT is also set to 1 and an interrupt signal is output to the ITC if the interrupt is enabled with BSTAT_IEN (D2/I2CS_ICTL register). This interrupt can be used to perform an error or terminate handling. BSTAT will be reset to 0 when the TXUDF/RXOVF (D5), BFREQ (D4), DMS (D3), ASDET (D2), DA_NAK (D1), and DA_STOP (D0) bits are all reset to 0. D6 Reserved D5 TXUDF: Transmit Data Underflow Bit (for transmission) RXOVF: Receive Data Overflow Bit (for reception) Indicates the transmit/receive data register status. 1 (R/W): Data underflow/overflow has been occurred 0 (R/W): Data underflow/overflow has not been occurred (default) This bit is effective during transmission/reception when the clock stretch function is disabled. If a data transmission begins before transmit data is written to the I2CS_TRNS register, it is regarded as a transmit data underflow and TXUDF is set to 1. If the next data reception has completed before the received data is read from the I2CS_RECV register and the I2CS_RECV register value is overwritten with the newly received data, it is regarded as a data overflow and RXOVF is set to 1. At the same time, an interrupt signal is output to the ITC if the interrupt is enabled with BSTAT_IEN (D2/I2CS_ICTL register). This interrupt can be used to perform an error handling. After TXUDF/RXOVF is set to 1, it is reset to 0 by writing 1. D4 BFREQ: Bus Free Request Bit Indicate the I2C bus free request input status. 1 (R/W): Request has been issued 0 (R/W): Request has not been issued (default) If BFREQ_EN (D4/I2CS_CTL register) has been set to 1 (bus free request enabled), a low pulse longer than five system clock (PCLK) cycles input to the #BFR pin sets BFREQ to 1 and the bus free request is accepted. When a bus free request is accepted, the I 2C slave module initializes the I2C communication process and puts the SDA1 and SCL1 pins into high-impedance state. The control registers will not be initialized in this process. At the same time, an interrupt signal is output to the ITC if the interrupt is enabled with BSTAT_IEN (D2/I2CS_ICTL register). This interrupt can be used to perform an error handling. After BFREQ is set to 1, it is reset to 0 by writing 1. If BFREQ_EN is set to 0, low pulse inputs to the #BFR pin are ignored and BFREQ is not set to 1. 21-20 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 21 I2C Slave (I2CS) D3 DMS: Output Data Mismatch Bit Represents the results of comparison between output data and SDA1 line status. 1 (R/W): Error has been occurred 0 (R/W): Error has not been occurred (default) The SDA1 line status during data transmission is input in the module and is compare with the output data. The comparison results are set to DMS. DMS is set to 0 when data is output correctly. If the SDA1 line status is different from the output data, DMS is set to 1. This may be caused by a low pullup resistor value or another device that is controlling the SDA1 line. At the same time, an interrupt signal is output to the ITC if the interrupt is enabled with BSTAT_IEN (D2/I2CS_ICTL register). This interrupt can be used to perform an error handling. After DMS is set to 1, it is reset to 0 by writing 1. Note: When the master device of the I2C bus, which has multiple slave devices connected including this IC, starts communication with another slave device, the I2C slave module of this IC issues NAK in response to the sent slave address. On the other hand, the selected slave device issues ACK. Therefore, DMS may be set due to a difference between the output value of this IC and the SDA line status. When SELECTED (D1/I2CS_ASTAT register) is set to 0, you can ignore DMS without a problem even if it is set to 1 as there is a difference in the response code (ACK/NAK) from the selected slave device. When the I2C slave is placed into asynchronous address detection mode, a DMS does not occur as in the condition above. D2 ASDET: Async. Address Detection Status Bit Indicates the asynchronous address detection status. 1 (R/W): Detected 0 (R/W): Not detected (default) The I2C slave module operation clock (PCLK) frequency must be set eight-times or higher than the transfer rate during data transfer. However, the PCLK frequency can be lowered to reduce current consumption if no other processing is required during standby for data transfer. The asynchronous address detection function is provided to detect the I2C slave address sent from the master in this status. ASDET is set to 1 if the slave address of the I2C slave module is detected when the asynchronous address detection function has been enabled by setting ASDET_EN (D1/I2CS_CTL register). The I2C slave module returns a NAK to the I2C master to request for resending the slave address. At the same time, an interrupt signal is output to the ITC if the interrupt is enabled with BSTAT_IEN (D2/ I2CS_ICTL register). Set the PCLK frequency to eight-times or higher than the transfer rate and reset ASDET_EN to 0 in the interrupt handler routine. Data transfer will be able to resume normally after the master retries transmission. After ASDET is set to 1, it is reset to 0 by writing 1. D1 DA_NAK: NAK Receive Status Bit Indicates the acknowledge bit returned from the master. 1 (R/W): NAK 0 (R/W): ACK (default) DA_NAK is set to 0 when an ACK is returned from the master after an eight-bit data has been sent. This indicates that the master could receive data. If DA_NAK is 1, it indicates that the master could not receive data or the master terminates data reception. At the same time DA_NAK is set to 1, an interrupt signal is output to the ITC if the interrupt is enabled with BSTAT_IEN (D2/I2CS_ICTL register). This interrupt can be used to perform an error handling. After DA_NAK is set to 1, it is reset to 0 by writing 1. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 21-21 21 I2C Slave (I2CS) D0 DA_STOP: Stop Condition Detect Bit Indicates that a stop condition or a repeated start condition is detected. 1 (R/W): Detected 0 (R/W): Not detected (default) If a STOP condition or a repeated start condition is detected while the I2C slave module is selected as the slave device (SELECTED (D1/I2CS_ASTAT register) = 1), the I2C slave module sets DA_STOP to 1. At the same time, it initializes the I2C communication process. When DA_STOP is set to 1, an interrupt signal is output to the ITC if the interrupt is enabled with BSTAT_IEN (D2/I2CS_ICTL register). This interrupt can be used to perform a terminate handling. After DA_STOP is set to 1, it is reset to 0 by writing 1. 21-22 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 21 I2C Slave (I2CS) 0x436a: I2C Slave Access Status Register (I2CS_ASTAT) Register name Address I2C Slave Access Status Register (I2CS_ASTAT) 0x436a (16 bits) Bit Name D15-5 D4 D3 D2 D1 D0 - RXRDY TXEMP BUSY SELECTED R/W Function reserved Receive data ready Transmit data empty I2C bus status I2C slave select status Read/write direction D[15:5] Reserved D4 RXRDY: Receive Data Ready Bit Indicates that the received data is ready to read. 1 (R): Received data ready 0 (R): No received data (default) Setting - 1 1 1 1 1 Ready Empty Busy Selected Output 0 0 0 0 0 Not ready Not empty Free Not selected Input Init. R/W - 0 0 0 0 0 - R R R R R Remarks 0 when being read. When the received data is loaded to the I2CS_RECV register, RXRDY is set to 1. At the same time, an interrupt signal is output to the ITC if the interrupt is enabled with RXRDY_IEN (D1/I2CS_ICTL register). This interrupt can be used to read the received data from the I2CS_RECV register. After RXRDY is set to 1, it is reset to 0 when the I2CS_RECV register is read. D3 TXEMP: Transmit Data Empty Bit Indicates that transmit data can be written. 1 (R): Transmit data empty (data can be written) 0 (R): Transmit data still stored (data cannot be written) (default) When the transmit data written to the I2CS_TRNS register is sent, TXEMP is set to 1. At the same time, an interrupt signal is output to the ITC if the interrupt is enabled with TXEMP_IEN (D0/I2CS_ICTL register). This interrupt can be used to write the next transmit data to the I2CS_TRNS register. After TXEMP is set to 1, it is reset to 0 when data is written to the I2CS_TRNS register. D2 BUSY: I2C Bus Status Bit Indicates the I2C bus status. 1 (R): Bus busy status 0 (R): Bus free status (default) When the I2C slave module detects a START condition or detects that the SCL1 or SDA1 signal goes low, BUSY is set to 1 to indicate that the I2C bus enters busy status. The slave select status whether this module is selected as the slave device or not does not affect the BUSY status. After BUSY is set to 1, it is reset to 0 when a STOP condition is detected. D1 SELECTED: I2C Slave Select Status Bit Indicates that this module is selected as the I2C slave device. 1 (R): Selected 0 (R): Not selected (default) When the slave address that is set in this module is received, SELECTED is set to 1 to indicate that this module is selected as the I2C slave device. After SELECTED is set to 1, it is reset to 0 when a STOP condition or a Repeated START condition is detected. D0 R/W: Read/Write Direction Bit Represents the transfer direction bit value. 1 (R): Output (master read operation) 0 (R): Input (master write operation) (default) The transfer direction bit value that has been received with the slave address is set to R/W. Use R/W to select the transmit- or receive-handling. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 21-23 21 I2C Slave (I2CS) 0x436c: I2C Slave Interrupt Control Register (I2CS_ICTL) Register name Address Bit 0x436c I2C Slave Interrupt Control (16 bits) Register (I2CS_ICTL) D15-3 D2 D1 D0 Name Function - reserved BSTAT_IEN Bus status interrupt enable RXRDY_IEN Receive interrupt enable TXEMP_IEN Transmit interrupt enable D[15:3] Reserved D2 BSTAT_IEN: Bus Status Interrupt Enable Bit Enables/disables the bus status interrupt. 1 (R/W): Enable 0 (R/W): Disable (default) Setting - 1 Enable 1 Enable 1 Enable 0 Disable 0 Disable 0 Disable Init. R/W - 0 0 0 Remarks - 0 when being read. R/W R/W R/W When BSTAT_IEN is set to 1, I2C slave bus status interrupt requests to the ITC are enabled. A bus status interrupt request occurs when BSTAT (D7/I2CS_STAT register) is set to 1. (See description of BSTAT.) When BSTAT_IEN is set to 0, a bus status interrupt will not be generated. D1 RXRDY_IEN: Receive Interrupt Enable Bit Enables/disables the I2C slave receive interrupt. 1 (R/W): Enable 0 (R/W): Disable (default) When RXRDY_IEN is set to 1, I2C slave receive interrupt requests to the ITC are enabled. A receive interrupt request occurs when the data received in the shift register is loaded to the I2CS_RECV register (receive operation completed). When RXRDY_IEN is set to 0, a receive interrupt will not be generated. D0 TXEMP_IEN: Transmit Interrupt Enable Bit Enables/disables the I2C slave transmit interrupt. 1 (R/W): Enable 0 (R/W): Disable (default) When TXEMP_IEN is set to 1, I2C slave transmit interrupt requests to the ITC are enabled. A transmit interrupt request occurs when the data written to the I2CS_TRNS register is transferred to the shift register. When TXEMP_IEN is set to 0, a transmit interrupt will not be generated. 21-24 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 21 I2C Slave (I2CS) 21.8 Precautions * The I2C slave module operating clock (PCLK) frequency must be set to eight-times or higher than the transfer rate during data transfer. * When the asynchronous address detection function is enabled, the I2C signals are input without passing through the noise filter. Therefore, the slave address may not be detected in a high-noise environment. * When the asynchronous address detection function is enabled, data transfer cannot be performed even if the PCLK frequency is eight-times or higher than the transfer rate. Be sure to disable the asynchronous address detection function during normal operation. * When the master device of the I2C bus, which has multiple slave devices connected including this IC, starts communication with another slave device, the I2C slave module of this IC issues NAK in response to the sent slave address. On the other hand, the selected slave device issues ACK. Therefore, DMS may be set due to a difference between the output value of this IC and the SDA1 line status. When SELECTED (D1/I2CS_ASTAT register) is set to 0, you can ignore DMS without a problem even if it is set to 1 as there is a difference in the response code (ACK/NAK) from the selected slave device. When the I2C slave is placed into asynchronous address detection mode, a DMS does not occur as in the condition above. * When setting the first transmit data after this module has been selected as the slave device, follow the precautions described below. When the clock stretch function is disabled (default) Transmit data must be written to SDATA[7:0] within 1 cycle of the I2C slave clock (SCL1) after TXEMP has been set to 1. This time is not enough for data preparation, so write transmit data before TXEMP has been set to 1. If the previous transmit data is still stored in SDATA[7:0], it is overwritten with the new data to be transferred. Therefore, the clear operation (see below) using TBUF_CLR is unnecessary. When the clock stretch function is enabled The master device is placed into wait status by the clock stretch function, so transmit data can be written after TXEMP is set. However, if the previous transmit data is still stored in SDATA[7:0], it will be sent immediately after TXEMP has been set. In order to avoid this problem, clear the I2CS_TRNS register using TBUF_CLR (D8/I2CS_CTL register) before this module is selected as the slave device. The I2CS_TRNS register is cleared by writing 1 to TBUF_CLR then writing 0 to it. It is not necessary to clear the I2CS_TRNS register if the first transmit data is written before TXEMP has been set. * When the clock stretch function has been disabled, transmit data/receive data must be written/read within the time shown below. During data transmission: Within 7 cycles of the I2C slave clock (SCL1) after TXEMP is set (a transmit interrupt occurs) (See the precaution above for the first transmit data after slave selection.) During data reception: Within 7 cycles of the I2C slave clock (SCL1) after RXRDY is set (a receive interrupt occurs) To return NAK, NAK_ANS should be set within this period. * If the I2CS module has sent back a NAK as the response to the address sent by the master when the conditions shown below are all met, the master must wait for 33 s or more before it can send another slave address (except when the master sends the I2CS slave address again). 1. The transfer rate is set to 320 kbps or higher. 2. The asynchronous address detection function is enabled. 3. The I2CS module is placed into transfer standby state and OSC1 is used as the operating clock (PCLK). S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 21-25 22 Remote Controller (REMC) 22 Remote Controller (REMC) 22.1 REMC Configuration The S1C17003 incorporates a remote controller (REMC) module for generating infrared remote control communication signals. The REMC module consists of a carrier generation circuit for generating a carrier signal using the prescaler output clock, an 8-bit down-counter for counting the transferred data length, a modulation circuit for generating transmission data of the specified carrier length, and an edge detection circuit for detecting input signal rising and falling edges. The module is also capable of generating counter underflow interrupts indicating that the specified data length has been transmitted and input rising/falling edge detection interrupts for data receipt processing. Figure 22.1.1 shows the REMC module configuration. Prescaler Internal bus ITC PCLK-1/1 to 1/16K Bus I/F and control register Remote controller Carrier generation circuit Data length counter Interrupt control Modulation circuit REMO (P00) Edge detection circuit REMI (P01) Figure 22.1.1: REMC module configuration S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 22-1 22 Remote Controller (REMC) 22.2 REMC Input/output Pin Table 22.2.1 lists the REMC input/output pins. Table 22.2.1: REMC input/output pin list Pin name REMI (P01) I/O I Qty 1 REMO (P00) O 1 Function Remote control transmit data input pin Inputs receive data. Remote control transmit data output pin Outputs modulated remote control transmit data. The REMC module input/output pins (REMI, REMO) are shared with general purpose input/output port pins (P01, P00) and are initially set as general purpose input/output port pins. The function must be switched using the P0_PMUX register setting to use general purpose input/output port pins as REMC input/output pins. Switch the pins to REMC input/output by setting the following control bits to 1. P01 REMI * P01MUX: P01 Port Function Select Bit in the P0 Port Function Select (P0_PMUX) Register (D2/0x52a0) P00 REMO * P00MUX: P00 Port Function Select Bit in the P0 Port Function Select (P0_PMUX) Register (D0/0x52a0) For detailed information on pin function switching, refer to "10.2 Input/output Pin Function Selection (Port MUX)." 22-2 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 22 Remote Controller (REMC) 22.3 Carrier Generation The REMC module incorporates a carrier generation circuit that generates a carrier signal for transmission in accordance with the clock set by the software and carrier H and L section lengths. The prescaler output clock is used for the carrier signal generation clock. The prescaler generates 15 different clocks, dividing the PCLK clock from 1/1 to 1/16K. One is selected by CGCLK[3:0] (D[15:12]/REMC_PSC register). * CGCLK[3:0]: Carrier Generator Clock Select Bits in the REMC Prescaler Clock Select (REMC_PSC) Register (D[15:12]/0x5340) Table 22.3.1: Carrier generation clock selection CGCLK[3:0] 0xf 0xe 0xd 0xc 0xb 0xa 0x9 0x8 Prescaler output clock Reserved PCLK-1/16384 PCLK-1/8192 PCLK-1/4096 PCLK-1/2048 PCLK-1/1024 PCLK-1/512 PCLK-1/256 CGCLK[3:0] 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 Prescaler output clock PCLK-1/128 PCLK-1/64 PCLK-1/32 PCLK-1/16 PCLK-1/8 PCLK-1/4 PCLK-1/2 PCLK-1/1 (Default: 0x0) For more information on prescaler control, refer to "9 Prescaler (PSC)." Note: The prescaler must run before the REMC module. The carrier H and L section lengths are set by REMCH[5:0] (D[5:0]/REMC_CARH register) and REMCL[5:0] (D[13:8]/REMC_CARL register), respectively. These registers set a value corresponding to the number of clock cycles selected above + 1. * REMCH[5:0]: H Carrier Length Setup Bits in the REMC H Carrier Length Setup (REMC_CARH) Register (D[5:0]/ 0x5342) * REMCL[5:0]: L Carrier Length Setup Bits in the REMC L Carrier Length Setup (REMC_CARL) Register (D[13:8]/0x5342) The carrier H and L section lengths can be calculated as follows: REMCH + 1 Carrier H section length = ------------ [s] clk_in REMCL + 1 Carrier L section length = ------------ [s] clk_in REMCH: Carrier H section length register data value REMCL: Carrier L section length register data value clk_in: Prescaler output clock frequency The carrier signal is generated from these settings as shown in Figure 22.3.1. Example: CGCLK[3:0] = 0x2 (PCLK-1/4), REMCH[5:0] = 2, REMCL[5:0] = 1 PCLK PSC output clock Count 0 1 2 0 1 0 Carrier Carrier H section length Carrier L section length Figure 22.3.1: Carrier signal generation S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 22-3 22 Remote Controller (REMC) 22.4 Data Length Counter Clock Settings The data length counter is an 8-bit counter for setting data lengths when transmitting data. When a value corresponding to the data pulse width is written during data transmission, the data length counter begins counting down from that value, generating an underflow interrupt factor and halting when the counter reaches 0. The subsequent transmit data is set using this interrupt. This counter is also used for data receiving, enabling measurement of the receive data length. Interrupts can be generated at the input signal rising or falling edges when receiving data. The data pulse length can be obtained from the difference between data pulses by setting the data length counter to 0xff using the interrupt when the input changes and by reading out the count value when a subsequent interrupt occurs due to input changes. This data length counter count clock also uses a prescaler output clock and can select one of 15 different types. The prescaler output clock is selected by the control bit LCCLK[3:0] (D[11:8]/REMC_CFG register) provided separately to the carrier generation clock. * LCCLK[3:0]: Length Counter Clock Select Bits in the REMC Prescaler Clock Select (REMC_CFG) Register (D[11:8]/0x5340) Table 22.4.1: Data length counter clock selection LCCLK[3:0] 0xf 0xe 0xd 0xc 0xb 0xa 0x9 0x8 Prescaler output clock Reserved PCLK-1/16384 PCLK-1/8192 PCLK-1/4096 PCLK-1/2048 PCLK-1/1024 PCLK-1/512 PCLK-1/256 LCCLK[3:0] 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 Prescaler output clock PCLK-1/128 PCLK-1/64 PCLK-1/32 PCLK-1/16 PCLK-1/8 PCLK-1/4 PCLK-1/2 PCLK-1/1 (Default: 0x0) The data length counter can count up to 256. The count clock should be selected to ensure that the data length fits within this range. 22-4 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 22 Remote Controller (REMC) 22.5 Data Transfer Control Make the following settings before starting data transfers. (1) Set the carrier signal. (See Section 22.3.) (2) Select the data length counter clock. (See Section 22.4.) (3) Set the interrupt conditions. (See Section 22.6.) Note: Make sure the REMC module is halted (when REMEN/REMC_CFG register = 0) before changing the above settings. * REMEN: REMC Enable Bit in the REMC Configuration (REMC_CFG) Register (D0/0x5340) Data transfer control REMDT REMO pin output Carrier REMDT REMO pin output Figure 22.5.1: Data transmission PCLK PSC output clock (data length counter clock) REMLEN[7:0] 4 3 2 1 0 Interrupt signal Figure 22.5.2: Underflow interrupt generation timing (1) Data transmit mode setting Set REMC to transmit mode by writing 0 to REMMD (D1/REMC_CFG register). * REMMD: REMC Mode Select Bit in the REMC Configuration (REMC_CFG) Register (D1/0x5340) (2) Permit data transmission Permit REMC operation by setting REMEN (D0/REMC_CFG register) to 1. This initiates REMC transmission. Set REMDT (D0/REMC_ST register) to 0 and REMLEN[7:0] (D[7:0]/REMC_LCNT register) to 0x0 before setting REMEN to 1 to prevent unnecessary data transmission. (3) Transmission data settings Set the data to be transmitted (High or Low) to REMDT (D0/REMC_ST register). * REMDT: Transmit/Receive Data Bit in the REMC Status (REMC_ST) Register (D0/0x5344) Setting REMDT to 1 outputs High; setting it to 0 outputs Low from the REMO pin after being modulated by the carrier signal. (4) Data pulse length setting Set the value corresponding to the data pulse length (High or Low section) at the start of transmission to REMLEN[7:0] (D[15:8]/REMC_LCNT register) to set to the data length counter. * REMLEN[7:0]: Transmit/Receive Data Length Count Bits in the REMC Length Counter (REMC_LCNT) Register (D[15:8]/0x5344) S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 22-5 22 Remote Controller (REMC) Given below are the values to which the data length counter is set: Setting = Data pulse length (seconds) x prescaler output clock frequency (Hz) The data length counter begins counting down from the value written using the prescaler output clock selected. An underflow interrupt factor occurs when the data length counter value reaches 0. If interrupts are permitted, an REMC interrupt request is output to the interrupt controller (ITC). The data length counter stops counting when it reaches 0. (5) Interrupt processing To transmit the subsequent data, set the subsequent data (step 3) and set the data pulse length (step 4) as part of the interrupt processing routine generated by the data length counter underflow. (6) Data transmission end To end data transmission, set REMEN to 0 after the final data transmission is complete (after underflow interrupt has occurred). Data receipt control PCLK PSC output clock (data length counter clock) REMI input REMDT (sample waveform) REMRIF 1 written REMFIF 1 written Interrupt signal REMLEN[7:0] x+2 x+1 x 0xff 0xff written 0xfe 0xfd 0xff 0xff written Figure 22.5.3: Data receipt (1) Data receipt mode setting Set REMC to receipt mode by writing 1 to REMMD (D1/REMC_CFG register). (2) Permit data receipt Permit REMC operation by setting REMEN (D0/REMC_CFG register) to 1. This initiates REMC transmission (input edge detection operation). REMC detects input changes (signal rising or falling edges) by sampling the input signal from the REMI pin using the prescaler output clock selected for carrier generation. If a signal edge is detected, a rising or falling edge interrupt factor is generated. An REMC interrupt request is output to the ITC if interrupts are permitted. Rising edge and falling edge interrupts can be individually permitted or blocked. Note that if the signal level after the input has changed is not detected for at least two continuous sampling clock cycles, the interrupt factor is interpreted as noise, and no rising or falling edge interrupt is generated. 22-6 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 22 Remote Controller (REMC) (3) Interrupt processing When a rising edge or falling edge interrupt occurs, 0xff is written to REMLEN[7:0] (D[15:8]/REMC_LCNT register) as part of the interrupt processing routine and set as the value of the data length counter. The data length counter begins counting down using the selected prescaler output clock from the value written. The data received can be read out from REMDT (D0/REMC_LCNT register). The subsequent trailing or rising edge interrupt is generated once the data pulse ends, at which point the data length counter is read out. The data length can be calculated from the difference between 0xff and the value read. To receive the subsequent data, set the data length counter to 0xff once again, then wait for the subsequent interrupt. If the data length counter becomes 0 after being set to 0xff without the occurrence of an edge interrupt, either data receiving is complete or a receive error has occurred. Data length counter underflow interrupts are generated even when receiving data and should be used for end/error processing. (4) Data receipt end To end data receipt, write 0 to REMEN after the final data has been received. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 22-7 22 Remote Controller (REMC) 22.6 REMC Interrupts The REMC module includes functions to generate the following three different interrupt types. * Underflow interrupt * Rising edge interrupt * Falling edge interrupt The REMC module outputs one interrupt signal shared by the three interrupt factors above to the interrupt controller (ITC). To identify the interrupt factor that occurred, inspect the interrupt flag within the REMC module. Underflow interrupt Generated when the data length counter has counted down to 0, this interrupt request sets the interrupt flag REMUIF (D0/REMC_IFLG register) inside the REMC to 1. When data is being transmitted, the underflow interrupt indicates that the specified data length has been transmitted. When receiving data, the underflow interrupt indicates that data has been received or that a receive error has occurred. * REMUIF: Underflow Interrupt Flag in the REMC Interrupt Flag (REMC_INT) Register (D0/0x5346) To use this interrupt, set REMUIE (D0/REMC_IMSK register) to 1. If REMUIE is set to 0 (default), REMUIF will not be set to 1, and the interrupt request attributable to this factor will not be sent to the ITC. * REMUIE: Underflow Interrupt Enable Bit in the REMC Interrupt Mask (REMC_IMSK) Register (D0/0x5346) When REMUIF is set to 1, REMC outputs an interrupt request signal to the ITC. This interrupt request sets the REMC interrupt flag to 1 within the ITC, and generates an interrupt if the ITC and S1C17 core interrupt conditions are met. REMUIF should be inspected as part of the REMC interrupt processing routine to determine whether the REMC interrupt is attributable to data length counter underflow. The interrupt factor should be cleared as part of the interrupt processing routine by resetting both the ITC REMC interrupt flag and REMC module REMUIF (i.e., setting both to 1). Rising edge interrupt Generated when the REMI pin input signal changes from Low to High, this interrupt request sets the interrupt flag REMRIF (D1/REMC_IFLG register) to 1 within the REMC. When data is being received, the data length counter can be operated between this interrupt and a falling edge interrupt to calculate the received data pulse width from that count value. * REMRIF: Rising Edge Interrupt Flag in the REMC Interrupt Flag (REMC_INT) Register (D1/0x5346) To use this interrupt, set REMRIE (D1/REMC_IMSK register) to 1. If REMRIE is set to 0 (default), REMRIF is not set to 1 and the interrupt request for this factor is not sent to the ITC. * REMRIE: Rising Edge Interrupt Enable Bit in the REMC Interrupt Mask (REMC_INT) Register (D1/0x5346) When REMRIF is set to 1, REMC outputs an interrupt request to the ITC. This interrupt request signal sets the REMC interrupt flag to 1 within the ITC, generating an interrupt if the ITC and S1C17 core interrupt conditions are met. REMRIF should be inspected as part of the REMC interrupt processing routine to determine whether the REMC interrupt is attributable to input signal rising edge. The interrupt factor should be cleared as part of the interrupt processing routine by resetting both the ITC REMC interrupt flag and REMC module REMRIF (i.e., setting both to 1). 22-8 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 22 Remote Controller (REMC) Falling edge interrupt Generated when the REMI pin input signal changes from High to Low, this interrupt request sets the interrupt flag REMRIF (D2/REMC_INT register) to 1 within the REMC. When data is being received, the data length counter can be operated between this interrupt and a falling edge interrupt to calculate the received data pulse width from that count value. * REMFIF: Falling Edge Interrupt Flag in the REMC Interrupt Flag (REMC_INT) Register (D2/0x5346) To use this interrupt, set REMFIE (D2/REMC_IMSK register) to 1. If REMFIE is set to 0 (default), REMFIF is not set to 1 and the interrupt request for this factor is not sent to the ITC. * REMFIE: Falling Edge Interrupt Enable Bit in the REMC Interrupt Mask (REMC_INT) Register (D2/0x5346) When REMFIF is set to 1, REMC outputs an interrupt request to the ITC. This interrupt request signal sets the REMC interrupt flag to 1 within the ITC, generating an interrupt if the ITC and S1C17 core interrupt conditions are met. REMFIF should be inspected as part of the REMC interrupt processing routine to determine whether the REMC interrupt is attributable to input signal falling edge. The interrupt factor should be cleared as part of the interrupt processing routine by resetting both the ITC REMC interrupt flag and REMC module REMFIF (i.e., setting both to 1). Interrupt vectors The REMC interrupt vector numbers and vector addresses are as listed below. Vector number: 20 (0x14) Vector address: TTBR + 0x50 Other interrupt settings The ITC allows the priority of REMC interrupts to be set between level 0 (the default value) and level 7. To generate actual interrupts, the PSR (S1C17 core internal processor status register) IE (interrupt enable) bit must be set to 1. For more information on interrupt processing, see "6 Interrupt Controller (ITC)." S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 22-9 22 Remote Controller (REMC) 22.7 Control Register Details Table 22.7.1: REMC register list Address 0x5340 0x5342 0x5344 0x5346 Register name REMC_CFG REMC_CAR REMC_LCNT REMC_INT Function REMC Configuration Register REMC Carrier Length Setup Register REMC Length Counter Register REMC Interrupt Mask Register Clock and transfer control Carrier H/L section length setting Transfer bit and tranfer data length setting Interrupt control The REMC registers are described in detail below. These are 16-bit registers. Note: When data is written to the registers, the "Reserved" bits must always be written as 0 and not 1. 22-10 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 22 Remote Controller (REMC) 0x5340: REMC Configuration Register (REMC_CFG) Register name Address REMC Configuration Register (REMC_CFG) Bit Name Function 0x5340 D15-12 CGCLK[3:0] Carrier generator clock select (16 bits) (Prescaler output clock) D11-8 LCCLK[3:0] Length counter clock select (Prescaler output clock) D7-2 - REMMD D1 REMEN D0 reserved REMC mode select REMC enable Setting CGCLK[3:0] LCCLK[3:0] 0xf 0xe 0xd 0xc 0xb 0xa 0x9 0x8 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 1 Receive 1 Enable Init. R/W Clock Remarks 0x0 R/W reserved PCLK-1/16384 PCLK-1/8192 PCLK-1/4096 PCLK-1/2048 PCLK-1/1024 PCLK-1/512 PCLK-1/256 0x0 R/W PCLK-1/128 PCLK-1/64 PCLK-1/32 PCLK-1/16 PCLK-1/8 PCLK-1/4 PCLK-1/2 PCLK-1/1 - - - 0 when being read. 0 Transmit 0 R/W 0 Disable 0 R/W D[15:12] CGCLK[3:0]: Carrier Generator Clock Select Bits Select a carrier generation clock from the 15 prescaler output clocks. Table 22.7.2: Carrier generation clock selection CGCLK[3:0] 0xf 0xe 0xd 0xc 0xb 0xa 0x9 0x8 Prescaler output clock Reserved PCLK-1/16384 PCLK-1/8192 PCLK-1/4096 PCLK-1/2048 PCLK-1/1024 PCLK-1/512 PCLK-1/256 CGCLK[3:0] 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 Prescaler output clock PCLK-1/128 PCLK-1/64 PCLK-1/32 PCLK-1/16 PCLK-1/8 PCLK-1/4 PCLK-1/2 PCLK-1/1 (Default: 0x0) D[11:8] LCCLK[3:0]: Length Counter Clock Select Bits Select a data length counter clock from the 15 prescaler output clocks. Table 22.7.3: Carrier generation clock selection LCCLK[3:0] 0xf 0xe 0xd 0xc 0xb 0xa 0x9 0x8 Prescaler output clock Reserved PCLK-1/16384 PCLK-1/8192 PCLK-1/4096 PCLK-1/2048 PCLK-1/1024 PCLK-1/512 PCLK-1/256 LCCLK[3:0] 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 Prescaler output clock PCLK-1/128 PCLK-1/64 PCLK-1/32 PCLK-1/16 PCLK-1/8 PCLK-1/4 PCLK-1/2 PCLK-1/1 (Default: 0x0) Note: The clock should be set only while the REMC module is stopped (REMEN(D0) = 0). D[7:2] Reserved D1 REMMD: REMC Mode Select Bit Selects the transfer direction. 1 (R/W): Receive 0 (R/W): Transmit (default) S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 22-11 22 Remote Controller (REMC) D0 22-12 REMEN: REMC Enable Bit Permits or prohibit data transfer by the REMC module 1 (R/W): Permitted 0 (R/W): Prohibited (default) Setting REMEN to 1 begins transmission or receiving in accordance with REMMD (D1) settings. Setting REMEN to 0 halts REMC module operations. Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 22 Remote Controller (REMC) 0x5342: REMC Carrier Length Setup Register (REMC_CAR) Register name Address REMC Carrier Length Setup Register (REMC_CAR) Bit Name Function Setting 0x5342 D15-14 - reserved (16 bits) D13-8 REMCL[5:0] L carrier length setup D7-6 - reserved D5-0 REMCH[5:0] H carrier length setup Init. R/W - 0x0 to 0x3f - 0x0 to 0x3f Remarks - - 0 when being read. 0x0 R/W - - 0 when being read. 0x0 R/W D[15:14] Reserved D[13:8] REMCL[5:0]: L Carrier Length Setup Bits Set the carrier signal L section length. (Default: 0x0) Specify a value corresponding to the number of carrier generation clock cycles selected by CGCLK[3:0] (D[15:12]/REMC_CFG register) + 1. Calculate carrier L section length as follows: REMCL + 1 Carrier L section length = ------------ [s] clk_in REMCL: REMCL[5:0] settings clk_in: Prescaler output clock frequency The H section length is specified by REMCH[5:0] (D[5:0]). The carrier signal is generated from these settings as shown in Figure 22.7.1. D[7:6] Reserved D[5:0] REMCH[5:0]: H Carrier Length Setup Bits Set the carrier signal H section length. (Default: 0x0) Specify a value corresponding to the number of carrier generation clock cycles selected by CGCLK[3:0] (D[15:12]/REMC_CFG register) + 1. Calculate carrier H section length as follows: REMCH + 1 Carrier H section length = ------------ [s] clk_in REMCH: REMCH[5:0] settings clk_in: Prescaler output clock frequency The L section length is specified by REMCL[5:0] (D[13:8]). The carrier signal is generated from these settings as shown in Figure 22.7.1. Example: CGCLK[3:0] = 0x2 (PCLK-1/4), REMCH[5:0] = 2, REMCL[5:0] = 1 PCLK PSC output clock Count 0 1 2 0 1 0 Carrier Carrier H section length Carrier L section length Figure 22.7.1: Carrier signal generation S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 22-13 22 Remote Controller (REMC) 0x5344: REMC Length Counter Register (REMC_LCNT) Register name Address 0x5344 REMC Length Counter Register (16 bits) (REMC_LCNT) D[15:8] Bit Name Function D15-8 REMLEN[7:0] Transmit/receive data length count (down counter) D7-1 - reserved REMDT Transmit/receive data 1 1 (H) D0 Setting Init. R/W 0x0 to 0xff 0x0 R/W - 0 0 (L) - 0 Remarks - 0 when being read. R/W REMLEN[7:0]: Transmit/Receive Data Length Count Bits Sets the data length counter value and begins counting. (Default: 0x0) The counter stops when it reaches 0 and generates an underflow interrupt factor. For data transmission Sets the transmit data length for data transmission. When a value corresponding to the data pulse width is written, the data length counter begins counting down from that value, generating an underflow interrupt and halting when the counter reaches 0. The subsequent transmit data is set using this interrupt. For data receiving Interrupts can be generated at the input signal rising or falling edges when receiving data. The data pulse length can be obtained from the difference by setting the data length counter to 0xff using the interrupt when the input changes and reading out the count value when the next interrupt occurs due to an input change. D[7:1] Reserved D0 REMDT: Transmit/Receive Data Bit Sets the transmit data for data transmission. Receive data can be read when receiving data. 1 (R/W): 1 (H) 0 (R/W): 0 (L) (default) If REMEN (D0/REMC_CFG register) is set to 1, the REMDT setting is modulated by the carrier signal for data transmission and output from the REMO pin. For data receiving, this bit is set to the value corresponding to the signal level of the data pulse input. 22-14 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 22 Remote Controller (REMC) 0x5346: REMC Interrupt Control Register (REMC_INT) Register name Address Bit Name REMC Interrupt 0x5346 D15-11 - Control Register (16 bits) D10 REMFIF (REMC_INT) REMRIF D9 REMUIF D8 D7-3 - REMFIE D2 REMRIE D1 REMUIE D0 Function reserved Falling edge interrupt flag Rising edge interrupt flag Underflow interrupt flag reserved Falling edge interrupt enable Rising edge interrupt enable Underflow interrupt enable Setting - 0 Cause of interrupt not occurred 1 Cause of interrupt occurred - 1 Enable 1 Enable 1 Enable 0 Disable 0 Disable 0 Disable Init. R/W - 0 0 0 - 0 0 0 Remarks - 0 when being read. R/W Reset by writing 1. R/W R/W - 0 when being read. R/W R/W R/W This register indicates the occurrence status of interrupt factors arising from data length counter underflow, input signal rising edge, or input signal falling edge. When an REMC interrupt occurs, the interrupt flag in this register should be inspected to identify the interrupt factor. Setting the corresponding interrupt enable bit to 1 sets the interrupt flag to 1 when a data length counter underflow, input signal rising edge, or input signal falling edge occurs. The REMC outputs an interrupt request signal to the ITC at the same time, which sets the REMC interrupt flag to 1 within the ITC and generates an interrupt if the ITC and S1C17 core interrupt conditions are met. Note: * To prevent interrupt recurrences, the REMC module interrupt flag must be reset within the interrupt processing routine following an REMC interrupt. * To prevent generating unnecessary interrupts, reset the interrupt flag before permitting interrupts by the interrupt enable bit. D[15:11] Reserved D10 REMFIF: Falling Edge Interrupt Flag Interrupt flag indicating the falling edge interrupt occurrence status. 1(R): Interrupt factor present 0(R): No interrupt factor (default) 1(W): Reset flag 0(W): Disabled Setting REMFIE (D2/REMC_IMSK register) to 1 sets SIF1 to 1 at the input signal falling edge. D9 REMRIF: Rising Edge Interrupt Flag Interrupt flag indicating the rising edge interrupt factor occurrence status. 1(R): Interrupt factor present 0(R): No interrupt factor (default) 1(W): Reset flag 0(W): Disabled Setting REMRIF (D1/REMC_IMSK register) to 1 sets REMRIE to 1 at the input signal falling edge. D8 REMUIF: Underflow Interrupt Flag Interrupt flag indicating the underflow interrupt factor occurrence status. 1(R): Interrupt factor present 0(R): No interrupt factor (default) 1(W): Reset flag 0(W): Disabled Setting REMUIE (D1/REMC_IMSK register) to 1 sets REMUIF to 1 when a data length counter underflow occurs. D[7:3] Reserved D2 REMFIE: Falling Edge Interrupt Enable Bit Permits or blocks input signal falling edge interrupts. 1 (R/W): Interrupt permitted 0 (R/W): Interrupt prohibited (default) S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 22-15 22 Remote Controller (REMC) D1 REMRIE: Rising Edge Interrupt Enable Bit Permits or blocks input signal rising edge interrupts. 1 (R/W): Interrupt permitted 0 (R/W): Interrupt prohibited (default) D0 REMUIE: Underflow Interrupt Enable Bit Permits or blocks data length counter underflow interrupts. 1 (R/W): Interrupt permitted 0 (R/W): Interrupt prohibited (default) 22-16 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 22 Remote Controller (REMC) 22.8 Precautions * The prescaler must run before operating the REMC module. * To prevent interrupt recurrences, the REMC module interrupt flag must be reset within the interrupt processing routine following an REMC interrupt. * To prevent unwanted interrupts, reset the interrupt flag before permitting interrupts with the interrupt enable bit. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 22-17 23 A/D Converter (ADC10SA) 23 A/D Converter (ADC10SA) 23.1 Outline of A/D Converter S1C17003 has built-in A/D converter with the following characteristics. * Conversion method: Successive approximation type * Resolution: 10 bit * Input channel: 4 channels * A/D Conversion clock: 2MHz (Max.), 16kHz (Min.) * Conversion time: 9 clock (sampling time) + 11 clock (conversion time) = 20 clock Min. 10 sec (when 2 MHz input block selected) Max. 1,250 sec (when 16 kHz input block selected) * Analog input voltage range: VSS-AVDD(=VDD) * Built-in Sampling & hold circuit * Converter mode (4 types): 1 time conversion of single channel 1 time conversion of Multi channels Continuous conversion of single channel (end with software control) Continuous conversion of multi channels (end with software control) * Conversion trigger (3 types): Software trigger External terminal (#ADTRG) trigger 16bit timer Ch.0 underflow trigger * Conversion result 10bit can be read by filling to the upper side /lower side. * Interruption Conversion completion interruption Conversion result overwrite error interruption Figure 23.1.1 shows structure of A/D converter. Prescaller PCLK*1/2 to 1/32768 AVDD - AIN2 AIN1 Successive Approximation Control circuit + Multi plexer D/A converter ITC Bus I/F or Control register AIN0 #ADTRG External Trigger Internal data bus Sampling and converter with hold circuit AIN3 A/D converter clock Timer trigger (16 bit Timer Ch.0) Figure: 23.1.1: A/D Converter Configuration S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 23-1 23 A/D Converter (ADC10SA) 23.2 ADC Terminal Figure 23.2.1 shows input/output terminal list of A/D converter. Table 23.2.1: Input/output terminal of A/D converter Terminal #ADTRG (P03) AIN3 (P17) AIN2 (P20) AIN1 (P21) AIN0 (P22) AVDD I/O Number I I I I I - 1 1 1 1 1 1 Function A/D converter external trigger terminal A/D converter Ch.3 analog input terminal A/D converter Ch.2 analog input terminal A/D converter Ch.1 analog input terminal A/D converter Ch.0 analog input terminal Analog voltage Set as AVDD=VDD. Set as AVDD=VDD, even when A/D converter is not used. P03 #ADTRG * P03MUX: P03 Port Function Select Bit in the P0 Port Function Select (P0_PMUX) Register (D4/0x52a1) P17 AIN3 * P17MUX: P1 Port Function Select Bit in the P1 Port Function Select (P1_PMUX) Register (D2/0x52a3) P20 AIN2 * P20MUX: P2 Port Function Select Bit in the P1 Port Function Select (P2_PMUX) Register (D2/0x52a4) P21 AIN1 * P21MUX: P2 Port Function Select Bit in the P1 Port Function Select (P2_PMUX) Register (D2/0x52a4) P22 AIN0 * P22MUX: P2 Port Function Select Bit in the P1 Port Function Select (P2_PMUX) Register (D2/0x52a4) Refer to "10.2 Input/Output Pin Function Selection (Port MUX)" for the details of terminal function and switching of function. Notes : Be aware that the interface voltage level is AVDD even if the AINx pin is used as an input port (P0x) pin. 23-2 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 23 A/D Converter (ADC10SA) 23.3 A/D Converter Settings To use the A/D converter, the following settings are required in advance. 1. 2. 3. 4. 5. 6. 7. 8. Setting for analog input pins ... See section 23.2 Setting for A/D conversion clock Selection of the start/end channels for analog conversion process Setting of A/D conversion mode Selection of the trigger type Setting of sampling time Setting of conversion result storage mode Setting for interrupts... See section 23.6 Note: Be sure to disable the A/D converter (set ADEN(DO/ADC10_CTL register)=0) before configuring those settings. Changing settings in enabled state can cause a malfunction. * ADEN: A/D Enable Bit in the A/D Control/Status (ADC10_CTL) Register (DO/0x5384) Setting for A/D conversion clock To use the A/D converter, the peripheral clock (PCLK) supplied from the clock generator (CLG) and a division clock supplied from the Prescaler (PSC) must be turned on. For details, refer to the "8.3 Peripheral Module Clock (PCLK) Control", and "9.1 Prescaler Configuration." The A/D converter can select the Prescaler-supplied division clock from 15 types shown in the table 23.3.1.Use ADDF[3:0] (D[3:0]/ADC10_DIV register) for the selection. * ADDF[3:0]: A/D Converter Clock Divided Frequency Selection Bits in the ADCIO Divided Frequency (ADC10_DIV) Register(D[3:0]/Ox5386) Table 23.3.1: Selection of A/D conversion clock ADDF3:0 0xf 0xe 0xd 0xc 0xb 0xa 0x9 0x8 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 A/D clock reserved PCLK*1/32768 PCLK*1/16384 PCLK*1/8192 PCLK*1/4096 PCLK*1/2048 PCLK*1/1024 PCLK*1/521 PCLK*1/256 PCLK*1/128 PCLK*1/64 PCLK*1/32 PCLK*1/16 PCLK*1/8 PCLK*1/4 PCLK*1/2 (Default: 0x0) Note: * For information about restriction of input clock frequencies, refer to "26.5 A/D Converter Characteristics." * Do not start A/D conversion while clock output from the Prescaler to the AD converter is turned off, or turn off clock output from the Prescaler while A/D conversion is in process. It can cause a malfunction. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 23-3 23 A/D Converter (ADC10SA) Selection of the start/end channels for analog conversion process The channels used for the A/D conversion should be selected from pins (channels) configured for analog input. This setting enables single converting operation to process the serial A/D conversion over multiple channels. Use ADCS[2:0] (D[10:8]/ADC10_TRG register) and ADCE[2:0] (D[13:11]/ADC10_TRG register) to specify the start and end channel respectively for conversion process. * ADCS[2:0]: A/D Converter Start Channel Selection Bits in the ADC10 Trigger/Channel Select (ADC10_TRG) Register (D[10:8]/0x5382) * ADCE[2:0]: A/D Converter End Channel Selection Bits in the ADC10 Trigger/Channel Select (ADC10_TRG) Register (D[13:11]/0x5382) Table 23.3.2: Relation between ADCS/ADCE and input channels. ADCS[2:0]/ADCE[2:0] 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 Select channel Dummy ch[7:4] 0 (Vss level) AIN3 AIN2 AIN1 AIN0 (Default: 0x0) Example: A/D conversion process of single operation ADCS[2:0] = 0, ADCE[2:0] = 0: Convert only AIN0. ADCS[2:0] = 0, ADCE[2:0] = 3: Convert serially in the order of AIN0AIN1AIN2AIN3 ADCS[2:0] = 2, ADCE[2:0] = 1: Convert serially in the order of AIN2AIN3(Dummy ch[7:4]) AIN0AIN1 Setting of A/D conversion mode Single conversion or serial conversion can be selected for the A/D converter by using ADMS (D5/ADC10_TRG register). * ADMS: A/D Conversion Mode Selection Bit in the ADC10 Trigger/Channel Select (ADC10_TRG) Register (D6/0x5382) 1. Single conversion mode (ADMS=0) This mode performs a single A/D conversion of all inputs to channels in the range specified by ADCS[2:0] (D[10:8]/ADC10_TRG register) and ADCE[2:0] (D[13:11]/ADC10_TRG register), and then stops. 2. Serial conversion mode (ADMS=1) This mode keeps performing A/D conversion of channels in the range specified by ADCS[2:0] or ADCE[2:0] until software stops the process. The mode is set to single conversion after the initial reset. Selection of the trigger type Select the type of trigger starting A/D conversion from 3 types shown in the table 23.3.2 and specify it by ADTS[1:0] (D[5:4]/ADC10_TRG register). * ADTS[1:0]: A/D Conversion Trigger Selection Bits in the ADC10 Trigger/Channel Select (ADC10_TRG) Register (D[5:4]/0x5382) Table 23.3.3: Selection of the trigger type ADTS[1:0] 0x3 0x2 0x1 0x0 Trigger source External trigger (#ADTRG pin) reserved 16-bit programmable timer Ch.0 Software trigger (Default: 0x0) 23-4 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 23 A/D Converter (ADC10SA) 1. External trigger (#ADTRG) This type uses an input signal via the #ADTRG pin as a trigger. To use this trigger type, the #ADTRG pin must be configured using the Port Function Select Register. This type starts A/D conversion by detecting negative edge of #ADTRG signal. 2. 16-bit timer (T16) Ch.0 This type uses an underflow signal of 16-bit timer (T16) Ch.0 as a trigger. The type is effective when periodic A/D conversion is required because the cycle of the signal can be configured programmably by the timer. For settings for the timer, refer to "11 16-bit Timer (T16)." 3. Software trigger This type uses the software's writing 1 to ADCTL (D1/AD_CTL register) as a trigger to start A/D conversion. * ADCTL: A/D Conversion Control/Status Bit in the ADC10 Control/Status (ADC10_CTL) Register (D1/0x5382) Setting of sampling time This A/D converter provides ADST[2:0] (D[2:0]/ADC10_TRG register) enabling the input sampling time of analog signals to be configured to 8 steps (2 to 9 of the conversion clock). The register must be set to default (ADST[2:0]=111). * ADST[2:0]: Sampling Clock Count Bits in the ADC10 Control/Status (AD_CTL) Register (D[2:0]/0x5382) Setting of conversion result storage mode After completing A/D conversion, this 10-bit A/D converter stores the 10-bit conversion result in the A/D conversion result storage register ADD[15:0] (D[15:0]/ADC10_ADD register). * ADD[15:0]: A/D Converted Data Bits in the ADC10 Conversion Result (ADC10_ADD) Register (D[15:0]/ 0x5380) The conversion result storage mode can configure STMD (D[7]/ADC10_TRG register), and select either highorder or low-order to store 10-bit A/D conversion result in ADD[15=0]. * STMD: Converted Data Store Mode Bits in the ADC10 Trigger/Channel Select (ADC10_TRG) Register (D[7]/0x5382) STMD=0: ADD[15:10]=0, ADD[9]= conversion result [MSB], ADD[0]= conversion result [LSB] STMD=1: ADD[15]=[MSB], ADD[6]= conversion result [LSB], ADD[5:0]=0 S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 23-5 23 A/D Converter (ADC10SA) 23.4 A/D Conversion Control and Operations The following shows the process of A/D conversion operation 1. Activating A/D converter circuit 2. Starting A/D conversion 3. Reading A/D conversion result 4. Completing A/D conversion Activating A/D converter circuit After configuring settings shown in the previous section, write 1 to ADEN (DO/ADC10_CTL register) to enable the A/D converter. This allows the A/D converter to permit a trigger to start A/D conversion. To reconfigure or disable the A/D converter, set the ADEN bit to 0. * ADEN: A/D Enable Bit in the ADC10 Control/Status (ADC10_CTL) Register (D0/0x5384) Starting A/D conversion The A/D converter starts A/D conversion if a trigger is input when the ADEN bit is set to 1. When software trigger is selected, A/D conversion starts by writing 1 to ADCTL (Dl/ADC10_CTL register). * ADCTL: A/D Conversion Control Bit in the ADC10 Control/Status (ADC10_CTL) Register (D1/0x5384) Triggers other than selected by ADTS[1:0](D[5:4]/ADC10_TRG register) are not permitted. * ADTS[1:0]: A/D Conversion Trigger Selection Bits in the ADC10 Trigger/Channel Select (ADC10_TRG) Register (D[5:4]/0x5382) Once a trigger is input, the A/D converter processes the sampling of analog input signals from the conversion starting channel selected by ADCS[2:0] (D[10:8]/ADC10_TRG register) to perform A/D conversion. * ADCS[2:0]: A/D Converter Start Channel Selection Bits in the ADC10 Trigger/Channel Select (ADC10_TRG) Register (D[10:8]/0x5382) The ADCTL bit used for software trigger turns to 1 even by the trigger of other type, enabling itself to be used as the status bit for A/D conversion. ADICH[2:0] (D[2=0]/ADC10_CTL register) can read the channel in conversion process. * ADICH[2:0]: Internal Conversion Channel Status Bits in the ADC10 Control/Status (ADC10_CTL) Register (D[14:12]/0x5384) Reading A/D conversion result After completing A/D conversion, the A/D converter stores conversion result in 10-bit data register ADD[15:0] (D[15:0]/ADC10_ADD register), and set the conversion complete flag ADCF (D8/ADC10_CTL register). If ADCS[2:0] (D[10:8]/ADC10_TRG register) and ADCE[2:0] (D[13:11]/ADC10_TRG register) specify multiple channels, the A/D converter continues A/D conversion for subsequent channels. * ADD[15:0]: A /D Converted Data Bits in the ADC10 Conversion Result (ADC10_ADD) Register (D[15:0]/0x5380) * ADCF: Conversion-Complete Flag Bit in the ADC10 Control/Status (ADC10_CTL) Register (D8/0x5384 * ADCE[2:0]: End Channel Selection Bits in the ADC10 Trigger/Channel Select (ADC10_TRG) Register (D[13:11]/0x5382) A/D conversion result is stored in ADD[15:0] each time when conversion for a channel is completed. The conversion complete interrupt can be generated concurrently with the storing. The interrupt is usually used to read converted data. If you do not use the conversion complete interrupt, check that the conversion complete factor ADCF (D8/ADD[15:0] register) is set to 1, and then read conversion result from ADD ADD[15:0]. By reading the ADD [15:0] value, the conversion complete interrupt and the ADCF flag are automatically set to 0. 23-6 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 23 A/D Converter (ADC10SA) When the serial conversion mode has been selected, conversion result must be read from ADD[15:0] before the next conversion is completed. If you cannot read the conversion result before ADD[15:0] is updated while the conversion complete flag ADCF (D8/ADC10_CTL register) is set to 1, the overwrite error flag ADOWE (D9/ADC10_CTL register) is set to 1, so that you can check that the conversion result has been overwritten. You can also generate the conversion data overwrite interrupt concurrently with overwriting. After reading the conversion result from ADD[15:0], read also the ADOWE flag, or check that the conversion data overwrite interrupt has not occurred so that the read data is valid. Once the ADOWE flag has been set, it is not reset until software write 1 to the flag. If the ADOWE flag has been reset, the conversion data overwrite interrupt can be stopped to occur. Note that setting ADOWE flag to 1 also sets the ADCF flag. Therefore, read converted data to reset ADCF to 0. * ADOWE: Overwrite Error Flag Bit in the ADC10 Control/Status (ADC10_CTL) Register (D9/0x5384) Note: Occurrence of an overwrite error does not stop serial conversion process. Completing A/D conversion * For single conversion mode (ADMS=0) Single conversion mode stops the conversion process once completing a cycle from the start channel specified by ADCS[2:0] (D[10:8]/ADC10_TRG register) to the end channel ADCE[2:0] (D[13:11]/ADC10_TRG register). After the completion, ADCTL (D1/ADC10_CTL register) is returned to 0. * ADMS: Conversion Mode Selection bit in the ADC10 Trigger/Channel Select (ADC10_TRG) Register (D6/0x5382) * For serial conversion mode (ADMS=1) Serial conversion mode maintains the A/D conversion cycles from the start channel to the end channel continuously. Hardware in this mode does not stop the cycles. Use software to set ADCTL (D1/ADC10_CTL register) to 1 to terminate the process forcibly. You cannot get data under A/D conversion process when forcible termination occurs. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 23-7 23 A/D Converter (ADC10SA) Figure 23.4.1 shows A/D conversion operation. ADEN Conversion Trigger ADIBS A/D operation Sampling Conversion AIN0(Ch0) AIN0(Ch0) ADD AIN0 (Ch0) conversion result ADCF Clear Conversion result reading ADOWE Interrupt request (1) Single channel (ADCS=0, ADSE=0) single conversion (ADMS=0) mode ADEN Conversion Trigger ADIBS A/D operation Sampling Conversion Sampling Conversion Sampling Conversion AIN0(Ch0) AIN0(Ch0) AIN1(Ch1) AIN1(Ch1) AIN2(Ch2) AIN2(Ch2) AIN0 (Ch0) conversion result AIN1 (Ch1) conversion result ADD AIN2 (Ch2) conversion result ADD overwrite ADCF Clear Conversion result reading ADOWE Interrupt request (2) Multi channels [AIN0(ch0)-AIN2(ch2)] (ADCS=0, ADSE=2) single conversion (ADMS=0) mode ADEN Conversion Trigger ADIBS A/D operation Conversion stop writing ADCTL=0 Sampling Conversion Sampling Conversion Sampling Conversion AIN0(Ch0) AIN0(Ch0) AIN1(Ch0) AIN1(Ch1) AIN0(Ch0) Invalid AIN0 (Ch0) conversion result AIN1 (Ch1) conversion result ADD ADCF Clear Conversion result reading Clear ADOWE Interrupt request (3) Multi channels [AIN0(ch0)-AIN1(ch1)] (ADCS=0, ADSE=1) continuous conversion (ADMS=1) mode ADEN Conversion Trigger ADIBS A/D operation ADD Conversion stop writing ADCTL=0 Sampling Conversion Sampling Conversion Sampling Conversion AIN0(Ch0) AIN0(Ch0) AIN1(Ch1) AIN1(Ch1) AIN0(Ch0) Invalid AIN0 (Ch0) conversion result AIN1 (Ch1) conversion result Clear Clear ADCF Conversion result reading ADOWE Interrupt request (4) Multi channels [AIN0(ch0)-AIN1(ch1)] (ADCS=0, ADSE=1) continuous conversion (ADMS=1) mode Figure 23.4.1: Operation of A/D conversion 23-8 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 23 A/D Converter (ADC10SA) 23.5 A/D Converter interrupt The A/D converter provides function of generating the following 2 types of interrupts. * Conversion complete interrupt * Conversion data overwrite interrupt The A/D converter outputs an interrupt signal shared by those 2 types of interrupt factors to the interrupt controller (ITC). To determine the generated interrupt factor, read a relevant interrupt factor register. Conversion complete interrupt Once completing A/D conversion for a channel, and if ADCIE (D4/ADC10_CTL register) is set to 1 (default:0), the A/D converter outputs the conversion complete interrupt signal to the controller (ITC) to request an interrupt. * ADCIE: Conversion-Complete Interrupt Enable Bit in the ADC10 Control/Status (ADC10_CTL) Register (D4/0x5384) By reading ADD[15:0] (D[15:0]/ADC10_ADD register), the conversion complete interrupt factor is automatically cleared, and ADCF (D8/ADC10_CTL register) is also reset from 1 to 0. To disable generation of the conversion complete interrupt, set the ADCIE bit to 0. Conversion data overwrite interrupt When the ADD[15:0] register has not been read before it is overwritten by the subsequent A/D conversion result, and if ADOIE (D5/ADC10_CTL register) is set to 1 (default:0), the A/D converter outputs the conversion data overwrite interrupt signal to the controller (ITC) to request an interrupt. * ADOIE: Overwrite Interrupt Enable Bit in the ADC10 Control/Status (ADC10_CTL) Register (D5/0x5384) By writing 1 to ADOWE (D9/ADC10_CTL register), the conversion data overwrite interrupt factor is reset to 0. * ADOWE: Overwrite Error Flag Bit in the ADC10 Control/Status (ADC10_CTL) Register (D9/0x5384) To disable generation of the conversion data overwrite interrupt, set the ADOIE bit to 0. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 23-9 23 A/D Converter (ADC10SA) ITC register for A/D converter interrupts Table 23.5.1 shows the ICT control register corresponding to the A/D converter interrupt factors. Table 23.5.1: ITC register Interrupt factor Conversion complete/Conversion data overwrite interrupt level setting bit ILV18[2:0] (D[2:0]/ITC_LV9) ITC_LV9 register (0x4318) Specify the A/D converter interrupt level (0 to 7) for the interrupt level bit. If the same interrupt level is specified, out-of-range interrupts have higher priority while the conversion complete interrupt has lower. The S1C17 core permits an interrupt when all of the following conditions are met: * The interrupt enable bit of the A/D converter module is set to 1. * The IE (interrupt enable) bit of the processor status register inside the S1C17 core (PSR) is set to 1. * A/D converter interrupts are set to higher level than the value set in Interrupt Level (IL) of PSR. * NMI or other interrupt factor with higher priority has not occurred. For details on the interrupt control register and its operation when an interrupt occurs, refer to "6. Interrupt Controller (ITC)." Interrupt vector The following shows the vector number and address of A/D converter interrupts. Table 23.5.2: A/D converter interrupt vector Interrupt factor Conversion complete/Conversion data overwrite 23-10 Vector No. 22 (0x16) Seiko Epson Corporation Vector address TTBR + 0x58 S1C17003 TECHNICAL MANUAL 23 A/D Converter (ADC10SA) 23.6 Controlling Register Details Table 23.6.1: ADC10SA register list Address 0x5380 0x5382 0x5384 0x5386 Register name ADC10_ADD ADC10_TRG ADC10_CTL ADC10_DIV ADC10 Conversion Rersult Register ADC10 Trigger/Channel Select Register ADC10 Control/Status Register ADC10 Divided Frequency Register Function AD conversion result Setting of conversion trigger/conversion channel Conversion control, conversion status A/D conversion clock division setting Each register of ADC10SA module is explained below. These are 16 bites registers. Note: Write 0 in "Reserved" bit while writing the data to the register. Do not write 1. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 23-11 23 A/D Converter (ADC10SA) 0x5380: ADC10 Conversion Result Register (ADC10_ADD) Register name Address A/D Conversion 0x5380 Result Register (16 bits) (ADC10_ADD) D[15:0] Bit Name D15-0 ADD[15:0] Function A/D converted data @STMD=0 ADD[15:10]=60, ADD9=MSB, ADD0=LSB @STMD=1 ADD15=MSB, ADD6=LSB, ADD[5.:0]=60 Setting 0-1023 Init. R/W 0 Remarks R ADD[15:0]: A/D Converted Data Bits A/D conversion result is stored. Storage methods can be changed by settings of STMD register. STMD=0 ADD[15:10]=0, ADD[9]=MSB, ADD[0]=LSB STMD=1 ADD[15]=MSB, ADD[6]=LSB, ADD[5:0]=0 This register is read only so writing is not possible. Data is 0 at the time of initial setting. 23-12 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 23 A/D Converter (ADC10SA) 0x5382: ADC10 Trigger/Channel Selection Register (ADC10_TRG) Register name Address A/D trigger/ Channel Select (ADC10_TRG) Bit Name Function 0x5382 D15-14 - (16 bits) D13-11 ADCE[2:0] D10-8 ADCS[2:0] D7 STMD reserved End channel selection Start channel selection Covnerted data store mode D6 D5-4 ADMS ADTS[1:0] Conversion mode selection Conversion trigger selection D3 D2-0 - ADST[2:0] reserved Sampling clock count Setting - 0x0-0x7 0x0-0x7 1 {AD[9:0], 6' 0 {6'b0, b0} AD[9:0]} 1 continuous 0 single ADST[1:0] trigger #ADTRG pin 0x3 reserved 0x2 16bit timer 0x1 software 0x0 - ADST[2:0] count clock 9clocks 0x7 8clocks 0x6 7clocks 0x5 6clocks 0x4 5clocks 0x3 4clocks 0x2 3clocks 0x1 2clocks 0x0 Init. R/W Remarks - 0 0 0 - 0 when being read. R/W R/W R/W 0 0 R/W R/W - - 0 when being read. 0x7 R/W Must set 0x7 D[15:14] Reserved D[13:11] ADCE[2:0]: End Channel Selection Bits Set the conversion end channel within (0-7) channel numbers. Analog input from the channel set by ADCS register up to the channel set by register can be converted continuously in 1 A/D conversion. When A/D is to be converted only for 1 channel, set the same channel numbers in ADCS register and ADCE register. ADCE is set to 0 (AIN0) at the time of initial reset. D[10:8] ADCS[2:0]: Start Channel Selection Bit Set the conversion start channel with channel numbers (0-7). Analog input from the channel set by this register up to the channel set by ADCE register can be converted continuously in 1 A/D conversion. When A/D is converted for only 1 channel, set the same channel number in ADCS register and ADCE register. ADCS is set to 0 (AIN0) at the time of initial reset. D7 STMD: Converted Data Store Mode Bit Select the method to store conversion result to ADD register. For the details, refer to ADD register. STMD is set to 0 (ADD [15:10]=6'b0, ADD[9]=MSB, ADD[0]=LSB) at the time of initial reset. D6 ADMS: Conversion Mode Selection Bit Select the A/D conversion mode. 1 (R/W) : Continuous conversion mode 0 (R/W) : Single conversion mode A/D converter is set to continuous mode by writing 1 to ADMS. A/D conversion in the range of channel selected by ADCS and ADCE can be performed continuously till software stops it. When ADMS is 0, it operates in single conversion mode and A/D conversion for all inputs in the range of channel selected by ADCS and ADCE register is performed once and stopped. ADMS is set to 0 (single conversion mode) at the time of initial reset. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 23-13 23 A/D Converter (ADC10SA) D[5:4] ADTS [1:0]: Conversion Trigger Selection Bits Select the trigger method by which A/D conversion is started. Table 23.6.2: Trigger selection ADTS1 ADTS0 1 1 0 0 1 0 1 0 Trigger External trigger (# ADTRG) Reserved 16 bits programmable timer Software When external trigger is used, select the # ADTRG from the port MUX (For the details, refer to I/O port section and port MUX section). When 16 bits programmable timer ch0 is used, since the underflow signal becomes trigger, set the period and other settings by programmable timer. ADTS is set to 0 (software trigger) at the time of initial reset. D3 Reserved D[2:0] ADST [2:0]: Sampling clock Count Bits Sets the sampling time of analog input. Table 23.6.3: Trigger selection ADST2 ADST1 ADST0 Sampling time 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 9 clocks 8 clocks 7 clocks 6 clocks 5 clocks 4 clocks 3 clocks 2 clocks Clock number is an input clock number of A/D converter. ADST is set to 111 (9 clocks) at the time of initial reset. ADST must be set to 111 (9 clocks). Do not change the register value. 23-14 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 23 A/D Converter (ADC10SA) 0x5384: ADC10 Control/Status Register (ADC10_CTL) Register name Address Bit 0x5384 D15 A/D Control/ Status Register (16 bits) D14-12 (ADC10_CTL) D11 D10 D9 D8 D15 Name - ADICH - ADIBS ADOWE ADCR D7-6 D5 D4 - ADOIE ADCIE D3-2 D1 D0 - ADCTL ADEN Function Setting reserved - Internal conversion channel status 0x0-0x7 reserved - Internal busy status 1 busy 0 idle Overwrite error flag 1 Error 0 Normal Conversion-complete flag 1 Completed 0 Not conmpleted reserved Overwrite interrupt enable 1 Enable 0 Disable Conversion-complete interrupt 1 Enable 0 Disable enable reserved conversion control 1 Start/Run 0 Stop A/D enable 1 Enable 0 Disable Init. R/W Remarks - 0 - 0 0 0 - R - R R/W R 0 when being read. - 0 0 - R/W R/W - 0 0 - 0 when being read. R/W Stop by writing 0 R/W 0 when being read. Reset by writing 1 Reset when ADADD is read. 0 when being read. Reserved D[14:12] ADICH [2:0]: Internal Conversion Channel Status Bits Shows the channel numbers (0-7) during A/D conversion (4-7 are Dummy ch). When multi channels make A/D conversion, channels currently under conversion can be confirmed by reading this bit. ADICH is set to 0 (AIN0) at the time of initial reset. D11 Reserved D10 ADIBS: Internal Busy status Bits Shows the status of A/D converter. 1 (R/W) : during conversion 0 (R/W) : Conversion complete 1 is output during A/D conversion and 0 is output after A/D conversion completion. D9 ADOWE: Overwrite Error Flag Bit This is an interruption flag indicating the status of conversion data overwrite cause 1 (R) : With Interruption cause 0 (R) : Without interruption cause (default) 1 (W) : Reset the flag 0 (W) : Disable When multi channels make A/D conversion, ADOWE set to 1 if conversion result of next channel is written (overwritten) to conversion data register before resetting the conversion end flag ADCF set by conversion of previous channel by reading conversion data. At that time, if the ADOIE (D5/ ADC10_CTL register) is set to 1, overwrite interruption request signal related for ITC is output. If interruption conditions of ITC and S1C17 core are valid, interruption will be occurred. ADOWE is reset by writing 1. Note: * After generating overwrite interruption, it is necessary to reset the ADOWE in interruption process routine to prevent the regeneration of same interruption. * B efore permitting overwrite interruption by ADOIE, reset the ADOWE to prevent the generation of unnecessary interruption. D8 ADCF: Conversion Complete Flag Bit It is an interruption flag indicating condition for generating conversion completion cause. 1 (R) : With interruption cause 0 (R) : Without interruption cause (default) 1 (W) : Disable 1 (W) : Disable S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 23-15 23 A/D Converter (ADC10SA) After completion of A/D conversion, if the conversion data is stored to ADD(D[15:0]/ADC10_ADD register) it is set to 1. At that time, if the ADCIE(D4/ADC10_CTL register) is set to 1, conversion completion interruption request signal for ITC is output. If interruption conditions of ITC and S1C17 core are valid, interruption will be occurred. It is reset to 0 by reading ADD. When multiple channels make A/D conversion, if next A/D conversion is finished in the status where ADCF is 1 (before reading conversion data), data register overwrites to the new conversion result and overwrite error is generated. Therefore, it is necessary to reset the ADCF by reading the conversion data before completing the next A/D conversion. D[7:6] Reserved D5 ADOIE: Overwrite Interrupt Enable Bit Permits or prohibits the generation of overwrite interruption of A/D conversion result for CPU. 1 (R/W) : Interruption permitted 0 (R/W) : Interruption prohibited In the interruption enable bit that controls the overwrite interruption of A/D conversion result, when ADOIE is set to 1, interruption is permitted and when it sets to 0, interruption is prohibited. ADOIE is set to 0 (Interruption prohibition) at the time of initial reset. D4 ADCIE: Conversion-complete Interrupt Enable Bit Permits or prohibits the generation of A/D conversion complete interrupt for CPU. 1 (R/W) : Interruption permitted 0 (R/W) : Interruption prohibited In the interruption enable bit that controls the A/D conversion complete interruption, when ADCIE is set to 1, interruption is permitted and when it sets to 0, interruption is prohibited. ADCIE is set to 0 (Interruption prohibition) at the time of initial reset. D[3:2] Reserved D1 ADCTL: Conversion Control Bit Controls the A/D conversion. 1 (R/W) : Software trigger 0 (R/W) : A/D conversion stop If the A/D conversion is started by software trigger, 1 is written to ADCTL. In case of other trigger methods, ADCTL is set to 1 by hardware. ADCTL retained to 1 during A/D conversion. At the time of single conversion mode, if the A/D conversion of specified channels is stopped, ADCTL returns to 0 and A/D conversion circuit is stopped. When A/D conversion of continuous mode is stopped, write 0 to ADCTL. When ADEN is 0, a trigger is not accepted. ADCTL is set to 0 (A/D conversion stop) at the time of initial reset. D0 ADEN: A/D Enable Bit Set the A/D converter to enable (conversion possible status). 1 (R/W) : Enable 0 (R/W) : Disable A/D converter is enabled by writing 1 to ADEN and it is a condition where A/D conversion (trigger can be received) can be started. When ADEN is 0, A/D converter is set to default status and trigger is not received. Furthermore, when the A/D converter of mode and start/complete channels is to be set, it is set after setting ADEN to 0 in order to avoid the error operation. ADEN is set to 0 (disable) at the time of initial reset. 23-16 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 23 A/D Converter (ADC10SA) 0x5386: ADC10 Divided Frequency Register (ADC10_DIV) Register name Address 0x5386 A/D Divided Frequency Reg- (16 bits) ister (ADC_DIV) Bit Name D15-4 D3-0 ADDF[3:0] Function reserved A/D converter clock divided frequency select Setting 0-1023 ADDF[3:0] clock 0xf Reserved 0xe PCLK.1/32768 0xd PCLK.1/16384 0xc PCLK.1/8192 0xb PCLK.1/4096 0xa PCLK.1/2048 0x9 PCLK.1/1024 0x8 PCLK.1/512 0x7 PCLK.1/256 0x6 PCLK.1/128 0x5 PCLK.1/64 0x4 PCLK.1/32 0x3 PCLK.1/16 0x2 PCLK.1/8 0x1 PCLK.1/4 0x0 PCLK.1/2 D[15:4] Reserved D[3:0] ADCTL: A/D Converter Clock Divided Frequency Select Bits A/D conversion clock can be selected from 16 types mentioned above. Init. R/W 0 0 Remarks R 0 when being read. R/W Note: * Prescaler should be operated is the precondition for the operation of A/D converter. For the details, refer to CLG chapter, PCLK control section, PSC chapter, prescaler structure section. * For information about restriction of input clock frequencies, refer to "26.5 A/D Converter Characteristics." * W hen the clock output from prescaler to A/D converter is OFF, never start the A/D conversion nor set the clock output of prescaler during A/D conversion operation to OFF. Otherwise it may cause an error. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 23-17 23 A/D Converter (ADC10SA) 23.7 Notes * When A/D converter like mode or start/complete channel is to be set, A/D converter should be set to disable status (ADEN (D0/ADC10_CTL register) is 0). It may cause an error if enable status is changed. * For information about restriction of A/D conversion clock frequencies, refer to "26.5 A/D Converter Characteristics." * If the clock output from prescaler to A/D converter is OFF, never start the A/D conversion nor set the clock output of prescaler during A/D conversion operation to OFF. Otherwise it may cause an error. * ADCF (D8/ADC_CTL register) and ADOWE (D9/ADOWE) will not be fixed after initial reset. Reset the program to prevent the generation of unnecessary interruption. * After interruption, reset the PSR or interruption cause flag before executing instruction to prevent regeneration of interruption due to same reason. * If the external triggers are used as A/D conversion triggers, ensure to maintain the length more than 2 cycles of S1C17 core operation clock for Low period of input to # ADTRG terminal. 23-18 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 24 On-chip Debugger (DBG) 24 On-chip Debugger (DBG) 24.1 Resource Requirements and Debugging Tool Debugging work area Debugging requires a 64-byte debugging work area. In the S1C17003, RAM addresses 0x0007c0 to 0x0007ff are assigned as the debugging work area. When using the debugging function, avoid using this area for any other user applications. The start address for this debugging work area can be read from the DBRAM register (0xffff90). Debugging tool Debugging involves connecting an ICD (In-Circuit Debugger) such as S5U1C17001H (ICD Mini) to the S1C17003 debug pin and inputting the debug instruction from the PC debugger. The following tools are required: * S1C17 Family In-Circuit Debugger (e.g., S5U1C17001H) * S1C17 Family C compiler package (S5U1C17001C) Debug pins The following debug pins are used to connect an ICD (e.g., S5U1C17001H). Table 24.1.1: Debug pin list Pin name DCLK (P43) I/O O Qty 1 DSIO (P41) I/O 1 DST2 (P42) O 1 Function On-chip debugger clock output pin Outputs a clock to the ICD. On-chip debugger data input/output pin Used for inputting/outputting debugging data and inputting break signals. On-chip debugger status signal output pin Outputs the processor status during debugging. Shared with general purpose input/output port pins (P43, P42, P41), the on-chip debugger input/output pins (DCLK, DST2, DSIO) are initially set for use as debugger pins. If the debugging function is not used, these pins can be switched via the P4_PMUX register to enable use as general purpose input/output port pins. Set the control bits shown below to 1 to switch the pins to general purpose input/output port use. DCLK P43 * P43MUX: P43 Port Function Select Bit in the P4 Port Function Select (P4_PMUX) Register (D6/0x52a8) DST2 P42 * P42MUX: P42 Port Function Select Bit in the P4 Port Function Select (P4_PMUX) Register (D4/0x52a8) DSIO P41 * P41MUX: P41 Port Function Select Bit in the P4 Port Function Select (P4_PMUX) Register (D2/0x52a8) For more information on pin function and switching, refer to "10.2 Input/Output Pin Function Selection (Port MUX)." S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 24-1 24 On-chip Debugger (DBG) 24.2 Debug Break Operation Status The S1C17 core switches to debug mode when the brk instruction is executed or a debug interrupt is generated by a break signal (Low) input to the DSIO pin. This state persists until the retd instruction is executed. During this time, hardware interrupts and NMIs are disabled. The default setting halts peripheral circuit operations. This setting can be modified even when debugging is underway. Peripheral circuits that operate using the prescaler output clock * * * * * * * * * 8-bit timer 16-bit timer PWM timer Remote controller P port UART SPI I2C (master/slave) ADC With the default settings, the prescaler will stop in debug mode, also stopping the peripheral circuits above that use the prescaler output clock. The prescaler includes PRUND (D1/PSC_CTL register) to specify prescaler operations during debug mode. When PRUND is set to 1, the prescaler operates even in debug mode, allowing the peripheral circuits above to operate as well. When PRUND is 0 (default), the prescaler and the peripheral circuits above will stop when the S1C17 core switches to debug mode. * PRUND: Prescaler Run/Stop Setting (in Debug Mode) Bit in the Prescaler Control (PSC_CTL) Register (D1/0x4020) Peripheral circuits that operate using the OSC1 clock * * * * Clock timer Watchdog timer Stopwatch timer 8-bit OSC1 timer The MISC register includes O1DBG (D0/MISC_OSC1 register) to specify the operation of the above OSC1 peripheral circuits during debug mode. When O1DBG is set to 1, the OSC1 peripheral circuits operate even in debug mode. When O1DBG is 0 (default), the OSC1 peripheral circuits will stop when the S1C17 core switches to debug mode. * O1DBG: OSC1 Peripheral Control (in Debug Mode) Bit in the OSC1 Peripheral Control (MISC_OSC1) Register (D0/0x5324) 24-2 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 24 On-chip Debugger (DBG) 24.3 Additional Debugging Function The S1C17003 expands the following on-chip debugging functions of the S1C17 core. Branching destination in debug mode When a debug interrupt is generated, the S1C17 core enters debug mode and branches to the debug processing routine. In this process, the S1C17 core is designed to branch to address 0xfffc00. In addition to this branching destination, the S1C17003 also allows designation of address 0x0 (beginning address of internal RAM) as the branching destination when debug mode is activated. The branching destination address is selected using DBADR (D8/MISC_IRAMSZ register). When the DBADR is set to "0" (default), the branching destination is set to 0xfffc00. When it is set to "1," the branching destination is set to 0x0. * DBADR: Debug Base Address Select Bit in the IRAM Size Select (MISC_IRAMSZ) Register (D8/0x5326) Adding instruction breaks The S1C17 core supports two instruction breaks (hardware PC breaks). The S1C17003 increased this number to five, adding the control bits and registers given below. * IBE2: Instruction Break #2 Enable Bit in the Debug Control (DCR) Register (D5/0xffffa0) * IBE3: Instruction Break #3 Enable Bit in the Debug Control (DCR) Register (D6/0xffffa0) * IBE4: Instruction Break #4 Enable Bit in the Debug Control (DCR) Register (D7/0xffffa0) * IBAR2[23:0]: Instruction Break Address #2 Bits in the Instruction Break Address (IBAR2) Register 2 (D[23:0]/0xffffb8) * IBAR3[23:0]: Instruction Break Address #3 Bits in the Instruction Break Address (IBAR3) Register 3 (D[23:0]/0xffffbc) * IBAR4[23:0]: Instruction Break Address #4 Bits in the Instruction Break Address (IBAR4) Register 4 (D[23:0]/0xffffd0) To use five hardware PC breaks (including four user breaks, and one reserved), the S1C17 Software Integrated Development Environment GNU17 (ver. 1.2.1 or later) must be installed. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 24-3 24 On-chip Debugger (DBG) 24.4 Control Register Details Table 24.4.1: Debug register list Address 0x5322 0x5326 0xffff90 0xffffa0 0xffffb8 0xffffbc 0xffffd0 Register name MISC_OSC1 MISC_IRAMSZ DBRAM DCR IBAR2 IBAR3 IBAR4 Function OSC1 Peripheral Control Register IRAM Size Select Register Debug RAM Base Register Debug Control Register Instruction Break Address Register 2 Instruction Break Address Register 3 Instruction Break Address Register 4 OSC1 operation peripheral function setting for debugging IRAM size selection Debug RAM base address display Debug control Instruction break address #2 setting Instruction break address #3 setting Instruction break address #4 setting The debug registers are described in detail below. These are 8-bit registers. Note: * When data is written to the registers, the "Reserved" bits must always be written as 0 and not 1. * For debug registers not described here, refer to the S1C17 Core Manual. 24-4 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 24 On-chip Debugger (DBG) 0x5322: OSC1 Peripheral Control Register (MISC_OSC1) Register name Address OSC1 Peripheral 0x5322 Control Register (16 bits) (MISC_OSC1) Bit Name D15-1 - D0 O1DBG Function reserved OSC1 peripheral control in debug 1 Run mode D[7:1] Reserved D0 O1DBG: OSC1 Peripheral Control in Debug Mode Bit Sets OSC1 peripheral circuit operation in debug mode. 1 (R/W): Operate 0 (R/W): Stop (default) Setting - 0 Stop Init. R/W - 0 Remarks - 0 when being read. R/W OSC1 peripheral circuit refers to the following peripheral circuits that operate using the OSC1 clock. * Clock timer * Watchdog timer * Stopwatch timer * 8-bit OSC1 timer S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 24-5 24 On-chip Debugger (DBG) 0x5326: IRAM Size Select Register (MISC_IRAMSZ) Register name Address Bit IRAM Size 0x5326 Select Register (16 bits) (MISC_IRAMSZ) D15-9 D8 D7-2 D1-0 Name Function - reserved DBADR Debug base address select - reserved IRAMSZ[1:0] IRAM size select Setting Init. R/W - 1 0x0 0 0xfffc00 - IRAMSZ[1:0] 0x3 0x2 0x1 0x0 D[15:9] Reserved D8 DBADR: Debug Base Address Select Bit Selects the address to branch to in the event of a debug interrupt. 1(R/W): 0x0 0(R/W): 0xfffc00 (default) D[7:2] Reserved D[1:0] IRAMSZ[1:0]: IRAM Size Select Bits Selects the size of the internal RAM to be used. Read cycle 2KB 4KB 8KB 12KB Remarks - - 0 when being read. 0 R/W - - 0 when being read. 0x0 R/W Table 24.4.2 Selecting the size of internal RAM IRAMSZ[1:0] 0x3 0x2 0x1 0x0 Internal RAM size 2KB 4KB 8KB 12KB (Default: 0x2) Note: The IRAM Size Select Register is write-protected. To rewrite this register, the write-protection must be overridden by writing 0x96 to the MISC Protect Register (0x5324). Normally, the MISC Protect Register (0x5324) should be set to a value other than 0x96, except when rewriting the IRAM Size Select Register. Unnecessary rewriting of the IRAM Size Select Register may result in system malfunctions. 24-6 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 24 On-chip Debugger (DBG) 0xffff90: Debug RAM Base Register (DBRAM) Register name Address Debug RAM Base Register (DBRAM) Bit Name Function 0xffff90 D31-24 - Unused (fixed at 0) (32 bits) D23-0 DBRAM[23:0] Debug RAM base address Setting Init. R/W 0x0 0x0fc0 0x0 0x0f c0 Remarks R R D[31:24] Not used (Fixed at 0) D[23:0] DBRAM[23:0]: Debug RAM Base Address Bits Read-only register containing the initial address of the debugging work area (64 bytes). S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 24-7 24 On-chip Debugger (DBG) 0xffffa0: Debug Control Register (DCR) Register name Address Bit 0xffffa0 (8 bits) D7 D6 D5 D4 D3 D2 D1 D0 Debug Control Register (DCR) D7 Name IBE4 IBE3 IBE2 DR IBE1 IBE0 SE DM Function Instruction break #4 enable Instruction break #3 enable Instruction break #2 enable Debug request flag Instruction break #1 enable Instruction break #0 enable Single step enable Debug mode Setting 1 1 1 1 1 1 1 1 Enable Enable Enable Occurred Enable Enable Enable Debug mode 0 0 0 0 0 0 0 0 Init. R/W Disable Disable Disable Not occurred Disable Disable Disable User mode 0 0 0 0 0 0 0 0 Remarks R/W R/W R/W R/W Reset by writing 1. R/W R/W R/W R IBE4: Instruction Break #4 Enable Bit Permits or prohibits instruction break #4. 1(R/W): Permit 0(R/W): Prohibit (default) If this bit is set to 1, the instruction fetch address and the value set in the Instruction Break Address Register 4 (0xffffd0) are compared. If they match, an instruction break is generated. If this bit is set to 0, no comparison is performed. D6 IBE3: Instruction Break #3 Enable Bit Permits or prohibits instruction break #3. 1(R/W): Permit 0(R/W): Prohibit (default) If this bit is set to 1, the instruction fetch address and the value set in the Instruction Break Address Register 3 (0xffffbc) are compared. If they match, an instruction break is generated. If this bit is set to 0, no comparison is performed. D5 IBE2: Instruction Break #2 Enable Bit Permits or prohibits instruction break #2. 1(R/W): Permit 0(R/W): Prohibit (default) If this bit is set to 1, the instruction fetch address and the value set in the Instruction Break Address Register 2 (0xffffb8) are compared. If they match, an instruction break is generated. If this bit is set to 0, no comparison is performed. D4 DR: Debug Request Flag Indicates the presence or absence of an external debug request. 1(R): Request generated 0(R): None (default) 1(W): Resets flag 0(W): Invalid This flag is cleared (reset to 0) when 1 is written. It must be cleared before the debug processing routine is terminated by the retd instruction. D3 IBE1: Instruction Break #1 Enable Bit Permits or prohibits instruction break #1. 1(R/W): Permit 0(R/W): Prohibit (default) If this bit is set to 1, the instruction fetch address and the value set in the Instruction Break Address Register 1 (0xffffb4) are compared. If they match, an instruction break is generated. If this bit is set to 0, no comparison is performed. 24-8 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 24 On-chip Debugger (DBG) D2 IBE0: Instruction Break #0 Enable Bit Permits or prohibits instruction break #0. 1(R/W): Permit 0(R/W): Prohibit (default) If this bit is set to 1, the instruction fetch address and the value set in the Instruction Break Address Register 0 (0xffffb0) are compared. If they match, an instruction break is generated. If this bit is set to 0, no comparison is performed. D1 SE: Single Step Enable Bit Permits or prohibits single-step operations. 1(R/W): Permit 0(R/W): Prohibit (default) D0 DM: Debug Mode Bit Indicates the processor operating mode (debug mode or user mode). 1(R): Debug mode 0(R): User mode (default) S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 24-9 24 On-chip Debugger (DBG) 0xffffb8: Instruction Break Address Register 2 (IBAR2) Register name Address Instruction Break Address Register 2 (IBAR2) Bit Name Function 0xffffb8 D31-24 - reserved (32 bits) D23-0 IBAR2[23:0] Instruction break address #2 IBAR223 = MSB IBAR20 = LSB Setting - 0x0 to 0xffffff Init. R/W Remarks - - 0 when being read. 0x0 R/W D[31:24] Reserved D[23:0] 24-10 IBAR2[23:0]: Instruction Break Address #2 Bits Sets instruction break address #2. (default: 0x000000) Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 24 On-chip Debugger (DBG) 0xffffbc: Instruction Break Address Register 3 (IBAR3) Register name Address Instruction Break Address Register 3 (IBAR3) Bit Name Function 0xffffbc D31-24 - reserved (32 bits) D23-0 IBAR3[23:0] Instruction break address #3 IBAR323 = MSB IBAR30 = LSB Setting - 0x0 to 0xffffff Init. R/W Remarks - - 0 when being read. 0x0 R/W D[31:24] Reserved D[23:0] IBAR3[23:0]: Instruction Break Address #3 Bits Sets instruction break address #3. (default: 0x000000) S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 24-11 24 On-chip Debugger (DBG) 0xffffd0: Instruction Break Address Register 4 (IBAR4) Register name Address Instruction Break Address Register 4 (IBAR4) Bit Name Function 0xffffd0 D31-24 - reserved (32 bits) D23-0 IBAR4[23:0] Instruction break address #4 IBAR423 = MSB IBAR40 = LSB Setting - 0x0 to 0xffffff Init. R/W Remarks - - 0 when being read. 0x0 R/W D[31:24] Reserved D[23:0] 24-12 IBAR4[23:0]: Instruction Break Address #4 Bits Sets instruction break address #4. (default: 0x000000) Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 25 Multiplier/Divider 25 Multiplier/Divider 25.1 Overview The S1C17003 incorporates a coprocessor that provides signed/unsigned 16 x 16 bit multiplication functions, 16 / 16 bit division functions, and signed 16 x 16 bit + 32-bit Product-sum calculation (MAC, Multiplyord Accumulator) functions enabling overflow detection. Use of these functions is discussed below. Argument 2 Argument 1 Arithmetic unit Mode setting Arithmetic result S1C17 core Arithmetic result register Selector Coprocessor output Flag output Figure 25.1.1: Multiplier/divider block diagram Table 25.1.1: Arithmetic cycles Operation Multiplication Product-sum calculation Division S1C17003 TECHNICAL MANUAL Cycles 1 cycle 1 cycle 17 to 20 cycles Seiko Epson Corporation 25-1 25 Multiplier/Divider 25.2 Operating Mode and Output Mode The multiplier/divider operates in accordance with the operating mode specified by the application program. The multiplier/divider supports six different operations, as shown in Table 25.2.1. The multiplication, division, and MAC arithmetic results are 32-bit data. This means the S1C17 core cannot read out results in a single access cycle. The output mode is provided to specify whether the first 16 bits or last 16 bits of the multiplier/divider arithmetic results are read out. Specify the operating and output modes by writing 7-bit data to the multiplier/divider internal mode setting register. Use the "ld.cw" instruction for writing. ld.cw ld.cw %rd,%rs %rd,imm7 %rs[6:0] is written to the mode setting register. (%rd: not used) imm7[6:0] is written to the mode setting register. (%rd: not used) 6 4 Output mode setting 3 0 Operating mode setting Figure 25.2.1: Mode setting registers Table 25.2.1: Mode setting Setting (D[6:4]) 0x0 Output mode Last 16-bit output mode Last 16 bits of the arithmetic results are read out as coprocessor output. 0x1 First 16-bit output mode First 16 bits of the arithmetic results are read out as coprocessor output. 0x2 to 0x7 Reserved Setting (D[3:0]) 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 0x9 0xa to 0xf 25-2 Seiko Epson Corporation Operating mode Initialization mode 0 Clears the arithmetic results register to 0x0. Initialization mode 1 Loads the 16-bit arithmetic augend into the last 16 bits of the arithmetic results register. Initialization mode 2 Loads the 32-bit arithmetic augend into the arithmetic results register. Arithmetic results reading mode Outputs the arithmetic results register data without performing calculations. Unsigned multiplication mode Performs unsigned multiplication. Signed multiplication mode Performs signed multiplication. Reserved Signed MAC mode Performs signed MAC multiplication. Unsigned division mode Performs unsigned division. Signed division mode Performs signed division. Reserved S1C17003 TECHNICAL MANUAL 25 Multiplier/Divider 25.3 Multiplication The multiplication function executes "A (32 bits) = B (16 bits) x C (16 bits)." To perform multiplication, set the operating mode to 0x4 (unsigned multiplication) or 0x5 (signed multiplication). Next, transfer the 16-bit multiplicand (B) and 16-bit multiplier (C) to the multiplier/divider using the "ld.ca" instruction. Half of the arithmetic result (16 bits, A [15:0] or A[31:16], depending on output mode) is returned to the CPU register, together with the flag status. The remaining half of the arithmetic result is read out by setting the multiplier/divider to arithmetic result reading mode. Argument 2 16 bits Argument 1 32 bits Arithmetic result S1C17 core Arithmetic result register Selector Coprocessor output (16 bits) Flag output Figure 25.3.1: Multiplier mode data paths Table 25.3.1: Multiplier mode operations Mode setting 0x04 or 0x05 0x14 or 0x15 Instruction Operation Flag res[31:0] %rd x %rs psr (CVZN) 0b0000 %rd res[15:0] (ext imm9) res[31:0] %rd x imm7/16 ld.ca %rd,imm7 %rd res[15:0] ld.ca %rd,%rs res[31:0] %rd x %rs %rd res[31:16] (ext imm9) res[31:0] %rd x imm7/16 ld.ca %rd,imm7 %rd res[31:16] ld.ca %rd,%rs Remarks The arithmetic result register retains arithmetic results until the results are overwritten by another operation. res: Arithmetic result register Examples: ld.cw ld.ca ld.cw ld.ca %r0,0x4 %r0,%r1 %r0,0x13 %r1,%r0 ; ; ; ; Mode setting (unsigned multiplication mode & last 16 bit output mode) Executes "res = %r0 x %r1" and loads the last 16 bits of the result to %r0 register. Mode setting (arithmetic result reading mode & first 16 bit output mode) Loads the first 16 bits of the result to %r1 register. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 25-3 25 Multiplier/Divider 25.4 Division The division function executes "A (16 bits) = B (16 bits) / C (16 bits), D (16 bits) = Remainder." To perform a division, set the operating mode to 0x8 (unsigned division) or 0x9 (signed division). Next, transfer the 16-bit dividend (B) and 16-bit divisor (C) to the multiplier/divider using the "1d.ca" instruction. The quotient will be placed in the lower 16 bits of the arithmetic result register, while the remainder is placed in the upper 16 bits. When the calculation is completed, the 16 bits corresponding to the quotient or remainder as specified in the output mode and the flag status are returned to the CPU register. The other 16 bits of the arithmetic result can be read out by setting the multiplier/divider to arithmetic result reading mode. Argument 2 16 bits Argument 1 / 16 bits Arithmetic result S1C17 core Arithmetic result register Selector Coprocessor output (16 bits) Flag output Figure 25.4.1 Division mode data path Table 25.4.1 Division mode operations Mode setting 0x08 or 0x09 0x18 or 0x19 Instruction Operation Flag res[31:0] %rd / %rs psr (CVZN) 0b0000 %rd res[15:0] (quotient) (ext imm9) res[31:0] %rd / imm7/16 ld.ca %rd,imm7 %rd res[15:0] (quotient) ld.ca %rd,%rs res[31:0] %rd / %rs %rd res[31:16] (remainder) (ext imm9) res[31:0] %rd / ld.ca %rd,imm7 imm7/16 %rd res[31:16] (remainder) ld.ca %rd,%rs Remarks The arithmetic result register retains the calculated result until it is overwritten by the result of another arithmetic operation. res: Arithmetic result register Example: ld.cw %r0,0x8 ld.ca %r0,%r1 ; Mode setting (unsigned division mode & lower 16-bit output mode) ; Executes "res = %r0 + %r1" and loads the lower 16 bits (quotient) of the result to the %r0 register. ld.cw %r0,0x13 ; Mode setting (arithmetic result reading mode & upper 16-bit output mode) ld.ca %r1,%r0 ; Loads the upper 16 bits (remainder) of the result to the %r1 register. 25-4 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 25 Multiplier/Divider 25.5 Product-sum Operation The Product-sum operation function executes "A (32 bits) = B (16 bits) x C (16 bits) + A (32 bits)." The initial value (A) must be set to the arithmetic result register before performing Product-sum operations. To clear the arithmetic result register (A = 0), set the operating mode to 0x0. There is no need to send 0x0 to the multiplier/divider using separate instructions. To load 16-bit or 32-bit values to the arithmetic result register, set the operating mode to 0x1 (16 bits) or 0x2 (32 bits). Next, transfer the initial value to the multiplier/divider using the "ld.cf" instruction. Argument 2 16 bits Argument 1 32 bits S1C17 core Arithmetic result register Selector Coprocessor output (16 bits) Flag output Figure 25.5.1: Initialization mode data paths Table 25.5.1: Arithmetic result register initialization Mode setting 0x0 0x1 0x2 Instruction - Operation res[31:0] 0x0 Remarks Initializes using operating mode settings only (no data transfer). res[31:16] 0x0 res[15:0] %rs (ext imm9) res[31:16] 0x0 ld.cf %rd,imm7 res[15:0] imm7/16 ld.cf %rd,%rs res[31:16] %rd res[15:0] %rs (ext imm9) res[31:16] %rd ld.cf %rd,imm7 res[15:0] imm7/16 ld.cf %rd,%rs res: Arithmetic result register To perform MAC operations, set the operating mode to 0x7 (signed MAC). Next, transfer the 16-bit multiplicand (B) and 16-bit multiplier (C) to the multiplier/divider using the "ld.ca" instruction. Half of the arithmetic result (16 bits, A [15:0] or A[31:16], depending on output mode) is returned to the CPU register together with the flag status. The remaining half of the arithmetic result is read out by setting the multiplier/divider to arithmetic result reading mode. The PSR overflow flag (V) is set to 1 by the arithmetic results. Other flags are cleared to 0. Transfer the required number of multiplicands and multipliers to continue MAC operations without switching to arithmetic result reading mode. In this case, there is no need to set to MAC mode each time data is sent. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 25-5 25 Multiplier/Divider Argument 2 32 bits 16 bits Argument 1 32 bits Arithmetic result S1C17 core Arithmetic result register Selector Coprocessor output (16 bits) Flag output Figure 25.5.2: MAC mode data paths Table 25.5.2: MAC mode operations Mode setting 0x07 0x17 Instruction Operation res[31:0] %rd x %rs + res[31:0] %rd res[15:0] (ext imm9) res[31:0] %rd x imm7/16 + res[31:0] ld.ca %rd,imm7 %rd res[15:0] ld.ca %rd,%rs res[31:0] %rd x %rs + res[31:0] %rd res[31:16] (ext imm9) res[31:0] %rd x imm7/16 + res[31:0] ld.ca %rd,imm7 %rd res[31:16] ld.ca %rd,%rs Flag Remarks If overflow occurs The arithmetic result psr (CVZN) 0b0100 register retains arithmetic results until the results Other cases psr (CVZN) 0b0000 are overwritten by another operation. res: Arithmetic result register Examples: ld.cw ld.ca ld.cw ld.ca %r0,0x7 ; %r0,%r1 ; %r0,0x13 ; %r1,%r0 ; Mode setting (signed MAC mode & last 16 bit output mode) Executes "res = %r0 x %r1 + res" and loads the last 16 bits of the result to %r0 register. Mode setting (arithmetic result reading mode & first 16 bit output mode) Loads first 16 bits of the result to %r1 register. Overflow flag (V) setting conditions If the multiplication result sign, arithmetic result register sign, and arithmetic result sign satisfy the following conditions in MAC operations, an overflow occurs, and the overflow flag (V) is set to 1. Table 25.5.3: Overflow flag (V) setting conditions Mode setting 0x07 0x07 Multiplication result sign 0 (Positive) 1 (Negative) Arithmetic result register sign 0 (Positive) 1 (Negative) Arithmetic result sign 1 (Negative) 0 (Positive) An overflow occurs if positive values are summed giving a negative result in MAC operations or if negative values are summed giving a positive result. The result is retained in the coprocessor until the overflow flag (V) is cleared. Overflow flag (V) clear conditions The overflow flag (V) set is cleared if the "ld.ca" instruction is executed for MAC operation without causing an overflow or if the "ld.ca" or "ld.cf" instruction is executed in other than arithmetic result reading mode. 25-6 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 25 Multiplier/Divider 25.6 Arithmetic Results Reading Since the "ld.ca" instruction cannot load 32-bit arithmetic results to the CPU register, multiplication and Product -sum operation return half of the arithmetic result (16 bits, A[15:0] or A[31:16], depending on output mode) together with the flag status to the CPU register. The remaining half of the arithmetic result is read by setting the multiplier to arithmetic result reading mode. The arithmetic result register retains arithmetic results until the results are overwritten by another operation. Argument 2 Argument 1 S1C17 core Arithmetic result register Selector Coprocessor output (16 bits) Flag output Figure 25.6.1: Arithmetic result reading mode data paths Table 25.6.1: Arithmetic result reading mode operations Mode setting 0x03 0x13 Instruction ld.ca ld.ca ld.ca ld.ca %rd,%rs %rd,imm7 %rd,%rs %rd,imm7 Operation %rd res[15:0] %rd res[15:0] %rd res[31:16] %rd res[31:16] Flag Remarks psr (CVZN) 0b0000 This operating mode does not affect the arithmetic result register. res: Arithmetic result register S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 25-7 26 Electrical Characteristics 26 Electrical Characteristics 26.1 Absolute Maximum Ratings Item Core power supply voltage I/O power supply voltage Analog power supply voltage Input voltage Analog input voltage Output voltage High-level output current Low-level output current Storage temperature Soldering temperature/time Code Condition LVDD HVDD AVDD HVI LVI AVI VO 1 pin IOH Total for all pins 1 pin IOL Total for all pins Tstg Tsol Rating -0.3 to 2.5 -0.3 to 4.0 -0.3 to 4.0 -0.3 to HVDD + 0.5 -0.3 to LVDD + 0.5 -0.3 to AVDD + 0.3 -0.3 to HVDD + 0.5 -10 -40 -10 -40 -65 to 150 260C, 10 s (leads) Units V V V V V V mA mA mA mA C - 26.2 Recommended Operating Conditions Item Code Condition Core power supply voltage LVDD I/O power supply voltage HVDD Analog power supply voltage*1 AVDD P17, P[22:20]=When analog signal input P17, P[22:20]=When digital signal input Input voltage HVI LVI Analog input voltage AVI Operating frequency fosc3 Crystal/ceramic oscillation fosc1 Crystal oscillation Operating temperature Ta Input rise time (Schmitt input) tri Input fall time (Schmitt input) tfi Min. 1.65 1.65 2.7 1.65 VSS VSS VSS 5 - -40 - - Typ. - - - - - - - - 32.768 - - - Max. 1.95 3.6 3.6 3.6 HVDD LVDD AVDD 20 - 85 5 5 Units V V V V V V V MHz kHz C ms ms 1) The AVDD voltage range can be extended into 1.65 to 3.60 V only when the ADC is not used and the P17, P[22:20] are used as digital signal input pins, not analog input pins. However, the high and low level input voltages of the digital signals must be AVDD and GND, respectively. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 26-1 26 Electrical Characteristics 26.3 Current Consumption Unless otherwise stated: LVDD = HVDD = 1.8V, AVDD = 3.3V, VSS = 0V, Ta = 25C, Peripheral modules: stopped Item SLEEP current consumption HALT current consumption Execution current *1 consumption ADC operating *2 current consumption Code Condition ISLP OSC1: Off, OSC3: Off IHALT1 IHALT2 IHALT3 IHALT4 IHALT5 IEXE1 IEXE2 IEXE3 IEXE4 IEXE5 IADC OSC1: 32kHz, OSC3: Off OSC1: 32kHz, OSC3: 1MHz OSC1: 32kHz, OSC3: 4MHz OSC1: 32kHz, OSC3: 8MHz OSC1: 32kHz, OSC3: 20MHz OSC1: 32kHz, OSC3: Off OSC1: 32kHz, OSC3: 1MHz OSC1: 32kHz, OSC3: 4MHz OSC1: 32kHz, OSC3: 8MHz OSC1: 32kHz, OSC3: 20MHz ADC enable Min. - Typ. 1 Max. - Units A - - - - - - - - - - - 3.3 180 300 500 1.3 8.0 350 840 1.6 4.0 260 - - - - - - - - - - - A A A A mA A A A mA mA A *1: Execution current consumption is the value for continuous operations while fetching the test program (ALU instruction 60.5%, branch instruction 17%, memory read 12%, memory write 10.5%) from flash memory. *2: Current consumption at AVDD 26-2 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 26 Electrical Characteristics 26.4 Input/Output Terminal Characteristics Unless otherwise stated: LVDD = HVDD = 1.8V0.15V, VSS = 0V, Ta = -40 to 85C Item Input leakage current High level output current Low level output current Positive trigger input voltage Negative trigger input voltage Hysteresis voltage Input pull-up resistance Input pin capacitance Output pin capacitance I/O pin capacitance Code Condition ILI HVDD=Max, VI=Max. IOH VOH = HVDD-0.4V HVDD = Min. IOL VOL = 0.4V HVDD = Min. VT1+ HVDD=Max. VT1HVDD=Min. DV HVDD=Min. RIN1 Pxx, VI=0V RIN2 #RESET, VI=0V CI f = 1MHz, HVDD = 0V CO f = 1MHz, HVDD = 0V CIO f = 1MHz, HVDD = 0V Min. -5 -1 Typ. - - Max. 5 - Units A mA 1 - - mA 0.6 0.3 0.02 48 - - - 120 1.4 1.1 - 300 V V V kW 96 240 600 kW - - - - - - 8 8 8 pF pF pF Min. -5 - 1.7 Typ. - - Max. 5 - Units V mA 1.7 - - mA 1.2 0.5 0.2 25 - - - 50 2.7 1.8 - 144 V V V kW 50 100 288 kW - - - - - - 8 8 8 pF pF pF Unless otherwise stated: LVDD = 1.8V0.15V, HVDD = 2.7 to 3.6V, VSS = 0V, Ta = -40 to 85C Item Input leakage current High level output current Low level output current Positive trigger input voltage Negative trigger input voltage Hysteresis voltage Input pull-up resistance Input pin capacitance Output pin capacitance I/O pin capacitance S1C17003 TECHNICAL MANUAL Code Condition ILI HVDD=Max, VI=Max. IOH VOH=HVDD-0.4V, HVDD=Min. IOL VOL=0.4V, HVDD=Min. VT1+ HVDD=Max. VT1HVDD=Min. V HVDD=Min. RIN1 Pxx, VI=0V RIN2 #RESET, VI=0V CI f = 1MHz, HVDD = 0V CO f = 1MHz, HVDD = 0V CIO f = 1MHz, HVDD = 0V Seiko Epson Corporation 26-3 26 Electrical Characteristics 26.5 A/D Converter Characteristics Unless otherwise stated: HVDD = AVDD = 2.7 to 3.6V, LVDD = 1.65 to 1.95V, VSS = 0V, Ta = -40 to 85C Item Resolution Conversion time *1 Zero scale error Full scale error Integral linearity error Differential linearity error Permissible signal source impedance Analog input capacitance Code - - EZS EFS EL ED - - Condition Min. - 10 -2 -2 -3 -3 - - Typ. 10 - - - - - - - Max. - 1250 2 2 3 3 5 45 Units bit s LSB LSB LSB LSB kW pF 1) Indicates the minimum value when A/D clock = 2MHz. Indicates the maximum value when A/D clock = 16kHz. A/D conversion error V[001]h V'[001]h V[3FF]h V'[3FF]h = Ideal voltage at zero-scale point (=0.5LSB) = Actual voltage at zero-scale point = Ideal voltage at full-scale point (=1022.5LSB) = Actual voltage at full-scale point AVDD - VSS 210 - 1 V'[3FF]h - V'[001]h 1LSB' = 210 - 2 1LSB = Zero scale error Digital output (hex) 004 Ideal conversion characteristic 003 002 V[001]h (=0.5LSB) Actual conversion characteristic Zero scale error EZS = 001 (V'[001]h - 0.5LSB') - (V[001]h - 0.5LSB) [LSB] 1LSB V'[001]h 000 VSS Analog input Full scale error Digital output (hex) 3FF V[3FF]h (=1022.5LSB) V'[3FF]h 3FE Full scale error EFS = 3FD 3FC 3FB (V'[3FF]h + 0.5LSB') - (V[3FF]h + 0.5LSB) [LSB] 1LSB Actual conversion characteristic Ideal conversion characteristic AVDD Analog input Integral linearity error 3FF Digital output (hex) 3FE V'[3FF]h 3FD Integral linearity error EL = VN 003 VN ' VN' - VN [LSB] 1LSB' Actual conversion characteristic 002 Ideal conversion characteristic 001 000 VSS V'[001]h Analog input AVDD Differential linearity error Digital output (hex) N+1 Ideal conversion characteristic N Actual conversion characteristic N-1 N-2 V'[N]h Differential linearity error ED = V'[N-1]h V'[N]h - V'[N-1]h - 1 [LSB] 1LSB' Analog input 26-4 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 26 Electrical Characteristics 26.6 SPI Characteristics Master mode Unless otherwise stated: HVDD = 1.65 to 3.6V, LVDD = 1.65 to 1.95V, VSS = 0V, Ta = -40 to 85C Item SPICLK cycle time SDI setup time SDI hold time SDO output delay time Code tSPCK tSDS tSDH tSDO Min. 200 60 10 - Typ. - - - - Max. - - - 20 Units ns ns ns ns Max. - - - 60 Units ns ns ns ns Slave mode Unless otherwise stated: HVDD = 1.65 to 3.6V, LVDD = 1.65 to 1.95V, VSS = 0V, Ta = -40 to 85C Item SPICLK cycle time SDI setup time SDI hold time SDO output delay time Code tSPCK tSDS tSDH tSDO Min. 200 10 10 - Typ. - - - - 26.7 I2C Characteristics tSCL SCL SDA tSTH tSDD Figure 26.7.1: tSPH I2C Timing Unless otherwise stated: VDD = 1.8 to 3.6V, VSS = 0V, Ta = -25 to 70C Item SCL cycle time Start condition hold time Data output delay time Stop condition hold time Code tSCL tSTH tSDD tSPH Min. 2500 1/fSYS 1/fSYS 1/fSYS Typ. Max. Units ns ns ns ns * fSYS: System operation clock frequency S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 26-5 26 Electrical Characteristics 26.8 Oscillation Circuit Characteristics Oscillation characteristics change depending on conditions such as components used (resonator, Rf, Rd, CG, CD) and board pattern. Use the following characteristics as reference values. In particular, when a ceramic or crystal resonator is used, evaluate the components adequately under real operating conditions by mounting them on the board before the external register (Rf, Rd) and capacitor (CG, CD) values are finally decided. OSC1 crystal oscillator Unless otherwise stated: LVDD = 1.8V, VSS = 0V, Ta = 25C Item Oscillation start time Code Condition tSTA1 When the recommended parts shown in Section "27. Basic External Wiring Diagram" are used Min. Typ. Max. 1 Units s OSC3 crystal oscillator Note: A "crystal resonator that uses a fundamental" should be used for the OSC3 crystal oscillation circuit. Unless otherwise stated: LVDD = 1.8V, VSS = 0V, Ta = 25C Item Oscillation start time Code Condition tSTA3 When the recommended parts shown in Section "27. Basic External Wiring Diagram" are used Min. Typ. Max. 10 Units ms Min. Typ. Max. 1 Units ms OSC3 ceramic oscillator Unless otherwise stated: LVDD = 1.8V, VSS = 0V, Ta = 25C Item Oscillation start time Code Condition tSTA3 When the recommended parts shown in Section "27. Basic External Wiring Diagram" are used 26.9 External Clock Input Characteristics tC1/tC3 tC1H/tC3H tC1ED = tC1H/tC1 tC3ED = tC3H/tC3 OSC1/OSC3 tIF tIR OSC1 external clock Unless otherwise specified: HVDD = AVDD = 2.7 to 3.6V, LVDD = 1.65 to 1.95V, VSS = 0V, Ta = -40 to 85C Item OSC1 external clock cycle time OSC1 external clock input duty OSC1 external clock input rise time OSC1 external clock input fall time Symbol tC1 tC1ED tIF tIR Min. Typ. Max. Unit 55 5 5 s % ns ns 30.51 45 OSC3 external clock Unless otherwise specified: HVDD = AVDD = 2.7 to 3.6V, LVDD = 1.65 to 1.95V, VSS = 0V, Ta = -40 to 85C Item OSC3 external clock cycle time OSC3 external clock input duty OSC3 external clock input rise time OSC3 external clock input fall time 26-6 Symbol tC3 tC3ED tIF tIR Min. 50 45 Seiko Epson Corporation Typ. Max. Unit 1000 55 5 5 ns % ns ns S1C17003 TECHNICAL MANUAL 27 Basic External Connection Diagram 27 Basic External Connection Diagram 2.7 to 3.6V + AVDD CP 1.65 to 1.95V P17(AIN3) P20(AIN2) P21(AIN1) P22(AIN0) LVDD + CP 1.65 to 3.6V + HVDD CP Rres #RESET Cres CG1 OSC1 Rf1 X'tal1 CD1 OSC2 Rd1 CG2 OSC4 X'tal2/ Ceramic CD2 Rf2 Rd2 OSC3 TEST P00(REMO) P01(REMI) P02(EXCL0) P03(#ADTRG) P04(SPICLK) P05(SDO) P06(SDI) P07(#SPISS) P10(SCLK0) P11(SOUT0) P12(SIN0) P13(EXCL1) [Circuit board potential (chip underside) is VSS.] P14(EXCL2) P15(EXCL3) P16(SCLK1) P23 P24 P27(SOUT1) P30(SIN1) P31(SCL0) P32(SDA0) P33(SCL1/SCL0) P34(SDA1/SDA0) P35(FOUT1/#BFR) P36(TOUT3) P37(TOUTN3) P40(FOUTH) INPUT or AIN (When used for general-purpose input, signals must be input with AVDD voltage set to High.) I/O S1C17003 HVDD DSIO(P41) DST2(P42) DCLK(P43) VSS R3 ICD or I/O Recommended values for external parts External parts for the OSC1 oscillator circuit Frequency Symbol Resonator Recommended manufacturer [Hz] X'tal1 Crystal Epson Toyocom Corporation 32.768k Recommended Recommended values operating condition Product number CD1 CG1 Rf1 Rd1 Temperature range [pF] [pF] [W] [W] [C] 7 1M 0 -40 to 85 MC-146 (CL = 7.0 pF) 7 External parts for the OSC3 oscillator circuit Symbol Resonator Recommended manufacturer X'tal2 Crystal Ceramic Ceramic Epson Toyocom Corporation Frequency [Hz] 4M 8M Murata Manufacturing Co., Ltd. 16M 20M 4M 8M 12M 16M 20M 4M 8M 12M 16M 20M Recommended Recommended values operating condition CD2 CG2 Rf2 Rd2 Temperature range [pF] [pF] [W] [W] [C] -40 to 85 MA-406 (CL = 16 pF) 27 27 1M 0 -40 to 85 MA-406 (CL = 7.0 pF) 18 18 1M 0 Product number FA-238 (CL = 7.0 pF) FA-238 (CL = 7.0 pF) CSTCR4M00G55 CSTCE8M00G55 CSTCE12M0G55 CSTCE16M0V53 CSTCE20M0V53 CSTCR4M00G55Z CSTCE8M00G55Z CSTCE12M0G55Z CSTCE16M0V53Z CSTCE20M0V53Z 4 4 (39) (33) (33) (15) (15) (39) (33) (33) (15) (15) 4 4 (39) (33) (33) (15) (15) (39) (33) (33) (15) (15) 1M 0 1M 0 1M 100 1M 0 1M 0 1M 0 1M 0 1M 100 1M 0 1M 0 1M 0 1M 0 -40 to 85 -40 to 85 -20 to 80 -20 to 80 -20 to 80 -20 to 80 -20 to 80 -40 to 85 -40 to 85 -40 to 85 -40 to 85 -40 to 85 The CD2 and CG2 values enclosed with ( ) are the built-in capacitances of the resonator. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 27-1 27 Basic External Connection Diagram Other Symbol Name CP Capacitor for power supply Cres Capacitor for #RESET pin Rres Resistor for #RESET pin Recommended value 3.3 F 0.47 F 10 kW Notes: * The values in the above table are shown only for reference and not guaranteed. * Crystal and ceramic resonators are extremely sensitive to influence of external components and printed-circuit boards. Before using a resonator, please contact the manufacturer for further information on conditions of use. 27-2 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 28 Package 28 Package 28.1 TQFP12-64 pin package (Units: mm) 9 7 48 33 49 9 7 32 INDEX 64 17 0.4 0.13-0.23 16 1 0.09-0.2 0 10 0.10.05 1.2max. 1 0.3-0.75 1 Figure 28.1.1 TQFP12-64pin package scale S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 28-1 28 Package 28.2 WCSP-48 package Top View D A1 Corner E Index Bottom View e1 A b x ZD M A1 A 2 y S G Symbol F E e2 D C B ZE A A1 Corner 1 2 3 4 5 6 D E A A1 A2 e1 e2 b X y ZD ZE Dimension in Millimeters Min Nom Max 3.024 3.124 3.224 3.024 3.124 3.224 - - 0.78 - 0.23 - - 0.49 - - 0.40 - - 0.40 - 0.23 0.26 0.29 - - 0.08 - - 0.05 - 0.362 - - 0.362 - 7 Figure 28.2.1 WCSP-48 package scale 28-2 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL 28 Package 28.3 Thermal Resistance of the Package The chip temperature of LSI devices tends to increase with the power consumed on the chip. The chip temperature when encapsulated in a package is calculated from its ambient temperature (Ta), the thermal resistance of the package (), and power dissipation (PD). Chip temperature (Tj) = Ta + (PD x ) [C] When used under normal operating conditions, make sure that the chip temperature (Tj) is 125C or less. 1. When mounted on a board (windless condition) Thermal resistance (j-a) = 33.3C/W This value indicates the thermal resistance of the package when measured under a windless condition, with the sample mounted on a measurement board (size: 114 x 76 x 1.6 mm thick, FR4/4 layered board). 2. When suspended alone (windless condition) Thermal resistance = 90-100C/W This value indicates the thermal resistance of the package when measured under a windless condition, with the sample suspended alone. Note: The thermal resistance of the package varies significantly depending on how it is mounted on the board and whether forcibly air-cooled. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation 28-3 28 Package 28.4 Pad Layout 28.4.1 Diagram of Pad Layout 66 60 55 50 45 67 89 44 70 40 35 (0, 0) X 80 3.124mm Y 75 30 85 25 88 23 1 5 10 15 20 22 90 3.124mm Chip thickness: 400 m 28-4 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL Appendix A: I/O Register List Appendix A: I/O Register List Peripheral circuit Prescaler (8-bit device) UART (with IrDA) Ch.0 (8-bit device) UART (with IrDA) Ch.1 (8-bit device) 8-bit timer (with F mode) Ch.0 (16-bit device) 16-bit timer Ch.0 (16-bit device) 16-bit timer Ch.1 (16-bit device) 16-bit timer Ch.2 (16-bit device) 8-bit timer (with F mode) Ch.1 (16-bit device) Interrupt controller (16-bit device) Address Register name 0x4020 0x4021~0x403f 0x4100 0x4101 0x4102 0x4103 0x4104 0x4105 0x4106~0x411f 0x4120 0x4121 0x4122 0x4123 0x4124 0x4125 0x4126~0x413f 0x4200 0x4202 0x4204 0x4206 0x4208 0x420a~0x421f 0x4220 0x4222 0x4224 0x4226 0x4228 0x422a~0x423f 0x4240 0x4242 0x4244 0x4246 0x4248 0x424a~0x425f 0x4260 0x4262 0x4264 0x4266 0x4268 0x426a~0x427f 0x4280 0x4282 0x4284 0x4286 0x4288 0x428a~0x429f 0x4300~0x4304 0x4306 0x4308 0x430a 0x430c 0x430e PSC_CTL - UART_ST0 UART_TXD0 UART_RXD0 UART_MOD0 UART_CTL0 UART_EXP0 - UART_ST1 UART_TXD1 UART_RXD1 UART_MOD1 UART_CTL1 UART_EXP1 - T8F_CLK0 T8F_TR0 T8F_TC0 T8F_CTL0 T8F_INT0 - T16_CLK0 T16_TR0 T16_TC0 T16_CTL0 T16_INT0 - T16_CLK1 T16_TR1 T16_TC1 T16_CTL1 T16_INT1 - T16_CLK2 T16_TR2 T16_TC2 T16_CTL2 T16_INT2 - T8F_CLK1 T8F_TR1 T8F_TC1 T8F_CTL1 T8F_INT1 - - ITC_LV0 ITC_LV1 ITC_LV2 ITC_LV3 ITC_LV4 Prescaler Control Register - UART Ch.0 Status Register UART Ch.0 Transmit Data Register UART Ch.0 Receive Data Register UART Ch.0 Mode Register UART Ch.0 Control Register UART Ch.0 Expansion Register - UART Ch.1 Status Register UART Ch.1 Transmit Data Register UART Ch.1 Receive Data Register UART Ch.1 Mode Register UART Ch.1 Control Register UART Ch.1 Expansion Register - 8-bit Timer Ch.0 Input Clock Select Register 8-bit Timer Ch.0 Reload Data Register 8-bit Timer Ch.0 Counter Data Register 8-bit Timer Ch.0 Control Register 8-bit Timer Ch.0 Interrupt Control Register - 16-bit Timer Ch.0 Input Clock Select Register 16-bit Timer Ch.0 Reload Data Register 16-bit Timer Ch.0 Counter Data Register 16-bit Timer Ch.0 Control Register 16-bit Timer Ch.0 Interrupt Control Register - 16-bit Timer Ch.1 Input Clock Select Register 16-bit Timer Ch.1 Reload Data Register 16-bit Timer Ch.1 Counter Data Register 16-bit Timer Ch.1 Control Register 16-bit Timer Ch.1 Interrupt Control Register - 16-bit Timer Ch.2 Input Clock Select Register 16-bit Timer Ch.2 Reload Data Register 16-bit Timer Ch.2 Counter Data Register 16-bit Timer Ch.2 Control Register 16-bit Timer Ch.2 Interrupt Control Register - 8-bit Timer Ch.1 Input Clock Select Register 8-bit Timer Ch.1 Reload Data Register 8-bit Timer Ch.1 Counter Data Register 8-bit Timer Ch.1 Control Register 8-bit Timer Ch.1 Interrupt Control Register - - Interrupt Level Setup Register 0 Interrupt Level Setup Register 1 Interrupt Level Setup Register 2 Interrupt Level Setup Register 3 Interrupt Level Setup Register 4 0x4310 0x4312 ITC_LV5 ITC_LV6 Interrupt Level Setup Register 5 Interrupt Level Setup Register 6 0x4314 0x4316 0x4318 0x431a~0x431f ITC_LV7 ITC_LV8 ITC_LV9 - Interrupt Level Setup Register 7 Interrupt Level Setup Register 8 Interrupt Level Setup Register 9 - S1C17003 TECHNICAL MANUAL Seiko Epson Corporation Function Prescaler start/stop control Reserved Transfer, buffer, error status display Transmission data Receiving data Transfer data format setting Data transfer control IrDA mode setting Reserved Transfer, buffer, error status display Transmission data Receiving data Transfer data format setting Data transfer control IrDA mode setting Reserved Prescaler output clock selection Reload data setting Counter data Timer mode setting and timer RUN/STOP Interrupt control Reserved Prescaler output clock selection Reload data setting Counter data Timer mode setting and timer RUN/STOP Interrupt control Reserved Prescaler output clock selection Reload data setting Counter data Timer mode setting and timer RUN/STOP Interrupt control Reserved Prescaler output clock selection Reload data setting Counter data Timer mode setting and timer RUN/STOP Interrupt control Reserved Prescaler output clock selection Reload data setting Counter data Timer mode setting and timer RUN/STOP Interrupt control Reserved Reserved P0/P1 interrupt level setting SWT/CT interrupt level setting T8OSC1 interrupt level setting T16E Ch.0 interrupt level setting T8F Ch.0/Ch.1, T16 Ch.0 interrupt level setting T16 Ch.1/Ch.2 interrupt level setting UART Ch.0, I2C/UART Ch.1 slave interrupt level setting SPI/I2C master interrupt level setting REMC interrupt level setting ADC10SA interrupt setting Reserved AP-1 Appendix A: I/O Register List Peripheral circuit SPI (16-bit device) Address 0x4320 0x4322 0x4324 0x4326 0x4328~0x433f I2C (master) 0x4340 (16-bit device) 0x4342 0x4344 0x4346 0x4348~0x435f I2C (salave) 0x4360 (16-bit device) 0x4362 0x4364 0x4366 0x4368 0x436a 0x436c 0x4370~0x437f Clock timer 0x5000 (8-bit device) 0x5001 0x5002 0x5003 0x5004~0x501f Stopwatch timer 0x5020 (8-bit device) 0x5021 0x5022 0x5023 0x5024~0x503f Watchdog timer 0x5040 (8-bit device) 0x5041 0x5042~0x505f Oscillator circuit 0x5060 (8-bit device) 0x5061 0x5062 0x5063 0x5064 0x5065 0x5066~0x507f Clock generator 0x5080 (8-bit device) 0x5081 0x5082~0x509f 8-bit OSC1 timer 0x50c0 (8-bit device) 0x50c1 0x50c2 0x50c3 0x50c4 0x50c5 0x50c6~0x50df AP-2 Register name SPI_ST SPI_TXD SPI_RXD SPI_CTL - I2C_EN I2C_CTL I2C_DAT I2C_ICTL - I2CS_TRNS I2CS_RECV I2CS_SADRS I2CS_CTL I2CS_STAT I2CS_ASTAT I2CS_ICTL - CT_CTL CT_CNT CT_IMSK CT_IFLG - SWT_CTL SWT_BCNT SWT_IMSK SWT_IFLG - WDT_CTL WDT_ST - OSC_SRC OSC_CTL OSC_NFEN - OSC_FOUT OSC_T8OSC1 - CLG_PCLK CLG_CCLK - T8OSC1_CTL T8OSC1_CNT T8OSC1_CMP T8OSC1_IMSK T8OSC1_IFLG T8OSC1_DUTY - SPI Status Register SPI Transmit Data Register SPI Receive Data Register SPI Control Register - I2C Enable Register I2C Control Register I2C Data Register I2C Interrupt Control Register - I2C Slave Transfer Data Write Register I2C Slave Receive Data Read Register I2C Slave Address Set Register I2C Slave Control Register I2C Slave Status Register I2C Slave Access Status Register I2C Slave Interrupt Control Register - Clock Timer Control Register Clock Timer Counter Register Clock Timer Interrupt Mask Register Clock Timer Interrupt Flag Register - Stopwatch Timer Control Register Stopwatch Timer BCD Counter Register Stopwatch Timer Interrupt Mask Register Stopwatch Timer Interrupt Flag Register - Watchdog Timer Control Register Watchdog Timer Status Register - Clock Source Select Register Oscillation Control Register Noise Filter Enable Register - FOUT Control Register T8OSC1 Clock Control Register - PCLK Control Register CCLK Control Register - 8-bit OSC1 Timer Control Register 8-bit OSC1 Timer Counter Data Register 8-bit OSC1 Timer Compare Data Register 8-bit OSC1 Timer Interrupt Mask Register 8-bit OSC1 Timer Interrupt Flag Register 8-bit OSC1 Timer PWM Data Register - Seiko Epson Corporation Function Transfer and buffer status display Transmission data Receiving data SPI mode and data transfer permission setting Reserved I2C module enable I2C control and transfer status display Transfer data I2C interrupt control Reserved Transmission data Receiving data Slave address data I2C slave control I2C slave status display I2C slave transfer status display I2C slave interrupt control Reserved Timer reset and RUN/STOP control Counter data Interrupt mask setting Interrupt occurrence status display/reset Reserved Timer reset and RUN/STOP control BCD counter data Interrupt mask setting Interrupt occurrence status display/reset Reserved Timer reset and RUN/STOP control Timer mode setting and NMI status display Reserved Clock source selection Oscillation control Noise filter ON/OFF Reserved Clock external output control 8-bit OSC1 timer clock setting Reserved PCLK feed control CCLK division ratio setting Reserved Timer mode setting and timer RUN/STOP Counter data Compare data setting Interrupt mask setting Interrupt occurrence status display/reset PWM output data setting Reserved S1C17003 TECHNICAL MANUAL Appendix A: I/O Register List Peripheral circuit Address P port & port MUX 0x5200 (8-bit device) 0x5201 0x5202 0x5203 0x5204 0x5205 0x5206 0x5207 0x5208 0x5209 0x520a 0x520b~0x520f 0x5210 0x5211 0x5212 0x5213 0x5214 0x5215 0x5216 0x5217 0x5218 0x5219 0x521a 0x521b~0x521f 0x5220 0x5221 0x5222 0x5223 0x5224~0x5229 0x522a 0x522b~0x522f 0x5230 0x5231 0x5232 0x5233 0x5234~0x5239 0x523a 0x523b~0x523f 0x5240 0x5241 0x5242 0x5243 0x5244~0x5249 0x524a 0x524b~0x527f 0x52a0~0x52a1 0x52a2~0x52a3 0x52a4~0x52a5 0x52a6~0x52a7 0x52a8 0x52a9~0x52bf PWM timer Ch.0 0x5300 (16-bit device) 0x5302 0x5304 0x5306 0x5308 0x530a 0x530c 0x530e~0x531f MISC register 0x5320 (16-bit device) 0x5322 0x5324 0x5326 0x5328 0x532a 0x532c 0x532e~0x533f Register name P0_IN P0_OUT P0_OEN P0_PU - P0_IMSK P0_EDGE P0_IFLG P0_CHAT P0_KRST P0_IEN - P1_IN P1_OUT P1_OEN P1_PU - P1_IMSK P1_EDGE P1_IFLG P1_CHAT - P1_IEN - P2_IN P2_OUT P2_OEN P2_PU - P2_IEN - P3_IN P3_OUT P3_OEN P3_PU - P3_IEN - P4_IN P4_OUT P4_OEN P4_PU - P4_IEN - P0_PMUX P1_PMUX P2_PMUX P3_PMUX P4_PMUX - T16E_CA T16E_CB T16E_TC T16E_CTL T16E_CLK T16E_IMSK T16E_IFLG - MISC_FL MISC_OSC1 P0 Port Input Data Register P0 Port Output Data Register P0 Port Output Enable Register P0 Port Pull-up Control Register - P0 Port Interrupt Mask Register P0 Port Interrupt Edge Select Register P0 Port Interrupt Flag Register P0 Port Chattering Filter Control Register P0 Port Key-Entry Reset Configuration Register P0 Port Input Enable Register - P1 Port Input Data Register P1 Port Output Data Register P1 Port Output Enable Register P1 Port Pull-up Control Register - P1 Port Interrupt Mask Register P1 Port Interrupt Edge Select Register P1 Port Interrupt Flag Register P1 Port Chattering Filter Control Register - P1 Port Input Enable Register - P2 Port Input Data Register P2 Port Output Data Register P2 Port Output Enable Register P2 Port Pull-up Control Register - P2 Port Input Enable Register - P3 Port Input Data Register P3 Port Output Data Register P3 Port Output Enable Register P3 Port Pull-up Control Register - P3 Port Input Enable Register - P4 Port Input Data Register P4 Port Output Data Register P4 Port Output Enable Register P4 Port Pull-up Control Register - P4 Port Input Enable Register - P0 Port Function Select Register P1 Port Function Select Register P2 Port Function Select Register P3 Port Function Select Register P4 Port Function Select Register - PWM Timer Compare Data A Register PWM Timer Compare Data B Register PWM Timer Counter Data Register PWM Timer Control Register PWM Timer Input Clock Select Register PWM Timer Interrupt MASK Register PWM Timer Interrupt Flag Register - FLASHC/SRAMC Control Register OSC1 Peripheral Control Register MISC_PROT MISC_IRAMSZ MISC_TTBRL MISC_TTBRH MISC_PSR - MISC Protect Register IRAM Size Select Register Vactor Table Address Low Register Vector Table Address High Register PSR Register - S1C17003 TECHNICAL MANUAL Seiko Epson Corporation Function P0 port input data P0 port output data P0 port output enable P0 port pull-up control Reserved P0 port interrupt mask setting P0 port interrupt edge selection P0 port interrupt occurrence status display/reset P0 port chattering filter control P0 port key entry reset setting P0 port input enable Reserved P1 port input data P1 port output data P1 port output enable P1 port pull-up control Reserved P1 port interrupt mask setting P1 port interrupt edge selection P1 port interrupt occurrence status display/reset P1 port chattering filter control Reserved P1 port input enable Reserved P2 port input data P2 port output data P2 port output enable P2 port pull-up control Reserved P2 port input enable Reserved P3 port input data P3 port output data P3 port output enable P3 port pull-up control Reserved P3 port input enable Reserved P4 port input data P4 port output data P4 port output enable P4 port pull-up control Reserved P4 port input enable Reserved P0 port function selection P1 port function selection P2 port function selection P3 port function selection P4 port function selection Reserved Compare data A setting Compare data B setting Counter data Timer mode setting and timer RUN/STOP Prescaler output clock selection Interrupt factor mask selection Interrupt factor checking Reserved FLASHC/SRAMC access condition setting OSC1 operation peripheral function setting for debugging MISC register write protection IRAM size selection Vector table address setting Vector table address setting PSR status reading Reserved AP-3 Appendix A: I/O Register List Peripheral circuit Address Remote controller 0x5340 (16-bit device) 0x5342 0x5344 0x5346 0x5348~0x535f A/D converter 0x5380 (16-bit device) 0x5382 0x5384 0x5386 0x5388~0x539f S1C17 core I/O 0xffff84 0xffff90 0xffffa0 0xffffb8 0xffffbc 0xffffd0 Register name REMC_CFG REMC_CAR REMC_LCNT REMC_INT - ADC10_ADD ADC10_TRG ADC10_CTL ADC10_DIV - IDIR DBRAM DCR IBAR2 IBAR3 IBAR4 REMC Configuration Register REMC Carrier Length Setup Register REMC Length Counter Register REMC Interrupt Control Register - ADC10 Conversion Result Register ADC10 Trigger/Channel Select Register ADC10 Control/Status Register ADC10 divided frequency Register - Processor ID Register Debug RAM Base Register Debug Control Register Instruction Break Address Register 2 Instruction Break Address Register 3 Instruction Break Address Register 4 Function Clock transfer control Carrier H/L section length setting Transfer bit and transfer data length setting Interrupt control Reserved A/D conversion result Conversion Trigger/channel setting Conversion control/status A/D conversion clock divided frequency setting Reserved Processor ID display Debugging RAM base address display Debug control Instruction break address #2 setting Instruction break address #3 setting Instruction break address #4 setting Note: Addresses marked as "Reserved" or unused peripheral circuit areas not marked in the table must not be accessed by application programs. AP-4 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL Appendix A: I/O Register List 0x4020 Register name Address 0x4020 Prescaler Control Register (8 bits) (PSC_CTL) Prescaler Bit Name D7-2 - PRUND D1 PRUN D0 S1C17003 TECHNICAL MANUAL Function reserved Prescaler run/stop in debug mode 1 Run Prescaler run/stop control 1 Run Seiko Epson Corporation Setting - 0 Stop 0 Stop Init. R/W - 0 0 Remarks - 0 when being read. R/W R/W AP-5 Appendix A: I/O Register List 0x4100-0x4124 Register name Address 0x4100 UART Ch.0 Status Register (8 bits) (UART_ST0) UART (with IrDA) Bit D7 D6 D5 D4 D3 D2 D1 D0 Name - FER PER OER RD2B TRBS RDRY TDBE Function reserved Framing error flag Parity error flag Overrun error flag Second byte receive flag Transmit busy flag Receive data ready flag Transmit data buffer empty flag Setting Init. R/W - 1 1 1 1 1 1 1 Error Error Error Ready Busy Ready Empty 0 0 0 0 0 0 0 Normal Normal Normal Empty Idle Empty Not empty - 0 0 0 0 0 0 1 Remarks - 0 when being read. R/W Reset by writing 1. R/W R/W R R Shift register status R R UART Ch.0 Transmit Data Register (UART_TXD0) 0x4101 (8 bits) D7-0 TXD[7:0] Transmit data TXD7(6) = MSB TXD0 = LSB 0x0 to 0xff (0x7f) 0x0 R/W UART Ch.0 Receive Data Register (UART_RXD0) 0x4102 (8 bits) D7-0 RXD[7:0] Receive data in the receive data buffer RXD7(6) = MSB RXD0 = LSB 0x0 to 0xff (0x7f) 0x0 UART Ch.0 Mode Register (UART_MOD0) 0x4103 (8 bits) D7-5 - CHLN D4 PREN D3 PMD D2 STPB D1 SSCK D0 reserved Character length Parity enable Parity mode select Stop bit select Input clock select - - 0 0 0 0 0 - 0 when being read. R/W R/W R/W R/W R/W 0x4104 UART Ch.0 Control Register (8 bits) (UART_CTL0) - D7 REIEN D6 RIEN D5 TIEN D4 D3-2 - RBFI D1 RXEN D0 reserved Receive error int. enable Receive buffer full int. enable Transmit buffer empty int. enable reserved Receive buffer full int. condition UART enable - 0 0 0 - 0 0 - 0 when being read. R/W R/W R/W - 0 when being read. R/W R/W UART Ch.0 Expansion Register (UART_EXP0) 0x4105 (8 bits) D7 D6-4 D7 D6 D5 D4 D3 D2 D1 D0 - FER PER OER RD2B TRBS RDRY TDBE 8 bits With parity Odd 2 bits External 0 0 0 0 0 7 bits No parity Even 1 bit Internal - 1 Enable 1 Enable 1 Enable 0 Disable 0 Disable 0 Disable - 1 2 bytes 1 Enable - reserved IRCLK[2:0] IrDA receive detection clock select D3-1 - IRMD D0 0x4120 UART Ch.1 Status Register (8 bits) (UART_ST1) 1 1 1 1 1 0 1 byte 0 Disable - IRCLK[2:0] 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 reserved IrDA mode select 1 On reserved Framing error flag Parity error flag Overrun error flag Second byte receive flag Transmit busy flag Receive data ready flag Transmit data buffer empty flag 1 1 1 1 1 1 1 Clock PCLK*1/128 PCLK*1/64 PCLK*1/32 PCLK*1/16 PCLK*1/8 PCLK*1/4 PCLK*1/2 PCLK*1/1 - Older data in the buffer is read out first. - - 0 when being read. 0x0 R/W 0 Off - 0 - 0 when being read. R/W 0 0 0 0 0 0 0 - 0 0 0 0 0 0 1 - 0 when being read. R/W Reset by writing 1. R/W R/W R R Shift register status R R - Error Error Error Ready Busy Ready Empty R Normal Normal Normal Empty Idle Empty Not empty UART Ch.1 Transmit Data Register (UART_TXD1) 0x4121 (8 bits) D7-0 TXD[7:0] Transmit data TXD7(6) = MSB TXD0 = LSB 0x0 to 0xff (0x7f) 0x0 R/W UART Ch.1 Receive Data Register (UART_RXD1) 0x4122 (8 bits) D7-0 RXD[7:0] Receive data in the receive data buffer RXD7(6) = MSB RXD0 = LSB 0x0 to 0xff (0x7f) 0x0 UART Ch.1 Mode Register (UART_MOD1) 0x4123 (8 bits) D7-5 - CHLN D4 PREN D3 PMD D2 STPB D1 SSCK D0 reserved Character length Parity enable Parity mode select Stop bit select Input clock select - - 0 0 0 0 0 - 0 when being read. R/W R/W R/W R/W R/W 0x4124 UART Ch.1 Control Register (8 bits) (UART_CTL1) - D7 REIEN D6 RIEN D5 TIEN D4 D3-2 - RBFI D1 RXEN D0 reserved Receive error int. enable Receive buffer full int. enable Transmit buffer empty int. enable reserved Receive buffer full int. condition UART enable - 0 0 0 - 0 0 - 0 when being read. R/W R/W R/W - 0 when being read. R/W R/W AP-6 1 1 1 1 1 8 bits With parity Odd 2 bits External 0 0 0 0 0 7 bits No parity Even 1 bit Internal - 1 Enable 1 Enable 1 Enable 0 Disable 0 Disable 0 Disable - 1 2 bytes 1 Enable Seiko Epson Corporation 0 1 byte 0 Disable R Older data in the buffer is read out first. S1C17003 TECHNICAL MANUAL Appendix A: I/O Register List 0x4125 UART (with IrDA) Register name Address UART Ch.1 Expansion Register (UART_EXP1) 0x4125 (8 bits) Bit Name Function - D7 reserved D6-4 IRCLK[2:0] IrDA receive detection clock select D3-1 - IRMD D0 S1C17003 TECHNICAL MANUAL reserved IrDA mode select Setting - IRCLK[2:0] 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 Clock PCLK*1/128 PCLK*1/64 PCLK*1/32 PCLK*1/16 PCLK*1/8 PCLK*1/4 PCLK*1/2 PCLK*1/1 - 1 On Seiko Epson Corporation 0 Off Init. R/W Remarks - - 0 when being read. 0x0 R/W - 0 - 0 when being read. R/W AP-7 Appendix A: I/O Register List 0x4200-0x4208 Register name Address 8-bit Timer (with Fine Mode) Ch.0 Bit Name Function Setting Init. R/W Remarks 8-bit Timer Ch.0 0x4200 Input Clock (16 bits) Select Register (T8F_CLK0) D15-4 - D3-0 DF[3:0] reserved 8-bit timer input clock select (Prescaler output clock) 8-bit Timer Ch.0 0x4202 Reload Data (16 bits) Register (T8F_TR0) D15-8 - D7-0 TR[7:0] reserved 8-bit timer reload data TR7 = MSB TR0 = LSB - 0x0 to 0xff - - 0 when being read. 0x0 R/W 8-bit Timer Ch.0 0x4204 Counter Data (16 bits) Register (T8F_TC0) D15-8 - D7-0 TC[7:0] reserved 8-bit timer counter data TC7 = MSB TC0 = LSB - 0x0 to 0xff - 0xff reserved Fine mode setup - 0x0 to 0xf - - 0 when being read. 0x0 R/W Set a number of times to insert delay into a 16-underflow period. - - 0 when being read. 0 R/W - - 0 when being read. 0 W 0 R/W 8-bit Timer Ch.0 0x4206 D15-12 - Control Register (16 bits) D11-8 TFMD[3:0] (T8F_CTL0) 8-bit Timer Ch.0 0x4208 Interrupt (16 bits) Control Register (T8F_INT0) AP-8 D7-5 D4 D3-2 D1 D0 - TRMD - PRESER PRUN reserved Count mode select reserved Timer reset Timer run/stop control D15-9 D8 D7-1 D0 - T8IE - T8IF reserved 8-bit timer interrupt enable reserved 8-bit timer interrupt flag - DF[3:0] 0xf 0xe 0xd 0xc 0xb 0xa 0x9 0x8 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 Clock reserved PCLK*1/16384 PCLK*1/8192 PCLK*1/4096 PCLK*1/2048 PCLK*1/1024 PCLK*1/512 PCLK*1/256 PCLK*1/128 PCLK*1/64 PCLK*1/32 PCLK*1/16 PCLK*1/8 PCLK*1/4 PCLK*1/2 PCLK*1/1 - 1 One shot 0 Repeat - 1 Reset 1 Run 0 Ignored 0 Stop - 1 Enable 0 Disable - 1 Cause of interrupt occurred Seiko Epson Corporation 0 Cause of interrupt not occurred - - 0 when being read. 0x0 R/W - 0 - 0 - R 0 when being read. - 0 when being read. R/W - 0 when being read. R/W Reset by writing 1. S1C17003 TECHNICAL MANUAL Appendix A: I/O Register List 0x4220-0x4244 Register name Address 16-bit Timer Bit Name Function Setting Init. R/W 16-bit Timer Ch.0 Input Clock Select Register (T16_CLK0) 0x4220 (16 bits) D15-4 - D3-0 DF[3:0] reserved Timer input clock select (Prescaler output clock) 16-bit Timer Ch.0 Reload Data Register (T16_TR0) 0x4222 (16 bits) D15-0 TR[15:0] 16-bit timer reload data TR15 = MSB TR0 = LSB 0x0 to 0xffff 0x0 R/W 16-bit Timer Ch.0 Counter Data Register (T16_TC0) 0x4224 (16 bits) D15-0 TC[15:0] 16-bit timer counter data TC15 = MSB TC0 = LSB 0x0 to 0xffff 0xffff 16-bit Timer Ch.0 Control Register (T16_CTL0) 0x4226 D15-11 - (16 bits) D10 CKACTV D9-8 CKSL[1:0] D7-5 - TRMD D4 D3-2 - PRESER D1 PRUN D0 0x4228 16-bit Timer Ch.0 Interrupt (16 bits) Control Register (T16_INT0) D15-9 D8 D7-1 D0 - T16IE - T16IF reserved External clock active level select Input clock and pulse width measurement mode select reserved Count mode select reserved Timer reset Timer run/stop control reserved 16-bit timer interrupt enable reserved 16-bit timer interrupt flag - DF[3:0] 0xf 0xe 0xd 0xc 0xb 0xa 0x9 0x8 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 Clock reserved PCLK*1/16384 PCLK*1/8192 PCLK*1/4096 PCLK*1/2048 PCLK*1/1024 PCLK*1/512 PCLK*1/256 PCLK*1/128 PCLK*1/64 PCLK*1/32 PCLK*1/16 PCLK*1/8 PCLK*1/4 PCLK*1/2 PCLK*1/1 - 1 High CKSL[1:0] 0x3 0x2 0x1 0x0 1 One shot 1 Reset 1 Run - 0 Low 1 Mode 0x0 reserved Pulse width External clock Internal clock - - 0 Repeat 0 - - 0 Ignored 0 0 Stop 0 - 1 Enable 0 Disable - 0 Cause of interrupt not occurred 1 Cause of interrupt occurred - 0 - 0 R - 0 when being read. R/W R/W - 0 when being read. R/W - 0 when being read. W R/W - 0 when being read. R/W - 0 when being read. R/W Reset by writing 1. 16-bit Timer Ch.1 Input Clock Select Register (T16_CLK1) 0x4240 (16 bits) D15-4 - D3-0 DF[3:0] reserved Timer input clock select (Prescaler output clock) 16-bit Timer Ch.1 Reload Data Register (T16_TR1) 0x4242 (16 bits) D15-0 TR[15:0] 16-bit timer reload data TR15 = MSB TR0 = LSB 0x0 to 0xffff 0x0 R/W 16-bit Timer Ch.1 Counter Data Register (T16_TC1) 0x4244 (16 bits) D15-0 TC[15:0] 16-bit timer counter data TC15 = MSB TC0 = LSB 0x0 to 0xffff 0xffff S1C17003 TECHNICAL MANUAL - DF[3:0] 0xf 0xe 0xd 0xc 0xb 0xa 0x9 0x8 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 Seiko Epson Corporation Clock reserved PCLK*1/16384 PCLK*1/8192 PCLK*1/4096 PCLK*1/2048 PCLK*1/1024 PCLK*1/512 PCLK*1/256 PCLK*1/128 PCLK*1/64 PCLK*1/32 PCLK*1/16 PCLK*1/8 PCLK*1/4 PCLK*1/2 PCLK*1/1 Remarks - - 0 when being read. 0x0 R/W - - 0 when being read. 0x0 R/W R AP-9 Appendix A: I/O Register List 0x4246-0x4268 Register name Address 16-bit Timer Ch.1 Control Register (T16_CTL1) 16-bit Timer Bit Name 0x4246 D15-11 - (16 bits) D10 CKACTV D9-8 CKSL[1:0] D7-5 - TRMD D4 D3-2 - PRESER D1 PRUN D0 0x4248 16-bit Timer Ch.1 Interrupt (16 bits) Control Register (T16_INT1) D15-9 D8 D7-1 D0 - T16IE - T16IF Function reserved External clock active level select Input clock and pulse width measurement mode select reserved Count mode select reserved Timer reset Timer run/stop control reserved 16-bit timer interrupt enable reserved 16-bit timer interrupt flag Setting Init. R/W - 1 High CKSL[1:0] 0x3 0x2 0x1 0x0 0 Low Mode reserved Pulse width External clock Internal clock - 1 One shot 0 Repeat - 1 Reset 1 Run 0 Ignored 0 Stop - 1 Enable 0 Disable - 0 Cause of interrupt not occurred 1 Cause of interrupt occurred - 0 - 0 0 - 0 when being read. R/W - 0 when being read. W R/W - 0 - 0 - 0 when being read. R/W - 0 when being read. R/W Reset by writing 1. 16-bit Timer Ch.2 Input Clock Select Register (T16_CLK2) 0x4260 (16 bits) D15-4 - D3-0 DF[3:0] reserved Timer input clock select (Prescaler output clock) 16-bit Timer Ch.2 Reload Data Register (T16_TR2) 0x4262 (16 bits) D15-0 TR[15:0] 16-bit timer reload data TR15 = MSB TR0 = LSB 0x0 to 0xffff 0x0 R/W 16-bit Timer Ch.2 Counter Data Register (T16_TC2) 0x4264 (16 bits) D15-0 TC[15:0] 16-bit timer counter data TC15 = MSB TC0 = LSB 0x0 to 0xffff 0xffff 16-bit Timer Ch.2 Control Register (T16_CTL2) 0x4266 D15-11 - (16 bits) D10 CKACTV D9-8 CKSL[1:0] D7-5 - TRMD D4 D3-2 - PRESER D1 PRUN D0 0x4268 16-bit Timer Ch.2 Interrupt (16 bits) Control Register (T16_INT2) AP-10 D15-9 D8 D7-1 D0 - T16IE - T16IF reserved External clock active level select Input clock and pulse width measurement mode select reserved Count mode select reserved Timer reset Timer run/stop control reserved 16-bit timer interrupt enable reserved 16-bit timer interrupt flag - DF[3:0] 0xf 0xe 0xd 0xc 0xb 0xa 0x9 0x8 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 Clock reserved PCLK*1/16384 PCLK*1/8192 PCLK*1/4096 PCLK*1/2048 PCLK*1/1024 PCLK*1/512 PCLK*1/256 PCLK*1/128 PCLK*1/64 PCLK*1/32 PCLK*1/16 PCLK*1/8 PCLK*1/4 PCLK*1/2 PCLK*1/1 - - 0 when being read. 0x0 R/W - 1 High CKSL[1:0] 0x3 0x2 0x1 0x0 1 One shot 1 Reset 1 Run - 0 Low 1 Mode 0x0 reserved Pulse width External clock Internal clock - - 0 Repeat 0 - - 0 Ignored 0 0 Stop 0 - 1 Enable 0 Disable - 1 Cause of interrupt occurred Seiko Epson Corporation 0 Cause of interrupt not occurred Remarks - - 0 when being read. 1 R/W 0x0 R/W - 0 - 0 R - 0 when being read. R/W R/W - 0 when being read. R/W - 0 when being read. W R/W - 0 when being read. R/W - 0 when being read. R/W Reset by writing 1. S1C17003 TECHNICAL MANUAL Appendix A: I/O Register List 0x4280-0x4288 Register name Address 8-bit Timer (with Fine Mode) Ch.1 Bit Name Function Setting Init. R/W Remarks 8-bit Timer Ch.1 0x4280 Input Clock (16 bits) Select Register (T8F_CLK1) D15-4 - D3-0 DF[3:0] reserved 8-bit timer input clock select (Prescaler output clock) 8-bit Timer Ch.1 0x4282 Reload Data (16 bits) Register (T8F_TR1) D15-8 - D7-0 TR[7:0] reserved 8-bit timer reload data TR7 = MSB TR0 = LSB - 0x0 to 0xff - - 0 when being read. 0x0 R/W 8-bit Timer Ch.1 0x4284 Counter Data (16 bits) Register (T8F_TC1) D15-8 - D7-0 TC[7:0] reserved 8-bit timer counter data TC7 = MSB TC0 = LSB - 0x0 to 0xff - 0xff reserved Fine mode setup - 0x0 to 0xf - - 0 when being read. 0x0 R/W Set a number of times to insert delay into a 16-underflow period. - - 0 when being read. 0 R/W - - 0 when being read. 0 W 0 R/W 8-bit Timer Ch.1 0x4286 D15-12 - Control Register (16 bits) D11-8 TFMD[3:0] (T8F_CTL1) 8-bit Timer Ch.1 0x4288 Interrupt (16 bits) Control Register (T8F_INT1) D7-5 D4 D3-2 D1 D0 - TRMD - PRESER PRUN reserved Count mode select reserved Timer reset Timer run/stop control D15-9 D8 D7-1 D0 - T8IE - T8IF reserved 8-bit timer interrupt enable reserved 8-bit timer interrupt flag S1C17003 TECHNICAL MANUAL - DF[3:0] 0xf 0xe 0xd 0xc 0xb 0xa 0x9 0x8 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 Clock reserved PCLK*1/16384 PCLK*1/8192 PCLK*1/4096 PCLK*1/2048 PCLK*1/1024 PCLK*1/512 PCLK*1/256 PCLK*1/128 PCLK*1/64 PCLK*1/32 PCLK*1/16 PCLK*1/8 PCLK*1/4 PCLK*1/2 PCLK*1/1 - 1 One shot 0 Repeat - 1 Reset 1 Run 0 Ignored 0 Stop - 1 Enable 0 Disable - 1 Cause of interrupt occurred Seiko Epson Corporation 0 Cause of interrupt not occurred - - 0 when being read. 0x0 R/W - 0 - 0 - R 0 when being read. - 0 when being read. R/W - 0 when being read. R/W Reset by writing 1. AP-11 Appendix A: I/O Register List 0x4306-0x4318 Register name Address Interrupt Controller Bit Name Function Setting Init. R/W Remarks Interrupt Level 0x4306 D15-11 - Setup Register 0 (16 bits) D10-8 ILV1[2:0] (ITC_LV0) D7-3 - D2-0 ILV0[2:0] reserved P1 interrupt level reserved P0 interrupt level - 0 to 7 - 0 to 7 - - 0 when being read. 0x0 R/W - - 0 when being read. 0x0 R/W Interrupt Level 0x4308 D15-11 - Setup Register 1 (16 bits) D10-8 ILV3[2:0] (ITC_LV1) D7-3 - D2-0 ILV2[2:0] reserved CT interrupt level reserved SWT interrupt level - 0 to 7 - 0 to 7 - - 0 when being read. 0x0 R/W - - 0 when being read. 0x0 R/W Interrupt Level 0x430a Setup Register 2 (16 bits) (ITC_LV2) reserved T8OSC1 interrupt level - 0 to 7 - - 0 when being read. 0x0 R/W Interrupt Level 0x430c D15-11 - Setup Register 3 (16 bits) D10-8 ILV7[2:0] (ITC_LV3) D7-0 - reserved T16E Ch.0 interrupt level reserved - 0 to 7 - - - 0 when being read. 0x0 R/W - - 0 when being read. Interrupt Level 0x430e D15-11 - Setup Register 4 (16 bits) D10-8 ILV9[2:0] (ITC_LV4) D7-3 - D2-0 ILV8[2:0] reserved T16 Ch.0 interrupt level reserved T8F Ch.0/Ch.1 interrupt level - 0 to 7 - 0 to 7 - - 0 when being read. 0x0 R/W - - 0 when being read. 0x0 R/W Interrupt Level 0x4310 D15-11 - Setup Register 5 (16 bits) D10-8 ILV11[2:0] (ITC_LV5) D7-3 - D2-0 ILV10[2:0] reserved T16 Ch.2 interrupt level reserved T16 Ch.1 interrupt level - 0 to 7 - 0 to 7 - - 0 when being read. 0x0 R/W - - 0 when being read. 0x0 R/W Interrupt Level 0x4312 D15-11 - Setup Register 6 (16 bits) D10-8 ILV13[2:0] (ITC_LV6) D7-3 - D2-0 ILV12[2:0] reserved UART Ch.1/I2C slave interrupt level reserved UART Ch.0 interrupt level - 0 to 7 - - 0 when being read. 0x0 R/W - 0 to 7 - - 0 when being read. 0x0 R/W Interrupt Level 0x4314 D15-11 - Setup Register 7 (16 bits) D10-8 ILV15[2:0] (ITC_LV7) D7-3 - D2-0 ILV14[2:0] reserved I2C Master interrupt level reserved SPI interrupt level - 0 to 7 - 0 to 7 - - 0 when being read. 0x0 R/W - - 0 when being read. 0x0 R/W Interrupt Level 0x4316 Setup Register 8 (16 bits) (ITC_LV8) D15-3 - D2-0 ILV16[2:0] reserved REMC interrupt level - 0 to 7 - - 0 when being read. 0x0 R/W Interrupt Level 0x4318 Setup Register 9 (16 bits) (ITC_LV9) D15-3 - D2-0 ILV18[2:0] reserved ADC10SA interrupt level - 0 to 7 - - 0 when being read. 0x0 R/W AP-12 D15-3 - D2-0 ILV4[2:0] Seiko Epson Corporation S1C17003 TECHNICAL MANUAL Appendix A: I/O Register List 0x4320-0x4326 Register name Address SPI Status Register (SPI_ST) 0x4320 (16 bits) SPI Bit Name D15-3 - SPBSY D2 D1 D0 SPRBF SPTBE Function reserved Transfer busy flag (master) ss signal low flag (slave) Receive data buffer full flag Transmit data buffer empty flag Setting - 1 1 1 1 Busy ss = L Full Empty 0 0 0 0 Idle ss = H Not full Not empty Init. R/W - 0 - R 0 1 R R Remarks 0 when being read. SPI Transmit Data Register (SPI_TXD) 0x4322 (16 bits) D15-8 - reserved D7-0 SPTDB[7:0] SPI transmit data buffer SPTDB7 = MSB SPTDB0 = LSB - 0x0 to 0xff - - 0 when being read. 0x0 R/W SPI Receive Data Register (SPI_RXD) 0x4324 (16 bits) D15-8 - reserved D7-0 SPRDB[7:0] SPI receive data buffer SPRDB7 = MSB SPRDB0 = LSB - 0x0 to 0xff - 0x0 - R 0 when being read. SPI Control Register (SPI_CTL) 0x4326 D15-10 - (16 bits) MCLK D9 MLSB D8 D7-6 - SPRIE D5 SPTIE D4 CPHA D3 CPOL D2 MSSL D1 SPEN D0 - - 0 0 - 0 0 0 0 0 0 - R/W R/W - R/W R/W R/W R/W R/W R/W 0 when being read. S1C17003 TECHNICAL MANUAL reserved SPI clock source select LSB/MSB first mode select reserved Receive data buffer full int. enable Transmit data buffer empty int. enable Clock phase select Clock polarity select Master/slave mode select SPI enable 1 T16 Ch.1 1 LSB 0 PCLK*1/4 0 MSB - 1 1 1 1 1 1 Enable Enable Data out Active L Master Enable Seiko Epson Corporation 0 0 0 0 0 0 Disable Disable Data in Active H Slave Disable 0 when being read. These bits must be set before setting SPEN to 1. AP-13 Appendix A: I/O Register List I2C Master 0x4340-0x4346 Register name Address Bit Name Function I2C Enable Register (I2C_EN) 0x4340 (16 bits) I2C Control Register (I2C_CTL) 0x4342 D15-10 - (16 bits) RBUSY D9 TBUSY D8 D7-5 - NSERM D4 D3-2 - STP D1 STRT D0 reserved Receive busy flag Transmit busy flag reserved Noise remove on/off reserved Stop control Start control 0x4344 D15-12 - (16 bits) D11 RBRDY D10 RXE TXE D9 RTACK D8 D7-0 RTDT[7:0] reserved Receive buffer ready Receive execution Transmit execution Receive/transmit ACK Receive/transmit data RTDT7 = MSB RTDT0 = LSB I2C Data Register (I2C_DAT) D0 0x4346 I2C Interrupt Control Register (16 bits) (I2C_ICTL) AP-14 D15-1 - I2CEN D15-2 - RINTE D1 TINTE D0 Setting reserved I2C enable reserved Receive interrupt enable Transmit interrupt enable - 1 Enable 0 Disable - 1 Busy 1 Busy 0 Idle 0 Idle - 1 On 0 Off - 1 Stop 1 Start 1 1 1 1 0 Ignored 0 Ignored - Ready 0 Empty Receive 0 Ignored Transmit 0 Ignored Error 0 ACK 0x0 to 0xff - 1 Enable 1 Enable Seiko Epson Corporation 0 Disable 0 Disable Init. R/W Remarks - - 0 when being read. 0 R/W - 0 0 - 0 - 0 0 - 0 when being read. R R - 0 when being read. R/W - 0 when being read. R/W R/W - 0 0 0 0 0x0 - 0 when being read. R R/W R/W R/W R/W - 0 0 - 0 when being read. R/W R/W S1C17003 TECHNICAL MANUAL Appendix A: I/O Register List I2C Slave 0x4360-0x436c Register name Address Bit Name Function Setting Init. R/W Remarks I2C Slave Transmit Data Register (I2CS_TRNS) 0x4360 (16 bits) D15-8 - reserved D7-0 SDATA[7:0] I2C slave transmit data - 0-0xff - - 0 when being read. 0x0 R/W I2C Slave Receive Data Register (I2CS_RECV) 0x4362 (16 bits) D15-8 - reserved D7-0 RDATA[7:0] I2C slave receive data - 0-0xff - 0x0 I2C Slave Address Setup Register (I2CS_SADRS) 0x4364 (16 bits) D15-7 - reserved D6-0 SADRS[6:0] I2C slave address - 0-0x7f - - 0 when being read. 0x0 R/W 0x4366 I2C Slave Control Register (16 bits) (I2CS_CTL) D15-9 D8 D7 D6 D5 D4 D3 D2 D1 D0 - reserved TBUF_CLR I2CS_TRNS register clear I2C_EN I2C slave enable SOFTRESET Software reset NAK_ANS NAK answer BFREQ_EN Bus free request enable CLKSTR_EN Clock stretch On/Off NF_EN Noise filter On/Off ASDET_EN Async.address detection On/Off COM_MODE I2C slave communication mode 0x4368 I2C Slave Status Register (16 bits) (I2CS_STAT) D15-8 D7 D6 D5 - BSTAT - TXUDF RXOVF BFREQ DMS ASDET DA_NAK DA_STOP reserved Bus status transition reserved Transmit data underflow Receive data overflow Bus free request Output data mismatch Async. address detection status NAK receive status STOP condition detect 1 Occurred 1 1 1 1 1 Occurred Error Detected NAK Detected reserved Receive data ready Transmit data empty I2C bus status I2C slave select status Read/write direction 1 1 1 1 1 Ready Empty Busy Selected Output D4 D3 D2 D1 D0 I2C Slave Access Status Register (I2CS_ASTAT) 0x436a (16 bits) D15-5 D4 D3 D2 D1 D0 - RXRDY TXEMP BUSY SELECTED R/W 0x436c I2C Slave Interrupt Control (16 bits) Register (I2CS_ICTL) D15-3 D2 D1 D0 - reserved BSTAT_IEN Bus status interrupt enable RXRDY_IEN Receive interrupt enable TXEMP_IEN Transmit interrupt enable S1C17003 TECHNICAL MANUAL - 1 1 1 1 1 1 1 1 1 Clear state Enable Reset NAK Enable On On On Active - 0 when being read. R/W R/W R/W R/W R/W R/W R/W R/W R/W NAK response when standby 0 Not occurred - 0 - 0 - 0 when being read. R - 0 when being read. R/W Reset by writing 1. 0 0 0 0 0 Not occurred Normal Not detected ACK Not detected 0 0 0 0 0 R/W R/W R/W R/W R/W 0 0 0 0 0 Not ready Not empty Free Not selected Input - 0 0 0 0 0 - R R R R R Normal Disable Cancel ACK Disable Off Off Off Standby - 0 Unchanged - - - 1 Enable 1 Enable 1 Enable Seiko Epson Corporation 0 when being read. - 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 Changed - R 0 Disable 0 Disable 0 Disable - 0 0 0 0 when being read. - 0 when being read. R/W R/W R/W AP-15 Appendix A: I/O Register List 0x5000-0x5003 Register name Address Clock Timer Bit Name Function 0x5000 Clock Timer Control Register (8 bits) (CT_CTL) D7-5 - CTRST D4 D3-1 - CTRUN D0 0x5001 Clock Timer Counter Register (8 bits) (CT_CNT) D7-0 CTCNT[7:0] Clock timer counter value Clock Timer Interrupt Mask Register (CT_IMSK) 0x5002 (8 bits) D7-4 D3 D2 D1 D0 Clock Timer Interrupt Flag Register (CT_IFLG) 0x5003 (8 bits) D7-4 - CTIF32 D3 CTIF8 D2 CTIF2 D1 CTIF1 D0 AP-16 - CTIE32 CTIE8 CTIE2 CTIE1 reserved Clock timer reset reserved Clock timer run/stop control reserved 32 Hz interrupt enable 8 Hz interrupt enable 2 Hz interrupt enable 1 Hz interrupt enable reserved 32 Hz interrupt flag 8 Hz interrupt flag 2 Hz interrupt flag 1 Hz interrupt flag Setting Init. R/W - 1 Reset - 0 - 0 0 Ignored - 1 Run 1 1 1 1 0 Stop 0x0 to 0xff 0 - - 0 0 0 0 - 0 when being read. R/W R/W R/W R/W - 0 0 0 0 - 0 when being read. R/W Reset by writing 1. R/W R/W R/W Enable Enable Enable Enable 0 0 0 0 Disable Disable Disable Disable - 1 Cause of interrupt occurred Seiko Epson Corporation Remarks - 0 when being read. W - R/W 0 Cause of interrupt not occurred R S1C17003 TECHNICAL MANUAL Appendix A: I/O Register List 0x5020-0x5023 Register name Address Stopwatch Timer Control Register (SWT_CTL) 0x5020 (8 bits) 0x5021 Stopwatch Timer BCD (8 bits) Counter Register (SWT_BCNT) Stopwatch Timer Bit D7-5 D4 D3-1 D0 Name - SWTRST - SWTRUN Function reserved Stopwatch timer reset reserved Stopwatch timer run/stop control Setting - 1 Reset 1 Run D7-4 BCD10[3:0] 1/10 sec. BCD counter value D3-0 BCD100[3:0] 1/100 sec. BCD counter value - SIE1 SIE10 SIE100 Stopwatch Timer Interrupt Mask Register (SWT_IMSK) 0x5022 (8 bits) D7-3 D2 D1 D0 Stopwatch Timer Interrupt Flag Register (SWT_IFLG) 0x5023 (8 bits) D7-3 - SIF1 D2 SIF10 D1 SIF100 D0 S1C17003 TECHNICAL MANUAL 0 Ignored - reserved 1 Hz interrupt enable 10 Hz interrupt enable 100 Hz interrupt enable 1 Enable 1 Enable 1 Enable reserved 1 Hz interrupt flag 10 Hz interrupt flag 100 Hz interrupt flag 1 Cause of interrupt occurred 0 Stop - 0 - 0 Remarks - 0 when being read. W - R/W 0 to 9 0 R 0 to 9 0 R - 0 Disable 0 Disable 0 Disable - 0 0 0 - 0 when being read. R/W R/W R/W 0 Cause of interrupt not occurred - 0 0 0 - 0 when being read. R/W Reset by writing 1. R/W R/W - Seiko Epson Corporation Init. R/W AP-17 Appendix A: I/O Register List 0x5040-0x5041 Register name Address Watchdog Timer Bit Name Function Watchdog Timer Control Register (WDT_CTL) 0x5040 (8 bits) D7-5 - reserved WDTRST D4 Watchdog timer reset D3-0 WDTRUN[3:0] Watchdog timer run/stop control Watchdog Timer Status Register (WDT_ST) 0x5041 (8 bits) D7-2 - AP-18 D1 D0 WDTMD WDTST Setting - - - 1 Reset 0 NMI 1 NMI occurred 0 Not occurred 0 0 R/W R Seiko Epson Corporation Remarks - - 0 when being read. 0 W 1010 R/W 1 Reset 0 Ignored Other than 1010 1010 Run Stop reserved NMI/Reset mode select NMI status Init. R/W - 0 when being read. S1C17003 TECHNICAL MANUAL Appendix A: I/O Register List 0x5060-0x5065 Register name Address Clock Source Select Register (OSC_SRC) 0x5060 (8 bits) 0x5061 Oscillation Control Register (8 bits) (OSC_CTL) 0x5062 Noise Filter Enable Register (8 bits) (OSC_NFEN) FOUT Control Register (OSC_FOUT) 0x5064 (8 bits) Oscillator Bit Function reserved reserved System clock source select D7-6 - reserved D5-4 OSC3WT[1:0] OSC3 wait cycle select Setting - - 1 OSC1 OSC3WT[1:0] 0x3 0x2 0x1 0x0 reserved OSC1 enable OSC3 enable 1 Enable 1 Enable D7-2 - RSTFE D1 NMIFE D0 reserved Reset noise filter enable NMI noise filter enable 1 Enable 1 Enable D7-4 - D3-2 FOUTHD [1:0] reserved FOUTH clock division ratio select FOUTHE FOUT1E FOUTH output enable FOUT1 output enable 0 HSCLK - D3-2 - OSC1EN D1 OSC3EN D0 D1 D0 T8OSC1 Clock 0x5065 Control Register (8 bits) (OSC_T8OSC1) Name D7-2 - - D1 CLKSRC D0 Wait cycle 128 cycles 256 cycles 512 cycles 1024 cycles - Remarks - 0 when being read. R 1 when being read. R/W 0 - 0 when being read. 0x0 R/W - 0 1 - 0 when being read. R/W R/W 0 Disable 0 Disable - 1 0 - 0 when being read. R/W R/W - - FOUTHD[1:0] Division ratio reserved 0x3 HSCLK*1/4 0x2 HSCLK*1/2 0x1 HSCLK*1/1 0x0 1 Enable 0 Disable 1 Enable 0 Disable Seiko Epson Corporation - 1 0 0 Disable 0 Disable D7-4 - reserved - D3-1 T8O1CK[2:0] T8OSC1 clock division ratio select T8O1CK[2:0] Division ratio reserved 0x7-0x6 OSC1*1/32 0x5 OSC1*1/16 0x4 OSC1*1/8 0x3 OSC1*1/4 0x2 OSC1*1/2 0x1 OSC1*1/1 0x0 T8O1CE D0 T8OSC1 clock output enable 1 Enable 0 Disable S1C17003 TECHNICAL MANUAL Init. R/W - - 0 when being read. 0x0 R/W Note: FOUTHD must be operated while FOUT1E and FOUT1E are disabled. 0 R/W 0 R/W - - 0 when being read. 0x0 R/W Note: T8O1CK must be operated while T8O1CE is disabled. 0 R/W AP-19 Appendix A: I/O Register List 0x5080-0x5081 Register name Address Clock Generator Bit Name Function PCLK Control Register (CLG_PCLK) 0x5080 (8 bits) D7-2 - reserved D1-0 PCKEN[1:0] PCLK enable CCLK Control Register (CLG_CCLK) 0x5081 (8 bits) D7-2 - reserved D1-0 CCLKGR[1:0] CCLK clock gear ratio select AP-20 Setting Init. R/W - PCKEN[1:0] 0x3 0x2 0x1 0x0 PCLK supply Enable Not allowed Not allowed Disable - CCLKGR[1:0] 0x3 0x2 0x1 0x0 Seiko Epson Corporation Gear ratio 1/8 1/4 1/2 1/1 Remarks - - 0 when being read. 0x3 R/W - - 0 when being read. 0x0 R/W S1C17003 TECHNICAL MANUAL Appendix A: I/O Register List 0x50c0-0x50c5 Register name Address 8-bit OSC1 Timer Name Function D7-5 D4 D3-2 D1 D0 - T8ORST - T8ORMD T8ORUN reserved Timer reset reserved Count mode select Timer run/stop control 0x50c1 (8 bits) D7-0 T8OCNT[7:0] Timer counter data T8OCNT7 = MSB T8OCNT0 = LSB 0x0 to 0xff 0x0 0x50c2 8-bit OSC1 Timer Compare (8 bits) Data Register (T8OSC1_CMP) D7-0 T8OCMP[7:0] Compare data T8OCMP7 = MSB T8OCMP0 = LSB 0x0 to 0xff 0x0 R/W 8-bit OSC1 0x50c3 Timer Interrupt (8 bits) Mask Register (T8OSC1_IMSK) D7-1 D0 - T8OIE 0x50c4 8-bit OSC1 Timer Interrupt (8 bits) Flag Register (T8OSC1_IFLG) D7-1 - T8OIF D0 8-bit OSC1 0x50c5 Timer PWM (8 bits) Duty Data Register (T8OSC1_DUTY) D7-0 T8ODTY[7:0] PWM output duty data T8ODTY7 = MSB T8ODTY0 = LSB 8-bit OSC1 Timer Control Register (T8OSC1_CTL) 0x50c0 (8 bits) 8-bit OSC1 Timer Counter Data Register (T8OSC1_CNT) Bit S1C17003 TECHNICAL MANUAL reserved 8-bit OSC1 timer interrupt enable reserved 8-bit OSC1 timer interrupt flag Setting - 1 Reset 0 Ignored - 1 One shot 1 Run 0 Repeat 0 Stop - 1 Enable 0 Disable - 1 Cause of interrupt occurred Seiko Epson Corporation 0 Cause of interrupt not occurred 0x0 to 0xff Init. R/W - 0 - 0 0 Remarks - 0 when being read. W - R/W R/W R - 0 - 0 when being read. R/W - 0 - 0 when being read. R/W Reset by writing 1. 0x0 R/W AP-21 Appendix A: I/O Register List 0x5200-0x5213 Register name Address P Port & Port MUX Name Function P0 Port Input Data Register (P0_IN) 0x5200 (8 bits) D7-0 P0IN[7:0] P0[7:0] port input data P0 Port Output Data Register (P0_OUT) 0x5201 (8 bits) P0 Port Output Enable Register (P0_IO) 0x5202 (8 bits) P0 Port Pull-up 0x5203 Control Register (8 bits) (P0_PU) Bit x R D7-0 P0OUT[7:0] P0[7:0] port output data 1 1 (H) 0 0 (L) 0 R/W D7-0 P0OEN[7:0] P0[7:0] port output enable 1 Enable 0 Disable 0 R/W D7-0 P0PU[7:0] P0[7:0] port pull-up enable 1 Enable 0 Disable P0[7:0] port interrupt enable 1 Enable 0 Disable 0x5205 (8 bits) D7-0 P0IE[7:0] P0 Port Interrupt Edge Select Register (P0_EDGE) 0x5206 (8 bits) D7-0 P0 Port Interrupt Flag Register (P0_IFLG) 0x5207 (8 bits) D7-0 P0IF[7:0] P0 Port Chattering Filter Control Register (P0_CHAT) 0x5208 (8 bits) D7 D6-4 P0EDGE[7:0] P0[7:0] port interrupt edge select P0[7:0] port interrupt flag - reserved P0CF2[2:0] P0[7:4] chattering filter time - D3 reserved D2-0 P0CF1[2:0] P0[3:0] chattering filter time 0x5209 (8 bits) 0x520a P0 Port Input Enable Register (8 bits) (P0_IEN) Init. R/W 0 0 (L) P0 Port Interrupt Mask Register (P0_IMSK) P0 Port KeyEntry Reset Configuration Register (P0_KRST) Setting 1 1 (H) D7-2 - reserved D1-0 P0KRST[1:0] P0 port key-entry reset configuration 1 R/W (0xff) 0 R/W 1 Falling edge 0 Rising edge 0 R/W 0 Cause of interrupt not occurred 0 R/W Reset by writing 1. 1 Cause of interrupt occurred - P0CF2[2:0] 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 Filter time 16384/fPCLK 8192/fPCLK 4096/fPCLK 2048/fPCLK 1024/fPCLK 512/fPCLK 256/fPCLK None - P0CF1[2:0] 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 Filter time 16384/fPCLK 8192/fPCLK 4096/fPCLK 2048/fPCLK 1024/fPCLK 512/fPCLK 256/fPCLK None - - - 0 when being read. 0 R/W 0x0 R/W - - 0 when being read. 0x0 R/W - - 0 when being read. 0x0 R/W P0KRST[1:0] 0x3 0x2 0x1 0x0 Configuration P0[3:0] = 0 P0[2:0] = 0 P0[1:0] = 0 Disable D7-0 P0IEN[7:0] P0[7:0] port input enable 1 Enable 0 Disable 1 1 (H) 0 0 (L) x R 0xff R/W P1 Port Input Data Register (P1_IN) 0x5210 (8 bits) D7-0 P1IN[7:0] P1 Port Output Data Register (P1_OUT) 0x5211 (8 bits) D7-0 P1OUT[7:0] P1[7:0] port output data 1 1 (H) 0 0 (L) 0 R/W P1 Port Output Enable Register (P1_IO) 0x5212 (8 bits) D7-0 P1OEN[7:0] P1[7:0] port output enable 1 Enable 0 Disable 0 R/W D7-0 P1PU[7:0] 1 Enable 0 Disable P1 Port Pull-up 0x5213 Control Register (8 bits) (P1_PU) AP-22 P1[7:0] port input data P1[7:0] port pull-up enable Remarks Seiko Epson Corporation 1 R/W (0xff) S1C17003 TECHNICAL MANUAL Appendix A: I/O Register List 0x5215-0x523a Register name Address P Port & Port MUX Bit Name Function P1 Port Interrupt Mask Register (P1_IMSK) 0x5215 (8 bits) D7-0 P1IE[7:0] P1 Port Interrupt Edge Select Register (P1_EDGE) 0x5216 (8 bits) D7-0 P1 Port Interrupt Flag Register (P1_IFLG) 0x5217 (8 bits) D7-0 P1IF[7:0] P1 Port Chattering Filter Control Register (P1_CHAT) 0x5218 (8 bits) - D7 reserved D6-4 P1CF2[2:0] P1[7:4] chattering filter time P1[7:0] port interrupt enable P1EDGE[7:0] P1[7:0] port interrupt edge select P1[7:0] port interrupt flag - D3 reserved D2-0 P1CF1[2:0] P1[3:0] chattering filter time 0x521a P1 Port Input Enable Register (8 bits) (P1_IEN) Setting 1 Enable 0 Disable Init. R/W R/W 1 Falling edge 0 Rising edge 0 R/W 0 Cause of interrupt not occurred 0 R/W Reset by writing 1. 1 Cause of interrupt occurred - P0CF2[2:0] 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 Filter time 16384/fPCLK 8192/fPCLK 4096/fPCLK 2048/fPCLK 1024/fPCLK 512/fPCLK 256/fPCLK None - P0CF1[2:0] 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 Filter time 16384/fPCLK 8192/fPCLK 4096/fPCLK 2048/fPCLK 1024/fPCLK 512/fPCLK 256/fPCLK None - - 0 when being read. 0 R/W 0x0 R/W - - 0 when being read. 0x0 R/W D7-0 P1IEN[7:0] P1[7:0] port input enable 1 Enable 0 Disable 1 1 (H) 0 0 (L) x R 0xff R/W P2 Port Input Data Register (P2_IN) 0x5220 (8 bits) D7-0 P2IN[7:0] P2 Port Output Data Register (P2_OUT) 0x5221 (8 bits) D7-0 P2OUT[7:0] P2[7:0] port output data 1 1 (H) 0 0 (L) 0 R/W P2 Port Output Enable Register (P2_IO) 0x5222 (8 bits) D7-0 P2OEN[7:0] P2[7:0] port output enable 1 Enable 0 Disable 0 R/W P2 Port Pull-up 0x5223 Control Register (8 bits) (P2_PU) D7-0 P2PU[7:0] 1 Enable 0 Disable 1 R/W (0xff) 0x522a P2 Port Input Enable Register (8 bits) (P2_IEN) D7-0 P2IEN[7:0] P2[7:0] port input enable 1 Enable 0 Disable 0xff R/W 1 1 (H) 0 0 (L) x R P2[7:0] port input data P2[7:0] port pull-up enable P3 Port Input Data Register (P3_IN) 0x5230 (8 bits) D7-0 P3IN[7:0] P3 Port Output Data Register (P3_OUT) 0x5231 (8 bits) D7-0 P3OUT[7:0] P3[7:0] port output data 1 1 (H) 0 0 (L) 0 R/W P3 Port Output Enable Register (P3_IO) 0x5232 (8 bits) D7-0 P3OEN[7:0] P3[7:0] port output enable 1 Enable 0 Disable 0 R/W P3 Port Pull-up 0x5233 Control Register (8 bits) (P3_PU) D7-0 P3PU[7:0] 1 Enable 0 Disable 1 R/W (0xff) 0x523a P3 Port Input Enable Register (8 bits) (P3_IEN) D7-0 P3IEN[7:0] P3[7:0] port input enable 1 Enable 0 Disable 0xff R/W S1C17003 TECHNICAL MANUAL P3[7:0] port input data P3[7:0] port pull-up enable Remarks 0 Seiko Epson Corporation P25, P26 are 0, when being read. AP-23 Appendix A: I/O Register List 0x5240-0x52a4 Register name Address P Port & Port MUX Name Function P4 Port Input Data Register (P4_IN) 0x5240 (8 bits) D7-4 - D3-0 P4IN[7:0] reserved P4[3:0] port input data P4 Port Output Data Register (P4_OUT) 0x5241 (8 bits) D7-4 - reserved D3-0 P4OUT[3:0] P4[3:0] port output data 1 1 (H) P4 Port Output Enable Register (P4_IO) 0x5242 (8 bits) D7-4 - reserved D3-0 P4OEN[3:0] P4[3:0] port output enable 1 Enable P4 Port Pull-up 0x5243 Control Register (8 bits) (P4_PU) D7-4 - D3-0 P4PU[3:0] 1 Enable 0x524a P4 Port Input Enable Register (8 bits) (P4_IEN) D7-4 - reserved D3-0 P4IEN[3:0] P4[3:0] port input enable 0x52a0 P0 Port Function Select (8 bits) Register (P0_PMUX) 0x52a1 P0 Port Function Select (8 bits) Register (P0_PMUX) 0x52a2 P1 Port Function Select (8 bits) Register (P1_PMUX) Bit D7 D6 D5 D4 D3 D2 D1 D0 - P03MUX - P02MUX - P01MUX - P00MUX reserved P03 port function select reserved P02 port function select reserved P01 port function select reserved P00 port function select D7 D6 D5 D4 D3 D2 D1 D0 - P07MUX - P06MUX - P05MUX - P04MUX reserved P07 port function select reserved P06 port function select reserved P05 port function select reserved P04 port function select D7-6 P13MUX [1:0] P13 port function select - P12MUX - P11MUX - P10MUX reserved P12 port function select reserved P11 port function select reserved P10 port function select - D7 P17MUX D6 D5-4 P16MUX [1:0] reserved P17 port function select P16 port function select D3-2 P15MUX [1:0] P15 port function select D1-0 P14MUX [1:0] P14 port function select - P23MUX - P22MUX - P21MUX - P20MUX reserved P23 port function select reserved P22 port function select reserved P21 port function select reserved P20 port function select D5 D4 D3 D2 D1 D0 0x52a3 P1 Port Function Select (8 bits) Register (P1_PMUX) 0x52a4 P2 Port Function Select (8 bits) Register (P2_PMUX) AP-24 reserved P4[3:0] port pull-up enable D7 D6 D5 D4 D3 D2 D1 D0 Setting Init. R/W - 1 1 (H) 0 0 (L) 0 0 (L) - 0 - 0 when being read. R/W 0 Disable - 0 - 0 when being read. R/W - - - - - - 1 when being read. 0xff R/W 0 Disable - 1 #ADTRG 0 P03 - 1 reserved 0 P02/EXCL0 - 1 REMI 0 P01 - 1 REMO 0 P00 - 1 #SPISS 0 P07 - 1 SDI 0 P06 - 1 SDO 0 P05 - 1 SPICLK 0 P04 P13MUX[1:0] 0x3 0x2 0x1 0x0 Port Reserved Reserved Reserved P13/EXCL1 - 1 SIN 0 P12 - 1 SOUT 0 P11 - 1 SCLK 0 P10 - 1 AIN3 0 P17 P16MUX[1:0] Port Reserved 0x3 Reserved 0x2 SCLK1 0x1 P16/EXCL4 0x0 P15MUX[1:0] Port Reserved 0x3 Reserved 0x2 Reserved 0x1 P15/EXCL3 0x0 P14MUX[1:0] Port Reserved 0x3 Reserved 0x2 Reserved 0x1 P14/EXCL2 0x0 - 1 Reserved 0 P23 - 1 AIN0 0 P22 - 1 AIN1 0 P21 - 1 AIN2 Seiko Epson Corporation 0 P20 0 when being read. - - 1 when being read. 1 R/W (0xff) 0 Disable 1 Enable - R Remarks - x - 0 - 0 - 0 - 0 - R/W - R/W - R/W - R/W 0 when being read. - 0 - 0 - 0 - 0 - R/W - R/W - R/W - R/W 0 when being read. 0 R/W - 0 - 0 - 0 - 0 when being read. R/W - 0 when being read. R/W - 0 when being read. R/W - 0 0 - 0 when being read. R/W R/W 0 R/W 0 R/W - 0 - 0 - 0 - 0 - R/W - R/W - R/W - R/W 0 when being read. 0 when being read. 0 when being read. 0 when being read. 0 when being read. 0 when being read. 0 when being read. 0 when being read. 0 when being read. 0 when being read. S1C17003 TECHNICAL MANUAL Appendix A: I/O Register List 0x52a5-0x52a8 Register name Address 0x52a5 P2 Port Function Select (8 bits) Register (P2_PMUX) 0x52a6 P3 Port Function Select (8 bits) Register (P3_PMUX) 0x52a7 P3 Port Function Select (8 bits) Register (P3_PMUX) 0x52a8 P4 Port Function Select (8 bits) Register (P4_PMUX) P Port & Port MUX Bit Name Function D7-6 P27MUX [1:0] P27 port function select D5-1 - P24MUX D0 reserved P24 port function select D7-6 P33MUX [1:0] P33 port function select D5-4 P32MUX [1:0] P32 port function select D3-2 P31MUX [1:0] P31 port function select D1-0 P30MUX [1:0] P30 port function select D7-6 P37MUX [1:0] P37 port function select D5-4 P36MUX [1:0] P36 port function select D3-2 P35MUX [1:0] P35 port function select D1-0 P34MUX [1:0] P34 port function select D7 D6 D5 D4 D3 D2 D1 D0 - P43MUX - P42MUX - P41MUX - P40MUX reserved P43 port function select reserved P42 port function select reserved P41 port function select reserved P40 port function select S1C17003 TECHNICAL MANUAL Setting P27MUX[1:0] 0x3 0x2 0x1 0x0 Port Reserved Reserved SOUT1 P27 - 1 Reserved 0 P24 Init. R/W R/W - 0 - 0 when being read. R/W P33MUX[1:0] 0x3 0x2 0x1 0x0 P32MUX[1:0] 0x3 0x2 0x1 0x0 P31MUX[1:0] 0x3 0x2 0x1 0x0 P30MUX[1:0] 0x3 0x2 0x1 0x0 Port Reserved SCL0 SCL1 P33 Port Reserved Reserved SDA0 P32 Port Reserved Reserved SCL0 P31 Port Reserved Reserved SIN1 P30 0 R/W 0 R/W 0 R/W 0 R/W P37MUX[1:0] 0x3 0x2 0x1 0x0 P36MUX[1:0] 0x3 0x2 0x1 0x0 P35MUX[1:0] 0x3 0x2 0x1 0x0 P34MUX[1:0] 0x3 0x2 0x1 0x0 Port TOUT4 Reserved TOUTN3 P37 Port Reserved Reserved TOUT3 P36 Port Reserved #BFR FOUT1 P35 Port Reserved SDA0 SDA1 P34 0 R/W 0 R/W 0 R/W 0 R/W - 0 - 0 - 0 - 0 - R/W - R/W - R/W - R/W - 1 P43 0 DCLK - 1 P42 0 DST2 - 1 P41 0 DSI0 - 1 FOUTH Seiko Epson Corporation 0 P40 Remarks 0 0 when being read. 0 when being read. 0 when being read. 0 when being read. AP-25 Appendix A: I/O Register List 0x5300-0x530c Register name Address PWM & Capture Timer Setting Init. R/W PWM Timer Compare Data A Register (T16E_CA) 0x5300 (16 bits) D15-0 T16ECA[15:0] Compare data A T16ECA15 = MSB T16ECA0 = LSB 0x0 to 0xffff 0x0 R/W PWM Timer Compare Data B Register (T16E_CB) 0x5302 (16 bits) D15-0 T16ECB[15:0] Compare data B T16ECB15 = MSB T16ECB0 = LSB 0x0 to 0xffff 0x0 R/W PWM Timer Counter Data Register (T16E_TC) 0x5304 (16 bits) D15-0 T16ETC[15:0] Counter data T16ETC15 = MSB T16ETC0 = LSB 0x0 to 0xffff 0x0 R/W 0x5306 PWM Timer Control Register (16 bits) (T16E_CTL) 0x5308 PWM Timer Input Clock (16 bits) Select Register (T16E_CLK) PWM Timer Interrupt Mask Register (T16E_IMSK) 0x530a (16 bits) PWM Timer Interrupt Flag Register (T16E_IFLG) 0x530c (16 bits) AP-26 Bit D15-9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name - INITOL - SELFM CBUFEN INVOUT CLKSEL OUTEN T16ERST T16ERUN Function reserved Internal output level reserved Fine mode select Comparison buffer enable Inverse output Input clock select Clock output enable Timer reset Timer run/stop control D15-4 - reserved D3-0 T16EDF[3:0] Timer input clock select (Prescaler output clock) D15-2 - D1 D0 CBIE CAIE Compare B interrupt enable Compare A interrupt enable reserved Compare B interrupt flag CAIF Compare A interrupt flag 0 Low - 1 1 1 1 1 1 1 Fine mode Enable Invert External Enable Reset Run 0 0 0 0 0 0 0 Normal mode Disable Normal Internal Disable Ignored Stop - T16EDF[3:0] Clock 0xf reserved 0xe PCLK*1/16384 0xd PCLK*1/8192 0xc PCLK*1/4096 0xb PCLK*1/2048 0xa PCLK*1/1024 0x9 PCLK*1/512 0x8 PCLK*1/256 0x7 PCLK*1/128 0x6 PCLK*1/64 0x5 PCLK*1/32 0x4 PCLK*1/16 0x3 PCLK*1/8 0x2 PCLK*1/4 0x1 PCLK*1/2 0x0 PCLK*1/1 reserved D15-2 - CBIF D1 D0 - 1 High - 1 Enable 1 Enable 0 Disable 0 Disable - 1 Cause of interrupt occurred Seiko Epson Corporation 0 Cause of interrupt not occurred - 0 - 0 0 0 0 0 0 0 Remarks - 0 when being read. R/W - R/W R/W R/W R/W R/W W 0 when being read. R/W - - 0 when being read. 0x0 R/W - - 0 when being read. 0 0 R/W R/W - 0 - 0 when being read. R/W Reset by writing 1. 0 R/W S1C17003 TECHNICAL MANUAL Appendix A: I/O Register List 0x5320-0x532c Register name Address ROM Control Register (MISC_FL) 0x5320 (16 bits) OSC1 Peripheral 0x5322 Control Register (16 bits) (MISC_OSC1) MISC Protect Register (MISC_PROT) 0x5324 (16 bits) IRAM Size 0x5326 Select Register (16 bits) (MISC_IRAMSZ) MISC Registers Bit Name Function D15-3 - reserved D2-0 FLCYC[2:0] FLASHC read access cycle D15-1 - O1DBG D0 reserved OSC1 peripheral control in debug mode D15-0 PROT[15:0] MISC register write protect D15-9 D8 D7-2 D1-0 - reserved DBADR Debug base address select - reserved IRAMSZ[1:0] IRAM size select Setting - FLCYC[2:0] 0x7-0x5 0x4 0x3 0x2 0x1 0x0 Read cycle reserved 1 cycle 5 cycles 4 cycles 3 cycles 2 cycles - 1 Run 0 Stop Writing 0x96 removes the write protection of the MISC registers (0x5326-0x532a). Writing another value set the write protection. - 1 0x0 0 0xfffc00 - IRAMSZ[1:0] 0x3 0x2 0x1 0x0 Read cycle reserved reserved reserved reserved Init. R/W Remarks - - 0 when being read. 0x3 R/W - 0 - 0 when being read. R/W 0x0 R/W - - 0 when being read. 0 R/W - - 0 when being read. 0x2 R/W Vector Table Address Low Register (MISC_TTBRL) 0x5328 (16 bits) D15-8 TTBR[15:8] Vector table base address A[15:8] D7-0 TTBR[7:0] Vector table base address A[7:0] (fixed at 0) 0x0-0xff 0x0 0x80 R/W 0x0 R Vector Table Address High Register (MISC_TTBRH) 0x532a (16 bits) D15-8 - reserved D7-0 TTBR[23:16] Vector table base address A[23:16] - 0x0-0xff - - 0 when being read. 0x0 R/W PSR Register (MISC_PSR) 0x532c (16 bits) D15-8 D7-5 D4 D3 D2 D1 D0 - PSRIL[2:0] PSRIE PSRC PSRV PSRZ PSRN S1C17003 TECHNICAL MANUAL reserved PSR interrupt level (IL) bits PSR interrupt enable (IE) bit PSR carry (C) flag PSR overflow (V) flag PSR zero (Z) flag PSR negative (N) flag 1 1 1 1 1 - 0x0 to 0x7 1 (enable) 0 0 (disable) 1 (set) 0 0 (cleared) 1 (set) 0 0 (cleared) 1 (set) 0 0 (cleared) 1 (set) 0 0 (cleared) Seiko Epson Corporation - 0x0 0 0 0 0 0 - R R R R R R 0 when being read. AP-27 Appendix A: I/O Register List 0x5340-0x5346 Register name Address REMC Configuration Register (REMC_CFG) Remote Controller Bit Name Function 0x5340 D15-12 CGCLK[3:0] Carrier generator clock select (16 bits) (Prescaler output clock) D11-8 LCCLK[3:0] Length counter clock select (Prescaler output clock) D7-2 - REMMD D1 REMEN D0 REMC Carrier Length Setup Register (REMC_CAR) 1 Receive 1 Enable 0x5342 D15-14 - reserved (16 bits) D13-8 REMCL[5:0] L carrier length setup D7-6 - reserved D5-0 REMCH[5:0] H carrier length setup 0x5344 REMC Length Counter Register (16 bits) (REMC_LCNT) D15-8 REMLEN[7:0] Transmit/receive data length count (down counter) D7-1 - reserved REMDT Transmit/receive data 1 1 (H) D0 REMC Interrupt 0x5346 D15-11 - Control Register (16 bits) D10 REMFIF (REMC_INT) REMRIF D9 REMUIF D8 D7-3 - REMFIE D2 REMRIE D1 REMUIE D0 AP-28 reserved REMC mode select REMC enable Setting CGCLK[3:0] LCCLK[3:0] 0xf 0xe 0xd 0xc 0xb 0xa 0x9 0x8 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 reserved Falling edge interrupt flag Rising edge interrupt flag Underflow interrupt flag reserved Falling edge interrupt enable Rising edge interrupt enable Underflow interrupt enable Init. R/W Clock reserved PCLK*1/16384 PCLK*1/8192 PCLK*1/4096 PCLK*1/2048 PCLK*1/1024 PCLK*1/512 PCLK*1/256 0x0 R/W PCLK*1/128 PCLK*1/64 PCLK*1/32 PCLK*1/16 PCLK*1/8 PCLK*1/4 PCLK*1/2 PCLK*1/1 - - - 0 when being read. 0 Transmit 0 R/W 0 Disable 0 R/W - 0x0 to 0x3f - 0x0 to 0x3f - - 0 when being read. 0x0 R/W - - 0 when being read. 0x0 R/W 0x0 to 0xff 0x0 R/W - 0 0 (L) - 0 Cause of interrupt not occurred 1 Cause of interrupt occurred - 1 Enable 1 Enable 1 Enable Seiko Epson Corporation Remarks 0x0 R/W 0 Disable 0 Disable 0 Disable - 0 - 0 when being read. R/W - 0 0 0 - 0 0 0 - 0 when being read. R/W Reset by writing 1. R/W R/W - 0 when being read. R/W R/W R/W S1C17003 TECHNICAL MANUAL Appendix A: I/O Register List 0x5380-0x5386 Register name Address A/D Conversion 0x5380 Result Register (16 bits) (ADC10_ADD) A/D Trigger/ Channel Select (ADC10_TRG) ADC10SA Bit Name D15-0 ADD[15:0] 0x5382 D15-14 - reserved (16 bits) D13-11 ADCE[2:0] End channel selection D10-8 ADCS[2:0] Start channel selection STMD D7 Converted data store mode ADMS D6 D5-4 ADTS Conversion mode selection Conversion trigger selection - D3 D2-0 ADST[2:0] reserved Sampling clock count 0x5384 A/D Control/ D15 - Status Register (16 bits) D14-12 ADICH (ADC10_CTL) D11 - D10 ADIBS ADOWE D9 ADCF D8 D7-6 - ADOIE D5 ADCIE D4 D3-2 - ADCTL D1 ADEN D0 A/D divided frequency Register (ADC_DIV) Function 0x5386 (16 bits) D15-4 - D3-0 ADDF[3:0] S1C17003 TECHNICAL MANUAL Setting Remarks 0 - 0x0-0x7 0x0-0x7 1 {AD[9:0], 0 { 6'b0, 6'b0} AD[9:0]} 1 continuous 0 Single ADTS[2:0] trigger #ADTRG pin 0x3 reserved 0x2 16bit timer 0x1 software 0x0 - ADST[2:0] count clock 9clocks 0x7 8clocks 0x6 7clocks 0x5 6clocks 0x4 5clocks 0x3 4clocks 0x2 3clocks 0x1 2clocks 0x0 - 0 0 0 - 0 when being read. R/W R/W R/W 0 0 R/W R/W reserved - Internal conversion channel status 0x0-0x7 reserved - Internal busy status 1 busy 0 idle Overwrite error flag 1 Error 0 Normal Conversion-complete flag 1 Completed 0 Not completed reserved - Overwrite interrupt enable 1 Enable 0 Disable 1 Enable 0 Disable Conversion-complete interrupt enable reserved - conversion control 1 Start/Run 0 Stop A/D enable 1 Enable 0 Disable reserved A/D converter clock divided frequency select Init. R/W 0-1023 A/D converted data @STMD=0 ADD[15:10]=6'b0,ADD9=MSB, ADD0=LSB @STMD=1 ADD15=MSB,ADD6=LSB, ADD[5:0]=6'b0 - ADDF[3:0] 0xf 0xe 0xd 0xc 0xb 0xa 0x9 0x8 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 Seiko Epson Corporation clock Reserved PCLK1/32768 PCLK1/16384 PCLK1/8192 PCLK1/4096 PCLK1/2048 PCLK1/1024 PCLK1/512 PCLK1/256 PCLK1/128 PCLK1/64 PCLK1/32 PCLK1/16 PCLK1/8 PCLK1/4 PCLK1/2 R - - 0 when being read. 0x7 R/W Must set 0x7 - 0 - 0 0 0 - R - R R/W R 0 when being read. - 0 0 - R/W R/W - 0 0 - 0 when being read. R/W Stop by writing 0 R/W - 0 - 0 when being read. R/W 0 when being read. Reset by writing 1 Reset when ADC10_ADD is read. 0 when being read. AP-29 Appendix A: I/O Register List 0xffff84-0xffffd0 Register name Address S1C17 Core I/O Bit Name Setting Init. R/W Remarks 0xffff84 (8 bits) Debug RAM Base Register (DBRAM) 0xffff90 D31-24 - Unused (fixed at 0) (32 bits) D23-0 DBRAM[23:0] Debug RAM base address Debug Control Register (DCR) 0xffffa0 (8 bits) Instruction Break Address Register 2 (IBAR2) 0xffffb8 D31-24 - reserved (32 bits) D23-0 IBAR2[23:0] Instruction break address #2 IBAR223 = MSB IBAR20 = LSB - 0x0 to 0xffffff - - 0 when being read. 0x0 R/W Instruction Break Address Register 3 (IBAR3) 0xffffbc D31-24 - reserved (32 bits) D23-0 IBAR3[23:0] Instruction break address #3 IBAR323 = MSB IBAR30 = LSB - 0x0 to 0xffffff - - 0 when being read. 0x0 R/W Instruction Break Address Register 4 (IBAR4) 0xffffd0 D31-24 - reserved (32 bits) D23-0 IBAR4[23:0] Instruction break address #4 IBAR423 = MSB IBAR40 = LSB - 0x0 to 0xffffff - - 0 when being read. 0x0 R/W AP-30 D7-0 IDIR[7:0] Function Processor ID Register (IDIR) D7 D6 D5 D4 D3 D2 D1 D0 IBE4 IBE3 IBE2 DR IBE1 IBE0 SE DM Processor ID 0x10: S1C17 Core Instruction break #4 enable Instruction break #3 enable Instruction break #2 enable Debug request flag Instruction break #1 enable Instruction break #0 enable Single step enable Debug mode 1 1 1 1 1 1 1 1 0x10 0x10 R 0x0 0x0fc0 0x0 0x0fc0 R R Enable Enable Enable Occurred Enable Enable Enable Debug mode Seiko Epson Corporation 0 0 0 0 0 0 0 0 Disable Disable Disable Not occurred Disable Disable Disable User mode 0 0 0 0 0 0 0 0 R/W R/W R/W R/W Reset by writing 1. R/W R/W R/W R S1C17003 TECHNICAL MANUAL Appendix B: Power Saving Appendix B: Power Saving Current consumption will vary dramatically, depending on CPU operating mode, operation clock frequency, and the peripheral circuits being operated. Listed below are the control methods for saving power. B.1 Clock Control Power Saving Figure B.1.1 illustrates the S1C17003 clock system. OSC CLG Clock source selection System HSCLK clock OSC3 OSC4 FOUTH OSC3 oscillator circuit 20MHz FOUT1 RESET NMI Clock gear (1/1 to 1/8) OSC3 HALT Gate CCLK S1C17 core Gate BCLK Internal bus, RAM, ROM OSC1 Wait circuit for wakeup SLEEP, on/off control FOUTH Division circuit output circuit (1/1 to 1/4) On/off control SLEEP, on/off control OSC1 OSC2 wakeup Gear selection HALT On/off control Gate Division ratio selection PCLK OSC1 oscillator circuit T16, T8F, UART, SPI, I2C(master), T16E, P, MISC, REMC, ADC, I2C(slave) PSC On/off control FOUT1 output circuit Division circuit (1/1 to 1/16K) Gate On/off control Noise filter S1C17 core On/off control Noise filter S1C17 core On/off control OSC1 Division circuit CLK_256Hz CT, SWT, WDT (1/128) (1/1 to 1/32) T8F, T16, T16E, REMC, P, UART, SPI, I2C(master), ADC Gate T8OSC1 Division ratio selection On/off control Figure B.1.1 Clock system S1C17003 TECHNICAL MANUAL Seiko Epson Corporation AP-31 Appendix B: Power Saving This section describes clock systems that can be controlled via software and power-saving control details. For more information on control registers and control methods, refer to the respective module sections. System SLEEP (All clocks stopped) * Execute slp instruction Execute the slp instruction when the entire system can be stopped. The CPU switches to SLEEP mode and the system clocks stop. This also stops all peripheral circuits using clocks. Starting up the CPU from SLEEP mode is therefore limited to startup using ports (described later). System clocks * Clock source selection (OSC module) Select between OSC3 and OSC1 for the system clock source. Reduce current consumption by selecting the OSC1 clock when low-speed processing is possible. * OSC3 oscillation circuit stop (OSC module) You can reduce current consumption by using OSC1 as the system clock and stopping the OSC3 oscillation circuit. CPU clock (CCLK) * Execute the halt instruction Execute the halt instruction when program execution by the CPU is not required--for example, when only the display is required or for interrupt standby. The CPU switches to HALT mode and suspends operations, but the peripheral circuits maintain the status in place at the time of the halt instruction, enabling use of peripheral circuits for timers and interrupts. You can reduce power consumption even further by suspending unnecessary peripheral circuits before executing the halt instruction. The CPU is started from HALT mode using the port or interrupts from the peripheral circuit operating in HALT mode. * Low-speed clock gear selection (CLG module) The CLG module can reduce CPU clock speeds to between 1/1 and 1/8 of the system clock via the clock gear settings. Reduce current consumption by operating the CPU at the minimum speed required for applications. Peripheral clock (PCLK) * PCLK stop (CLG module) Stop the PCLK clock feed from the CLG to peripheral circuits if none of the following peripheral circuits is required. Peripheral circuits operating with PCLK * Prescaler (PWM & capture timer, remote controller, P port) * UART * 8-bit timer * 16-bit timer Ch.0 to Ch.2 * SPI * I2C (master/slave) * P port and port MUX (control register, chattering filter) * PWM & capture timer * MISC register * Remote controller * A/D converter AP-32 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL Appendix B: Power Saving The peripheral modules listed below are operated by clocks other than PCLK, except for control register access. This means PCLK is not required after the control register has been set and operation started. * Clock timer * Stopwatch timer * Watchdog timer * 8-bit OSC1 timer Table B.1.1 shows a list of methods for clock control and starting/stopping the CPU. Table B.1.1: Clock control list Current consumption Low OSC1 OSC3 CPU (CCLK) PCLK peripheral OSC1 peripheral Stop Stop Stop Stop Stop Stop Stop Stop Operation Stop Stop Operation Operation Stop Operation(1/1) Operation Operation Stop Operation Operation Operation (Low gear) Operation Operation Operation(1/1) Operation Operation Oscillation (system CLK) Oscillation (system CLK) Oscillation (system CLK) Oscillation Oscillation High Oscillation Oscillation (system CLK) Oscillation (system CLK) Oscillation (system CLK) CPU stop method Execute slp instruction Execute halt instruction Execute halt instruction Execute halt instruction CPU startup method 1 1, 2 1, 2, 3 1, 2, 3 HALT and SLEEP mode cancellation methods (CPU startup method) 1. Startup by port Started up by input/output port interrupt and debug interrupt (ICD forced break). 2. Startup by OSC1 peripheral circuit Started up by clock timer, stopwatch timer, watchdog timer, or 8-bit OSC1 timer interrupts. 3. Startup by PCLK peripheral circuit Started up by PCLK peripheral circuit interrupt. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation AP-33 Appendix C: Mounting Precautions Appendix C: Mounting Precautions This section describes various precautions for circuit board design and IC mounting. Oscillator circuit * Oscillation characteristics depend on factors such as components used (oscillator, Rf, CG, CD) and circuit board patterns. In particular, with ceramic or crystal oscillators, select the appropriate external resistors (Rf,) and capacitors (CG, CD) only after fully evaluating components actually mounted on the circuit board. * Oscillator clock disturbances caused by noise may cause malfunctions. To prevent such disturbances, consider the following points. The latest devices, in particular, are manufactured by microscopic processes, making them especially susceptible to noise. Areas in which noise countermeasures are especially important include the OSC2 pin and related circuit components and wiring. OSC1 pin handling is equally important. The noise precautions required for the OSC1 and OSC2 pins are described below. We also recommend applying similar noise countermeasures to high-speed oscillator circuits, such as the OSC3 and OSC4 pins and wiring. (1) Components such as oscillators, resistors, and capacitors connected to the OSC1 (OSC3) and OSC2 (OSC4) pins should have the shortest connections possible. (2) Wherever possible, avoid locating digital signal lines within 3 mm of the OSC1 (OSC3) and OSC2 (OSC4) pins or related circuit components and wiring. Rapidly-switching signals, in particular, should be kept at a distance from these components. Since the spacing between layers of multi-layer printed circuit boards is a mere 0.1 mm to 0.2 mm, the above precautions also apply when positioning digital signal lines on other layers. Never place digital signal lines alongside such components or wiring, even if more than 3 mm distance or located on other layers. Avoid crossing wires. (3) Use VSS to shield OSC1 (OSC3) and OSC2 (OSC4) pins and related wiring (including wiring for adjacent circuit board layers). Layers wired should be adequately shielded as shown to the right. Fully ground adjacent layers, where possible. At minimum, shield the area at least 5 mm around the above pins and wiring. Even after implementing these precautions, avoid configuring digital signal lines in parallel, as described in (2) above. Avoid crossing even on discrete layers, except for lines carrying signals with low switching frequencies. VSS pattern example (OSC3) OSC4 OSC3 VSS (4) After implementing these precautions, check the output clock waveform by running the actual application program within the product. Use an oscilloscope to check outputs from the FOUT1 and FOUTH pins. You can check the quality of the OSC3 output waveform via the FOUTH output. Confirm that the frequency is as designed, is free of noise, and has minimal jitter. You can check the quality of the OSC1 waveform via the FOUT1 output. In particular, enlarge the areas before and after the clock rising and falling edges and take special care to confirm that the regions approximately 100 ns to either side are free of clock or spiking noise. Failure to observe precautions (1) to (3) adequately may lead to jitter in the OSC3 output and noise in the OSC1 output. Jitter in the OSC3 output will reduce operating frequencies, while noise in the OSC1 output will destabilize timers operated by the OSC1 clock as well as CPU core operations when the system clock switches to OSC1. AP-34 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL Appendix C: Mounting Precautions Reset circuit * The reset signal input to the #RESET pin when power is turned on will vary, depending on various factors, such as power supply start-up time, components used, and circuit board patterns. Constants such as capacitance and resistance should be determined through thorough testing with real-world products. Account for resistance fluctuations when setting the #RESET pin pull-up resistance for constants settings. * Components such as capacitors and resistors connected to the #RESET pin should have the shortest connections possible to prevent noise-induced resets. Power supply circuit Sudden power supply fluctuations due to noise will cause malfunctions. Consider the following issues. (1) Connections from the power supply to the VDD and VSS pins should be implemented via the shortest, thickest patterns possible. (2) If a bypass capacitor is connected between VDD and VSS, connections between the VDD and VSS pins should be as short as possible. Bypass capacitor connection example VDD VDD VSS VSS Signal line location * To prevent electromagnetically-induced noise arising from mutual induction large-current signal lines should not be positioned close to circuits susceptible to noise, such as oscillators. * Locating signal lines in parallel over significant distances or crossing signal lines operating at high speed will cause malfunctions due to noise generated by mutual interference. Specifically, avoid positioning crossing signal lines operating at high speed close to circuits susceptible to noise, such as oscillators. Example of configuration to avoid OSC1, OSC3 OSC2, OSC4 VSS Large-current signal line High-speed operation signal line S1C17003 TECHNICAL MANUAL Seiko Epson Corporation AP-35 Appendix C: Mounting Precautions Noise-induced malfunctions Check the following three points if you suspect the presence of noise-induced IC malfunctions. (1) DSIO pin Low-level noise to this pin will cause a switch to Debug mode. The switch to Debug mode can be confirmed by the clock output from DCLK and a High signal from the DST2 pin. For the product version, we recommend connecting the DSIO pin directly to HVDD or pulling up the DISO pin using a resistor not exceeding 10 k. The IC includes an internal pull-up resistor. The resistor has a relatively high impedance of 50 k to 100 k and is not noise-resistant. (2) #RESET pin Low-level noise to this pin will reset the IC. Depending on the input waveform, the reset may not proceed correctly. This is more likely to occur if, due to circuit design choices, the impedance is high when the reset input is High. (3) VDD and VSS power supply The IC will malfunction the instant noise falling below the rated voltage is input. Incorporate countermeasures on the circuit board, including close patterns for circuit board power supply circuits, noise-filtering decoupling capacitors, and surge/noise prevention components on the power supply line. Perform the inspections described above using an oscilloscope capable of observing waveforms of at least 200 MHz. It may not be possible to observe high-speed noise events with a low-speed oscilloscope. If you detect potential noise-induced malfunctions while observing the waveform with an oscilloscope, recheck with a low-impedance (less than 1 k) resistor connecting the relevant pin to GND or to the power supply. Malfunctions at that pin are likely if changes are visible, such as the malfunction disappearing, becoming less frequent, or the phenomena changing. The DSIO and #RESET input circuits described above detect input signal edges and are susceptible to malfunctions induced by spike noise. This makes these digital signal pins the most susceptible to noise. To reduce potential noise, keep the following two points in mind when designing circuit boards: (A) It is important to use low impedance resistors when driving the signals, as described above. Avoid connecting impedance exceeding 1 k (ideally, 0 ) to the power supply or GND. The signal lines connected should be no longer than approximately 5 cm. (B) Signals switching from 1 to 0 or 0 to 1 may generate noise if signal lines run parallel to other digital lines on the circuit board. The highest risk of noise occurs in configurations in which a line is sandwiched between multiple signal lines that vary in synchrony. You can minimize noise effects by reducing the length of parallel sections (limit to a few cm) or by increasing the separation (to at least 2 mm). AP-36 Seiko Epson Corporation S1C17003 TECHNICAL MANUAL Appendix C: Mounting Precautions Handling of light (for bare chip mounting) The characteristics of semiconductor components can vary when exposed to light. ICs may malfunction or nonvolatile memory data may be corrupted if ICs are exposed to light. Consider the following precautions for circuit boards and products in which this IC is mounted to prevent IC malfunctions attributable to light exposure. (1) Design and mount the product so that the IC is shielded from light during use. (2) Shield the IC from light during inspection processes. (3) Shield the IC on the upper, underside, and side faces of the IC chip. (4) Mount the IC chip within one week of opening the package. If the IC chip must be stored before mounting, take measures to ensure light shielding. (5) Adequate evaluations are required to assess nonvolatile memory data retention characteristics before product delivery if the product is subjected to heat stress exceeding regular reflow conditions during mounting processes. Miscellaneous This product series is manufactured using 0.18 m microscopic processes. Although it is designed to ensure basic IC reliability meeting EIAJ and MIL standards, consider the following points when mounting the product. All oscillator circuit input/output pins use direct connections to internal 0.18 m transistors. In addition to physical damage during mounting, minor variations over time may result in electrical damage arising from disturbances in the form of voltages exceeding the absolute maximum rating (2.5 V). The following factors can give rise to these variations: (1) electromagnetically-induced noise from industrial power supplies used in mounting reflow, reworking after mounting, and individual characteristic evaluation (testing) processes; (2) electromagnetically-induced noise from a solder iron when soldering. In particular, during soldering, take care to ensure that the soldering iron GND (tip potential) has the same potential as the IC GND. S1C17003 TECHNICAL MANUAL Seiko Epson Corporation AP-37 Appendix D: Developing S1C17003 Mask ROM Code Appendix D: Developing S1C17003 Mask ROM Code (1) Use the S1C17602 Flash microcomputer to develop mask ROM code for the S1C17003. (2) The ROM data file format to submit to SEIKO EPSON should be "file.PAn" (output from winmdc). Before submitting the file, perform final verification of the user ROM data using "file.psa" (output from sconv32). (3) Specify the following values as the arguments for the S1C17003 when moto2ff is executed. * Data start address = 0x8000 * Data block size = 512 x 16 bits (4) Take the differences listed in the table below into consideration and perform operation check using the S1C17602. Memory Clock Co-processor Peripheral circuit Circuit/function Boot address Flash Mask ROM IRAM Display RAM Maximum operating frequency IOSC oscillator circuit OSC3 oscillator circuit OSC1 oscillator circuit Product-sum operation Divider S1C17602 0x8000 64KB - 4KB 40B 8.2MHz Internal oscillator Crystal/Ceramic/External input Crystal/External input 16bitx16bit+32bit(1cycle) 16bit/16bit(20cycle) 36 (With Hi-z mode and input Schmitt switching) I/O port Input port - 1ch 1ch 2ch 1ch 2ch 3ch 1ch 1ch 1ch 1ch 1ch 36x8 / 40x4 10bitx8ch (1.5LSB) 2ch Power supply SPI(master / slave) I2C(master / slave) UART(with IrDA1.0) Infrared rays remote controller (REMC) 8-bit timer with the fine mode (T8F) 16-bit timer (T16) PWM timer & Capture timer (T16E) Clock timer(CT) Stopwatch timer (SWT) 8-bit OSC1 timer (T8OSC1) Watchdog timer (WDT) LCD driver A/D converter R/F converter Power supply voltage detection (SVD) circuit Power supply voltage Temperature Configuration Operating temperatures Package AP-38 1.8 to 3.2V detect VDD=1.8V to 3.6V (in normal operation) VDD=2.7V to 3.6V (while writing to flash ROM) (Regulator is built-in) -20 to 70C TQFP14-100 VFBGA7H-144 Bare chip 100m pitch Seiko Epson Corporation S1C17003 - 64KB - 20MHz - 30 (Without Hi-z mode, and with fixed Input Schmitt) 4 (Interface level AVDD) - 10bitx4ch - - (3LSB) HVDD(I/O)=1.65V to 3.6V LVDD(core)=1.65V to 1.95V AVDD(Analog)=2.7V to 3.6V -40 to 85C TQFP12-64 WCSP 48pin Bare chip 100m pitch S1C17003 TECHNICAL MANUAL REVISION HISTORY Revision History Code No. 411635101 411635102 Page Contents New anactment Figure 1.2.1 modified. Opening of Pad and Chip thickness added Description modified. Branch ipa.djpa.d 3-4 0x5326 Register table and Table 3.3.1.1 modified. Descriptions added. * Please do not change the setting of IRAMSZ[2:0]/MISC_IRAMSZ Register from a default value. 6-15 Descriptions modified. Set the UART Ch.1 or I2C (slave) interrupt level (0 to 7). (Default: 0) 7-1, 8-1, AP- Delete ITC from the block that connect to PCLK 31 7-2 Descriptions added. For information about input clock waveforms, refer to "26 Electrical Characteristics." 7-6, 7-7 Figure 7.7.2 and Figure 7.7.3 modified. 8-3, 8-5, 8-7, Description deleted. AP-32 * Interrupt controller 18-6 Descriptions modified. (2)RDRY = 1, RD2B = 0...of the receive data buffer must be read out before an overrun error occurs. 18-7 Descriptions modified. After a data transfer is completed (both transmission and reception), data transfers are blocked by writing 0 to the RXEN bit. 18-8 Descriptions modified. However, if the receive data buffer is not emptied...by the time this data has been received, the third data received in the shift register will not be sent to the buffer and generate an overrun error. 18-14 Descriptions modified. FER is reset by writing 1. PER is reset by writing 1. OER is reset by writing 1. 18-19 Descriptions modified. Preventing transfers by writing 0 to RXEN also clears transmit data buffer. 18-21 Descriptions modified. RBFI bit in the UART_CTLx register Preventing transfer by setting RXEN to 0 clears (initializes) transfer data buffers. Before writing 0 to RXEN, confirm the absence of data in the buffers awaiting transmission. 19-3 Descriptions modified. The Master mode SPI uses the internal clock output by the 16-bit timer Ch.1 as the SPI clock. Figure 19.3.1 modified. Figure 19.3.2 deleted. Description deleted. Since the internal circuit operates in sync with the PCLK clock, the input clock is used to synchronize the differentiated PCLK clock. Descriptions modified. Note: The duty ratio of the clock input via the SPICLK pin must be 50%. 19-4, 19-5 Descriptions added. Note: When the SPI module is used in master...second and following bytes during continuous transfer. Figure 19.4.2 added. 19-6, 19-7 Figure 19.5.1 and Figure 19.5.2 deleted. Figure 19.5.1 added. 19-7 Descriptions modified. After a data transfer is completed ...guaranteed if SPEN is set to 0 while data is being sent or received. 19-8 Descriptions modified. If SPTBE is 0,If SPTBE is 1, 19-11 Descriptions added. Note: Make sure that SPEN is set to 1 before...SPI_TXD register to start data transmission/reception. 20-3 Descriptions added. If the I2C master module communicates with a slave device which has clock stretching, Transfer rates are limited up to 50 kbits/s in the Standard-mode, up to 200 kbits in the Fast-mode. 20-6, 20-7, Descriptions modified. 20-15 NACKNAK 20-6 Figure 20.5.2 modified. 20-7 Descriptions modified. The data is shifted into the shift register with the clock pulses, ....RXE is reset to 0 when D7 is loaded. All 1-3 1-6 2-5 REVISION HISTORY 20-8 Descriptions modified. When transmission or reception ends, TBUSY or RBUSY is cleared. Then, after a ....clock cycle set. Descriptions modified. Disabling data transfer ...the I2C bus is in busy status, the SCL0 and SDA0 output levels and transfer data at that point cannot be guaranteed. 20-9 Figure 20.5.6, Figure 20.5.7 and Figure 20.5.8 modified. 20-10 Figure 20.5.9 modified. Descriptions modified. Transmit buffer empty interrupt occurs when the data was only sent....NOTE: When I2CM interrupt occurs, decide the transmit buffer empty interrupt or the receive buffer full interrupt by the program sequence of the I2C master. There're not registers to decide which interrupt occurred. 20-13 Descriptions added. Setting the STP bit 1 makes the I2C master module...the 1/4 cycle of I2C clock, STP can set to 1. 21-1 Figure 21.1.1 modified. 21-2 Descriptions modified. I2C slave clock input/output pin...SCL line status and outputs low level to the I2C bus when clock stretch. 21-4 Descriptions modified. (one system clock (PCLK) cycle is required. Two PCLK cycles or more pulse width is recommended) Descriptions added. Note: When I2C slave module is slave transceiver mode,...depends on the PCLK frequency. 21-6 Descriptions modified. STOP condition detection clears BUSY. STOP or Repeated START condition detection clears SELECTED. 21-7 Descriptions added. When the asynchronous address detection function is used, the data written before ASDET_EN is reset in 0 becomes invalid. Therefore, the transmission data must be written, after TXEMP has been set to 1. 21-8 Descriptions added. Note: If the I2CS module has sent back a NAK as the response ...The I2CS module is placed into transfer standby state and OSC1 is used as the operating clock (PCLK). 21-10, 21-11 Figure 21.5.5, Figure 21.5.6, Figure 21.5.7 and Figure 21.5.8 modified. 21-12 Descriptions modified. DA_STOP: set to 1 if a stop condition or a repeated start condition is detected while this module is selected as the slave device 21-22 Descriptions modified. Indicates that a stop condition or a repeated start condition is detected...At the same time, it initializes the I2C communication process. 21-23 Descriptions modified. After SELECTED is set to 1, it is reset to 0 when a STOP condition or a Repeated START condition is detected. 23-5 Descriptions modified. Low levelnegative edge 23-16 Descriptions modified. When ADEN is 0, a trigger is not accepted. 23-18 Description deleted. Moreover, set back the input to #ADTRG terminal to High with less than 20 cycles of set input clock so that it will not be detected as next A/D conversion trigger. 26-6 26.9 External Clock Input Characteristics added. International Sales Operations AMERICA ASIA EPSON ELECTRONICS AMERICA, INC. EPSON (CHINA) CO., LTD. 2580 Orchard Parkway, San Jose, CA 95131, USA Phone: +1-800-228-3964 7F, Jinbao Bldg., No.89 Jinbao St., Dongcheng District, Beijing 100005, CHINA Phone: +86-10-8522-1199 Fax: +86-10-8522-1125 Fax: +1-408-922-0238 EUROPE EPSON EUROPE ELECTRONICS GmbH Riesstrasse 15, 80992 Munich, GERMANY Phone: +49-89-14005-0 Fax: +49-89-14005-110 SHANGHAI BRANCH 7F, Block B, Hi-Tech Bldg., 900 Yishan Road, Shanghai 200233, CHINA Phone: +86-21-5423-5577 Fax: +86-21-5423-4677 SHENZHEN BRANCH 12F, Dawning Mansion, Keji South 12th Road, Hi-Tech Park, Shenzhen 518057, CHINA Phone: +86-755-2699-3828 Fax: +86-755-2699-3838 EPSON HONG KONG LTD. Unit 715-723, 7/F Trade Square, 681 Cheung Sha Wan Road, Kowloon, Hong Kong. Phone: +852-2585-4600 Fax: +852-2827-4346 EPSON TAIWAN TECHNOLOGY & TRADING LTD. 14F, No. 7, Song Ren Road, Taipei 110, TAIWAN Phone: +886-2-8786-6688 Fax: +886-2-8786-6660 EPSON SINGAPORE PTE., LTD. 1 HarbourFront Place, #03-02 HarbourFront Tower One, Singapore 098633 Phone: +65-6586-5500 Fax: +65-6271-3182 SEIKO EPSON CORP. KOREA OFFICE 5F, KLI 63 Bldg., 60 Yoido-dong, Youngdeungpo-Ku, Seoul 150-763, KOREA Phone: +82-2-784-6027 Fax: +82-2-767-3677 SEIKO EPSON CORP. MICRODEVICES OPERATIONS DIVISION Device Sales & Marketing Dept. 421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN Phone: +81-42-587-5814 Fax: +81-42-587-5117 Document Code: 411635102 First Issue January 2009 Revised April 2011 H