151
TM
March 1997
HM-6514/883
1024 x 4 CMOS RAM
Features
• This Circuit is Processed in Accordance to MIL-STD-
883 and is Fully Conformant Under the Provi sions of
Paragraph 1.2.1.
• Low Power Standby. . . . . . . . . . . . . . . . . . . 125µW M ax
• L o w Power O pe r a tio n . . . . . . . . . . . . . .35 mW / M H z Max
• Data Retention . . . . . . . . . . . . . . . . . . . . . . . at 2.0V Min
• TTL Compatible I nput/Output
• Common Data Input/Output
• Three-State Output
• Standard JEDEC Pinout
• Fast Access Time . . . . . . . . . . . . . . . . . 120/200ns Max
• 18 Pin Package for High Densi ty
• Gated Input s - No Pull Up or Pull Down Resistor s
Required
• On-Chip Address Register
Description
The HM-6514/883 is a 1024 x 4 static CMOS RAM fabri-
cated using self-aligned silicon gate technology. The device
utilizes synchronous circuitry to achieve high performance
and low power operation.
On chip latches are provided for addresses allowing efficient
interfacing with microprocessor systems. The data output
can be forced to a h igh impedance st ate for use in expanded
memory arr ays.
Gated inputs al low l ower o perating cur rent and also eliminates
the need for pull up or pull down resistors. The HM-6514/883 is
fully static RAM and may be maintained in any state for an
indefinite period of time.
Data ret enti on supply vol tage and suppl y curre nt are guaran -
teed over temperature.
Ordering Information
Pinout HM-6514/883
(CERDIP)
TOP VIEW
120n s 200n s 300n s TEMPERATURE RANGE PACKAG E PKG. NO.
HM1-6514S/883 HM1-6514B/883 HM1-6514/883 -55oC to 125oC CERDIP F18.3
PIN DESCRIPTION
A Address Input
EChip Enable
WWrite Enable
D Data Input
Q Data Ou tput
10
11
12
13
14
15
16
17
18
9
8
7
6
5
4
3
2
1VCC
A8
A9
DQ0
DQ1
DQ2
DQ3
A7
W
A6
A5
A4
A3
A0
A1
E
A2
GND
FN2996.1
CA UTION: The se devices are s ensi tiv e to el ectrosta tic di schar ge; follow proper IC H andling Procedures.
1-888-INTERSIL or 321-724-7143 |Intersil (and design) is a trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
152
Functional Dia gram
64
A
6
6
4
L
G
A
A9
A8
A7
A6
A5
A4
64 x 64
MATRIX
G
A2
A1
A0
A3
E
W
LATCHED
ADDRESS
REGISTER
A
4
4
A
L16 16 16 16
1 OF 4
DQ
LATCHED
ADDRESS
REGISTER
GATED
ROW
DECODER
LSB
LSB GATED
COLUMN
I/O SELECT
HM-6514/883
153
Absolute Maximum Ratings Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7.0V
Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC +0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Thermal Resistance θJA θJC
CERDIP Package . . . . . . . . . . . . . . . . 75oC/W 15oC/W
Maximum Storage Temperature Range . . . . . . . . .-65oC to +150oC
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . +175oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . +300oC
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6910 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only r ating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Ope rat i ng Condit io ns
Operating Voltage Range. . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Range. . . . . . . . . . . . . . . . -55oC to +125oC
Input Low Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to +0.8V
Input High Voltage. . . . . . . . . . . . . . . . . . . . . . . . VCC -2.0V to VCC
Input Rise and Fall Time. . . . . . . . . . . . . . . . . . . . . . . . . . 40ns Max
TABLE 1. HM-6514/88 3 DC ELECTRICAL PERFORMANCE SPECIFICATIONS
Device Guaranteed and 100% Tested
PARAMETER SYMBOL (NOTE 1)
CONDITIONS GROUP A
SUBGROUPS TEMPERATURE
LIMITS
UNITS MIN MAX
Output Low Voltage VOL VCC = 4.5V
IOL = 3.2mA 1, 2, 3 -55oC ≤ TA ≤ +125oC- 0.4 V
Output High Voltage VOH VCC = 4.5V
IOH = -1.0mA 1, 2, 3 -55oC ≤ TA ≤ +125oC2.4 - V
Input Leakage Current II VCC = 5.5V,
VI = GND or VCC 1, 2, 3 -55oC ≤ TA ≤ +125oC -1.0 +1.0 µA
Input/Output Leakage
Current IIOZ VCC = 5.5 V,
VIO = GND or VC C 1, 2, 3 -55oC ≤ TA ≤ +125oC -1.0 +1.0 µA
Data Retention Supply
Current ICCDR VCC = 2.0V,
E = VCC -0.3V,
IO = 0mA
1, 2, 3 -55oC ≤ TA ≤ +125oC- 25 µA
Operating Supply
Current ICCOP VCC = 5.5V, (Note 2)
E = 1MHz 1, 2, 3 -55oC ≤ TA ≤ +125oC- 7 mA
Standby Supply
Current ICCSB VCC = 5.5V,
E = VCC-0.3V,
IO = 0mA
1, 2, 3 -55oC ≤ TA ≤ +125oC- 50 µA
NOTES:
1. All voltag es referenced to de vice GND.
2. Typical derating 1.5mA/MHz increase in ICCOP.
HM-6514/883
154
TABLE 2. HM-6514/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS
Devi ce Guaranteed and 100% Tes te d
PARAMETER SYMBOL (NOT E S 1, 2)
CONDITIONS
GROUP
A SUB -
GROUPS TEMPERA-
TURE
LIMITS
UNITS
HM-6514S/883 HM-6514B/883 HM-6514/883
MIN MAX MIN MAX MIN MAX
Chip Enable
Acce ss Time (1) TELQV VCC = 4.5 an d
5.5V 9, 10, 11 -55oC ≤ TA
≤ +125oC-120-200-300ns
Address Access
Time (2) TA VQ V VC C = 4. 5 and
5.5V, Note 3 9, 10, 11 -55oC ≤ TA
≤ +125oC-120-220-320ns
Chip Enable
Pulse Negative
Width
(5) TELEH VCC = 4.5 and
5.5V 9, 10, 11 -55oC ≤ TA
≤ +125oC120 - 200 - 300 - ns
Chip Enable
Pulse Positi v e
Width
(6) TEHEL V CC = 4.5 an d
5.5V 9, 10, 11 -55oC ≤ TA
≤ +125oC50 - 90 - 120 - ns
Address Setup
Time (7) TA VEL VC C = 4. 5 and
5.5V 9, 10, 11 -55oC ≤ TA
≤ +125oC0-20-20-ns
Address Hold
Time (8) TE LA X VCC = 4.5 and
5.5V 9, 10, 11 -55oC ≤ TA
≤ +125oC40 - 50 - 50 - ns
Wri te Enab l e
Pulse Width (9) TWL WH VCC = 4. 5 and
5.5V 9, 10, 11 -55oC ≤ TA
≤ +125oC120 - 200 - 300 - ns
Wri te Enab l e
Pulse Setu p
Time
(10) TWLEH VC C = 4. 5 and
5.5V 9, 10, 11 -55oC ≤ TA
≤ +125oC120 - 200 - 300 - ns
Wri te Enab l e
Pulse Hold Time (11) TELWH VCC = 4. 5 and
5.5V 9, 10, 11 -55oC ≤ TA
≤ +125oC120 - 200 - 300 - ns
Data Setup Time (12) TDV WH VCC = 4.5 an d
5.5V 9, 10, 11 -55oC ≤ TA
≤ +125oC50 - 120 - 200 - ns
Data Hold Time (13) TWH DX VC C = 4. 5 and
5.5V 9, 10, 11 -55oC ≤ TA
≤ +125oC0-0-0-ns
Wri t e Data Delay
Time (14) TWLDV VC C = 4. 5 and
5.5V 9, 10, 11 -55oC ≤ TA
≤ +125oC70 - 80 - 100 - ns
Early Output
High-Z Time (15) TWLEL V CC = 4.5 and
5.5V 9, 10, 11 -55oC ≤ TA
≤ +125oC0-0-0-ns
Late Output
High-Z Time (16) TE HWH VCC = 4.5 and
5.5V 9, 10, 11 -55oC ≤ TA
≤ +125oC0-0-0-ns
Read or W ri t e
Cycle Time (17) TELEL VC C = 4. 5 and
5.5V 9, 10, 11 -55oC ≤ TA
≤ +125oC170 - 290 - 420 - ns
NOTES:
1. All voltages referenced to device GND.
2. Input pulse levels: 0.8V to VCC-2.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V; Output load: 1 TTL gate
equi valent , CL = 50pF (mi n) - for CL greater than 5 0pF , acce ss time is derated by 0.15ns per pF.
3. TAVQ V = TELQV + TAVEL.
HM-6514/883
155
TABLE 3. HM-6514/88 3 ELE CTRICAL PERFORMANCE SPECIFICATIONS
PARAMETER SYMBOL CONDITIONS NOTE TEMPERATURE
HM-6514/883
UNITS
LIMITS
MIN MAX
Input Capa cita nce CI VCC = Open, f = 1MHz, All
Measurements Referenced
to Device Ground
1T
A = +2 5oC-8pF
Input/Output
Capacitance CIO VCC = Open , f = 1MHz, All
Measurements Referenced
to Device Ground
1T
A = +2 5oC-10pF
Chip Enable Output
Disable Time TELQX VCC = 4.5 and 5.5V 1-55oC ≤ TA ≤
+125oC5-
Chip Enable Output
Disable Time TEHQZ VC C = 4.5 and 5.5V
HM-6514S/883 1-55oC ≤ TA ≤
+125oC-50ns
VC C = 4.5 and 5.5V
HM-6514B/883 1-55oC ≤ TA ≤
+125oC-80ns
VC C = 4.5 and 5.5V
HM-6514/883 1-55oC ≤ TA ≤
+125oC- 100 ns
High Level Output
Voltage VOH2 VCC = 4.5V, IO = -100µA1 -55oC ≤ TA ≤
+125oCVCC -0.4 - V
NOTES:
1. The parameter s listed in Tab le 3 are controlled via design, or process parameters are c haracte riz ed upon init ial design and after major
proces s and/or design changes.
TABLE 4. APPLICABLE SUBGROUPS
CONFORMANCE GROUPS METHOD SUBGROUPS
Initial Test 100%/5004 -
I nte r i m Tes t 100%/5 00 4 1, 7, 9
PDA 100%/5004 1
Final Test 100%/5004 2, 3, 8A, 8B, 10, 11
Group A Samples/5005 1, 2, 3, 7, 8A, 8B, 9, 10, 11
Groups C & D Samples/5005 1, 7, 9
HM-6514/883
156
Timing Waveforms
The address information is latched in the on-chip registers
on the fall ing edge of E (T = 0). Minimum ad dress se t up and
hold time requirements must be met. After the required hold
time, the addresses may change state without affecting
device operati on. During t ime (T = 1) t he output becomes
enabled b ut data is not vali d until duri ng time (T = 2). W must
remain high throughout the read cycle. After the output data
has been read, E may return high (T = 3). This will disable
the output buffer and all inputs, and ready the RAM for the
next me mo ry cycle (T = 4).
(8) (7) TAVEL
(6)
(4) TEHQZ HIGH Z
VALID DATA OUT
(6)
HIGH Z
TAVEL
(7)
-1
TIME
01 2345
REFERENCE
(2) TAVQV
(17) TELEL
TELAX
NEXT ADD
TEHEL
(2) TAVQY
TEHEL (5) TELEH
(1) TELQV
(3) TELQX
DQ
W
E
A
FIGURE 1. READ CYCLE
VALID ADD
TRUTH TABLE
TIME
REFERENCE
INPUTS DATA I/O
DQ FUNCTIONEW A
-1 H X X Z Memory Disabled
0 H V Z Cycle Begins, Addresses are Latched
1 L H X X Output Enabled
2 L H X V Output Valid
3 H X V Read Accomplished
4 H X X Z Prepa re for Next Cycle (Same as -1)
5 H V Z Cycl e Ends , Next Cycl e Begins (Sam e as 0)
HM-6514/883
157
Timing Waveforms (Continued)
The write cycle is initiated by the falling edge of E (T = 0),
which latches the address information in the on-chip regis-
ters. There are t w o basic types of writ e cycles, which diffe r i n
the control of the comm on data-in/ data-out bus.
Case 1: E fall s before W falls
The output buffers may become enabled (reading) if E falls
before W falls. W is used to disable (three-state) the outputs
so input data can be applied. TWLDV must be met to allow
the W signal time to disable the outputs before applying
input data. Also, at the end of the cycle the outputs may
become active if W rises before E. The RAM outputs and all
inputs will three-state after E rises (TEHQZ). In this type of
write cycle TWLEL and TEHWH may be ignor ed.
Case 2: E fall s equal to or after W falls, and E rise s befo re
or equal to W rising
This E and W control timing will guarantee that the data out-
puts will stay disabled throughout the cycle, thus simplifying
the data input timing. TWLEL and TEHWH must be met, but
TWLDV becomes meaningless and can be ignored. In this
cycle TDVWH and TWHDX become TDVEH and TEHDX. I n
other words, reference data setup and hold times to the E
rising edge.
If a series of consecutive write cycles are to be performed,
W may be held low unt il all desir ed locations have been wri t-
ten (an extensi on of Case 2).
TAVEL
TELWL
TEVEL
TELAX
TWHEH
HIGH ZHIGH Z
TWHDZ
-1
TIME
01 2345
REFERENCE
VALID ADD NEXT ADD
TELEL
TEHEL TELEH
TWLEH
TWLWH
TEHEL
TWLDV VALID DATA INPUT
TDVWH
TELWH
W
DQ
E
A
FIGURE 2. WRITE CYCLE
TRUTH TABLE
TIME
REFERENCE
INPUTS
DQ FUNCTIONEW A
-1 H X X Z Memory Disabled
0 X V Z Cycle Begins, Addresses are Latched
1 L L X Z Write Period Begins
2 L X V Data In is Written
3HXZWrite Completed
4 H X X Z Prepare for Next Cycle (Sam e as -1)
5 X V Z Cycle Ends, Ne xt Cycle Begins (Same as 0)
IF OBSERVE IGNORE
Case 1 E falls before W TWLDV TWLEL
Case 2 E falls after W and
E rises before W TWLEL
TEHWH TWLDV
TWHDX
HM-6514/883
158
Test Lo ad Circuit
NOTE:
1. Test head capacitance.
Burn-In Circuit
HM6514/883 CERDIP
NOTES:
All resistors 47kΩ ±5%.
F0 = 100kHz ±10%.
F1 = F0 ÷ 2, F2 = F1 ÷ 2, F3 = F2 ÷ 2 . . . F12 = F11 ÷ 2.
VCC = 5.5V ±0.5V.
VIH = 4.5V ±10%.
VIL = -0.2V to +0.4V.
C1 = 0.01µF Min.
DUT
1.5V IOLIOH +
-
(NOTE 1) CL
EQUIVALENT CIRCUIT
10
11
12
13
14
15
16
17
18
9
8
7
6
5
4
3
2
1A6
A5
A4
A3
A0
A1
A2
GND
VCC
A8
A9
DQ0
DQ1
DQ2
DQ3
A7
F9
F8
F7
F4
F3
F6
F5
F0
C1
VCC
F10
F11
F12
F2
F1
W
E
HM-6514/883
159
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Intersil Corporati on’s quali ty certifi cations can be viewed at www. int ersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsi diaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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Die Charact eris tics
DIE DIMENSIONS:
136 x 167 x 19 ±1mils
METALLIZATION:
Type: Si - Al
Thickness: 11kÅ ±2kÅ
GLASSIVATION:
Type: SiO2
Thickness: 8kÅ ± 1kÅ
WORST CASE CURRENT DENSITY:
1.79 x 105 A/cm2
LEAD TEMPERATURE (10s soldering):
300oC
Metallization Mask Layout
HM-6514/883
NOTE:
1. Pin numbers correspond to DIP Package only.
A5 A6 VCC A7
A8
A9
A0
A1
A2
EGND W DQ3
DQ2
DQ1
DQ0
A4
A3
HM-6514/883
