LFI98A/LF398A Ni AR LF198/LF398 TECHNOLOGY FEATURES Guaranteed 6yus Max. Acquisition Time m Guaranteed 0.005% Max. Gain Error = Guaranteed 1mV Max. Offset Voltage = Guaranteed 1mV Max. Hold Step m Very Low Feedthrough 86dB Min. High Input Impedance under All Conditions = Logic Inputs Compatible with All Logic Families APPLICATIONS # 12-Bit Data Acquisition Systems = Ramp Generators w Analog Switches @ Staircase Generators = Sample and Difference Circuits Precision Sample and Hold Amplifier DESCRIPTION The LF198 is a precision sample and hold amplifier which uses a combination of bipolar and junction FET transis- tors to provide precision, high speed, and long hold times. A typical offset voltage of 1mV and gain error of 0.002% allow this sample and hold amplifier to be used in 12-bit systems. Dynamic performance can be optimized by proper selection of the external hold capacitor. Acqui- sition times can be as low as 4ys for small capacitors while hold step and droop errors can be held below 0.1mV and 30yV/sec respectively when using larger capacitors. The LF198 is fixed at unity gain with 10'Q input im- pedance independent of sample / hold mode. The logic in- puts are high impedance differential to allow easy inter- facing to any logic family without ground loop problems. A separate offset adjust pin can be used to zero the offset voltage in either the sample or hold mode. Additionally, the hold capacitor can be driven with an external signal to provide precision level shifting or differencing opera- tion. The device will operate over a wide supply voltage range from + 5V to + 18V with very little change in per- formance, and key parameters are specified over this full supply range. The LF198A version offers tightened electrical specifica- tions for key parameters. Basic Sample and Hold ANALOG INPUT 5v_.p v-- Acquisition Time 1 Vin=OV TO +10V Tj=25C = a TIME (uSEC) 100 1000 0.001 0.01 1.0 HOLD CAPACITOR (x) ee 9-97LFI98A/LF398A LF198/LF398 ABSOLUTE MAXIMUM RATINGS PACKAGE/ORDER INFORMATION Input Voltage .............. Equal to Supply Voltage vP View Logic to Logic Reference Differential ORDER Voltage (Note 2)............0000. +30V, 30V PART NUMBER Output Short Circuit Duration ............. Indefinite Hold Capacitor Short Circuit Duration ......... 10 sec Lead Temperature (Soldering, 10 seconds)... .. 300C LFIS8AH Supply Voltage... 2.2... eee eee eee + 18V nat rae LF198H Power Dissipation (Package Limitation) LF398AH 0) (hs 500mW LF398H Operating Temperature Range PACKAGE LF198/LF198A .............. 55C to 125C METAL CAN LF398/LF398A .................. 0C to 70C Storage Temperature Range ....... 65C to 150C ou vf [adios LF398J8 wat 7 ae se eur [i on LF398AN8 fi Fe] oureur LF398N8 J8 PACKAGE HERMETIC OIP N8 PACKAGE PLASTIC DUAL IN LINE ELECTRICAL CHARACTERISTICS (note 3) LF198A LF398A PARAMETER CONDITIONS MIN TYP wax | MIN TP max | UNITS Input Offset Voltage (Note 6) 0.5 1 1 2 mV e 2 3 mV Input Bias Current (Note 6) 5 25 10 25 nA e 75 50 nA input Impedance 10 10% Q Gain Error Ri =10k 0.001 0.005 0.001 0.005 % e 0.01 0.01 % Feedthrough Attenuation Ratio Cy=0.01pF 86 96 86 96 dB at 1kHz Output Impedance HOLD Mode 0.5 1 0.5 1 Q e 4 6 a HOLD Step (Note 4) Cy=0.01pF, Voyr =0 0.25 1 0.25 #1 mv Supply Current (Note 6) T= 25C 4.5 5.5 4.5 6.5 mA Logic and Logic Reference Input 2 10 2 10 pA Current Leakage Current into Hold *HOLD Mode (Note 5) 10 100 10 100 pA Capacitor (Note 6) Acquisition Time to 0.1% AVout = 10V, Cp = 1000pF 4 6 4 6 ps Cy=0.01pF 16 25 16 25 uS Hold Capacitor Charging Current | Viy Voyr=2V 5 5 mA Supply Voltage Rejection Ratio Vour =0 90 110 90 110 dB Differential Logic Threshold 0.8 1.4 2.4 0.8 1.4 2.4 V 9-98LFI98A/LF398A LF198/LF398 ELECTRICAL CHARACTERISTICS (Note 3) LF198 LF398 UNITS PARAMETER CONDITIONS MIN TP MAX MIN 1vP MAX Input Offset Voltage (Note 6) 1 3 2 7 mV 5 10 mV Input Bias Current (Note 6) 5 25 10 50 nA 75 100 nA Input Impedance 10' 100 Q Gain Error Ry = 10k 0.002 0.005 0.004 0.01 % 0.02 0,02 % Feedthrough Attenuation Ratio Cy =0.01 nF 86 96 80 96 dB at 1kHz Output Impedance *HOLD Mode 0.5 2 0.5 4 Qo 4 6 Q *HOLD Step (Note 4) C,h=0.01nF, Voy7 =0 0.5 2.0 0.5 2.5 mV Supply Current (Note 6) Tj2= 25C 4.5 5.5 4.5 6.5 mA Logic and Logic Reference Inout 2 10 2 10 pA Current Leakage Current into Hold HOLD Mode (Note 5) 30 100 30 200 pA Capacitor (Note 6) Acquisition Time to 0.1% AVout = 10V, Cy = 1000pF 4 4 BS C,=0.01 pF 16 16 ps Hold Capacitor Charging Current | Vij Voyr=2V 5 5 mA Supply Voltage Rejection Ratio Vout =9 80 110 80 110 dB Differential Logic Threshold 0.8 1.4 2.4 0.8 1.4 2.4 V The @ denotes the specifications which apply over the full operating temperature range. Note 1: 1; max for the LF198/LF198A is 150C; Tj max for the LF398/LF398A is 100C. Note 2: The logic inputs are protected to + 30V differential as long as the voltage on both pins does not exceed the supply voltage. For proper opera- tion, however, both logic and logic reference pins must be at least 2V below the positive supply and one of these pins must be at least 3V above the negative supply. Note 3: Uniess otherwise noted, Vs = + 15V, T;=25C, 11.5V<Viys +11.5V, Cy =0.01pF, Ry = 10k@and unitis in sample mode. Logic ref- erence =OV and logic voltage = 2.5V. Note 4: The hold step is sensitive to stray capacitance coupling between in- put logic signals and the hold capacitor. 1pF, for instance, will create an ad- ditional 0.5mV step with a 5V logic swing and a 0.01pF hold capacitor. Magnitude of the hold step is inversely proportional to hold capacitor value. Note 5: Leakage current is measured at a junction temperature of 25C. The effects of junction temperature rise due to power dissipation or elevated ambient can be calculated by doubling the 25C value for each 11C in- crease in chip temperature. Leakage is guaranteed over full input signal range. Note 6: These parameters are guaranteed over a supply voltage range of + 5V to + 18V. LOGIC it REFERENCE T 4 | 5 output | | | 1500 15 wou AA CAPACITOR LY Wee 9-99LFI98A/LF398A LF198/LF398 TYPICAL PERFORMANCE CHARACTERISTICS Dynamic Sampling Error* Vt=aV-= Tj=25C Aperture Time* Vt=V-=15V AVours1 mv =10V 0 -50 -25 0 25 SO 75 100 125 150 JUNCTION TEMPERATURE (C) *See Definition of Terms Hold Step Vin= Tj=25C 100 HOLD STEP (mv) S z S ~~ 0.01 100pF = 1000pF = O.01 uF HOLD CAPACITOR 0.1.F LF Input Bias Current 25 20 at) 10 5 CURRENT (nA) -10 15 -50 -25 90 100 125 150 23 8660) (75 JUNCTION TEMPERATURE (C) 100 10 ERROR (mV) | = o 100 0.1 1 10 100 1000 INPUT SLEW RATE (V/mSEC) *See Definition of Terms Hold Step vs Input Voltage 8 Cy=0.01uF* 1.2 }Tj=25C 0.8 0.4 HOLD STEP (mW) o | va -1.2 1.6 -15 -10 -5 0 5 10 15 INPUT VOLTAGE (V) Amplitude of hold step scales inversely with hold capacitor value Capacitor Pin Leakage 100k 10k LEAKAGE (pA) x _ Qo o 10 1 ~50-25 @ 25 SO 75 100 125 150 JUNCTION TEMPERATURE (C) AV ar VA SEC) Hold Settling Time* V+ =V-=15V 1.8 101 1.6 14 z 1.2 ge 1 - 08 0.6 0.4 0.2 0 50 25 0 25 50 75 100 125 150 JUNCTION TEMPERATURE (C) *See Definition of Terms Hold Step vs Logic Slew Rate 3.5 uF 3.0 Ny 2.5 HOLD STEP (mv) = 4 ow o _ o 0.5 0.01 0.1 1.0 10 100 LOGIC SLEW RATE (V/,S) Output Droop Rate 109 10-2 10-3 10-4 100pF 1000pF == 0.01 pF 0.1yF 1aF HOLD CAPACITOR 9-100 OwenLFI98A/LF398A LF198/LF398 TYPICAL PERFORMANCE CHARACTERISTICS SOURCING CURRENT (mA) S o MP > GD & -50-25 0 2 50 75 100 JUNCTION TEMPERATURE (C) * Phase and Gain (Input to Output, Small Signal) 5 Che 0 Output Short Circuit Current Output Noise Gain Error 160 0.3 T Ty=25C 140 A, =10k2 _ 02 120 = a 2 0.1 = 100 = 2 S { mm] = 80 5 0 } u | 2 * 3 0.1 [Nr EEN 40 5 | Ss.ope~0.0007% z 20 0.2 0 0.3 125 150 10 100 1k 10k 100k -15 -10 -5 0 5 10 (15 FREQUENCY (Hz) OUTPUT VOLTAGE (V) Feedthrough Rejection Ratio Power Supply Rejection 130 ey 160 ie Vin=10Vp- +=V~ =15 rz eae [vour=av 120 Cy=1 Cy2 0.01 uF Cy=1 1 _ I. o wn GAININPUT TO OUTPUT (dB) n20.14F h= 1k 10k 100k 1M FREQUENCY (Hz) 110 ~ 100 a oe 80 REJECTION RATIO (dB) 8 REJECTION RATIO (dB) 8 70 40 {o) AW130 3SVHd LNdLNO OL LNdNt 20 10M 10 1002S tks 10k = 100k) M 100 1k 40k 100k 1M FREQUENCY (Hz) FREQUENCY (Hz) Ca Capacitor Dielectric Absorption Capacitor Dielectric Absorption 0.001 = 0.001 MEASURED 1ms AFTER START OF HOLD = 0.901 = 0.01 S 3 3 5 & 2 01 2 a1 <x <x 1.0 Tps 10ps SAMPLE TIME = 1.0 100s tms 10s ts 10us 100s = Ams 10ms SAMPLE TIME TIME IN HOLD MODE LY Withee 9-101LFI98A/LF398A LF198/LF398 TYPICAL PERFORMANCE CHARACTERISTICS Output Transient at Start of Hold Made ALL VALUES OF C;, LN ! VY 0.01% (1mv) SETTLING =0.8ps | smv |-\Y OUTPUT AMPLITUDE (mV) 0 02 04 06 08 10 12 1.4 16 TIME (xs) APPLICATIONS INFORMATION Hold Capacitor For fast sample and hold applications, the size of the hald Capacitor is critical. A low value will give fast acquisition, but will also increase errors due to hold step, and droop caused by amplifier bias current. The capacitor should be made as large as possible, consistent with acquisition time and dynamic sampling error requirements. Capaci- tors larger than 0.1yF have an additional problem. They are generally not available in the low loss dielectrics like Teflon, Polystyrene, and NPO, at least not at a reasonable price and size. Mylar, even with its poor dielectric absorption properties, may be a reasonable choice where very long sample times are used and low droop rates are needed. Dielectric absorption in the hold capacitor can often be the major source of error ina sample and hold. The equivalent circuit of a typical capacitor is shown below with parallel RC networks used to model dielectric absorption. Output Transient at Start of Sampie Period a |__| 0.4 POSITIVE INPUT SLEW (OR SAMPLE RATE < Skitz} 0.2 Cy= 1000p 0 ae = 0.2 \ 4 4 Y 2. NEGATIVE INPUT-SLEW (OR SAMPLE pz 04 pres Cy = 1000F 4 5 = 04 } posi marl SLEW (08 SAMPLE RATE <SkHz} 4 < f C,2=0.01,F 0.2 VA | 0 Xo 02 NEGATIVE INPUT SLEW (OR SAMPLE RATE > SkHz) Cy 2:0.01pF -0.4 0 1 2 3 4 5 TIME (ys) Typical Hold Capacitor Equivalent Circuit C,, Ch~0.01 70.0.1 Cy Ry, Ry GENERATE TIME CONSTANTS OF 0.1-50 MILLISECONDS WITH C, Cy ' One can see that rapid changes in capacitor voltage will not be tracked by the internal parasitic capacitors because of the resistance in series with them. This leads to a sag effect in the hold capacitor after a sudden change in voltage followed by rapid switch to the hold mode. The capacitor remembers its previous state via the charge on the internal parasitic capacitance and sags 9-102 LI neLFIYSA/LFSYSA LF198/LF398 APPLICATIONS INFORMATION back slightly toward the previous voltage. The magnitude of the sag depends on the voltage change and the time spent sampling the new voltage. Several time constants are typically evident in the sag, although some capacitors tend to exhibit a single time constant, while others show a sag that indicates a blending of many time constants. The curves labeled CAPACITOR DIELECTRIC ABSORPTION show the amount of sag found after a 10V step with sam- ple time at the new voltage and hold time at the new voltage as variables. It is obvious that sag problems are minimized by long sample times and short hold times. This is often in conflict with basic sampling requirements, but one point should be made: if at all possible, keep the sample and hold amplifier in the tracking, or sam- pling, mode as much as possible to maximize the time the hold capacitor spends near the voltage at which it will eventually hold. The best capacitor for sample and hold applications is Teflon. It is clearly superior with regard to dielectric ab- sorption and operates over the full 55C to 125C temperature range. If size or price becomes a problem, the second choice for full temperature range operation is NPO, or COG ceramic units. Some care must be used herenot all NPO capacitors use the low dielectric constant ceramic necessary for low dielectric absorption. For lower temperatures (< 70C), Polystyrene has tradi- tionally been the best hold capacitor. The best units are cylindrical and fairly largethere seems to be a strong correlation between small size and poorer dielectric per- formance. Polypropylene has nearly the same absorption properties as polystyrene and offers 85C operation. It also tends to be smaller. Again, stay with cylindrically wrapped units. Other standard dielectrics such as mica, glass, mylar, and ordinary ceramic are much worse with regard to dielectric absorption. Mylar is sometimes used for large values when the ratio of sample to hold time is large and extremely low droop is required. Dynamic Sampling Error A significant sampling error can occur in any sample and hold if the input is moving when the unit is put into the hold mode. The two major causes for this error are digital delay in switch opening and analog delay across the hold capacitor. The switch opening delay is obvious and leads to a held output error of (dv/dt) x (Tg), where dv/dt is the slew rate of the input signal and Tg is switch delay. In the case of the LF198, Tg is approximately 150ns, giving a 4.5mV error when sampling the zero crossing of a 5V (peak) sine wave at 1kHz (dv/dt =A*2af =527r*10%). The analog delay is the difference between input signal and capacitor voltage. It is determined by the RC product of the hold capacitor and the effective series resistance, which in the case of the | LF198 is about 1500. This analog delay with a 0.01 pF hold /capacitor is ReC = 150 x 10-8 = 1 .5ys, or about ten times the delay of the switch. The sign of the analog delay is negativethe held output is related in time to the input voltage before the hold command was given. The overall dynamic sampling error is the sum of the digital and analog errors. The curve labeled Dynamic Sampling Error will be helpful in estimating these errors as a function of input slew rate and hold capacitor size. , Dynamic sampling error can be reduced by a factor of ten or more by inserting a delay in the logic input so that the hold command is delayed by an amount equal to the RC time constant of the LF198 and external hold capaci- tor. For a0.01F hold capacitor and the 1500 resistor in- ternal to the LF198, this is 1.5us. A simple RC network can be used in front of the logic input for delays up to == 1S. Longer delays require the addition of a logic gate to speed up the rise time of the delayed signal. See LOGIC RISE TIME in this section for further details. Hold Step Hold step is the small voltage step (after settling) seen at the output of a sample and hold amplifier when it is switched from the sample mode to the hold mode with a steady DC input. Hold step is typically the result of, or can be modeled as, a fixed quantity of charge transferred to the hold capacitor as a result of the internal switching that . occurs during the hold command. In the case of the LF198, that charge is about 5 picocoulombs, giving a hold step of 0.5mV for a 0.014F hold capacitor and 5mV for a 1000pF hold capacitor. (V=Q/C.) Hold step is reasonably independent of logic amplitude if care is taken to minimize the stray capacitance between the logic input Neen errr eee ere errr eee LY Wear 9-103LFI98A/LF398A LF198/LF398 APPLICATIONS INFORMATION and the hold capacitor. With thoughtful layout, including the guarding technique shown below, stray capacitance should be under 0.3pF, limiting charge variations to less than 0.3 picocoulombs per volt. Guarding Technique OFFSET AOJUST LOGIC REFERENCE GUARD TOP AND BOTTOM OF BOARD HOLD o~\ OUTPUT CAPACITOR tou BOTTOM VIEW Use 10-pin layout. Guard around C, is tied to output. Hold step varies slightly with analog input voltage (see curves). A typical unit will change at 0.4 picocoulombs per voit. This manifests itself as a gain error when the amplifier is switched to the hold mode. With a 0.01,F capacitor, the resulting gain error will be (0.4 PC/V)/0.01p4F =0.004%. This gain error is in the opposite direction of DC (sample mode) gain error. At high values of hold capacitor, DC gain error will dominate and gain will be slightly below unity (0.002%). For low value capacitors (<0.01,F), hold step induced gain error will dominate and hold mode gain will be slightly above unity. Zeroing out hold step does not change the variation of hold step with regard to input voltage. 9-104 Offset Zeroing A sample and hold amplifier has two distinct offset volt- ages. The first is just the DC offset of the amplifier while in the sample or tracking mode. It is identical to the input offset of any operational amplifier. The second offset voltage is the sum of the DC offset plus a dynamic term called hold step. Hold step is a change in output voltage when the amplifier is switched from sample mode to hold mode, with the input held steady. This second offset is often called hold mode offset. It can be less than or much greater than the DC offset, depending on the magnitude and sign of hold step. A fairly accurate model for hold step is a fixed charge injected into the hold capacitor by the switch turn-off cir- cuitry. The magnitude of the charge is reasonably inde- pendent of logic input amplitude. The resulting change in hold capacitor voltage is Q/ Ch. The charge, Q, is typically 5 picocoulombs, giving a 0.5mV hold step with a 0.01 pF hold capacitor. Since most sample and hold amplifiers are used, i.e., have their outputs read by an A to D con- verter, etc., during the hold mode, hold mode offset is arguably much more important than sample mode DC offset. DC offset adjustment is accomplished with a 1k low TC cermet potentiometer tied to V+ with 0.6mA flowing through it and the wiper tied to pin 2. This allows pin 2 to be moved +300mV around its nominal voltage (0.3V below V+). Offset adjustment range is + 9mvV, and the adjustment procedure nominally improves offset drift when the DC offset is reduced to zero. This offset method can be used to zero out hold mode offset, but at the expense of some induced offset drift. Each millivolt of hold step offset that is corrected by this method intro- duces 3.3uV/C drift. For 0.002pF or larger hold capacitors where hold step is a few millivolts or less, this is a practical solution to hold mode offset. In precision wide temperature range applications, or where Cy is less than 0.002yF, a separate hold mode zeroing method should be used. The circuit shown in the application sec- tion using a logic inverter and a 5pF capacitor is recom- mended (DC AND AC ZEROING). LI WeeLFI98A/LF398A LF198/LF398 APPLICATIONS INFORMATION Logic Fall Time Hold step is independent of logic input fall time only for fall times faster than 10V/,s. For instance, as logic fall time changes from 10V/ps to 1V/ps, hold step with a 0.01 ,F hold capacitor will typically increase from 0.25mV to 1.0mV. See the curve labeled HOLD STEP vs LOGIC SLEW RATE for further data points. If logic slew rate is not constant, use the value at the threshold point (1.5V with respect to logic reference). An RC network will have a discharge slew rate of V_/RC, where V, is the logic threshold of the LF198. The delay generated by the net- work will be RC*in(V*+/V_), where V* is logic ampli- tude. For a 1s delay, with 5V logic, an RC time constant of 0.8us is needed. This has a slew rate of 2V/ys at threshold, which will slightly degrade hold step. It is ob- vious that an RC delay network significantly longer then 1S will have a large effect on hold step. If longer delays are required, they should be followed by several inverter stages or a Schmitt trigger to increase slew rate. Adding Delay to Logic Input INVERTERS MAY BE ELIMINATED FOR AC <3ys LOGIC INPUT CONFIGURATIONS * TTL and CMOS cmos 3V <V_ (Hi State) <10V TV sV_ (Hi State) < 15V Op Amp Drive mM SAMPLE 7 I HOLD THRESHOLD = 1.4V THRESHOLD = 0.6 (V+)}+1.4V p 2.8V HOLD > RB | | > 5.6k SAMPLE SAMPLE THRESHOLD = 1.4 SELECT FOR 2.8V AT PIN B LAA r > & an 13v- HOLD THRESHOLD =0.6 (V+)1.4 aw SAMPLE > > 20k 13V 1 SAMPLE 13V ~~ HOLD THRESHOLD = + 4V = yt 2 > $ 20k THRESHOLD = ~ 44 = The logic input signal high state must be at least 2V below the positive supply voltage of the LF198. LY Wear 9-105LFI98A/LF398A LF1I98/LF398 TYPICAL APPLICATIONS X1000 Sample and Hold *FOR LOWER GAINS, THE LT1008 MUST BE FREQUENCY COMPENSATED USE = oF FROM COMP 2 TO GROUND Ramp Generator with Variable Reset Level D1 (T1004 1.2V OUTPUT RESET Sv ov RAMP SELECT FOR RAMP AATE AV _1.2V R= 10k at (R2)C) Sample and Difference Circuit (Output Follows Input in Hold Mode and Resets to Vg in Sample Mode) Vour=Vp+ 4Vjy (HOLD MODE) | RESET TRACK THIS RESISTOR PROTECTS INPUT FROM SURGE CURRENTS, BUT INCREASES SAMPLE TIME. IT CAN BE ELIMINATED IF INPUT IS OTHERWISE PROTECTED. Integrator with Programmable Reset Level RESET Vp LEVEL INPUT sit + INTEGRATE DIFFERENTIAL INTEGRATING INPUT 1% Vour (HOLD MODE) = anty S| vws | + [vs] 9-106 LY WeLFI98A/LF398A LF198/LF398 TYPICAL APPLICATIONS Output Holds at Average of Sampled Input Fast Acquisition, Low Droop Sample and Hold SAMPLE DC and AC Zeroing 2-Channel Switch DC Vos 15y 24k 1k ZERO A INPUT A SELECT __ 5V 5pF ov "B SELECT tL AC (HOLD STEP) ZERO - A B Gain 10.02% 1+0.2% 10k ZN 10109 47ka INV Bw =1MHz = 400kHZ Crosstalk 90d8 ~9008 | | @tkHz Offset s6mvV <T5mV LY Whee 9-107LFI98A/LF398A LF198/LF398 TYPICAL APPLICATIONS Staircase Generator 4 ov RESET 5 sv- out ct ov 0.01 uF cLock oa bag: = FS ur0012F, Sox 1.2 5v 1 TL: a ov L 300 pF *SELECT FOR STEP HEIGHT 50k =1V STEP Differential Hold OUTPUT =Vg WHEN IN HOLD MODE =(Vs + Vem} WHEN IN- SAMPLE MODE SELECT FOR TIME CONSTANT C1 = Tonk ** ADJUST FOR AMPLITUDE 9-108 LT unterLFI98A/LF398A LF198/LF398 TYPICAL APPLICATIONS Isolated Temperature Sensor RB 1000* 2.4K 4N914 COMPENSATES FOR TRANSFORMER RESISTANCE. SELECT FOR FLAT OUTPUT FROM LF198 WHILE IN SAMPLE MODE. LM135 10mv/K Ti=TRW PC-SS0-32 0.01 nS rl" 4.7k 390pF = d c2 R7 D2 470pF 100k 1N914 -15V Pulse Width to Voltage Converter 15V 01 LT1004 c1_t 1.235V OUTPUT T0 OtuF a1 6 SYNCHRONIZED 2N3906 ATO D CONVERTOR d3 Nees : OVM OUTPUTT cs 1000pF T" , POLYSTYRENE R8 = R2g C2 D4 = 10k = 3k> 1000pF POLY- 05 STYRENE 03 , 2N3906 R3 Sv 12k LC 5V Sis + > k 5V Le | | i 5,14 RE sy INPUT fe C 5 | 1k 1 k 3 4 a AA + 741.121 9 REF ne 7 READ = 1s AFTER i L a 10k 0 GOES LOW = +FOR REPETITIVE PULSES D2-D5 1N914 c4 ONLY. INCREASE C5 FOR 1000pF fs 10kHz LY Wine 9-109LFI98A/LF398A LF198/LF398 TYPICAL APPLICATIONS Motor Speed Controller Needs No Tachometer* 15 >= 1 LI Le iF 173524 Vv @15V RM 3 2k gon 4 ANA { eusazs 5 1N4148 *BACK EMF OF MOTOR IS SAMPLED AND USED TO CONTROL SPEED. ** SELECT FOR OPTIMUM LOOP STABILITY. C3 1S NON POLARIZED DEFINITION OF TERMS Hold Step: The voltage step at the output of the amplifier when switching from sample mode to hold mode with a constant analog input voltage and a logic swing of 5V. Acquisition Time: The time required to acquire, within a defined error, a new analog input voltage with an output change of 10V. Acquisition time includes output settling time and includes the time required for all internal nodes to settle so that the output is at the proper value when switched to the hold mode. Gain Error: The ratio of output voltage swing to input voltage swing in the sample mode expressed as a percent difference. tD1 IS USED FOR START-UP. IT LIMITS DUTY CYCLE TO ~75% @ MOTOR + Hold Settling Time: The time required for the output to settle within imV of final value after a hold command is initiated. Dynamic Sampling Error: The error introduced into the held output voltage due to a changing analog input at the time the hold command is given. Error is expressed in mV with a given hold capacitor value and input slew rate. Note that this error term occurs even for long sample times. Aperture Time: The delay required between Hold command and an input analog transition, so that the tran- sition does not affect the held output. 9-110 Lo wnereLFI98A/LF398A LF198/LF398 SCHEMATIC DIAGRAM =: Els Ci: , z ane w 8 & [3 T_ g oF Et fF oS ee g "i oa }__7. ne Gee Te 4,4 5 oss 1 10k 10k Z 6 AN VA Q! 33k 3k 159 CAP [s] LOGIC 2 10k > Q27 I gh 2 < 2 100k 21.1k 3620 q , tk Pa 2 22k zk i 039 Q36 025 y a24 > > arg a 1 mee) Bk [ C 200k - yr | 020 16k 023 } 550 3 = & & = n Nid / | ed > 2 & 3 8 \ 3S Ps 1 & = 5 S ia ~L LI Wee 9-111 > :LFI98A/LF398A LF198/LF398 errr PACKAGE DESCRIPTION Dimensions in inches (millimeters) unless otherwise noted. H Package J8 Package Metal Can 8 Lead Hermetic DIP 0.355 0.370 C4 *~ (9.017 9.398) 3 5 A 0.2200.310 Oat 8 5 (5.588 7.874) 0,040 DIA 1 4 (1.016) 0.050 i 2 (1.270) 0.165 0.185, ao } MAX (4.191 4.699) 0.055 SEATING Tt : | 1se7 __ GAUGE MAX = ht W__ PLANE ae 0.405 0.010 0.045 fil i it (12. y" ) a 200 (10.28 (0.254 1.143) ye] fg 9.076 0.021. 0.016 pt ee 5.080) 0.015 0.060 0.005 (0.406 0.833) MAX (0.381 1.524) iz TP MIN i, | . ast < 0.027 -0,045, +. 4 ! 0.027-0.034 7S (0.686 - 1.143) 0.125 0.200 (3.175 5,080) t 0.150 i 3.810) rt MIN 1 u 0030-0070 4 = a/ GLASS 0 Ct 4 9-48" 0.008 0.015 10 (0. fo.762= 1.778 rh (0.203 0:38) (254) 0.014-0.023 ot, 023 0.290 0.320 (0.356 (0.396 0.504 (7.3668.128) 0.100 (2.540) 0.1200.160 BSC" 7a.0a8 4.068) RAD TYP *LEADS WITHIN 0.007 OF TRUE POSITION (TP) AT GAUGE PLANE INSULATING STANDOFF Tmax Sa LF398 100C 100C /W Tjmax Gia Gic LF198/LF198A 150C 150C /W 45C/W LF398/LF398A 100C 150C /W 45C/W N8 Package 8 Lead Plastic ooo Mm a 1 ( 0.240 0.280 = 7.112) 5 8 + Coro | 0.040 0.060 one 528) sa 0.370 0.400. cH (9.400 10.16) . 0.005 one MIN >| (0127) jwe 7 5 MIN i 0.155 ~0.175 (3.937 4.445) il | Y __. A ' q 0.1250.130 B15 0.145 i (3.175 3.302} (2.921 7) i a u u <_ 0.0300.060_ wa o age 0.008 0.015 ! 0.100 (0.762 1.524) Tez 1.526 sel eoeatse of (0.203 0.381) B TYP (2540) 0.014 0.023. vho2 0.290 0.310 TYP (0.356 0.584) (7.366 7.674) TYP LEADS WITHIN 0.007 OF TRUE POSITION (TP) AT GAUGE PLANE Tymax Gia LF398/LF398A 100C 130C /W 9-112 LD Wive