MTC-20276PC-C - ON Semiconductor L.L.C.

MTC-20276

Single Chip ISDN NT

2B1Q (INTQ)

Data Sheet

Rev. 2.3 - October 1999

Key Features

▼Fully integrated basic rate U

to S/T ISDN NT device

▼Pin compatible with MTC-

20277 INTT (4B3T)

▼Full compliance with the

applicable ETSI and

ITU requirements

▼Minimal external components

▼< 355mW power consump-

tion, 3.3V operating voltage

▼Fully integrated Embedded

Operations Channel handling

▼Advanced 0.5µ CMOS

mixed analog/digital

process technology

▼-40°C to +85°C or 0 to 70°C

operating ranges

▼44 pin PQFP

Applications

▼Standard ISDN NT1 applica-

tions (stand-alone mode)

▼Advanced NT with analog

line interfaces (“NT1+”)

▼Micro-PABX

▼Data network gateways

▼Pair gain systems

▼Data terminals

▼CTI

‘U’ interface ‘S’ interface

Digital Expansion and Test logic

Crystal

Oscillator

Power-on

Reset

TX TX

RX RX

JTAG

test

access

SPI and

Aux. test

access

Dual GCI access

and expansion

port

Analog

Support

Functions

(S-bus mode)

Power Supply

Optional Expanded functions

(Analog lines, data

interfaces,...)

4-wire / 2 wire

network

Uk0 S0

MTC-20276 INTQ

Fig.1: MTC-20276 Application Block Diagram

General Description

The MTC-20276 INTQ integrates all

of the communications functions re-

quired in a Basic Rate ISDN Network

Terminator on a single monolithic inte-

grated circuit. It provides activation/

deactivation on chip and does not

require an external microprocessor.

The INTQ is designed for the 2B1Q

line-code on the U-interface and is pin

compatible with the MTC-20277 INTT,

which performs identical functions but

with the 4B3T U-interface line code.

The MTC-20276 includes a GCI

expansion port, to allow extended

functions to be added (e.g. interfaces

to existing analog terminal equipment

by means of the MTK-40131 Short-

Haul POTS chipset).

Ordering Information

Part number Package Code Temp.

MTC-20276PC-I 44 pin PLCC PC44 -40 /+85°C

MTC-20276PC-C 44 pin PLCC PC44 0 /+70°C

MTC-20276 INTQ

The MTC-20276 has a number of test

access ports to facilitate system or pro-

duction testing. One of these ports is

configured as a dual GCI interface,

which operates in one of two modes.

In Mode 0 (GMode = logic 0), the

GCI port allows the data flow between

the 'U' and the 'S' ports to be optional-

ly monitored.

This is the “stand alone” mode, which

is the normal mode for simple NT1

applications. No additional micro-

processor or other control device is

required in this mode.

Mode 1 (GMode = logic1) allows sep-

arate access to the 'U' and the 'S'

ports, for use by an external GCI com-

patible controller device. In this mode,

the chip supports additional

features required by extended NT

modules (“NT1+”) such as interfaces

to existing analog equipment, or

advanced data communication gate-

ways.

The application section describes the

circuit configuration of the MTC-

20276 in its stand alone mode, for

conventional NT1 applications.

(Figure 4)

Figure 2 below shows the system

concept of an MTC-20276/77 in an

“NT1+” application, in combination

with the MTK-40131 “SH-POTS” chip-

set for short-haul analog telephone

lines.

MTC-2028xx is one of a family of inter-

face and controller devices which cover

a wide range of applications, e.g. MTC-

20280 for ISDN NT+ or small PABX

applications

MTC-20276 complies with relevant

ANSI and ETSI specifications.

ETSI ETS 300 297

ETSI ETS 300 012

ETSI ETR 80

ANSI T1.601

ITU I.430

ITU G.961

* GCI (General Circuit Interface), is an

interface specification developed jointly

by Alcatel, Italtel, GPT and Siemens,

and can be obtained from Alcatel

Microelectronics.

US - bus

MTC-

30132

SH-LIC

MTK-40131

SH-POTS chipset

Analog Line 1

Analog Line 2

MTC-

30132

SH-LIC

Power

Supply

mains

GCI

MTC-

20232

CODSP

“NT1+” Box

MTC-2028x

Series

Controller for

ISDN

Terminal

Adapters

MTC-20276/7

INT

Analog

FAX

Answering Machine Analog Telephone

Digital TelephonePC / POS Terminal

ISDN Line Connection

Existing Analog Installation

RS 232

Fig.2: Concept of an NT1+ Configuration for 2 Analog Lines

NT and Extended NT

Functions (“NTplus”)

Standards Compliance

MTC-20276 INTQ

Table of Content

Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

NT and Extended NT Functions (“NTplus”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Standards Compliance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Electrical Characteristics

Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8

Quality / Reliability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Package / Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

LED Indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

NT1Schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Recommended Component Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Application Information

Transformer Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

S-Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

U-Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Master Clock and XTAL Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Typical Crystal Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Overvoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Unused Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Detailed Functional Description

U-Interface Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Physical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Logical Characteristics of the U-interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Scrambling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Descrambling. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Activation and Deactivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Analog Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

MTC-20276 INTQ

GCI Interface, Common Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Data Format and Timing of the GCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Continuous Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

The GCI Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

The Physical Organization of the GCI Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

General Content of the GCI Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Power-down on GCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Frame Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

External Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27

G1 External GCI Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

G2 External GCI Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

U-Interface Command List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Command and Indicate (C/I) Channel (A bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Power Down of the Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Transition from Synchronous to Power-Down State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Wake-up Originated by Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

Wake-up Originated by the Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31

S-interface Commands and Indications Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Commands in NT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Indications in NT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

The S-interface Functional Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

General Description of the S-bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

S-interface - General Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Test Modes Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

GCI Clock Synchronization in the ISDN Environment for the Upstream S-interface (NT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37

Clock Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Power Saving / Deactivation of the S-interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Activation of the S-interface in NT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Detailed Operational Description of the S-bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

General Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Transmission Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Frame Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

AMI S-bus Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

Balance Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38

AMI Violations for Frame Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Frame Synchronization - Distance Rule . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Frame Synchronization - Multiframing Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Synchronization Principles - Adaptive Bit Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Synchronization Principles - Fixed Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Pulse Polarity in the S-bus Frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Transmitted Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Details on Downlink Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Details on Uplink Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

S-bus Transmitter Timing and Framing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40

Transmitter Timing and Framing at the NT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

S-bus Receiver Timing and Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Frame Synchronization Details in Adaptive Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

First Violation Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Violation Validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

MTC-20276 INTQ

RX Bit Synchronization NT Adaptive bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Immediate Bit Synchronization at Instant t2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Continuous Bit Synchronization at Each F/L Crossing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Timing Relation Between RX and TX on the S-bus in NT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41

Frame Relation Between GCI and S-Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

E-channel Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Multiframing - S and Q Channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

S-Interface Programming

M-Channel Messages and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

M-Channel Receiver and Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

General Content of M-Channel Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

S and Q Channel Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Internal Register M-Channel Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42

M-Channel Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

M-Channel Format - Bit and Byte Numbering Convention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Byte Transfer Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Idle M-Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Start of Message (SOM) and First Byte Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Acknowledge of the SOM and First Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Further Byte transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Further Byte Acknowledgement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

End of Message (EOM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Acknowledge of EOM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Sender Not Ready . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Receiver Not Ready . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

IDLE forced From Sender . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Abort request From Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Acknowledge Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Reset of the M-channel Transceiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43

Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Read Operation and Content . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Detailed Bitmap of the Internal Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Identification Register Read Only Address 0h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Version Number Register Read and Write Address 1h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Configuration Register Read and Write Address 2h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Output Register Read and Write Address 3h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

IN1 and IN2 Registers Read Only Addresses 4h and 5h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Performance Register Read Only Address 6h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

M-Channel Operation Messages Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Package Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

Device Branding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47

44PQFP Mechanical Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48

Application Note: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

MTC-20276 INTQ Compliance Issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49

Lists of Tables

Maintenance and Service Channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Service and Maintenance Data Convention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Service and Maintenance Data Convention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Command and Indicate (C/I) Channel (A bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

S-interface Commands and Indications Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Commands in NT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Indications in NT Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Transmitted Frames . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39

Detailed Bitmap of the Internal Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Identification Register Read Only Address 0h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Version Number Register Read and Write Address 1h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Configuration Register Read and Write Address 2h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Output Register Read and Write Address 3h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

IN1 and IN2 Registers Read Only Addresses 4h and 5h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

Performance Register Read Only Address 6h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

MTC-20276 INTQ

Operating Conditions

Unless otherwise stated, the following

electrical characteristics are valid over

the ranges specified here. (Vss = 0V).

Parameter Min Max Units Note

DVDD, AVDD 3.15 3.45 V =3.3V ±5%

SNAVDD, supply noise, analog 10 mVpp

SNDVDD, supply noise, digital 100 mVpp

SNAREF, supply noise, analog ref. 0.1 mVpp Note 2

IAREF - 0.25 + 0.25 mA load on AREF Pin

Crystal frequency 15.359 15.361 MHz ±50ppm, Note 1

Temperature range -40 +85 °C

Note 1: An external clock may be

applied to XTAL2, pin 24. Temperature

dependent drift <10ppm.

Note 2: AREF is an output, designed to

allow a decoupling capacitor to be

placed on the internal analog reference

voltage. The external circuit layout must

avoid the induction of noise on this pin.

MTC-20276 INTQ

Electrical Characteristics

Absolute Maximum Ratings

Operation of the device beyond these

conditions is not guaranteed. Sustained

exposure to these limits will adversely

effect device reliability.

Parameter Max Units

DVDD, AVDD 4.8 V (see note)

Vin, Voltage on any device pin VSS-0.3 V

VDD+0.3 or 3.63 V, whichever is lower

Storage temperature -65 to +150 °C

Temperature under bias -55 to +125 °C

Lead Temperature 300 °C

(soldering 10 sec)

Table 1

Table 2

Note: Exposure to voltages at or above

this level for more than 10 hours accum-

mulated over the device’s operating life

will adversely effect reliability.

Note 2. All logic pins except NRESET,

which is a Schmitt-trigger input with hys-

teresis.

MTC-20276 INTQ

DC Characteristics

Parameter Conditions Min Max Units Note

VIH Input level, logic 1 0.8 DVDD 1

VIL Input level, logic 0 0.2 DVDD 1

VOH Output level, logic 1 0.85 DVDD 1

VOL Output level, logic 0 0.4 V 1

VIH Rising, NRESET 1.7 1.9 V 1

VIL Falling, NRESET 0.9 1.1 V 1

VAREF Reference voltage output,

load current < ±250µA. 1.6 1.7 V

VTNRES Nreset input threshold 1.6 1.7 V

Note 1: All logic pins except NRESET,

which is a Schmitt-trigger input with

hysteresis.

AC Characteristics

Quality / Reliability

Early failure rate ≤0.3% at 3000 hours

Long term failure rate ≤300 FIT for 45°C average ambient and 45% average humidity

Lifetime ≥15 years

Parameter Conditions Min Max Units Note

Cin Input capacitance any pin 1 pF

Cload Load capacitance on any output pin 100 pF

VTPWRES Reset pulse width 10 mS

Table 4

MTB-20276 State Typ Max Unit

Full activated - ETSQI loop 1 on U loop, random data 362 390 mW

Full activated - ETSQI loop 2 (40dB) on U loop, random data 325 355 mW

U loop only activated - ETSI loop 1, random data 340 mW

U loop only activated - ETSI loop 2 (40dB), random data 301 mW

Deactivated 20 22 mW

Table 3

Table 5

MTC-20276 INTQ

Package / Pinout

SXP

SXN

SRP

SRN

AUX

SPIDO

SPIDI

VDD

XTAL1

XTAL2

VSS

LOUT2

AREF

LIN1

LIN2

TRST

TCK

TMS

TDI

TDO

SPICK

SPICS

LOUT1

AVDD

AVSS

NRESET

TSP

PW220

PW40

SBUS

AVDD

AVSS

SATP

G1DOUT

G1DIN

G1DCLK

G1DFR

VDD

VSS

G2DOUT

G2DIN

G2DCLK

G2DFR

GMODE

MTC-20276

INTQ

Fig.3: Pinout, 44 PQFP Package (MTC-20276PQ)

MTC-20276 INTQ

Pin Description

Nr. Function Name Dir. Description

44 LOUT1 O U-interface analog outputs. The connections LOUT1 and LOUT2 interface

1 LOUT2 O the U driver outputs, via termination resistors and the line coupling

U transformer, to the U0 reference point.

3 LIN1 I U-interface analog inputs to the INTQ from the analog ‘hybrid’

4 LIN2 I

2 AREF O Analog ground, +1.65 V ±3%. Used as reference voltage for A/D and D/A.

43 AVDD P +3.3V ±5% power supply for analog U-interface functions

42 AVSS P 0V ground for analog U-interface functions

33 SXP O S-interface analog outputs. SXP and SXN interface the S-driver outputs

32 SXN O via terminating resistors and the Tx line coupling transformer to the S0

reference point (Tx).

31 S SRP I S-interface analog inputs. SRP and SRN interface the S-inputs via the Rx line

30 SRN I coupling transformer to the S0 reference point (Rx).

37 SBUS I S-bus type configuration. 1 = short bus with fixed timing, 0 = adaptive

timing for extended bus or point-to-point

34 SATP O Analog test pin. Used for test purposes only, should be left open circuit

36 AVDD P +3.3 ±5% power supply for analog S-interface functions

35 AVSS P 0V ground for analog S-interface functions

12 G1DOUT O Primary GCI interface G1:

13 G1DIN I/O GMODE = 0: Monitoring of the internal GCI between the U and S.

14 GCI G1DCLK O GMODE = 1: NTplus mode; complete GCI connected to U with U as master.

15 G1DFR O G1DOUT = data output

G1DIN = data input (output direction in monitoring mode)

G1DCLK = 512 KHz GCI clock

G1DFR = 8KHz GCI frame clock which identifies the beginning of

the frame of G1DIN and G1DOUT

18 G2DOUT O Secondary GCI interface G2:

19 G2DIN I GMODE = 0: No function

20 G2DCLK I GMODE = 1: NTplus mode; complete GCI connected to S with external master.

21 G2DFR I G2DOUT = data output

G2DIN = data input

G2DCLK = 512KHz GCI clock

G2DFR = 8KHz GCI frame clock which identifies the beginning of

the frame of G2DIN and G2DOUT

Remark: if NT Plus mode is not used, the inputs should be strapped

high or low.

22 GMODE I Select NTplus mode. 0 = monitoring mode, 1 = NTplus mode.

5 TRST I TAP (Test Access Port) controller reset, active low

6 JTAG TCK I TAP controller clock, maximum 10 MHz

7 TMS I TAP controller mode selection

8 TDI I TAP controller input

9 TDO O TAP controller output

The table gives a summary of all MTC-20276 pins and their functions.

Table 6

Note: None of the Input pins are 5V tolerant.

* This only affects the “PS1” and “PS2” bits in the upstream M symbol, and does not have any functional implication.

MTC-20276 INTQ

** This only affects the “CSO” bit in the upstream M symbol, and does not influence the activation performance of the INTQ.

LED OFF Both U and S-interfaces are inactive

Fast flashing (8Hz) The U-interface is attempting to synchronize, or the EOC has activated a

2B+D loopback.

Slow flashing (1Hz) The U-interface is synchronized and the S-interface is attempting to synchronize.

LED ON Both U and S-interfaces are fully synchronized and ‘connect through’

status is achieved.

LED Indicator

The LED output can source up to 4mA to directly drive an LED, via a current limiting resistor.

Table 7

Device pin 27 (OPTO) is used to determine whether an automatic upstream activation request is performed after power-up

or reset, or not. (New releases of the relevant ETSI specifications require automatic activation on power-up, whereas

previous releases did not)

Pin 27 should be strapped as follows:

Function: Pin 27 strapped to:

Automatic activation request VDD

No automatic activation request VSS

41 RESET NRESET I Hardware reset, active low. Schmitt-trigger input for connection to

external RC or logic device.

25 OSC. XTAL1 I Connection to external crystal (15.36MHz ± 100ppm). May also be used

as input for external master clock source.

24 XTAL2 I Connection to external crystal.

40 Monitor TSP I Transmit Single Pulses. INTQ transmits single pulses of alternating maximum

positive and negative polarity at the S and U-interface.

Pulse repetition rate is 0.67 kHz at the U-interface, for test purposes and

as a search tone on the line.

39 PW220 I Indicate if the local mains power supply is available.*

1 = mains power supply ON

0 = mains power supply OFF

38 PW40 I Indicate if the local 40V power supply is available.*

1 = 40V power supply ON

0 = 40V power supply OFF

10 TEST0 O Factory use only. Leave open circuit.

11 TEST1 O

27 OPTO I Opto isolator input. See below.

28 LED O State indicator LED. See below.

29 CSO I Indicate cold-start-only operation mode:

0 = normal mode

1 = cold-start-only operation mode**

16 VDD P +3.3 V ±5% power supply for digital functions

26 VDD P

17 VSS P 0V ground for digital functions

23 VSS P

NT1 Schematic

MTC-20276 INTQ

UK0

C6C5

VSS AVSSVDD AVDD

LOUT1

LOUT2

LIN1

LIN2

NRESET

X1 X2

SXP

SXN

SRP

SRN

+/- 40V -/+ 40V

Power Supply

Vdd (+3.3V)

Vss

230V AC

S0 (Tx)

S0 (Rx)

30...100V from

UK0 power feed

MTC-20276

INTQ

Clf

Vdd

Vdd Vdd

R10

R11

GMODE

SBUS

S-bus type

AREF

C3 C4

TSP Vddline test

R12

R13

Vdd

Passive

Hybrid

(Figure 4a)

Metalic Line

Termination

Circuit

R14

Vdd

OPTO LED

R15

Power Feed

(30..100V)

Z1* North American Market Only

R20

LOUT1

LIN1

LOUT2

LIN2

Rh11

Rh21

Rh12

Rh22

Rh13

Rh23

Rh14

Rh24

Rh16

Rh26Ch2

Ch1

Clf

Ch7

Li-line

power feed

Ch3

Ch4

Ch5 Ch6

Rh17

Fig.4: NT1 Application Schematic

Fig.4a: Recommended Hybrid Component Configuration

Application Information

The MTC-20276 requires very few

external components, all of which are

low-cost and readily available types.

In addition, the use of a 44PQFP

package style allows further savings in

the total cost and physical size of the

ISDN NT module.

The following recommended applica-

tions information is constantly being

reviewed to improve cost and

performance. Please contact Alcatel

Microelectronics’ application support

group for the latest details.

MTC-20276 INTQ

Component Function Value Comment

U Interface

T1 U transformer 2:1, 15 mH see text

Rh14, Rh24 U feed bridge 13Ω±1%

Rh17 Hybrid 590Ω(470Ω+120Ω)±1%

Rh11, Rh21 Hybrid 1k ±1%

Rh12, Rh22 Hybrid 4.32kΩ±1%

Rh13, Rh23 Hybrid 6.81kΩ±1%

Rh16, Rh26 Hybrid 100Ω±1%

Ch1, Ch2 Hybrid 4.7nF ±5%

Ch3 Hybrid 470pF ±5%

Ch4, Ch5 Hybrid 39nF ±5%

Ch6 Hybrid 2.7nF ±5%

Ch7 100nF 200V

Clf Line-feed coupling 2.2µF 200V

S/T Interface

T2,T3 S transformer 2:1 see text

R8,R9 S-bus transmit impedance 33Ω±1%

R10,R11 S-bus receive impedance 5kΩ±10%

Rt S-bus termination resistor 100Ω

C8 S-bus receive capacitor 27pF 10%

Crystal

X1 crystal 15.36 MHz see text

C5,C6 crystal load 22pF see text

C7 crystal load 0 to 22pF (optional) see text

R20 crystal stabilizer 1MΩ

Miscellaneous

R7,R12,R13,R14 Pull-up/down 100kΩ

R15 LED current limit 510Ω-

C1,C2 reset delay 100nF

C3,C4 supply decoupling 100nF

D1 loss-of-power reset 1N4148 any small signal diode

Z1 Power Supply Clamp 4.1V zener

S1 switch - S-bus mode

S2 switch - Test signal

Recommended Component Values

Table 8

MTC-20276 INTQ

At the pins XTAL1 and XTAL2 a

crystal must be connected to form a

parallel mode oscillator. Two capaci-

tors of 22 pF should be connected to

ground.

Some crystals may require the parallel

capacitor Cp to be used (10 pf Typ).

Master Clock and XTAL Connections

XTAL1

XTAL2

22pF

15.36 MHz

1MΩ

Application Information

Transformer Specifications

Table 9

S-Interface

Parameter Min Max Units

Turns Ratio 2:1 Line: Chip

Primary Inductance 20 mH

Leakage Inductance 13 µH

Interwinding Capacitance 50 pF nominal

PRI DCR 0.9 1.3 Ω(1.1Ω± 20%)

SEC DCR 2.1 3.1 Ω(2.6Ω± 20%)

U-Interface

Parameter Min Max Units

Turns Ratio 2:1 Line: Chip

Primary Inductance 13.5 16.5 mH

Leakage Inductance 60 µH

Interwinding Capacitance 90 pF

PRI DCR 6 7 Ω

SEC DCR 2.8 3.3 Ω

Typical Crystal Specifications

Table 10

AT cut, fundamental mode

Parallel resonance frequency 15.360 MHz

Total tolerance ± 50 ppm

Dynamic capacitance 15 fF

Load capacitance 30 pF

Parallel capacitance 7 pF

Series resistance 40 Ω

Series resistance drift (age) ± 10 %

Drive level 0.25 mW

Fig.5: Crystal Configuration

Unused Pins

The INTQ has a number of device pins

which are used only in specific applica-

tions, or for device testing. These pins

should be connected as shown below to

ensure proper operation in a given

application. ‘0’ means connect to

ground, ‘1’ means connect to Vdd,

‘open’ means make no connection.

A dash (‘-’) means that the pin is used

in the application. All other pins have

defined states as shown in the applica-

tion schematic.

MTC-20276 INTQ

Pin Number NT mode NT+ mode

GMODE 22 0 1

G2DOUT 18 open -

G2DIN 19 1 -

G2DCLK 20 0 -

G2DFR 21 0 -

G1DOUT 12 open/monitor -

G1DIN 13 open/monitor -

G1DCLK 14 open/monitor -

G1DFR 15 open/monitor -

TRST 5 0 (pull down) 0 (pull down)

TCK 6 1 (pull up) 1 (pull up)

TMS 7 1 (pull up) 1 (pull up)

TDI 8 1 (pull up) 1 (pull up)

TDO 9 open open

CSO 29 0 (normal) 0 (normal)

1 ( CSO) 1 (CSO)

PW40 38 - -

PW220 39 - -

TEST0 10 open open

TEST1 11 open open

OPTO 27 - -

LED 28 - -

SATP 34 open open

TSP 40 0 (normal) 0 (normal)

1 ( test pulses) 1 ( test pulses)

PW40 38 - -

S BUS 37 0 (P-P S Bus) 0 (P-P S Bus)

1 (Short S Bus) 1 (Short S Bus)

Overvoltage Protection

This is strongly dependant on the Print-

ed Circuit Board layout and local

specification variations. Generally, it

is recommended to use standard small-

signal diodes to clamp voltages from

the S-interface (e.g. 1N4148) and

U-interface (e.g. 1N4004) to Vdd and

ground. The recommended protection

for the U-interface is to diode clamp

the chip side transformer pins to the

supply rails, and for the S-interface

clamp the INTQ device pins (30, 31,

32, 33). In order to prevent excessive

disturbance voltages from causing the

power-supply voltage to increase (full-

wave rectifier effect through the protec-

tion diodes), it is recommended that a

zener-diode is used to clamp the Vdd

voltage < 4,8V.

Table 11

MTC-20276 INTQ

Common Hybrid Schematics for 4B3T and 2B1Q

LOUT1

LIN1

LOUT2

LIN2

15mH

4k32

6k81

13Ω

100

4n7

u-line

power feed

4n7

470p

39n

39n 2n7

590

LOUT1

LIN1

LOUT2

LIN2

6mH

T2 3k3

3k3

25Ω

470p

u short

(* for FTZ loops, 470p -> 680p and 7kΩ -> 6k8)

10nF

200V 200V

2:1

2.2µF

u-line

power feed

10nF

200V 200V

2.2µF

1.6:1

2B1Q - Recommended Hybrid component Configuration

Fig.5a: 4B3T - Recommended Hybrid Component Configuration, using same PCB layout as 2B1Q,

MTC-20276 INTQ

Fig.5b: MTC-20276 / 20277 Recommended Power Supply Arrangement

Vdd in

10µ + 100n 10µ + 100n

AVDD AVDD VDD VDD

43 36 16 26

Vss in

AVSS AVSS VSS VSS

42 35 17 23

Note: It is recommended to put the decoupling capacitors close to the chip.

MTC-20276 INTQ

Detailed Functional Description

U-Interface Block

Physical Characteristics

The quaternary symbol stream on the

U-interface has to the following physi-

cal characteristics:

Symbol rate

The symbol rate is 80 kbaud ± 1 ppm

and applies to synchronous symbol

transmission.

Input Jitter

The INTQ tolerates a sinusoidal input

jitter of the quaternary symbols as indi-

cated in Figure 6.

Jitter Transfer Function

The jitter transfer function of the INTQ

(looped between U-interfaces) doesn’t

exceed ± 1 dB in the frequency range

3 Hz to 30 Hz.

Output Jitter

The peak-to-peak jitter produced by

the INTQ doesn’t exceed 0.02 UI

(≤166 ns), when measured via a high

pass filter with a cut-off frequency of

30 Hz. Without this filter the same

measurement doesn’t read more than

0.1 UI.

Transmit Signal Amplitude

The absolute peak value VImax of a

single pulse VI at the U0 interface ter-

minated with a 135 Ohm resistance is

2.5 V ± 5%.

The absolute peak value of the coded

quaternary signal measured at U0

interface terminated with 135 Ohm

doesn’t exceed 4 V.

Jitter Amplitude

(peak-to-peak)

Jitter Amplitude

(peak-to-peak)

UI = Unit

Interval

UI = Unit

Interval

0,30 UIpp

0,008 UIpp

20 db/Decade

19 Hz 10 KHz

Jitter Frequency

0,5 Hz

Fig.6: Range of Admissible Sinusoidal Input Jitter

Stability

The transmit signal amplitude mea-

sured over a period of one minute

doesn’t vary by more than 1% begin-

ning 5 ms after the INTQ is switched

into power-up state.

Transmit Spectrum

The spectrum of the quaternary trans-

mit signal at U0 interface doesn’t

exceed the limits given in Figure 8.

Pulse Shape

A single pulse measured across a 135

Ohm resistance at U0 interface com-

ply to the spectral requirements pre-

sented in Figure 8 and the pulse mask

requirements given in Figure 9.

Maximum Voltage

The maximum peak-to-peak value

VUmax of the voltage VU as shown in

figure 7 with full receive signal (short

line), that can be accepted is 2 V. Due

to the analog echo subtraction the

maximum peak-to peak value Vinmax

of the voltage Vin between LIN1 and

LIN2 is 1.35 V.

Input/Output Impedance

The line terminating impedance is

nominally 135 Ohm in power up and

power down states. The return loss

against 135Ωreal exceeds 16 dB

between 12 kHz and 50 kHz.

- slope below 12 kHz: 20 dB /

decade

- slope above 50 kHz: -10 dB /

decade

Load

The load is given by the line trans-

former and the subscriber line. The

loops are standardised by the ANSI

and ETSI documents.

- Turns ratio of line transformer: 2:1

- Transformer coil inductance (from

line side): 15 mH ± 10%

MTC-20276 INTQ

Analog Echo

Subtraction

12 Ohm

1:2

LIN1

LIN2

LOUT2

LOUT1

MTC-20276

INTQ

U0, short line

VIN

Fig.7: Test Circuit for Voltages VU and VIN, U0 Interface

-U

-T 0

2.625V

2.5V

2.375V

T= = 12.5 µs

80 KHz

10mV

-10mV

T 8T2T 29T 30T

Time t

0.2V

-0.2V

Fig.8: Single Pulse Mask

MTC-20276 INTQ

Logical Characteristics of the U-Interface

MTC-20276 INTQ

The quaternary symbol stream crossing

the U-interface complies with the fol-

lowing logical characteristics:

Frame Structure

The information flow across the sub-

scriber line uses frames as shown in Fig-

ure 10. The length of such a frame cor-

responds to 120 quaternary symbols

being transmitted within 1.5 ms. The

frame structure is detailed as follows:

B+B+D - Data

108 quaternary symbols represent 216

bits of scrambled and encoded B+B+D

data. The 108 quaternary symbols are

transmitted in succession. These blocks

are assembled as follows:

Data of

B1 + B2 + D + B1 + B2 + D

Number of bits

8 8 2 8 8 2

Quad

Position

Bit

Position

1-9

1-18

10-117

19-234

118-120

235-240

Frame 1 ISW 2B+D 2B+D ... 2B+D 2B+D M1 ... M6

Frame 2 2B+D 2B+D ... 2B+D 2B+D M1 ... M6

Frame 3 SW 2B+D 2B+D ... 2B+D 2B+D M1 ... M6

Frame 4 SW 2B+D 2B+D ... 2B+D 2B+D M1 ... M6

Frame 5 SW 2B+D 2B+D ... 2B+D 2B+D M1 ... M6

Frame 6 SW 2B+D 2B+D ... 2B+D 2B+D M1 ... M6

Frame 7 SW 2B+D 2B+D ... 2B+D 2B+D M1 ... M6

Frame 8 SW 2B+D 2B+D ... 2B+D 2B+D M1 ... M6

Fig.9: Frame and Superframe Structure

Synchronising Word

9 quaternary symbols in each direction

represent a non-scrambled synchronis-

ing word. They are used to generate

frame clocks. If they are out of position

for 60 ... 200 consecutive frames, the

line resynchronization procedure is

started. The quaternary values and the

frame position are as follows:

1. From LT to NT or analog loop in LT

(loop 1) or analog loop on NT, and

from NT to LT.

SW Polarity: +3 +3 -3 -3 -3 +3 -3 +3 +3

ISW Polarity: -3 -3 +3 +3 +3 -3 +3 -3 -3

SW-Sync Word

ISW-Inverted SW

M1-M6

Mantenance Channel

MTC-20276 INTQ

M1 M2 M3 M4 M5 M6

Frame1 EOC a1 EOC a2 EOC a3 ACT 1 1

Frame 2 EOC dm EOC i1 EOC i2 PS1 1 FEBE

Frame 3 EOC i3 EOC i4 EOC i5 PS2 CRC 1 CRC 2

Frame 4 EOC i6 EOC i7 EOC i8 NTM CRC 3 CRC4

Frame 5 EOC a1 EOC a2 EOC a3 CSO CRC 5 CRC6

Frame 6 EOC dm EOC i1 EOC i2 1 CRC 7 CRC8

Frame 7 EOC i3 EOC i4 EOC i5 SAI CRC9 CRC10

Frame 8 EOC i6 EOC i7 EOC i8 1 CRC 11 CRC 12

3 quaternary symbols per frame are

transmitted to convey maintenance and

embedded operations channel informa-

tion. This information is contained in a

superframe consisting of 8 frames (dura-

tion: 12 ms). The start of a superframe

in up and downstream directions is mar-

ket by a single inversion of the synchro-

nisation word (ISW). The quaternary

symbol sequences represent data that

can be transmitted at a rate of 4 kbits/s.

They are transmitted immediately before

the sync word (SW).

The M symbol is used for various pur-

poses incluiding:

1. Maintenance Channel (control test

loops and report frame errors)

2. Service channel (carry transparent

user data in both directions)

In detail the following convention

applies (NT to LT):

Maintenance and Service Channel

Service and Maintenance Data Convention

Table 13: Messages required for command/response EOC mode

Table 12

origin (o) & destination (d) & transfer (t)

Message Message Network NT1 REG

code

Operate 2B+D Loopback 0101 0000 o d t/d

Operate B1-channel Loopback (note) 0101 0001 o d t/d

Operate B2-channel Loopback (note) 0101 0010 o d t/d

Request Corrupted CRC 0101 0011 o d t/d

Notify of Corrupted CRC 0101 0100 o d t/d

Return to Normal 1111 1111 o d t/d

Hold State 0000 0000 d/o o/d o/d/t

Unable to Comply Acknowledgement 1010 1010 d o t/o

Note: In order to perform B1 or B2 channel loopback, the S-bus of the MTC-20276 needs to be fully activated.

Encoding

The encoding of a binary bit stream is

such that 2 binary bits correspond to 1

quaternary symbol. The first symbol of a

frame will always contain the informa-

tion of the first 2 bits of a B1 channel

(although these bits are of course scram-

bled).

MTC-20276 INTQ

Quaternal Symbol First bit (Sign) Second Bit (Magnitude)

+3 1 0

+1 1 1

-1 0 1

-3 0 0

Table 15

In the receive direction, the first symbol

of the quaternary frame is always con-

verted (after descrambling) into the first

two bits of a B1 channel.

The exact convertion is done according

to the following rules (ANSI specifica-

tion):

Symbol Description

ACT Activation bit (set to ONE during activation)

CRC Cyclic Redundancy check: covers 2B+D & M4:

1= most significant bit;

2= next most significant bit, etc.

CSO Cold-start-only bit (ONE indicates cold-start-only)

EOC Embedded operations channel:

a = address bit;

dm = data/message indicator;

i = information (data/message).

FEBE Far end block error bit (ZERO for errored multiframe).

NTM NT in test mode bit (ZERO indicates test mode).

PS1/PS2 Power status bits (ZERO indicates power problems).

SAI S-activation indicator bit (optional, set = 1 to activate S/T

Note: Transmission errors in the data

protected by the Cyclic Redundancy

Check are detected during each super-

frame and reported back to the LT in the

next superframe.

This is for loop quality checking only

and does not invoke retransmission of

any sort.

Table 14

Activation and Deactivation

In order to reduce the power consump-

tion of circuits connected to the sub-

scriber line, INTQ can be switched to

stand-by or powered down during idle

periods. The components are powered

up again during the line activation pro-

cedure. Two states are defined:

- Power-down state

Power consumption of the majority of

the functions is reduced by stopping the

clocks; maximum power reduction;

- Power-up state

All functions powered up; GCI interface

is activated; exchange of C/I messages

is possible.

The activation procedure consists of

three phases:awake ( see the following

sections), synchronise, and connect

through.

Maximum activation time (from com-

mand ACT to indication CT) without

repeater:

≤170 ms under normal conditions

(starting with stored coefficients)

1 s after reset of the coefficients.

The deactivation procedure consists of

two phases:line deactivation of the NT

can be initiated only by INFO U0.

Deactivation time (from Command

DEAC to Indication DC) is in the order

of 4 ms.

Reset

The INTQ can be reset via an external

pin (NRESET = LOW) or via the com-

mand RES in the C/I channel. Normally

the INTQ is reset via the pin NRESET

(hardware reset).

Both reset requests cause a reset for var-

ious function blocks via the

activation/deactivation control and the

reset logic. The INTQ is initialised such

that a “cold start” (resetting of the coeffi-

cients) is possible.

Analog Loop (Loop 2 in NT)

For maintenance purposes a loop can

be closed by applying the correct com-

mand into the M channel or into the

GCI C/I channel, described in the next

section.

MTC-20276 INTQ

Scrambling

The received binary data stream is

divided by generating polynomials.

The scrambler contains supervision cir-

cuitry which flags if a continuous series

of ones or zeros have been detected at

the output for a complete 1 ms frame.

Descrambling

The quaternary signals received on

each side of the subscriber line are con-

verted back into a binary bit stream

and multiplied by the generating poly-

nomials in order to recover the original

data.

-1

-18

Ds.X

-23

Ds.X

: XOR function

-18 -23

Ds = Di Ds.X Ds.X

Fig.10: NT Transmit Scrambler

-1

-5

Ds.X

-23

Ds.X

: XOR function

-5 -23

Ds = Di Ds.X Ds.X

Fig.11: NT Receive Descrambler

GCI Interface, Common Functions

MTC-20276 INTQ

Data Format and Timing of the GCI Interface

(DIN, DOUT, DCLK, DFR)

Continuous Modes

Nominal bitrate of data (DIN and DOUT) 256 kbit/s

Nominal frequency of clock (DCLK) 512 kHz

Peak-to-peak output jitter (DCLK) ≤166 ns

Nominal frequency of frame clock (DFR) 8 kHz

Mark-to-space ratio of DFR, i (input) 1:2 . . . 2:1

Mark-to-space ratio of DFR, o (output) 0.4:0.6 . . . 0.6:0.4

Figure 13 shows the timing of data and

clocks at the digital interface 256 kbit/s

(continuous modes).

Transitions of the data occur after even

numbered rising edges of the DCLK.

The data is valid on the odd

numbered rising edges of the DCLK.

Even-numbered rising edges of the

clock are defined as the second rising

edge following the rising edge of

the frame clock and every second rising

edge thereafter.The maximum allowed

jitter is shown in figure 14.

The start of the frame is marked by the

rising edge of the frame clock DFR.

One frame contains four time slots. The

data streams at DIN and DOUT consist

of four bytes per frame. See figure 15.

The input data DIN and the output data

DOUT are synchronous and in phase.

In the power-down state, the signal at

DIN and at DOUT is high and the sig-

nal at DFR and DCLK is low.

Fig.12: Timing of Data and Clocks at the GCI Interface

The GCI Interface

At the digital control interface the S-inter-

face block is connected via a bidirec-

tional serial interface, a digital bus

called the General Circuit Interface

(GCI), also called the ISDN Oriented

Modular (IOM) interface. This bus is log-

ically organized as many parallel point

to point links, each at 256 kbit/s. The

description of the GCI is available in the

related documents and on page 23.

The Physical Organization of

the GCI Bus

The bus has a clock and frame signal as

timing, and two data lines, one for each

direction.

In NT mode the S-interface receives the

GCI timing.

General Content of the

GCI Bus

The GCI interface is organized with 4

channels at 64 kbit/s: B1, B2, M

(Maintenance or Monitor), and B1*

channel.

The B1 and B2 channels are transpar-

ent, switched at 64 kbit/s.

In ISDN applications the B1* channel

contains two D-channel bits, 4 bits C/I

channel with the commands (towards S-

interface) or the indications (from S-inter-

face), and two extra bits (MR and MX)

to control the M-channel.

The D-channel contains HDLC messages.

It is transported transparently (NT) or ter-

minated by an HDLC transceiver (LT-

S/LT-T/TE). In the TE/LT-T a D-channel

access protocol exists on the S-bus,

which must be controlled by the S-inter-

face, and obeyed by the HDLC transmit-

ter.

Via the Command/Indication (C/I)

channel, Commands to, and state Indi-

cations from the S-interface are

exchanged with a control element

(microcontroller) or with another uplink

or downlink ISDN circuit. Commands

and Indications are debounced to avoid

erroneous behaviour.

The M-channel is a 64 kbit/s channel. It

has a byte oriented structure, and the

content is indicated and acknowledged

with the MR and MX bits, the two last

bits in the B1* channel. Content of the

channel: write and read access of inter-

nal S-interface registers.

Power-down on GCI

For maximal power saving the GCI bus

can be halted completely, and reactivat-

ed asynchronously from either side of

the bus.

Frame Format

4 bytes are transmitted in each frame:

1st byte B1:

B-channel (64 kbit/s data), transparent

2nd byte B2:

B-channel (64 kbit/s data), transparent

3rd byte B2*:

Monitor channel, DIN: 8 bit address,

MSB first, DOUT: 8 bit data

4th byte B1*:

2 bit D-channel (16 kbit/s data)

4 bit C/l channel A1, A2, A3, A4

A, E bit used to control the transfer of

information on the Monitor channel

Fig.14: GCI Frame Format

MTC-20276 INTQ

Fig.13: Maximum Admissable Peak-To-Peak Input Jitter of Clocks

(DCLK, DFR) at the GCI

MTC-20276 INTQ

External GCI Interfaces

G1 External GCI Interface

Figure 16 shows a schematic represen-

tation of the two possible modes of the

GCI ports.

In normal mode, corresponding to pin

GMODE low, the two internal GCI inter-

faces are connected. The G1 interface is

used as a monitorpoint.

In NTplus mode, corresponding to pin

GMODE being high, the GCI interface

coming from the U-interface block is con-

nected to the G1 External GCI.

The S-interface block is connected to the

G2 External GCI.

The U-interface block is the master of the

GCI interface and thus controls the GCI

clock (DCLK) and the GCI frame (DFR).

DCLK and DFR signals at the G1 inter-

face are outputs of the INTQ.

G1 interface characteristics:

- G1 DOUT: output, data channel,

256 KHz

- G1 DIN: input in NTplus mode,

output in normal mode; data channel,

256 KHz

- G1 DFR: output, frame clock, 8 KHz

- G1 DCLK:output,clock, 512 KHz

G2 External GCI Interface

In normal mode, corresponding to pin

GMODE low, the two internal GCI inter-

faces are connected together. G2 inter-

face has no function.

In NTplus mode, corresponding to pin

GMODE high, the GCI interface of the

S-interface block is connected to the G2

External GCI.

The S-interface block is the slave of the

GCI interface, so the GCI clock (DCLK)

and the GCI frame (DFR) signals at the

G2 interface are inputs of the INTQ .

G2 interface characteristics:

- G2 DOUT,: output, data channel,

256 KHz

- G2 DIN,: input, data channel,

256 KHz

- G2 DFR: input, frame clock, 8 KHz

- G2 DCLK: input, clock, 512 KHz

Fig.15: External GCI Interface

MTC-20276 INTQ

Awake 0000: AW This command is to be used when the deactivated module interface is to be set in

the power-up state. The control may be represented by a steady-state binary ‘0’

condition at DIN. The module interface will be activated, i.e. provided with bit and

frame clocks for synchronous transmission.

Any other command may now be applied.

The command AW, however, maintains the activated state of the module interface

without emission of any signal at U0.

Activate 1000: ACT Layer 1 is activated at the U0 interface, starting with transmission of the wake-up

signal INFO U1W. After execution of the wakeup procedure, the transmitter

generates INFO U1A during synchronization process. When synchronization is

completed successfully, the transmitter outputs INFO U1.

Synchronized 1100: SY When the synchronization process of the receiver is completed successfulIy, the

transmitter outputs INFO U3. After reception of INFO U4H, Connect Through (CT)

is indicated and the INTQ will be connected through from module interface to line

interface (transparent).

Deactivate 1111: DC This control has to be used if the reciever is to be able to recognize awake-

Confirmation signals at interface U0, but the transmitter still is disabled. If no wake-up signal is

recognized, the INTQ is set to its power-down state. The module interface will

be deactivated.

The evaluation of any command is done

according to a double last look criteri-

on: any command is recognized only

after the same command has been

detected in two successive frames. Until

then the preceding command is consid-

ered valid.

If commands are received that are not

included in the list, the last recognized

command is considered valid. Com-

mands which are logically impossible to

receive in the current state are ignored

(ref. TS 102 080).

The indications are transmitted continu-

ously in each frame. Under no circum-

stances can an indication that is not

included in the list be transmitted.

The maintenance and Service Channel,

and the B2* Channel are not used by

the U-interface block.

U-Interface Command List

Command and Indicate (C/l) Channel (A bits)

Command (DIN) (from GCI to U).

Table 16

MTC-20276 INTQ

Indication (DOUT) (From U to GCI)

Deactivate 0000: DEAC A request to deactivate level 1 (INFO U0) has been detected. INFO U0

is transmitted at U0.

Test mode 1 0010: TM1 Forces S-interface in test mode 1, sending single zeros.

Not supported by the U-interface but recognized by the S-interface (NT mode only)

Resynchro- 0100: RESYN The receiver has lost framing and is attempting to resynchronize. The INTQ

nization remains connected through from module interface to line interface (transparent).

Activate 1000: ACT The synchronous state of the receiver is established (without a loop 2 or a loop 4

command). The transmitter outputs INFO U1.

Loop 2 1010: L2 The synchronous state of the receiver is established with a loop 2 command.

The transmitter outputs INFO U3.

Connection 1100: CT INFO U4H has been detected at the U-interface.

Through The INTQ will be connected through from module interface to line interface

(transparent).

Connection 1110: CTL2 INFO U4H and a loop 2 command have been detected at the U-interface.

Through The INTQ will be connected through from module interface to line interface

with Loop 2 (transparent).

Deactivated 1111: DC The transmitter is disabled, but the receiver remains enabled to detect wake-up

Confirmation signals at the U-interface. The INTQ is set in its power-down state, as long as

wake-up signals are not recognized.

When a wake-up procedure is finished, INFO U1A is transmitted.

Power Down of the Interfaces

In the following description, the U-inter-

face port of the GCI interface (G1) is the

master, and the S port of the GCI (G2)

is the slave.

Transition from Synchronous

to Power-Down State

The corresponding procedure is shown

in figure 17. After a DC code has been

detected at the module interface of the

master in two successive frames from the

slave, the master responds by indicating

DC four times and then the master turns

off the timing signals at the end of bit

A4 of the fourth DC indication. After this

time, the DOUT pins of master and slave

must be kept HIGH (quiescent condi-

tion).

MTC-20276 INTQ

Wake-up Originated by Slave

Transition from power-down to

synchronous operation is initiated by

the slave by transmitting LOW at

DOUT. See the figure above.

The master responds by turning timing

signals on within the wake-up time

Taw (typical 4 ms, max. 10 ms). To

ensure continuous supply of timing sig-

nals by the master the slave must keep

DOUT LOW.

After the timing signals have been

detected by the slave, the slave must

transmit AW for at least two frames

(e.g. 8 frames). Then the slave may

insert a valid code in the C/I channel

(e.g. ACT).

Monitoring of pin DOUT for LOW by

the master will start only after the tim-

ing signals have been turned off.

Fig.16 Transition to Power-Down State

Wake-up Originated by the

Master

Transition of the device from power-

down to synchronous state can

be initiated by the master by turning on

clock signals DCLK and DFR. Simultane-

ously, the master must apply the desired

command code in the C/I channel.

The slave may enter the power-up

state immediately after clock signals

have been applied, and the received

command code has been evaluated.

See figure 19.

MTC-20276 INTQ

It is required that the clock signals at

DCLK and DFR will have the nominal

frequency with the specified tolerance

from the moment they are turned on.

The slave may deactivate the master if

only AW (not yet ACT) has been detect-

ed by the DC command or by transmit-

ting continuous HIGH at DOUT. The

master will respond by turning off the

timing signals. See figure 18.

Fig.18: Wake-up Initialisation Procedure, downstream

Fig.17: Wake-up Initialisation Procedure, upstream

S-Interface Commands and Indications Summary.

Table 17

Commands (Downstream) in NT Mode

Table 18

0000 DR Deactivate Forces the S-interface block to deactivate the S-bus (=INFO0)

Request followed by DIu and did=DC

0001 RES RESET Forces S-interface to soft reset, extended mode only,

S-interface accepts it in basic mode (merged)

0010 ssz TEST-MODE 1 Forces S-interface to test-mode 1, sending

= TM1 single zeros

0011 TM2 TEST-MODE 2 Forces S-interface to test-mode 2, extended mode

only, sending continuous zeros.

0100 RSYd Resynchon- The U-interface is not synchronous,

izing down S-interface sends INFO2 {or SCZ}, see remark 1 below

1000 ARd Activation MTC-20172 S-interface forced to INFO2 transmission,

Request down receiver indicates the S-bus reaction

1010 ARL Activat. req INFO2 transmission on the S-bus

with S-loop test loop2 switched (transparent loop)

1100 AId Activation INFO4 transmission, normally only after

Indication AIu indication is received

1110 AIL Activ. Indic. INFO4 transmission

with S-loop test loop2 switched (transparent loop)

1111 did= Deactivate Deactivation confirmation, entering the

DC Confirmation power down state, INFO0 sent, critical

timing to halt the clocks.

Remark 1: When the U-interface is

resynchronizing, the S-interface will

send INFO2.

Remark 2: During loops, the S-inter-

face simply ignores the incoming

INFO3 from the S-bus. The receiver syn-

chronizes on looped INFO2/4.

MTC-20276 INTQ

NT Downstr Upstr. Downstr Upstr.

Command Indicat. Command Indicat

0000 DR TIM 1000 ARd ARu

0001 RES (lsl) 1001 - -

0010 ssz=TM1 - 1010 ARL -

0011 TM2 - 1001 - -

0100 RSYd RSYu 1100 AId AIu

0101 - - 1101 - -

0110 - ei 1110 AIL -

0111 - - 1111 did=DC DIu

MTC-20276 INTQ

Indications (Upstream) in NT Mode

Table 19

0000 TIM Timing The S-interface requires GCI clocks.

Request

0100 RSYu Resynchron- The S-bus receiver tries to synchronize

izing

0101 --------- --------- ---------

0110 ei Error RSTB and SCZ- pin both low simultaneously

Indication

1000 ARu Activation INFO1 received (actually any AMI signal)

Request up

1100 AIu Activation Receiver synchronized on INFO2/3/4

Indication up (INFO3 normally, INFO2/4 in loop)

1111 DIu Deactivation Timer (32 ms) expired, or INFO0 received

Indication (16 ms) after DR (deactiv. request)

For transmission of data over the sub-

scriber premises, the S-interface pro-

vides the S0-interface. This interface

enables full duplex transmission of data

(2B + 1 D-channel) over 4 wires at a

nominal data rate of 192 kBits/s. An

Alternating Mark Invert (AMI) code is

used for the line transmission. The trans-

mission of data over the S0-interface

consists of frames of 250 µs. Each

frame is 48 bits wide, and contains 4

data bytes (2 B1, 2 B2) and 4 D-bits.

The frame structures are shown in

fig.20.

A frame start is marked using a first

code violation (no mark inversion).

To allow secure synchronization of the

receiver, a second code violation is gen-

erated before the 14th bit of the frame.

To guarantee this second violation, an

auxiliary framing bit pair FA and N

(from NT to TE) or the framing bit FA

with associated balance bit (from TE to

NT) are introduced.

The first bit of the transmitted frame from

TE to NT is delayed for 2 bit periods

with respect to the frame received from

the NT. Furthermore, an echo bit (E-bit)

for the D-channel and an activation bit

(A-bit) are provided, where DC-balanc-

ing is done by means of the L-bits.

The S-Interface

Functional Overview

General Description

of the S-bus Interface

The S-interface can be used on the S-bus

configured as a point-to-point connec-

tion or as a passive bus. The bus con-

nection can handle up to 8 terminals. It

is either a short bus with the terminals

dispersed over a length of 200m, or

an extended bus with a cluster of termi-

nals within a 25 m range.

The chip handles full-duplex transmission

of two B-channels (64 kbit/s each) and

one D-channel (16 kbit/s). It handles

also the echo E-channel, the multifram-

ing S and Q bits, ...

The S-interface contains all circuit parts

necessary for the adaption of the S-inter-

face, especially transmitter and receiver

stages.

- S-bus outputs are balanced, allow

ing bus operation;

- S-bus inputs are balanced;

- Out-of-band noise is filtered;

- RX has AGC and an adaptive

threshold, and corrects long-line

distortion by optimizing the sample

moment.

- NT receiver bus type is selectable:

short bus with fixed timing, or adap-

tive timing for extended bus or point to

point.

The S-bus tranceiver stages must be con-

nected to the bus via external interface

circuitry (2:1 transformer) and protec-

tion. When the S-interface is in unpow-

ered state (supply voltage = 0 V) the S-

bus transmitter is high ohmic (see CCITT

I.430).

MTC-20276 INTQ

N : = FA

B1 : BIT OF CHANNEL B1

B2 : BIT OF CHANNEL B2

A : ACTIVATION BIT

S : S-BIT

M : MULTIFRAMING BIT

F : FRAMING BIT

L : DC BALANCING BIT

D : D-CHANNEL BIT

E : D-CHANNEL ECHO-BIT

FA : AUXILIARY FRAMING BIT

D L. F L. B1 L. D L. FA L B2

L. D L. L. D L. L. D L. F L.

D L. F L. B1 E D A FA N B2

ED M B1 E D S B2 E D L. F L.

2 BITS OFFSET

NT to TE

TE to NT

B1 B2

Fig.19: So-Frame Format

MTC-20276 INTQ

The S -interface can be used in a point-

to-point and in a point to multipoint con-

figuration (including extended passive

bus). In the first configuration, the length

of the cable is limited to aprox. 1.2 km

(see fig.21).

In the bus configuration (point to multi-

point), up to 8 terminals may be con-

nected to the S0-interface (fig.22)

The terminals must be connected in a

range of 150 m. For the extended pas-

sive bus, the terminals must be clustered

within a 25m range with a maximum

cable length of about 1 km.

To avoid bus mismatching when multi-

ple TEs are connected, the driver stages

present a high impedance when they

are not powered.

Controlled access to the shared data

channels is realized within the S-inter-

face by a D-channel access procedure.

Each terminal can be given a certain

priority for D access. Via the echo bit,

which is the reflection of the received D

channel at the NT, it is possible for the

terminal to detect the status of the D-

channel. In order to try to gain access

over the D-channel, a terminal has to

see 8 to 11 consecutive ones in the

echo-channel. The exact number

depends on the priority given to the ter-

minal. When several terminals try to

gain access at the same time, collisions

occur on the S-bus. The terminal that

transmitted "one" but sees a “zero” in

the echo channel detects the collision

and loses the D-channel access.

The terminal that transmitted the "zero"

gains the access. When a successful D-

channel message is transmitted, the pri-

ority is decreased by 1 in order to guar-

antee fairness with the other terminals.

The status of the D-channel of the TE/LTT

is at the 5th bit position of the monitor

byte. This enables the control of the D-

channel by an external HDLC controller.

S i/f

<= 1.2 Km

RS i/f GCI

GCI

TE/LTT NT/INT

Fig.20: Point to Point Configuration

<150 m

RGCI

S i/f

TE # 1

S i/f

TE # 8

MAX 8

RTERMINATING RESISTOR

of 100Ω

NT/INT

S i/f

Fig.21:Point to Multipoint Configuration

MAX 8

S-Interface

General Overview

The block diagram of the S-interface is

shown in fig.22.

Data from the So-interface is received

by the S-interface receiver, which has

a balanced input, an AGC stage, a fil-

ter and comparators with dynamically

adapted thresholds. The timing of the

received S0-frame is fixed (Only NT).

In the fixed timing case, the timing is

locked to the transmitted frame, and

the tolerable phase delay on the

received So-frame is limited. In adap-

tive timing mode, delays up to 48 µs

can be tolerated. The start of the

received frame is detected in the FL-

detection unit. An adaptive algorithm

is used for compensation of the slope

of the FL transition. A digital PLL recov-

ers the received bit clock (192 kHz).

A second digital PLL generates the

transmit bit clock (192 kHz), which is

locked to the GCI frame. It is possible

to compensate external circuits (e.g.

filters) by adjusting the internal phase

of the bit clocks by means of a register

accessible by the monitor channel.

These circuits work with a 7680 kHz

±100 ppm clock. This clock is internal-

ly delivered to the S-interface by the U-

interface block.

The serial B and D data from the V*

GCI digital-interface is stored into a

buffer with a dynamic pointer struc-

ture, and is presented to the S_trans-

mitter where the So-frame formatting is

done. In the other direction, the

S_receiver unit disassembles the

received So-frame.

The B and D data are stored in the

buffer and multiplexed together with

M, C/I, MX and MR into a digital V*

GCI frame. The pointer structure of the

buffer guarantees a minimum round-

trip delay. If the clock wander

becomes too big, a warning is given

in the C/I channel, and the internal

pointers are reinitialized.

Activation/deactivation procedures

are handled in the status controller.

Two basic modes are available:

A V* mode, compatible with the U-

interface block, and a GCI compatible

mode. The S-interface automatically

selects the connect mode.

The S/Q control module handles the

multiframing on the S and the Q chan-

nel of the So-interface. This function is

disabled in the INT.

In order to reduce the power consump-

tion of the components connected to

the subscriber line, the S-interface

are switched to a power down mode

during idle periods.

MTC-20276 INTQ

Analog

transmitter

s_transmitter

DPLL

s_receiver

FL detection

M control

buffer

S/Q control

activity

detector 7680 kHz

oscillator asynchronous

power up/down

V*/GCI

DIN

DOUT

DFR

DCLK

status

controller

Analog

receiver

MUX

C/I

S, Q

B, D

S, Q

B, D

CHP boundary

XTI from U side

Fig.22: Block Diagram of the S-interface

Test Modes Summary

Test loops may be closed in the S-inter-

face, where all three channels (B1, B2

and D) are looped back as close as

possible to the So-interface.

Loop 2 is a transparent loop where the

transmitted So-frame is also switched

on the S-bus. Activation from the So-

interface is not possible.

Both loops are initiated over the C/I-

channel and under control of a layer 2

component.

For further testing of the subscriber line,

two test signals can be transmitted over

the So-interface: A 96 kHz test

sequence sending continuous AMI

marks, and a 2 kHz test sequence

sending single AMI marks. Both test

modes are under control of the C/I

channel, as well as TSP pin.

GCI Clock Synchronization in

the ISDN Environment for the

Upstream S-Interface (NT)

In general the downstream devices are

slaved to the upstream devices.

The S-interface is master of the S-bus,

and can sample the received (upstream)

S-bus frames with a receive clock at

exactly the transmit frequency, but with

an unknown phase.

The S-interface receives the GCI timing,

and must derive the 192 kHz S-bus bit-

clock from it. As the GCI timing is not

necessarily a multiple of 192 kHz, the

S-interface generates a 192 kHz TX and

RX clock from a clock input at 7680

kHz +/- 100 ppm. The 192 kHz is not

a pure divide by 40 of the X-tal, but is

locked to the 8 kHz frame signal of the

GCI-interface. This is a DPLL action

where the 192 kHz clock period can be

adjusted 1/40 of the 192 kHz clock

period every 250 us. Note that jitter on

the 192 kbit S-bus signals is a combina-

tion of the jitter on the 7680 kHz before

the DPLL and the effects of the DPLL lock-

ing to the GCI 8 kHz frame.

The S-bus RX clock in fixed timing (short

passive bus) is derived from the same

clock input with the same frequency cor-

rection as the transmit clock, but with a

phase offset. The corrections of 1/40 of

a bit period are used in open loop here.

The S-bus RX clock in adaptive timing

(extended bus, point to point) is also

derived from the same master clock.

However, the receiver must optimize the

symbol sampling moment. This is an

extra phase correction, which tracks

wander and jitter of the received data.

The receiver tracks the RX data by lock-

ing on the F/L transitions.

Note: The timing stays identical for an

internal loop from TX to RX, because

then the S-interface uses adaptive RX

timing as well. Even an external S-bus

loop can be applied, provided that the

receiver does NOT work with fixed RX

timing.

Conclusion: the S-interface block has 3

different clocks, which are locked in fre-

quency, but with unknown phase rela-

tion. Because the clocks are derived via

DPLL blocks the phase relation is not

constant, but has some jitter and wan-

der.

Clock Speed

The master clock runs at 7680 kHz +/-

100 PPM.

Internally the S-bus transceiver part runs

at 192 kHz, derived from the master

clock, but locked to the ISDN network

clock with a phase locked loop, adjust-

ing one 7.68 MHz period every 250

us. The ISDN network clock is sent

downstream via the S-bus or the GCI

interface.

The GCI part runs at the clockspeed of

its interface, which is 512 kHz in NT

mode.

Power Saving/Deactiv-

ation of the S-Interface

The S-interface is controlled via the GCI

interface. This interface is designed to

be shut down and consequently reacti-

vated. Shutting the bus down is com-

manded by the controller on the bus.

Once the command is acknowledged,

there exists a fixed procedure to halt the

clock (by the controller in NT). Reacti-

vating the bus can be done by the S-

interface or the controller.

When the GCI bus is going to be shut

down, the S-bus transceiver is put to idle

also. The S-bus transceiver enables an

asynchronous signal detector, which

can reactivate the S-interface on receipt

of INFO via the S-bus. Then the S-inter-

face shuts down the internal 7.68 MHz

clock distribution. If the clock is external-

ly provided it can be put to idle also,

after the GCI bus has become idle.

The S-interface can receive activation

via the S-bus during the process of shut-

ting down via the GCI bus.

Activation of the

S-Interface in NT mode

Activation through the S-bus will be seen

by the signal detector. The S-interface

does not need a GCI clock to activate

the GCI interface, which it does by

asynchronously pulling the data line

low. The master on the bus answers

with GCI and frame, followed by com-

mands via the C/I channel. The bus

master also delivers the 7.68 MHz fre-

quency simultaneously with GCI activa-

tion.

Activation through the GCI bus consists

of clock and frame delivery, followed

by commands via the C/I channel. The

S-interface will activate the S-bus trans-

ceiver according to the commands,

including the internal clock distribution.

If the master clock must be delivered to

S-interface. Note that the internal clock

distribution to the S-tranceiver section is

delayed for 2 ms (using the GCI frame-

clock).

MTC-20276 INTQ

Introduction

In this section, external and internal

operational details of the S-bus interface

are given. Detailed interface timing and

electrical specifications are given in

related documents.

General Characteristics

The S-interface realizes full-duplex trans-

mission of two B-channels (64 kbit/s

each) and one D-channel (16 kbit/s).

Additionally the S-interface allows con-

trolled access to the common D-channel

and the activation/ deactivation of each

connected device.

Transmission Rate

The nominal transmission rate is 192

kbit/s in each direction. There is no

requirement for special bit sequences in

the B-channels.

Frame Structure

Data is transmitted within a frame of 48

bits in each direction. The nominal

frame period is 250 us which gives a

frequency of 4 kHz. The frame structure

is not depending on ’bus’ or ’point-to-

point’ configuration.

AMI S-bus Coding

For both directions a pseudo-ternary

coding (AMI) is used. A binary ’1’ (high

level logic) is coded as ’no signal’

whereas a binary ’0’ sequence is repre-

sented by alternating positive and nega-

tive pulses.

The polarity inversions, coupled with a

minimal density of marks per frame,

reduce the low frequency components

of the signal. The 4 kHz frame always

starts with a positive pulse (F-bit), fol-

lowed by a negative balance bit L.

Balance Bits

Inside the frame more balance bits are

present serving two purposes:

1) In both directions they guarantee that

the polarity of the first bit or F-bit is con-

stant. They also increase the mark densi-

ty on the link.

2) Moreover, in uplink direction the bits

in the frame can be generated by differ-

ent terminals. Therefore, the frame is

subdivided in groups of bits, each sent

by a single terminal and terminated also

with a balance bit. The first binary ’0’ of

each group of bits except for the fram-

ing signal is coded as a negative pulse.

The balance L-bit finishes those group

with a positive mark if needed, to avoid

violations of the mark inversion scheme.

This allows the different B and D chan-

nel bits to be sent by different transmit-

ters on a bus, because the AMI polarity

is always fixed. Thus no AMI violation

can be caused by the multipoint nature

of the bus.

AMI Violations for

Frame Synchronization

For synchronization purposes the AMI is

violated twice per frame. A 48 bit

frame always starts with a positive pulse

(F-bit) followed by a negative balance

bit L. The F-bit is a violation, because

the last mark of the previous frame is

positive also. The first binary ’0’ follow-

ing a framing signal (F, L) is always

negative, and is a second violation.

Frame Synchronization

Distance Rule

There are two AMI violations in the

frame: the F-bit at the beginning is at a

fixed position. The second violation

must follow the F-bit within 13 bit posi-

tions, because the frame contains an FA

(auxiliary flag) at position 14, which is

a binary 0, even if all other bits (2 to

13) are binary one. After the FA the

next violation will be the F flag itself, at

a distance much larger than13 bit posi-

tions. This distance rule allows for fast

and reliable frame flag detection.

Frame Synchronization

Multiframing Exceptions

AMI violation delay in multiframing:

At the TE/LT-T position the received FA

bit is occasionally a binary 1 in case

of multiframing. However, then the N

bit at position 15 is a binary one,

because it is the binary inverse of the

FA. This guarantees a second violation

within 14 positions after the F-bit.

AMI violation exception in multiframing:

At the NT/LT-S position the received FA

bit is occasionally a binary 1 in case of

multiframing. FA is followed by a bal-

ance bit L, which is then also at binary

1. If all B and D bits between F-L and

FA-L are also at binary 1, then there is

no second violation within the 14 posi-

tions. If the remaining bits (B and D

channels) are also at 1 in the remain-

der of the 48 bit frame, then the second

violation will be absent and next F-bit

will be no violation! This can delay the

synchronization and could trigger an

invalid loss of synchronization.

The delayed synchronization during

multiframing is unavoidable. To avoid

an invalid loss of sync at the NT/LT-S

when multiframing is on, all incorrect

second violations (too late or missing) in

uplink direction are ignored if the FA bit

was a binary 1 in the corresponding 48

bit frame in downlink direction. Missing

violation at the F-bit position are

ignored if the preceeding 48 bit frame

(downlink) had the FA-bit at one.

MTC-20276 INTQ

Detailed Operational Description

of the S-bus Interface

Synchronization Principles -

Adaptive Bit Timing

1) The receiver first finds the AMI viola-

tions by oversampling.

2) Immediate bit-synchronization is

given by the F-L transition.

3) The distance rule of the next violation

within 14 positions is used to validate

the F-bit.

4) Frame synchronization is acquired

after 3 correct frames, with a correct F-

bit violation and a second one within

14 bit positions.

5) The F-L transition determines the

adaptive bit sampling.

6) At NT/LT-S loss of sync after two

frames not having F violation or second

violation following the distance rule (at

14 bits), when no multiframing is active.

The downlink signal stays active, but

changes automatically from INFO4 to

INFO2. In case of multiframing we

ignore missing second violation within

the 14 bit distance, or the missing viola-

tion at the next F-bit for uplink frames

with the corresponding downlink FA bit

at binary 1.

Synchronization Principles -

Fixed Bus Timing

On a short passive bus the position of

the bit sampling can be fixed.

The points 3), 4) and 6) of the previous

paragraph are executed. No oversam-

pling is done, no DPLL action is needed

to track the F-L adge.

Note that the fixed timing is changed

automatically to adaptive timing, when

internal S-bus loops are commanded.

When external S-bus loops are used

(e.g. for production test) only adaptive

timing is suitable!

Pulse Polarity in the S-bus

Frame

The receiver is polarity independent.

The transmitter in NT mode has no

polarity requirements.

Table 20

Transmitted Frames

In the MTC-20276, the S-interface can

transmit different signals called INFO 0,

2, 4 and 2 test signals.

The B-channel and D-channel are trans-

parently transmitted on the S-bus. When

idle those channels are all binary 1.

Details on Downlink Frames

The downlink frames transmitted by

upstream devices contain an E-bit.

During INFO4 the E-bit is the echoed

D-channel-bit received from the down-

stream devices. This D-echo-channel is

used for D-channel access procedure.

Two L-bits are used for DC-balancing,

after the F-bit and the last bit the frame.

In downlink direction some special bits

are used:

- A-bit used for activation (A=1 for

INFO4, A=0 for INFO2);

- S-bit coded as binary zero, if no multi-

framing active;

- N-bit coded as N = .NOT. FA (applies

to INFO2 and INFO4);

- M-bit at binary zero, except when mul-

tiframing;

- FA-bit, additional flag (bin. zero),

except when multiframing.

Without multiframing active S, FA, M

bits are binary zeros. Multiframing is

allowed to be active during INFO2 and

INFO4 and influences the S, FA, M bits.

Details on Uplink Frames

The INFO3 frame transmitted at termi-

nal-side consists of several groups of

bits, each of them DC-balanced by an

adjacent symmetry bit L.

The uplink D-channel requires an access

protocol. Downlink multiframing influ-

ences the FA-bit in uplink (Q-channel):

If the S-interface receives the FA-bit as

binary 0 (electrical mark) it will always

answer with binary 0.

If the S-interface sees the FA-bit as bina-

ry 1 it answers with binary 1, when mul-

tiframing is not active.

MTC-20276 INTQ

Signals from network to terminal Signals from terminal to network

INFO0 No signal, open circuit INFO0 No signal, open circuit

INFO2 Frame with all bits of INFO1 Continuous signal with

B, D, and E-Echo channels, the following pattern:

and A bit at binary zero, positive zero,

FA, M, S, N and L bits negative ZERO, six ONEs

follow the coding rules

INFO4 Frame with operational INFO3 Synchronized frames with

data on B, D, and E-Echo operational data on B, D

channels. Bit A set to channels. FA and L bits

binary ONE. FA, M, S, N, L according to normal coding

bits follow to coding

TEST1 Send Single Zeros (SSZ), TEST1 Send Single Zeros (SSZ),

AMI marks, 250 us distance AMI marks, 250 us distance

forced via pin (NT) or C/I forced via pin (NT) or C/I

TEST2 Send Continuous Zeros TEST2 Send Continuous Zeros

(SCZ), alternating marks, (SCZ), alternating marks

forced via pin (NT) or C/I forced via pin (NT) or C/I

S-bus Transmitter Timing

and Framing

The transmitter data are sent at 192

kHz. The 192 kHz are derived from the

master frequency of 7.68 MHz, by divi-

sion by 40. The transmitter framing is at

4 kHz. The timing is slaved to the down-

link clocks, the 4 kHz S-bus frame is

locked in phase to the available down-

link framing.

Transmitter Timing and Fram-

ing at the NT

With a DPLL the 192 kHz is locked to

the GCI interface, by synchronizing the

S-bus frame with the GCI frame. The

DPLL locks the falling edge of the F/L

frame signal on the GCI frame signal.

Jitter is according to the CCITT I.430

spec.

S-bus Reciever Timing

and Synchronization

RX Frame Sync and Bit Sam-

pling in NT Short Passive Bus

Mode

The bit-sampling moment is fixed, and

coupled with the TX bit clock, which is

derived from the master clock, and

locked to the GCI frame. The RX bit

counters (counting the position of the

uplink bits in the frame) are also locked

to the downlink/TX bit counter. Uplink

data are 2 counts late.

The fixed bit sampling moment is

advanced 5 periods of the 7.68 MHz

clock, before the edges of the S-inter-

face transmit data stream. This is need-

ed to allow an advance of 7% or 3

periods of the uplink data, allowed

according to the CCITT to be sent by TE

at zero distance, combined with a 1

period jump of the downlink data clock

derived from the master clock.

This relationship is valid on the S-bus

itself. Inside the S-interface the actual bit

sampling must be delayed to account

for the nominal delay of the external

transformer, the internal filters and dri-

ver delays. The total delay of the exter-

nal devices was estimated at 100 ns,

the internal delay is implementation

related.

The frame synchronization knows the F

position, and applies the rules

explained earlier (i.e. without over- sam-

pling). The NT in fixed bus mode can

be forced to loop the S-bus signals inter-

nally! Then S-interface applies adaptive

timing, to test a maximal functionality.

Frame Synchronization

Details in Adaptive Tim-

ing

During synchronization the device over-

samples the incoming bits with a fixed

threshold, which is at 33 % of the nomi-

nal pulse height, with AGC active.

First Violation Detection

The oversampling is done at the 7.68

Mhz master clock, or at a factor 40. A

simple voting technique is used to detect

a violation: the detector output incre-

ments a counter as long as the detected

bits are marks of the same polarity or

zeros. When a polarity change of the

marks is seen, the counter is cleared.

Whenever a sequence of more than

50 oversampled marks of the same

polarity are seen, the receiver decides

that a violation came in. The number 50

must not be too large, to allow synchro-

nization on signals with flat edges.

After finding a single violation, the over-

sampling looks for the mark-to-zero and

the subsequent zero-to- opposite-mark

transition which it uses to estimate the

actual F/L crossing; see next para-

graph.

Violation Validation

During the hunt for frame synchroniza-

tion the F/L transition forces the RX bit

sampling clock and bit counter in an

deterministic state, which is optimal. The

RX part now hunts for a next violation.

In fact the next mark must be a viola-

tion. This violation (polarity should be

opposite, but this is ignored) must arrive

before the counter indicates 14

received bits. If the second violation is

found before 14 received bits, the F/L

must be validated for 2 more consecu-

tive frames. In all following frames

the F/L transition is oversampled to lock

the RX bit sampling clocks with DPLL

movements of 1 period of 7.68 MHz. If

the F/L validation is not correct during

the 2 subsequent frames, the S-interface

restarts its hunt.

RX Bit Synchronization NT

Adaptive Bus

Bit synchronization is done only by

detection of the F-L zero crossing. This is

optimal for short busses and extended

busses, where multiple signal sources

are present, each with an independent

bit timing. Only the F/L is a ”stable”

combination of all electrical drivers on

the bus. For long point to point links the

same technique is used, although aver-

aging of all zero crossings would be

better, theoretically.

Each time the bit counters indicate the

reception of F/L, the RX part oversam-

ples the transition at 7.68 MHz.

The F/L crossing is used for several pur-

poses:

1) It gives an immediate estimate of the

RX data optimal sampling moment, after

a first violation is found, via oversam-

pling.

2) It indicates how to correct the RX 192

kHz sampling clock each frame by one

7.68 MHz period (DPLL action in adap-

tive RX sampling).

MTC-20276 INTQ

The ”F-L zero crossing” is not detected.

The S-interface detects the transition

mark-zero (instant t1) and the subse-

quent zero-opposite-mark (instant t2).

During the F/L bits the device oversam-

ples the incoming signal with a fixed

threshold, which is ALWAYS at 33 % of

the nominal pulse height.

In between t1 and t2 the RX part counts

”Y”, the number of zeros, ignoring pos-

sible marks. The zero count Y is less

than the t2-t1, because noise could

force marks to be seen by the receiver

during the interval.

The number ”Y” of intermediate zeros is

used to estimate the slope of the arriving

signal, to predict the edge of the F/L

transition. Y is limited to 15, which cor-

responds to a first order time constant of

2 us for the S-bus data, filtered by the S-

interface input filter. This is 2.5 times

slower than the worst case point to point

signal as specified in CCITT I.430.

Note that Y could be larger than 15 if

the zero crossing is sought on a mark

which is followed by a zero bit, i.e.

when the violation is not the F bit fol-

lowed by L.

Immediate Bit Synchroni-

zation at Instant t2

When the receiver is not synchronized

the receiver is oversampling and hunts

for violations.

The F/L crossing is found at instant t2

and the 192 kHz bit clock is preset to

predict an optimal sampling moment.

The data edge is estimated at instant

( t2 - 2.00*Y ).

The optimal sampling precedes the theo-

retical edge by 8 periods of the 7.68

MHz clock. The advance is needed to

allow a jitter of +/- 7% (15% or 6 peri-

ods of 7.68 MHz) of the data, allowed

according to the CCITT to be sent by

any TE, combined with a 1 period DPLL

correction needed at the NT to correct

for its own X-tal.

Continuous Bit Synchroniza-

tion at Each F/L Crossing

Once the receiver is synchronized on

the data, the F/L edge is used on each

frame to validate the sampling moment.

The oversampling clock is used in the

F/L window to validate the zero crossing.

At instant t2 (zero to opposite mark tran-

sition) the state of the counter generat-

ing the 192 kHz clock from the 7.68

MHz is compared with the optimal

value, which should be loaded for an

immediate bit synchronization as

explained above. If the difference (in #

of periods of 7.68 MHz) is -1, 0, or 1,

the counter is not changed, to provide

hysteresis. If the difference is larger, the

counters are adjusted with only 1 1/40,

to limit the DPLL reaction.

In this manner the sampling moment is

adjusted with one 7.68 MHz period,

every 250 us. At the TE this allows a

maximal frequency error of the X-tal of

500 PPM.

Timing Relation Between

RX and TX on the S-bus

in NT Mode

The delay between transmitted and

received frames at NT is 2 bits plus the

roundtrip delay across the S-interface,

in normal operation. Worst case delay

between downlink frames and uplink

frames is 42 us (see CCITT) or 8 bits.

Longer delays cause problems to cor-

rectly send the E-channel bits. In loop-

back mode, the delay is zero.

The receiver in NT is conceived to

accept any delay, while in adaptive

sampling mode. This is convenient when

looping the S-bus signals. E-channel

operation is only correct if the delay is 0

to 8 bits.

Frame Relation Between

GCI and S-Interface

If the S-interface is in the Network posi-

tion, the 192 kHz S-bus bit clock is

derived from the master clock, which is

locked to the 8 kHz frame of the GCI

bus.

The leading edge of the F-bit starts the

frame on the S-bus. The DPLL forces this

F-bit edge in a fixed range relative to

the frame signal of the GCI bus.

The F-bit start is situated in a 520 ns

zone starting with the edge beween

bit0 and bit1 on the GCI bus. The

uncertainty is caused by the DPLL

actions which will correct the 192 kHz

S-bus clock in steps of 130 ns, i.e. one

7.68 MHz period.

This phase relation optimizes the total

roundtrip delay on the S-bus for each B-

channel, if the GCI clock is 512 kHz.

The delay of the NT with S-bus looped

is only 125 us for both B-channels at the

GCI side.

E-Channel Generation

At the NT site the S-interfaceA mirrors

the uplink D-bits in the downlink E-chan-

nel. The purpose of the E-channel is to

control the D-channel access from multi-

ple TEs on the S-bus.

In INFO2 the E-bits are zero, in INFO4

the E-channel mirrors the preceding D-

channel bit received in the S-bus receiver.

The E-channel can be blocked to trans-

mit only 0 via DEX1 and DEX0 bits.

Multiframing - S and Q

Channels

The S-interface block supports multi-

framing according to I.430 but multi-

framing is disabled on chip.

MTC-20276 INTQ

S-Interface Programming

M-Channel Messages and Registers

In the INTQ, the S-interface block can

operate in its normal mode, or can be

selected to operate in a reduced func-

tion mode compatible with earlier

devices.

Introduction

In the S-interface block, the M-Channel

is used for the transfer of operation and

maintenance information:

The WRITE and READ operations of

internal registers;

- Test and identification registers;

- Mode registers, overriding the default

state, changing the modes without

having to change straps;

- Control registers to change auxilliary

inputs and outputs;

- Status registers, e.g. alarm and error

monitoring;

M-Channel Receiver and

Transmitter

In the S-interface the M-channel tran-

ceiver works half-duplex, with mes-

sages lenght 2 bytes, with the M-

channel going to idle after every mes-

sage, to allow a change of direction

in the S-interface M-transceiver.

General Content of

M-Channel Messages

In the S-interface block, the M-channel

messages are limited to double bytes.

The first nybble of the message is a

general address, defined in the GCI

standards. In the S-interface this

address nibble is limited to:

1000b, used to read or write internal

registers.

All other values are ignored.

S and Q Channel Messages

This feature is disabled on the INTQ.

Internal Register M-Channel

Messages

All internal register operations on the

M-channel are double byte messages.

Both READ and WRITE operations are

possible. After every operation, the

M-channel must go idle again.

Concatenation of double byte messa-

ges could result in errors. Messages

which are aborted are ignored. The S-

interface block debounces the different

bytes of the message.

A WRITE operation is a one way mes-

sage, acknowledged only via the MR

bit. However, every register can be

read. A READ operation results in an

answer, delivering the CONTENT.

The READ operation causes the two

directions of the M-channel to be

logically dependent! After the READ

message to the S-interface block the

incoming M-channel must return to

IDLE. The M-transceiver in the S-

interface block gives priority to the

delivery of the CONTENT before

it can handle the next incoming

READ/WRITE.

M-Channel Operations

M-Channel Format - Bit and

Byte Numbering Convention

The M-channel is a byte oriented chan-

nel. Bytes (also called octets) are trans-

mitted in ascending numerical order.

Within a byte the most significant bit is

transmitted first.

Byte Transfer Procedure

To transfer a message composed of sub-

sequent bytes on the GCI M-channel

each byte is presented by the transmitter

and acknowledged by the receiver. For

that purpose the two M-channels (to and

from the S-interface) have separate

handshake bits, the MR and MX bits in

the B1*-channel. The MX bit signals the

presence of new information in the M-

byte, the MR bit signals the reading of

the information by the receiver.

Idle M-Channel

The procedure starts from idle, where

MX and MR are both inactive at 1. The

M-channel content during idle is invalid

and should be at FFh. However, the idle

value received by the S-interface is

ignored.

Start of Message (SOM) and

First Byte Transfer

From the idle state a start of message

transmission is initiated by the sender

with the transition of the MX-bit from

inactive to the active state. The data to

be transmitted are passed in the M-byte

starting in the same frame as the MX-bit

activation. In normal operation the first

byte must be kept constant in the M-

channel until the SOM is acknowledged

by the receiver.

Acknowledge of the SOM

and First Byte

On detection of the SOM the receiver

will read the M-byte. It will acknowl-

edge reception, provided that identical

data were seen in the M-channel during

two consecutive frames. To acknowl-

edge SOM and the first byte, the MR bit

goes from inactive to the active state,

remaining there, until:

1) a next byte is transferred, with MX

indication, see next paragraph;

2) an EOM is signalled by the transmit-

ter;

3) the receiver wants to abort the mes-

sage.

Further Byte Transfers

In the case of the second byte transfer,

the sender must detect the transition of

the MR bit of the receiver from inactive

to the active state (negative edge 1 to

0), before transmitting the second byte,

see previous paragraph. The

sender indicates a new byte of informa-

tion by the transition of the MX bit from

active to inactive, for exactly one frame.

The data is valid in the same frame. The

next frame the MX bit goes from inac-

tive to active, and the valid data are

repeated. The data are thus repeated

for minimally two frames. The sender

repeats the data in all subsequent

frames until the receiver returns the MR

bit inactive, to acknowledge the data

(see next paragraph), or to abort the

message.

Further Byte Acknowledge-

ment

Each subsequent byte (signaled by MX

going high for one frame, see previous

paragraph) is acknowledged by the

receiver once it has seen two consecu-

tive identical bytes in the M-channel. It

acknowledges it by putting the MR

inactive (at 1) for exactly one frame.

In the next frame the MR bit must go

back to active.

End of Message (EOM)

Once the sender has received the

acknowledge of the last byte, it changes

the content to FFh, moves the MX to

inactive and keeps it inactive for at least

two frames.

Acknowledge of EOM

After the EOM of the sender, the receiv-

er acknowledges the EOM by putting

MR bit in the inactive state for at least

two frames, keeping it there until the

transmitter goes active again.

Sender Not Ready

If the sender is not ready (second byte

or subsequent) the MX bit will be kept in

the active state and the channel byte

stays constant.

Receiver Not Ready

If the receiver is not ready for the first

byte it keeps the MR in the inactive

state. If the receiver is not ready for the

second byte, it refuses to acknowledge

the bytes by keeping MR in the active

state.

IDLE Forced From Sender

If the first byte is never acknowledged,

i.e. MR staying at 1, the sender can

force the M-channel and MX to IDLE.

If the reception of a subsequent byte is

not (or not yet) acknowledged (MR is

staying active at 0) by the receiver, the

sender can put the M-channel and MX

to IDLE. The receiver should return MR

to inactive. The last byte or even the

complete message are never really

acknowledged by the receiver.

Abort Request From Receiver

The receiver can abort a message after

the SOM acknowledge or any subse-

quent byte acknowledge by forcing MR

inactive for at least two frames. The S-

interface aborts a message only when it

is forced in hard reset.

Acknowledge Abort

The sender acknowledges the abort

request by entering the idle state.

Reset of the M-Channel

Transceiver

At reset, the M-channel transceiver is

forced to the idle state.

All message bytes are put to idle, the

MX and MR bits are forced to 1,

aborting any ongoing message.

MTC-20276 INTQ

To S i/f byte 1: 1 0 0 0 X ADR2 ADR1 ADRO

block byte 2: CONTENT (MSB first to LSB last)

MTC-20276 INTQ

There is no outgoing message in reac-

tion to the WRITE.

The second nibble is address of the

internal register, limited from 1 to 6 in

the S-interface block. The write

addresses must differ from 0000, oth-

erwise the READ operation is

assumed.

Write Operation

For a Write operation, the double byte messages is as follows:

Table 21

The second nibble is all zero for an

internal READ operation. The fourth

nibble is the address of the register,

from 0 to 6.

Read Operation and Content

For a READ operation, the double byte messages is as follows:

Table 22

The second nibble is the address of

the internal register. The second byte

contains the content of the register.

The answer is the CONTENT message, two bytes as follows:

Detailed Bitmap of the Internal Registers

Table 23

Address name sent first Bits sent last Access

0h ID 0 1 1 0 1 0 0 0 read

1h VN 0 0 0 0 1 X X X read

2h CONF BT1/SC BTO DEX1 DEXO 1 MFE LTS/T DELT rd/wr

3h OUT RES RES RES RES - TEST RES RES rd/wr

0000 1000

4h IN1 1 1 1 1 1 1 1 1 read

5h IN2 (TEST) SCLK XTR4 XTR3 1 XTR2 XTR1 XTR0 read

6h PERF RES RES RES RES 1 RES 0 BER read

7h TEST device test only; not used in normal operation rd/wr

To S i/f byte 1: 1 0 0 0 0 0 0 0

block byte 2: X X X X X ADR2 ADR1 ADRO

From S i/f byte 1: 1 0 0 0 1 ADR2 ADR1 ADRO

block byte 2: CONTENT (MSB first to LSB last)

01101000

MTC-20276 INTQ

The version number of the device starts at 00h.

Configuration Register Read and Write Address 2h

Table 26

BT1/SC BT0 bus type selection

0 X bus type according to BUS pin; value at reset;

1 0 bus type = Adaptive; BUS pin ignored, pin usable as l/O;

1 1 bus type = Fixed; BUS pin ignored.

DEX1 DEX0 Common Echo Bus mode selection

0 X E-channel activated.

1 0 E-channel activated.

1 1 E-channel forced to ‘0’.

BUSY READ only bit. Must be writen at 0, writing BUSY at 1 triggers testmodes.

MFE Multiframing enable if 1; Reset value is 0. Always write as 0.

Multiframing is disabled in the MTC-20276.

RES Not used in this configuration. Always write 0. (Reserved)

DELT Not used in this configuration. Always write 0.

Output Register Read and Write Address 3h

Table 27

Note: The RES pins are reserved and cannot be used in this configuration.

TEST Must be written 0, writing TEST 1 triggers test modes.

CONF

reset

Identification Register Read Only Address 0h

Table 24

Version Number Register Read and Write Address 1h

Table 25

00001XXX

BT1/SC BT0 DEX1 DEX0 - MFE RES DELT

00001000

RES RES4 RES RES - TEST RES RES

00001000

OUT

reset

IN1 and IN2 Registers Read Only Addresses 4h and 5h

Table 28

S-bus mode Selection TSP Selection

0 Adaptative timing (PTP and EPB) 0 Transmit single Pulse U+S

1 Fixed timing (SPB) 1 Normal mode

Performance Register Read Only Address 6h

Table 29

RES Always reads as 0

BER Set each time the BER signal goes low, reset after being read.

M-Channel operation messages overview

Table 30

IN1

Reads

IN2

Reads

MTC-20276 INTQ

RES RES RES RES 1 RES 0 BER

11111111

(TEST) S-bus mode TSP

x11x1x00

The RES bits are reserved and cannot

be used in this configuration.

The bits represent the binary level of the

input pin. All values are sampled asyn-

chronously at the moment the content

message is assembled.

to the SIC block from the SIC block

byte 1 byte 2 byte 1 byte 2 byte 1 byte 2

identification 80h 00h - - 88h content

version number 80h 01h - - 89h content

configuration 80h 02h 82h content 8Ah content

output 80h 03h 83h content 8Bh content

input1 80h 04h (test only) 8Ch content

input2 80h 05h (test only) 8Dh content

performance 80h 06h - - 8Eh content

test (test only) (test only) (test only)

PERF

BER:Bit Error Rate. This indicate that

the SIC blocks has seen excessive bit

errors, indicating a link transmission

problem.

MTC-20276 INTQ

Package Specification

Device Branding

ALCATEL 2840

YYWW INTQ

MTC 20276 PQ -C

QNTB-MMM ARM

LLLLLLLLL AA

Fig.23: Device Marking-PQ Order number MTC-20276 PQ-I or C

MTC-20276 INTQ

44PQFP Mechanical Specification

All dimensions are in inches and parenthetically in millimeters. Inches dimensions are approximated.

Drawing revision: 11

Date: 07-06-95

General dimensions

.018(0.45)

.010(0.25)

TYP .0315(0.80)

.041(1.03)

.026(0.65)

0°- 10°

.398(10.10)

.390(9.90)

TYP .063(1.60)

Pin 1

.529(13.45)

.510(12.95)

.087(2.20)

.075(1.90)

TYP.006(0.15)

MAX .096(2.45)

MIN .002(0.05)

.529(13.45)

.510(12.95) .398(10.10)

.390(9.90)

44 LEAD PQFP / DQFP

DWG.NR.90-0010

MTC-20276 INTQ

This application note discusses the func-

tional implementation of certain system

features which are either optional or not

clearly defined in the prevailing interna-

tional standards ETSI TS 102 080 and

ANSI T1.601-1990.

EOC Data Channel

This is not implemented. The ETSI TS

102 080 and ANSI T1.601-1990

mention this data channel, but do not

describe how it should be used.

NTM Bit Is Not Supported (SET

to 1)

This is an optional feature of ETSI TS

102 080.

AIB Bit Is Ignored

This is an optional feature of ETSI ETS

102080.

After U-only Activation, the

Loopbacks (2B+D, B1, B2) Are

Not Transparent.

This is a logical consequence of the fact

that only the U is activated. However,

ETSI TS 102 080 does not describe the

characteristics of the loopbacks in U-

only activation (and in normal activa-

tion, the loopbacks should be transpar-

ent).

The Event ’UOA=0 and DEA=1’

in State NT6(a) and NT6 Trig-

gers Transition to NT8(A) (TS

102 080)

ETSI TS 102 080 specifies as next state

’NT8(a) or NT8(c)’. The MTC-20276

uses NT8(a).

New INFO1 Received

ETSI TS 102 080 is ambiguous (in

NOTE 12, p. 84):It states ”when INFO1

remains continuously after the NT fails to

bring up the network side and returns to

state NT1, the NT does not go again

into state NT2 unless a new transition

from INFO0 to INFO1 is received”.

Two interpretations are possible:

1. ’success’ is INFO3 reception instead

of INFO1 (i.e. arrival into state NT7).

2. ’success’ is arrival into state ’active’

(NT8).

The MTC-20276 uses the first interpretation.

TL:Tolerance on Recognised

10khz

The tolerance is not clear in ETSI TS 102

080. Currently, 8.6khz and 11.7khz

are used as specified pass/fail points

(i.e. a factor of 1.36 between these 2

frequencies, as in the implementation of

4B3T in the MTC-20277 INTT device).

Autoact

Reset of the chip (or power-up) automati-

cally causes an activation (as in ETSI TS

102 080, ANSI - clause 6.4, ANSI.

Table C.1).

ACT-bit (NT->LT) During 2B+D

Loopback

There is a difference between ETSI TS

102 080-1995 and ANSI T1.601 for

the 2B+D loopback case:

- act bit (NT->LT):

ANSI: always 0

ETSI: 0 until synchronised on its own

transmitted INFO2, then 1

- start of upstream transparency:

ANSI: on receipt of 2B+D loopback

request

ETSI: on receipt of ’act-bit = 1’ from LT.

The ETSI approach is chosen, as ANSI

is in the process of aligning itself to ETSI

(the contribution has been voted on the

ANSI T1E1.4 living list).

S/T Only Activation

This feature is described in ANSI92, in

Section C.5. It occurs when the NT does

not acquire the superframe marker with-

in 15s. This feature appears to be

optional, but is not stated as such. It

appears not to be present in ETSI TS

102 080, and to cause different behav-

iour from the TS 102 080 activation

tables (i.e. the actions on event ’15s

expired’ in states 3, 4, 5) and in the

ANSI tables C.1 and C.4. Currently, it

is not implemented.

EOC Message Notification of

Corrupted CRC: Impact on

FEBE_from_NT ?

ETSI TS 102 080. ANSI T1.601 do not

describe an NT- action that should be

the consequence of the above EOC

message. One could argue that the

FEBE bit sent by the NT should then be

fixed to 0 or 1. However, we currently

keep the definition of FEBE that reflects

the comparison between the NT-comput-

ed CRC and the CRC received in the

frame (as is the case when the CRC is

not corrupted).

ANSI NT Maintenance Modes

Metallic Loop Terminator for North

American applications only. (ANSI Sec-

tion 6.5)

Loss of Signal in State NT5

ETSI TS 102 080 and ANSI specify ‘no

action’, when the signal is lost in state

NT5. This means that the system does

not deactivate until the 15s timer M4 is

expired. The implementation is as

described in TS 102 080/ANSI.

Response to EOC-message

’Notification of Corrupted CRC’

ETSI TS 102 080 and ANSI do not

explicitly state what the NT has to send

back. The INTQ sends back ’unable to

comply’.

Time Between end EC-training

and Going into Power-down

ETSI TS 102 080 specifies this time as

480ms. The current MTC-20276 imple-

mentation uses 960ms, to allow a test

system to respond more slowly than

480ms.

MTC-20276 INTQ Compliance Issues

Compatibility with ETSI/ANSI Specs

MTC-20276 INTQ

Note

MTC-20276 INTQ

Note

MTC-20276 INTQ

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Alcatel Microelectronics

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http://www.alcatel.com/telecom/micro

This document contains information on a new product.

Alcatel Microelectronics

reserves the right to make

changes in specifications at any time and without notice.

The information furnished by

Alcatel Microelectronics

this document is believed to be accurate and reliable.

However, no responsibility is assumed by

Alcatel Microelec-

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for its use, nor for any infringements of patents or

other rights of third parties resulting from its use.

No licence is granted under any patents or patent rights

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