19-2167; Rev 0; 10/01 Low-Jitter, 800Mbps, 10-Port LVDS Repeaters with 100 Drive The MAX9153/MAX9154 low-jitter, low-voltage differential signaling (LVDS) repeaters are ideal for applications that require high-speed data or clock distribution while minimizing power, space, and noise. The devices accept a single LVDS input (MAX9153) or single LVPECL input (MAX9154) and repeat the signal at 10 LVDS outputs. Each differential output drives 100, allowing point-topoint distribution of signals on transmission lines with 100 termination at the receiver input. Ultra-low 90psp-p (max) added deterministic jitter and 1psRMS (max) added random jitter ensure reliable communication in high-speed links that are highly sensitive to timing error, especially those incorporating clock-anddata recovery or serializers and deserializers. The highspeed switching performance guarantees 800Mbps data rate and less than 60ps (max) skew between channels while operating from a single +3.3V supply. Supply current at 800Mbps is 118mA and reduces to 2A in power-down mode. LVDS inputs and outputs conform to the ANSI/EIA/TIA -644 standard. A fail-safe feature on the MAX9153 sets the output high when the input is undriven and open, terminated, or shorted. The MAX9153/MAX9154 are available in a 28-pin TSSOP package and are specified for the -40C to +85C extended temperature range. Refer to the MAX9150 data sheet for a pin-compatible 10-port LVDS repeater capable of driving a double-terminated (50) LVDS link. Features Ultra-Low 90psp-p (max) Added Deterministic Jitter at 800Mbps (223-1) PRBS Pattern 1psRMS (max) Added Random Jitter 60ps (max) Skew Between Channels Guaranteed 800Mbps Data Rate LVDS (MAX9153) or LVPECL (MAX9154) Input Versions Fail-Safe Circuit Sets Output High for Undriven Inputs (MAX9153) High-Impedance Differential Input when VCC = 0 2A Power-Down Supply Current Conforms to ANSI/EIA/TIA-644 LVDS Standard Pin-Compatible Upgrade to DS90LV110 Ordering Information TEMP. RANGE PART PINPACKAGE INPUT MAX9153EUI -40C to +85C 28 TSSOP LVDS MAX9154EUI -40C to +85C 28 TSSOP LVPECL Refer to the MAX9110/MAX9112 and MAX9111/MAX9113 data sheets for LVDS line drivers and receivers. Applications Typical Application Circuit Cellular Phone Base-Stations Add/Drop Muxes LVDS Digital Cross-Connects MAX9153 MAX9154 Network Switches/Routers Backplane Interconnect Clock Distribution 1 RX 100 LVDS* TX BACKPLANE OR CABLE 100 10 MAX9111 RX 100 MAX9110 Pin Configuration appears at end of data sheet. *(LVPECL INPUT FOR MAX9154) MAX9111 ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com. 1 MAX9153/MAX9154 General Description MAX9153/MAX9154 Low-Jitter, 800Mbps, 10-Port LVDS Repeaters with 100 Drive ABSOLUTE MAXIMUM RATINGS VCC to GND ...........................................................-0.3V to +4.0V RIN+, RIN- to GND ................................................-0.3V to +4.0V PWRDN to GND..........................................-0.3V to (VCC + 0.3V) DO_+, DO_- to GND..............................................-0.3V to +4.0V Short-Circuit Duration (DO_+, DO_-) .........................Continuous Continuous Power Dissipation (TA = +70C) 28-Pin TSSOP (derate 12.8mW/C above +70C) .....1026mW Storage Temperature.........................................-65C to +150C Maximum Junction Temperature .....................................+150C Operating Temperature Range ...........................-40C to +85C ESD Protection Human Body Model (RIN+, RIN-, DO_+, DO_-) ..............8kV Lead Temperature (soldering, 10s) .................................+300C Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. DC ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, RL = 100 1%, differential input voltage |VID| = 0.05V to 1.2V, MAX9153 LVDS input common-mode voltage VCM = |VID/2| to 2.4V - |VID/2|, MAX9154 LVPECL input voltage range = 0 to VCC, PWRDN = high, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = +3.3V, |VID| = 0.2V, VCM = 1.2V, TA = +25C.) (Notes 1 and 2) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS CONTROL INPUT (PWRDN) Input High Voltage VIH 2.0 VCC V Input Low Voltage VIL GND 0.8 V Input Current IIN -20 20 A 50 mV PWRDN = high or low DIFFERENTIAL INPUT (RIN+, RIN-) Differential Input High Threshold VTH Differential Input Low Threshold VTL Input Current (MAX9153) Power-Off Input Current (MAX9153) IRIN+ (OFF), IRIN- (OFF) Input Resistor 1 (MAX9153) RIN1 Input Resistor 2 (MAX9153) RIN2 Input Current (MAX9154) IRIN+, IRIN- Power-Off Input Current (MAX9154) 2 IRIN+, IRIN- IRIN+ (OFF), IRIN- (OFF) -3 -50 -3 0.05V | VID | 0.6V, PWRDN = high or low (Figure 1) mV -15 -3 15 0.6V < | VID | 1.2V, PWRDN = high or low (Figure 1) -20 -4 20 0.05V | VID | 0.6V, VCC = 0 or open, PWRDN = 0 or open (Figure 1) -15 3 15 0.6V < | VID | 1.2V, VCC = 0 or open, PWRDN = 0 or open (Figure 1) -20 4 20 PWRDN = high or low (Figure 1) 103 VCC = 0 or open, PWRDN = 0 or open (Figure 1) 103 PWRDN = high or low (Figure 1) 154 VCC = 0 or open, PWRDN = 0 or open(Figure 1) 154 VRIN+ = 3.6V, VRIN- = 3.6V or 0, PWRDN = high or low (Figure 2) -10 3 10 VRIN+ = 0, VRIN- = 3.6V or 0, PWRDN = high or low (Figure 2) -10 3 10 VRIN+ = 3.6V, VRIN- = 0, VCC = 0 or open, PWRDN = 0 or open (Figure 2) -10 3 10 VRIN+ = 0, VRIN- = 3.6V, VCC = 0 or open, PWRDN = 0 or open (Figure 2) -10 3 10 A A k k A A _______________________________________________________________________________________ Low-Jitter, 800Mbps, 10-Port LVDS Repeaters with 100 Drive (VCC = +3.0V to +3.6V, RL = 100 1%, differential input voltage |VID| = 0.05V to 1.2V, MAX9153 LVDS input common-mode voltage VCM = |VID/2| to 2.4V - |VID/2|, MAX9154 LVPECL input voltage range = 0 to VCC, PWRDN = high, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = +3.3V, |VID| = 0.2V, VCM = 1.2V, TA = +25C.) (Notes 1 and 2) PARAMETER SYMBOL CONDITIONS MIN PWRDN = high or low (Figure 2) 360 RIN3 VCC = 0 or open, PWRDN = 0 or open (Figure 2) 360 Differential Output Voltage VOD Figure 3 250 Charge in VOD Between Complementary Output States VOD Figure 3 VOS Figure 3 Change in VOS Between Complementary Output States VOS Figure 3 Output High Voltage VOH Figure 3 Output Low Voltage VOL Figure 3 Input Resistor 3 (MAX9154) TYP MAX UNITS k LVDS OUTPUT (DO_+, DO_-) Offset (Common-Mode) Voltage Differential Output Resistance Differential High Output Voltage in Fail-Safe Single-Ended Output ShortCircuit Current Single-Ended Output Short-Circuit Current Differential Output Short-Circuit Current (Note 3) RODIFF VOD+ IOZ IOS IOSD 1.125 380 450 mV 1 25 mV 1.26 1.375 V 3 25 mV 1.6 V 0.9 PWDRN = high or low 150 VCC = 0 PWDRN = 0 or open V 238 330 RIN+, RIN- undriven with short, open, or 100 termination (MAX9153) 250 450 RIN+, RIN- open (MAX9154) 250 450 PWDRN = low; VDO_+ = 3.6V or 0, DO_- + open; or VDO_- = 3.6V or 0, DO_+ = open -1 1 VCC = 0, PWRDN = 0 or open; VDO_+ = 3.6V or 0, DO_- = 3.6V or VDO_- = 3.6V or 0, DO_+ = open -1 1 -15 15 mA -15 15 mA VID = +50mV, VDO_+ = 0 or VCC, VDO_- = 0 or VCC VID = -50mV, VDO_+ = 0 or VCC, VDO_- = 0 or VCC VID = +50mV, VOD = 0 VID = -50mV, VOD = 0 mV A SUPPLY Supply Current ICC Power-Down Supply Current ICCZ DC, RL = 100 (Figure 4) 70 95 200MHz (400Mbps), RL = 100 90 115 118 145 2 20 400MHz (800Mbps), RL = 100 PWDRN = low Figure 4 (Note 3) mA A _______________________________________________________________________________________ 3 MAX9153/MAX9154 DC ELECTRICAL CHARACTERISTICS (continued) MAX9153/MAX9154 Low-Jitter, 800Mbps, 10-Port LVDS Repeaters with 100 Drive AC ELECTRICAL CHARACTERISTICS (VCC = +3.0V to +3.6V, RL = 100 1%, CL = 5pF, differential input voltage |VID| = 0.15V to 1.2V, MAX9153 LVDS input commonmode voltage VCM = |VID/2| to 2.4V - |VID/2|, MAX9154 LVPECL input voltage range = 0 to VCC, PWRDN = high, TA = -40C to +85C, unless otherwise noted. Typical values are at VCC = +3.3V, |VID| = 0.2V, VCM = 1.2V, TA = +25C.) (Notes 3, 4, 5) PARAMETER SYMBOL Rise Time tLHT Fall Time tHLT CONDITIONS Added Deterministic Jitter (Note 6) tDJ VID = 200mV, 2 - 1 PRBS data, VCM = 1.2V Added Random Jitter (Note 6) tRJ VID = 200mV, 50% duty cycle input, VCM = 1.2V tPLHD Differential Propagation Delay High to Low tPHLD Pulse Skew | tPLHD - tPHLD | tSKEW Channel-to-Channel Skew (Note 7) tCCS Differential Part-to-Part Skew 1 (Note 8) tPPS1 Differential Part-to-Part Skew 2 (Note 9) tPPS2 Maximum Input Frequency (Note 10) fMAX TYP MAX UNITS 150 220 450 ps 150 220 450 ps 400Mbps (NRZ) 13 50 800Mbps (NRZ) 24 90 ps (p-p) Figures 4, 5 23 Differential Propagation Delay Low to High MIN 200MHz 1 400MHz 1 ps (RMS) 1.6 2.3 3.3 1.6 2.3 3.3 Figures 4, 5 27 80 ps Figures 4, 5 35 60 ps 1.2 ns 1.7 ns Figures 4, 5 ns Figures 4, 5 Power-Down Time tPD Power-Up Time tPU Figures 4, 5 Figures 6, 7 800 Mbps 10 20 ns 20 40 s Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to ground except VTH, VTL, VID, VOD, and VOD. Note 2: Maximum and minimum limits over temperature are guaranteed by design and characterization. Devices are production tested at TA = +25C. Note 3: Guaranteed by design and characterization. Note 4: CL includes scope probe and test jig capacitance. Note 5: Signal generator conditions unless otherwise noted: frequency = 400MHz, 50% duty cycle, RO = 50, tR = 0.6ns, and tF = 0.6ns (0% to 100%). Note 6: Device jitter added to the input signal. Note 7: tCCS is the magnitude difference in differential propagation delay between outputs for a same-edge transition. Note 8: tPPS1 is the magnitude difference of any differential propagation delays between devices operating over rated conditions at the same supply voltage, input conditions, and ambient temperature. Note 9: TPPS2 is the magnitude difference of any differential propagation delays between devices operating over rated conditions. Note 10: Device meets VOD DC specification, and AC specifications while operating at fMAX. 4 _______________________________________________________________________________________ Low-Jitter, 800Mbps, 10-Port LVDS Repeaters with 100 Drive (VCC = +3.3V, RL = 100, CL = 5pF, |VID| = 200mV, VCM = 1.2V, fIN = 200MHz, TA = +25C, unless otherwise noted.) DIFFERENTIAL PROPAGATION DELAY vs. SUPPLY VOLTAGE 130 120 110 100 90 80 2.40 2.35 2.30 tPHLD 2.25 2.20 2.15 10 100 3.1 3.2 3.3 3.4 3.5 DIFFERENTIAL PROPAGATION DELAY vs. INPUT COMMON-MODE VOLTAGE DIFFERENTIAL OUTPUT-TO-OUTPUT SKEW vs. SUPPLY VOLTAGE tPLHD 2.35 2.30 2.25 tPHLD 35 H 1.0 1.5 2.0 B G 25 15 D 3.2 3.3 3.4 3.5 tHLT 210 220 tHLT 3.1 3.2 3.3 3.4 3.5 3.6 TRANSITION TIME vs. LOAD CAPACITANCE 500 450 400 tLHT 350 300 250 200 200 150 3.0 550 205 130 tLHT 230 SUPPLY VOLTAGE (V) MAX9153/54 toc07 215 110 240 3.6 TRANSITION TIME (ps) TRANSITION TIME (ps) 3.1 SUPPLY VOLTAGE (V) A = DO5 - DO1 B = DO5 - DO2 C = DO5 - DO3 D = DO5 - DO4 E = DO5 - DO6 F = DO5 - DO7 G = DO5 - DO8 H = DO5 - DO9 I = DO5 - D010 220 90 150 190 tLHT OUTPUT LOAD () 130 200 E 225 70 110 250 210 10 TRANSITION TIME vs. OUTPUT LOAD 50 90 260 A, F INPUT COMMON MODE-MODE VOLTAGE (V) 230 70 270 C 3.0 235 2.15 TRANSITION TIME vs. SUPPLY VOLTAGE I 20 2.5 tPHLD 2.20 MAX9153/54 toc08 0.5 2.25 280 5 0 2.30 OUTPUT LOAD () 30 2.20 tPLHD 2.35 50 TRANSITION TIME (ps) MAX9153/54 toc04 2.40 DIFFERENTIAL OUTPUT-TO-OUTPUT SKEW (ps) SUPPLY VOLTAGE (V) 2.45 2.40 3.6 INPUT FREQUENCY (MHz) 2.50 2.45 2.10 3.0 1000 2.55 MAX9153/54 toc03 tPLHD 2.10 70 DIFFERENTIAL PROPAGATION DELAY (ns) 2.45 MAX9153/54 toc06 140 2.50 MAX9153/54 toc05 SUPPLY CURRENT (mA) 150 2.50 MAX9153/54 toc02 160 DIFFERENTIAL PROPAGATION DELAY (ns) MAX9153/54 toc01 170 DIFFERENTIAL PROPAGATION DELAY vs. OUTPUT LOAD DIFFERENTIAL PROPAGATION DELAY (ns) SUPPLY CURRENT vs. FREQUENCY tHLT 5 7 9 11 13 15 LOAD CAPACITANCE (pF) _______________________________________________________________________________________ 5 MAX9153/MAX9154 Typical Operating Characteristics Typical Operating Characteristics (continued) (VCC = +3.3V, RL = 100, CL = 5pF, |VID| = 200mV, VCM = 1.2V, fIN = 200MHz, TA = +25C, unless otherwise noted.) DIFFERENTIAL OUTPUT vs. SUPPLY VOLTAGE DIFFERENTIAL OUTPUT vs. OUTPUT LOAD 396 DIFFERENTIAL OUTPUT (mV) 398 394 392 390 388 386 384 MAX9153/54 toc10 520 MAX9153/54 toc09 400 DIFFERENTIAL OUTPUT (mV) MAX9153/MAX9154 Low-Jitter, 800Mbps, 10-Port LVDS Repeaters with 100 Drive 470 420 370 320 270 382 380 220 3.0 3.1 3.2 3.3 3.4 3.5 3.6 50 SUPPLY VOLTAGE (V) 70 90 110 130 150 OUTPUT LOAD () Pin Description PIN NAME FUNCTION 1, 3, 11, 13, 16, 18, 20, 24, 26, 28 DO2+, DO1+, DO10+, DO9+, DO8+, DO7+, DO6+, DO5+, DO4+, DO3+ 2, 4, 12, 14, 15, 17, 19, 23, 25, 27 DO2-, DO1-, DO10-, DO9-, DO8-, DO7-, DO6-, DO5-, DO4-, DO3- 5 PWRDN 6, 9, 21 GND Ground 10, 22 VCC Power. Bypass each VCC pin to GND with 0.1F and 1nF ceramic capacitors. 7 RIN+ 8 RIN- LVDS (MAX9153) or LVPECL (MAX9154) Differential Inputs. RIN+ and RIN- are high-impedance inputs. Connect a resistor from RIN+ to RIN- to terminate the input signal. Differential LVDS Outputs Power Down. Drive PWRDN low to disable all outputs and reduce supply current to 2A. Drive PWRDN high for normal operation. Detailed Description LVDS is a signaling method for point-to-point data communication over a controlled-impedance medium as defined by the ANSI/TIA/EIA-644 and IEEE 1596.3 standards. LVDS uses a lower voltage swing than other common communication standards, achieving higher data rates with reduced power consumption, while reducing EMI emissions and system susceptibility to noise. The MAX9153/MAX9154 are 800Mbps, 10-port repeaters for high-speed, point-to-point, low-power 6 applications. The MAX9153 accepts an LVDS input and has a fail-safe input circuit. The MAX9154 accepts an LVPECL input. Both devices repeat the input at 10 LVDS outputs. The devices detect differential signals as low as 50mV and as high as 1.2V within the 0 to 2.4V input voltage range as specified in the LVDS standards. The MAX9153/MAX9154 outputs use a current-steering configuration to generate a 2.5mA to 4.5mA output current. This current-steering approach induces less ground bounce and no shoot-through current, enhancing noise margin and system speed performance. The outputs are short-circuit current limited and are high _______________________________________________________________________________________ Low-Jitter, 800Mbps, 10-Port LVDS Repeaters with 100 Drive Table 1. Input/Output Function Table INPUT, VID MAX9153/MAX9154 impedance (to ground) when PWRDN = low or the device is not powered. The outputs have a typical differential resistance of 238. The internal differential output resistance terminates induced noise and reflections from the primary termination located at the LVDS receiver. The MAX9153/MAX9154 current-steering output requires a resistive load to terminate the signal and complete the transmission loop. Because the devices switch the direction of current flow and not voltage levels, the output voltage swing is determined by the value of the termination resistor multiplied by the output current. With a typical 3.8mA output current, the MAX9153/MAX9154 produce a 380mV output voltage when driving a transmission line terminated with a 100 resistor (3.8mA x 100 = 380mV). Logic states are determined by the direction of current flow through the termination resistor. VCC MAX9153 RIN2 COMPARATOR VCC - 0.3V DO1+ DO1- RIN+ RIN1/2 RIN1/2 RECEIVER RIN- DO10+ DO10- Figure 1. MAX9153 Input Fail-Safe Circuit OUTPUTS, VOD +50mV High MAX9153 MAX9154 -50mV VCC Low DO1+ High Open Undriven short MAX9153 High Undriven terminated MAX9153 High RIN3 DO1- RIN+ Note: VID = RIN+ - RIN-, VOD = DO_+ - DO_High = 450mV > VOD > 250mV Low = -250mV > VOD > -450mV RIN- Fail-Safe The fail-safe feature of the MAX9153 sets the outputs high when the differential input is: * Open * Undriven and shorted * Undriven and terminated Without a fail-safe circuit, when the input is undriven, noise at the input may switch the outputs and it may appear to the system that data is being sent. Open or undriven terminated input conditions can occur when a cable is disconnected or cut, or when an LVDS driver output is in high impedance. A shorted input can occur because of a cable failure. When the input is driven with signals meeting the LVDS standard, the input common-mode voltage is less than VCC - 0.3V and the fail-safe circuit is not activated. If RECEIVER RIN3 DO10+ MAX9154 DO10- Figure 2. MAX9154 Input Bias Resistors the input is open, undriven and shorted, or undriven and parallel terminated, an internal resistor in the failsafe circuit pulls both inputs above VCC - 0.3V, activating the fail-safe circuit and forcing the outputs high (Figure 1). The MAX9154 is essentially the MAX9153 without the fail-safe circuit. The MAX9154 accepts input voltages from 0 to VCC (vs. 0 to 2.4V for the MAX9153), which allows interfacing to LVPECL input signals while retaining a good common-mode tolerance. _______________________________________________________________________________________ 7 MAX9153/MAX9154 Low-Jitter, 800Mbps, 10-Port LVDS Repeaters with 100 Drive Applications Information Supply Bypassing Bypass each VCC with high-frequency surface-mount ceramic 0.1F and 1nF capacitors in parallel as close to the device as possible, with the smaller value capacitor closest to the VCC pin. Traces, Cables, and Connectors The characteristics of input and output connections affect the performance of the MAX9153/MAX9154. Use controlled-impedance traces, cables, and connectors with matched characteristic impedance. Ensure that noise couples as common mode by running the traces of a differential pair close together. Reduce within-pair skew by matching the electrical length of the traces of a differential pair. Excessive skew can result in a degradation of magnetic field cancellation. Maintain the distance between traces of a differential pair to avoid discontinuities in differential impedance. Minimize the number of vias to further prevent impedance discontinuities. Termination The MAX9153/MAX9154 are specified for 100 differential characteristic impedance but can operate with 90 to 132 to accommodate various types of interconnect. The termination resistor should match the differential characteristic impedance of the interconnect and be located close to the LVDS receiver input. Use a 1% surface-mount termination resistor. The output voltage swing is determined by the value of the termination resistor multiplied by the output current. With a typical 3.8mA output current, the MAX9153/MAX9154 produce a 380mV output voltage when driving a transmission line terminated with a 100 resistor (3.8mA x 100 = 380mV). Chip Information TRANSISTOR COUNT: 1394 PROCESS: CMOS Avoid the use of unbalanced cables, such as ribbon cable. Balanced cables, such as twisted pair, offer superior signal quality and tend to generate less EMI due to canceling effects. Balanced cables tend to pick up noise as common mode, which is rejected by the LVDS receiver. Test Circuits and Timing Diagrams DO1+ MAX9153 MAX9154 50 VOD VOS 50 50 DO1- DO10+ RIN+ GENERATOR RIN- 50 VOD 50 VOS 50 DO10- Figure 3. Driver-Load Test Circuit 8 _______________________________________________________________________________________ Low-Jitter, 800Mbps, 10-Port LVDS Repeaters with 100 Drive CL 5pF MAX9153 MAX9154 DO1+ RL 100 DO1- CL 5pF 50 CL 5pF RIN+ GENERATOR DO10+ RINRL 100 50 DO10- CL 5pF Figure 4. Propagation Delay and Transition Time Test Circuit RIN0 DIFFERENTIAL VID RIN+ tPLHD tPHLD 80% 50% O 80% VOD = (VDO_+) - (VDO_-) O 50% 20% 20% tLHT tHLT Figure 5. Propagation Delay and Transition Time Waveforms _______________________________________________________________________________________ 9 MAX9153/MAX9154 Test Circuits and Timing Diagrams (continued) Low-Jitter, 800Mbps, 10-Port LVDS Repeaters with 100 Drive MAX9153/MAX9154 Test Circuits and Timing Diagrams (continued) CL 5pF DO1+ RL 50 MAX9153 MAX9154 RL 50 DO1- CL 5pF 1.2V 1.05V CL 5pF RIN+ 1.0V 1.05V DO10+ RL 50 RIN- 1.0V GENERATOR RL 50 DO10- CL 5pF PWRDN 1.2V 50 Figure 6. Power-Up/Down Delay Test Circuit VCC PWRDN 50% 50% tPD tPU O VOH 50% VDO_+ WHEN VID = +50mV VDO_- WHEN VID = -50mV 50% 1.2V 1.2V VDO_+ WHEN VID = -50mV VDO_- WHEN VID = +50mV 50% tPD 50% tPU VOL Figure 7. Power-Up/Down Delay Waveforms 10 ______________________________________________________________________________________ Low-Jitter, 800Mbps, 10-Port LVDS Repeaters with 100 Drive MAX9153/MAX9154 Pin Configuration TOP VIEW MAX9153 MAX9154 DO2+ 1 28 DO3+ DO2- 2 27 DO3- DO1+ 3 26 DO4+ DO1- 4 25 DO4- PWRDN 5 24 DO5+ GND 6 23 DO5- RIN+ 7 22 VCC RIN- 8 21 GND GND 9 20 DO6+ VCC 10 19 DO6- DO10+ 11 18 DO7+ DO10- 12 17 DO7- DO9+ 13 16 DO8+ DO9- 14 15 DO8- TSSOP TSSOP4.40mm.EPS Package Information Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 11 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2001 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products. Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Maxim Integrated: MAX9153EUI+ MAX9153EUI+T