ZY2105 5A No-Bus POL Data Sheet
8V to 14V Input • 0.5V to 5.5V Output
ZD-01967 Rev. B1.3, 7-Feb-2011 www.power-one.com Page 12 of 14
8. Pin and Feature Description
8.1 OK, Fault Status
The open drain input/output with the internal pull-up
resistor. The POL converter pulls its OK pin low, if a
fault occurs. Pulling low the OK input by an external
circuitry turns off the POL converter.
8.2 SYNC, Frequency Synchronization Line
The bidirectional input/output with the internal pull-up
resistor. If the POL converter is configured as a
master, the SYNC line propagates clock to other
POL converters. If the POL converter is configured
as a slave, the internal clock recovery circuit
synchronizes to the clock of the SYNC line.
8.3 IM, Interleave Mode
The input with the internal pull-up resistor. Pulling
the IM pin low configures a POL converter as a
master.
8.4 PG, Power Good
The open drain input/output with the internal pull-up
resistor. The pin is pulled low by the POL converter,
if the output voltage is outside of the window defined
by the Power Good High and Low thresholds.
Note: See the No-Bus Application Note for recommendations on
PG deglitching.
8.5 CCA, Compensation Coefficient Address
The input with internal pull-up to select one of 2 sets
of digital filter coefficients optimized for different
characteristics of output capacitance.
8.6 MARGIN, Output Voltage Margining
The output of the 2V internal voltage reference that
is used to program the output voltage of the POL
converter.
8.7 EN, Enable
The input with the internal pull-up resistor. The POL
converter is turned off, when the pin is pulled low
8.8 TRIM, Output Voltage Trim
The input of the TRIM comparator for the output
voltage programming.
The output voltage can be programmed by a single
resistor connected between MARGIN and TRIM
pins.
9. Application Information
9.1 Output Voltage Programming
Resistance of the trim resistor is determined from the
equation below:
,
)5.5(20
OUT
OUT
TRIM V
V
R−×
= kΩ
where VOUT is the desired output voltage in Volts.
If the RTRIM is open or the TRIM pin is shorted to
PGND, the VOUT=0.5V.
9.2 Output Voltage Margining
Margining can be implemented by changing the
resistance between the REF and TRIM pins.
Figure 13. Margining Configuration
In the schematic shown in Figure 13, the nominal
output voltage is set with the trim resistor RTRIM
calculated from the equation in the paragraph 9.1.
Resistors RUP and RDOWN are added to margin the
output voltage up and down respectively and
determined from the equations below.
⎟
⎟
⎠
⎞
⎜
⎜
⎝
⎛
∆
∆−×
×
+
×
=%
%5
20
20
V
VR
R
R
RTRIM
TRIM
TRIM
UP , kΩ
()
⎟
⎠
⎞
⎜
⎝
⎛
∆−
∆
×+= %100
%
20 V
V
RR TRIMDOWN , kΩ
MARGIN
TRIM
POL
GND
R
DOWN
R
TRIM
Margining
Down Switch
(normally
closed)
Margining
Up Switch
(normally
open)
RUP