STM32F303xD STM32F303xE ARM(R) Cortex(R)-M4 32b MCU+FPU, up to 512KB Flash, 80KB SRAM, FSMC, 4 ADCs, 2 DAC ch., 7 comp, 4 Op-Amp, 2.0-3.6 V Datasheet - production data Features * Core: ARM(R) Cortex(R)-M4 32-bit CPU with 72 MHz FPU, single-cycle multiplication and HW division, 90 DMIPS (from CCM), DSP instruction and MPU (memory protection unit) LQFP64 (10 x 10 mm) LQFP100 (14 x 14 mm) LQFP144 (20 x 20 mm) * Operating conditions: - VDD, VDDA voltage range: 2.0 V to 3.6 V * Memories - Up to 512 Kbytes of Flash memory - 64 Kbytes of SRAM, with HW parity check implemented on the first 32 Kbytes. - Routine booster: 16 Kbytes of SRAM on instruction and data bus, with HW parity check (CCM) - Flexible memory controller (FSMC) for static memories, with four Chip Select * CRC calculation unit * Reset and supply management - Power-on/Power-down reset (POR/PDR) - Programmable voltage detector (PVD) - Low-power modes: Sleep, Stop and Standby - VBAT supply for RTC and backup registers * Clock management - 4 to 32 MHz crystal oscillator - 32 kHz oscillator for RTC with calibration - Internal 8 MHz RC with x 16 PLL option - Internal 40 kHz oscillator * Up to 115 fast I/Os - All mappable on external interrupt vectors - Several 5 V-tolerant * Interconnect matrix * 12-channel DMA controller * Four ADCs 0.20 s (up to 40 channels) with selectable resolution of 12/10/8/6 bits, 0 to 3.6 V conversion range, separate analog supply from 2.0 to 3.6 V October 2016 This is information on a product in full production. UFBGA100 (7 x 7 mm) WLCSP100 (4.775 x 5.041 mm) * Two 12-bit DAC channels with analog supply from 2.4 to 3.6 V * Seven ultra-fast rail-to-rail analog comparators with analog supply from 2.0 to 3.6 V * Four operational amplifiers that can be used in PGA mode, all terminals accessible with analog supply from 2.4 to 3.6 V * Up to 24 capacitive sensing channels supporting touchkey, linear and rotary touch sensors * Up to 14 timers: - One 32-bit timer and two 16-bit timers with up to four IC/OC/PWM or pulse counter and quadrature (incremental) encoder input - Three 16-bit 6-channel advanced-control timers, with up to six PWM channels, deadtime generation and emergency stop - One 16-bit timer with two IC/OCs, one OCN/PWM, deadtime generation and emergency stop - Two 16-bit timers with IC/OC/OCN/PWM, deadtime generation and emergency stop - Two watchdog timers (independent, window) - One SysTick timer: 24-bit downcounter - Two 16-bit basic timers to drive the DAC * Calendar RTC with Alarm, periodic wakeup from Stop/Standby * Communication interfaces - CAN interface (2.0B Active) DocID026415 Rev 5 1/173 www.st.com STM32F303xD STM32F303xE - Three I2C Fast mode plus (1 Mbit/s) with - USB 2.0 full-speed interface with LPM 20 mA current sink, SMBus/PMBus, support wakeup from STOP - Infrared transmitter - Up to five USART/UARTs (ISO 7816 * SWD, Cortex(R)-M4 with FPU ETM, JTAG interface, LIN, IrDA, modem control) * 96-bit unique ID - Up to four SPIs, 4 to 16 programmable bit frames, two with multiplexed half/full duplex I2S interface Table 1. Device summary Reference Part number STM32F303xD STM32F303RD, STM32F303VD, STM32F303ZD. STM32F303xE STM32F303RE, STM32F303VE, STM32F303ZE. 2/173 DocID026415 Rev 5 STM32F303xD STM32F303xE Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1 ARM(R) Cortex(R)-M4 core with FPU with embedded Flash and SRAM . . . 16 3.2 Memory protection unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.4 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.5 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.6 Cyclic redundancy check (CRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.7 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.7.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.7.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.7.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.7.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.8 Interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.9 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.10 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.11 Direct memory access (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.12 Flexible static memory controller (FSMC) . . . . . . . . . . . . . . . . . . . . . . . . 22 3.13 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.13.1 3.14 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 23 Fast analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.14.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.14.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.14.3 VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.14.4 OPAMP reference voltage (VREFOPAMP) . . . . . . . . . . . . . . . . . . . . . . 24 3.15 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.16 Operational amplifier (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.17 Ultra-fast comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.18 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 DocID026415 Rev 5 3/173 5 Contents STM32F303xD STM32F303xE 3.18.1 Advanced timers (TIM1, TIM8, TIM20) . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.18.2 General-purpose timers (TIM2, TIM3, TIM4, TIM15, TIM16, TIM17) . . 26 3.18.3 Basic timers (TIM6, TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.18.4 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.18.5 Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.18.6 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.19 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 28 3.20 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.21 Universal synchronous/asynchronous receiver transmitter (USART) . . . 29 3.22 Universal asynchronous receiver transmitter (UART) . . . . . . . . . . . . . . . 30 3.23 Serial peripheral interface (SPI)/Inter-integrated sound interfaces (I2S) . 30 3.24 Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.25 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.26 Infrared transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 3.27 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 3.28 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.28.1 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.28.2 Embedded Trace Macrocell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4 Pinout and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.1 4/173 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 73 DocID026415 Rev 5 STM32F303xD STM32F303xE 7 Contents 6.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 73 6.3.4 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 6.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 6.3.6 Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.3.7 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 6.3.8 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 6.3.9 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 6.3.10 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 6.3.11 FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 6.3.12 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 6.3.13 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 6.3.14 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 6.3.15 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 6.3.16 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 6.3.17 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 6.3.18 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 6.3.19 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 6.3.20 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 6.3.21 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 6.3.22 Operational amplifier characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 148 6.3.23 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 6.3.24 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 7.1 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 7.2 LQFP144 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 7.3 UFBGA100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 7.4 LQFP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 7.5 WLCSP100 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 7.6 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 7.7 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 7.7.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 7.7.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 168 8 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 DocID026415 Rev 5 5/173 5 List of tables STM32F303xD STM32F303xE List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. 6/173 Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 STM32F303xD/E family device features and peripheral counts . . . . . . . . . . . . . . . . . . . . . 13 External analog supply values for analog peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 STM32F303xD/E peripheral interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 STM32F303xD/E I2C implementation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 USART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 STM32F303xD/E SPI/I2S implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Capacitive sensing GPIOs available on STM32F303xD/E devices . . . . . . . . . . . . . . . . . . 32 Number of capacitive sensing channels available on STM32F303xD/E devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 STM32F303xD/E pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 STM32F303xD/E alternate function mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Memory map, peripheral register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 73 Programmable voltage detector characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Typical and maximum current consumption from VDD supply at VDD = 3.6V . . . . . . . . . . . 75 Typical and maximum current consumption from the VDDA supply . . . . . . . . . . . . . . . . . . 76 Typical and maximum VDD consumption in Stop and Standby modes. . . . . . . . . . . . . . . . 77 Typical and maximum VDDA consumption in Stop and Standby modes. . . . . . . . . . . . . . . 78 Typical and maximum current consumption from VBAT supply. . . . . . . . . . . . . . . . . . . . . . 78 Typical current consumption in Run mode, code with data processing running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Typical current consumption in Sleep mode, code running from Flash or RAM . . . . . . . . . 81 Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Wakeup time using USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . . 96 Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . 96 DocID026415 Rev 5 STM32F303xD STM32F303xE Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. Table 93. Table 94. Table 95. Table 96. Table 97. List of tables Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . 97 Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT timings. . . . . . . . . . . . 98 Asynchronous multiplexed PSRAM/NOR read-NWAIT timings . . . . . . . . . . . . . . . . . . . . . 98 Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Asynchronous multiplexed PSRAM/NOR write-NWAIT timings . . . . . . . . . . . . . . . . . . . . 101 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 105 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Switching characteristics for PC Card/CF read and write cycles in attribute/common space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 Switching characteristics for PC Card/CF read and write cycles in I/O space . . . . . . . . . 111 Switching characteristics for NAND Flash read cycles . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Switching characteristics for NAND Flash write cycles. . . . . . . . . . . . . . . . . . . . . . . . . . . 114 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 IWDG min/max timeout period at 40 kHz (LSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 WWDG min-max timeout value @72 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 USB: full-speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Maximum ADC RAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 ADC accuracy - limited test conditions, 100-/144-pin packages . . . . . . . . . . . . . . . . . . . 137 ADC accuracy, 100-pin/144-pin packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 ADC accuracy - limited test conditions, 64-pin packages . . . . . . . . . . . . . . . . . . . . . . . . . 140 ADC accuracy, 64-pin packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 ADC accuracy at 1MSPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Operational amplifier characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 LQFP144 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 UFBGA100 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 UFBGA100 recommended PCB design rules (0.5 mm pitch BGA) . . . . . . . . . . . . . . . . . 157 LQPF100 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 WLCSP100 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 WLCSP100 recommended PCB design rules (0.4 mm pitch) . . . . . . . . . . . . . . . . . . . . . 164 DocID026415 Rev 5 7/173 8 List of tables Table 98. Table 99. Table 100. Table 101. 8/173 STM32F303xD STM32F303xE LQFP64 package mechanical data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 DocID026415 Rev 5 STM32F303xD STM32F303xE List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. STM32F303xD/E block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 STM32F303xD/E clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Infrared transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 STM32F303xD/E LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 STM32F303xD/E LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 STM32F303xD/E LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 STM32F303xD/E WLCSP100 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 STM32F303xD/E UFBGA100 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 STM32F303xD/E memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Typical VBAT current consumption (LSE and RTC ON/LSEDRV[1:0] 00') . . . . . . . . . . . . . 79 High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 HSI oscillator accuracy characterization results for soldered parts . . . . . . . . . . . . . . . . . . 93 Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . . 95 Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . 97 Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . 105 Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 PC Card/CompactFlash controller waveforms for common memory read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 PC Card/CompactFlash controller waveforms for common memory write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 PC Card/CompactFlash controller waveforms for attribute memory read access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 PC Card/CompactFlash controller waveforms for attribute memory write access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 PC Card/CompactFlash controller waveforms for I/O space read access . . . . . . . . . . . . 112 PC Card/CompactFlash controller waveforms for I/O space write access . . . . . . . . . . . . 112 NAND controller read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 NAND controller write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 TC and TTa I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 TC and TTa I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Five volt tolerant (FT and FTf) I/O input characteristics - CMOS port. . . . . . . . . . . . . . . . 120 Five volt tolerant (FT and FTf) I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . 120 I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 DocID026415 Rev 5 9/173 10 List of figures Figure 45. Figure 46. Figure 47. Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. 10/173 STM32F303xD STM32F303xE I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . 131 ADC typical current consumption on VDDA pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 ADC typical current consumption on VREF+ pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 OPAMP voltage noise versus frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 LQFP144 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 Recommended footprint for the LQFP144 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 LQFP144 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 UFBGA100 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 Recommended footprint for the UFBGA100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 UFBGA100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 LQFP100 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Recommended footprint for the LQFP100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 LQFP100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 WLCSP100 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 Recommended footprint for the WLCSP100 package . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 WLCSP100 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 LQFP64 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Recommended footprint for the LQFP64 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 LQFP64 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 LQFP100 PD max vs. TA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 DocID026415 Rev 5 STM32F303xD STM32F303xE 1 Introduction Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32F303xD/E microcontrollers. This STM32F303xD/E datasheet should be read in conjunction with the reference manual of STM32F303xB/C/D/E, STM32F358xC and STM32F328x4/6/8 devices (RM0316) available on STMicroelectronics website at www.st.com. For information on the ARM(R) Cortex(R)-M4 core with FPU, refer to the following documents: * Cortex(R) -M4 with FPU Technical Reference Manual, available from the www.arm.com website * STM32F3 and STM32F4 Series Cortex(R) -M4 programming manual (PM0214) available on STMicroelectronics website at www.st.com. DocID026415 Rev 5 11/173 67 Description 2 STM32F303xD STM32F303xE Description The STM32F303xD/E family is based on the high-performance ARM(R) Cortex(R)-M4 32-bit RISC core with FPU operating at a frequency of 72 MHz, and embedding a floating point unit (FPU), a memory protection unit (MPU) and an embedded trace macrocell (ETM). The family incorporates high-speed embedded memories (512-Kbyte Flash memory, 80-Kbyte SRAM), a flexible memory controller (FSMC) for static memories (SRAM, PSRAM, NOR and NAND), and an extensive range of enhanced I/Os and peripherals connected to an AHB and two APB buses. The devices offer four fast 12-bit ADCs (5 Msps), seven comparators, four operational amplifiers, two DAC channels, a low-power RTC, up to five general-purpose 16-bit timers, one general-purpose 32-bit timer, and up,to three timers dedicated to motor control. They also feature standard and advanced communication interfaces: up to three I2Cs, up to four SPIs (two SPIs are with multiplexed full-duplex I2Ss), three USARTs, up to two UARTs, CAN and USB. To achieve audio class accuracy, the I2S peripherals can be clocked via an external PLL. The STM32F303xD/E family operates in the -40 to +85C and -40 to +105C temperature ranges from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving mode allows the design of low-power applications. The STM32F303xD/E family offers devices in different packages ranging from 64 to 144 pins. Depending on the device chosen, different sets of peripherals are included. 12/173 DocID026415 Rev 5 STM32F303xD STM32F303xE Description Table 2. STM32F303xD/E family device features and peripheral counts Peripheral Flash (Kbytes) STM32F303Rx STM32F303Vx STM32F303Zx 384 384 384 512 512 SRAM (Kbytes) on data bus 64 CCM (Core Coupled Memory) RAM (Kbytes) 16 FMC (flexible memory controller) Advanced control NO 2 YES (16-bit)(1) 3 (16-bit) 5 (16-bit) 1 (32-bit) General purpose Timers PWM channels (all) (2) 31 40 Basic PWM channels (except complementary) 512 40 2 (16-bit) 22 28 SPI (I2S)(3) 28 4(2) I2C 3 Communication USART interfaces UART 3 2 CAN 1 USB 1 Normal I/Os (TC, TTa) 26 37 in WLCSP100,44 in LQFP100 and UFBGA100 45 5-volt tolerant I/Os (FT, FTf) 25 42 in LQFP100 40 in WLCSP100 and UFBGA100 70 GPIOs DMA channels Capacitive sensing channels 12-bit ADCs 12 18 4 22 channels 24 4 39 channels in LQFP100-pin and UFBGA100 33 channels in WLCSP100 4 40 channels 12-bit DAC channels Analog comparator Operational amplifiers CPU frequency 72 MHz Operating voltage 2.0 to 3.6 V DocID026415 Rev 5 13/173 67 Description STM32F303xD STM32F303xE Table 2. STM32F303xD/E family device features and peripheral counts (continued) Peripheral Operating temperature Packages STM32F303Rx STM32F303Vx Ambient operating temperature: - 40 to 85 C / - 40 to 105 C Junction temperature: - 40 to 125 C LQFP64 LQFP100 WLCSP100 UFBGA100 1. TIM1 and TIM8 are the two available advanced timers. 2. This total number considers also the PWMs generated on the complementary output channels. 3. The SPI interfaces works in an exclusive way in either the SPI mode or the I2S audio mode. 14/173 STM32F303Zx DocID026415 Rev 5 LQFP144 STM32F303xD STM32F303xE Description Figure 1. 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AF: alternate function on I/O pins. DocID026415 Rev 5 15/173 67 Functional overview STM32F303xD STM32F303xE 3 Functional overview 3.1 ARM(R) Cortex(R)-M4 core with FPU with embedded Flash and SRAM The ARM(R) Cortex(R)-M4 processor with FPU is the latest generation of ARM processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts. The ARM(R) Cortex(R)-M4 32-bit RISC processor with FPU features exceptional codeefficiency, delivering the high-performance expected from an ARM core in the memory size usually associated with 8- and 16-bit devices. The processor supports a set of DSP instructions which allows efficient signal processing and complex algorithm execution. Its single precision FPU speeds up software development by using metalanguage development tools, while avoiding saturation. With its embedded ARM core, the STM32F303xD/E family is compatible with all ARM tools and software. Figure 1 shows the general block diagram of the STM32F303xD/E family devices. 3.2 Memory protection unit (MPU) The memory protection unit (MPU) is used to separate the processing of tasks from the data protection. The MPU manage up to 8 protection areas that are further divided up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory. The memory protection unit is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-time operating system). If a program accesses a memory location that is prohibited by the MPU, the RTOS detects it and takes action. In an RTOS environment, the kernel dynamically updates the MPU area setting, based on the process to be executed. The MPU is optional and can be bypassed for applications that do not need it. 3.3 Embedded Flash memory All STM32F303xD/E devices feature 384/512 Kbyte of embedded Flash memory available for storing programs and data. The Flash memory access time is adjusted to the CPU clock frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 48 MHz and 2 wait states above). 16/173 DocID026415 Rev 5 STM32F303xD STM32F303xE 3.4 Functional overview Embedded SRAM STM32F303xD/E devices feature 80 Kbytes of embedded SRAM with hardware parity check. The memory can be accessed in read/write at CPU clock speed with 0 wait states, allowing the CPU to achieve 90 Dhrystone MIPS at 72 MHz (when running code from the CCM (Core Coupled Memory) RAM). 3.5 * 16 Kbytes of CCM SRAM mapped on both instruction and data bus, used to execute critical routines or to access data (parity check on all of CCM SRAM). * 64 Kbytes of SRAM mapped on the data bus (parity check on first 32 Kbytes of SRAM). Boot modes At startup, Boot0 pin and Boot1 option bit are used to select one of three boot options: * Boot from user Flash * Boot from system memory * Boot from embedded SRAM The boot loader is located in the system memory. It is used to reprogram the Flash memory by using USART1 (PA9/PA10), USART2 (PA2/PA3) or USB (PA11/PA12) through DFU (device firmware upgrade). 3.6 Cyclic redundancy check (CRC) The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a configurable generator polynomial value and size. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location. DocID026415 Rev 5 17/173 67 Functional overview STM32F303xD STM32F303xE 3.7 Power management 3.7.1 Power supply schemes * VSS, VDD = 2.0 to 3.6 V: external power supply for I/Os and the internal regulator. It is provided externally through VDD pins. * VSSA, VDDA = 2.0 to 3.6 V: external analog power supply for ADC, DAC, comparators, operational amplifier, reset blocks, RCs and PLL. The minimum voltage to be applied to VDDA differs from one analog peripheral to another. Table 3 provides the summary of the VDDA ranges for analog peripherals. The VDDA voltage level must always be greater than or equal to the VDD voltage level and must be provided first. Table 3. External analog supply values for analog peripherals Analog peripheral * 3.7.2 Minimum VDDA supply Maximum VDDA supply ADC/COMP 2.0 V 3.6 V DAC/OPAMP 2.4 V 3.6 V VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present. Power supply supervisor The device has an integrated power-on reset (POR) and power-down reset (PDR) circuits. They are always active, and ensure proper operation above a threshold of 2 V. The device remains in reset mode when the monitored supply voltage is below a specified threshold, VPOR/PDR, without the need for an external reset circuit. * The POR monitors only the VDD supply voltage. During the startup phase it is required that VDDA should arrive first and be greater than or equal to VDD. * The PDR monitors both the VDD and VDDA supply voltages, however the VDDA power supply supervisor can be disabled (by programming a dedicated Option bit) to reduce the power consumption if the application design ensures that VDDA is higher than or equal to VDD. The device features an embedded programmable voltage detector (PVD) that monitors the VDD power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD drops below the VPVD threshold and/or when VDD is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. 3.7.3 Voltage regulator The regulator has three operation modes: main (MR), low power (LPR), and power-down. * The MR mode is used in the nominal regulation mode (Run) * The LPR mode is used in Stop mode. * The power-down mode is used in Standby mode: the regulator output is in high impedance, and the kernel circuitry is powered down thus inducing zero consumption. The voltage regulator is always enabled after reset. It is disabled in Standby mode. 18/173 DocID026415 Rev 5 STM32F303xD STM32F303xE 3.7.4 Functional overview Low-power modes The STM32F303xD/E supports three low-power modes to achieve the best compromise between low power consumption, short startup time and available wakeup sources: * Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and wake up the CPU when an interrupt/event occurs. * Stop mode Stop mode achieves the lowest power consumption while retaining the content of SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low-power mode. The device can be woken up from Stop mode by any of the EXTI line. The EXTI line source can be one of the 16 external lines, the PVD output, the USB wakeup, the RTC alarm, COMPx, I2Cx or U(S)ARTx. * Standby mode The Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.8 V domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering Standby mode, SRAM and register contents are lost except for registers in the Backup domain and Standby circuitry. The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on the WKUP pin or an RTC alarm occurs. Note: The RTC, the IWDG and the corresponding clock sources are not stopped by entering Stop or Standby mode. 3.8 Interconnect matrix Several peripherals have direct connections between them. This allows autonomous communication between peripherals, saving CPU resources thus power supply consumption. In addition, these hardware connections allow fast and predictable latency. Table 4. STM32F303xD/E peripheral interconnect matrix Interconnect source Interconnect destination Interconnect action TIMx Timers synchronization or chaining ADCx DAC1 Conversion triggers DMA Memory to memory transfer trigger Compx Comparator output blanking COMPx TIMx Timer input: OCREF_CLR input, input capture ADCx TIMx Timer triggered by analog watchdog TIMx DocID026415 Rev 5 19/173 67 Functional overview STM32F303xD STM32F303xE Table 4. STM32F303xD/E peripheral interconnect matrix (continued) Interconnect source Interconnect destination Interconnect action GPIO RTCCLK HSE/32 MC0 TIM16 Clock source used as input channel for HSI and LSI calibration CSS CPU (hard fault) COMPx GPIO TIM1, TIM8, TIM20 TIM15, 16, 17 Timer break TIMx External trigger, timer break GPIO ADCx DAC1 Conversion external trigger DAC1 COMPx Comparator inverting input Note: For more details about the interconnect actions, refer to the corresponding sections in the STM32F303xD/Ereference manual (RM0316). 3.9 Clocks and startup System clock selection is performed on startup, however the internal RC 8 MHz oscillator is selected as default CPU clock on reset. An external 4-32 MHz clock can be selected, in which case it is monitored for failure. If failure is detected, the system automatically switches back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example with failure of an indirectly used external oscillator). Several prescalers allow to configure the AHB frequency, the high speed APB (APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and the high speed APB domains is 72 MHz, while the maximum allowed frequency of the low speed APB domain is 36 MHz. 20/173 DocID026415 Rev 5 STM32F303xD STM32F303xE Functional overview Figure 2. STM32F303xD/E clock tree )/,7)&/. WR)ODVKSURJUDPPLQJLQWHUIDFH +6, WR,&[ [ 6<6&/. ,665& 6<6&/. WR,6[ [ ([WFORFN ,6B&.,1 86% SUHVFDOHU +6, 0+] +6,5& 86%&/.WR86%LQWHUIDFH WR)0& +&/. 3//65& 3// [[ [ 6: 3//08/ WR$+%EXVFRUHPHPRU\DQG '0$ +6, $+% $+ % SUHVFDOHU 3//&/. +6( 35(',9 WR&RUWH[V\VWHPWLPHU )+&/.&RUWH[IUHHUXQQLQJFORFN $3% SUHVFDOHU 3&/. ,I $3%SUHVFDOHU [HOVH[ &66 WR$3%SHULSKHUDOV WR7,0 3/&/. 26&B287 26&B,1 26&B,1 26&B287 6<6&/. +6, /6( 0+] +6(26& WR7,0 /6(26& N+] WR8 6 $57[ [ $3% SUHVFDOHU 57&&/. WR57& 3&/. WR$3%SHULSKHUDOV ,I $3%SUHVFDOHU [HOVH[ /6( 57&6(/>@ 3&/. /6, /6,5& N+] 0&2SUHVFDOHU 0&2 0&2 ,:'*&/. WR,:'* 3//&/. +6, /6, +6( 6<6&/. 6<6&/. +6, /6( [ $'& SUHVFDOHU WR86$57 7,0 WR$'&[\ [\ $'&SUHVFDOHU 069 DocID026415 Rev 5 21/173 67 Functional overview 3.10 STM32F303xD STM32F303xE General-purpose input/outputs (GPIOs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current capable except for analog inputs. The I/Os alternate function configuration can be locked if needed following a specific sequence to avoid spurious writing to the I/Os registers. Fast I/O handling allows I/O toggling up to 36 MHz. 3.11 Direct memory access (DMA) The flexible general-purpose DMA is able to manage memory-to-memory, peripheral-tomemory and memory-to-peripheral transfers. The DMA controller supports circular buffer management, avoiding the generation of interrupts when the controller reaches the end of the buffer. Each of the 12 DMA channels is connected to dedicated hardware DMA requests, with software trigger support for each channel. Configuration is done by software and transfer sizes between source and destination are independent. The DMA is used with the main peripherals: SPI, I2C, USART, general-purpose timers, DAC and ADC. 3.12 Flexible static memory controller (FSMC) The flexible static memory controller (FSMC) includes two memory controllers: * The NOR/PSRAM memory controller, * The NAND/PC Card memory controller. This memory controller is also named Flexible memory controller (FMC). The main features of the FMC controller are the following: * Interface with static-memory mapped devices including: - Static random access memory (SRAM), - NOR Flash memory/OneNAND Flash memory, - PSRAM (four memory banks), - NAND Flash memory with ECC hardware to check up to 8 Kbyte of data, - 16-bit PC Card compatible devices. * 8-,16-bit data bus width, * Independent Chip Select control for each memory bank, * Independent configuration for each memory bank, * Write FIFO, * LCD parallel interface. The FMC can be configured to interface seamlessly with most graphic LCD controllers. It supports the Intel 8080 and Motorola 6800 modes, and is flexible enough to adapt to specific LCD interfaces. This LCD parallel interface capability makes it easy to build cost 22/173 DocID026415 Rev 5 STM32F303xD STM32F303xE Functional overview effective graphic applications using LCD modules with embedded controllers or high performance solutions using external controllers with dedicated acceleration. 3.13 Interrupts and events 3.13.1 Nested vectored interrupt controller (NVIC) The STM32F303xD/E devices embed a nested vectored interrupt controller (NVIC) able to handle up to 73 maskable interrupt channels and 16 priority levels. The NVIC benefits are the following: * Closely coupled NVIC gives low latency interrupt processing * Interrupt entry vector table address passed directly to the core * Closely coupled NVIC core interface * Allows early processing of interrupts * Processing of late arriving higher priority interrupts * Support for tail chaining * Processor state automatically saved * Interrupt entry restored on interrupt exit with no instruction overhead The NVIC hardware block provides flexible interrupt management features with minimal interrupt latency. 3.14 Fast analog-to-digital converter (ADC) Four fast analog-to-digital converters 5 MSPS, with selectable resolution between 12 and 6 bit, are embedded in the STM32F303xD/E family devices. The ADCs have up to 40 external channels. Some of the external channels are shared between ADC1&2 and between ADC3&4. The ADCs can perform conversions in single-shot or scan modes. In scan mode, automatic conversion is performed on a selected group of analog inputs. The ADCs have also internal channels: Temperature sensor connected to ADC1 channel 16, VBAT/2 connected to ADC1 channel 17, Voltage reference VREFINT connected to the 4 ADCs channel 18, VREFOPAMP1 connected to ADC1 channel 15, VREFOPAMP2 connected to ADC2 channel 17, VREFOPAMP3 connected to ADC3 channel 17 and VREFOPAMP4 connected to ADC4 channel 17. Additional logic functions embedded in the ADC interface allow: * Simultaneous sample and hold * Interleaved sample and hold * Single-shunt phase current reading techniques. The ADC can be served by the DMA controller. Three analog watchdogs are available per ADC. The analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. DocID026415 Rev 5 23/173 67 Functional overview STM32F303xD STM32F303xE The events generated by the general-purpose timers and the advanced-control timers (TIM1, TIM8 and TIM20) can be internally connected to the ADC start trigger and injection trigger, respectively, to allow the application to synchronize A/D conversion and timers. 3.14.1 Temperature sensor The temperature sensor (TS) generates a voltage VSENSE that varies linearly with temperature. The temperature sensor is internally connected to the ADC1_IN16 input channel which is used to convert the sensor output voltage into a digital value. The sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. As the offset of the temperature sensor varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only. To improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by ST. The temperature sensor factory calibration data are stored by ST in the system memory area, accessible in read-only mode. 3.14.2 Internal voltage reference (VREFINT) The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the ADC and Comparators. VREFINT is internally connected to the ADCx_IN18, x=1...4 input channel. The precise voltage of VREFINT is individually measured for each part by ST during production test and stored in the system memory area. It is accessible in read-only mode. 3.14.3 VBAT battery voltage monitoring This embedded hardware feature allows the application to measure the VBAT battery voltage using the internal ADC channel ADC1_IN17. As the VBAT voltage may be higher than VDDA, and thus outside the ADC input range, the VBAT pin is internally connected to a bridge divider by 2. As a consequence, the converted digital value is half the VBAT voltage. 3.14.4 OPAMP reference voltage (VREFOPAMP) Every OPAMP reference voltage can be measured using a corresponding ADC internal channel: VREFOPAMP1 connected to ADC1 channel 15, VREFOPAMP2 connected to ADC2 channel 17, VREFOPAMP3 connected to ADC3 channel 17 and VREFOPAMP4 connected to ADC4 channel 17. 3.15 Digital-to-analog converter (DAC) Two 12-bit buffered DAC channels can be used to convert digital signals into analog voltage signal outputs. The chosen design structure is composed of integrated resistor strings and an amplifier in inverting configuration. This digital interface supports the following features: 24/173 * Two DAC output channels * 8-bit or 10-bit monotonic output DocID026415 Rev 5 STM32F303xD STM32F303xE 3.16 Functional overview * Left or right data alignment in 12-bit mode * Synchronized update capability * Noise-wave generation * Triangular-wave generation * Dual DAC channel independent or simultaneous conversions * DMA capability (for each channel) * External triggers for conversion * Input voltage reference VREF+ Operational amplifier (OPAMP) The STM32F303xD/E embed four operational amplifiers with external or internal follower routing and PGA capability (or even amplifier and filter capability with external components). When an operational amplifier is selected, an external ADC channel is used to enable output measurement. The operational amplifier features: 3.17 * 8.2 MHz bandwidth * 0.5 mA output capability * Rail-to-rail input/output * In PGA mode, the gain is programmed to be 2, 4, 8 or 16. Ultra-fast comparators (COMP) The STM32F303xD/E devices embed seven ultra-fast rail-to-rail comparators with programmable reference voltage (internal or external) and selectable output polarity. The reference voltage can be one of the following: * External I/O * DAC output pin * Internal reference voltage or submultiple (1/4, 1/2, 3/4). Refer to Table 23: Embedded internal reference voltage for the value and precision of the internal reference voltage. All comparators can wake up from STOP mode, generate interrupts and breaks for the timers. 3.18 Timers and watchdogs The STM32F303xD/E include three advanced control timers, up to six general-purpose timers, two basic timers, two watchdog timers and one SysTick timer. The table below compares the features of the advanced control, general purpose and basic timers. DocID026415 Rev 5 25/173 67 Functional overview STM32F303xD STM32F303xE Table 5. Timer feature comparison Timer type Timer Counter resolution Counter type Prescaler factor DMA request generation Capture/ compare channels Complementary outputs Advanced TIM1, TIM8, TIM20 16-bit Up, Down, Up/Down Any integer between 1 and 65536 Yes 4 Yes Generalpurpose TIM2 32-bit Up, Down, Up/Down Any integer between 1 and 65536 Yes 4 No Generalpurpose TIM3, TIM4 16-bit Up, Down, Up/Down Any integer between 1 and 65536 Yes 4 No Generalpurpose TIM15 16-bit Up Any integer between 1 and 65536 Yes 2 1 Generalpurpose TIM16, TIM17 16-bit Up Any integer between 1 and 65536 Yes 1 1 Basic TIM6, TIM7 16-bit Up Any integer between 1 and 65536 Yes 0 No Note: TIM1/8/20/2/3/4/15/16/17 can have PLL as clock source, and therefore can be clocked at 144 MHz. 3.18.1 Advanced timers (TIM1, TIM8, TIM20) The advanced-control timers (TIM1, TIM8, TIM20) can each be seen as a three-phase PWM multiplexed on six channels. They have complementary PWM outputs with programmable inserted dead-times. They can also be seen as complete general-purpose timers. The four independent channels can be used for: * Input capture * Output compare * PWM generation (edge or center-aligned modes) with full modulation capability (0100%) * One-pulse mode output In debug mode, the advanced-control timer counter can be frozen and the PWM outputs disabled to turn off any power switches driven by these outputs. Many features are shared with those of the general-purpose TIM timers (described in Section 3.18.2) using the same architecture, so the advanced-control timers can work together with the TIM timers via the Timer Link feature for synchronization or event chaining. 3.18.2 General-purpose timers (TIM2, TIM3, TIM4, TIM15, TIM16, TIM17) There are up to six synchronizable general-purpose timers embedded in the STM32F303xD/E (see Table 5 for differences). Each general-purpose timer can be used to generate PWM outputs, or act as a simple time base. 26/173 DocID026415 Rev 5 STM32F303xD STM32F303xE * Functional overview TIM2, 3, and TIM4 These are full-featured general-purpose timers: - TIM2 has a 32-bit auto-reload up/downcounter and 32-bit prescaler - TIM3 and 4 have 16-bit auto-reload up/downcounters and 16-bit prescalers. These timers all feature 4 independent channels for input capture/output compare, PWM or one-pulse mode output. They can work together, or with the other generalpurpose timers via the Timer Link feature for synchronization or event chaining. The counters can be frozen in debug mode. All have independent DMA request generation and support quadrature encoders. * TIM15, 16 and 17 These three timers general-purpose timers with mid-range features: They have 16-bit auto-reload upcounters and 16-bit prescalers. - TIM15 has 2 channels and 1 complementary channel - TIM16 and TIM17 have 1 channel and 1 complementary channel All channels can be used for input capture/output compare, PWM or one-pulse mode output. The timers can work together via the Timer Link feature for synchronization or event chaining. The timers have independent DMA request generation. The counters can be frozen in debug mode. 3.18.3 Basic timers (TIM6, TIM7) These timers are mainly used for DAC trigger generation. They can also be used as a generic 16-bit time base. 3.18.4 Independent watchdog (IWDG) The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 40 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode. 3.18.5 Window watchdog (WWDG) The window watchdog is based on a 7-bit downcounter that can be set as free running. It is used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. DocID026415 Rev 5 27/173 67 Functional overview 3.18.6 STM32F303xD STM32F303xE SysTick timer This timer is dedicated to real-time operating systems, but could also be used as a standard down counter. It features: 3.19 * A 24-bit down counter * Autoreload capability * Maskable system interrupt generation when the counter reaches 0. * Programmable clock source Real-time clock (RTC) and backup registers The RTC and the 16 backup registers are supplied through a switch that takes power from either the VDD supply when present or the VBAT pin. The backup registers are sixteen 32-bit registers used to store 64 bytes of user application data when VDD power is not present. They are not reset by a system or power reset, or when the device wakes up from Standby mode. The RTC is an independent BCD timer/counter. It supports the following features: * Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date, month, year, in BCD (binary-coded decimal) format. * Reference clock detection: a more precise second source clock (50 or 60 Hz) can be used to enhance the calendar precision. * Automatic correction for 28, 29 (leap year), 30 and 31 days of the month. * Two programmable alarms with wake up from Stop and Standby mode capability. * On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to synchronize it with a master clock. * Digital calibration circuit with 1 ppm resolution, to compensate for quartz crystal inaccuracy. * Three anti-tamper detection pins with programmable filter. The MCU can be woken up from Stop and Standby modes on tamper event detection. * Timestamp feature which can be used to save the calendar content. This function can be triggered by an event on the timestamp pin, or by a tamper event. The MCU can be woken up from Stop and Standby modes on timestamp event detection. * 17-bit Auto-reload counter for periodic interrupt with wakeup from STOP/STANDBY capability. The RTC clock sources can be: 3.20 * A 32.768 kHz external crystal * A resonator or oscillator * The internal low-power RC oscillator (typical frequency of 40 kHz) * The high-speed external clock divided by 32. Inter-integrated circuit interface (I2C) Up to three I2C bus interfaces can operate in multimaster and slave modes. They can support standard (up to 100 kHz), fast (up to 400 kHz) and fast mode + (up to 1 MHz) modes. 28/173 DocID026415 Rev 5 STM32F303xD STM32F303xE Functional overview All I2C bus interfaces support 7-bit and 10-bit addressing modes, multiple 7-bit slave addresses (2 addresses, 1 with configurable mask). They also include programmable analog and digital noise filters. Table 6. Comparison of I2C analog and digital filters - Analog filter Digital filter Pulse width of suppressed spikes 50 ns Programmable length from 1 to 15 I2C peripheral clocks Benefits Available in Stop mode 1. Extra filtering capability vs. standard requirements. 2. Stable length Drawbacks Variations depending on temperature, voltage, process Wakeup from Stop on address match is not available when digital filter is enabled. In addition, they provide hardware support for SMBUS 2.0 and PMBUS 1.1: ARP capability, Host notify protocol, hardware CRC (PEC) generation/verification, timeouts verifications and ALERT protocol management. They also have a clock domain independent from the CPU clock, allowing the I2Cx (x=1,2,3) to wake up the MCU from Stop mode on address match. The I2C interfaces can be served by the DMA controller. Refer to Table 7 for the features available in I2C1, I2C2 and I2C3. Table 7. STM32F303xD/E I2C implementation I2C features(1) I2C1 I2C2 I2C3 7-bit addressing mode X X X 10-bit addressing mode X X X Standard mode (up to 100 kbit/s) X X X Fast mode (up to 400 kbit/s) X X X Fast Mode Plus with 20mA output drive I/Os (up to 1 Mbit/s) X X X Independent clock X X X SMBus X X X Wakeup from STOP X X X 1. X = supported. 3.21 Universal synchronous/asynchronous receiver transmitter (USART) The STM32F303xD/E devices have three embedded universal synchronous/asynchronous receiver transmitters (USART1, USART2 and USART3). The USART interfaces are able to communicate at speeds of up to 9 Mbit/s. They provide hardware management of the CTS and RTS signals, they support IrDA SIR ENDEC, the multiprocessor communication mode, the single-wire half-duplex DocID026415 Rev 5 29/173 67 Functional overview STM32F303xD STM32F303xE communication mode and have LIN Master/Slave capability. The USART interfaces can be served by the DMA controller. 3.22 Universal asynchronous receiver transmitter (UART) The STM32F303xD/E devices have 2 embedded universal asynchronous receiver transmitters (UART4, and UART5). The UART interfaces support IrDA SIR ENDEC, multiprocessor communication mode and single-wire half-duplex communication mode. The UART4 interface can be served by the DMA controller. Refer to Table 8 for the features available in all U(S)ART interfaces. Table 8. USART features USART modes/features(1) USART1 USART2 USART3 UART4 UART5 Hardware flow control for modem X X X - - Continuous communication using DMA X X X X - Multiprocessor communication X X X X X Synchronous mode X X X - - Smartcard mode X X X - - Single-wire half-duplex communication X X X X X IrDA SIR ENDEC block X X X X X LIN mode X X X X X Dual clock domain and wakeup from Stop mode X X X X X Receiver timeout interrupt X X X X X Modbus communication X X X X X Auto baud rate detection X X X - - Driver Enable X X X - - 1. X = supported. 3.23 Serial peripheral interface (SPI)/Inter-integrated sound interfaces (I2S) Up to four SPIs are able to communicate up to 18 Mbit/s in slave and master modes in fullduplex and half-duplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame size is configurable from 4 bits to 16 bits. Two standard I2S interfaces (multiplexed with SPI2 and SPI3) supporting four different audio standards can operate as master or slave at half-duplex and full duplex communication modes. They can be configured to transfer 16 and 24 or 32 bits with 16-bit or 32-bit data resolution and synchronized by a specific signal. Audio sampling frequency from 8 kHz up to 192 kHz can be set by 8-bit programmable linear prescaler. When operating in master mode it can output a clock for an external audio component at 256 times the sampling frequency. Refer to Table 9 for the features available in SPI1, SPI2, SPI3 and SPI4. 30/173 DocID026415 Rev 5 STM32F303xD STM32F303xE Functional overview Table 9. STM32F303xD/E SPI/I2S implementation SPI features(1) SPI1 SPI2 SPI3 SPI4 Hardware CRC calculation X X X X Rx/Tx FIFO X X X X NSS pulse mode X X X X I2S mode - X X - TI mode X X X X 1. X = supported. 3.24 Controller area network (CAN) The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s. It can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with 3 stages and 14 scalable filter banks. 3.25 Universal serial bus (USB) The STM32F303xD/E embeds a full-speed USB device peripheral compliant with the USB specification version 2.0. The USB interface implements a full-speed (12 Mbit/s) function interface with added support for USB 2.0 Link Power Management. It has softwareconfigurable endpoint setting with packet memory up-to 1 Kbyte (256 bytes are used for CAN peripheral if enabled) and suspend/resume support. The dedicated 48 MHz clock is generated from the internal main PLL (the clock source must use a HSE crystal oscillator). 3.26 Infrared transmitter The STM32F303xD/E devices provide an infrared transmitter solution. The solution is based on internal connections between TIM16 and TIM17 as shown in the figure below. TIM17 is used to provide the carrier frequency and TIM16 provides the main signal to be sent. The infrared output signal is available on PB9 or PA13. To generate the infrared remote control signals, TIM16 channel 1 and TIM17 channel 1 must be properly configured to generate correct waveforms. All standard IR pulse modulation modes can be obtained by programming the two timers output compare channels. DocID026415 Rev 5 31/173 67 Functional overview STM32F303xD STM32F303xE Figure 3. Infrared transmitter 7,0(5 2& IRUHQYHORS 7,0(5 3%3$ 2& IRUFDUULHU 06Y9 3.27 Touch sensing controller (TSC) The STM32F303xD/E devices provide a simple solution for adding capacitive sensing functionality to any application. These devices offer up to 24 capacitive sensing channels distributed over 8 analog I/O groups. Capacitive sensing technology is able to detect the presence of a finger near a sensor which is protected from direct touch by a dielectric (glass, plastic, etc.). The capacitive variation introduced by the finger (or any conductive object) is measured using a proven implementation based on a surface charge transfer acquisition principle. It consists of charging the sensor capacitance and then transferring a part of the accumulated charges into a sampling capacitor until the voltage across this capacitor has reached a specific threshold. To limit the CPU bandwidth usage this acquisition is directly managed by the hardware touch sensing controller and only requires few external components to operate. The touch sensing controller is fully supported by the STMTouch touch sensing firmware library which is free to use and allows touch sensing functionality to be implemented reliably in the end application. Table 10. Capacitive sensing GPIOs available on STM32F303xD/E devices Group 1 2 32/173 Capacitive sensing signal name Pin name TSC_G1_IO1 PA0 TSC_G1_IO2 PA1 TSC_G1_IO3 PA2 TSC_G1_IO4 PA3 TSC_G2_IO1 PA4 TSC_G2_IO2 PA5 TSC_G2_IO3 PA6 TSC_G2_IO4 PA7 - Group 5 - DocID026415 Rev 5 6 Capacitive sensing signal name Pin name TSC_G5_IO1 PB3 TSC_G5_IO2 PB4 TSC_G5_IO3 PB6 TSC_G5_IO4 PB7 TSC_G6_IO1 PB11 TSC_G6_IO2 PB12 TSC_G6_IO3 PB13 TSC_G6_IO4 PB14 STM32F303xD STM32F303xE Functional overview Table 10. Capacitive sensing GPIOs available on STM32F303xD/E devices (continued) Group Capacitive sensing signal name Pin name - TSC_G3_IO1 PC5 - TSC_G3_IO2 PB0 - TSC_G3_IO3 PB1 - TSC_G3_IO4 PB2 TSC_G4_IO1 3 4 Capacitive sensing signal name Pin name TSC_G7_IO1 PE2 TSC_G7_IO2 PE3 TSC_G7_IO3 PE4 - TSC_G7_IO4 PE5 PA9 - TSC_G8_IO1 PD12 TSC_G4_IO2 PA10 - TSC_G8_IO2 PD13 TSC_G4_IO3 PA13 - TSC_G8_IO3 PD14 TSC_G4_IO4 PA14 - TSC_G8_IO4 PD15 Group 7 8 Table 11. Number of capacitive sensing channels available on STM32F303xD/E devices Number of capacitive sensing channels Analog I/O group STM32F303VE/ZE STM32F303RE G1 3 3 G2 3 3 G3 3 3 G4 3 3 G5 3 3 G6 3 3 G7 3 0 G8 3 0 Number of capacitive sensing channels 24 18 3.28 Development support 3.28.1 Serial wire JTAG debug port (SWJ-DP) The ARM SWJ-DP Interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP. 3.28.2 Embedded Trace Macrocell The ARM embedded trace macrocell (ETMTM) provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the STM32F303xD/E through a small number of ETMTM pins to an external hardware trace DocID026415 Rev 5 33/173 67 Functional overview STM32F303xD STM32F303xE port analyzer (TPA) device. The TPA is connected to a host computer using a high-speed channel. Real-time instruction and data flow activity can be recorded and then formatted for display on the host computer running debugger software. TPA hardware is commercially available from common development tool vendors. It operates with third party debugger software tools. 34/173 DocID026415 Rev 5 STM32F303xD STM32F303xE Pinout and pin description 3& 3&26&B,1 3&26&B287 3)26&B,1 3)26&B287 1567 3& 3& 3& 3& 966$ 9''$ 3$ 3$ 3$ /4)3 9'' 966 3$ 3$ 3$ 3$ 3$ 3$ 3& 3& 3& 3& 3% 3% 3% 3% 3$ 3$ 3$ 3$ 3& 3& 3% 3% 3% 3% 3% 966 9'' 9%$7 3% 3% %227 3% 3% 3% 3% 3% 3' 3& 3& 3& 3$ 3$ 9'' 966 Figure 4. STM32F303xD/E LQFP64 pinout 3$ 966 9'' 4 Pinout and pin description 069 DocID026415 Rev 5 35/173 67 Pinout and pin description STM32F303xD STM32F303xE 9'' 966 3( 3( 3% 3% %22 7 3% 3% 3% 3% 3% 3' 3' 3' 3' 3' 3' 3' 3' 3& 3& 3& 3$ 3$ Figure 5. STM32F303xD/E LQFP100 pinout /4)3 9'' 966 3) 3$ 3$ 3$ 3$ 3$ 3$ 3& 3& 3& 3& 3' 3' 3' 3' 3' 3' 3' 3' 3% 3% 3% 3% 3$ 966 9'' 3$ 3$ 3$ 3$ 3& 3& 3% 3% 3% 3( 3( 3( 3( 3( 3( 3( 3( 3( 3% 3% 966 9'' 3( 3( 3( 3( 3( 9%$7 3& 3&26&B,1 3&26&B287 3) 3) 3)26&B,1 3)2&6B287 1567 3& 3& 3& 3& 3) 966$95() 95() 9''$ 3$ 3$ 3$ 069 36/173 DocID026415 Rev 5 STM32F303xD STM32F303xE Pinout and pin description 3' 3' 3' 3' 3' 3' 3& 3& 3& 3$ 3$ 9'' 966 3* 3* 3* 3* 3* 3* 3' 3' 9'' 966 3( 3( 3% 3% %227 3% 3% 3% 3% 3% 3* 9'' 966 Figure 6. STM32F303xD/E LQFP144 pinout 9'' 966 3+ 3$ 3$ 3$ 3$ 3$ 3$ 3& 3& 3& 3& 9'' 966 3* 3* 3* 3* 3* 3* 3* 3' 3' 9'' 966 3' 3' 3' 3' 3' 3' 3% 3% 3% 3% 966 9'' 3( 3( 3( 3( 3( 3( 3% 3% 966$ 95() 95() 9''$ 3$B:.83 3$ 3$ 966 9'' 1567 3& 3& 3& 3& 3) 3) 3) 3* 3* 3( 3( 3( 3)26&B,1 3)26&B287 /4)3 966 9'' 3) 3) 3) 3) 3) 3$ 3$ 3$ 3$ 3& 3& 3% 3% 3% 3) 3) 966 9'' 3) 3) 3) 3) 966 9'' 3&B$17,B7$03 3&B26&B,1 3&B26&B287 3+ 3+ 3$ 3( 3( 3( 3( 3( 9%$7 069 DocID026415 Rev 5 37/173 67 Pinout and pin description STM32F303xD STM32F303xE Figure 7. STM32F303xD/E WLCSP100 ballout 3( 9'' 9'' $ 966 966 3& 3' 3% 3% % 966 3$ 3' 3' 3% 3% 3( 9'' 3( 9'' & 3) 3$ 3' 3' 3% 3% 966 3( 3& 3& 26&,1 ' 3$ 9'' 3& 3' 3% 3( 3( 9%$7 3& 26&287 3) ( 3$ 3$ 3$ 3& 3$ 3( 3( 3) 1567 3) ) 3& 3& 3& 3& 3$ 3& 3$ 3( 3) 26&287 3) 26&,1 * 3' 3' 3' 3' 3( 3& 3$ 3& 3& 3& + 3' 3' 3' 3% 3( 3$ 3$ 966$ 3$ 3& - 966 3% 3% 3% 9'' 3% 3$ 95() 3$ 9''$ 966 966 3% 3% 3% 3% 3$ 9'' 966 966 . %227 06Y9 38/173 DocID026415 Rev 5 STM32F303xD STM32F303xE Pinout and pin description Figure 8. STM32F303xD/E UFBGA100 ballout $ 3( 3( 3% %227 3' 3' 3% 3% 3$ 3$ 3$ 3$ % 3( 3( 3% 3% 3% 3' 3' 3' 3' 3& 3& 3$ & 3& 3( 3( 9'' 3% 3' 3' 3& 3) 3$ ' 3& 3( 966 3$ 3$ 3& 3& 9%$7 966 3& 3& 3& 966 966 9'' 9'' ( ) * 3)26&,1 3) 3)26&287 3) + 3& 1567 9'' 3' 3' 3' - 3) 3& 3& 3' 3' 3' . 966$ 95() 3& 3$ 3$ 3& / 9''$ 3$ 3$ 3$ 3& 3% 0 95() 3$ 3$ 3$ 3% 3% 3' 3' 3% 3% 3% 3( 3( 3( 3% 3% 3% 3( 3( 3( 3( 3( 3( 069 DocID026415 Rev 5 39/173 67 Pinout and pin description STM32F303xD STM32F303xE Table 12. Legend/abbreviations used in the pinout table Name Pin name I/O structure Notes Alternate functions Pin functions 40/173 Abbreviation Definition Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name FT 5 V tolerant I/O FTf 5 V tolerant I/O, I2C FM+ option TTa 3.3 V tolerant I/O TC Standard 3.3V I/O B Dedicated to BOOT0 pin RST Bi-directional reset pin with embedded weak pull-up resistor Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset Functions selected through GPIOx_AFR registers Additional Functions directly selected/enabled through peripheral registers functions DocID026415 Rev 5 STM32F303xD STM32F303xE Pinout and pin description Table 13. STM32F303xD/E pin definitions - - - 1 2 3 B2 A1 B1 D6 D7 C8 1 2 3 PE2 PE3 PE4 I/O I/O I/O Notes I/O structure Pin name (function after reset) Pin type LQFP144 WLCSP100 UFBGA100 LQFP100 LQFP64 Pin number Alternate functions Additional functions FT (1) TRACECK, EVENTOUT, TIM3_CH1, TSC_G7_IO1, SPI4_SCK, TIM20_CH1, FMC_A23 FT (1) TRACED0, EVENTOUT, TIM3_CH2, TSC_G7_IO2, SPI4_NSS, TIM20_CH2, FMC_A19 FT (1) TRACED1, EVENTOUT, TIM3_CH3, TSC_G7_IO3, SPI4_NSS, TIM20_CH1N, FMC_A20 TRACED2, EVENTOUT, TIM3_CH4, TSC_G7_IO4, SPI4_MISO, TIM20_CH2N, FMC_A21 - 4 C2 B9 4 PE5 I/O FT (1) - 5 D2 E7 5 PE6 I/O FT (1) TRACED3, EVENTOUT, SPI4_MOSI, TIM20_CH3N, FMC_A22 WKUP3, RTC_TAMP3 1 6 E2 D8 6 VBAT S - - - - 2 7 C1 C9 7 PC13(2) I/O TC - EVENTOUT, TIM1_CH1N WKUP2,RTC_TAMP1, RTC_TS, RTC_OUT 3 8 D1 C10 8 PC14 OSC32_IN (2) I/O TC - EVENTOUT OSC32_IN 4 9 E1 D9 9 PC15 I/O OSC32_OUT(2) TC - EVENTOUT OSC32_OUT - - - - 10 PH0 I/O FT (1) EVENTOUT, TIM20_CH1, FMC_A0 - - - - 11 PH1 I/O FT (1) EVENTOUT, TIM20_CH2, FMC_A1 - 19 J1 E8 12 PF2 I/O TTa (1) EVENTOUT, TIM20_CH3, ADC12_IN10 FMC_A2 - - - - 13 PF3 I/O FT (1) EVENTOUT, TIM20_CH4, FMC_A3 DocID026415 Rev 5 41/173 67 Pinout and pin description STM32F303xD STM32F303xE Table 13. STM32F303xD/E pin definitions (continued) - 14 PF4 I/O TTa (1) EVENTOUT, COMP1_OUT, TIM20_CH1N, FMC_A4 ADC1_IN5(3) - - - - 15 PF5 I/O FT (1) EVENTOUT, TIM20_CH2N, FMC_A5 - - - - - 16 VSS S - (1) - - - (1) - - - - UFBGA100 LQFP100 - - - 17 Pin name (function after reset) VDD S Notes I/O structure - LQFP144 - WLCSP100 - LQFP64 Pin type Pin number Alternate functions Additional functions - 73 C11 C1 18 PF6 I/O FTf (1) EVENTOUT, TIM4_CH4, I2C2_SCL, USART3_RTS, FMC_NIORD - - - - 19 PF7 I/O FT (1) EVENTOUT, TIM20_BKIN, FMC_NREG - - - - 20 PF8 I/O FT (1) EVENTOUT, TIM20_BKIN2, FMC_NIOWR - 10 F2 D10 21 PF9 I/O FT (1) EVENTOUT, TIM20_BKIN, TIM15_CH1, SPI2_SCK, FMC_CD - - - 11 G2 E10 22 PF10 I/O FT (1) EVENTOUT, TIM20_BKIN2, TIM15_CH2, SPI2_SCK, FMC_INTR 5 12 F1 F10 23 PF0-OSC_IN I FTf - EVENTOUT, I2C2_SDA, SPI2_NSS/I2S2_WS, TIM1_CH3N OSC_IN 6 13 G1 F9 24 PF1OSC_OUT O FTf - EVENTOUT, I2C2_SCL, SPI2_SCK/I2S2_CK OSC_OUT 7 14 H2 E9 25 NRST I-O RST - Device reset input/internal reset output (active low) 8 15 H1 G10 26 PC0 I/O TTa - EVENTOUT, TIM1_CH1 ADC12_IN6, COMP7_INM 9 16 J2 G9 27 PC1 I/O TTa - EVENTOUT, TIM1_CH2 ADC12_IN7, COMP7_INP 10 17 J3 G8 28 PC2 I/O TTa - EVENTOUT, TIM1_CH3, COMP7_OUT ADC12_IN8 42/173 DocID026415 Rev 5 STM32F303xD STM32F303xE Pinout and pin description Table 13. STM32F303xD/E pin definitions (continued) H10 29 PC3 I/O TTa - EVENTOUT, TIM1_CH4, TIM1_BKIN2 ADC12_IN9 12 20 K1 H8 VSSA S - (1) - - - - 30 UFBGA100 LQFP100 Pin name (function after reset) Notes I/O structure K2 LQFP144 18 WLCSP100 11 LQFP64 Pin type Pin number Alternate functions Additional functions - - - - 31 VREF- S - (1) - 21 M1 J8 32 VREF+(4) S - - - - 13 22 L1 J10 33 VDDA S - - - - - TIM2_CH1/TIM2_ETR, TSC_G1_IO1, USART2_CTS, COMP1_OUT, TIM8_BKIN, TIM8_ETR, EVENTOUT ADC1_IN1(3), COMP1_INM, RTC_TAMP2, WKUP1 - RTC_REFIN, TIM2_CH2, TSC_G1_IO2, USART2_RTS, TIM15_CH1N, EVENTOUT ADC1_IN2(3), COMP1_INP, OPAMP1_VINP, OPAMP3_VINP (5) TIM2_CH3, TSC_G1_IO3, ADC1_IN3(3), USART2_TX, COMP2_INM, COMP2_OUT, OPAMP1_VOUT TIM15_CH1, EVENTOUT 14 15 16 23 24 25 L2 M2 K3 H9 J9 F7 34 35 36 PA0 PA1 PA2 I/O I/O I/O TTa TTa TTa 17 26 L3 G7 37 PA3 I/O TTa - TIM2_CH4, TSC_G1_IO4, ADC1_IN4(3), OPAMP1_VINM USART2_RX, TIM15_CH2, EVENTOUT OPAMP,1_VINP 18 27 D3 K9, 38 K10 VSS S - - - - 19 28 H3 K8 VDD S - (1) - - (5) ADC2_IN1(3), DAC1_OUT1, COMP1_INM, TIM3_CH2, TSC_G2_IO1, COMP2_INM, SPI1_NSS, COMP3_INM, SPI3_NSS/I2S3_WS, COMP4_INM, USART2_CK, EVENTOUT COMP5_INM, COMP6_INM, COMP7_INM, OPAMP4_VINP 20 29 M3 J7 39 40 PA4 I/O TTa DocID026415 Rev 5 43/173 67 Pinout and pin description STM32F303xD STM32F303xE Table 13. STM32F303xD/E pin definitions (continued) 21 22 30 31 K4 L4 H7 H6 41 42 PA5 PA6 I/O I/O TTa TTa Notes I/O structure Pin name (function after reset) Pin type LQFP144 WLCSP100 UFBGA100 LQFP100 LQFP64 Pin number Alternate functions Additional functions (5) ADC2_IN2(3), DAC1_OUT2, COMP1_INM, COMP2_INM, COMP3_INM, TIM2_CH1/TIM2_ETR, COMP4_INM, TSC_G2_IO2, SPI1_SCK, COMP5_INM, EVENTOUT COMP6_INM, COMP7_INM, OPAMP1_VINP, OPAMP2_VINM, OPAMP3_VINP (5) TIM16_CH1, TIM3_CH1, TSC_G2_IO3, TIM8_BKIN, SPI1_MISO, TIM1_BKIN, COMP1_OUT, EVENTOUT ADC2_IN3(3), OPAMP2_VOUT ADC2_IN4(3), COMP2_INP, OPAMP1_VINP, OPAMP2_VINP ADC2_IN5(3) 23 32 M4 K7 43 PA7 I/O TTa - TIM17_CH1, TIM3_CH2, TSC_G2_IO4, TIM8_CH1N, SPI1_MOSI, TIM1_CH1N, EVENTOUT 24 33 K5 G6 44 PC4 I/O TTa - EVENTOUT, TIM1_ETR, USART1_TX 25 34 L5 F6 45 PC5 I/O TTa - EVENTOUT, TIM15_BKIN, ADC2_IN11, TSC_G3_IO1, OPAMP1_VINM, USART1_RX OPAMP2_VINM - ADC3_IN12, TIM3_CH3, TSC_G3_IO2, COMP4_INP, TIM8_CH2N, OPAMP2_VINP, TIM1_CH2N, EVENTOUT OPAMP3_VINP 26 35 M5 J6 46 PB0 I/O TTa 27 36 M6 K6 47 PB1 I/O TTa (5) TIM3_CH4, TSC_G3_IO3, TIM8_CH3N, ADC3_IN1(3), TIM1_CH3N, OPAMP3_VOUT COMP4_OUT, EVENTOUT 28 37 L6 K5 48 PB2 I/O TTa - TSC_G3_IO4, EVENTOUT 44/173 DocID026415 Rev 5 ADC2_IN12, COMP4_INM, OPAMP3_VINM STM32F303xD STM32F303xE Pinout and pin description Table 13. STM32F303xD/E pin definitions (continued) Notes I/O structure Pin name (function after reset) Pin type LQFP144 WLCSP100 UFBGA100 LQFP100 LQFP64 Pin number Alternate functions Additional functions - - - - 49 PF11 I/O FT (1) EVENTOUT, TIM20_ETR - - - - 50 PF12 I/O FT (1) EVENTOUT, TIM20_CH1, FMC_A6 - - - - 51 VSS S - - - - - - - - 52 VDD S - (1) - - - - - - 53 PF13 I/O FT (1) EVENTOUT, TIM20_CH2, FMC_A7 - - - - 54 PF14 I/O FT (1) EVENTOUT, TIM20_CH3, FMC_A8 - - - - 55 PF15 I/O FT (1) EVENTOUT, TIM20_CH4, FMC_A9 - - - - 56 PG0 I/O FT (1) EVENTOUT, TIM20_CH1N, FMC_A10 - - - - - 57 PG1 I/O FT (1) EVENTOUT, TIM20_CH2N, FMC_A11 - - 38 M7 F8 58 PE7 I/O TTa (1) EVENTOUT, TIM1_ETR, FMC_D4 ADC3_IN13 - 39 L7 E6 59 PE8 I/O TTa (1) EVENTOUT, TIM1_CH1N, ADC34_IN6, FMC_D5 COMP4_INM - 40 M8 - 60 PE9 I/O TTa (1) EVENTOUT, TIM1_CH1, FMC_D6 ADC3_IN2(3) - - - - 61 VSS S - (1) - - - - - - - - - 62 VDD S - (1) - 41 L8 - 63 PE10 I/O TTa (1) EVENTOUT, TIM1_CH2N, ADC3_IN14 FMC_D7 - 42 M9 H5 64 PE11 I/O TTa (1) EVENTOUT, TIM1_CH2, SPI4_NSS, FMC_D8 - 43 L9 G5 65 PE12 I/O TTa (1) EVENTOUT, TIM1_CH3N, ADC3_IN16 SPI4_SCK, FMC_D9 - 44 M10 - 66 PE13 I/O TTa (1) EVENTOUT, TIM1_CH3, SPI4_MISO, FMC_D10 DocID026415 Rev 5 ADC3_IN15 ADC3_IN3(3) 45/173 67 Pinout and pin description STM32F303xD STM32F303xE Table 13. STM32F303xD/E pin definitions (continued) PE14 I/O TTa (1) EVENTOUT, TIM1_CH4, SPI4_MOSI, TIM1_BKIN2, ADC4_IN1(3) FMC_D11 - 46 M12 - 68 PE15 I/O TTa (1) EVENTOUT, TIM1_BKIN, USART3_RX, FMC_D12 29 47 L10 K4 69 PB10 I/O TTa - COMP5_INM, TIM2_CH3, TSC_SYNC, OPAMP3_VINM, USART3_TX, EVENTOUT OPAMP4_VINM 30 48 L11 K3 70 PB11 I/O TTa - ADC12_IN14, TIM2_CH4, TSC_G6_IO1, COMP6_INP, USART3_RX, EVENTOUT OPAMP4_VINP 31 49 F12 K1, J1, K2 71 VSS S - - - - 32 50 G12 J5 72 VDD S - - - - (5) TSC_G6_IO2, I2C2_SMBAL, ADC4_IN3(3), SPI2_NSS/I2S2_WS, COMP3_INM, TIM1_BKIN, USART3_CK, OPAMP4_VOUT EVENTOUT - TSC_G6_IO3, SPI2_SCK/I2S2_CK, TIM1_CH1N, USART3_CTS, EVENTOUT ADC3_IN5(3), COMP5_INP, OPAMP3_VINP, OPAMP4_VINP - TIM15_CH1, TSC_G6_IO4, SPI2_MISO/I2S2ext_SD, TIM1_CH2N, USART3_RTS, EVENTOUT ADC4_IN4(3), COMP3_INP, OPAMP2_VINP 33 34 35 51 52 53 UFBGA100 L12 K12 K11 J4 J3 J2 73 74 75 Pin name (function after reset) PB12 PB13 PB14 I/O I/O I/O TTa TTa TTa Notes I/O structure 67 LQFP144 M11 - WLCSP100 45 LQFP100 - LQFP64 Pin type Pin number Alternate functions Additional functions ADC4_IN2(3) 36 54 K10 H4 76 PB15 I/O TTa - RTC_REFIN, TIM15_CH2, TIM15_CH1N, ADC4_IN5(3), TIM1_CH3N, COMP6_INM SPI2_MOSI/I2S2_SD, EVENTOUT - 55 K9 - 77 PD8 I/O TTa (1) EVENTOUT, USART3_TX, FMC_D13 46/173 DocID026415 Rev 5 ADC4_IN12, OPAMP4_VINM STM32F303xD STM32F303xE Pinout and pin description Table 13. STM32F303xD/E pin definitions (continued) G4 78 PD9 I/O TTa (1) EVENTOUT, USART3_RX, FMC_D14 ADC4_IN13 - 57 J12 H3 79 PD10 I/O TTa (1) EVENTOUT, USART3_CK, FMC_D15 ADC34_IN7, COMP6_INM - 58 J11 H2 80 PD11 I/O TTa (1) EVENTOUT, ADC34_IN8, USART3_CTS, FMC_A16 OPAMP4_VINP - 59 J10 H1 81 PD12 I/O TTa (1) EVENTOUT, TIM4_CH1, TSC_G8_IO1, ADC34_IN9 USART3_RTS, FMC_A17 - 60 H12 G3 82 PD13 I/O TTa (1) EVENTOUT, TIM4_CH2, TSC_G8_IO2, FMC_A18 ADC34_IN10, COMP5_INM - - - - 83 VSS S - (1) - - - ADC34_IN11, OPAMP2_VINP UFBGA100 LQFP100 Pin name (function after reset) Notes I/O structure K8 LQFP144 56 WLCSP100 - LQFP64 Pin type Pin number Alternate functions Additional functions - - - - 84 VDD S - (1) - 61 H11 G2 85 PD14 I/O TTa (1) EVENTOUT, TIM4_CH3, TSC_G8_IO3, FMC_D0 - 62 H10 G1 86 PD15 I/O TTa (1) EVENTOUT, TIM4_CH4, TSC_G8_IO4, SPI2_NSS, COMP3_INM FMC_D1 - - - - 87 PG2 I/O FT (1) EVENTOUT, TIM20_CH3N, FMC_A12 - - - - 88 PG3 I/O FT (1) EVENTOUT, TIM20_BKIN, FMC_A13 - - - - 89 PG4 I/O FT (1) EVENTOUT, TIM20_BKIN2, FMC_A14 - - - - 90 PG5 I/O FT (1) EVENTOUT, TIM20_ETR, FMC_A15 - - - - 91 PG6 I/O FT (1) EVENTOUT, FMC_INT2 - EVENTOUT, FMC_INT3 - - - - - - - 92 PG7 I/O FT (1) - - - - 93 PG8 I/O FT (1) EVENTOUT - - (1) - - - (1) - - - - - - 94 95 VSS VDD S S DocID026415 Rev 5 47/173 67 Pinout and pin description STM32F303xD STM32F303xE Table 13. STM32F303xD/E pin definitions (continued) Notes I/O structure Pin name (function after reset) Pin type LQFP144 WLCSP100 UFBGA100 LQFP100 LQFP64 Pin number Alternate functions Additional functions 37 63 E12 F4 96 PC6 I/O FT - EVENTOUT, TIM3_CH1, TIM8_CH1, I2S2_MCK, COMP6_OUT - 38 64 E11 F2 97 PC7 I/O FT - EVENTOUT, TIM3_CH2, TIM8_CH2, I2S3_MCK, COMP5_OUT - 39 65 E10 F1 98 PC8 I/O FT - EVENTOUT, TIM3_CH3, TIM8_CH3, COMP3_OUT 40 66 D12 F3 99 PC9 I/O FTf - EVENTOUT, TIM3_CH4, I2C3_SDA, TIM8_CH4, I2SCKIN, TIM8_BKIN2 - MCO, I2C3_SCL, I2C2_SMBAL, I2S2_MCK, TIM1_CH1, USART1_CK, COMP3_OUT, TIM4_ETR, EVENTOUT - I2C3_SMBAL, TSC_G4_IO1, I2C2_SCL, I2S3_MCK, TIM1_CH2, USART1_TX, COMP5_OUT, TIM15_BKIN, TIM2_CH3, EVENTOUT - TIM17_BKIN, TSC_G4_IO2, I2C2_SDA, SPI2_MISO/I2S2ext_SD, TIM1_CH3, USART1_RX, COMP6_OUT, TIM2_CH4, TIM8_BKIN, EVENTOUT - SPI2_MOSI/I2S2_SD, TIM1_CH1N, USART1_CTS, USB_DM COMP1_OUT, CAN_RX, TIM4_CH1, TIM1_CH4, TIM1_BKIN2, EVENTOUT 41 42 43 44 67 68 69 70 48/173 D11 D10 C12 B12 F5 E5 E1 E2 100 PA8 101 PA9 102 PA10 103 PA11 I/O I/O I/O I/O FTf FTf FTf FT DocID026415 Rev 5 - - STM32F303xD STM32F303xE Pinout and pin description Table 13. STM32F303xD/E pin definitions (continued) 45 71 A12 D1 104 PA12 I/O FT Notes I/O structure Pin name (function after reset) Pin type LQFP144 WLCSP100 UFBGA100 LQFP100 LQFP64 Pin number Alternate functions Additional functions - TIM16_CH1, I2SCKIN, TIM1_CH2N, USART1_RTS, COMP2_OUT, CAN_TX, TIM4_CH2, TIM1_ETR, EVENTOUT USB_DP - 46 72 A11 E3 105 PA13 I/O FT - SWDIO-JTMS, TIM16_CH1N, TSC_G4_IO3, IR-OUT, USART3_CTS, TIM4_CH3, EVENTOUT - - - - 106 PH2 I/O FT (1) EVENTOUT - 47 74 F11 A1, A2, B1 107 VSS S - - - - 48 75 G11 D2 108 VDD S - - - - - SWCLK-JTCK, TSC_G4_IO4, I2C1_SDA, TIM8_CH2, TIM1_BKIN, USART2_TX, EVENTOUT - JTDI, TIM2_CH1/TIM2_ETR, TIM8_CH1, TSC_SYNC, I2C1_SCL, SPI1_NSS, SPI3_NSS/I2S3_WS, USART2_RX, TIM1_BKIN, EVENTOUT - EVENTOUT, TIM8_CH1N, UART4_TX, SPI3_SCK/I2S3_CK, USART3_TX - EVENTOUT, TIM8_CH2N, UART4_RX, SPI3_MISO/I2S3ext_SD, USART3_RX 49 50 51 52 76 77 78 79 A10 A9 B11 C10 C2 B2 E4 D3 109 PA14 110 111 112 PA15 PC10 PC11 I/O I/O I/O I/O FTf FTf FT FT DocID026415 Rev 5 49/173 67 Pinout and pin description STM32F303xD STM32F303xE Table 13. STM32F303xD/E pin definitions (continued) Notes I/O structure Pin name (function after reset) Pin type LQFP144 WLCSP100 UFBGA100 LQFP100 LQFP64 Pin number Alternate functions Additional functions 53 80 B10 A3 113 PC12 I/O FT - EVENTOUT, TIM8_CH3N, UART5_TX, SPI3_MOSI/I2S3_SD, USART3_CK - 81 C9 B3 114 PD0 I/O FT (1) EVENTOUT, CAN_RX, FMC_D2 - - 82 B9 C3 115 PD1 I/O FT (1) EVENTOUT, TIM8_CH4, TIM8_BKIN2, CAN_TX, FMC_D3 - 54 83 C8 A4 116 PD2 I/O FT - EVENTOUT, TIM3_ETR, TIM8_BKIN, UART5_RX - - 84 B8 B4 117 PD3 I/O FT (1) EVENTOUT, TIM2_CH1/TIM2_ETR, USART2_CTS, FMC_CLK - 85 B7 C4 118 PD4 I/O FT (1) EVENTOUT, TIM2_CH2, USART2_RTS, FMC_NOE - - 86 A6 - 119 PD5 I/O FT (1) EVENTOUT, USART2_TX, FMC_NWE - - - - - 120 VSS S - (1) - - - - - - - - 121 VDD S - (1) - 87 B6 - 122 PD6 I/O FT (1) EVENTOUT, TIM2_CH4, USART2_RX, FMC_NWAIT - - 88 A5 D4 123 PD7 I/O FT (1) EVENTOUT, TIM2_CH3, USART2_CK, FMC_NE1/FMC_NCE2 - - - - - 124 PG9 I/O FT (1) EVENTOUT, FMC_NE2/FMC_NCE3 - - - - - 125 PG10 I/O FT (1) EVENTOUT, FMC_NCE4_1/FMC_NE3 - - - - - 126 PG11 I/O FT (1) EVENTOUT, FMC_NCE4_2 - - - - - 127 PG12 I/O FT (1) EVENTOUT, FMC_NE4 - FT (1) EVENTOUT, FMC_A24 - - - 50/173 - - 128 PG13 I/O DocID026415 Rev 5 STM32F303xD STM32F303xE Pinout and pin description Table 13. STM32F303xD/E pin definitions (continued) - - - - I/O Notes Pin name (function after reset) 129 PG14 I/O structure Pin type LQFP144 WLCSP100 UFBGA100 LQFP100 LQFP64 Pin number Alternate functions Additional functions FT (1) EVENTOUT, FMC_A25 - - - - - - - 130 VSS S - (1) - - - - 131 VDD S - (1) - - FT (1) EVENTOUT - - JTDO-TRACESWO, TIM2_CH2, TIM4_ETR, TSC_G5_IO1, TIM8_CH1N, SPI1_SCK, SPI3_SCK/I2S3_CK, USART2_TX, TIM3_ETR, EVENTOUT - - JTRST, TIM16_CH1, TIM3_CH1, TSC_G5_IO2, TIM8_CH2N, SPI1_MISO, SPI3_MISO/I2S3ext_SD, USART2_RX, TIM17_BKIN, EVENTOUT - TIM16_BKIN, TIM3_CH2, TIM8_CH3N, I2C1_SMBAl, SPI1_MOSI, SPI3_MOSI/I2S3_SD, USART2_CK, I2C3_SDA, TIM17_CH1, EVENTOUT - TIM16_CH1N, TIM4_CH1, TSC_G5_IO3, I2C1_SCL, TIM8_CH1, TIM8_ETR, USART1_TX, TIM8_BKIN2, EVENTOUT - 55 56 57 58 - 89 90 91 92 - A8 A7 C5 B5 - A5 B5 A6 B6 132 PG15 133 PB3 134 PB4 135 PB5 136 PB6 I/O I/O I/O I/O I/O FT FT FTf FTf 59 93 B4 C5 137 PB7 I/O FTf - TIM17_CH1N, TIM4_CH2, TSC_G5_IO4, I2C1_SDA, TIM8_BKIN, USART1_RX, TIM3_CH4, FMC_NADV, EVENTOUT 60 94 A4 A7 138 BOOT0 I - - - DocID026415 Rev 5 - 51/173 67 Pinout and pin description STM32F303xD STM32F303xE Table 13. STM32F303xD/E pin definitions (continued) 61 95 A3 D5 139 PB8 I/O FTf Notes I/O structure Pin name (function after reset) Pin type LQFP144 WLCSP100 UFBGA100 LQFP100 LQFP64 Pin number Alternate functions Additional functions - TIM16_CH1, TIM4_CH3, TSC_SYNC, I2C1_SCL, USART3_RX, COMP1_OUT, CAN_RX, TIM8_CH2, TIM1_BKIN, EVENTOUT - - 62 96 B3 C6 140 PB9 I/O FTf - TIM17_CH1, TIM4_CH4, I2C1_SDA, IR-OUT, USART3_TX, COMP2_OUT, CAN_TX, TIM8_CH3, EVENTOUT - 97 C3 B7 141 PE0 I/O FT (1) EVENTOUT, TIM4_ETR, TIM16_CH1, TIM20_ETR, USART1_TX, FMC_NBL0 - 98 A2 A8 142 PE1 I/O FT (1) EVENTOUT, TIM17_CH1, TIM20_CH4, USART1_RX, FMC_NBL1 63 99 E3 C7 143 VSS S - - - - A9, A10 , 144 VDD B10 , B8 S - - - - 64 100 C4 1. Function availability depends on the chosen device. 2. PC13, PC14 and PC15 are supplied through the power switch. Since the switch sinks only a limited amount of current (3 mA), the use of GPIO PC13 to PC15 in output mode is limited: - The speed should not exceed 2 MHz with a maximum load of 30 pF - These GPIOs must not be used as current sources (e.g. to drive an LED) After the first backup domain power-up, PC13, PC14 and PC15 operate as GPIOs. Their function then depends on the content of the Backup registers which is not reset by the main reset. For details on how to manage these GPIOs, refer to the Battery backup domain and BKP register description sections in the RM0316 reference manual. 3. Fast ADC channel. 4. The VREF+ functionality is not available on the 64-pin package. In this package, the VREF+ is internally connected to VDDA. 5. These GPIOs offer a reduced touch sensing sensitivity. It is thus recommended to use them as sampling capacitor I/O. 52/173 DocID026415 Rev 5 AF0 Port DocID026415 Rev 5 Port A SYS_AF AF1 AF2 AF3 I2C3/TIM1 I2C3/TIM TIM2/15/ /2/3/4/8/20 8/20/15/G 16/17/E /15/GPCO PCOMP7 VENT MP1 /TSC AF4 I2C1/2/TI M1/8/16/ 17 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SPI1/SPI2 /I2S2/SPI3 SPI2/I2S2/ USART1/2 I2C3/GPC /I2S3/SPI4 SPI3/I2S3/ /3/CAN/GP CAN/TIM1 OMP1/2/3/ /UART4/5/ TIM1/8/20/ COMP3/5/ /8/15 4/5/6 TIM8/Infra Infrared 6 red TIM2/3/ 4/8/17 TIM1/8 FSMC /TIM1 - - EVENT - TIM2_ CH1/TIM 2_ETR - TSC_G1 _IO1 - - - USART2_ CTS COMP1_ OUT TIM8_ BKIN TIM8_ ETR - - - - EVENT OUT PA1 RTC_ REFIN TIM2_ CH2 - TSC_G1 _IO2 - - - USART2_ RTS - TIM15_ CH1N - - - - - EVENT OUT PA2 - TIM2_ CH3 - TSC_G1 _IO3 - - - USART2_ TX COMP2_ OUT TIM15_ CH1 - - - - - EVENT OUT PA3 - TIM2_ CH4 - TSC_G1 _IO4 - - - USART2_ RX - TIM15_ CH2 - - - - - EVENT OUT PA4 - TIM3_ CH2 TSC_G2 _IO1 - SPI1_NSS SPI3_NSS /I2S3_WS USART2_ CK - - - - - - - EVENT OUT PA5 - TIM2_ CH1/TIM 2_ETR - TSC_G2 _IO2 - SPI1_SCK - - - - - - - - - EVENT OUT PA6 - TIM16_ CH1 TIM3_ CH1 TSC_G2 _IO3 TIM8_BKI N SPI1_ MISO TIM1_ BKIN - COMP1_ OUT - - - - - - EVENT OUT PA7 - TIM17_ CH1 TIM3_ CH2 TSC_G2 _IO4 TIM8_CH 1N SPI1_ MOSI TIM1_ CH1N - - - - - - - - EVENT OUT PA8 MCO - - I2C3_ SCL I2C2_ SMBAL I2S2_ MCK TIM1_ CH1 USART1_ CK COMP3_ OUT - TIM4_ ETR - - - - EVENT OUT PA9 - - I2C3_ SMBAL TSC_G4 _IO1 I2C2_SCL I2S3_ MCK TIM1_ CH2 USART1_ TX COMP5_ OUT TIM15_ BKIN TIM2_ CH3 - - - - EVENT OUT 53/173 Pinout and pin description PA0 STM32F303xD STM32F303xE Table 14. STM32F303xD/E alternate function mapping AF0 Port AF2 AF3 I2C3/TIM1 I2C3/TIM TIM2/15/ /2/3/4/8/20 8/20/15/G 16/17/E /15/GPCO PCOMP7 VENT MP1 /TSC AF4 I2C1/2/TI M1/8/16/ 17 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SPI1/SPI2 /I2S2/SPI3 SPI2/I2S2/ USART1/2 I2C3/GPC /I2S3/SPI4 SPI3/I2S3/ /3/CAN/GP CAN/TIM1 OMP1/2/3/ /UART4/5/ TIM1/8/20/ COMP3/5/ /8/15 4/5/6 TIM8/Infra Infrared 6 red TIM2/3/ 4/8/17 TIM1/8 FSMC /TIM1 - - EVENT PA10 - TIM17_ BKIN - TSC_G4 _IO2 I2C2_SDA SPI2_MIS O/I2S2ext _SD TIM1_ CH3 USART1_ RX COMP6_ OUT - TIM2_ CH4 TIM8_B KIN - - - EVENT OUT PA11 - - - - - SPI2_MO SI/I2S2_ SD TIM1_ CH1N USART1_ CTS COMP1_ OUT CAN_RX TIM4_ CH1 TIM1_ CH4 TIM1_ BKIN2 - - EVENT OUT PA12 - TIM16_ CH1 - - - I2SCKIN TIM1_ CH2N USART1_ RTS COMP2_ OUT CAN_TX TIM4_ CH2 TIM1_ ETR - - - EVENT OUT PA13 SWDIOJTMS TIM16_ CH1N - TSC_G4 _IO3 - IR-OUT - USART3_ CTS - - TIM4_ CH3 - - - - EVENT OUT PA14 SWCLKJTCK - - TSC_G4 _IO4 I2C1_SDA TIM8_ CH2 TIM1_ BKIN USART2_ TX - - - - - - - EVENT OUT PA15 JTDI TIM2_ CH1/TIM 2_ETR TIM8_ CH1 TSC_ SYNC SPI3_NSS /I2S3_WS USART2_ RX - TIM1_ BKIN - - - - - EVENT OUT PB0 - - TIM3_ CH3 TSC_G3 _IO2 TIM8_ CH2N - TIM1_ CH2N - - - - - - - - EVENT OUT PB1 - - TIM3_ CH4 TSC_G3 _IO3 TIM8_ CH3N - TIM1_ CH3N - COMP4_ OUT - - - - - - EVENT OUT PB2 - - - TSC_G3 _IO4 - - - - - - - - - - - EVENT OUT PB3 JTDOTRACES WO TIM2_ CH2 TIM4_ ETR TSC_G5 _IO1 TIM8_ CH1N SPI1_SCK SPI3_SCK /I2S3_CK USART2_ TX - - TIM3_ ETR - - - - EVENT OUT I2C1_SCL SPI1_NSS STM32F303xD STM32F303xE Port B DocID026415 Rev 5 Port A SYS_AF AF1 Pinout and pin description 54/173 Table 14. STM32F303xD/E alternate function mapping (continued) AF0 Port DocID026415 Rev 5 Port B SYS_AF AF1 AF2 AF3 I2C3/TIM1 I2C3/TIM TIM2/15/ /2/3/4/8/20 8/20/15/G 16/17/E /15/GPCO PCOMP7 VENT MP1 /TSC AF4 I2C1/2/TI M1/8/16/ 17 AF5 AF6 AF7 AF8 AF9 SPI1/SPI2 /I2S2/SPI3 SPI2/I2S2/ USART1/2 I2C3/GPC /I2S3/SPI4 SPI3/I2S3/ /3/CAN/GP CAN/TIM1 OMP1/2/3/ /UART4/5/ TIM1/8/20/ COMP3/5/ /8/15 4/5/6 TIM8/Infra Infrared 6 red AF10 AF11 AF12 AF13 AF14 AF15 TIM2/3/ 4/8/17 TIM1/8 FSMC /TIM1 - - EVENT JTRST TIM16_ CH1 TIM3_ CH1 TSC_G5 _IO2 TIM8_ CH2N SPI1_ MISO SPI3_MIS O/I2S3ext _SD USART2_ RX - - TIM17_ BKIN - - - - EVENT OUT PB5 - TIM16_ BKIN TIM3_ CH2 TIM8_ CH3N I2C1_ SMBAl SPI1_ MOSI SPI3_MO SI/I2S3_ SD USART2_ CK I2C3_SDA - TIM17_ CH1 - - - - EVENT OUT PB6 - TIM16_ CH1N TIM4_ CH1 TSC_G5 _IO3 I2C1_SCL TIM8_ CH1 TIM8_ ETR USART1_ TX - - TIM8_ BKIN2 - - - - EVENT OUT PB7 - TIM17_ CH1N TIM4_ CH2 TSC_G5 _IO4 I2C1_SDA TIM8_ BKIN - USART1_ RX - - TIM3_ CH4 - FMC_ NADV - - EVENT OUT PB8 - TIM16_ CH1 TIM4_ CH3 TSC_ SYNC I2C1_SCL - - USART3_ RX COMP1_ OUT CAN_RX TIM8_ CH2 - TIM1_ BKIN - - EVENT OUT PB9 - TIM17_ CH1 TIM4_ CH4 - I2C1_SDA - IR-OUT USART3_ TX COMP2_ OUT CAN_TX TIM8_ CH3 - - - - EVENT OUT PB10 - TIM2_ CH3 - TSC_ SYNC - - - USART3_ TX - - - - - - - EVENT OUT PB11 - TIM2_ CH4 - TSC_G6 _IO1 - - - USART3_ RX - - - - - - - EVENT OUT PB12 - - - TSC_G6 _IO2 I2C2_ SMBAL SPI2_NSS /I2S2_WS TIM1_ BKIN USART3_ CK - - - - - - - EVENT OUT PB13 - - - TSC_G6 _IO3 - SPI2_SCK /I2S2_CK TIM1_ CH1N USART3_ CTS - - - - - - - EVENT OUT 55/173 Pinout and pin description PB4 STM32F303xD STM32F303xE Table 14. STM32F303xD/E alternate function mapping (continued) AF0 Port AF2 AF3 I2C3/TIM1 I2C3/TIM TIM2/15/ /2/3/4/8/20 8/20/15/G 16/17/E /15/GPCO PCOMP7 VENT MP1 /TSC AF4 I2C1/2/TI M1/8/16/ 17 AF5 AF6 AF7 AF8 AF9 SPI1/SPI2 /I2S2/SPI3 SPI2/I2S2/ USART1/2 I2C3/GPC /I2S3/SPI4 SPI3/I2S3/ /3/CAN/GP CAN/TIM1 OMP1/2/3/ /UART4/5/ TIM1/8/20/ COMP3/5/ /8/15 4/5/6 TIM8/Infra Infrared 6 red AF10 AF11 AF12 AF13 AF14 AF15 TIM2/3/ 4/8/17 TIM1/8 FSMC /TIM1 - - EVENT PB14 - TIM15_ CH1 - TSC_G6 _IO4 - SPI2_MIS O/I2S2ext _SD TIM1_ CH2N USART3_ RTS - - - - - - - EVENT OUT PB15 RTC_ REFIN TIM15_ CH2 TIM15_ CH1N - TIM1_ CH3N SPI2_MO SI/I2S2_S D - - - - - - - - - EVENT OUT PC0 - EVENT OUT TIM1_ CH1 - - - - - - - - - - - - - PC1 - EVENT OUT TIM1_ CH2 - - - - - - - - - - - - - PC2 - EVENT OUT TIM1_ CH3 COMP7_ OUT - - - - - - - - - - - - PC3 - EVENT OUT TIM1_ CH4 - - - TIM1_ BKIN2 - - - - - - - - - PC4 - EVENT OUT TIM1_ ETR - - - - USART1_ TX - - - - - - - - PC5 - EVENT OUT TIM15_ BKIN TSC_G3 _IO1 - - - USART1_ RX - - - - - - - - PC6 - EVENT OUT TIM3_ CH1 - TIM8_ CH1 - I2S2_ MCK COMP6_O UT - - - - - - - - PC7 - EVENT OUT TIM3_ CH2 - TIM8_ CH2 - I2S3_ MCK COMP5_O UT - - - - - - - - PC8 - EVENT OUT TIM3_ CH3 - TIM8_ CH3 - - COMP3_O UT - - - - - - - - PC9 - EVENT OUT TIM3_ CH4 I2C3_ SDA TIM8_ CH4 I2SCKIN TIM8_ BKIN2 - - - - - - - - - STM32F303xD STM32F303xE Port C DocID026415 Rev 5 Port B SYS_AF AF1 Pinout and pin description 56/173 Table 14. STM32F303xD/E alternate function mapping (continued) AF0 Port AF2 AF3 I2C3/TIM1 I2C3/TIM TIM2/15/ /2/3/4/8/20 8/20/15/G 16/17/E /15/GPCO PCOMP7 VENT MP1 /TSC AF4 I2C1/2/TI M1/8/16/ 17 AF5 AF6 AF7 AF8 AF9 SPI1/SPI2 /I2S2/SPI3 SPI2/I2S2/ USART1/2 I2C3/GPC /I2S3/SPI4 SPI3/I2S3/ /3/CAN/GP CAN/TIM1 OMP1/2/3/ /UART4/5/ TIM1/8/20/ COMP3/5/ /8/15 4/5/6 TIM8/Infra Infrared 6 red AF10 AF11 AF12 AF13 AF14 AF15 TIM2/3/ 4/8/17 TIM1/8 FSMC /TIM1 - - EVENT 57/173 PC10 - EVENT OUT - - TIM8_ CH1N UART4_ TX SPI3_SCK /I2S3_CK USART3_ TX - - - - - - - - PC11 - EVENT OUT - - TIM8_ CH2N UART4_ RX SPI3_MIS O/I2S3ext _SD USART3_ RX - - - - - - - - PC12 - EVENT OUT - - TIM8_ CH3N UART5_ TX SPI3_MO SI/I2S3_ SD USART3_ CK - - - - - - - - PC13 - EVENT OUT - - TIM1_ CH1N - - - - - - - - - - - PC14 - EVENT OUT - - - - - - - - - - - - - - PC15 - EVENT OUT - - - - - - - - - - - - - - PD0 - EVENT OUT - - - - - CAN_RX - - - - FMC_D2 - - - PD1 - EVENT OUT - - TIM8_ CH4 TIM8_ BKIN2 CAN_TX - - - - FMC_D3 - - - PD2 - EVENT OUT TIM3_ ETR - TIM8_ BKIN UART5_ RX - - - - - - - - - - PD3 - EVENT OUT TIM2_CH 1/TIM2_ ETR - - - - USART2_ CTS - - - - FMC_ CLK - - - PD4 - EVENT OUT TIM2_ CH2 - - - - USART2_ RTS - - - - FMC_ NOE - - - Pinout and pin description Port D DocID026415 Rev 5 Port C SYS_AF AF1 STM32F303xD STM32F303xE Table 14. STM32F303xD/E alternate function mapping (continued) AF0 Port DocID026415 Rev 5 Port D SYS_AF AF1 AF2 AF3 I2C3/TIM1 I2C3/TIM TIM2/15/ /2/3/4/8/20 8/20/15/G 16/17/E /15/GPCO PCOMP7 VENT MP1 /TSC AF4 I2C1/2/TI M1/8/16/ 17 AF5 AF6 AF7 AF8 AF9 AF10 AF11 AF12 AF13 AF14 AF15 SPI1/SPI2 /I2S2/SPI3 SPI2/I2S2/ USART1/2 I2C3/GPC /I2S3/SPI4 SPI3/I2S3/ /3/CAN/GP CAN/TIM1 OMP1/2/3/ /UART4/5/ TIM1/8/20/ COMP3/5/ /8/15 4/5/6 TIM8/Infra Infrared 6 red TIM2/3/ 4/8/17 TIM1/8 FSMC /TIM1 - - EVENT - EVENT OUT - - - - - USART2_ TX - - - - FMC_ NWE - - - PD6 - EVENT OUT TIM2_ CH4 - - - - USART2_ RX - - - - FMC_ NWAIT - - - PD7 - EVENT OUT TIM2_ CH3 - - - - USART2_ CK - - - - FMC_NE 1/FMC_ NCE2 - - - PD8 - EVENT OUT - - - - - USART3_ TX - - - - FMC_ D13 - - - PD9 - EVENT OUT - - - - - USART3_ RX - - - - FMC_ D14 - - - PD10 - EVENT OUT - - - - - USART3_ CK - - - - FMC_ D15 - - - PD11 - EVENT OUT - - - - - USART3_ CTS - - - - FMC_ A16 - - - PD12 - EVENT OUT TIM4_ CH1 TSC_G8 _IO1 - - - USART3_ RTS - - - - FMC_ A17 - - - PD13 - EVENT OUT TIM4_ CH2 TSC_G8 _IO2 - - - - - - - - FMC_ A18 - - - PD14 - EVENT OUT TIM4_ CH3 TSC_G8 _IO3 - - - - - - - - FMC_D0 - - - PD15 - EVENT OUT TIM4_ CH4 TSC_G8 _IO4 - - SPI2_NSS - - - - - FMC_D1 - - - STM32F303xD STM32F303xE PD5 Pinout and pin description 58/173 Table 14. STM32F303xD/E alternate function mapping (continued) AF0 Port DocID026415 Rev 5 Port E SYS_AF AF1 AF2 AF3 I2C3/TIM1 I2C3/TIM TIM2/15/ /2/3/4/8/20 8/20/15/G 16/17/E /15/GPCO PCOMP7 VENT MP1 /TSC AF4 I2C1/2/TI M1/8/16/ 17 AF5 AF6 AF7 AF8 AF9 SPI1/SPI2 /I2S2/SPI3 SPI2/I2S2/ USART1/2 I2C3/GPC /I2S3/SPI4 SPI3/I2S3/ /3/CAN/GP CAN/TIM1 OMP1/2/3/ /UART4/5/ TIM1/8/20/ COMP3/5/ /8/15 4/5/6 TIM8/Infra Infrared 6 red AF10 AF11 AF12 AF13 AF14 AF15 TIM2/3/ 4/8/17 TIM1/8 FSMC /TIM1 - - EVENT - EVENT OUT TIM4_ ETR - TIM16_ CH1 - TIM20_ ETR USART1_ TX - - - - FMC_ NBL0 - - - PE1 - EVENT OUT - - TIM17_ CH1 - TIM20_ CH4 USART1_ RX - - - - FMC_ NBL1 - - - PE2 TRACECK EVENT OUT TIM3_ CH1 TSC_G7 _IO1 - SPI4_SCK TIM20_ CH1 - - - - - FMC_ A23 - - - PE3 TRACED0 EVENT OUT TIM3_ CH2 TSC_G7 _IO2 - SPI4_NSS TIM20_ CH2 - - - - - FMC_ A19 - - - PE4 TRACED1 EVENT OUT TIM3_ CH3 TSC_G7 _IO3 - SPI4_NSS TIM20_ CH1N - - - - - FMC_ A20 - - - PE5 TRACED2 EVENT OUT TIM3_ CH4 TSC_G7 _IO4 - SPI4_ MISO TIM20_ CH2N - - - - - FMC_ A21 - - - PE6 TRACED3 EVENT OUT - - - SPI4_ MOSI TIM20_ CH3N - - - - - FMC_ A22 - - - PE7 - EVENT OUT TIM1_ ETR - - - - - - - - - FMC_D4 - - - PE8 - EVENT OUT TIM1_ CH1N - - - - - - - - - FMC_D5 - - - PE9 - EVENT OUT TIM1_ CH1 - - - - - - - - - FMC_D6 - - - PE10 - EVENT OUT TIM1_ CH2N - - - - - - - - - FMC_D7 - - - PE11 - EVENT OUT TIM1_ CH2 - - SPI4_NSS - - - - - - FMC_D8 - - - 59/173 Pinout and pin description PE0 STM32F303xD STM32F303xE Table 14. STM32F303xD/E alternate function mapping (continued) AF0 Port Port E SYS_AF DocID026415 Rev 5 AF2 AF3 I2C3/TIM1 I2C3/TIM TIM2/15/ /2/3/4/8/20 8/20/15/G 16/17/E /15/GPCO PCOMP7 VENT MP1 /TSC AF4 I2C1/2/TI M1/8/16/ 17 AF5 AF6 AF7 AF8 AF9 SPI1/SPI2 /I2S2/SPI3 SPI2/I2S2/ USART1/2 I2C3/GPC /I2S3/SPI4 SPI3/I2S3/ /3/CAN/GP CAN/TIM1 OMP1/2/3/ /UART4/5/ TIM1/8/20/ COMP3/5/ /8/15 4/5/6 TIM8/Infra Infrared 6 red AF10 AF11 AF12 AF13 AF14 AF15 TIM2/3/ 4/8/17 TIM1/8 FSMC /TIM1 - - EVENT PE12 - EVENT OUT TIM1_ CH3N - - SPI4_SCK - - - - - - FMC_D9 - - - PE13 - EVENT OUT TIM1_ CH3 - - SPI4_ MISO - - - - - - FMC_ D10 - - - PE14 - EVENT OUT TIM1_ CH4 - - SPI4_ MOSI TIM1_ BKIN2 - - - - - FMC_ D11 - - - PE15 - EVENT OUT TIM1_ BKIN - - - - USART3_ RX - - - - FMC_ D12 - - - PF0 - EVENT OUT - - I2C2_SDA SPI2_NSS /I2S2_WS TIM1_ CH3N - - - - - - - - - PF1 - EVENT OUT - - I2C2_SCL SPI2_SCK /I2S2_CK - - - - - - - - - - PF2 - EVENT OUT TIM20_ CH3 - - - - - - - - - FMC_A2 - - - PF3 - EVENT OUT TIM20_ CH4 - - - - - - - - - FMC_A3 - - - PF4 - EVENT OUT COMP1_ OUT TIM20_ CH1N - - - - - - - - FMC_A4 - - - PF5 - EVENT OUT TIM20_ CH2N - - - - - - - - - FMC_A5 - - - PF6 - EVENT OUT TIM4_ CH4 - I2C2_SCL - - USART3_ RTS - - - - FMC_ NIORD - - - PF7 - EVENT OUT TIM20_ BKIN - - - - - - - - - FMC_ NREG - - - STM32F303xD STM32F303xE Port F AF1 Pinout and pin description 60/173 Table 14. STM32F303xD/E alternate function mapping (continued) AF0 Port AF2 AF3 I2C3/TIM1 I2C3/TIM TIM2/15/ /2/3/4/8/20 8/20/15/G 16/17/E /15/GPCO PCOMP7 VENT MP1 /TSC AF4 I2C1/2/TI M1/8/16/ 17 AF5 AF6 AF7 AF8 AF9 SPI1/SPI2 /I2S2/SPI3 SPI2/I2S2/ USART1/2 I2C3/GPC /I2S3/SPI4 SPI3/I2S3/ /3/CAN/GP CAN/TIM1 OMP1/2/3/ /UART4/5/ TIM1/8/20/ COMP3/5/ /8/15 4/5/6 TIM8/Infra Infrared 6 red AF10 AF11 AF12 AF13 AF14 AF15 TIM2/3/ 4/8/17 TIM1/8 FSMC /TIM1 - - EVENT 61/173 PF8 - EVENT OUT TIM20_ BKIN2 - - - - - - - - - FMC_ NIOWR - - - PF9 - EVENT OUT TIM20_ BKIN TIM15_ CH1 - SPI2_SCK - - - - - - FMC_CD - - - PF10 - EVENT OUT TIM20_ BKIN2 TIM15_ CH2 - SPI2_SCK - - - - - - FMC_ INTR - - - PF11 - EVENT OUT TIM20_ ETR - - - - - - - - - - - - - PF12 - EVENT OUT TIM20_ CH1 - - - - - - - - - FMC_A6 - - - PF13 - EVENT OUT TIM20_ CH2 - - - - - - - - - FMC_A7 - - - PF14 - EVENT OUT TIM20_ CH3 - - - - - - - - - FMC_A8 - - - PF15 - EVENT OUT TIM20_ CH4 - - - - - - - - - FMC_A9 - - - PG0 - EVENT OUT TIM20_ CH1N - - - - - - - - - FMC_ A10 - - - PG1 - EVENT OUT TIM20_ CH2N - - - - - - - - - FMC_ A11 - - - PG2 - EVENT OUT TIM20_ CH3N - - - - - - - - - FMC_ A12 - - - PG3 - EVENT OUT TIM20_ BKIN - - - - - - - - - FMC_ A13 - - - PG4 - EVENT OUT TIM20_ BKIN2 - - - - - - - - - FMC_ A14 - - - Pinout and pin description Port G DocID026415 Rev 5 Port F SYS_AF AF1 STM32F303xD STM32F303xE Table 14. STM32F303xD/E alternate function mapping (continued) AF0 Port DocID026415 Rev 5 Port G SYS_AF AF1 AF2 AF3 I2C3/TIM1 I2C3/TIM TIM2/15/ /2/3/4/8/20 8/20/15/G 16/17/E /15/GPCO PCOMP7 VENT MP1 /TSC AF4 I2C1/2/TI M1/8/16/ 17 AF5 AF6 AF7 AF8 AF9 SPI1/SPI2 /I2S2/SPI3 SPI2/I2S2/ USART1/2 I2C3/GPC /I2S3/SPI4 SPI3/I2S3/ /3/CAN/GP CAN/TIM1 OMP1/2/3/ /UART4/5/ TIM1/8/20/ COMP3/5/ /8/15 4/5/6 TIM8/Infra Infrared 6 red AF10 AF11 AF12 AF13 AF14 AF15 TIM2/3/ 4/8/17 TIM1/8 FSMC /TIM1 - - EVENT - EVENT OUT TIM20_ ETR - - - - - - - - - FMC_ A15 - - - PG6 - EVENT OUT - - - - - - - - - - FMC_ INT2 - - - PG7 - EVENT OUT - - - - - - - - - - FMC_ INT3 - - - PG8 - EVENT OUT - - - - - - - - - - - - - - PG9 - EVENT OUT - - - - - - - - - - FMC_NE 2/FMC_ NCE3 - - - PG10 - EVENT OUT - - - - - - - - - - FMC_ NCE4_1/ FMC_ NE3 - - - PG11 - EVENT OUT - - - - - - - - - - FMC_ NCE4_2 - - - PG12 - EVENT OUT - - - - - - - - - - FMC_ NE4 - - - PG13 - EVENT OUT - - - - - - - - - - FMC_ A24 - - - PG14 - EVENT OUT - - - - - - - - - - FMC_ A25 - - - PG15 - EVENT OUT - - - - - - - - - - - - - - STM32F303xD STM32F303xE PG5 Pinout and pin description 62/173 Table 14. STM32F303xD/E alternate function mapping (continued) AF0 Port Port H SYS_AF AF1 AF2 AF3 I2C3/TIM1 I2C3/TIM TIM2/15/ /2/3/4/8/20 8/20/15/G 16/17/E /15/GPCO PCOMP7 VENT MP1 /TSC AF4 I2C1/2/TI M1/8/16/ 17 AF5 AF6 AF7 AF8 AF9 SPI1/SPI2 /I2S2/SPI3 SPI2/I2S2/ USART1/2 I2C3/GPC /I2S3/SPI4 SPI3/I2S3/ /3/CAN/GP CAN/TIM1 OMP1/2/3/ /UART4/5/ TIM1/8/20/ COMP3/5/ /8/15 4/5/6 TIM8/Infra Infrared 6 red AF10 AF11 AF12 AF13 AF14 AF15 TIM2/3/ 4/8/17 TIM1/8 FSMC /TIM1 - - EVENT DocID026415 Rev 5 PH0 - EVENT OUT TIM20_ CH1 - - - - - - - - - FMC_A0 - - - PH1 - EVENT OUT TIM20_ CH2 - - - - - - - - - FMC_A1 - - - PH2 - EVENT OUT - - - - - - - - - - - - - - STM32F303xD STM32F303xE Table 14. STM32F303xD/E alternate function mapping (continued) Pinout and pin description 63/173 Memory mapping 5 STM32F303xD STM32F303xE Memory mapping Figure 9. STM32F303xD/E memory map [)) [)))))))) &RUWH[0 ZLWK)38 ,QWHUQDO 3HULSKHUDOV [( $+% [ 5HVHUYHG [ $+% [ 5HVHUYHG [& [)) $+% [ 5HVHUYHG [$ [& )0&FRQWURO UHJLVWHUV [$ [ $3% [ 5HVHUYHG )0& EDQNDQG EDQN [$ )0& EDQNDQG EDQN [))))))) [ $3% [ 2SWLRQE\WHV [)))) 6\VWHPPHPRU\ [)))' [ 3HULSKHUDOV [ 5HVHUYHG &&05$0 [ [ [ 65$0 &2'( )ODVKPHPRU\ [ [ 5HVHUYHG 64/173 5HVHUYHG 5HVHUYHG [ [ )ODVKV\VWHP PHPRU\RU65$0 GHSHQGLQJRQ%227 FRQILJXUDWLRQ 06Y9 DocID026415 Rev 5 STM32F303xD STM32F303xE Memory mapping Table 15. Memory map, peripheral register boundary addresses Bus AHB4 AHB3 - AHB2 - AHB1 Boundary address Size (bytes) Peripheral 0xA000 0000 - 0xA000 0FFF 4K 0x8000 0000 - 0x9FFF FFFF 512 M FSMC Banks 3 and 4 0x6000 0000 - 0x7FFF FFFF 512 M FSMC Banks 1 and 2 0x5000 0800 - 0x5FFF FFFF 384 M Reserved 0x5000 0400 - 0x5000 07FF 1K ADC3 - ADC4 0x5000 0000 - 0x5000 03FF 1K ADC1 - ADC2 0x4800 2000 - 0x4FFF FFFF ~132 M 0x4800 1C00 - 0x4800 1FFF 1K GPIOH 0x4800 1800 - 0x4800 1BFF 1K GPIOG 0x4800 1400 - 0x4800 17FF 1K GPIOF 0x4800 1000 - 0x4800 13FF 1K GPIOE 0x4800 0C00 - 0x4800 0FFF 1K GPIOD 0x4800 0800 - 0x4800 0BFF 1K GPIOC 0x4800 0400 - 0x4800 07FF 1K GPIOB 0x4800 0000 - 0x4800 03FF 1K GPIOA 0x4002 4400 - 0x47FF FFFF ~128 M 0x4002 4000 - 0x4002 43FF 1K TSC 0x4002 3400 - 0x4002 3FFF 3K Reserved 0x4002 3000 - 0x4002 33FF 1K CRC 0x4002 2400 - 0x4002 2FFF 3K Reserved 0x4002 2000 - 0x4002 23FF 1K Flash interface 0x4002 1400 - 0x4002 1FFF 3K Reserved 0x4002 1000 - 0x4002 13FF 1K RCC 0x4002 0800 - 0x4002 0FFF 2K Reserved 0x4002 0400 - 0x4002 07FF 1K DMA2 0x4002 0000 - 0x4002 03FF 1K DMA1 DocID026415 Rev 5 FSMC control registers Reserved Reserved 65/173 67 Memory mapping STM32F303xD STM32F303xE Table 15. Memory map, peripheral register boundary addresses (continued) Bus - APB2 - 66/173 Boundary address Size (bytes) Peripheral 0x4001 8000 - 0x4001 FFFF 32 K Reserved 0x4001 5400 - 0x4001 7FFF 11 K Reserved 0x4001 5000 - 0x4001 53FF 1K TIM20 0x4001 4C00 - 0x4001 4FFF 1K Reserved 0x4001 4800 - 0x4001 4BFF 1K TIM17 0x4001 4400 - 0x4001 47FF 1K TIM16 0x4001 4000 - 0x4001 43FF 1K TIM15 0x4001 3C00 - 0x4001 3FFF 1K SPI4 0x4001 3800 - 0x4001 3BFF 1K USART1 0x4001 3400 - 0x4001 37FF 1K TIM8 0x4001 3000 - 0x4001 33FF 1K SPI1 0x4001 2C00 - 0x4001 2FFF 1K TIM1 0x4001 0800 - 0x4001 2BFF 9K Reserved 0x4001 0400 - 0x4001 07FF 1K EXTI 0x4001 0000 - 0x4001 03FF 1K SYSCFG + COMP + OPAMP 0x4000 7C00 - 0x4000 FFFF 32 K Reserved DocID026415 Rev 5 STM32F303xD STM32F303xE Memory mapping Table 15. Memory map, peripheral register boundary addresses (continued) Bus APB1 Boundary address Size (bytes) Peripheral 0x4000 7800 - 0x4000 7BFF 1K I2C3 0x4000 7400 - 0x4000 77FF 1K DAC 0x4000 7000 - 0x4000 73FF 1K PWR 0x4000 6800 - 0x4000 6FFF 2K Reserved 0x4000 6400 - 0x4000 67FF 1K bxCAN 0x4000 6000 - 0x4000 63FF 1K USB/CAN SRAM 0x4000 5C00 - 0x4000 5FFF 1K USB device FS 0x4000 5800 - 0x4000 5BFF 1K I2C2 0x4000 5400 - 0x4000 57FF 1K I2C1 0x4000 5000 - 0x4000 53FF 1K UART5 0x4000 4C00 - 0x4000 4FFF 1K UART4 0x4000 4800 - 0x4000 4BFF 1K USART3 0x4000 4400 - 0x4000 47FF 1K USART2 0x4000 4000 - 0x4000 43FF 1K I2S3ext 0x4000 3C00 - 0x4000 3FFF 1K SPI3/I2S3 0x4000 3800 - 0x4000 3BFF 1K SPI2/I2S2 0x4000 3400 - 0x4000 37FF 1K I2S2ext 0x4000 3000 - 0x4000 33FF 1K IWDG 0x4000 2C00 - 0x4000 2FFF 1K WWDG 0x4000 2800 - 0x4000 2BFF 1K RTC 0x4000 1800 - 0x4000 27FF 4K Reserved 0x4000 1400 - 0x4000 17FF 1K TIM7 0x4000 1000 - 0x4000 13FF 1K TIM6 0x4000 0C00 - 0x4000 0FFF 1K Reserved 0x4000 0800 - 0x4000 0BFF 1K TIM4 0x4000 0400 - 0x4000 07FF 1K TIM3 0x4000 0000 - 0x4000 03FF 1K TIM2 DocID026415 Rev 5 67/173 67 Electrical characteristics STM32F303xD STM32F303xE 6 Electrical characteristics 6.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 6.1.1 Minimum and maximum values Unless otherwise specified, the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 C and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes and are not tested in production. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3). 6.1.2 Typical values Unless otherwise specified, typical data are based on TA = 25 C, VDD = VDDA = 2.0 to 3.6 V. They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2). 6.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 6.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 10. 6.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 11. Figure 10. Pin loading conditions Figure 11. Pin input voltage 0&8SLQ 0&8SLQ & S) 9,1 069 68/173 DocID026415 Rev 5 069 STM32F303xD STM32F303xE 6.1.6 Electrical characteristics Power supply scheme Figure 12. Power supply scheme 9%$7 %DFNXSFLUFXLWU\ /6(57& :DNHXSORJLF %DFNXSUHJLVWHUV 287 *3,2V ,1 /HYHOVKLIWHU 3RZHU VZLWFK 9 9'' [9'' [Q) [) ,2ORJLF .HUQHOORJLF &38 GLJLWDO PHPRULHV 5HJXODWRU [966 9''$ 9''$ 95() Q) ) Q) ) 95() $'&'$& 95() $QDORJ5&V 3//FRPSDUDWRUV23$03 966$ 069 1. Dotted lines represent the internal connections on low pin count packages, joining the dedicated supply pins. Caution: Each power supply pair (VDD/VSS, VDDA/VSSA etc.) must be decoupled with filtering ceramic capacitors as shown above. These capacitors must be placed as close as possible to, or below the appropriate pins on the underside of the PCB to ensure the good functionality of the device. DocID026415 Rev 5 69/173 151 Electrical characteristics 6.1.7 STM32F303xD STM32F303xE Current consumption measurement Figure 13. Current consumption measurement scheme )$$ 6$$ )$$! 6$$! -36 6.2 Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 16: Voltage characteristics, Table 17: Current characteristics, and Table 18: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 16. Voltage characteristics(1) Symbol Ratings Min Max VDD-VSS External main supply voltage (including VDDA, VBAT and VDD) -0.3 4.0 Allowed voltage difference for VDD > VDDA - 0.4 Allowed voltage difference for VREF+ > VDDA - 0.4 Input voltage on FT and FTf pins VSS -0.3 VDD + 4.0 Input voltage on TTa pins VSS -0.3 4.0 Input voltage on any other pin VSS - 0.3 4.0 Input voltage on Boot0 pin 0 9 Variations between different VDD power pins - 50 Variations between all the different ground pins - 50 VDD-VDDA VREF+-VDDA(2) VIN(3) |VDDx| |VSSX - VSS| VESD(HBM) Electrostatic discharge voltage (human body model) Unit V V mV see Section 6.3.13: Electrical sensitivity characteristics 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. The following relationship must be respected between VDDA and VDD: VDDA must power on before or at the same time as VDD in the power up sequence. VDDA must be greater than or equal to VDD. 2. VREF+ must be always lower or equal than VDDA (VREF+ VDDA). If unused then it must be connected to VDDA. 3. VIN maximum must always be respected. Refer to Table 17: Current characteristics for the maximum allowed injected current values. 70/173 DocID026415 Rev 5 - STM32F303xD STM32F303xE Electrical characteristics Table 17. Current characteristics Symbol Ratings Max. IVDD Total current into sum of all VDD_x power lines (source) 160 IVSS Total current out of sum of all VSS_x ground lines (sink) -160 IVDD Maximum current into each VDD_x power line (source) (1) 100 IVSS Maximum current out of each VSS _x ground line (sink)(1) 100 Output current sunk by any I/O and control pin 25 IIO(PIN) IIO(PIN) Output current source by any I/O and control pin Total output current sunk by sum of all IOs and control pins Total output current sourced by sum of all IOs and control pins(2) Injected current on FT, FTf, and B IINJ(PIN) Injected current on TC and RST Injected current on TTa pins IINJ(PIN) -25 (2) pins(3) 80 Unit mA -80 -5/+0 pin(4) 5 (5) 5 Total injected current (sum of all I/O and control pins)(6) 25 1. All main power (VDD, VDDA) and ground (VSS and VSSA) pins must always be connected to the external power supply, in the permitted range. 2. This current consumption must be correctly distributed over all I/Os and control pins.The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count LQFP packages. 3. Positive injection is not possible on these I/Os and does not occur for input voltages lower than the specified maximum value. 4. A positive injection is induced by VIN > VDD while a negative injection is induced by VIN< VSS. IINJ(PIN) must never be exceeded. Refer to Table 16: Voltage characteristics for the maximum allowed input voltage values. 5. A positive injection is induced by VIN > VDDA while a negative injection is induced by VIN< VSS. IINJ(PIN) must never be exceeded. Refer also to Table 16: Voltage characteristics for the maximum allowed input voltage values. Negative injection disturbs the analog performance of the device. See note (2) below Table 81. 6. When several inputs are submitted to a current injection, the maximum IINJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values). Table 18. Thermal characteristics Symbol TSTG TJ Ratings Storage temperature range Maximum junction temperature DocID026415 Rev 5 Value Unit -65 to +150 C 150 C 71/173 151 Electrical characteristics STM32F303xD STM32F303xE 6.3 Operating conditions 6.3.1 General operating conditions Table 19. General operating conditions Symbol Parameter Conditions Min Max fHCLK Internal AHB clock frequency - 0 72 fPCLK1 Internal APB1 clock frequency - 0 36 fPCLK2 Internal APB2 clock frequency - 0 72 Standard operating voltage - 2 3.6 2 3.6 VDD VDDA VBAT Analog operating voltage (OPAMP and DAC not used) Analog operating voltage (OPAMP and DAC used) Must have a potential equal to or higher than VDD 3.6 1.65 3.6 -0.3 VDD+0.3 -0.3 VDDA+0.3 -0.3 5.5 BOOT0 0 5.5 LQFP144 - 606 WLCSP100 - 454 LQFP100 - 476 UFBGA100 - 339 LQFP64 - 435 -40 85 -40 105 Maximum power dissipation -40 105 Low power dissipation(3) -40 125 6 suffix version -40 105 7 suffix version -40 125 TC I/O TTa I/O VIN PD FT and FTf I/O input voltage Power dissipation at TA = 85 C for suffix 6 or TA = 105 C for suffix 7(2) Ambient temperature for 6 suffix version TA Ambient temperature for 7 suffix version TJ I/O(1) Junction temperature range Maximum power dissipation Low power dissipation(3) MHz V V 2.4 Backup operating voltage Unit V V mW C C C 1. To sustain a voltage higher than VDD+0.3 V, the internal pull-up/pull-down resistors must be disabled. 2. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJmax (see Section 7.7: Thermal characteristics). 3. In low power dissipation state, TA can be extended to this range as long as TJ does not exceed TJmax (see Section 7.7: Thermal characteristics). 72/173 DocID026415 Rev 5 STM32F303xD STM32F303xE 6.3.2 Electrical characteristics Operating conditions at power-up / power-down The parameters given in Table 20 are derived from tests performed under the ambient temperature condition summarized in Table 19. Table 20. Operating conditions at power-up / power-down Symbol Parameter VDD rise time rate tVDD - VDD fall time rate VDDA rise time rate tVDDA 6.3.3 Conditions - VDDA fall time rate Min Max 0 20 0 20 Unit s/V Embedded reset and power control block characteristics The parameters given in Table 21 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 19. Table 21. Embedded reset and power control block characteristics Symbol VPOR/PDR(1) VPDRhyst (1) Parameter Conditions Power on/power down reset threshold Min. Typ. Max. Falling edge 1.8(2) 1.88 1.96 V Rising edge 1.84 1.92 2.0 V - 40 - mV PDR hysteresis - Unit 1. The PDR detector monitors VDD and also VDDA (if kept enabled in the option bytes). The POR detector monitors only VDD. 2. The product behavior is guaranteed by design down to the minimum VPOR/PDR value. Table 22. Programmable voltage detector characteristics Symbol Parameter VPVD0 PVD threshold 0 VPVD1 PVD threshold 1 VPVD2 PVD threshold 2 VPVD3 PVD threshold 3 VPVD4 PVD threshold 4 VPVD5 PVD threshold 5 Min(1) Typ Max(1) Rising edge 2.1 2.18 2.26 Falling edge 2 2.08 2.16 Rising edge 2.19 2.28 2.37 Falling edge 2.09 2.18 2.27 Rising edge 2.28 2.38 2.48 Falling edge 2.18 2.28 2.38 Rising edge 2.38 2.48 2.58 Falling edge 2.28 2.38 2.48 Rising edge 2.47 2.58 2.69 Falling edge 2.37 2.48 2.59 Rising edge 2.57 2.68 2.79 Falling edge 2.47 2.58 2.69 Conditions DocID026415 Rev 5 Unit V 73/173 151 Electrical characteristics STM32F303xD STM32F303xE Table 22. Programmable voltage detector characteristics (continued) Symbol VPVD6 Min(1) Typ Max(1) Rising edge 2.66 2.78 2.9 Falling edge 2.56 2.68 2.8 Rising edge 2.76 2.88 3 Falling edge 2.66 2.78 2.9 Parameter Conditions PVD threshold 6 Unit V VPVD7 PVD threshold 7 VPVDhyst(2) PVD hysteresis - - 100 - mV IDD(PVD) PVD current consumption - - 0.15 0.26 A 1. Data based on characterization results only, not tested in production. 2. Guaranteed by design, not tested in production. 6.3.4 Embedded reference voltage The parameters given in Table 23 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 19. Table 23. Embedded internal reference voltage Symbol Parameter VREFINT Internal reference voltage TS_vrefint VRERINT TCoeff Conditions Min Typ Max Unit -40 C < TA < +105 C 1.16 1.2 1.25 V -40 C < TA < +85 C 1.16 1.2 1.24(1) V ADC sampling time when reading the internal reference voltage - 2.2 - - s Internal reference voltage spread over the temperature range VDD = 3 V 10 mV - - 10(2) mV - - - 100(2) ppm/C Temperature coefficient 1. Data based on characterization results, not tested in production. 2. Guaranteed by design, not tested in production. Table 24. Internal reference voltage calibration values Calibration value name VREFINT_CAL 6.3.5 Description Raw data acquired at temperature of 30 C VDDA= 3.3 V Memory address 0x1FFF F7BA - 0x1FFF F7BB Supply current characteristics The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code. The current consumption is measured as described in Figure 13: Current consumption measurement scheme. 74/173 DocID026415 Rev 5 STM32F303xD STM32F303xE Electrical characteristics All Run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to CoreMark code. Note: The total current consumption is the sum of IDD and IDDA. Typical and maximum current consumption The MCU is placed under the following conditions: * All I/O pins are in input mode with a static value at VDD or VSS (no load) * All peripherals are disabled except when explicitly mentioned * The Flash memory access time is adjusted to the fHCLK frequency (0 wait state from 0 to 24 MHz,1 wait state from 24 to 48 MHz and 2 wait states from 48 to 72 MHz) * Prefetch in ON (reminder: this bit must be set before clock setting and bus prescaling) * When the peripherals are enabled fPCLK2 = fHCLK and fPCLK1 = fHCLK/2 * When fHCLK > 8 MHz, the PLL is ON and the PLL input is equal to HSI/2 (4 MHz) or HSE (8 MHz) in bypass mode. The parameters given in Table 25 to Table 29 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 19. Table 25. Typical and maximum current consumption from VDD supply at VDD = 3.6V All peripherals enabled Symbol Parameter Conditions IDD Supply current in Run mode, executing from Flash fHCLK Max @ TA(1) Typ 85 C 105 C 72 MHz 66.4 76.5 76.9 77.4 64 MHz 59.8 66.4 67.7 48 MHz 47.3 53.7 32 MHz 33.3 85 C 105 C 33.0 37.2 38.1 38.9 68.6 29.7 33.5 34.3 35.0 53.8 55.1 23.2 26.2 27.1 28.0 36.8 37.4 38.5 16.8 19.8 20.6 21.4 24 MHz 26.0 29.4 30.0 31.2 13.5 16.6 17.4 18.6 8 MHz 10.7 13.8 14.4 15.3 6.63 10.2 10.5 11.2 1 MHz 4.27 7.47 8.13 8.90 3.78 7.40 7.70 8.50 64 MHz 55.6 59.6 62.8 63.2 29.4 33.1 34.5 35.0 48 MHz 43.6 Internal 32 MHz 30.8 clock (HSI) 24 MHz 24.0 47.0 49.2 50.1 23.1 26.2 27.1 28.0 33.6 35.3 35.8 16.7 19.8 20.6 21.5 28.0 28.2 29.7 13.5 16.5 17.5 18.4 13.6 14.7 15.2 6.63 9.74 10.6 11.2 72 MHz 66.2 76.2 76.7 77.2(2) 32.8 36.9(2) 37.7 38.5(2) 64 MHz 59.6 66.2 67.6 68.4 29.3 33.1 33.9 34.4 External 48 MHz 47.0 clock (HSE 32 MHz 33.0 bypass) 53.4 53.6 54.9 22.4 25.6 26.2 27.2 36.6 37.2 38.1 16.0 19.0 19.5 20.4 24 MHz 25.6 29.0 29.5 30.6 12.8 15.7 16.3 17.6 8 MHz 13.4 13.8 14.7 6.40 9.48 9.93 10.90 8 MHz 10.5 (2) IDD Supply current in Run mode, executing from RAM Max @ TA(1) Typ 25 C External clock (HSE bypass) 25 C All peripherals disabled 10.3 DocID026415 Rev 5 Unit mA 75/173 151 Electrical characteristics STM32F303xD STM32F303xE Table 25. Typical and maximum current consumption from VDD supply at VDD = 3.6V (continued) All peripherals enabled Symbol Parameter Conditions IDD Supply current in Run mode, executing from RAM fHCLK Max @ TA(1) Typ 85 C 105 C 3.92 7.06 7.54 8.60 64 MHz 55.4 59.2 62.5 48 MHz 43.1 Internal 32 MHz 30.5 clock (HSI) 24 MHz 23.8 46.7 Unit 25 C 85 C 105 C 3.42 6.53 7.05 8.10 62.9 29.1 32.7 34.0 34.6 49.0 49.9 22.8 26.1 26.8 27.8 33.2 35.0 35.5 15.8 18.8 19.5 20.9 27.8 27.9 29.2 12.6 15.6 16.3 17.5 13.1 14.1 14.6 6.20 9.37 10.3 10.7 72 MHz 48.8 53.5 53.6 54.0(2) 7.60 8.20(2) 8.50 9.00(2) 64 MHz 43.5 48.6 49.1 49.3 6.90 7.50 7.80 8.00 48 MHz 33.6 External clock (HSE 32 MHz 24.3 bypass) 24 MHz 18.6 38.1 40.0 41.3 5.30 5.80 6.00 6.40 27.5 28.1 29.3 3.80 4.10 4.40 4.70 21.9 22.4 22.6 2.90 3.30 3.40 3.90 8 MHz 8.24 11.27 11.79 12.70 1.36 1.74 1.85 2.00 1 MHz 3.64 6.72 7.36 8.30 0.79 1.17 1.26 1.35 64 MHz 39.7 43.9 45.5 45.8 6.70 7.30 7.40 7.70 48 MHz 30.4 Internal 32 MHz 21.9 clock (HSI) 24 MHz 17.0 33.9 35.3 36.5 5.10 5.60 5.70 6.10 25.8 26.2 26.7 3.60 4.10 4.20 4.50 20.2 21.5 21.7 2.98 3.41 3.46 3.57 11.0 11.7 12.4 1.41 1.74 1.81 1.87 External clock (HSE bypass) 1 MHz 9.85 (2) IDD Max @ TA(1) Typ 25 C 8 MHz Supply current in Sleep mode, executing from Flash or RAM All peripherals disabled 8 MHz 7.81 mA 1. Data based on characterization results, not tested in production unless otherwise specified. 2. Data based on characterization results and tested in production with code executing from RAM. Table 26. Typical and maximum current consumption from the VDDA supply VDDA = 2.4 V Symbol Parameter IDDA 76/173 Supply current in Run mode, code executing from Flash or RAM Conditions (1) HSE bypass fHCLK Typ VDDA = 3.6 V Max @ TA(2) 25 C 85 C 105 C Typ Max @ TA(2) 25 C Unit 85 C 105 C 72 MHz 220 243 255 260 241 264 281 287 64 MHz 194 215 226 231 212 233 248 254 48 MHz 145 164 172 176 158 176 187 192 32 MHz 100 116 121 124 108 123 130 134 24 MHz 78 92 96 98 85 97 102 105 8 MHz 1.9 3.1 3.6 4.4 2.5 3.7 4.4 5.5 DocID026415 Rev 5 A STM32F303xD STM32F303xE Electrical characteristics Table 26. Typical and maximum current consumption from the VDDA supply (continued) VDDA = 2.4 V Symbol Parameter IDDA Supply current in Run mode, code executing from Flash or RAM Conditions (1) HSE bypass HSI clock fHCLK Typ VDDA = 3.6 V Max @ TA(2) 25 C 85 C 105 C Typ Max @ TA(2) 25 C Unit 85 C 105 C 1 MHz 1.9 3.1 3.6 4.4 2.5 3.7 4.4 5.5 64 MHz 266 290 301 306 295 320 335 341 48 MHz 216 237 247 251 240 262 274 279 32 MHz 170 188 196 199 190 208 217 221 24 MHz 148 164 170 172 166 182 189 192 8 MHz 70 78 81 82 84 92 95 97 A 1. Current consumption from the VDDA supply is independent of whether the peripherals are on or off. Furthermore when the PLL is off, IDDA is independent from the frequency. 2. Data based on characterization results, not tested in production. Table 27. Typical and maximum VDD consumption in Stop and Standby modes Symbol Parameter IDD Typ @VDD (VDD=VDDA) Max 2.0 V 2.4 V 2.7 V 3.0 V 3.3 V 3.6 V TA = TA = TA = 25 C 85 C 105 C Conditions Regulator in run mode, 18.4 Supply all oscillators OFF current in Stop mode Regulator in low-power 6.80 mode, all oscillators OFF Supply current in Standby mode 18.7 18.8 18.9 19.0 19.1 47 435 940 6.94 7.11 7.18 7.26 7.39 33 408 898 0.72 0.87 0.99 1.10 1.23 1.37 - - - LSI OFF and IWDG OFF 0.57 0.68 0.76 0.85 0.94 1.03 6.2 8.6 13.5 LSI ON and IWDG ON Unit A DocID026415 Rev 5 77/173 151 Electrical characteristics STM32F303xD STM32F303xE Table 28. Typical and maximum VDDA consumption in Stop and Standby modes Supply current in Stop mode IDDA Supply current in Standby mode Supply current in Stop mode Supply current in Standby mode Max(1) 2.0 V 2.4 V 2.7 V 3.0 V 3.3 V 3.6 V TA = TA = TA = 25 C 85 C 105 C 1.72 1.85 1.97 2.10 2.25 2.41 10.7 11 12 - - - 3.6 4 6 Conditions VDDA supervisor OFF VDDA supervisor ON Symbol Parameter Typ @VDD (VDD = VDDA) Regulator in run/lowpower mode, all oscillators OFF LSI ON and IWDG ON 2.08 2.26 2.43 2.61 2.82 3.05 LSI OFF and IWDG OFF 1.60 1.73 1.85 1.98 2.13 2.29 Unit A Regulator in run/lowpower mode, all oscillators OFF 1.00 1.02 1.05 1.10 1.16 1.24 - - - LSI ON and IWDG ON 1.36 1.43 1.51 1.61 1.74 1.88 - - - LSI OFF and IWDG OFF - - - 0.88 0.90 0.93 0.98 1.05 1.12 1. Data based on characterization results, not tested in production. Table 29. Typical and maximum current consumption from VBAT supply Symbol Para meter Max @VBAT = 3.6 V(2) Typ @VBAT Conditions (1) LSE & RTC ON; "Xtal mode" lower driving capability; LSEDRV[1: Backup 0] = '00' domain IDD_VBAT supply LSE & RTC current ON; "Xtal mode" higher driving capability; LSEDRV[1: 0] = '11' 1.65V 1.8V 2V 0.48 0.50 0.52 2.4V 2.7V 0.58 3V 0.65 0.72 0.80 0.90 1.1 1.5 2.0 A 0.83 0.86 0.90 0.98 1.03 1.10 1.20 1.30 1. Crystal used: Abracon ABS07-120-32.768 kHz-T with a CL of 6 pF for typical values. 2. Data based on characterization results, not tested in production. 78/173 Unit T = TA = TA = 3.3V 3.6V A 25C 85C 105C DocID026415 Rev 5 1.5 2.2 2.9 STM32F303xD STM32F303xE Electrical characteristics Figure 14. Typical VBAT current consumption (LSE and RTC ON/LSEDRV[1:0] 00') 6 6 6 6 6 6 ) 6"!4 ! 6 6 # # # # 4! # -36 Typical current consumption The MCU is placed under the following conditions: * VDD = VDDA = 3.3 V * All I/O pins available on each package are in analog input configuration * The Flash access time is adjusted to fHCLK frequency (0 wait states from 0 to 24 MHz, 1 wait state from 24 to 48 MHz and 2 wait states from 48 MHz to 72 MHz), and Flash prefetch is ON * When the peripherals are enabled, fAPB1 = fAHB/2, fAPB2 = fAHB * PLL is used for frequencies greater than 8 MHz * AHB prescaler of 2, 4, 8,16 and 64 is used for the frequencies 4 MHz, 2 MHz, 1 MHz, 500 kHz and 125 kHz respectively. DocID026415 Rev 5 79/173 151 Electrical characteristics STM32F303xD STM32F303xE Table 30. Typical current consumption in Run mode, code with data processing running from Flash Typ Symbol IDD Parameter Conditions Supply current in Run mode from VDD supply Running from HSE crystal clock 8 MHz, code executing from Flash IDDA(1) (2) Supply current in Run mode from VDDA supply fHCLK Peripherals enabled Peripherals disabled 72 MHz 60.7 27.3 64 MHz 54.3 24.1 48 MHz 42.1 19.4 32 MHz 28.7 13.9 24 MHz 22.2 11.0 16 MHz 15.4 7.9 8 MHz 8.3 4.51 4 MHz 5.14 3.02 2 MHz 3.37 2.21 1 MHz 2.49 1.80 500 kHz 2.04 1.57 125 kHz 1.71 0.84 72 MHz 239.7 64 MHz 210.5 48 MHz 155.6 32 MHz 105.5 24 MHz 81.9 16 MHz 58.6 8 MHz 1.16 4 MHz 1.16 2 MHz 1.16 1 MHz 1.16 500 kHz 1.16 125 kHz 1.16 Unit mA A 1. VDDA supervisor is OFF. 2. When peripherals are enabled, the power consumption of the analog part of peripherals such as ADC, DAC, Comparators, OpAmp is not included. Refer to the tables of characteristics in the subsequent sections. 80/173 DocID026415 Rev 5 STM32F303xD STM32F303xE Electrical characteristics Table 31. Typical current consumption in Sleep mode, code running from Flash or RAM Typ Symbol IDD Parameter Conditions Supply current in Sleep mode from VDD supply Running from HSE crystal clock 8 MHz, code executing from Flash or RAM IDDA(1) (2) Supply current in Sleep mode from VDDA supply fHCLK Peripherals enabled Peripherals disabled 72 MHz 43.0 7.4 64 MHz 38.3 6.8 48 MHz 29.0 5.29 32 MHz 19.7 3.91 24 MHz 15.2 3.19 16 MHz 10.8 2.46 8 MHz 5.85 1.55 4 MHz 3.80 1.45 2 MHz 2.67 1.32 1 MHz 2.12 1.22 500 kHz 1.83 1.19 125 kHz 1.60 0.83 72 MHz 239.7 64 MHz 210.5 48 MHz 155.6 32 MHz 105.5 24 MHz 81.9 16 MHz 58.6 8 MHz 1.16 4 MHz 1.16 2 MHz 1.16 1 MHz 1.16 500 kHz 1.16 125 kHz 1.16 Unit mA A 1. VDDA supervisor is OFF. 2. When peripherals are enabled, the power consumption of the analog part of peripherals such as ADC, DAC, Comparators, OpAmp is not included. Refer to the tables of characteristics in the subsequent sections. DocID026415 Rev 5 81/173 151 Electrical characteristics STM32F303xD STM32F303xE I/O system current consumption The current consumption of the I/O system has two components: static and dynamic. I/O static current consumption All the I/Os used as inputs with pull-up generate current consumption when the pin is externally held low. The value of this current consumption can be simply computed by using the pull-up/pull-down resistors values given in Table 66: I/O static characteristics. For the output pins, any external pull-down or external load must also be considered to estimate the current consumption. Additional I/O current consumption is due to I/Os configured as inputs if an intermediate voltage level is externally applied. This current consumption is caused by the input Schmitt trigger circuits used to discriminate the input value. Unless this specific configuration is required by the application, this supply current consumption can be avoided by configuring these I/Os in analog mode. This is notably the case of ADC input pins which should be configured as analog inputs. Caution: Any floating input pin can also settle to an intermediate voltage level or switch inadvertently, as a result of external electromagnetic noise. To avoid current consumption related to floating pins, they must either be configured in analog mode, or forced internally to a definite digital value. This can be done either by using pull-up/down resistors or by configuring the pins in output mode. I/O dynamic current consumption In addition to the internal peripheral current consumption (seeTable 33: Peripheral current consumption), the I/Os used by an application also contribute to the current consumption. When an I/O pin switches, it uses the current from the MCU supply voltage to supply the I/O pin circuitry and to charge/discharge the capacitive load (internal or external) connected to the pin: I SW = V DD x f SW x C where: ISW is the current sunk by a switching I/O to charge/discharge the capacitive load VDD is the MCU supply voltage fSW is the I/O switching frequency C is the total capacitance seen by the I/O pin: C = CINT+ CEXT+CS The test pin is configured in push-pull output mode and is toggled by software at a fixed frequency. 82/173 DocID026415 Rev 5 STM32F303xD STM32F303xE Electrical characteristics Table 32. Switching output I/O current consumption Symbol Parameter Conditions(1) VDD = 3.3 V Cext = 0 pF C = CINT + CEXT+ CS VDD = 3.3 V Cext = 10 pF C = CINT + CEXT +CS ISW I/O current consumption VDD = 3.3 V Cext = 22 pF C = CINT + CEXT +CS VDD = 3.3 V Cext = 33 pF C = CINT + CEXT+ CS VDD = 3.3 V Cext = 47 pF C = CINT + CEXT+ CS I/O toggling frequency (fSW) Typ 2 MHz 0.90 4 MHz 0.93 8 MHz 1.16 18 MHz 1.60 36 MHz 2.51 48 MHz 2.97 2 MHz 0.93 4 MHz 1.06 8 MHz 1.47 18 MHz 2.26 36 MHz 3.39 48 MHz 5.99 2 MHz 1.03 4 MHz 1.30 8 MHz 1.79 18 MHz 3.01 36 MHz 5.99 2 MHz 1.10 4 MHz 1.31 8 MHz 2.06 18 MHz 3.47 36 MHz 8.35 2 MHz 1.20 4 MHz 1.54 8 MHz 2.46 18 MHz 4.51 36 MHz 9.98 Unit mA 1. CS = 5 pF (estimated value). DocID026415 Rev 5 83/173 151 Electrical characteristics STM32F303xD STM32F303xE On-chip peripheral current consumption The MCU is placed under the following conditions: * all I/O pins are in analog input configuration * all peripherals are disabled unless otherwise mentioned * the given value is calculated by measuring the current consumption * 84/173 - with all peripherals clocked off - with only one peripheral clocked on ambient operating temperature at 25C and VDD = VDDA = 3.3 V. DocID026415 Rev 5 STM32F303xD STM32F303xE Electrical characteristics Table 33. Peripheral current consumption Peripheral Typical consumption(1) Unit IDD BusMatrix (2) 8.3 DMA1 7.0 DMA2 5.4 FSMC 35.0 CRC 1.5 GPIOH 1.3 GPIOA 5.4 GPIOB 5.3 GPIOC 5.4 GPIOD 5.0 GPIOE 5.4 GPIOF 5.2 GPIOG 5.0 TSC 5.2 ADC1&2 15.4 ADC3&4 APB2-Bridge A/MHz 16.2 (3) 3.1 SYSCFG 4.0 TIM1 26.0 SPI1 6.2 TIM8 26.4 USART1 17.7 SPI4 6.2 TIM15 11.9 TIM16 8.0 TIM17 8.5 TIM20 25.3 DocID026415 Rev 5 85/173 151 Electrical characteristics STM32F303xD STM32F303xE Table 33. Peripheral current consumption (continued) Peripheral Typical consumption(1) Unit IDD APB1-Bridge (3) 6.7 TIM2 39.2 TIM3 30.8 TIM4 31.3 TIM6 4.3 TIM7 4.3 WWDG 1.3 SPI2 33.6 SPI3 33.9 USART2 39.3 USART3 39.3 UART4 29.8 UART5 27.0 I2C1 6.7 I2C2 6.4 USB 14.7 CAN 25.6 PWR 3.7 DAC 22.1 I2C3 6.8 A/MHz 1. The power consumption of the analog part (IDDA) of peripherals such as ADC, DAC, Comparators, OpAmp is not included. Refer to the tables of characteristics in the subsequent sections. 2. BusMatrix is automatically active when at least one master is ON (CPU, DMA1 or DMA2). 3. The APBx bridge is automatically active when at least one peripheral is ON on the same bus. 86/173 DocID026415 Rev 5 STM32F303xD STM32F303xE 6.3.6 Electrical characteristics Wakeup time from low-power mode The wakeup times given in Table 34 are measured starting from the wakeup event trigger up to the first instruction executed by the CPU: * For Stop or Sleep mode: the wakeup event is WFE. * WKUP1 (PA0) pin is used to wake up from Standby, Stop and Sleep modes. All timings are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 19. Table 34. Low-power mode wakeup timings Symbol tWUSTOP Parameter Wakeup from Stop mode Wakeup from tWUSTANDBY(1) Standby mode tWUSLEEP Wakeup from Sleep mode Typ @VDD, VDD = VDDA Conditions Max 2.0 V 2.4 V 2.7 V 3V 3.3 V 3.6 V Regulator in run mode 5.4 5.2 5.2 5.1 5.0 4.9 5.6 Regulator in low power mode 12.0 10.1 9.2 8.6 8.1 7.8 12.9 LSI and IWDG OFF 91.0 77.1 71.7 68.0 65.1 63.1 139 - 6 - Unit s CPU clock cycles 1. Data based on characterization results, not tested in production. Table 35. Wakeup time using USART Symbol Parameter Conditions Typ Max Stop mode with main regulator in low power mode - 13.125 tWUUSART Wakeup time needed to calculate the maximum USART baudrate allowing to wakeup up from stop mode when USART clock source is HSI Stop mode with main regulator in run mode - DocID026415 Rev 5 Unit s 3.125 87/173 151 Electrical characteristics 6.3.7 STM32F303xD STM32F303xE External clock source characteristics High-speed external user clock generated from an external source In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO. The external clock signal has to respect the I/O characteristics in Section 6.3.15. However, the recommended clock input waveform is shown in Figure 15. Table 36. High-speed external user clock characteristics Symbol Parameter Conditions Min Typ Max Unit 1 8 32 MHz fHSE_ext User external clock source frequency(1) VHSEH OSC_IN input pin high level voltage 0.7VDD - VDD VHSEL OSC_IN input pin low level voltage VSS - 0.3VDD 15 - - - - 20 tw(HSEH) tw(HSEL) tr(HSE) tf(HSE) OSC_IN high or low - time(1) V ns OSC_IN rise or fall time(1) 1. Guaranteed by design, not tested in production. Figure 15. High-speed external clock source AC timing diagram WZ +6(+ 9+6(+ 9+6(/ WU +6( WI +6( WZ +6(/ W 7+6( 069 Low-speed external user clock generated from an external source In bypass mode the LSE oscillator is switched off and the input pin is a standard GPIO. The external clock signal has to respect the I/O characteristics in Section 6.3.15. However, the recommended clock input waveform is shown in Figure 16. 88/173 DocID026415 Rev 5 STM32F303xD STM32F303xE Electrical characteristics Table 37. Low-speed external user clock characteristics Symbol Parameter Conditions Min Typ Max Unit - 32.768 1000 kHz 0.7VDD - VDD VSS - 0.3VDD fLSE_ext User External clock source frequency(1) VLSEH OSC32_IN input pin high level voltage VLSEL OSC32_IN input pin low level voltage tw(LSEH) tw(LSEL) OSC32_IN high or low time(1) 450 - - tr(LSE) tf(LSE) OSC32_IN rise or fall time(1) - - 50 V - ns 1. Guaranteed by design, not tested in production. Figure 16. Low-speed external clock source AC timing diagram WZ /6(+ 9/6(+ 9/6(/ WU /6( WI /6( WZ /6(/ W 7/6( 069 DocID026415 Rev 5 89/173 151 Electrical characteristics STM32F303xD STM32F303xE High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 4 to 32 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in Table 38. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 38. HSE oscillator characteristics Symbol fOSC_IN RF Conditions(1) Min(2) Typ Max(2) Unit Oscillator frequency - 4 8 32 MHz Feedback resistor - - 200 - k - - 8.5 VDD= 3.3 V, Rm= 30, CL=10 pF@8 MHz - 0.4 - VDD= 3.3 V, Rm= 45, CL=10 pF@8 MHz - 0.5 - VDD= 3.3 V, Rm= 30, CL=5 pF@32 MHz - 0.8 - VDD= 3.3 V, Rm= 30, CL=10 pF@32 MHz - 1 - VDD= 3.3 V, Rm= 30, CL=20 pF@32 MHz - 1.5 - Startup 10 - - mA/V VDD is stabilized - 2 - ms Parameter During startup IDD gm tSU(HSE)(4) HSE current consumption Oscillator transconductance Startup time (3) mA 1. Resonator characteristics given by the crystal/ceramic resonator manufacturer. 2. Guaranteed by design, not tested in production. 3. This consumption level occurs during the first 2/3 of the tSU(HSE) startup time. 4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer. For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the 5 pF to 25 pF range (Typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see Figure 17). CL1 and CL2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing CL1 and CL2. Note: 90/173 For information on selecting the crystal, refer to the application note AN2867 "Oscillator design guide for ST microcontrollers" available from the ST website www.st.com. DocID026415 Rev 5 STM32F303xD STM32F303xE Electrical characteristics Figure 17. Typical application with an 8 MHz crystal 5HVRQDWRUZLWKLQWHJUDWHG FDSDFLWRUV &/ 26&B,1 0+] UHVRQDWRU &/ 5(;7 I+6( 5) %LDV FRQWUROOHG JDLQ 26&B287 069 1. REXT value depends on the crystal characteristics. Low-speed external clock generated from a crystal/ceramic resonator The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on design simulation results obtained with typical external components specified in Table 39. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 39. LSE oscillator characteristics (fLSE = 32.768 kHz) Symbol IDD gm tSU(LSE)(3) Parameter LSE current consumption Oscillator transconductance Startup time Conditions(1) LSEDRV[1:0]=00 lower driving capability LSEDRV[1:0]=01 medium low driving capability LSEDRV[1:0]=10 medium high driving capability LSEDRV[1:0]=11 higher driving capability LSEDRV[1:0]=00 lower driving capability LSEDRV[1:0]=01 medium low driving capability LSEDRV[1:0]=10 medium high driving capability LSEDRV[1:0]=11 higher driving capability VDD is stabilized Min(2) Typ Max(2) - 0.5 0.9 - - 1 - - 1.3 - - 1.6 5 - - 8 - - 15 - - 25 - - - 2 - Unit A A/V s 1. Refer to the note and caution paragraphs below the table, and to the application note AN2867 "Oscillator design guide for ST microcontrollers". 2. Guaranteed by design, not tested in production. 3. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal and it can vary significantly with the crystal manufacturer. DocID026415 Rev 5 91/173 151 Electrical characteristics Note: STM32F303xD STM32F303xE For information on selecting the crystal, refer to the application note AN2867 "Oscillator design guide for ST microcontrollers" available from the ST website www.st.com. Figure 18. Typical application with a 32.768 kHz crystal 5HVRQDWRUZLWKLQWHJUDWHG FDSDFLWRUV &/ 26&B,1 I/6( 'ULYH SURJUDPPDEOH DPSOLILHU N+] UHVRQDWRU 26&B287 &/ 069 Note: An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden to add one. 6.3.8 Internal clock source characteristics The parameters given in Table 40 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 19. High-speed internal (HSI) RC oscillator Table 40. HSI oscillator characteristics(1) Symbol fHSI TRIM DuCy(HSI) ACCHSI Parameter Conditions Min Typ - - Frequency HSI user trimming step Duty cycle Accuracy of the HSI oscillator - - - (2) 8 - MHz - (2) 1 (2) % - 55 TA = -40 to 105C - 3.8(3) TA = -10 to 85C -1.9(3) - 2.3(3) TA = 0 to 85C -1.9(3) - 2(3) TA = 0 to 70C -1.3(3) - 2(3) TA = 0 to 55C -1(3) - 2(3) -1 - 1 - 2(2) s 80 100(2) A tSU(HSI) HSI oscillator startup time - 1(2) IDDA(HSI) HSI oscillator power consumption - - 1. VDDA = 3.3 V, TA = -40 to 105 C unless otherwise specified. 2. Guaranteed by design, not tested in production. 3. Data based on characterization results, not tested in production. 4. Factory calibrated, parts not soldered. 92/173 Unit -2.8(3) TA = 25C(4) 45 Max DocID026415 Rev 5 % % STM32F303xD STM32F303xE Electrical characteristics Figure 19. HSI oscillator accuracy characterization results for soldered parts ."9 .*/ 5<$> " 069 Low-speed internal (LSI) RC oscillator Table 41. LSI oscillator characteristics(1) Symbol fLSI Parameter Min Typ Max Unit 30 40 50 kHz Frequency tsu(LSI)(2) LSI oscillator startup time - - 85 s IDD(LSI)(2) LSI oscillator power consumption - 0.75 1.2 A 1. VDDA = 3.3 V, TA = -40 to 105 C unless otherwise specified. 2. Guaranteed by design, not tested in production. 6.3.9 PLL characteristics The parameters given in Table 42 are derived from tests performed under ambient temperature and supply voltage conditions summarized in Table 19. Table 42. PLL characteristics Symbol fPLL_IN fPLL_OUT tLOCK Jitter Parameter Value Unit Min Typ Max 1(2) - 24(2) MHz PLL input clock duty cycle (2) 40 - 60(2) % PLL multiplier output clock 16(2) - 72 MHz - - 200(2) s - (2) ps PLL input clock(1) PLL lock time Cycle-to-cycle jitter - 300 1. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with the range defined by fPLL_OUT. 2. Guaranteed by design, not tested in production. DocID026415 Rev 5 93/173 151 Electrical characteristics 6.3.10 STM32F303xD STM32F303xE Memory characteristics Flash memory The characteristics are given at TA = -40 to 105 C unless otherwise specified. Table 43. Flash memory characteristics Min Typ Max(1) Unit 16-bit programming time TA = -40 to +105 C 40 53.5 60 s Page (2 KB) erase time TA = -40 to +105 C 20 - 40 ms tME Mass erase time TA = -40 to +105 C 20 - 40 ms IDD Supply current Write mode - - 10 mA Erase mode - - 12 mA Symbol tprog tERASE Parameter Conditions 1. Guaranteed by design, not tested in production. Table 44. Flash memory endurance and data retention Value Symbol NEND tRET Parameter Endurance Data retention Conditions TA = -40 to +85 C (6 suffix versions) TA = -40 to +105 C (7 suffix versions) 10 1 kcycle(2) at TA = 85 C 30 (2) 1 kcycle 10 at TA = 105 C kcycle(2) at TA = 55 C Unit Min(1) kcycles 10 Years 20 1. Data based on characterization results, not tested in production. 2. Cycling performed over the whole temperature range. 6.3.11 FSMC characteristics Unless otherwise specified, the parameters given in Table 45 to Table 60 for the FSMC interface are derived from tests performed under the ambient temperature, fHCLK frequency and VDD supply voltage conditions summarized in Table 19 with the following configuration: * Output speed is set to OSPEEDRy[1:0] = 11 * Capacitive load C = 30 pF * Measurement points are done at CMOS levels: 0.5VDD Refer to Section 6.3.15: I/O port characteristics: for more details on the input/output characteristics. 94/173 DocID026415 Rev 5 STM32F303xD STM32F303xE Electrical characteristics Asynchronous waveforms and timings Figure 20 to Figure 23 represent asynchronous waveforms and Table 45 to Table 52 provide the corresponding timings. The results shown in these tables are obtained with the following FSMC configuration: * AddressSetupTime = 0x1 * AddressHoldTime = 0x1 * DataSetupTime = 0x1 (except for asynchronous NWAIT mode, DataSetupTime = 0x5) * BusTurnAroundDuration = 0x0 * NOR NWAIT pulse width= 1THCLK In all the timing tables, the THCLK is the HCLK clock period. Figure 20. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings TW.% &-#?.% TV./%?.% T W./% T H.%?./% &-#?./% &-#?.7% TV!?.% &-#?!;= T H!?./% !DDRESS TV",?.% T H",?./% &-#?.",;= T H$ATA?.% T SU$ATA?./% TH$ATA?./% T SU$ATA?.% $ATA &-#?$;= T V.!$6?.% TW.!$6 &-#?.!$6 &-#?.7!)4 TH.%?.7!)4 TSU.7!)4?.% -36 DocID026415 Rev 5 95/173 151 Electrical characteristics STM32F303xD STM32F303xE Table 45. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1) Symbol Min Max 2THCLK- 1 2THCLK+1 0 1 2THCLK 2THCLK+ 1.5 0.5 - FMC_NEx low to FMC_A valid - 3 th(A_NOE) Address hold time after FMC_NOE high 0 - tv(BL_NE) FMC_NEx low to FMC_BL valid - 2 (NA) th(BL_NOE) FMC_BL hold time after FMC_NOE high 0 - tsu(Data_NE) Data to FMC_NEx high setup time THCLK + 6 - tsu(Data_NOE) Data to FMC_NOEx high setup time THCLK +7 - th(Data_NOE) Data hold time after FMC_NOE high 0 - th(Data_NE) Data hold time after FMC_NEx high 0 - tv(NADV_NE) FMC_NEx low to FMC_NADV low - 2 FMC_NADV low time - THCLK +1.5 tw(NE) tv(NOE_NE) tw(NOE) th(NE_NOE) tv(A_NE) tw(NADV) Parameter FMC_NE low time FMC_NEx low to FMC_NOE low FMC_NOE low time FMC_NOE high to FMC_NE high hold time Unit ns 1. Based on characterization, not tested in production Table 46. Asynchronous non-multiplexed SRAM/PSRAM/NOR read-NWAIT timings(1) Symbol Min Max FMC_NE low time 7THCLK +0.5 7THCLK+ 1 FMC_NWE low time 6THCLK -1.5 6THCLK +2 tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 4THCLK +5 - th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 4THCLK-3 - tw(NE) tw(NOE) Parameter 1. Based on characterization, not tested in production. 96/173 DocID026415 Rev 5 Unit ns STM32F303xD STM32F303xE Electrical characteristics Figure 21. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings TW.% &-#?.%X &-#?./% TV.7%?.% TW.7% T H.%?.7% &-#?.7% TV!?.% &-#?!;= TH!?.7% !DDRESS TV",?.% &-#?.",;= TH",?.7% .", TV$ATA?.% TH$ATA?.7% $ATA &-#?$;= T V.!$6?.% &-#?.!$6 TW.!$6 &-#?.7!)4 TH.%?.7!)4 TSU.7!)4?.% -36 1. Mode 2/B, C and D only. In Mode 1, FMC_NADV is not used. Table 47. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1) Symbol tw(NE) tv(NWE_NE) tw(NWE) th(NE_NWE) tv(A_NE) Parameter Min Max FMC_NE low time 3THCLK-1 3THCLK+2 FMC_NEx low to FMC_NWE low THCLK+0.5 THCLK+1 THCLK-2 THCLK+1 THCLK-0.5 - - 0 THCLK-1.5 - FMC_NWE low time FMC_NWE high to FMC_NE high hold time FMC_NEx low to FMC_A valid th(A_NWE) Address hold time after FMC_NWE high tv(BL_NE) FMC_NEx low to FMC_BL valid - 1 THCLK-0.5 - Data to FMC_NEx low to Data valid - THCLK+ 3 th(Data_NWE) Data hold time after FMC_NWE high THCLK+0.5 - tv(NADV_NE) FMC_NEx low to FMC_NADV low - 2.5 FMC_NADV low time - THCLK+2 th(BL_NWE) FMC_BL hold time after FMC_NWE high tv(Data_NE) tw(NADV) Unit ns 1. Based on characterization, not tested in production. DocID026415 Rev 5 97/173 151 Electrical characteristics STM32F303xD STM32F303xE Table 48. Asynchronous non-multiplexed SRAM/PSRAM/NOR write-NWAIT timings(1) Symbol tw(NE) tw(NWE) Parameter Min Max FMC_NE low time 8THCLK+1 8THCLK+2 FMC_NWE low time 6THCLK-1 6THCLK+2 tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 5THCLK-0.5 - th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 4THCLK+2 - Unit ns 1. Based on characterization, not tested in production. Table 49. Asynchronous multiplexed PSRAM/NOR read-NWAIT timings(1) Symbol Min Max FMC_NE low time 8THCLK+2 8THCLK+2 FMC_NWE low time 6THCLK-1 6THCLK+1.5 tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 4THCLK+6 - th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 4THCLK-4 - tw(NE) tw(NOE) Parameter 1. Based on characterization, not tested in production. 98/173 DocID026415 Rev 5 Unit ns STM32F303xD STM32F303xE Electrical characteristics Figure 22. Asynchronous multiplexed PSRAM/NOR read timings TW.% &-#? .% TV./%?.% T H.%?./% &-#?./% T W./% &-#?.7% TH!?./% TV!?.% &-#? !;= !DDRESS TV",?.% TH",?./% &-#? .",;= .", TH$ATA?.% TSU$ATA?.% T V!?.% TSU$ATA?./% $ATA !DDRESS &-#? !$;= TH$ATA?./% TH!$?.!$6 T V.!$6?.% TW.!$6 &-#?.!$6 &-#?.7!)4 TH.%?.7!)4 TSU.7!)4?.% -36 Table 50. Asynchronous multiplexed PSRAM/NOR read timings(1) Symbol tw(NE) tv(NOE_NE) tw(NOE) th(NE_NOE) tv(A_NE) tv(NADV_NE) tw(NADV) Parameter Min Max 3THCLK-0.5 3THCLK+1 FMC_NEx low to FMC_NOE low 2THCLK 2THCLK+1 FMC_NOE low time THCLK-2 THCLK+2 FMC_NOE high to FMC_NE high hold time 0 - FMC_NEx low to FMC_A valid - 1.5 FMC_NEx low to FMC_NADV low 0 2 THCLK-2 THCLK+2 FMC_NE low time FMC_NADV low time th(AD_NADV) FMC_AD(address) valid hold time after FMC_NADV high 0 - th(A_NOE) Address hold time after FMC_NOE high THCLK-0.5 - th(BL_NOE) FMC_BL time after FMC_NOE high 0 - DocID026415 Rev 5 Unit ns 99/173 151 Electrical characteristics STM32F303xD STM32F303xE Table 50. Asynchronous multiplexed PSRAM/NOR read timings(1) (continued) Symbol tv(BL_NE) Parameter Min Max - 2 FMC_NEx low to FMC_BL valid tsu(Data_NE) Data to FMC_NEx high setup time THCLK - tsu(Data_NOE) Data to FMC_NOE high setup time THCLK+1 - th(Data_NE) Data hold time after FMC_NEx high 0 - th(Data_NOE) Data hold time after FMC_NOE high 0 - Unit ns 1. Based on characterization, not tested in production. Figure 23. Asynchronous multiplexed PSRAM/NOR write timings TW.% &-#? .%X &-#?./% TV.7%?.% TW.7% T H.%?.7% &-#?.7% TH!?.7% TV!?.% &-#? !;= !DDRESS TV",?.% &-#? .",;= .", T V!?.% &-#? !$;= TH",?.7% T V$ATA?.!$6 !DDRESS TH$ATA?.7% $ATA TH!$?.!$6 T V.!$6?.% TW.!$6 &-#?.!$6 &-#?.7!)4 TH.%?.7!)4 TSU.7!)4?.% -36 100/173 DocID026415 Rev 5 STM32F303xD STM32F303xE Electrical characteristics Table 51. Asynchronous multiplexed PSRAM/NOR write timings(1) Symbol Min Max 4THCLK-1 4THCLK+1 THCLK THCLK+0.5 FMC_NWE low time 2THCLK-0.5 2THCLK+1 FMC_NWE high to FMC_NE high hold time THCLK-0.5 - FMC_NEx low to FMC_A valid - 5 FMC_NEx low to FMC_NADV low 1 2.5 FMC_NADV low time THCLK-2 THCLK+2 FMC_AD(adress) valid hold time after FMC_NADV high) THCLK-2 - th(A_NWE) Address hold time after FMC_NWE high THCLK-1 - th(BL_NWE) FMC_BL hold time after FMC_NWE high THCLK-0.5 - tw(NE) tv(NWE_NE) tw(NWE) th(NE_NWE) tv(A_NE) tv(NADV_NE) tw(NADV) th(AD_NADV) Parameter FMC_NE low time FMC_NEx low to FMC_NWE low tv(BL_NE) FMC_NEx low to FMC_BL valid - 1 tv(Data_NADV) FMC_NADV high to Data valid - THCLK +3.5 th(Data_NWE) Data hold time after FMC_NWE high THCLK +0.5 - Unit ns 1. Based on characterization, not tested in production. Table 52. Asynchronous multiplexed PSRAM/NOR write-NWAIT timings(1) Symbol tw(NE) tw(NWE) Parameter Min Max FMC_NE low time 9THCLK 9THCLK+0.5 FMC_NWE low time 6THCLK 6THCLK+2 tsu(NWAIT_NE) FMC_NWAIT valid before FMC_NEx high 5THCLK+6 - th(NE_NWAIT) FMC_NEx hold time after FMC_NWAIT invalid 5THCLK-5 - Unit ns 1. Based on characterization, not tested in production. Synchronous waveforms and timings Figure 24 and Figure 27 present the synchronous waveforms and Table 53 to Table 56 provide the corresponding timings. The results shown in these tables are obtained with the following FSMC configuration: * BurstAccessMode = FMC_BurstAccessMode_Enable; * MemoryType = FMC_MemoryType_CRAM; * WriteBurst = FMC_WriteBurst_Enable; * CLKDivision = 1; * DataLatency = 2 for NOR Flash; DataLatency = 0 for PSRAM In all timing tables, the THCLK is the HCLK clock period (with maximum FMC_CLK = 36 MHz). DocID026415 Rev 5 101/173 151 Electrical characteristics STM32F303xD STM32F303xE Figure 24. Synchronous multiplexed NOR/PSRAM read timings "53452. TW#,+ TW#,+ &-#?#,+ $ATA LATENCY TD#,+, .%X, &-#?.%X T D#,+, .!$6, TD#,+( .%X( TD#,+, .!$6( &-#?.!$6 TD#,+, !6 TD#,+( !)6 &-#?!;= TD#,+, ./%, TD#,+( ./%( &-#?./% T D#,+, !$6 &-#?!$;= TD#,+, !$)6 TSU!$6 #,+( !$;= TH#,+( !$6 TSU!$6 #,+( $ TSU.7!)46 #,+( &-#?.7!)4 7!)4#&' B 7!)40/, B &-#?.7!)4 7!)4#&' B 7!)40/, B $ TH#,+( .7!)46 TSU.7!)46 #,+( TSU.7!)46 #,+( TH#,+( !$6 TH#,+( .7!)46 TH#,+( .7!)46 -36 Table 53. Synchronous multiplexed NOR/PSRAM read timings(1) Symbol tw(CLK) FMC_CLK period td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) td(CLKH_NExH) FMC_CLK high to FMC_NEx high (x= 0...2) td(CLKL-NADVL) td(CLKL-NADVH) Min Max 2THCLK - THCLK+1 - FMC_CLK low to FMC_NADV low - 7 FMC_CLK low to FMC_NADV high 2.5 - FMC_CLK low to FMC_Ax valid (x=16...25) - 3 td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16...25) 0 - td(CLKL-NOEL) FMC_CLK low to FMC_NOE low - 6 td(CLKH-NOEH) FMC_CLK high to FMC_NOE high THCLK+1 - - 2 FMC_CLK low to FMC_AD[15:0] valid DocID026415 Rev 5 Unit 5 td(CLKL-AV) td(CLKL-ADV) 102/173 Parameter ns STM32F303xD STM32F303xE Electrical characteristics Table 53. Synchronous multiplexed NOR/PSRAM read timings(1) (continued) Symbol Parameter Min Max td(CLKL-ADIV) FMC_CLK low to FMC_AD[15:0] invalid 0 - tsu(ADV-CLKH) FMC_A/D[15:0] valid data before FMC_CLK high 4 - th(CLKH-ADV) FMC_A/D[15:0] valid data after FMC_CLK high 6 - tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 3 - th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 4 - Unit ns 1. Based on characterization, not tested in production. Figure 25. Synchronous multiplexed PSRAM write timings "53452. TW#,+ TW#,+ &-#?#,+ $ATA LATENCY TD#,+, .%X, TD#,+( .%X( &-#?.%X TD#,+, .!$6, TD#,+, .!$6( &-#?.!$6 TD#,+( !)6 TD#,+, !6 &-#?!;= TD#,+( .7%( TD#,+, .7%, &-#?.7% TD#,+, !$)6 TD#,+, !$6 &-#?!$;= TD#,+, $ATA TD#,+, $ATA !$;= $ $ &-#?.7!)4 7!)4#&' B 7!)40/, B TSU.7!)46 #,+( TH#,+( .7!)46 TD#,+( .",( &-#?.", -36 DocID026415 Rev 5 103/173 151 Electrical characteristics STM32F303xD STM32F303xE Table 54. Synchronous multiplexed PSRAM write timings(1) (2) Symbol Parameter Min Max tw(CLK) FMC_CLK period, VDD range= 2.7 to 3.6 V 2THCLK-1 - td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) - 5.5 td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0...2) THCLK+1 - td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 7 td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 2 - td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16...25) - 0 td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16...25) 0 - td(CLKL-NWEL) FMC_CLK low to FMC_NWE low - 5.5 td(CLKH-NWEH) FMC_CLK high to FMC_NWE high THCLK+1 - td(CLKL-ADV) FMC_CLK low to FMC_AD[15:0] valid - 7.5 td(CLKL-ADIV) FMC_CLK low to FMC_AD[15:0] invalid 0 - td(CLKL-DATA) FMC_A/D[15:0] valid data after FMC_CLK low - 8 td(CLKL-NBLL) FMC_CLK low to FMC_NBL low - 6 td(CLKH-NBLH) FMC_CLK high to FMC_NBL high THCLK+1 - tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 3 - th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 5 - 1. Based on characterization, not tested in production. 2. CL = 30 pF. 104/173 DocID026415 Rev 5 Unit ns STM32F303xD STM32F303xE Electrical characteristics Figure 26. Synchronous non-multiplexed NOR/PSRAM read timings TW#,+ TW#,+ &-#?#,+ TD#,+, .%X, TD#,+( .%X( $ATA LATENCY &-#?.%X TD#,+, .!$6, TD#,+, .!$6( &-#?.!$6 TD#,+( !)6 TD#,+, !6 &-#?!;= TD#,+, ./%, TD#,+( ./%( &-#?./% TSU$6 #,+( TH#,+( $6 TSU$6 #,+( &-#?$;= $ TSU.7!)46 #,+( &-#?.7!)4 7!)4#&' B 7!)40/, B $ TH#,+( .7!)46 TSU.7!)46 #,+( &-#?.7!)4 7!)4#&' B 7!)40/, B TSU.7!)46 #,+( TH#,+( $6 T H#,+( .7!)46 TH#,+( .7!)46 -36 Table 55. Synchronous non-multiplexed NOR/PSRAM read timings(1) Symbol tw(CLK) Parameter FMC_CLK period Min Max 2THCLK-1 - - 5 td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0...2) THCLK+1 - td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 7 td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 2.5 - - 7 THCLK - - 6 THCLK+1 - 3.5 - td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16...25) td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16...25) td(CLKL-NOEL) FMC_CLK low to FMC_NOE low td(CLKH-NOEH) FMC_CLK high to FMC_NOE high tsu(DV-CLKH) FMC_D[15:0] valid data before FMC_CLK high DocID026415 Rev 5 Unit ns 105/173 151 Electrical characteristics STM32F303xD STM32F303xE Table 55. Synchronous non-multiplexed NOR/PSRAM read timings(1) (continued) Symbol Parameter Min Max FMC_D[15:0] valid data after FMC_CLK high 5 - tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 2 - th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 4 - th(CLKH-DV) Unit ns 1. Based on characterization, not tested in production. Figure 27. Synchronous non-multiplexed PSRAM write timings TW#,+ TW#,+ &-#?#,+ TD#,+, .%X, TD#,+( .%X( $ATA LATENCY &-#?.%X TD#,+, .!$6, TD#,+, .!$6( &-#?.!$6 TD#,+( !)6 TD#,+, !6 &-#?!;= TD#,+, .7%, TD#,+( .7%( &-#?.7% TD#,+, $ATA &-#?$;= TD#,+, $ATA $ $ &-#?.7!)4 7!)4#&' B 7!)40/, B TSU.7!)46 #,+( TD#,+( .",( TH#,+( .7!)46 &-#?.", -36 106/173 DocID026415 Rev 5 STM32F303xD STM32F303xE Electrical characteristics Table 56. Synchronous non-multiplexed PSRAM write timings(1) Symbol tw(CLK) Parameter FMC_CLK period Min Max 2THCLK-1 - - 6 td(CLKL-NExL) FMC_CLK low to FMC_NEx low (x=0..2) td(CLKH-NExH) FMC_CLK high to FMC_NEx high (x= 0...2) THCLK+1.5 - td(CLKL-NADVL) FMC_CLK low to FMC_NADV low - 7.5 td(CLKL-NADVH) FMC_CLK low to FMC_NADV high 0 - td(CLKL-AV) FMC_CLK low to FMC_Ax valid (x=16...25) - 6.5 td(CLKH-AIV) FMC_CLK high to FMC_Ax invalid (x=16...25) 0 - td(CLKL-NWEL) FMC_CLK low to FMC_NWE low - 0 td(CLKH-NWEH) FMC_CLK high to FMC_NWE high THCLK+2 - td(CLKL-Data) FMC_D[15:0] valid data after FMC_CLK low - 7.5 td(CLKL-NBLL) FMC_CLK low to FMC_NBL low - 7 td(CLKH-NBLH) FMC_CLK high to FMC_NBL high THCLK+0.5 - tsu(NWAIT-CLKH) FMC_NWAIT valid before FMC_CLK high 2 - th(CLKH-NWAIT) FMC_NWAIT valid after FMC_CLK high 4 - Unit ns 1. Based on characterization, not tested in production. PC Card/CompactFlash controller waveforms and timings Figure 28 to Figure 33 present the PC Card/Compact Flash controller waveforms, and Table 57 to Table 58 provide the corresponding timings. The results shown in this table are obtained with the following FSMC configuration: * COM.FMC_SetupTime = 0x04; * COM.FMC_WaitSetupTime = 0x07; * COM.FMC_HoldSetupTime = 0x04; * COM.FMC_HiZSetupTime = 0x05; * ATT.FMC_SetupTime = 0x04; * ATT.FMC_WaitSetupTime = 0x07; * ATT.FMC_HoldSetupTime = 0x04; * ATT.FMC_HiZSetupTime = 0x05; * IO.FMC_SetupTime = 0x04; * IO.FMC_WaitSetupTime = 0x07; * IO.FMC_HoldSetupTime = 0x04; * IO.FMC_HiZSetupTime = 0x05; * TCLRSetupTime = 0; * TARSetupTime = 0. In all timing tables, the THCLK is the HCLK clock period. DocID026415 Rev 5 107/173 151 Electrical characteristics STM32F303xD STM32F303xE Table 57. Switching characteristics for PC Card/CF read and write cycles in attribute/common space(1) Symbol Parameter Max - 0 tv(NCEx-A) FMC_Ncex low to FMC_Ay valid th(NCEx_AI) FMC_NCEx high to FMC_Ax invalid 2.5 - td(NREG-NCEx) FMC_NCEx low to FMC_NREG valid - 2 th(NCEx-NREG) FMC_NCEx high to FMC_NREG invalid 0 - td(NCEx-NWE) FMC_NCEx low to FMC_NWE low - 5THCLK+2 8THCLK 8THCLK+0.5 tw(NWE) FMC_NWE low width td(NWE_NCEx) FMC_NWE high to FMC_NCEx high 5THCLK-1 - tv (NWE-D) FMC_NWE low to FMC_D[15:0] valid - 5 th (NWE-D) FMC_NWE high to FMC_D[15:0] invalid 4THCLK-1 - td (D-NWE) FMC_D[15:0] valid before FMC_NWE high 13THCLK-3 - - 5THCLK+2 FMC_NOE low width 8THCLK-1 8THCLK+2 FMC_NOE high to FMC_NCEx high 5THCLK-1 - FMC_D[15:0] valid data before FMC_NOE high THCLK+2 - 0 - td(NCEx-NOE) tw(NOE) td(NOE_NCEx) tsu (D-NOE) th(NOE-D) FMC_NCEx low to FMC_NOE low FMC_N0E high to FMC_D[15:0] invalid 1. Based on characterization, not tested in production. 108/173 Min DocID026415 Rev 5 Unit ns STM32F303xD STM32F303xE Electrical characteristics Figure 28. PC Card/CompactFlash controller waveforms for common memory read access &-#?.#%? &-#?.#%? TH.#%X !) TV.#%X ! &-#?!;= TH.#%X .2%' TH.#%X .)/2$ TH.#%X .)/72 TD.2%' .#%X TD.)/2$ .#%X &-#?.2%' &-#?.)/72 &-#?.)/2$ &-#?.7% TD.#%? ./% &-#?./% TW./% TSU$ ./% TH./% $ &-#?$;= -36 1. FMC_NCE4_2 remains high (inactive during 8-bit access. Figure 29. PC Card/CompactFlash controller waveforms for common memory write access &-#?.#%? &-#?.#%? (IGH TV.#%? ! TH.#%? !) &-#?!;= TH.#%? .2%' TH.#%? .)/2$ TH.#%? .)/72 TD.2%' .#%? TD.)/2$ .#%? &-#?.2%' &-#?.)/72 &-#?.)/2$ TD.#%? .7% TW.7% TD.7% .#%? &-#?.7% &-#?./% -%-X(): TD$ .7% TV.7% $ TH.7% $ &-#?$;= -36 DocID026415 Rev 5 109/173 151 Electrical characteristics STM32F303xD STM32F303xE Figure 30. PC Card/CompactFlash controller waveforms for attribute memory read access &-#?.#%? TV.#%? ! &-#?.#%? TH.#%? !) (IGH &-#?!;= &-#?.)/72 &-#?.)/2$ TD.2%' .#%? TH.#%? .2%' &-#?.2%' &-#?.7% TD.#%? ./% TW./% TD./% .#%? &-#?./% TSU$ ./% TH./% $ &-#?$;= -36 1. Only data bits 0...7 are read (bits 8...15 are disregarded). 110/173 DocID026415 Rev 5 STM32F303xD STM32F303xE Electrical characteristics Figure 31. PC Card/CompactFlash controller waveforms for attribute memory write access &-#?.#%? &-#?.#%? (IGH TV.#%? ! TH.#%? !) &-#?!;= &-#?.)/72 &-#?.)/2$ TD.2%' .#%? TH.#%? .2%' &-#?.2%' TD.#%? .7% TW.7% &-#?.7% TD.7% .#%? &-#?./% TV.7% $ &-#?$;= -36 1. Only data bits 0...7 are driven (bits 8...15 remains Hi-Z). Table 58. Switching characteristics for PC Card/CF read and write cycles in I/O space(1) Symbol tw(NIOWR) Parameter FMC_NIOWR low width tv(NIOWR-D) FMC_NIOWR low to FMC_D[15:0] valid th(NIOWR-D) FMC_NIOWR high to FMC_D[15:0] invalid Min Max 8THCLK-0.5 - - 5.5 4THCLK-0.5 - td(NCE4_1-NIOWR) FMC_NCE4_1 low to FMC_NIOWR valid - 5THCLK+1 th(NCEx-NIOWR) FMC_NCEx high to FMC_NIOWR invalid 4THCLK+0.5 - td(NIORD-NCEx) FMC_NCEx low to FMC_NIORD valid - 5THCLK th(NCEx-NIORD) FMC_NCEx high to FMC_NIORD) valid 6THCLK+2 - FMC_NIORD low width 8THCLK-1 8THCLK+1 tsu(D-NIORD) FMC_D[15:0] valid before FMC_NIORD high THCLK+2 - td(NIORD-D) FMC_D[15:0] valid after FMC_NIORD high 0 - tw(NIORD) Unit ns 1. Based on characterization, not tested in production. DocID026415 Rev 5 111/173 151 Electrical characteristics STM32F303xD STM32F303xE Figure 32. PC Card/CompactFlash controller waveforms for I/O space read access &-#?.#%? &-#?.#%? TH.#%? !) TV.#%X ! &-#?!;= &-#?.2%' &-#?.7% &-#?./% &-#?.)/72 TW.)/2$ TD.)/2$ .#%? &-#?.)/2$ TSU$ .)/2$ TD.)/2$ $ &-#?$;= -36 Figure 33. PC Card/CompactFlash controller waveforms for I/O space write access &-#?.#%? &-#?.#%? TV.#%X ! TH.#%? !) &-#?!;= &-#?.2%' &-#?.7% &-#?./% &-#?.)/2$ T D.#%? .)/72 TW.)/72 &-#?.)/72 !44X(): TV.)/72 $ TH.)/72 $ &-#?$;= -36 112/173 DocID026415 Rev 5 STM32F303xD STM32F303xE Electrical characteristics NAND controller waveforms and timings Figure 34 and Figure 35 present the NAND controller synchronous waveforms, and Table 59 and Table 60 provide the corresponding timings. The results shown in this table are obtained with the following FSMC configuration: * COM.FMC_SetupTime = 0x01; * COM.FMC_WaitSetupTime = 0x03; * COM.FMC_HoldSetupTime = 0x02; * COM.FMC_HiZSetupTime = 0x03; * ATT.FMC_SetupTime = 0x01; * ATT.FMC_WaitSetupTime = 0x03; * ATT.FMC_HoldSetupTime = 0x02; * ATT.FMC_HiZSetupTime = 0x03; * Bank = FMC_Bank_NAND; * MemoryDataWidth = FMC_MemoryDataWidth_16b; * ECC = FMC_ECC_Enable; * ECCPageSize = FMC_ECCPageSize_512Bytes; * TCLRSetupTime = 0; * TARSetupTime = 0. In all timing tables, the THCLK is the HCLK clock period. Figure 34. NAND controller read timings &-#?.#%X !,% &-#?! #,% &-#?! &-#?.7% TD!,% ./% TH./% !,% &-#?./% .2% TSU$ ./% TH./% $ &-#?$;= -36 DocID026415 Rev 5 113/173 151 Electrical characteristics STM32F303xD STM32F303xE Table 59. Switching characteristics for NAND Flash read cycles(1) (2) Symbol Min Max FMC_NOE low width 6THCLK 6THCLK + 2 tsu(D-NOE) FMC_D[15-0] valid data before FMC_NOE high THCLK+5 - th(NOE-D) FMC_D[15-0] valid data after FMC_NOE high 0 - td(ALE-NOE) FMC_ALE valid before FMC_NOE low - 6THCLK -0.5 th(NOE-ALE) FMC_NWE high to FMC_ALE invalid 6THCLK-1 - tw(NOE) Parameter Unit ns 1. Based on characterization, not tested in production. 2. CL = 30 pF Figure 35. NAND controller write timings &-#?.#%X !,% &-#?! #,% &-#?! TH.7% !,% TD!,% .7% &-#?.7% &-#?./% .2% TH.7% $ TV.7% $ &-#?$;= -36 Table 60. Switching characteristics for NAND Flash write cycles(1) Symbol tw(NWE) Parameter FMC_NWE low width Max 4THCLK-0.5 4THCLK + 1.5 - 3.5 tv(NWE-D) FMC_NWE low to FMC_D[15-0] valid th(NWE-D) FMC_NWE high to FMC_D[15-0] invalid 3THCLK -1.5 - td(D-NWE) FMC_D[15-0] valid before FMC_NWE high 5THCLK - 3 - td(ALE_NWE) FMC_ALE valid before FMC_NWE low - 4THCLK+2 th(NWE-ALE) FMC_NWE high to FMC_ALE invalid 2THCLK-1 - 1. Based on characterization, not tested in production. 114/173 Min DocID026415 Rev 5 Unit ns STM32F303xD STM32F303xE 6.3.12 Electrical characteristics EMC characteristics Susceptibility tests are performed on a sample basis during device characterization. Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling two LEDs through I/O ports), the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs: * Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard. * FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard. A device reset allows normal operations to be resumed. The test results are given in Table 61. They are based on the EMS levels and classes defined in application note AN1709. Table 61. EMS characteristics Symbol Parameter Conditions Level/ Class VFESD VDD = 3.3 V, LQFP144, TA = +25C, Voltage limits to be applied on any I/O pin to fHCLK = 72 MHz induce a functional disturbance conforms to IEC 61000-4-2 2B VEFTB Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a functional disturbance VDD = 3.3 V, LQFP144, TA = +25C, fHCLK = 72 MHz conforms to IEC 61000-4-4 4A Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and pre qualification tests in relation with the EMC level requested for his application. Software recommendations The software flowchart must include the management of runaway conditions such as: * Corrupted program counter * Unexpected reset * Critical Data corruption (control registers...) DocID026415 Rev 5 115/173 151 Electrical characteristics STM32F303xD STM32F303xE Pre qualification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Electromagnetic Interference (EMI) The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with IEC 61967-2 standard which specifies the test board and the pin loading. Table 62. EMI characteristics Symbol Parameter SEMI 6.3.13 Monitored frequency band Conditions Max vs. [fHSE/fHCLK] Unit 8/72 MHz 0.1 to 30 MHz VDD = 3.6 V, TA = 25 C, 30 to 130 MHz LQFP144 package Peak level compliant with IEC 130 MHz to 1GHz 61967-2 SAE EMI Level 7 15 dBV 31 4 - Electrical sensitivity characteristics Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts x (n+1) supply pins). This test conforms to the ANSI/JEDEC standard. Table 63. ESD absolute maximum ratings Symbol VESD(HBM) Ratings Conditions Electrostatic discharge TA = +25 C, conforming voltage (human body model) to ANSI/JEDEC JS-001 Electrostatic discharge VESD(CDM) voltage (charge device model) TA = +25 C, conforming to ANSI/ESD STM5.3.1 1. Data based on characterization results, not tested in production. 116/173 DocID026415 Rev 5 Class Maximum value(1) 2 2000 Unit V C3 250 STM32F303xD STM32F303xE Electrical characteristics Static latch-up Two complementary static tests are required on six parts to assess the latch-up performance: * A supply overvoltage is applied to each power supply pin * A current injection is applied to each input, output and configurable I/O pin These tests are compliant with EIA/JESD 78A IC latch-up standard. Table 64. Electrical sensitivities Symbol LU 6.3.14 Parameter Conditions Class TA = +105 C conforming to JESD78A Static latch-up class II Level A I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below VSS or above VDD (for standard, 3 V-capable I/O pins) should be avoided during normal product operation. However, to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization. Functional susceptibility to I/O current injection While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures. The failure is indicated by an out of range parameter: ADC error above a certain limit (higher than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of -5 A/+0 A range), or other functional failure (for example reset occurrence or oscillator frequency deviation). The test results are given in Table 65. Table 65. I/O current injection susceptibility Functional susceptibility Symbol IINJ Description Negative injection Positive injection Injected current on BOOT0 -0 NA Injected current on PF3, PC1, PC2, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PB0, PB1, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PB13, PB14, PB15, PD8, PD9, PD10, PD11, PD12, PD13, PD14 pins with induced leakage current on adjacent pins less than 50 A or more than +400 A -5 +5 Injected current on PF2, PF4, PC0, PC1, PC2, PC3, PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PC4, PC5, PB2, PB11 with induced leakage current on other pins from this group less than -50 A or more than +400 A -5 DocID026415 Rev 5 Unit mA +5 117/173 151 Electrical characteristics STM32F303xD STM32F303xE Table 65. I/O current injection susceptibility (continued) Functional susceptibility Symbol IINJ Description Negative injection Positive injection Injected current on PB0, PB1, PE7, PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PB12, PB13, PB14, P15, PD8, PD9, PD10, PD11, PD12, PD13, PD14 with induced leakage current on other pins from this group less than -50 A or more than +400 A -5 +5 Injected current on any other FT and FTf pins -5 NA Injected current on any other pins -5 +5 Unit mA Note: It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents. 6.3.15 I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 66 are derived from tests performed under the conditions summarized in Table 19. All I/Os are CMOS and TTL compliant. Table 66. I/O static characteristics Symbol VIL Parameter Low level input voltage Conditions Min Typ Max TC and TTa I/O - - 0.3 VDD+0.07 (1) FT and FTf I/O - - 0.475 VDD-0.2 (1) BOOT0 - - 0.3 VDD-0.3 (1) All I/Os except BOOT0 - - 0.3 VDD (2) TC and TTa I/O 0.445 VDD+0.398 (1) - - - - - - - - FT and FTf I/O VIH High level input voltage Vhys Schmitt trigger hysteresis BOOT0 All I/Os except BOOT0 0.5 VDD+0.2 0.2 VDD+0.95 0.7 VDD TC and TTa I/O FT and FTf I/O BOOT0 118/173 (1) DocID026415 Rev 5 (2) (1) - 200 (1) - - 100 (1) - 300 (1) - - Unit V V mV STM32F303xD STM32F303xE Electrical characteristics Table 66. I/O static characteristics (continued) Symbol Ilkg Parameter Input leakage current (3) Conditions Min Typ Max TC, FT and FTf I/O TTa I/O in digital mode VSS VIN VDD - - 0.1 TTa I/O in digital mode VDD VIN VDDA - - 1 TTa I/O in analog mode VSS VIN VDDA - - 0.2 FT and FTf I/O(4) VDD VIN 5 V - - 10 Unit A RPU Weak pull-up equivalent resistor(5) VIN = VSS 25 40 55 k RPD Weak pull-down equivalent resistor(5) VIN = VDD 25 40 55 k CIO I/O pin capacitance - - 5 - pF 1. Data based on design simulation. 2. Tested in production. 3. Leakage could be higher than the maximum value, if negative current is injected on adjacent pins. Refer to Table 65: I/O current injection susceptibility. 4. To sustain a voltage higher than VDD +0.3 V, the internal pull-up/pull-down resistors must be disabled. 5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This PMOS/NMOS contribution to the series resistance is minimum (~10% order). All I/Os are CMOS and TTL compliant (no software configuration required). Their characteristics cover more than the strict CMOS-technology or TTL parameters. The coverage of these requirements is shown in Figure 36 and Figure 37 for standard I/Os. Figure 36. TC and TTa I/O input characteristics - CMOS port 9,/9,+ 9 '' HQWV9 9,+PLQ 9 ,+PLQ QV ODWLR 9 '' LJQVLPX V H G Q VHGR GD 6VWDQ &02 XLUHP UGUHT 9 ,+PLQ XFWLRQ %D QSURG L 7HVWHG QV LPXODWLR ' 9 'HVLJQV G Q VHGR 9 ,/PD[ %D $UHDQRWGHWHUPLQHG &026VWDQGDUGUHTXLUHPHQWV9,/PD[ 9'' 9,/PD[ LRQ URGXFW VWHGLQS 7H 9'' 9 069 DocID026415 Rev 5 119/173 151 Electrical characteristics STM32F303xD STM32F303xE Figure 37. TC and TTa I/O input characteristics - TTL port 9,/9,+ 9 WLRQV OD 9 '' QVLPX 9 ,+PLQ RQGHVLJ G %DVH 77/VWDQGDUGUHTXLUHPHQWV9,+PLQ 9 9,+PLQ V XODWLRQ ' 9 ' VLJQVLP H QG VHGR 9 ,/PD[ %D $UHDQRWGHWHUPLQHG 9,/PD[ 77/VWDQGDUGUHTXLUHPHQWV9,/PD[ 9 9'' 9 069 Figure 38. Five volt tolerant (FT and FTf) I/O input characteristics - CMOS port 9,/9,+ 9 9'' 9,+PLQ URGXFWLRQ ODWLRQV '' X 9 LJQVLP 9 ,/PD[ RQGHV G H V %D $UHDQRWGHWHUPLQHG &026VWDQGDUGUHTXLUHPHQWV9,/PD[ 9'' GXFWLRQ 9 ,+PLQ % 7HVWHGLQS XODWLRQV ' 9 'VLJQVLP H RQG DVHG LUHPHQWV QGDUGUHTX &026VWD 7HVWHGLQSUR 9'' 9 069 Figure 39. Five volt tolerant (FT and FTf) I/O input characteristics - TTL port 9,/9,+ 9 77/VWDQGDUGUHTXLUHPHQWV9,+PLQ 9 $UHDQRWGHWHUPLQHG QV ' ODWLR 9 ' QVLPX 9 ,+PLQ QGHVLJ GR %DVH XODWLRQV 9 '' HVLJQVLP LQ P G 9 ,/ GRQ %DVH 77/VWDQGDUGUHTXLUHPHQWV9,/PD[ 9 9'' 9 069 120/173 DocID026415 Rev 5 STM32F303xD STM32F303xE Electrical characteristics Output driving current The GPIOs (general purpose input/outputs) can sink or source up to +/-8 mA, and sink or source up to +/- 20 mA (with a relaxed VOL/VOH). In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 6.2: * The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating IVDD (see Table 17). * The sum of the currents sunk by all the I/Os on VSS plus the maximum Run consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating IVSS (see Table 17). Output voltage levels Unless otherwise specified, the parameters given in Table 67 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 19. All I/Os (FT, TTa and TC unless otherwise specified) are CMOS and TTL compliant. Table 67. Output voltage characteristics Symbol Parameter VOL(1) Output low level voltage for an I/O pin VOH(3) Output high level voltage for an I/O pin VOL (1) Output low level voltage for an I/O pin VOH (3) Output high level voltage for an I/O pin VOL(1)(4) Output low level voltage for an I/O pin VOH(3)(4) Output high level voltage for an I/O pin VOL(1)(4) Output low level voltage for an I/O pin VOH(3)(4) Output high level voltage for an I/O pin VOLFM+(4)(4) Output low level voltage for an FTf I/O pin in FM+ mode Conditions Min Max CMOS port(2) IIO = +48 mA 2.7 V < VDD < 3.6 V - 0.4 VDD-0.4 - - 0.4 2.4 - - 1.3 VDD-1.3 - - 0.4 VDD-0.4 - - 0.4 TTL port(2) IIO = +8 mA 2.7 V < VDD < 3.6 V IIO = +20 mA 2.7 V < VDD < 3.6 V IIO = +6 mA 2 V < VDD < 2.7 V IIO = +20 mA 2.7 V < VDD < 3.6 V Unit V 1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 17 and the sum of IIO (I/O ports and control pins) must not exceed IIO(PIN). 2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52. 3. The IIO current sourced by the device must always respect the absolute maximum rating specified in Table 17 and the sum of IIO (I/O ports and control pins) must not exceed IIO(PIN). 4. Data based on design simulation. DocID026415 Rev 5 121/173 151 Electrical characteristics STM32F303xD STM32F303xE Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 40 and Table 68, respectively. Unless otherwise specified, the parameters given are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 19. Table 68. I/O AC characteristics(1) OSPEEDRy [1:0] value(1) x0 01 Symbol fmax(IO)out Maximum frequency(2) tf(IO)out Output high to low level fall time tr(IO)out Output low to high level rise time fmax(IO)out Maximum frequency(2) tf(IO)out Output high to low level fall time tr(IO)out Output low to high level rise time fmax(IO)out 11 tf(IO)out tr(IO)out FM+ configuration(4) - Parameter Maximum frequency(2) Output high to low level fall time Output low to high level rise time fmax(IO)out Maximum frequency(2) tf(IO)out Output high to low level fall time tr(IO)out Output low to high level rise time tEXTIpw Pulse width of external signals detected by the EXTI controller Conditions Min Max Unit - 2(3) MHz - 125(3) - 125(3) - 10(3) - 25(3) - 25(3) CL = 30 pF, VDD = 2.7 V to 3.6 V - 50(3) CL = 50 pF, VDD = 2.7 V to 3.6 V - 30(3) CL = 50 pF, VDD = 2 V to 2.7 V - 20(3) CL = 30 pF, VDD = 2.7 V to 3.6 V - 5(3) CL = 50 pF, VDD = 2.7 V to 3.6 V - 8(3) CL = 50 pF, VDD = 2 V to 2.7 V - 12(3) CL = 30 pF, VDD = 2.7 V to 3.6 V - 5(3) CL = 50 pF, VDD = 2.7 V to 3.6 V - 8(3) CL = 50 pF, VDD = 2 V to 2.7 V - 12(3) - 2(4) - 12(4) - (4) CL = 50 pF, VDD = 2 V to 3.6 V CL = 50 pF, VDD = 2 V to 3.6 V CL = 50 pF, VDD = 2 V to 3.6 V ns CL = 50 pF, VDD = 2 V to 3.6 V CL = 50 pF, VDD = 2 to 3.6 V - MHz ns MHz ns MHz ns 10(3) 34 - ns 1. The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the RM0316 reference manual for a description of GPIO Port configuration register. 2. The maximum frequency is defined in Figure 40. 3. Guaranteed by design, not tested in production. 4. The I/O speed configuration is bypassed in FM+ I/O mode. Refer to the reference manual RM0316 for a description of FM+ I/O mode configuration. 122/173 DocID026415 Rev 5 STM32F303xD STM32F303xE Electrical characteristics Figure 40. I/O AC characteristics definition WU ,2 RXW WI ,2 RXW 7 0D[LPXPIUHTXHQF\LVDFKLHYHGLI WUWI 7DQGLIWKHGXW\F\FOHLV ZKHQORDGHGE\&/ .47 1. See Table 68: I/O AC characteristics. 6.3.16 NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 66). Unless otherwise specified, the parameters given in Table 69 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 19. Table 69. NRST pin characteristics Symbol Conditions Min Typ Max VIL(NRST)(1) NRST Input low level voltage - - - 0.3VDD+ 0.07(1) VIH(NRST)(1) NRST Input high level voltage - 0.445VDD+ 0.398(1) - - - - 200 - mV VIN = VSS 25 40 55 k ns ns Vhys(NRST) RPU VF(NRST)(1) Parameter NRST Schmitt trigger voltage hysteresis Weak pull-up equivalent resistor NRST Input filtered pulse VNF(NRST)(1) NRST Input not filtered pulse (2) - - - 100(1) - 500(1) - - Unit V 1. Guaranteed by design, not tested in production. 2. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance must be minimum (~10% order). DocID026415 Rev 5 123/173 151 Electrical characteristics STM32F303xD STM32F303xE Figure 41. Recommended NRST pin protection ([WHUQDO UHVHWFLUFXLW 9'' 538 1567 ,QWHUQDOUHVHW )LOWHU ) 069 1. The reset network protects the device against parasitic resets. 2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 69. Otherwise the reset is not taken into account by the device. 3. Place the external capacitor 0.1u F on NRST as close as possible to the chip. 6.3.17 Timer characteristics The parameters given in Table 70 are guaranteed by design. Refer to Section 6.3.15: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 70. TIMx(1)(2) characteristics Symbol tres(TIM) fEXT ResTIM tCOUNTER Parameter Timer resolution time Timer external clock frequency on CH1 to CH4 Timer resolution 16-bit counter clock period Maximum possible count tMAX_COUNT with 32-bit counter Conditions Min Max Unit - 1 - tTIMxCLK fTIMxCLK = 72 MHz 13.9 - ns fTIMxCLK = 144 MHz 6.95 - ns 0 fTIMxCLK/2 MHz fTIMxCLK = 72 MHz 0 36 MHz TIMx (except TIM2) - 16 TIM2 - 32 - 1 65536 tTIMxCLK fTIMxCLK = 72 MHz 0.0139 910 s fTIMxCLK = 144 MHz 0.0069 455 s - - 65536 x 65536 tTIMxCLK fTIMxCLK = 72 MHz - 59.65 s fTIMxCLK = 144 MHz - 29.825 s - bit 1. TIMx is used as a general term to refer to the TIM1, TIM2, TIM3, TIM4, TIM8, TIM15, TIM16, TIM17 and TIM20 timers. 2. Guaranteed by design, not tested in production. 124/173 DocID026415 Rev 5 STM32F303xD STM32F303xE Electrical characteristics Table 71. IWDG min/max timeout period at 40 kHz (LSI) (1) Prescaler divider PR[2:0] bits Min timeout (ms) RL[11:0]= 0x000 Max timeout (ms) RL[11:0]= 0xFFF /4 0 0.1 409.6 /8 1 0.2 819.2 /16 2 0.4 1638.4 /32 3 0.8 3276.8 /64 4 1.6 6553.6 /128 5 3.2 13107.2 /256 7 6.4 26214.4 1. These timings are given for a 40 kHz clock but the microcontroller internal RC frequency can vary from 30 to 60 kHz. Moreover, given an exact RC oscillator frequency, the exact timings still depend on the phasing of the APB interface clock versus the LSI clock so that there is always a full RC period of uncertainty. Table 72. WWDG min-max timeout value @72 MHz (PCLK)(1) Prescaler WDGTB Min timeout value Max timeout value 1 0 0.05687 3.6409 2 1 0.1137 7.2817 4 2 0.2275 14.564 8 3 0.4551 29.127 1. Guaranteed by design, not tested in production. 6.3.18 Communications interfaces I2C interface characteristics The I2C interface meets the timings requirements of the I2C-bus specification and user manual rev.03 for: * Standard-mode (Sm): with a bit rate up to 100 kbit/s * Fast-mode (Fm): with a bit rate up to 400 kbit/s * Fast-mode Plus (Fm+): with a bit rate up to 1Mbits/s The I2C timings requirements are guaranteed by design when the I2C peripheral is properly configured (refer to Reference manual). The SDA and SCL I/O requirements are met with the following restrictions: the SDA and SCL I/O pins are "true" open-drain. When configured as open-drain, the PMOS connected between the I/O pin and VDDIOx is disabled, but is still present. Only FTf I/O pins support Fm+ low level output current maximum requirement. Refer to Section 6.3.15: I/O port characteristics. All I2C I/Os embed an analog filter, refer to the Table 73: I2C analog filter characteristics. DocID026415 Rev 5 125/173 151 Electrical characteristics STM32F303xD STM32F303xE Table 73. I2C analog filter characteristics(1) Symbol tAF Parameter Pulse width of spikes that are suppressed by the analog filter Min Max Unit 50 260 ns 1. Guaranteed by design, not tested in production. SPI/I2S characteristics Unless otherwise specified, the parameters given in Table 74 for SPI or in Table 75 for I2S are derived from tests performed under ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 19. Refer to Section 6.3.15: I/O port characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO for SPI and WS, CK, SD for I2S). Table 74. SPI characteristics(1) Symbol Parameter Conditions Master mode 2.7 V<VDD<3.6 V, SPI1/4 fSCK 1/tc(SCK) SPI clock frequency th(SI) 24 Slave mode 2 V<VDD<3.6 V, SPI1/2/3/4 18 Slave mode transmitter/full duplex 2.7 V<VDD<3.6 V, SPI1/4 22.5(2)) % 50 70 Slave mode, SPI presc = 2 4*Tpclk - - NSS hold time Slave mode, SPI presc = 2 2*Tpclk - - SCK high and low time Master mode Tpclk-2 Tpclk Tpclk+2 Master mode 3 - - Slave mode 3 - - Master mode 6.5 - - Slave mode 4.5 - - Data input hold time ta(SO) Data output access time Slave mode 10 - 30 tdis(SO) Data output disable time Slave mode 8 - 7 126/173 MHz 16.5(2) 30 Data input setup time Unit Slave mode transmitter/full duplex 2 V<VDD<3.6 V, SPI1/2/3/4 th(NSS) th(MI) - 24 NSS setup time tsu(SI) - Slave mode 2 V<VDD<3.6 V, SPI1/4 tsu(NSS) tsu(MI) Max 18 Slave mode tw(SCKH) tw(SCKL) Typ. Master mode 2 V<VDD<3.6 V, SPI1/2/3/4 Duty cycle of SPI clock frequency Duty(SCK) Min DocID026415 Rev 5 STM32F303xD STM32F303xE Electrical characteristics Table 74. SPI characteristics(1) (continued) Symbol Parameter tv(SO) Conditions Data output valid time tv(MO) th(SO) Data output hold time th(MO) Min Typ. Max Slave mode 2.7 V<VDD<3.6 V - 15 22 Slave mode 2 V<VDD<3.6 V - 15 30 Master mode - 2 4.5 Slave mode 9 - - Master mode 0 - - Unit 1. Data based on characterization results, not tested in production. 2. The maximum frequency in Slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit into SCK low or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates with a master having tsu(MI) = 0 while Duty(SCK) = 50%. Figure 42. SPI timing diagram - slave mode and CPHA = 0 166LQSXW 6&.,QSXW W68 166 &3+$ &32/ &3+$ &32/ WK 166 WF 6&. WZ 6&.+ WZ 6&./ W9 62 WD 62 0,62 287387 WK 62 06%287 %,7287 06%,1 %,7,1 WU 6&. WI 6&. WGLV 62 /6%287 WVX 6, 026, ,1387 /6%,1 WK 6, DLF DocID026415 Rev 5 127/173 151 Electrical characteristics STM32F303xD STM32F303xE Figure 43. SPI timing diagram - slave mode and CPHA = 1(1) 166LQSXW 6&.LQSXW W68 166 &3+$ &32/ &3+$ &32/ WK 166 WF 6&. WZ 6&.+ WZ 6&./ WK 62 WY 62 WD 62 0,62 287387 06%287 %,7287 WGLV 62 /6%287 WK 6, WVX 6, 026, ,1387 WU 6&. WI 6&. 06%,1 %,7,1 /6%,1 DLE 1. Measurement points are done at 0.5VDD and with external CL = 30 pF. Figure 44. SPI timing diagram - master mode(1) +LJK 166LQSXW 6&.2XWSXW &3+$ &32/ 6&.2XWSXW WF 6&. &3+$ &32/ &3+$ &32/ &3+$ &32/ WVX 0, 0,62 ,13 87 WZ 6&.+ WZ 6&./ 06%,1 WU 6&. WI 6&. %,7,1 /6%,1 WK 0, 026, 287387 06%287 WY 02 % , 7287 /6%287 WK 02 DLF 1. Measurement points are done at 0.5VDD and with external CL = 30 pF. 128/173 DocID026415 Rev 5 STM32F303xD STM32F303xE Electrical characteristics Table 75. I2S characteristics(1) Symbol fMCK Parameter Conditions I2S Main clock output Min Max Unit 256 x 8K 256xFs (2) MHz Master data: 32 bits - 64xFs MHz Slave data: 32 bits - 64xFs - 30 70 % - fCK I2S clock frequency DCK I2S clock frequency duty Slave receiver cycle tv(WS) WS valid time Master mode - 20 th(WS) WS hold time Master mode 2 - tsu(WS) WS setup time Slave mode 0 - th(WS) WS hold time Slave mode 4 - Master receiver 1 - Slave receiver 1 - Master receiver 8 - Slave receiver 2.5 - Slave transmitter (after enable edge) - 50 tv(SD_MT) Master transmitter (after enable edge) - 22 th(SD_ST) Slave transmitter (after enable edge) 8 - Master transmitter (after enable edge) 1 - tsu(SD_MR) tsu(SD_SR) th(SD_MR) th(SD_SR) Data input setup time Data input hold time tv(SD_ST) Data output valid time Data output hold time th(SD_MT) ns 1. Data based on characterization results, not tested in production. 2. 256xFs maximum is 36 MHz (APB1 Maximum frequency) Note: Refer to the I2S section in RM0316 Reference Manual for more details about the sampling frequency (Fs), fMCK, fCK, DCK values reflect only the digital peripheral behavior, source clock precision might slightly change the values DCK depends mainly on ODD bit value. Digital contribution leads to a min of (I2SDIV/(2*I2SDIV+ODD) and a max of (I2SDIV+ODD)/(2*I2SDIV+ODD) and Fs max supported for each mode/condition. DocID026415 Rev 5 129/173 151 Electrical characteristics STM32F303xD STM32F303xE Figure 45. I2S slave timing diagram (Philips protocol)(1) &.,QSXW WF &. &32/ &32/ WZ &.+ WK :6 WZ &./ :6LQSXW WY 6'B67 WVX :6 6'WUDQVPLW /6%WUDQVPLW 06%WUDQVPLW WVX 6'B65 /6%UHFHLYH 6'UHFHLYH WK 6'B67 %LWQWUDQVPLW /6%WUDQVPLW WK 6'B65 06%UHFHLYH %LWQUHFHLYH /6%UHFHLYH DLE 1. Measurement points are done at 0.5VDD and with external CL=30 pF. 2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. Figure 46. I2S master timing diagram (Philips protocol)(1) TF#+ TR#+ #+ OUTPUT TC#+ #0/, TW#+( #0/, TV73 TH73 TW#+, 73 OUTPUT TV3$?-4 3$TRANSMIT ,3" TRANSMIT -3" TRANSMIT ,3" RECEIVE ,3" TRANSMIT TH3$?-2 TSU3$?-2 3$RECEIVE "ITN TRANSMIT TH3$?-4 -3" RECEIVE "ITN RECEIVE ,3" RECEIVE AIB 1. Measurement points are done at 0.5VDD and with external CL=30 pF. 2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first byte. 130/173 DocID026415 Rev 5 STM32F303xD STM32F303xE Electrical characteristics USB characteristics Table 76. USB startup time Symbol Parameter tSTARTUP(1) Max Unit 1 s USB transceiver startup time 1. Guaranteed by design, not tested in production. Table 77. USB DC electrical characteristics Symbol Conditions Min.(1) Max.(1) Unit - 3.0(3) 3.6 V I(USB_DP, USB_DM) 0.2 - Parameter Input levels VDD USB operating voltage(2) VDI(4) Differential input sensitivity VCM(4) Differential common mode range Includes VDI range 0.8 2.5 VSE(4) Single ended receiver threshold - 1.3 2.0 V Output levels VOL Static output level low RL of 1.5 k to 3.6 V(5) - 0.3 VOH Static output level high RL of 15 k to VSS(5) 2.8 3.6 V 1. All the voltages are measured from the local ground potential. 2. To be compliant with the USB 2.0 full-speed electrical specification, the USB_DP (D+) pin should be pulled up with a 1.5 k resistor to a 3.0-to-3.6 V voltage range. 3. The STM32F303xD/E USB functionality is ensured down to 2.7 V but not the full USB electrical characteristics which are degraded in the 2.7-to-3.0 V VDD voltage range. 4. Guaranteed by design, not tested in production. 5. RL is the load connected on the USB drivers. Figure 47. USB timings: definition of data signal rise and fall time &URVVRYHU SRLQWV 'LIIHUHQWLDO GDWDOLQHV 9&56 966 WI WU DLE Table 78. USB: full-speed electrical characteristics(1) Symbol Parameter Conditions Min Typ Max Unit CL = 50 pF 4 - 20 ns CL = 50 pF 4 - 20 ns Driver characteristics tr tf Rise time(2) Fall time(2) DocID026415 Rev 5 131/173 151 Electrical characteristics STM32F303xD STM32F303xE Table 78. USB: full-speed electrical characteristics(1) (continued) Symbol trfm VCRS Parameter Conditions Min Typ Max Unit tr/tf 90 - 110 % - 1.3 - 2.0 V driving high and low 28 40 44 Rise/ fall time matching Output signal crossover voltage Output driver Z Impedance(3) DRV 1. Guaranteed by design, not tested in production. 2. Measured from 10% to 90% of the data signal. For more detailed information, refer to USB Specification - Chapter 7 (version 2.0). 3. No external termination series resistors are required on USB_DP (D+) and USB_DM (D-), the matching impedance is already included in the embedded driver. CAN (controller area network) interface Refer to Section 6.3.15: I/O port characteristics for more details on the input/output alternate function characteristics (CAN_TX and CAN_RX). 6.3.19 ADC characteristics Unless otherwise specified, the parameters given in Table 79 to Table 82 are guaranteed by design, with conditions summarized in Table 19. Table 79. ADC characteristics Symbol VDDA IDDA 132/173 Parameter Analog supply voltage for ADC Current on VDDA pin (see Figure 48) Conditions Min Typ Max Unit - 2.0 - 3.6 V Single-ended mode, 5 MSPS - 907 1033 Single-ended mode, 1 MSPS - 194 285.5 Single-ended mode, 200 KSPS - 51.5 70 Differential mode, 5 MSPS - 887.5 1009 Differential mode, 1 MSPS - 212 285 Differential mode, 200 KSPS - 51 69.5 DocID026415 Rev 5 A STM32F303xD STM32F303xE Electrical characteristics Table 79. ADC characteristics (continued) Symbol Conditions Min Typ Max Single-ended mode, 5 MSPS - 104 139 Single-ended mode, 1 MSPS - 20.4 37 Single-ended mode, 200 KSPS - 3.3 11.3 Differential mode, 5 MSPS - 174 235 Differential mode, 1 MSPS - 34.6 52.6 Differential mode, 200 KSPS - 6 13.6 Positive reference voltage - 2 - VDDA V ADC clock frequency - 0.14 - 72 MHz Resolution = 12 bits, Fast Channel 0.01 - 5.14 Resolution = 10 bits, Fast Channel 0.012 - 6 Resolution = 8 bits, Fast Channel 0.014 - 7.2 Resolution = 6 bits, Fast Channel 0.0175 - 9 fADC = 72 MHz Resolution = 12 bits - - 5.14 MHz Resolution = 12 bits - - 14 1/fADC - 0 - VREF+ V Current on VREF+ pin (see Figure 49) IREF VREF+ fADC fS(1) fTRIG Parameter (1) VAIN Sampling rate External trigger frequency Conversion voltage range(2) Unit A MSPS RAIN(1) External input impedance - - - 100 k CADC(1) Internal sample and hold capacitor - - 5 - pF tSTAB(1) Power-up time - 0 0 1 s tCAL(1) Calibration time tlatr(1) Trigger conversion latency Regular and injected channels without conversion abort tlatrinj(1) Trigger conversion latency Injected channels aborting a regular conversion fADC = 72 MHz 1.56 s - 112 1/fADC CKMODE = 00 1.5 2 2.5 1/fADC CKMODE = 01 - - 2 1/fADC CKMODE = 10 - - 2.25 1/fADC CKMODE = 11 - - 2.125 1/fADC CKMODE = 00 2.5 3 3.5 1/fADC CKMODE = 01 - - 3 1/fADC CKMODE = 10 - - 3.25 1/fADC CKMODE = 11 - - 3.125 1/fADC DocID026415 Rev 5 133/173 151 Electrical characteristics STM32F303xD STM32F303xE Table 79. ADC characteristics (continued) Symbol tS(1) Parameter Sampling time Conditions Min Typ Max Unit fADC = 72 MHz 0.021 - 8.35 s - 1.5 - 601.5 1/fADC - - - 10 s fADC = 72 MHz Resolution = 12 bits 0.19 - 8.52 s TADCVREG ADC Voltage Regulator (1) Start-up time _STUP tCONV(1) CMIR Total conversion time (including sampling time) Common Mode Input signal range Resolution = 12 bits ADC differential mode 14 to 614 (tS for sampling + 12.5 for successive approximation) (VSSA + VREF+)/2 - 0.18 (VSSA + VREF+)/2 1/fADC (VSSA + VREF+)/2 + 0.18 V 1. Data guaranteed by design, not tested in Production. 2. VREF+ can be internally connected to VDDA and VREF- can be internally connected to VSSA, depending on the package. Refer to Section 4: Pinout and pin description for further details. Figure 48. ADC typical current consumption on VDDA pin $'&FXUUHQWFRQVXPSWLRQ $ 6LQJOHHQGHGPRGH 'LIIHUHQWLDOPRGH &ORFNIUHTXHQF\ 0636 134/173 DocID026415 Rev 5 069 STM32F303xD STM32F303xE Electrical characteristics Figure 49. ADC typical current consumption on VREF+ pin $'&FXUUHQWFRQVXPSWLRQ $ 6LQJOHHQGHGPRGH 'LIIHUHQWLDOPRGH &ORFNIUHTXHQF\ 0636 069 Table 80. Maximum ADC RAIN (1) Resolution 12 bits 10 bits RAIN max (k) Sampling cycle @ 72 MHz Sampling time [ns] @ 72 MHz Fast channels(2) Slow channels Other channels(3) 1.5 20.83 0.018 NA NA 2.5 34.72 0.150 NA 0.022 4.5 62.50 0.470 0.220 0.180 7.5 104.17 0.820 0.560 0.470 19.5 270.83 2.70 1.80 1.50 61.5 854.17 8.20 6.80 4.70 181.5 2520.83 22.0 18.0 15.0 601.5 8354.17 82.0 68.0 47.0 1.5 20.83 0.082 NA NA 2.5 34.72 0.270 0.082 0.100 4.5 62.50 0.560 0.390 0.330 7.5 104.17 1.20 0.82 0.68 19.5 270.83 3.30 2.70 2.20 61.5 854.17 10.0 8.2 6.8 181.5 2520.83 33.0 27.0 22.0 601.5 8354.17 100.0 82.0 68.0 DocID026415 Rev 5 135/173 151 Electrical characteristics STM32F303xD STM32F303xE Table 80. Maximum ADC RAIN (1) (continued) Resolution 8 bits 6 bits RAIN max (k) Sampling cycle @ 72 MHz Sampling time [ns] @ 72 MHz Fast channels(2) Slow channels Other channels(3) 1.5 20.83 0.150 NA 0.039 2.5 34.72 0.390 0.180 0.180 4.5 62.50 0.820 0.560 0.470 7.5 104.17 1.50 1.20 1.00 19.5 270.83 3.90 3.30 2.70 61.5 854.17 12.00 12.00 8.20 181.5 2520.83 39.00 33.00 27.00 601.5 8354.17 100.00 100.00 82.00 1.5 20.83 0.270 0.100 0.150 2.5 34.72 0.560 0.390 0.330 4.5 62.50 1.200 0.820 0.820 7.5 104.17 2.20 1.80 1.50 19.5 270.83 5.60 4.70 3.90 61.5 854.17 18.0 15.0 12.0 181.5 2520.83 56.0 47.0 39.0 601.5 8354.17 100.00 100.0 100.0 1. Data based on characterization results, not tested in production. 2. All fast channels, expect channels on PA2, PA6, PB1, PB12. 3. Fast channels available on PA2, PA6, PB1, PB12. 136/173 DocID026415 Rev 5 STM32F303xD STM32F303xE Electrical characteristics Table 81. ADC accuracy - limited test conditions, 100-/144-pin packages (1)(2) Symbol Parameter ET Total unadjusted error Single ended Differential Single ended EO Offset error Differential Single ended EG Gain error Differential ED EL Differential linearity error Integral linearity error Effective ENOB(4) number of bits Signal-tonoise and (4) SINAD distortion ratio Min Conditions ADC clock freq. 72 MHz Sampling freq. 5 Msps VDDA = VREF+ = 3.3 V 25C 100-pin/144-pin package Single ended Differential Single ended Differential Single ended Differential Single ended Differential DocID026415 Rev 5 (3) Typ Max (3) Unit 3.5 4.5 Fast channel 5.1 Ms - Slow channel 4.8 Ms - 4 4.5 Fast channel 5.1 Ms - 3 3 Slow channel 4.8 Ms - 3 3 Fast channel 5.1 Ms - 1 1.5 Slow channel 4.8 Ms - 1 2.5 Fast channel 5.1 Ms - 1 1.5 Slow channel 4.8 Ms - 1 1.5 Fast channel 5.1 Ms - 3 4 Slow channel 4.8 Ms - 3.5 4 Fast channel 5.1 Ms - 1.5 2.5 Slow channel 4.8 Ms - 2 2.5 Fast channel 5.1 Ms - 1 1.5 Slow channel 4.8 Ms - 1 1.5 Fast channel 5.1 Ms - 1 1 Slow channel 4.8 Ms - 1 1 Fast channel 5.1 Ms - 1.5 2 Slow channel 4.8 Ms - 1.5 3 Fast channel 5.1 Ms - 1 1.5 Slow channel 4.8 Ms - 1 1.5 Fast channel 5.1 Ms 10.7 10.8 - Slow channel 4.8 Ms 10.7 10.8 - Fast channel 5.1 Ms 11.2 11.3 - Slow channel 4.8 Ms 11.1 11.3 - Fast channel 5.1 Ms 66 67 - Slow channel 4.8 Ms 66 67 - Fast channel 5.1 Ms 69 70 - Slow channel 4.8 Ms 69 70 - LSB bits dB 137/173 151 Electrical characteristics STM32F303xD STM32F303xE Table 81. ADC accuracy - limited test conditions, 100-/144-pin packages (1)(2) (continued) Symbol Parameter Single ended SNR(4) THD(4) Signal-tonoise ratio Total harmonic distortion Min Conditions ADC clock freq. 72 MHz Sampling freq 5 Msps VDDA = VREF+ = 3.3 V 25C 100-pin/144-pin package Differential Single ended Differential Max (3) Typ Fast channel 5.1 Ms 66 67 - Slow channel 4.8 Ms 66 67 - Fast channel 5.1 Ms 69 70 - Slow channel 4.8 Ms 69 70 - Fast channel 5.1 Ms - -76 -76 Slow channel 4.8 Ms - -76 -76 Fast channel 5.1 Ms - -80 -80 Slow channel 4.8 Ms - -80 -80 (3) Unit dB 1. ADC DC accuracy values are measured after internal calibration. 2. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative current. Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 6.3.15 does not affect the ADC accuracy. 3. Data based on characterization results, not tested in production. 4. Value measured with a -0.5 dB full scale 50 kHz sine wave input signal. Table 82. ADC accuracy, 100-pin/144-pin packages(1)(2)(3) Symbol Parameter ET Single Ended Total unadjusted error Differential Single Ended EO Offset error ADC clock freq. 72 MHz, Sampling freq. 5 Msps 2.0 V VDDA, VREF+ 3.6 V 100-pin/144-pin package EG Differential Single Ended Gain error Differential ED 138/173 Differential linearity error Min (4) Max(4) Fast channel 5.1 Ms - 6.5 Slow channel 4.8 Ms - 6.5 Fast channel 5.1 Ms - 4 Slow channel 4.8 Ms - 4 Fast channel 5.1 Ms - 3 Slow channel 4.8 Ms - 3 Fast channel 5.1 Ms - 2 Slow channel 4.8 Ms - 2 Fast channel 5.1 Ms - 6 Slow channel 4.8 Ms - 6 Fast channel 5.1 Ms - 3 Slow channel 4.8 Ms - 3 Fast channel 5.1 Ms - 1.5 Slow channel 4.8 Ms - 1.5 Fast channel 5.1 Ms - 1.5 Slow channel 4.8 Ms - 1.5 Conditions Single Ended Differential DocID026415 Rev 5 Unit LSB STM32F303xD STM32F303xE Electrical characteristics Table 82. ADC accuracy, 100-pin/144-pin packages(1)(2)(3) (continued) Symbol Parameter EL ENOB (5) SNR(5) Single Ended Integral linearity error Differential Single Ended Effective number of bits Signal-toSINAD noise and (5) distortion ratio Signal-tonoise ratio Differential ADC clock freq. 72 MHz, Sampling freq. 5 Msps, 2.0 V VDDA, VREF+ 3.6 V 100-pin/144-pin package Single Ended Differential Single Ended Differential THD(5) Total harmonic distortion Min (4) Max(4) Fast channel 5.1 Ms - 2 Slow channel 4.8 Ms - 3 Fast channel 5.1 Ms - 2 Slow channel 4.8 Ms - 2 Fast channel 5.1 Ms 10.4 - Slow channel 4.8 Ms 10.2 - Fast channel 5.1 Ms 10.8 - Slow channel 4.8 Ms 10.8 - Fast channel 5.1 Ms 64 - Slow channel 4.8 Ms 63 - Fast channel 5.1 Ms 67 - Slow channel 4.8 Ms 67 - Fast channel 5.1 Ms 64 - Slow channel 4.8 Ms 64 - Fast channel 5.1 Ms 67 - Slow channel 4.8 Ms 67 - Fast channel 5.1 Ms - 74 Slow channel 4.8 Ms - -74 Fast channel 5.1 Ms - -78 Slow channel 4.8 Ms - -76 Conditions Single Ended Differential Unit LSB bits dB 1. ADC DC accuracy values are measured after internal calibration. 2. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative current. Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 6.3.15 does not affect the ADC accuracy. 3. Better performance may be achieved in restricted VDDA, frequency and temperature ranges. 4. Data based on characterization results, not tested in production. 5. Value measured with a -0.5 dB full scale 50 kHz sine wave input signal. DocID026415 Rev 5 139/173 151 Electrical characteristics STM32F303xD STM32F303xE Table 83. ADC accuracy - limited test conditions, 64-pin packages(1)(2) Symbol Parameter ET Single ended Total unadjusted error Differential Single ended EO Offset error Differential Single ended EG Gain error Differential ED EL ENOB (4) SINAD (4) 140/173 Differential linearity error Integral linearity error Effective number of bits Signal-tonoise and distortion ratio Min Conditions ADC clock freq. 72 MHz Sampling freq. 5 Msps VDDA = 3.3 V 25C 64-pin package Single ended Differential Single ended Differential Single ended Differential Single ended Differential DocID026415 Rev 5 Max (3) Typ Fast channel 5.1 Ms - 4 4.5 Slow channel 4.8 Ms - 5.5 6 Fast channel 5.1 Ms - 3.5 4 Slow channel 4.8 Ms - 3.5 4 Fast channel 5.1 Ms - 2 2 Slow channel 4.8 Ms - 1.5 2 Fast channel 5.1 Ms - 1.5 2 Slow channel 4.8 Ms - 1.5 2 Fast channel 5.1 Ms - 3 4 Slow channel 4.8 Ms - 5 5.5 Fast channel 5.1 Ms - 3 3 Slow channel 4.8 Ms - 3 3.5 Fast channel 5.1 Ms - 1 1 Slow channel 4.8 Ms - 1 1 Fast channel 5.1 Ms - 1 1 Slow channel 4.8 Ms - 1 1 Fast channel 5.1 Ms - 1.5 2 Slow channel 4.8 Ms - 2 3 Fast channel 5.1 Ms - 1.5 1.5 Slow channel 4.8 Ms - 1.5 (3) Unit LSB 2 Fast channel 5.1 Ms 10.8 10.8 - Slow channel 4.8 Ms 10.8 10.8 - Fast channel 5.1 Ms 11.2 11.3 - Slow channel 4.8 Ms 11.2 11.3 - Fast channel 5.1 Ms 66 67 - Slow channel 4.8 Ms 66 67 - Fast channel 5.1 Ms 69 70 - Slow channel 4.8 Ms 69 70 - bit dB STM32F303xD STM32F303xE Electrical characteristics Table 83. ADC accuracy - limited test conditions, 64-pin packages(1)(2) (continued) Symbol Parameter Min Conditions Single ended SNR(4) THD(4) Signal-tonoise ratio Total harmonic distortion ADC clock freq. 72 MHz Sampling freq 5 Msps VDDA = 3.3 V 25C 64-pin package Differential Single ended Differential Max (3) Typ Fast channel 5.1 Ms 66 67 - Slow channel 4.8 Ms 66 67 - Fast channel 5.1 Ms 69 70 - Slow channel 4.8 Ms 69 70 - Fast channel 5.1 Ms - -80 -80 Slow channel 4.8 Ms - -78 -77 Fast channel 5.1 Ms - -83 -82 Slow channel 4.8 Ms - -81 -80 (3) Unit dB 1. ADC DC accuracy values are measured after internal calibration. 2. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative current. Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 6.3.15 does not affect the ADC accuracy. 3. Data based on characterization results, not tested in production. 4. Value measured with a -0.5 dB full scale 50 kHz sine wave input signal. Table 84. ADC accuracy, 64-pin packages(1)(2)(3) Symbol Parameter ET Single ended Total unadjusted error Differential Single ended EO Offset error ADC clock freq. 72 MHz, Sampling freq. 5 Msps 2.0 V VDDA 3.6 V 64-pin package EG Differential Single ended Gain error Differential ED Differential linearity error Min(4) Max Fast channel 5.1 Ms - 6.5 Slow channel 4.8 Ms - 6.5 Fast channel 5.1 Ms - 4 Slow channel 4.8 Ms - 4.5 Fast channel 5.1 Ms - 3 Slow channel 4.8 Ms - 3 Fast channel 5.1 Ms - 2.5 Slow channel 4.8 Ms - 2.5 Fast channel 5.1 Ms - 6 Slow channel 4.8 Ms - 6 Fast channel 5.1 Ms - 3.5 Slow channel 4.8 Ms - 4 Fast channel 5.1 Ms - 1.5 Slow channel 4.8 Ms - 1.5 Fast channel 5.1 Ms - 1.5 Slow channel 4.8 Ms - 1.5 Conditions Single ended Differential DocID026415 Rev 5 (4) Unit LSB 141/173 151 Electrical characteristics STM32F303xD STM32F303xE Table 84. ADC accuracy, 64-pin packages(1)(2)(3) (continued) Symbol Parameter EL ENOB (5) SINAD (5) Single ended Integral linearity error Differential Single ended Effective number of bits Signal-tonoise and distortion ratio Differential ADC clock freq. 72 MHz, Sampling freq 5 Msps, 2.0 V VDDA 3.6 V 64-pin package Single ended Differential Single ended SNR(5) Signal-tonoise ratio Differential THD(5) Total harmonic distortion Min(4) Max Fast channel 5.1 Ms - 3 Slow channel 4.8 Ms - 3.5 Fast channel 5.1 Ms - 2 Slow channel 4.8 Ms - 2.5 Fast channel 5.1 Ms 10.4 - Slow channel 4.8 Ms 10.4 - Fast channel 5.1 Ms 10.8 - Slow channel 4.8 Ms 10.8 - Fast channel 5.1 Ms 64 - Slow channel 4.8 Ms 63 - Fast channel 5.1 Ms 67 - Slow channel 4.8 Ms 67 - Fast channel 5.1 Ms 64 - Slow channel 4.8 Ms 64 - Fast channel 5.1 Ms 67 - Slow channel 4.8 Ms 67 - Fast channel 5.1 Ms - -75 Slow channel 4.8 Ms - -75 Fast channel 5.1 Ms - -79 Slow channel 4.8 Ms - -78 Conditions Single ended Differential (4) Unit LSB bits dB dB 1. ADC DC accuracy values are measured after internal calibration. 2. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative current. Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 6.3.15 does not affect the ADC accuracy. 3. Better performance may be achieved in restricted VDDA, frequency and temperature ranges. 4. Data based on characterization results, not tested in production. 5. Value measured with a -0.5 dB full scale 50 kHz sine wave input signal. 142/173 DocID026415 Rev 5 STM32F303xD STM32F303xE Electrical characteristics Table 85. ADC accuracy at 1MSPS(1)(2) Symbol Parameter Typ Max(3) Fast channel 2.5 5 Slow channel 3.5 5 Fast channel 1 2.5 1.5 2.5 2 3 Test conditions ET Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error Slow channel ADC Freq 72 MHz Fast channel Sampling Freq 1MSPS 2.4 V VDDA = VREF+ 3.6 V Slow channel Single-ended mode Fast channel 3 4 0.7 2 Slow channel 0.7 2 Fast channel 1 3 Slow channel 1.2 3 Unit LSB 1. ADC DC accuracy values are measured after internal calibration. 2. ADC accuracy vs. negative Injection Current: Injecting negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative current. Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 6.3.15: I/O port characteristics does not affect the ADC accuracy. 3. Data based on characterization results, not tested in production. Figure 50. ADC accuracy characteristics ;,3" )$%!, 6 2%& OR 6 $$! DEPENDING ON PACKAGE = %' %4 %/ %, %$ , 3" )$%!, 6 33! DocID026415 Rev 5 6 $$! AIC 143/173 151 Electrical characteristics STM32F303xD STM32F303xE Figure 51. Typical connection diagram using the ADC 9'' 6DPSOHDQGKROG$'& FRQYHUWHU 97 9 5$,1 9$,1 5$'& $,1[ &SDUDVLWLF ELW FRQYHUWHU ,/$ 97 9 &$'& 069 1. Refer to Table 79 for the values of RAIN. 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 pF). A high Cparasitic value downgrades conversion accuracy. To remedy this, fADC should be reduced. General PCB design guidelines Power supply decoupling should be performed as shown in Figure 12. The 10 nF capacitor should be ceramic (good quality) and it should be placed as close as possible to the chip. 6.3.20 DAC electrical specifications Table 86. DAC characteristics Symbol VDDA RLOAD (1) RL RO(1) CLOAD(1) VDAC_OUT (1) Parameter Conditions Min Typ Max Unit - 2.4 - 3.6 V DAC output buffer ON 5 - - k Dac output buffer ON: connected to VSSA 5 - - k Dac output buffer ON: connected to VDDA 25 - - k Output impedance DAC output buffer OFF - - 15 k Capacitive load DAC output buffer ON - - 50 pF 0.2 - VDDA - 0.2 V - 0.5 VDDA - 1LSB mV Analog supply voltage Resistive load Resistive load Voltage on DAC_OUT output Corresponds to 12-bit input code (0x0E0) to (0xF1C) at VDDA = 3.6 V and (0x155) and (0xEAB) at VDDA = 2.4 V DAC output buffer ON. DAC output buffer OFF 144/173 DocID026415 Rev 5 STM32F303xD STM32F303xE Electrical characteristics Table 86. DAC characteristics (continued) Symbol Parameter IREF DAC DC current consumption in quiescent mode (Standby mode) IDDA(3) DAC DC current consumption in quiescent mode (Standby mode)(2) Conditions Min Typ Max Unit With no load, worst code (0xF1C) on the input - - 220 A With no load, middle code (0x800) on the input. - - 380 A With no load, worst code (0xF1C) on the input. - - 480 A Given for a 10-bit input code - - 0.5 LSB DNL(3) Differential non linearity Difference between two consecutive code-1LSB) Given for a 12-bit input code - - 2 LSB - - 1 LSB INL(3) Integral non linearity Given for a 10-bit input code (difference between measured value at Code i and the value at Code i on a Given for a 12-bit input code line drawn between Code 0 and last Code 4095) - - 4 LSB - - 10 mV Offset(3) Offset error (difference Given for a 10-bit input code between measured value at at VDDA = 3.6 V Code (0x800) and the ideal value = VDDA/2) Given for a 12-bit input code at VDDA = 3.6 V - - 3 LSB - - 12 LSB Gain error(3) Gain error - - 0.5 % tSETTLING(3) Settling time (full scale: for a 12-bit input code transition between the lowest and the CLOAD 50 pF, highest input codes when RLOAD 5 k DAC_OUT reaches final value 1LSB - 3 4 s Given for a 12-bit input code Power-up time tSTAB - conver sion cycle 1 Max frequency for a correct CLOAD 50 pF, DAC_OUT change when small variation in the input RLOAD 5 k code (from code i to i+1LSB) - - 1 MS/s tWAKEUP(3) Wakeup time from off state (Setting the ENx bit in the DAC Control register) - 6.5 10 s PSRR+ (1) Power supply rejection ratio C LOAD = 50 pF, (to VDDA) (static DC No RLOAD 5 k, measurement - -67 -40 dB 100 - - A (3) Update rate Iskink(1) Output sink current CLOAD 50 pF, RLOAD 5 k DAC buffer ON Output level higher than 0.2 V 1. Guaranteed by design, not tested in production. DocID026415 Rev 5 145/173 151 Electrical characteristics STM32F303xD STM32F303xE 2. Quiescent mode refers to the state of the DAC a keeping steady value on the output, so no dynamic consumption is involved. 3. Data based on characterization results, not tested in production. Figure 52. 12-bit buffered /non-buffered DAC %XIIHUHGQRQEXIIHUHG'$& %XIIHU 5/2$' ELW GLJLWDOWR DQDORJ FRQYHUWHU '$&[B287 &/2$' DLG 1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register. 6.3.21 Comparator characteristics Table 87. Comparator characteristics(1) Symbol Conditions Min. Typ. Max. Analog supply voltage - 2 - 3.6 VIN Comparator input voltage range - 0 - VDDA VBG Scaler input voltage - - VREFINIT - VSC Scaler offset voltage - - 5 10 mV tS_SC Scaler startup time from power down - - - 0.2 ms tSTART Comparator startup time VDDA 2.7 V - - 4 VDDA < 2.7 V - - 10 Propagation delay for 200 mV step with 100 mV overdrive VDDA 2.7 V - 25 28 - 28 30 Propagation delay for full range step with 100 mV overdrive VDDA 2.7 V - 32 35 - 35 40 - 5 10 - - 25 VDDA Parameter 146/173 V s ns tD VOFFSET VDDA < 2.7 V Unit Comparator offset error VDDA < 2.7 V VDDA 2.7 V VDDA < 2.7 V DocID026415 Rev 5 mV STM32F303xD STM32F303xE Electrical characteristics Table 87. Comparator characteristics(1) (continued) Symbol TVOFFSET IDDA Parameter Total offset variation Conditions Full temperature range COMP current consumption - Min. Typ. Max. Unit - - 3 mV - 400 600 A 1. Guaranteed by design, not tested in production. DocID026415 Rev 5 147/173 151 Electrical characteristics 6.3.22 STM32F303xD STM32F303xE Operational amplifier characteristics Table 88. Operational amplifier characteristics(1) Symbol Parameter Condition Min Typ Max Unit VDDA Analog supply voltage - 2.4 - 3.6 V CMIR Common mode input range - 0 - VDDA V 25C, No Load on output. - - 4 All voltage/Temp. - - 6 25C, No Load on output. - - 1.6 All voltage/Temp. - - 3 Maximum calibration range VIOFFSET Input offset voltage After offset calibration VIOFFSET mV Input offset voltage drift - - 5 - V/C ILOAD Drive current - - - 500 A IDDA OPAMP consumption No load, quiescent mode - 690 1450 A ADC sampling time when reading the OPAMP output. - 400 - - ns CMRR Common mode rejection ratio - - 90 - dB PSRR Power supply rejection ratio 73 117 - dB GBW Bandwidth - - 8.2 - MHz SR Slew rate - - 4.7 - V/s RLOAD Resistive load - 4 - - k CLOAD Capacitive load - - - 50 pF Rload = min, Input at VDDA. VDDA-100 - - Rload = 20K, Input at VDDA. VDDA-20 - - TS_OPAMP_VOUT VOHSAT VOLSAT m tOFFTRIM tWAKEUP 148/173 High saturation voltage(2) Low saturation voltage(2) DC mV Rload = min, input at 0V - - 100 Rload = 20K, input at 0V. - - 20 Phase margin - - 62 - Offset trim time: during calibration, minimum time needed between two steps to have 1 mV accuracy - - - 2 ms - 2.8 5 s Wake up time from OFF state. CLOAD 50 pf, RLOAD 4 k, Follower configuration DocID026415 Rev 5 STM32F303xD STM32F303xE Electrical characteristics Table 88. Operational amplifier characteristics(1) (continued) Symbol PGA gain Rnetwork Parameter Condition Min Typ Max Unit - 2 - - - 4 - - - 8 - - - 16 - - Gain=2 - 5.4/5.4 - R2/R1 internal resistance values in Gain=4 PGA mode (3) Gain=8 - 16.2/5.4 - - 37.8/5.4 - - 40.5/2.7 - Non inverting gain value - Gain=16 PGA gain error Ibias PGA BW en k PGA gain error - -1% - 1% - OPAMP input bias current - - - 0.2(4) A PGA Gain = 2, Cload = 50pF, Rload = 4 K - 4 - PGA Gain = 4, Cload = 50pF, Rload = 4 K - 2 - PGA Gain = 8, Cload = 50pF, Rload = 4 K - 1 - PGA Gain = 16, Cload = 50pF, Rload = 4 K - 0.5 - @ 1KHz, Output loaded with 4 K - 109 - PGA bandwidth for different non inverting gain Voltage noise density @ 10KHz, Output loaded with 4 K MHz - 43 - nV ----------Hz 1. Guaranteed by design, not tested in production. 2. The saturation voltage can be also limited by the Iload (drive current). 3. R2 is the internal resistance between OPAMP output and OPAMP inverting input. R1 is the internal resistance between OPAMP inverting input and ground. The PGA gain =1+R2/R1 4. Mostly TTa I/O leakage, when used in analog mode. DocID026415 Rev 5 149/173 151 Electrical characteristics STM32F303xD STM32F303xE Figure 53. OPAMP voltage noise versus frequency 6.3.23 Temperature sensor characteristics Table 89. TS characteristics Symbol TL(1) Avg_Slope(1) V25 tSTART(1) TS_temp(1)(2) Parameter Min Typ Max Unit - 1 2 C Average slope 4.0 4.3 4.6 mV/C Voltage at 25 C 1.34 1.43 1.52 V 4 - 10 s 2.2 - - s VSENSE linearity with temperature Startup time ADC sampling time when reading the temperature 1. Guaranteed by design, not tested in production. 2. Shortest sampling time can be determined in the application by multiple iterations. Table 90. Temperature sensor calibration values Calibration value name 150/173 Description Memory address TS_CAL1 TS ADC raw data acquired at temperature of 30 C, VDDA= 3.3 V 0x1FFF F7B8 - 0x1FFF F7B9 TS_CAL2 TS ADC raw data acquired at temperature of 110 C VDDA= 3.3 V 0x1FFF F7C2 - 0x1FFF F7C3 DocID026415 Rev 5 STM32F303xD STM32F303xE 6.3.24 Electrical characteristics VBAT monitoring characteristics Table 91. VBAT monitoring characteristics Symbol Parameter Min Typ Max Unit R Resistor bridge for VBAT - 50 - K Q Ratio on VBAT measurement - 2 - - Error on Q -1 - +1 % ADC sampling time when reading the VBAT 1mV accuracy 2.2 - - s Er (1) TS_vbat(1)(2) 1. Guaranteed by design, not tested in production. 2. Shortest sampling time can be determined in the application by multiple iterations. DocID026415 Rev 5 151/173 151 Package information STM32F303xD STM32F303xE 7 Package information 7.1 Package mechanical data To meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. 7.2 LQFP144 package information LQFP144 is a 144-pin, 20 x 20 mm low-profile quad flat package. Figure 54. LQFP144 package outline C ! ! ! 3%!4).' 0,!.% # MM CCC # $ , $ + ! '!5'% 0,!.% , $ % % % B 0). )$%.4)&)#!4)/. E !?-%?6 1. Drawing is not to scale. 152/173 DocID026415 Rev 5 STM32F303xD STM32F303xE Package information Table 92. LQFP144 mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 21.800 22.000 22.200 0.8583 0.8661 0.8740 D1 19.800 20.000 20.200 0.7795 0.7874 0.7953 D3 - 17.500 - - 0.6890 - E 21.800 22.000 22.200 0.8583 0.8661 0.8740 E1 19.800 20.000 20.200 0.7795 0.7874 0.7953 E3 - 17.500 - - 0.6890 - e - 0.500 - - 0.0197 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0 3.5 7 0 3.5 7 ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. DocID026415 Rev 5 153/173 171 Package information STM32F303xD STM32F303xE Figure 55. Recommended footprint for the LQFP144 package DLH 1. Drawing is not to scale. 2. Dimensions are expressed in millimeters. 154/173 DocID026415 Rev 5 STM32F303xD STM32F303xE Package information Device marking for LQFP144 The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 56. LQFP144 marking example (package top view) 5HYLVLRQFRGH 3URGXFWLGHQWLILFDWLRQ 5 670) =(7 'DWHFRGH < :: 3LQLGHQWLILFDWLRQ D^s 1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity. DocID026415 Rev 5 155/173 171 Package information 7.3 STM32F303xD STM32F303xE UFBGA100 package information UFBGA100 is a 100-ball, 7 x 7 mm, 0.50 mm pitch, ultra fine pitch ball grid array package. Figure 57. UFBGA100 package outline = 6HDWLQJSODQH GGG = $ $ $ $ $ ( H $EDOO $EDOO LGHQWLILHU LQGH[DUHD ) ; ( $ ) ' ' H < 0 %277209,(: E EDOOV HHH 0 = < ; III 0 = 7239,(: $&B0(B9 1. Drawing is not to scale. Table 93. UFBGA100 package mechanical data inches(1) millimeters Symbol 156/173 Min. Typ. Max. Min. Typ. Max. A 0.460 0.530 0.600 0.0181 0.0209 0.0236 A1 0.050 0.080 0.110 0.0020 0.0031 0.0043 A2 0.400 0.450 0.500 0.0157 0.0177 0.0197 A3 - 0.130 - - 0.0051 - A4 0.270 0.320 0.370 0.0106 0.0126 0.0146 b 0.200 0.250 0.300 0.0079 0.0098 0.0118 D 6.950 7.000 7.050 0.2736 0.2756 0.2776 D1 5.450 5.500 5.550 0.2146 0.2165 0.2185 E 6.950 7.000 7.050 0.2736 0.2756 0.2776 E1 5.450 5.500 5.550 0.2146 0.2165 0.2185 e - 0.500 - - 0.0197 - F 0.700 0.750 0.800 0.0276 0.0295 0.0315 DocID026415 Rev 5 STM32F303xD STM32F303xE Package information Table 93. UFBGA100 package mechanical data (continued) inches(1) millimeters Symbol Min. Typ. Max. Min. Typ. Max. ddd - - 0.100 - - 0.0039 eee - - 0.150 - - 0.0059 fff - - 0.050 - - 0.0020 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 58. Recommended footprint for the UFBGA100 package 'SDG 'VP 069 Table 94. UFBGA100 recommended PCB design rules (0.5 mm pitch BGA) Dimension Recommended values Pitch 0.5 Dpad 0.27 mm Dsm 0.35 mm typ. (depends on the soldermask registration tolerance) Solder paste 0.27 mm aperture diameter. Note: Non-solder mask defined (NSMD) pads are recommended. Note: 4 to 6 mils solder paste screen printing process. DocID026415 Rev 5 157/173 171 Package information STM32F303xD STM32F303xE Device marking for UFBGA100 The following figure gives an example of topside marking orientation versus ball A1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 59. UFBGA100 marking example (package top view) 3URGXFW LGHQWLILFDWLRQ 45.' 7&) 'DWHFRGH : 88 6WDQGDUG67ORJR 5HYLVLRQFRGH %DOOLGHQWLILHU 3 069 1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity. 158/173 DocID026415 Rev 5 STM32F303xD STM32F303xE LQFP100 package information LQFP100 is a 100-pin, 14 x 14 mm low-profile quad flat package. Figure 60. LQFP100 package outline MM C ! ! 3%!4).' 0,!.% # ! '!5'% 0,!.% $ ! + CCC # , $ , $ 0). )$%.4)&)#!4)/. % % % B 7.4 Package information E ,?-%?6 1. Drawing is not to scale. Table 95. LQPF100 package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D 15.800 16.000 16.200 0.6220 0.6299 0.6378 DocID026415 Rev 5 159/173 171 Package information STM32F303xD STM32F303xE Table 95. LQPF100 package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max D1 13.800 14.000 14.200 0.5433 0.5512 0.5591 D3 - 12.000 - - 0.4724 - E 15.800 16.000 16.200 0.6220 0.6299 0.6378 E1 13.800 14.000 14.200 0.5433 0.5512 0.5591 E3 - 12.000 - - 0.4724 - e - 0.500 - - 0.0197 - L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - k 0.0 3.5 7.0 0.0 3.5 7.0 ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 61. Recommended footprint for the LQFP100 package AIC 1. Drawing is not to scale. 2. Dimensions are expressed in millimeters. 160/173 DocID026415 Rev 5 STM32F303xD STM32F303xE Package information Device marking for LQFP100 The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 62. LQFP100 marking example (package top view) 3URGXFWLGHQWLILFDWLRQ 670) 9(7 5HYLVLRQFRGH 5 'DWHFRGH < :: 3LQLGHQWLILFDWLRQ 06Y9 1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity. DocID026415 Rev 5 161/173 171 Package information 7.5 STM32F303xD STM32F303xE WLCSP100 package information WLCSP100 is a 100-ball, 4.775 x 5.041 mm, 0.4 mm pitch wafer level chip scale package. Figure 63.WLCSP100 package outline $%$///2&$7,21 $ '(7$,/$ . %277209,(: 6,'(9,(: )52179,(: '(7$,/$ 527$7(' $25,(17$7,21 5()(5(1&( DDD ; 7239,(: :$)(5%$&.6,'( 1. Drawing is not to scale. 162/173 DocID026415 Rev 5 :/&63B$5B0(B9 STM32F303xD STM32F303xE Package information Table 96. WLCSP100 package mechanical data inches(1) millimeters Symbol Min Typ Max Typ Min Max A 0.525 0.555 0.585 0.0207 0.0219 0.0230 A1 - 0.175 - - 0.0069 - A2 - 0.38 - - 0.0150 - (2) - 0.025 - - 0.0010 - (3) Ob 0.22 0.25 0.28 - 0.0098 0.0110 D 4.74 4.775 4.81 - 0.1880 0.1894 E 5.006 5.041 5.076 - 0.1985 0.1998 e - 0.4 - - 0.0157 - e1 - 3.6 - - 0.1417 - e2 - 3.6 - - 0.1417 - F - 0.5875 - - 0.0231 - G - 0.7205 - - 0.0284 - N - 100 - - 3.9370 - aaa - 0.1 - - 0.0039 - bbb - 0.1 - - 0.0039 - ccc - 0.1 - - 0.0039 - ddd - 0.05 - - 0.0020 - eee - 0.05 - - 0.0020 - A3 1. Values in inches are converted from mm and rounded to 4 decimal digits. 2. Back side coating. 3. Dimension is measured at the maximum bump diameter parallel to primary datum Z. Figure 64. Recommended footprint for the WLCSP100 package 'SDG 'VP :/&63B$5B)3B9 DocID026415 Rev 5 163/173 171 Package information STM32F303xD STM32F303xE Table 97. WLCSP100 recommended PCB design rules (0.4 mm pitch) Dimension Recommended values Pitch 0.4 mm Dpad 0.225 mm Dsm 0.290 mm Stencil thickness 0.1 mm Device marking for WLCSP100 The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 65. WLCSP100 marking example (package top view) %DOO$LGHQWLILHU 3URGXFWLGHQWLILFDWLRQ (6)9(< ZZZ < :: 5 06Y9 1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity. 164/173 DocID026415 Rev 5 STM32F303xD STM32F303xE LQFP64 package information LQFP64 is a 64-pin, 10 x 10 mm low-profile quad flat package. Figure 66. LQFP64 package outline PP *$8*(3/$1( F $ $ 6($7,1*3/$1( & $ $ FFF & ' ' ' . / / ( ( E ( 7.6 Package information 3,1 ,'(17,),&$7,21 H :B0(B9 1. Drawing is not to scale. Table 98. LQFP64 package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D - 12.000 - - 0.4724 - D1 - 10.000 - - 0.3937 - D3 - 7.500 - - 0.2953 - E - 12.000 - - 0.4724 - E1 - 10.000 - - 0.3937 - DocID026415 Rev 5 165/173 171 Package information STM32F303xD STM32F303xE Table 98. LQFP64 package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Min Typ Max E3 - 7.500 - - 0.2953 - e - 0.500 - - 0.0197 - 0 3.5 7 0 3.5 7 L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 67. Recommended footprint for the LQFP64 package AIC 1. Dimensions are expressed in millimeters. 166/173 DocID026415 Rev 5 STM32F303xD STM32F303xE Package information Device marking for LQFP64 The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 68. LQFP64 marking example (package top view) 5HYLVLRQFRGH 5 3URGXFWLGHQWLILFDWLRQ 670) 5(7 'DWHFRGH z tt 3LQLGHQWLILHU 06Y9 1. Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet qualified and therefore not yet ready to be used in production and any consequences deriving from such usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering samples in production. ST Quality has to be contacted prior to any decision to use these Engineering samples to run qualification activity. DocID026415 Rev 5 167/173 171 Package information 7.7 STM32F303xD STM32F303xE Thermal characteristics The maximum chip junction temperature (TJmax) must never exceed the values given in Table 19: General operating conditions. The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated using the following equation: TJ max = TA max + (PD max x JA) Where: * TA max is the maximum temperature in C, * JA is the package junction-to- thermal resistance, in C/W, * PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax), * PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power. PI/O max represents the maximum power dissipation on output pins where: PI/O max = (VOL x IOL) + ((VDD - VOH) x IOH), taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application. Table 99. Package thermal characteristics Symbol JA 7.7.1 Parameter Value Thermal resistance junctionLQFP144 - 20 x 20 mm 33 Thermal resistance junctionUFBGA100 - 7 x 7 mm 59 Thermal resistance junctionLQFP100 - 14 x 14 mm 42 Thermal resistance junctionWLCSP100 - 0.4 mm pitch 44 Thermal resistance junctionLQFP64 - 10 x 10 mm / 0.5 mm pitch 46 Unit C/W Reference document JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air). Available from www.jedec.org 7.7.2 Selecting the product temperature range When ordering the microcontroller, the temperature range is specified in the ordering information scheme shown in Section 8: Part numbering. Each temperature range suffix corresponds to a specific guaranteed temperature at maximum dissipation and to a specific maximum junction temperature. As applications do not commonly use the STM32F303xD/E at maximum dissipation, it is useful to calculate the exact power consumption and junction temperature to determine which temperature range is best suited to the application. 168/173 DocID026415 Rev 5 STM32F303xD STM32F303xE Package information The following examples show how to calculate the temperature range needed for a given application. Example 1: High-performance application Assuming the following application conditions: Maximum temperature TAmax = 82 C (measured according to JESD51-2), IDDmax = 50 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low level with IOL = 8 mA, VOL= 0.4 V and maximum 8 I/Os used at the same time in output at low level with IOL = 20 mA, VOL= 1.3 V PINTmax = 50 mA x 3.5 V= 175 mW PIOmax = 20 x 8 mA x 0.4 V + 8 x 20 mA x 1.3 V = 272 mW This gives: PINTmax = 175 mW and PIOmax = 272 mW: PDmax = 175 + 272 = 447 mW Using the values obtained in Table 99 TJmax is calculated as follows: - For LQFP100, 42 C/W TJmax = 82 C + (42 C/W x 447 mW) = 82 C + 18.774 C = 100.774 C This is within the range of the suffix 6 version parts (-40 < TJ < 105 C). In this case, parts must be ordered at least with the temperature range suffix 6 (see Section 8: Part numbering). Note: With this given PDmax we can find the TAmax allowed for a given device temperature range (order code suffix 6 or 7). Suffix 6: TAmax = TJmax - (42C/W x 447 mW) = 105-18.774 = 86.226 C Suffix 7: TAmax = TJmax - (42C/W x 447 mW) = 125-18.774 = 106.226 C Example 2: High-temperature application Using the same rules, it is possible to address applications that run at high temperature with a low dissipation, as long as junction temperature TJ remains within the specified range. Assuming the following application conditions: Maximum temperature TAmax = 100 C (measured according to JESD51-2), IDDmax = 20 mA, VDD = 3.5 V, maximum 20 I/Os used at the same time in output at low level with IOL = 8 mA, VOL= 0.4 V PINTmax = 20 mA x 3.5 V= 70 mW PIOmax = 20 x 8 mA x 0.4 V = 64 mW This gives: PINTmax = 70 mW and PIOmax = 64 mW: PDmax = 70 + 64 = 134 mW Thus: PDmax = 134 mW Using the values obtained in Table 99 TJmax is calculated as follows: - For LQFP100, 42 C/W TJmax = 100 C + (42 C/W x 134 mW) = 100 C + 5.628 C = 105.628 C This is above the range of the suffix 6 version parts (-40 < TJ < 105 C). In this case, parts must be ordered at least with the temperature range suffix 7 (see Section 8: Part numbering) unless we reduce the power dissipation to be able to use suffix 6 parts. DocID026415 Rev 5 169/173 171 Package information STM32F303xD STM32F303xE Refer to Figure 69 to select the required temperature range (suffix 6 or 7) according to your temperature or power requirements. Figure 69. LQFP100 PD max vs. TA 3' P: 6XIIL[ 6XIIL[ 7$ & 170/173 DocID026415 Rev 5 06Y9 STM32F303xD STM32F303xE 8 Part numbering Part numbering For a list of available options (memory, package, and so on) or for further information on any aspect of this device, contact the nearest ST sales office. Table 100. Ordering information scheme Example: STM32 F 303 V E T 6 x Device family STM32 = ARM-based 32-bit microcontroller Product type F = General-purpose Sub-family 303 = STM32F303xx Pin count R = 64 pins V = 100 pins Z = 144 pins Code size D = 384 Kbytes of Flash memory E = 512 Kbytes of Flash memory Package H = UFBGA T = LQFP Y = WLCSP Temperature range 6 = -40 to 85 C 7 = -40 to 105 C Options xxx = programmed parts TR = tape and reel DocID026415 Rev 5 171/173 171 Revision history 9 STM32F303xD STM32F303xE Revision history Table 101. Document revision history Date Revision 20-Jan-2015 1 Initial release. 2 Updated: - Table 13: STM32F303xD/E pin definitions - Table 14: STM32F303xD/E alternate function mapping - Table 38: HSE oscillator characteristics - Figure 56: LQFP144 marking example (package top view) - Figure 62: LQFP100 marking example (package top view) 3 Added USB_DM and USB_DP as additional function to PA11 and PA12 description, respectively in Table 13: STM32F303xD/E pin definitions. Updated: - Figure 56: LQFP144 marking example (package top view), - Figure 59: UFBGA100 marking example (package top view), - Figure 62: LQFP100 marking example (package top view). 4 Renamed: - FMC as FSMC, - CCM RAM as CCM SRAM. Removed: - table: I2C timings specification and Figure: I2C bus AC waveforms and measurement circuit in Section : I2C interface characteristics. - Added package information for WLCSP100 in Section 7: Package information. 5 Updated: Table 2: STM32F303xD/E family device features and peripheral counts, Section 3.17: Ultra-fast comparators (COMP), Table 66: DAC characteristics, Table 61: ADC characteristics, Table 13: STM32F303xD/E pin definitions, Table 14: STM32F303xD/E alternate function mapping, Figure 41: Recommended NRST pin protection Added: Table 37: Wakeup time using USART. 30-Jan-2015 03-Mar-2015 08-Dec-2015 21-Oct-2016 172/173 Changes DocID026415 Rev 5 STM32F303xD STM32F303xE IMPORTANT NOTICE - PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST's terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers' products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. (c) 2016 STMicroelectronics - All rights reserved DocID026415 Rev 5 173/173 173