DS04-27248-1Ea
FUJITSU MICROELECTRONICS
DATA SHEET
Copyright©2005-2008 FUJITSU MICROELECTRONICS LIMITED Al l rights reserv ed
2005.11
ASSP f or P ower Supply Applications (Secondary battery)
DC/DC Converter IC for Charging
Li-ion Batter y
MB39A125/126
■DESCRIPTION
MB39A125/1 26 is a DC/D C conver ter IC for charging Li-ion battery, which is suitable for down-conversion, and
uses pulse width modulation (PWM) for controlling the output voltage and current independently . This IC integrates
the build-in comparator for the voltage detection of the AC adapter, and selects the AC adapter or batter y auto-
matically for power supply to the system.
Provides a wide range of p ower supply voltage, lo w standb y current, and high efficiency, which mak es them ideal
as a b uilt-in charging device in products such as notebook PC.
■FEATURES
• High efficiency : 97% (MAX)
• Built-in two const an t curre n t c ontr ol circ uits
• Analog contr ol of th e ch ar gin g cu rr en t value (+INE1, +INE2 te rminal)
• Built-in AC adapter voltage detection function (ACOK, XACOK terminal) (Continued)
■PACKAGES
24-pin plas ti c SSOP 28-pin plas tic QFN
(FPT-24P-M03) (LCC-28P-M11)
MB39A125/126
2
(Continued)
• External output voltage setting resist or : MB39 A1 25
• Built-in output voltage setting resistor : MB39A126
• Built-in charge stop function at low VCC
• Output voltage setting accuracy : ± 0.74% (Ta = −10 °C to +85 °C) : MB39A125
: 12.6 V/16.8 V ± 0.8% (Ta = −10 °C to +85 °C) : MB39A126
• Built-in high accuracy current detection amplifier (±5%) (At input voltage difference 100 mV) ,
(±15%) (At input voltage dif ference 20 mV)
• In IC standby mode (Icc = 0 µA Typ) , make output voltage setting resistor open to prevent inefficient current loss
• Built-in soft-start circuit
• Standby current : 0 µA (Typ)
• Totem-pole type output for Pch MOS FET
MB39A125/126
3
■PIN ASSIGNMENTS
• MB39A125
(Continued)
(TOP VIEW)
(FPT-24P-M03)
−INC2 1 24 +INC2
OUTC2 2 23 GND
+INE2 3 22 CS
−INE2 4 21 VCC
ACOK 5 20 OUT
VREF 6 19 VH
ACIN 7 18 XACOK
−INE1 8 17 RT
+INE1 9 16 −INE3
OUTC1 1015 FB123
OUTD 11 14 CTL
−INC1 1213 +INC1
MB39A125/126
4
(Continued)
(TOP VIEW)
(LCC-28P-M11)
Note : Connect IC’s radiation board at bottom side to potential of GND.
CS
VCC
OUT
VH
XACOK
RT
−INE3
28 27 26 25 24 23 22
N.C. 1 21 FB123
GND 2 20 CTL
+INC2 3 19 +INC1
N.C. 4 18 N.C.
−INC2 5 17 −INC1
OUTC2 6 16 OUTD
+INE2 715
N.C.
8 9 10 11 12 13 14
−INE2
ACOK
VREF
ACIN
−INE1
+INE1
OUTC1
MB39A125/126
5
• MB39A126
(Continued)
(TOP VIEW)
(FPT-24P-M03)
−INC2 124+INC2
OUTC2 223GND
+INE2 322CS
−INE2 421VCC
ACOK 520OUT
VREF 619VH
ACIN 718XACOK
−INE1 817RT
+INE1 916−INE3
OUTC1 10 15 FB123
SEL 11 14 CTL
−INC1 12 13 +INC1
MB39A125/126
6
(Continued)
(TOP VIEW)
(LCC-28P-M11)
Note : Connect IC’s radiation board at bottom side to potential of GND.
CS
VCC
OUT
VH
XACOK
RT
−
INE3
28 27 26 25 24 23 22
N.C.
121
FB123
GND 220
CTL
+
INC2 319
+
INC1
N.C.
418
N.C.
−
INC2 517
−
INC1
OUTC2 616
SEL
+
INE2 715
N.C.
8910 11 12 13 14
−
INE2
ACOK
VREF
ACIN
−
INE1
+
INE1
OUTC1
MB39A125/126
7
■PIN DESCRIPTIONS
• MB39A125 : SSOP-24
Pin No. Pin Name I/O Description
1−INC2 I Current detection amplifier (Current Amp2) inverted input terminal
2 OUTC2 O Current detection amplifier (Current Amp2) output te rminal
3+INE2 I Error amplifier (Error Amp2) non-inverted input terminal
4−INE2 I Error amplifier (Error Amp2) inverted input terminal
5ACOKO
AC adapter voltage detection block (AC Comp.) output terminal
ACOK = L when ACIN = H, ACOK = Hi-Z when ACIN = L,
ACOK = Hi-Z when CTL = L
6 VREF O Reference voltage output terminal
7 ACIN I AC adapter voltage detection block (AC Comp.) input terminal
8−INE1 I Error amplifier (Error Amp1) inverted input terminal
9+INE1 I Error amplifier (Error Amp1) non-inverted input terminal
10 OUTC1 O Current detection amplifier (Current Amp1) output terminal
11 OUTD O When IC is standby mod e , this term in al is set to “Hi-Z” to prevent loss
of inefficient current through the output voltage setting resistor.
Set CTL terminal to “H” level to output “L” level.
12 −INC1 I Current detection amplifier (Current Amp1) inverted input terminal
13 +INC1 I Current detection amplifier (Current Amp1) non-inverted input terminal
14 CTL I Power supply control terminal
Setting the CTL term inal at “L” level places the IC in the sta ndby
mode.
15 FB123 O Error amplifier (Error Amp1, 2, 3) output terminal
16 −INE3 I Error amplifier (Error Amp3) inverted input terminal
17 RT ⎯Triangular wave oscillation frequency setting resistor connection terminal
18 XACOK O AC adapter voltage detection block ( AC Comp.) output terminal
XACOK = Hi-Z when ACIN = H, XACOK = L when ACIN = L,
XACOK = Hi-Z when CTL = L
19 VH O Power supply terminal for FET drive circuit (VH = VCC − 6 V)
20 OUT O Extern al F ET ga te drive terminal
21 VCC ⎯Power supply terminal for reference voltage, control circuit, and output cir-
cuit
22 CS ⎯S oft -s tar t set tin g ca pa cito r co nn e ctio n te rm ina l
23 GND ⎯Ground terminal
24 +INC2 I Current detection amplifier (Current Amp2) non-inverted input terminal
MB39A125/126
8
• MB39A125 : QFN-28
Pin No. Pin Name I/O Description
1N.C.⎯No connectio n
2GND⎯Ground terminal
3+INC2 I Current detection amplifier (Current Amp2) non-inverted input ter minal
4N.C.⎯No connectio n
5−INC2 I Current detection amplifier (Current Amp2) inverted input terminal
6 OUTC2 O Current detection amplifier (Current Amp2) output te rminal
7+INE2 I Error amplifier (Error Amp2) non-inverted input terminal
8−INE2 I Error amplifier (Error Amp2) inverted input terminal
9ACOKO
AC adapter voltage detection block (AC Comp.) output terminal
ACOK = L when ACIN = H, ACOK = Hi-Z when ACIN = L,
ACOK = Hi-Z when CTL = L
10 VREF O Reference voltage output terminal
11 ACIN I AC adapter voltage detection block (AC Comp.) input terminal
12 −INE1 I Error amplifier (Error Amp1) inverted input terminal
13 +INE1 I Error amplifier (Error Amp1) non-inverted input terminal
14 OUTC1 O Current detection amplifier (Current Amp1) output terminal
15 N.C. ⎯No connectio n
16 OUTD O When IC is standby mod e , this term in al is set to “Hi-Z” to prevent loss
of inefficient current through the output voltage setting resistor.
Set CTL terminal to “H” level to output “L” level.
17 −INC1 I Current detection amplifier (Current Amp1) inverted input terminal
18 N.C. ⎯No connectio n
19 +INC1 I Current detection amplifier (Current Amp1) non-inverted input ter minal
20 CTL I Power supply control terminal
Setting the CTL term inal at “L” level places the IC in the sta ndby
mode.
21 FB123 O Error amplifier (Error Amp1, 2, 3) output terminal
22 −INE3 I Error amplifier (Error Amp3) inverted input terminal
23 RT ⎯Triangular wave oscillation frequency setting resistor connection terminal
24 XACOK O AC adapter voltage detection block ( AC Comp.) output terminal
XACOK = Hi-Z when ACIN = H, XACOK = L when ACIN = L,
XACOK = Hi-Z when CTL = L
25 VH O Power supply terminal for FET drive circuit (VH = VCC - 6 V)
26 OUT O Extern al F ET ga te drive terminal
27 VCC ⎯Power supply terminal for reference voltage, control circuit, and output cir-
cuit
28 CS ⎯S oft -s tar t set tin g ca pa cito r co nn e ctio n te rm ina l
MB39A125/126
9
• MB39A126 : SSOP-24
Pin No. Pin Name I/O Description
1−INC2 I Current detection amplifier (Current Amp2) inverted input terminal
2 OUTC2 O Current detection amplifier (Current Amp2) output te rminal
3+INE2 I Error amplifier (Error Amp2) non-inverted input terminal
4−INE2 I Error amplifier (Error Amp2) inverted input terminal
5ACOKO
AC adapter voltage detection block (AC Comp.) output terminal
ACOK = L when ACIN = H, ACOK = Hi-Z when ACIN = L,
ACOK = Hi-Z when CTL = L
6 VREF O Reference voltage output terminal
7 ACIN I AC adapter voltage detection block (AC Comp.) input terminal
8−INE1 I Error amplifier (Error Amp1) inverted input terminal
9+INE1 I Error amplifier (Error Amp1) non-inverted input terminal
10 OUTC1 O Current detection amplifier (Current Amp1) output terminal
11 SEL I Charge voltage setting switch terminal (3cells or 4cells)
SEL terminal “H” level : Charge voltage setting 16.8 V (4ce lls)
SEL terminal “L” level : Charge voltage set ting 12.6 V (3cells)
12 −INC1 I Current detection amplifier (Current Amp1) inverted input terminal
13 +INC1 I Current detection amplifier (Current Amp1) non-inverted input ter minal
14 CTL I Power supply control terminal
Setting the CTL term inal at “L” level places the IC in the standby mode.
15 FB123 O Error amplifier (Error Amp1, 2, 3) output terminal
16 −INE3 I Error amplifier (Error Amp3) inverted input terminal
17 RT ⎯Triangular wave oscillation frequency setting resistor connection terminal
18 XACOK O AC adapter voltage detection block ( AC Comp.) output terminal
XACOK = Hi-Z when ACIN = H, XACOK = L when ACIN = L,
XACOK = Hi-Z when CTL = L
19 VH O Power supply terminal for FET drive circuit (VH = VCC - 6 V)
20 OUT O Extern al F ET ga te drive terminal
21 VCC ⎯Power supply terminal for reference voltage, control circuit, and output cir-
cuit
22 CS ⎯S oft -s tar t set tin g ca pa cito r co nn e ctio n te rm ina l
23 GND ⎯Ground terminal
24 +INC2 I Current detection amplifier (Current Amp2) non-inverted input ter minal
MB39A125/126
10
• MB39A126 : QFN-28
Pin No. Pin Name I/O Description
1N.C.⎯No connection
2GND⎯Ground terminal
3+INC2 I Current detection amplifier (Current Amp2) non-inverted input terminal
4N.C.⎯No connection
5−INC2 I Current detection amplifier (Current Amp2) inverted input terminal
6 OUTC2 O Current detection amplifier (Current Amp2) output terminal
7+INE2 I Error amplifier (Error Amp2) non-inverted input terminal
8−INE2 I Error amplifier (Error Amp2) inverted input termina l
9ACOKO
AC adapter voltage detection block (AC Comp.) output terminal
ACOK = L when ACIN = H, ACOK = Hi-Z when ACIN = L,
ACOK = Hi-Z when CTL = L
10 VREF O Reference voltage output terminal
11 ACIN I AC adapter voltage detection block (AC Comp.) input terminal
12 −INE1 I Error amplifier (Error Amp1) inverted input termina l
13 +INE1 I Error amplifier (Error Amp1) non-inverted input terminal
14 OUTC1 O Current detection amplifier (Current Amp1) output termin al
15 N.C. ⎯No connection
16 SEL I Charge voltage setting switch terminal (3cells or 4cells) .
SEL terminal “H” level : Charge voltage setting 16.8 V (4ce lls)
SEL terminal “L” level : Charge voltage setting 12.6 V (3cells)
17 −INC1 I Current detection amplifier (Current Amp1) inverted input terminal
18 N.C. ⎯No connection
19 +INC1 I Current detection amplifier (Current Amp1) non-inverted input terminal
20 CTL I Power supply control terminal
Setting the CTL terminal at “L” level places the IC in the standby
mode.
21 FB123 O Error amplifier (Error Amp1, 2, 3) output t erminal
22 −INE3 I Error amplifier (Error Amp3) inverted input termina l
23 RT ⎯Triangular wave oscillation frequency setting resistor connection terminal
24 XACOK O AC adapter voltage detection block ( AC Comp.) output terminal
XACOK = Hi-Z when ACIN = H, XACOK = L when ACIN = L,
XACOK = Hi-Z when CTL = L
25 VH O Power supply terminal for FET drive circuit (VH = VCC - 6 V)
26 OUT O Extern al FET gate drive terminal
27 VCC ⎯Power supply terminal for reference voltage, control circuit, and output cir-
cuit
28 CS ⎯Soft-start setting capacitor connection terminal
MB39A125/126
11
■BLOCK DIAGRAMS
• MB39A125
21
20
19
14
23
6
17
22
11
16
15
3
1
24
2
4
9
12
13
10
8
7518
−INE1
<Current Amp1>
<Error Amp1>
<Current Amp2> <Error Amp2>
(VCC − 6 V)
<Error Amp3>
4.2 V
< SOFT>
<OSC>
500 k
Hz Max
<REF> <CTL>
VREF
5.0 V
10 µA
C
T
(45 pF)
4.2 V
Bias
<PWM Comp.>
VREF
UVLO
Drive
Bias
Voltage
VH
−2.5 V
−1.5 V
VREF
VREF 1.4 V
<AC Comp.>
VCC
OUTC1
+INC1
−INC1
+INE1
−INE2
OUTC2
+INC2
−INC2
+INE2
FB123
−INE3
OUTD
CS
RT VREF GND
CTL
VH
OUT
VCC
ACOK
<OUT>
ACIN
<UVLO>
0.2 V <UV Comp.>
−
INC1
(Vo)
XACOK
Slope
Control
−
+
−
+
−
+
+
−
+
−
+
−
+
−
+
−
×20
×20
MB39A125/126
12
• MB39A126
−INE1
<Current Amp1>
<Error Amp1>
<Error Amp2>
<Error Amp3>
4.2 V/3.15 V
< SOFT>
<OSC>
500 k
Hz Max
<REF> <CTL>
VREF
5.0 V
10 µA
C
T
(45 pF)
4.2 V
Bias
<PWM Comp.>
VREF
UVLO
Drive
Bias
Voltage
VH
VREF
VREF 1.4 V
<AC Comp.>
VCC
OUTC1
+INC1
−INC1
+INE1
−INE2
OUTC2
+INC2
−INC2
+INE2
FB123
−INE3
SEL
CS
RT VREF GND
CTL
VH
OUT
VCC
ACOK
<OUT>
ACIN
<UVLO>
0.2 V <UV Comp.>
−INC1
(Vo)
XACOK
Slope
Control
−
+
−
+
−
+
+
−
+
−
+
−
+
−
+
−
×20
×20
R1
R2
21
20
19
14
23
6
17
22
11
16
15
3
1
24
2
4
9
12
13
10
8
7518
(VCC − 6 V)
−2.5 V
−1.5 V
<Current Amp2>
Hi : 4 Cells
Lo : 3 Cells
MB39A125/126
13
■ABSOLUTE MAXIMUM RATINGS
*1 : When mounted on a 10cm square epoxy double-sided.
*2 : The pac kages are mounte d on t he dual-si ded epoxy board (10 cm × 10 cm) . Connect IC’s radiation board at
bottom side to po te ntial of GND.
WARNING : Semiconductor devices can be permanently damaged b y application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
Parameter Symbol Condition Rating Unit
Min Max
Power supply voltage VCC VCC terminal ⎯28 V
Output current IOUT ⎯⎯60 mA
Peak output curr e nt IOUT Duty ≤ 5% (t = 1 / fosc × Duty) ⎯700 mA
Power dissipation PDTa ≤ +25 °C (SSOP-24) ⎯740*1mW
Ta ≤ +25 °C (QFN-28) ⎯3700*2mW
Storage temperature TSTG ⎯−55 +125 °C
MB39A125/126
14
■RECOMMENDED OPERATION CONDITIONS
Note : The terminal number which has been described in the text is the one of the SSOP-24P package after this .
WARNING: The recommende d operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended ope rating condition ranges. Oper ation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
representatives beforehand.
Parameter Symbol Condition Value Unit
MIN TYP MAX
Power supply voltage VCC VCC terminal 8 ⎯25 V
Reference vo ltage Output current IREF ⎯−1⎯0mA
VH terminal output current IVH ⎯0⎯30 mA
Input voltage VINE +INE, −INE terminal 0 ⎯5V
VINC +INC, −INC terminal 0 ⎯VCC V
CTL terminal input voltage VCTL ⎯0⎯25 V
Output current IOUT ⎯−45 ⎯+45 mA
Peak output curr e nt IOUT Duty ≤ 5%
(t = 1 / fosc × Duty) −600 ⎯+600 mA
ACIN terminal input Voltage VACIN ⎯0⎯VCC V
ACOK terminal output voltage VACOK ⎯0⎯25 V
ACOK terminal output current IACOK ⎯0⎯1mA
XACOK terminal output vo ltage VXACOK ⎯0⎯25 V
XACOK terminal output current IXACOK ⎯0⎯1mA
OUTD terminal output voltage :
MB39A125 VOUTD ⎯0⎯17 V
OUTD terminal output current :
MB39A125 IOUTD ⎯0⎯2mA
SEL terminal input voltage :
MB39A126 VSEL ⎯0⎯25 V
Oscillation frequency fOSC ⎯100 300 500 kHz
Timing resistor RT⎯27 47 130 kΩ
Soft-start capacitor CS⎯⎯0.22 1.0 µF
VH terminal capacitor CVH ⎯⎯0.1 1.0 µF
Reference vo ltage output capacitor CREF ⎯⎯0.22 1.0 µF
Operating ambient Temperature Ta ⎯−30 +25 +85 °C
MB39A125/126
15
■ELECTRICAL CHARACTERISTICS (VCC = 19 V, VREF = 0 mA, Ta = +25 °C)
* : Standard design value (Continued)
Parameter Sym-
bol Pin
No. Condition Value Unit Remarks
Min Typ Max
1.
Reference
voltage block
[REF]
Output voltage
VREF1 6Ta = +25 °C 4.963 5.000 5.037 V MB39A125
VREF2 6Ta = −10 °C to +85 °C 4.95 5.000 5.05 V MB39A125
VREF1 6Ta = +25 °C 4.943 4.980 5.017 V MB39A126
VREF2 6Ta = −10 °C to +85 °C 4.930 4.980 5.030 V MB39A126
Input stability Line 6 VCC = 8 V to 25 V ⎯310mV
Load stability Load 6 VREF = 0 mA t o −1 mA ⎯110mV
Output current
at short circuit Ios 6 VREF = 1 V −50 −25 −12 mA
2.
Under voltage
lockout
protection
circuit block
[UVLO]
Threshold
voltage VTLH 6VREF = 2.6 2.8 3.0 V
VTHL 6VREF = 2.4 2.6 2.8 V
Hysteresis
width VH6⎯⎯ 0.2* ⎯V
3.
Soft start block
[SOFT]
Charge
current ICS 22 ⎯−14 −10 −6µA
4.
Triangular
wave oscillator
block [OSC]
Oscillation
frequency fOSC 20 RT = 47 kΩ270 300 330 kHz
Frequency
temperature
stability ∆f/fdt 20 Ta = −30 °C to +85 °C⎯1* ⎯%
5-1.
Error amplifier
block
[Error Amp1,
Error Amp2]
Input offset
voltage VIO 3, 4,
8, 9 FB123 = 2 V ⎯15mV
Input bias
current IB3, 4,
8, 9 ⎯−100 −30 ⎯nA
Common
mode input
voltage range VCM 3, 4,
8, 9 ⎯0⎯5V
Voltage gain Av 15 DC ⎯ 100* ⎯dB
Frequency
bandwidth BW 15 AV = 0 dB ⎯ 1.3* ⎯MHz
Output voltage VFBH 15 ⎯4.8 5.0 ⎯V
VFBL 15 ⎯⎯0.8 0.9 V
Output so urce
current ISOURCE 15 FB123 = 2 V ⎯−120 −60 µA
Output sink
current ISINK 15 FB123 = 2 V 2.0 4.0 ⎯mA
MB39A125/126
16
(VCC = 19 V, VREF = 0 mA, Ta = +25 °C)
* : Standard design value (Continued)
Parameter Sym-
bol Pin
No. Condition Value Unit Remarks
Min Typ Max
5-2.
Error
amplifier
block
[Error
Amp3]
Input
current IINE 16 −INE3 = 0 V −100 −30 ⎯nA MB39A125
Voltage
gain Av 15 DC ⎯ 100* ⎯dB
Frequency
bandwidth BW 15 AV = 0 dB ⎯ 1.3* ⎯MHz
Output
voltage VFBH 15 ⎯4.8 5.0 ⎯V
VFBL 15 ⎯⎯0.8 0.9 V
Output
source
current ISOURCE 15 FB123 = 2 V ⎯−120 −60 µA
Output sink
current ISINK 15 FB123 = 2 V 2.0 4.0 ⎯mA
Threshold
voltage
VTH1 16 FB123 = 2 V,
Ta = +25 °C4.179 4.200 4.220 V MB39A125
VTH2 16 FB123 = 2 V,
Ta = −10 °C to +85 °C4.169 4.200 4.231 V MB39A125
VTH3 12 SEL = 5 V, FB123 = 2 V,
Ta = +25 °C16.700 16.800 16.900 V MB39A126
VTH4 12 SEL = 5 V, FB123 = 2 V,
Ta = −10 °C to +85 °C16.666 16.800 16.934 V MB39A126
VTH5 12 SEL = 0 V, FB123 = 2 V,
Ta = +25 °C12.525 12.600 12.675 V MB39A126
VTH6 12 SEL = 0 V, FB123 = 2 V,
Ta = −10 °C to +85 °C12.500 12.600 12.700 V MB39A126
OUTD
terminal
output leak
current
ILEAK 11 OUTD = 17 V ⎯01µA MB39A125
OUTD
terminal
output ON
resistance
RON 11 OUTD = 1 mA ⎯35 50 ΩMB39A125
Input
current IIN 12 −INC1 = 16.8 V ⎯84 150 µA MB39A126
Input
resistance R1 12, 16 ⎯105 150 195 kΩMB39A126
R2 16 ⎯35 50 65 kΩMB39A126
MB39A125/126
17
(VCC = 19 V, VREF = 0 mA, Ta = +25 °C)
(Continued)
Parameter Sym-
bol Pin No. Condition Value Unit Remarks
Min Typ Max
5-2.
Error
amplifier
block
[Error Amp3]
SEL input
voltage
VON 11
Error Amp3
reference voltage
= 4.2 V
(4-cell setting)
2⎯25 V MB39A126
VOFF 11
Error Amp3
reference voltage
= 3.15 V
(3-cell setting)
0⎯0.8 V MB39A126
Input
current ISELH 11 SEL = 5 V ⎯50 100 µA MB39A126
ISELL 11 SEL = 0 V ⎯01µA MB39A126
6.
Current
Detection
Amplifier
B l oc k
[Current
Amp1,
Current
Amp2]
Input
offset
voltage VIO 1, 12,
13, 24
+INC1 = +INC2 =
−INC1 = −INC2 =
3 V to VCC −3⎯+3 mV
Input
current
I+INCH 13, 24 +INC1 = +INC2 =
3 V to VCC,
∆VIN = −100 mV ⎯20 30 µA
I-INCH
1, 12 +INC1 = +INC2 =
3 V to VCC,
∆VIN = −100 mV ⎯0.1 0.2 µAMB39A125
1+INC1 = +INC2 =
3 V to VCC,
∆VIN = −100 mV ⎯0.1 0.2 µAMB39A126
I+INCL 13, 24 +INC1 = +INC2 = 0 V,
∆VIN = −100 mV −180 −120 ⎯µA
I-INCL 1, 12 +INC1 = +INC2 = 0 V,
∆VIN = −100 mV −195 −130 ⎯µA
Current
detection
voltage
VOUTC1 2, 10 +INC1 = +INC2 =
3 V to VCC,
∆VIN = −100 mV 1.9 2.0 2.1 V
VOUTC2 2, 10 +INC1 = +INC2 =
3 V to VCC,
∆VIN = −20 mV 0.34 0.40 0.46 V
VOUTC3 2, 10 +INC1 = +INC2 = 0 V,
∆VIN = −100 mV 1.8 2.0 2.2 V
VOUTC4 2, 10 +INC1 = +INC2 = 0 V,
∆VIN = −20 mV 0.2 0.4 0.6 V
Common
mode input
voltage
range
VCM 1, 12,
13, 24 ⎯0⎯VCC V
Voltage
gain Av 2, 10 +INC1 = +INC2 =
3 V to VCC,
∆VIN = −100 mV 19 20 21 V/V
MB39A125/126
18
(VCC = 19 V, VREF = 0 mA, Ta = +25 °C)
* : Standard design value (Continued)
Parameter Sym-
bol Pin No. Condition Value Unit Re-
marks
Min Typ Max
6.
Current
Detection
Amplifier
Block
[Current
Amp1,
Current
Amp2]
Frequency
bandwidth BW 2, 10 AV = 0 dB ⎯ 2* ⎯MHz
Output
voltage VOUTCH 2, 10 ⎯4.7 4.9 ⎯V
VOUTCL 2, 10 ⎯⎯20 200 mV
Output
source cur-
rent ISOURCE 2, 10 OUTC1 = OUTC2 = 2 V ⎯−2−1mA
Output sink
current ISINK 2, 10 OUTC1 = OUTC2 = 2 V 150 300 ⎯µA
7.
PWM Comp.
Block
[PWM
Comp.]
Threshold
voltage
VTL 15 Duty cycle = 0%1.4 1.5 ⎯V
VTH 15 Duty cycle = 100%⎯2.5 2.6 V
8.
Output
block
[OUT]
Output
source cur-
rent ISOURCE 20 OUT = 13 V,
Duty ≤ 5%
(t = 1 / fosc × Duty) ⎯−400* ⎯mA
Output sink
current ISINK 20 OUT = 19 V,
Duty ≤ 5%
(t = 1 / fosc × Duty) ⎯ 400* ⎯mA
Output ON
resistance ROH 20 OUT = −45 mA ⎯6.5 9.8 Ω
ROL 20 OUT = 45 mA ⎯5.0 7.5 Ω
Rise time tr1 20 O UT = 3300 pF ⎯ 50* ⎯ns
Fall time tf1 20 O UT = 3300 pF ⎯ 50* ⎯ns
9.
Low Input
Voltage
Detection
Block
[UV Comp.]
Threshold
voltage
VTLH 21 VCC = ,
−INC1 = 16.8 V 17.2 17.4 17.6 V
VTHL 21 VCC = ,
−INC1 = 16.8 V 16.8 17.0 17.2 V
Hysteresis
width VH21 ⎯⎯0.4* ⎯V
10.
AC Adapter
Voltage
Detection
Block
[AC Comp.]
Threshold
voltage VTLH 7ACIN = 1.3 1.4 1.5 V
VTHL 7ACIN = 1.2 1.3 1.4 V
Hysteresis
width VH7⎯⎯0.1* ⎯V
MB39A125/126
19
(Continued) (VCC = 19 V, VREF = 0 mA, Ta = +25 °C)
* : Standard design value
Parameter Sym-
bol Pin
No. Condition Value Unit Re-
marks
Min Typ Max
10.
AC Adapter
Voltage
Detection
Block
[AC Comp.]
ACOK
terminal
output leak
current
ILEAK 5ACOK = 25 V ⎯01µA
ACOK
terminal
output ON
resistance
RON 5ACOK = 1 mA ⎯200 400 Ω
XACOK
terminal
output leak
current
ILEAK 18 XACOK = 25 V ⎯01µA
XACOK
terminal
output ON
resistance
RON 18 XACOK = 1 mA ⎯200 400 Ω
11.
Power
Supply
Control
Block
[CTL]
CTL input
voltage VON 14 IC operation mode 2 ⎯25 V
VOFF 14 IC standby mode 0 ⎯0.8 V
Input current ICTLH 14 CTL = 5 V ⎯100 150 µA
ICTLL 14 CTL = 0 V ⎯01µA
12.
Bias Voltage
Block
[VH]
Output
Voltage VH19 VCC = 8 V to 25 V,
VH = 0 mA to 30 mA VCC −
6.5 VCC −
6.0 VCC −
5.5 V
13.
General
Standby
current ICCS 21 CTL = 0 V ⎯010µA
Power
supply
current ICC 21 CTL = 5 V ⎯57.5mA
MB39A125/126
20
■TYPICAL CHARACTERISTICS
(Continued)
6
5
4
3
2
1
00 5 10 15 20 25
Ta = +25 °C
CTL = 5 V
0
100
200
300
400
500
600
700
800
900
1000
0 5 10 15 20 250
1
2
3
4
5
6
7
8
9
10
Ta = +25 °C
VCC = 19 V
VREF = 0 mA
VREF
ICTL
6
5
4
3
2
1
00 5 10 15 20 25
Ta = +25 °C
CTL = 5 V
VREF = 0 mA
0
1
2
3
4
5
6
0 5 10 15 20 25 30 35
Ta = +25 °C
VCC = 19 V
CTL = 5 V
4.92
4.94
4.96
4.98
5.00
5.02
5.04
5.06
5.08
−40 −20 0 20 40 60 80 100
VCC = 19 V
CTL = 5 V
VREF = 0 mA
260
270
280
290
300
310
320
330
340
0 5 10 15 20 25
Ta = +25 °C
CTL = 5 V
RT = 47 kΩ
Power Supply Current vs. Power Supply Voltage
Power supply voltage VCC (V)
Power supply current Icc (mA)
CTL Terminal Input Current, Reference Voltage vs.
CTL Terminal Input Voltage
CTL terminal input voltage VCTL (V)
CTL terminal input
current ICTL (µA)
Reference voltage VREF (V)
Reference Volt ag e vs. Power Supply Voltage
Power supply voltage VCC (V)
Reference voltage VREF (V)
Reference Voltage vs. Load Current
Load current IREF (mA)
Reference voltage VREF (V)
Reference Voltage vs.
Operating Ambient Temperature
Operating ambient temperature Ta ( °C)
Reference voltage VREF (V)
Triangular Wave Oscillation Frequency vs.
Power Supply Voltage
Power Supply Voltage VCC (V)
Triangular wave oscillation
frequency fosc (kHz)
MB39A125/126
21
(Continued)
260
270
280
290
300
310
320
330
340
−40 −20 0 20 40 60 80 100
VCC = 19 V
CTL = 5 V
RT = 47 kΩ
10
100
1000
10 100 1000
Ta = +25 °C
VCC = 19 V
CTL = 5 V
−40
4.12
4.14
4.16
4.18
4.20
4.22
4.24
4.26
4.28
−20 0 20 40 60 80 100
VCC = 19 V
CTL = 5 V
VREF = 0 mA
16.70
16.75
16.80
16.85
16.90
−40 −20 0 20 40 60 80 100
VCC = 19 V
CTL = 5 V
SEL = 5 V
12.50
12.55
12.60
12.65
12.70
−40 −20 0 20 40 60 80 100
VCC = 19 V
CTL = 5 V
SEL = 0 V
Triangular Wave Oscillation Frequency vs.
Operating Ambient Temperature
Operating ambient temperature Ta ( °C)
Triangular wave oscillation
frequency fosc (kHz)
Triangular Wave Oscillation Frequency vs.
Timing Resistor
Timing resistor RT (kΩ)
Triangular wave oscillation
frequency fosc (kHz)
Error Amplifier Threshold Voltage vs.
Operating Ambient Temperatu re
Operating ambient temperature Ta ( °C)
Error amplifier thr eshold voltage VTH (V)
<MB39A125>
<MB39A126>
Error Amplifier Thre shold Voltage vs.
Operating Ambient Temperature
Operating amb ien t t em perat ur e Ta ( °C)
Error amplifier threshold voltage VTH (V)
Error Amplifier Thr eshold Voltage vs.
Operating Ambient Temperature
Operating ambient temperature Ta ( °C)
Error amplifier threshold voltage VTH (V)
MB39A125/126
22
(Continued)
−
+
Vcc = 19 V
100 1k 10k 100k 1M 10M
−180
−90
0
90
180
40
30
20
10
−10
−20
−30
−40
0Av
Ta = +25 °C
VCC = 19 V
φ
Error Amp1
(Error Amp2)
IN OUT
1 µF
+
10
kΩ10
kΩ
10
kΩ10
kΩ
2.4 kΩ
240 kΩ
4.2 V
(4)
(3)
8
915
FB123
−INE1, 2
+INE1, 2
−
+
−180
−90
0
90
18040
30
20
10
−10
−20
−30
−40
0
10
kΩ
10
kΩ
100 1k 10k 100k 1M 10M
Av
φ
IN OUT
1µF
+2.4 kΩ
240 kΩ
4.2 V Error Amp3
16 15
Ta = +25 °C
VCC = 19 V
FB123
−INE3
+
−
40
30
20
10
−10
−20
−30
−40
0
−180
−90
0
90
180
100 1k 10k 100k 1M 10M
Av
φ
Current Amp1
12.6 V 12.55 V
OUT
VCC = 19 V
+INC
−INC OUTC
(24)
(1) (2)
(Current Amp2)
×20
13
12 10
Error Amplifier, Gain, Phase vs. Frequency
Frequency f (Hz)
Gain Av (dB)
Phase φ (deg )
Error Amplifier, Gai n, Phase vs. Frequency
Frequency f (Hz)
Gain Av (dB)
Phase φ (deg)
Current Detection Amplifier, Gain, Phase vs. Frequency
Frequency f (Hz)
Gain Av (dB)
Phase φ (deg)
MB39A125/126
23
(Continued)
0
100
200
300
400
500
600
700
800
−40 −20 0 20 40 60 80 100
740
0
500
1000
1500
2000
2500
3000
3500
4000
−40 −20 0 20 40 60 80 100
3700
Power Dissipation vs.
Operating Ambien t Temperature (SSO P)
Operating ambient temperature Ta ( °C)
Power dissipation PD (mW)
Power Dissipation vs.
Operating Amb ient Temperature (QFN)
Operating am b i en t tem p er a tur e Ta ( °C)
Power dissipation PD (mW)
MB39A125/126
24
■FUNCTIONAL DESCRIPTION
1. DC/DC Converter Block
(1) Reference voltage block (REF)
The reference voltage circuit uses the voltage supplied from the VCC terminal (pin 21) to generate a temperature
compensated, stable voltage (5.0 V Typ) used as the reference power supply voltage for the IC’ s internal circuitry .
This block can also be used to obtain a load current to a maximum of 1 mA from the reference voltage VREF
terminal (pin 6) .
(2) Triangula r wave oscillator block (OSC)
The triangular wav e oscillator b lock has b uilt-in capacitor f or frequency setting into and generates the triangular
wave oscillation wa veform by connecting the frequency setting resistor with the RT terminal (pin 17) .
The triangular w ave is input to the PWM comparator circuits on the IC.
(3) Error amplifier block (Error Amp1)
This amplifier detects the output signal from the current detection amplifier (Current Amp1) , compares this to
the +INE1 ter minal (pin 9) , and outputs a PWM control signal to be used in controlling the charge current.
In addition, an arbitrar y loop gain can be set up by connecting a feedback resistor and capacitor between the
FB123 terminal (pin 15) and −INE1 terminal (pin 8) , providing stable phase compensation to the system.
(4) Error amplifier block (Error Amp2)
This amplifier detects the output signal from the current detection amplifier (Current Amp2) , compares this to
the +INE2 ter minal (pin 3) , and outputs a PWM control signal to be used in controlling the charge current.
In addition, an arbitrar y loop gain can be set up by connecting a feedback resistor and capacitor between the
FB123 terminal (pin 15) and −INE2 terminal (pin 4) , providing stable phase compensation to the system.
(5) Error amplifier block (Error Amp3)
This error amplifier (Error Amp3) detects the output voltage from the DC/DC conver ter and outputs the PWM
control signal. MB39A125 can set the desired le vel of output voltage from 1 cell to 4 cells by connecting e xternal
output voltage setting resistors to the error amplifier inverted input terminal. MB39A126 can set the output voltage
for 3 cells or 4 cells by SEL terminal (pin 11) input.
In addition, an arbitrary loop gain can be set by connecting a feedback resistor and capacitor from the FB123
ter m in al (p in 15 ) to the −INE3 terminal (pin 16) , enabling stab le phase compensation to t he system.
(6) Current detection amplifier block (Current Amp1)
The current detection amplifier (Current Amp1) detects a voltage drop which occurs between both ends of the
output sense re sistor (RS2) due t o the flow of the char ge current , using th e +INC1 terminal (pin 13) and −INC1
terminal (pin 12) . The signal amplified to 20 times is output to the OUTC1 terminal (pin 10) .
MB39A125/126
25
(7) Current detection amplifier block (Current Amp2)
The current detection amplifier (Current Amp2) detects a voltage drop which occurs between both ends of the
output sense resistor (RS1) due to the f low of the AC adapter current, using the +INC2 terminal (pin 24) and
−INC2 terminal (pin 1) . The signal amplified to 20 times is output to the OUTC2 terminal (pin 2) .
(8) PWM comparator block (PWM Comp.)
The PWM comparator circuit is a voltage-pulse width converter for controlling the output duty of the error
amplifiers (Error Amp1 to Error Amp3) depending on their output voltage.
The PWM compar ator circuit compares the triangular w av e v oltage the lo west generated b y the triangular w av e
oscillator to the error amplifier output voltage and turns on the external output transistor, during the inter val in
which the triangular wave voltage is lower than the error amplifier output voltage .
(9) Output block (OUT)
The output circuit uses a totem-pole configuration capable of driving an external Pch MOS FET.
The output “L” lev el se ts the output amplitu de to 6 V (Typ) using the v oltage gener ated b y the bias v oltage b loc k
(VH) .
This results in increasing con version efficiency and suppressing the withstand v oltage of the connected e xternal
transistor in a wide range of input voltages.
(10) Power supply control block (CTL)
Setting the CT L terminal (pin 14) low places the IC in the standby mode. (The power supply current is 10µA at
maximum in the standby mode.)
CTL function tab le : MB39A125
CTL function tab le : MB39A126
(11) Bias voltage block (VH)
The bias voltage circuit outputs VCC − 6 V (Typ) as the minimum potential of the output circuit. In the standby
mode, this circuit outputs the potential equal to VCC.
CTL Power OUTD
L OFF (Standby) Hi-Z
H ON (Active) L
CTL Power
L OFF (Standby)
H ON (Active)
MB39A125/126
26
2. Protection Functions
(1) Under voltage lockout protect ion circuit block (UVLO)
The transient state or a momentary decrease in power supply voltage or internal reference voltage (VREF) ,
which occurs when the po wer su pply (VCC) is turned on, ma y cause malfunction s in the control IC, resulting in
breakdown or deterioration of the system.
To prev ent such malfunction, the un der v oltage loc kou t protection circuit de tects internal ref erence v oltage dr op
and fixes the OUT terminal (pin 20) to the “H” level. The system restores voltage supply when the internal
reference voltage reaches the threshold voltage of the under voltage lockout protection circuit.
Protection circuit (UVLO) operation function table : MB39A125
When UVLO is operating (VREF voltage is lower than UVLO threshold voltage, the logic of the f ollowing terminal
is fixed.)
Protection circuit (UVLO) operation function table : MB39A126
When UVLO is operating (VREF voltage is lower than UVLO threshold voltage, the logic of the f ollowing terminal
is fixed.)
(2) Low input voltage detection b lock (UV Comp.)
UV Comp. detects th at pow er supp ly voltage (VCC) is lower t ha n the batt ery volt age +0.2 V (Typ) and fixes the
OUT terminal (pin 20) to the “H” level.
The system restores voltage supply when the power supply voltage reaches the threshold voltage of the AC
adapter detection block.
Protection cir cuit (UV Comp.) operation function table : MB39A1 25
When UV Comp . is oper ating (VCC v ol tage is lo wer th an UV Comp . th reshold v oltage, the logic of the following
terminal is fixed.)
Protection cir cuit (UV Comp.) operation function table : MB39A1 26
When UV Comp . is oper ating (VCC v ol tage is lo wer th an UV Comp . th reshold v oltage, the logic of the following
terminal is fixed.)
OUTD OUT CS ACOK XACOK
Hi-Z H L H L
OUT CS ACOK XACOK
HLHL
OUTD OUT CS
LHL
OUT CS
HL
MB39A125/126
27
3. Detection Function
(1) AC adapter voltage detection block (AC Comp.)
When ACIN terminal (pin 7) voltage is lower than 1.3 V (Typ) , AC adapter voltage detection block (AC Comp.)
outputs “Hi-Z” level to the ACOK termina l (pin 5) an d outputs “L” level to the XACOK terminal (pin 18) . When
CTL terminal (pin 14) is set to “L” level, ACOK terminal (pin 5) and XACOK terminal (pin 18) are fixed to “Hi-Z” level.
4. Switch Function : MB39A126
The charge volta ge can be set to 16.8 V/12.6 V with the SEL terminal (pin 11) .
SEL function table
ACIN ACOK XACOK
HLHi-Z
LHi-ZL
SEL DC/DC output setting voltage
H16.8 V
L12.6 V
MB39A125/126
28
■CONSTANT CHARGING VOLTAGE AND CURRENT OPERATION
MB39A125/126 is DC/DC converter with the pulse width modulation (PWM) .
MB39A125 is in the output voltage control loop, the Error Amp3 compares internal voltage reference voltage
4.2 V and DC/DC converter output to output the PWM controlled signal.
MB39A126 is in the output voltage control loop, the Error Amp3 compares internal voltage reference voltage
4.2 V/3.15 V and DC/DC converter output to output the PWM controlled signal.
In the charging cur rent control lo op, the voltag e drop gener at ed at both ends of chargin g current sen se resistor
(RS2) is sensed by +INC1 terminal (pin 13) , −INC1 terminal (pin 12) of Current Amp1, and the signal is ou tput
to OUTC1 terminal (pin 10) , w hich is amplified by 20 times. Error Amp1 compares the OUTC1 terminal (pin
10) voltage, which is the outpu t o f Curr ent Amp1, and +I NE1 t erminal (pin 9) to outpu t the PWM cont ro l signa l
and regulates the charging current.
In the AC adapter current control loop, the voltage drop generated at both ends of AC adapter current sense
resistor (RS1) is sensed by +INC2 terminal (pin 24) , −INC2 terminal (pin 1) of Cu rren t Am p2, a nd t he sign al is
output to OUTC2 ter minal (pin 2) , which is amplified by 20 times. Error Am p2 compares OU TC2 terminal (p in
2) voltage, which is output of Current Amp2, and +INE2 ter minal (pin 3) voltage and outputs PWM controlled
signal, and it limits the charging current due to the AC adapter current not to exceed the setti ng value.
The PWM comparator compares the triangular wave to the smallest terminal voltage among the Error AMP1,
Error AMP2 and Error AMP3. And the triangular wav e voltage generated b y the triangular wa ve oscillator . When
the triangular wave voltage is smaller than the error amplifier output voltage, the main side output transistor is
tur n e d on .
MB39A125/126
29
■SETTING THE CHARGE VOLTAGE
MB39A125
The charging v oltage (DC/DC out put v oltage) can be set b y connecting e xternal output v oltage setti ng resistors
(R3, R4) to the −INE3 terminal (pin 16) . Be sure to select a resistor value that allows you to ignore the on-
resistance (35 Ω, 1 mA) of the internal FET connected to the OUTD terminal (pin 11) .
Battery charging voltage : Vo
Vo (V) = (R3 + R4) / R4 × 4.2 (V)
−
+
B
<Error Amp3>
OUTD
−
INE3
Vo
R3
R4
4.2 V
11
16
MB39A125/126
30
MB39A126
The setting of the charge voltage is switched to 3cells or 4cells by the SEL terminal (pin 11) .
Charge voltage is set to 16.8 V when SEL ter m inal is “H” level, and charge voltage is set to 12.6 V when SEL
terminal is “L” level.
Battery charging voltage : Vo
Vo (V) = (150 kΩ + 50 kΩ) / 50 kΩ × 4.2 (V) = 16.8 (V) (SEL = H)
Vo (V) = (150 kΩ + 50 kΩ) / 50 kΩ × 3.15 (V) = 12.6 (V) (SEL = L)
−
+
<Error Amp3>
SEL
−
INC1
R3
R4
4.2 V3.15 V
150 k
Ω
50 k
Ω
−
INE3
11
16
12
MB39A125/126
31
■SETTING THE CHARGE CURRENT
The charge current value can be set at the analog voltage value of the +INE1 ter minal (pin 9) .
Charge current f ormula : Ichg (A) = V+INE1 (V) / (20 × RS1 (Ω) )
Charge current setting voltage : V+INE1 (V) = 20 × Ichg (A) × RS1 (Ω)
■SETTING THE INPUT CURRENT
The input limit current value can be set at the analog volt age value of the +INE2 terminal (pin 3) .
Input current formula : IIN (A) = V+INE2 (V) / (20 × RS2 (Ω) )
Input current setting voltage : V+INE2 (V) = 20 × IIN (A) × RS2 (Ω)
■SETTING THE TRIANGULAR WAVE OSCILLATION FREQUENCY
The triangular wave oscillation frequency can be set by the timing resistor (RT) connected to the RT terminal
(pin 17) .
Triangular wave oscillation frequency fosc
fosc (kHz) := 14100 / RT (kΩ)
MB39A125/126
32
■SETTING THE SOFT-START TIME
Soft-start function prevents rush current at start-up of IC when the Soft-start capacitor (Cs) is connecte d to the
CS ter minal (p in 22) . This IC char ges extern al soft-start capacitor (Cs) with 10 µA after CTL terminal (pin 14)
voltage level becomes high an d IC starts (when VCC ≥ UVLO threshold voltage) .
Output ON duty depends on PWM comparator, which compares the FB123 ter minal (pin 15) voltage with the
triangular wave oscillator output voltage.
During soft start, FB123 terminal (pin 15) v oltage increases wit h sum v oltage of CS terminal and diode v olta ge.
Therefore, the output voltage of the DC/DC converter and current increase can be set by output ON duty in
proportion to rise of CS terminal (pin 22) v oltage. The ON Duty is affected b y the ramp voltage of FB123 terminal
(pin 15) until an outp ut vo ltage of one Error Amp reaches the DC/DC converter loop controlled voltage.
Soft-start time is obtained from the following f ormula :
Soft-start tim e : ts (time to outpu t on duty 80 %)
ts (s) := 0.13 × Cs (µF)
CT
CS
0 V
0 V
0 V
0 A
Io
Vo
OUT
CT
CS
FB123
OUT
Vo
Io
Error Amp3 threshold voltage
FB123
•Soft-start timing chart
MB39A125/126
33
■TRANSIENT RESPONSE AT LOAD-STEP
The constant voltage control loop and the constant current control loop are independent. With the load-step,
these two control loops change.
The battery voltage and current overshoot are generated by the delay time of the control loop when the mode
changes. The delay time is determined by phase compensation constant. When the battery is removed if the
charge control is switched from the constant current control to the constant voltage control, and the charging
voltage does overshoot by generating the period controlled with high duty by output setting voltage. The excessive
voltage is not applied to the battery because the battery is not connected.
When the battery is connected if the charge control is s witched from the constant v oltage control to the consta nt
current control, and the charging current does overshoot by generating the period controlled with high duty by
charge current setting.
The battery pack manufacturer in Japan thinks it is not the problem the current overshoot of 10 ms or less.
10 ms
Constant Current
Battery Voltage
Error Amp3 Output
Error Amp1 Output
Error Amp3 Output
Constant Current Constant Voltage
Error Amp1 Output
Battery Current
When charge control switches
from the constant current control to
the constant voltage control, the
voltage does overshoot by gener-
ating the period controlled with
high duty by output setting voltage. The battery pack manufac-
turer in Japan thinks it is
not the problem the current
overshoot of 10 ms or less.
•Timing chart at load-step
MB39A125/126
34
■AC ADAPTER DETECTION FUNCTION
When ACIN terminal (pin 7) voltage is lower than 1.3 V (Typ) , AC adapter voltage detection block (AC Comp.)
outputs “Hi-Z” level to the ACOK ter minal (pin 5) and outputs “L” level to the XACOK ter minal (pin 18) . When
CTL terminal (pin 14) is set to “L” level, ACOK terminal (pin 5) and XACOK terminal (pin 18) are fixed to “Hi-Z” level.
(1) AC adapter presence
If you connect as shown in the figure below the presence of AC adapter can be easily detected because the
signal is output from the ACOK terminal (pin 5) to microcomputer etc. In this case, if the CTL terminal is set to
“L” level, IC becomes the standby state (ICC = 0 µA Typ).
+
−
micon
ACIN ACOK
<AC Comp.>
XACOK
AC adapter
7518
•Connection example of detecting AC adapter presence
MB39A125/126
35
(2) Automatic changing system power suppl y between AC adapter and battery
The A C adapter v oltage is detect ed and e xternal s witch at input side and battery side can be changed automat-
ically with the connection as follows. Connect CTL terminal ( pin 14) to VCC ter min al (pin 21) for this function.
OFF duty cycle becomes 100% when CS terminal (pin 22) voltage is made to be 0 V, if it is needed after full charge.
+
−
ACIN
ACOK
<AC Comp.>
XACOK
System
AC adapter
Battery
VCC
CTL
CS
VREF
10 µA
micon
< SOFT>
7518
21
14
22
•Connection example of automatic changing system powe r supply between AC adapter and battery
MB39A125/126
36
(3) Battery selector function
When control signal from microcomputer etc. is input to A CIN terminal (pin 7) as sho wn in the follo wing diagram,
ACOK terminal (pin 5) output voltage and XACOK terminal (pin 18) output voltage are controlled to select one
of the two batteries for charge. Connect CTL terminal (pin 14) to VCC terminal (pin 21) for this function. OFF
duty cycle becomes 100% when CS terminal (pin 22) v olta ge is made to be 0 V, if it is needed after full charge .
+
−
ACIN ACOK
<AC Comp.>
XACOK
System
AC adapter
Battery1
VCC
CTL
CS
VREF
< SOFT>
10 µA
micon
ICHG
RS1
AB
Battery2
7518
21
14
22
•Connection example of battery selector function
MB39A125/126
37
(4) When AC Comp. is not used
When A C Comp. (ACIN (pin 7) , ACOK (pin 5) , and XACOK (pin 18) terminals) is not used as f o llo ws, connect
the ACIN (pin 7) , ACOK (pin 5) , and XACOK (pin 18) terminals to GND terminal (pin 23) .
And connect VCC terminal (pin 21) to system, as follows, to avoid the reverse current from the batter y to the
VCC terminal (pin 21) .
+
−
ACIN ACOK
<AC Comp.>
XACOK
System
AC adapter
Battery
VCC
I
CHG
RS1
AB
7518
21
•Connection example when AC Comp. is not used
MB39A125/126
38
■PHASE COMPENSATION
+
−
−
+
VIN
Ro
Cc
Rc
Rin2
Rin1
ESR
Co
RLLo
RS2
15mΩ
OSC
−1.5V
−2.5V
VH
Bias
Voltage
Drive VBATT
RS1
33 mΩ
I1
<PWM Comp.>
VCC
OUT
FB123
4.2 V
<Error Amp 3>
−INE3 <OUT>
(VCC − 6V)
VH
16
20
19
15
21
Lo : Inductance
RL : Equivalent series resistance of inductance
Co : Capacity of condenser
ESR : Equivalent series resistance of condenser
Ro : Load resistance
•Example Circuit
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
10
20
30
40
50
60
70
80
90
1 10 100 1k 10k 100k 1M 10M−180
−160
−140
−120
−100
−80
−60
−40
−20
0
20
40
60
80
100
120
140
160
180
gain
phase
Phase
Gain
Phase [deg]
Gain [dB]
Frequency characteristic of power output LC filter
(DC gain is included.)
Frequency [Hz]
(Ro
(Ro
2π
1
RL)
ESR)
CoLo
f1 (Hz) =
×× +
+
Lo = 15 µH
Co = 14.1 µF
Ro = 4.2 Ω
RL = 30 mΩ
ESR = 100 mΩ
Cut-off frequency
• Frequency Characteristics of LC filter
MB39A125/126
39
Notes : 1) Please review the Error Amp frequency characteristics, when LC filter parameter is modified.
2) When the ceramic capacitor is used as smoothing capacitor Co, phase margin is reduced because ESR
of the ceramic capacitor is e xtremely small as shown in “Fr equency Character istics of LC filter wh ich is
using low ESR”.
Therefore, change phase compensation of Er ror Amp or create resistance equivalent to ESR using
pattern.
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
10
20
30
40
50
60
70
80
90
−180
−160
−140
−120
−100
−80
−60
−40
−20
0
20
40
60
80
100
120
140
160
180
1 10 100 1k 10k 100k 1M
total gain
AMP Open
Loop Gain
total phase
Phase
Phase [deg]
Gain [dB]
Gain ××
CcRc
f2(Hz) = 2π
1
Total frequency characteristic
Frequency [Hz]
Rc = 150 kΩ
Cc = 3300 pF
Cut-off freq ue n cy
• Frequency Characteristics of Error Amp
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
10
20
30
40
50
60
70
80
90
−180
−160
−140
−120
−100
−80
−60
−40
−20
0
20
40
60
80
100
120
140
160
180
1 10 100 1k 10k 100k 1M
Phase
Gain
total gain
AMP Open
Loop Gain
total phase
Phase [deg]
Gain [dB]
Total frequency characteristic
Frequency [Hz] Triangular wave frequency
The overview of freque ncy characteristic
for DC/DC converter can be obtained in
combination between “Frequency
Characteristics of LC filter” and
“Frequency Characteristics of Error Amp ”
as mentioned above.
Please note the following point in order to
stabilize the frequency characteristics of
DC/DC converter .
Cut-off frequency of DC/DC converter
should be set to half or less of the
triangular wave oscillator frequency.
• Frequency Char acteristics of DC/DC converter
MB39A125/126
40
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
10
20
30
40
50
60
70
80
90
1 10 100 1k 10k 100k 1M 10M−180
−160
−140
−120
−100
−80
−60
−40
−20
0
20
40
60
80
100
120
140
160
180
gain
phase
Phase
Gain
Phase [deg]
Gain [dB]
Frequency characteristic of power output LC filter
(DC gain is included.)
Frequency [Hz]
(Ro
(Ro
2π
1
RL)
ESR)
CoLo
f1 (Hz) =
×× +
+
Board Pattern
or connected
resistor
−
+
Lo = 15 µH
Co = 14.1 µF
Ro = 4.2 Ω
RL = 30 mΩ
ESR = 100 mΩ
Cut-off frequency
<3Pole2Zero>
DC/DC output < Additional ESR>
• Frequency Characteristics of LC filter which is using low ESR
MB39A125/126
41
■PROCESSING WITHOUT USING OF THE CURRENT AMP1 AND AMP2
When Current Amp is not u sed, con nect the +INC1 terminal (pin 13) , +INC2 terminal (pin 24) , −INC1 terminal
(pin 12) , a nd −INC2 terminal (pin 1) to VREF terminal (pin 6) , and then leave OUTC1 terminal (pin 10) and
OUTC2 terminal (p in 2) ope n.
■PROCESSING WITHOUT USING OF THE ERROR AMP1 AND AMP2
When Error Am p is not used, leav e FB123 terminal (pin 15) ope n, connect the −INE1 terminal (pin 8) and −INE2
terminal (pin 4) to GND, and connect +INE1 terminal (pin 9) and +INE2 terminal (pin 3) to VREF terminal (pin 6) .
6
2
10
1
12 13
−INC2
OUTC2
OUTC1
VREF
+INC1 24
+INC2
−INC1
”open”
•Connection when Curren t Amp is not used
6
16
4
8
3
923
+INE2
−INE2
−INE1
VREF
GND
FB123
+INE1
”open”
•Connection when Error Amp is not used
MB39A125/126
42
■PROCESSING WITHOUT USING OF THE CS TERMINAL
When soft-start function is not used, leave the CS terminal (pin 22) open.
CS 22
”open”
•Connection when no soft-start time is specified
MB39A125/126
43
■I/O EQUIVALENT CIRCUIT
(Continued)
1.235 V
VCC
CTL
GND
VREF
GND
GND GND GND
FB123
VCC VCC
CS
CS
4.2 V
RT
−INE1
+INE1
VREF
(5.0 V)
VREF
(5.0 V)
VREF
(5.0 V)
37.8
kΩ
33.1
kΩ
51
kΩ
12.35
kΩ
14
6
+
−
+
−
23
21
22
17
9
8
GND
GND
FB123
OUTC1
VCC
VCC
−INE2
−INC1
+INC1
+INE2
3
4
GND
VCC
16 15
10
12
13
GND
OUTC2
FB123
VCC
−INC2
+INC2
2
1
24
• <Reference voltage block> • <Power supply control block>
ESD
protection
element
• <Soft-start block> • <Triangular wave
oscillator block> • <Error amplifier block (Error Amp1) >
• <Error amplifier block (Erro r Amp2) > • <Error amplifier block (Error Amp3) >
• <Current detectio n amp lifier blo ck
(Current Amp1) > • <Current detection amplif ier block
(Current Amp2 ) >
ESD
protection
element
MB39A125/126
44
(Continued)
VCC
VCC
VCC
FB123 CT
GND
GND
VCC
VH
OUTD
SEL
GND GND GND
ACIN
ACOK XACOK
GND
VH
20
7
VREF
(
5.0 V
)5 18
19
11
11
33.1 k
Ω
51 k
Ω
OUT
• <PWM comparator block> • <Output block>
• <AC adapter voltage detection block>
• <Bias voltage block> • <Output voltage switching function block>
<MB39A126>
• <Invalidity current prevention block>
<MB39A125>
MB39A125/126
45
■APPLICATION EXAMPLE 1
• MB39A125
<SOFT>
<OSC>
500 kHz Max
<Current Amp 2>
<Error Amp 3>
<Current Amp 1>
<Error Amp 2>
<PWM Comp.>
<UV Comp.>
<AC Comp.>
<Error Amp 1>
<REF> <CTL>
<OUT>
<UVLO>
C
T
VH
VREF
VREF
UVLO
Bias
Voltage
−2.5 V
−1.5 V
VREF
VCC
0.2 V
Slope
Control
Q2 I
IN
R17
51
kΩ
RS1
0.015
Ω
R18
24
kΩ
Q1
V
IN
R14
15 kΩ
R15
68 kΩ
R16
10 kΩ
R12
30 kΩ
R3
33
kΩ
R6
10 kΩ
R7
10 kΩ
C10
6800
pF
R9
36 kΩ
R10
20 kΩ
C13
4.2 V
22 pF
C8
6800 pF
C6
2200 pF C14
47 pF
(45 pF)
R13
20
kΩ
R11
SW2
1.1
kΩ
(8 V to
25 V)
to System
Q3
Battery
100 kΩ
C15
R19
56 kΩ
0.033
Ω
RS2
L1
15 µH
10 µF
C3
D1
10 µF
C4
C1
0.1
µF
0.22
µF
C7
0.1
µF
C12
OUT
VH
VCC
XACOKACOK
ACIN
−INE1
−INC1
−INC1
(Vo)
+INC1
+INC2
+INE2
OUTD
FB123
R21
R23
100 kΩ
RT VREF
4.2 V
Bias
GND
CTL
C9
R4
47 kΩ
100 kΩ
R5
100 kΩ
R8
100 kΩ
R22
200 kΩ
CS
5.0 V
C11
0.22 µF
10 µF
−INC2
+INE1
−INE2
OUTC1
I
CHG
R20
0.22 µF
BA
21
1857
8
10
2
13
20
19
14
12
24
9
4
A
B
1
3
15
16
11
22
6
(VCC −
6 V)
−INE3
17 23
−
+
−
+
+
−
+
−
+
−
−
+
×20
+
−
×20
VREF
Drive
+
−
OUTC2
10 µF
MB39A125/126
46
■PARTS LIST 1
• MB39A125
Note : NEC : NEC Corporation
ROHM : ROHM CO., LTD.
SUMIDA : Sumida Corporation
TDK : TDK Corporation
KOA : KOA Corporation
ssm : SUSUMU CO., LTD.
COMPONENT ITEM SPECIFICATION VENDOR PARTS No.
Q1, Q2, Q3 Pch FET VDS = −30 V, ID = −7.0 A NEC µPA2714GR
D1 Diode VF = 0.42 V (Max) , At IF = 3 A ROHM RB053L-3 0
L1 Inductor 15 µH 3.6 A, 50 mΩSUMIDA CDRH104R-150
C1, C3, C4
C6
C7, C12
C8, C10
C9, C11
C13
C14
C15
Ceramics Condenser
Ceramics Condenser
Ceramics Condenser
Ceramics Condenser
Ceramics Condenser
Ceramics Condenser
Ceramics Condenser
Ceramics Condenser
10 µF
2200 pF
0.1 µF
6800 pF
0.22 µF
22 pF
47 pF
0.22 µF
25 V
50 V
50 V
50 V
16 V
50 V
50 V
25 V
TDK
TDK
TDK
TDK
TDK
TDK
TDK
TDK
C3225X5R1E106K
C1608JB1H222K
C1608JB1H104K
C1608JB1H682K
C1608JB1C224K
C1608CH1H220J
C1608CH1H470J
C2012JB1E224K
RS1
RS2
R3
R4
R5, R8
R6, R7
R9
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19, R21, R23
R20
R22
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
15 mΩ
33 mΩ
33 kΩ
47 kΩ
100 kΩ
10 kΩ
36 kΩ
20 kΩ
1.1 kΩ
30 kΩ
20 kΩ
15 kΩ
68 kΩ
10 kΩ
51 kΩ
24 kΩ
100 kΩ
56 kΩ
200 kΩ
1%
1%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
KOA
KOA
ssm
ssm
ssm
ssm
ssm
ssm
ssm
ssm
ssm
ssm
ssm
ssm
ssm
ssm
ssm
ssm
ssm
SL1TTE15LOF
SL1TTE33LOF
RR0816P-333-D
RR0816P-473-D
RR0816P-104-D
RR0816P-103-D
RR0816P-363-D
RR0816P-203-D
RR0816P-112-D
RR0816P-303-D
RR0816P-203-D
RR0816P-153-D
RR0816P-683-D
RR0816P-103-D
RR0816P-513-D
RR0816P-243-D
RR0816P-104-D
RR0816P-563-D
RR0816P-204-D
MB39A125/126
47
■APPLICATION EXAMPLE 2
• MB39A126
<SOFT>
<OSC>
500 kHz Max
<Current Amp 1>
<Error Amp 2>
<PWM Comp.>
<UV Comp.>
<AC Comp.>
<Error Amp 1>
<REF> <CTL>
<OUT>
<UVLO>
C
T
VH
VREF
VREF
UVLO
Bias
Voltage
−2.5 V
−1.5 V
VREF
VCC
0.2 V
Slope
Control
Q2 I
IN
R17
51
kΩ
RS1
0.015
Ω
R18
24
kΩ
Q1
V
IN
R14
15 kΩ
R15
68 kΩ
R16
10 kΩ
R12
30 kΩ
R3
33
kΩ
R6
10 kΩ
R7
10 kΩ
C10
6800
pF
R9
36 kΩ
R10
20 kΩ
C13
22 pF C14 R1
R2
47 pF
C8
6800 pF
C6
2200 pF
(45 pF)
R13
20
kΩ
R11
SW2
1.1
kΩ
(8 V to
25 V)
to System
Q3
Battery
100 kΩ
C15
R19
56 kΩ
0.033
Ω
RS2
L1
15 µH
10 µF
C3
D1
10 µF
C4
0.1
µF
0.22
µF
C7
0.1
µF
C12
OUT
VH
VCC
XACOK
ACOK
ACIN
−INE1
−INC1
−INC1
(Vo)
+INC1
+INC2
+INE2
FB123
Hi : 4 Cells
Lo : 3 Cells
RT VREF
4.2 V
Bias
GND
CTL
C9
R4
47 kΩ
R5
100 kΩ
R8
100 kΩ
CS
5.0 V
C11
0.22 µF
10 µF
−INC2
+INE1
−INE2
OUTC1
I
CHG
R20
0.22 µF
BA
21
1857
8
10
2
13
20
19
14
12
24
9
4
A
B
1
3
15
16
22
6
(VCC −
6 V)
−INE3
SEL
17 23
−
+
−
+
+
−
+
−
+
−
−
+
×20
+
−
×20
VREF
Drive
+
−
<Error Amp 3>
4.2 V/3.15 V
11
OUTC2
<Current Amp 2> 10 µF
C1
MB39A125/126
48
■PARTS LIST 2
• MB39A126
Note : NEC : NEC Corporation
ROHM : ROHM CO., LTD.
SUMIDA : Sumida Corporation
TDK : TDK Corporation
KOA : KOA Corporation
ssm : SUSUMU CO., LTD.
COMPONENT ITEM SPECIFICATION VENDOR PARTS No.
Q1, Q2, Q3 Pch FET VDS = −30 V, ID = -7.0 A NEC µPA2714GR
D1 Diode VF = 0.42 V (Max) , At I F = 3 A ROHM RB053L-30
L1 Inductor 15 µH 3.6 A, 50 mΩSUMIDA CDRH104R-150
C1, C3, C4
C6
C7, C12
C8, C10
C9, C11
C13
C14
C15
Ceramics Cond enser
Ceramics Cond enser
Ceramics Cond enser
Ceramics Cond enser
Ceramics Cond enser
Ceramics Cond enser
Ceramics Cond enser
Ceramics Cond enser
10 µF
2200 pF
0.1 µF
6800 pF
0.22 µF
22 pF
47 pF
0.22 µF
25 V
50 V
50 V
50 V
16 V
50 V
50 V
25 V
TDK
TDK
TDK
TDK
TDK
TDK
TDK
TDK
C3225X5R1E106K
C1608JB1H222K
C1608JB1H104K
C1608JB1H682K
C1608JB1C224K
C1608CH1H220J
C1608CH1H470J
C2012JB1E224K
RS1
RS2
R3
R4
R5, R8
R6, R7
R9
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
15 mΩ
33 mΩ
33 kΩ
47 kΩ
100 kΩ
10 kΩ
36 kΩ
20 kΩ
1.1 kΩ
30 kΩ
20 kΩ
15 kΩ
68 kΩ
10 kΩ
51 kΩ
24 kΩ
100 kΩ
56 kΩ
1%
1%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
KOA
KOA
ssm
ssm
ssm
ssm
ssm
ssm
ssm
ssm
ssm
ssm
ssm
ssm
ssm
ssm
ssm
ssm
SL1TTE15LOF
SL1TTE33LOF
RR0816P-333-D
RR0816P-473-D
RR0816P-104-D
RR0816P-103-D
RR0816P-363-D
RR0816P-203-D
RR0816P-112-D
RR0816P-303-D
RR0816P-203-D
RR0816P-153-D
RR0816P-683-D
RR0816P-103-D
RR0816P-513-D
RR0816P-243-D
RR0816P-104-D
RR0816P-563-D
MB39A125/126
49
■SELECTION OF COMPONENTS
• Pch MOS FET
The Pch MOS FET f or s witching use should be rated f or at least +20% more than the input voltage. To minimize
continuity loss, use a FET with low RDS (ON) between the drain and source. For high input voltage and high
frequency operation, on-cycle s witching loss will be higher so that po wer dissipation must be considered. In this
application, the NEC µPA 2714G R is us ed. Cont inuity loss, on /off switching loss, and total loss are determined
by the following formulas. The selection must ensure that peak drain current does not exceed rated values.
Example) Using the µPA2714GR
16.8 V setting
Input voltage VIN (Max) = 25 V, output vo ltage VO = 16.8 V, drain current ID = 3 A, oscillation frequency f osc = 300 kHz,
L = 15 µH, drain-source on resistance RDS (ON) := 18 mΩ, tr := 15 ns, tf := 42 ns
Continuity loss : Pc
PC = ID2 × RDS (ON) × Duty
On-cycle s witching loss : PS (ON)
PS (ON) = VD (Max) × ID × tr × fosc
6
Off-cycle switching loss : PS (OFF)
PS (OFF) = VD (Max) × ID (Max) × tf × fosc
6
Total loss : PT
PT = PC + PS (ON) + PS (OFF)
Drain current (Max) : I D (Max)
ID (Max) = Io + VIN − Vo tON
2L
= 3 + 25 − 16.8 × 1 × 0.672
2 × 15 × 10−6300 × 103
:= 3.6 A
Drain current (Min) : ID (Min)
ID (Min) = Io−VIN − Vo tON
2L
= 3−25 − 16.8 × 1 × 0.672
2 × 15 × 10−6300 × 103
:= 2.4 A
MB39A125/126
50
The above power dissipation figures for the µPA2714GR are satisfied with ample margin at 2.0 W.
12.6 V setting
Input voltage VIN (Max) = 22 V, output vo ltage VO = 12.6 V, drain current ID = 3 A, oscillation frequency f osc = 300 kHz,
L = 15 µH, drain-source on resistance RDS (ON) := 18 mΩ, tr := 15 ns, tf := 42 ns
PC = ID2 × RDS (ON) × Duty
= 3
2 × 0.018 × 0.672
:= 0.109 W
PS (ON) = VD × ID × tr × fosc
6
= 25 × 3 × 15 × 10−9 × 300 × 103
6
:= 0.056 W
PS (OFF) = VD × ID (Max) × tf × fosc
6
= 25 × 3.6 × 42 × 10−9 × 300 × 103
6
:= 0.189 W
PT = PC + PS (ON) + PS (O FF)
:= 0.109 + 0.056 + 0.189
:= 0.354 W
Drain current (Max) : I D (Max)
ID (Max) = Io + VIN − Vo tON
2L
= 3 + 22 − 12.6 × 1 × 0.572
2 × 15 × 10−6300 × 103
:= 3.6 A
Drain current (Min) : ID (Min)
ID (Min) = Io − VIN − Vo tON
2L
= 3 − 22 − 12.6 × 1 × 0.572
2 × 15 × 10−6300 × 103
:= 2.4 A
MB39A125/126
51
The above power dissipation figures for the µPA2714GR are satisfied with ample margin at 2.0 W.
The Pch MOS FET for switching use must use the one of more than input voltage +20%.
FET which operates when the AC adapter is connected should select FET which satisfies the current decided
by sense resistance R1 enou gh. Because FET which op erates when t he A C adapter is not connected becomes
a supply by the battery, it is necessary to select FET which satisfies the current of the system enough.
In this application, the NEC µPA2714GR is used.
• Inductor
In selecting inductors, it is of course essential not to apply more current than the rated capacity of the inductor,
but also to note that the lower limit for ripple current is a critical point that if reached will cause discontinuous
operation and a considerable drop in efficiency. This can be prevent ed by choosing a higher inductance value,
which will enable continuous operation under light-loads.
Note that if the inductance v al ue is too high, ho w ev e r, direct current resistance (DCR) is increased and this will
also reduce efficiency. The inductance must be set at the point where ef ficiency is greatest.
Note also that th e DC superimposition charact eristic becomes worse as t he load curre nt value appro aches the
rated current v alue of the inductor, so that the inductance v alue is reduced and ripple current increases, causing
loss of efficiency.
The selection of rated current value and inductance value will vary depending on where the point of peak efficiency
lies with respect to load current.
Inductance values are determined by the following formulas.
The L value for all load current conditions is set so that the peak to peak value of the ripple current is 1/2 the
load current or less.
PC = ID2 × RDS (ON) × Duty
= 3
2 × 0.018 × 0.572
:= 0.093 W
PS (ON) = VD × ID × tr × fosc
6
= 22 × 3 × 15 × 10−9 × 300 × 103
6
:= 0.050 W
PS (OFF) = VD × ID (Max) × tf × fosc
6
= 22 × 3.6 × 42 × 10−9 × 300 × 103
6
:= 0.166 W
PT = PC + PS (ON) + PS (OFF)
:= 0.093 + 0.050 + 0.166
:= 0.309 W
MB39A125/126
52
16.8 V output
Example)
12.6 V output
Example)
Inductance values derived from the above formulas are values that provide sufficient margin for continuous
operation at maximum load current, but at which continuous operation is not possible at light loads. It is therefore
necessary to determine the load level at which continuous operation becomes possible. In this application, the
SUMIDA CDRH104R-150 is used . The following formula is available to o btain th e load curr en t as a co nt in uo us
current conditio n whe n 15 µH is used.
Example) Using the CDRH104R-150
15 µH (tolerance ± 30%) , rated current = 3.6 A
16.8 V output
Inductance value : L
L ≥ 2 (VIN − Vo) tON
Io
L ≥ 2 (VIN (Max) − Vo) tON
Io
≥ 2 × (25 − 16.8) × 1 × 0.672
3 300 × 103
≥ 12.2 µH
L ≥ 2 (VIN (Max) − Vo) tON
Io
≥ 2 × (22 − 12.6) × 1 × 0.572
3 300 × 103
≥ 12.0 µH
The v alue of the load cu rrent satisfying the co ntinuous current co ndition : Io
Io ≥ Vo tOFF
2L
Io ≥ Vo tOFF
2L
≥ 16.8 × 1 × (1 − 0.672)
2 × 15 × 10−6300 × 103
≥ 0.61 A
MB39A125/126
53
12.6 V output
To deter mine whether the current through the inductor is within rated values, it is necessary to deter mine the
peak value of the ripple current as well as the peak-to-peak values of the ripple current that affects the output
ripple volta ge. The peak value an d pe ak-to- pe ak value of the ripple curr en t can be det ermined by the following
formulas.
Example) Using the CDRH104R-150
15 µH (tolerance ± 30%) , rated current = 3.6 A
Peak Value
16.8 V output
12.6 V output
Io ≥ Vo tOFF
2L
≥ 12.6 × 1 × (1 − 0.572)
2 × 15 × 10−6300 × 103
≥ 0.60 A
Peak Value : IL
IL ≥ Io + VIN − Vo tON
2L
Peak-to-peak Value : ∆IL
∆IL = VIN − Vo tON
L
IL ≥ Io + VIN − Vo tON
2L
≥ 3 + 25−16.8 × 1 × 0.672
2 × 15 × 10−6300 × 103
≥ 3.6 A
IL ≥ Io + VIN − Vo tON
2L
≥ 3 + 22 − 12.6 × 1 × 0.572
2 × 15 × 10−6300 × 103
≥ 3.6 A
MB39A125/126
54
Peak-to-peak Value
16.8 V output
12.6 V output
• Flyback diode
Shottky barrier diode (SBD) is generally used f or the flybac k diode when the r e ver se volt age to the diode is less
than 40V. The SBD has the characteristics of higher speed in terms of faster reverse recover y time, and lower
f orward v oltage, and is ideal f or achie ving high ef ficiency. As long as the DC rev erse voltage is sufficiently higher
than the inpu t vo ltage, and the m ean current flo wing during the diode conduction time is within the mean ou tput
current level, and as the peak current is within the peak surge current limits, there is no problem. In this application
the ROHM RB053L-30 are used. The diode mean current and diode peak current can be obtained by the following
formulas.
Example) Using the RB053L-30
VR (DC reverse voltage) = 30 V, mean output current = 3.0 A, peak surge current = 70 A,
VF (forw ard voltage) = 0.42 V, at IF = 3.0 A
16.8 V output
∆IL = VIN − Vo tON
L
= 25 − 16.8 × 1 × 0.672
15 × 10−6300 × 103
:= 1.22 A
∆IL = VIN − Vo tON
L
= 22 − 12.6 × 1 × 0.572
15 × 10−6300 × 103
:= 1.2 A
Diode mean current : IDi
IDi ≥ Io × (1 −Vo )
VIN
Diode peak current : IDip
IDip ≥ (Io + Vo tOFF)
2L
IDi ≥ Io × (1 −Vo )
VIN
≥ 3 × (1 − 0.672)
≥ 0.984 A
MB39A125/126
55
12.6 V output
16.8 V output
12.6 V output
• Charge current se nse resistor
Please note th e following in selecting the ch arge curre nt se nse r esista nce. First of a ll, me et th e ele ctr ic power
to the flo wing current. Ho we v er, the con ve rsion efficiency deteriorat es because the loss in the sen se resistance
gro ws when resista nce is adjust ed to a t oo big value . The a ccur acy of the charge curren t det eriorates becau se
the v oltage di ff erence o f both ends of the sense resist ance becomes sma ll when resistance is adjusted to a too
small value oppositely. 33 mΩ of the K O A SL1TTE33LOF is used in this application. The sense resistance v alue
can be determined by the following formulas.
In this application, 33 mΩ of the KOA SL1TTE33LOF is used.
Example) When the +INE1 terminal (pin 9) voltage is 2 V and the charge current (Io) is 3.0 A
IDi ≥ Io × (1 −Vo )
VIN
≥ 3 × (1 − 0.572)
≥ 1.284 A
IDip ≥ (Io + Vo tOFF)
2L
≥ 3.6 A
IDip ≥ (Io + Vo tOFF)
2L
≥ 3.6 A
Sense resistor : RS2
RS2 = +INE1
20 × Io
RS2 = +INE1
20 × Io
= 2
20 × 3.0
= 33.3 mΩ
MB39A125/126
56
• Input current se nse resistor
Please note the following in selecting the input current sense resistance. First of all, meet the el ectric power to
the flowing current. However, the conversion efficiency deteriorates because the loss in the sense resistance
grows when resistance is adjusted to a too big value. The accuracy of the input current deteriorates because
the v oltage di ff erence o f both ends of the sense resist ance becomes sma ll when resistance is adjusted to a too
small value oppositely. 33 mΩ of the K O A SL1TTE33LOF is used in this application. The sense resistance v alue
can be determined by the following formulas.
In this application, 15 mΩ of the KOA SL1TTE15LOF is used.
Example) When the +INE2 terminal (pin 3) voltage is 1.79 V and the input current (IIN) is 6.0 A
Sense resistor : RS1
RS1 = +INE2
20 × IIN
RS1 = +INE2
20 × IIN
= 1.79
20 × 6.0
= 14.9 mΩ
MB39A125/126
57
■REFERENCE DATA
(Continued)
50
55
60
65
70
75
80
85
90
95
100
VIN = 19 V
Vo = 16.8 V setting
100.10.01 1 50
55
60
65
70
75
80
85
90
95
100
VIN = 19 V
Vo = 12.6 V setting
100.10.01 1
50
55
60
65
70
75
80
85
90
95
100
VIN = 19 V
Io = 3 A setting
1824 80 6 10 12 14 16 50
55
60
65
70
75
80
85
90
95
100
VIN = 19 V
Io = 3 A setting
1824 80 6 10 12 14 16
0
2
4
6
8
10
12
14
16
18
20
VIN = 19 V
Vo = 16.8 V setting
0.5 1.0 1.5 2.0 2.5 3.0 4.03.50.0
SW2 = ON SW2 = OFF
0
2
4
6
8
10
12
14
16
18
20 VIN = 19 V
Vo = 12.6 V setting
0.5 1.0 1.5 2.0 2.5 3.0 4.03.50.0
SW2 = ON SW2 = OFF
Conversion efficiency vs. Charging current
(Constant Voltage mode)
Conversion efficiency η (%)
Charging current IO (A)
Conversion efficiency vs. Charging current
(Constant Vo ltage mode)
Conversion efficiency η (%)
Charging current IO (A)
Conversion efficiency vs. Charging voltage
(Constant Current mode)
Conversion efficiency η (%)
Charging voltage VO (V)
Conversion efficiency vs. Charging voltage
(Constant Current mode)
Conversion efficiency η (%)
Charging voltage VO (V)
Charging voltage vs. Charging current
Charging voltage VO (V)
Charging current IO (A)
Charging voltage vs. Charging current
Charging voltage VO (V)
Charging current IO (A)
MB39A125/126
58
(Continued)
0 1.0 2.0
OUT
(V)
15
10
5
0
Pch
Drain
(V)10
5
0
3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 (µs)
0 1.0 2.0
OUT
(V)
15
10
5
0
Pch
Drain
(V)10
5
0
3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 (µs)
0 1.0 2.0
OUT
(V)
15
10
5
0
Pch
Drain
(V)10
5
0
3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 (µs)
0 1.0 2.0
OUT
(V)
15
10
5
0
Pch
Drain
(V)10
5
0
3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 (µs)
OUT
OUT
OUT
OUT
Pch
Drain
Pch
Drain
Pch
Drain
Pch
Drain
V
IN
=
19 V
Vo
=
16.8 V setting
Io
=
1.5 A
SW2
=
OFF
V
IN =
19 V
Vo
=
10.0 V
Io
=
3.0 A setting
SW2
=
OFF
VIN = 19 V
Vo = 12.6 V setting
Io = 1.5 A
SW2 = OFF
V
IN =
19 V
Vo
=
10.0 V
Io
=
3.0 A setting
SW2
=
OFF
VO = 12.6 V setting VO = 16.8 V setting
Switching waveform (Constant Voltage M od e)
VO = 12.6 V setting VO = 16.8 V setting
Switching waveform (Constant Curren t Mo de)
MB39A125/126
59
(Continued)
0510
lo
(A)
5
4
3
2
1
0
Vo
(V)
18
16
14
12
10
CTL
(V)
10
0
15 20 25 30 35 40 45 50 (ms)
0510
lo
(A)
5
4
3
2
1
0
Vo
(V)
18
16
14
12
10
CTL
(V)
10
0
15 20 25 30 35 40 45 50 (ms)
0510
lo
(A)
5
4
3
2
1
0
Vo
(V)
18
16
14
12
10
CTL
(V)
10
0
15 20 25 30 35 40 45 50 (ms)
0510
lo
(A)
5
4
3
2
1
0
Vo
(V)
18
16
14
12
10
CTL
(V)
10
0
15 20 25 30 35 40 45 50 (ms)
VIN = 19 V
Io = 3 A setting
SW2 = OFF
CTL
lo
Vo
VIN = 19 V
Vo = 16.8 V setting
SW2 = OFF
lo
Vo
VIN = 19 V
Io = 3 A setting
SW2 = OFF
CTL
lo
Vo
VIN = 19 V
Vo = 16.8 V setting
SW2 = OFF
CTL
lo
Vo
CTL
Soft-start operating waveform (Constant Current Mode)
Soft-start oper ating waveform (Constant Voltage Mode)
MB39A125/126
60
(Continued)
0 2 4 6 8 10 12 14 16 18 20(ms)
Vo (V)
18
16
14
3
2
Io (A)
1
0Io
4
5
6
12
10
Io
0 2 4 6 8 10 12 14 16 18 20(ms)
Vo (V)
18
16
14
3
2
Io (A)
1
0
Io
4
5
6
12
10
0 2 4 6 8 10 12 14 16 18 20(ms)
Vo (V)
18
16
14
3
2
Io (A)
1
0Io
4
5
6
12
10
02468101214161820
(ms)
Vo (V)
18
16
14
3
2
Io (A)
1
0
Io
4
5
6
12
10
Vo
Vo Vo
Vo
Vo
Vo
Io
Vo
Vo
Io
Io
VIN = 19 V
Io = 3.0 A setting
SW2 = OFF
CV to CC
VIN = 19 V
Io = 3.0 A setting
SW2 = OFF
CC to CV
VIN = 19 V
Vo = 16.8 V setting
SW2 = OFF
CV to CV
VIN = 19 V
Vo = 16.8 V setting
SW2 = OFF
CV to CV
Load-step response operation waveform
(C.V mode → C.C mode) Load-step response operation waveform
(C.C mode → C.V mode)
Load-step response operation waveform
(C.V mode → C.V mode ) Load-step response operation waveform
(C.V mode → C.V mode)
MB39A125/126
61
■USAGE PRECAUTIONS
• Printed circuit board ground lines should be set up with consideration for common impedance.
• Take appropriate static electricity measures.
• Containers for semiconducto r mat erials should ha ve ant i-st at ic prot ectio n o r be mad e of conduct ive material.
• After mounting, printed circuit board s sh ou ld be st ored and shipped in conductive bags or cont ainers.
• Work platforms, tools, and instruments should be properly grounded.
• Working personnel should be grounded with r esistance of 250 kΩ to 1 MΩ between body and ground.
• Do not apply negative voltages.
• The use of negative voltages below −0.3 V may create parasitic transistors on LSI lines, which can cause
abnormal operation.
■ORDERING IN FORMATION
Part number Pac kage Remarks
MB39A125PFV 24-pin plastic SSOP
(FPT-24P-M03)
MB39A125WQN 28-pin plastic QFN
(LCC-28P-M11)
MB39A126PFV 24-pin plastic SSOP
(FPT-24P-M03)
MB39A126WQN 28-pin plastic QFN
(LCC-28P-M11)
MB39A125/126
62
■PACKAGE DIMENSIONS
(Continued)
24-pin plastic SSOP
(FPT-24P-M03)
Note 1) *1 : Resin protrusion. (Each side : +0.15 (.006) Max).
Note 2) *2 : These dim e nsio n s do not inc lud e re sin pro tr usio n .
Note 3) Pins width and pins thickness include plating t hickness.
Note 4) Pins width do no t include tie bar cutting remainder.
Dimensions in mm (inches).
Note: The valu es in pa re n th ese s ar e re fe re nc e va lue s .
C
2003 FUJITSU LIMITED F24018S-c-4-5
7.75±0.10(.305±.004)
5.60±0.10 7.60±0.20
(.220±.004) (.299±.008)
*1
*2
0.10(.004)
112
1324
0.65(.026) –0.07
+0.08
0.24
.009 +.003
–.003 M
0.13(.005)
INDEX
0.17±0.03
(.007±.001)
"A"
0.25(.010)
0.10±0.10
(.004±.004)
(Stand off)
Details of "A" part
(Mounting height)
1.25 +0.20
–0.10
–.004
+.008
.049
0~8˚
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
0.10(.004)
MB39A125/126
63
(Continued)
28-pin plastic QFN
(LCC-28P-M11)
Dimensions in mm (inches).
Note: The values in parenthese s are reference values.
C
2004 FUJITSU LIMITED C28068Sc-2-1
(.197±.004)
5.00±0.10
0.08(.003)
(.138±.004)
5.00±0.10
(.197±.004) 3.50±0.10
3.50±0.10
(.138±.004)
3-R0.20
(3-R.008)
0.50(.020)
TYP
(.016±.004)
0.40±0.10
1PIN CORNER
(C0.30(C.012))
0.25±0.10
(.010±.004)
MAX
0.80(.032)
0.20(.008)
INDEX AREA
.0008
0.02+.002
–.0008
–0.02
+0.05
FUJITSU MICROELECTRONICS LIMITED
Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku,
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For further information please contact:
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Tel: +49-6103-690-0 Fax: +49-6103-690-122
http://emea.fujitsu.com/microelectronics/
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Korea
Tel: +82-2-3484-7100 Fax: +82-2-3484-7111
http://www.fmk.fujitsu.com/
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FUJITSU MICROELECTRONICS ASIA PTE LTD.
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http://www.fujitsu.com/sg/services/micro/semiconductor/
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Tsimshatsui, Kowloon
Hong Kong
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The contents of this document are subject to change without notice.
Customers are advised to consult with sales representatives before ordering.
The information, such as descriptions of function and application circuit examples, in this document are presented solely for the purpose
of reference to show examples of operations and uses of FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS
does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporat-
ing the device based on such information, you must assume any responsibility arising out of such use of the information.
FUJITSU MICROELECTRONICS assumes no liability for any damages whatsoever arising out of the use of the information.
Any information in this document, including descriptions of function and schematic diagrams, shall not be construed as license of the use
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or any third party or does FUJITSU MICROELECTRONICS warrant non-infringement of any third-party's intellectual property right or
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limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and manufactured
as contemplated (1) for use accompanying fatal risks or dangers that, unless extremely high safety is secured, could have a serious effect
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Please note that FUJITSU MICROELECTRONICS will not be liable against you and/or any third party for any claims or damages arising
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Any semiconductor devices have an inherent chance of failure. You must protect against injury, damage or loss from such failures by
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levels and other abnormal operating conditions.
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