NT5DS32M4AT NT5DS32M4AW
NT5DS16M8AT NT5DS16M8AW
128Mb DDR333/300 SDRAM
Preliminary
08/01 1
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Features
•Double data rate architecture: two data transfers per
clock cycle
•Bidirectional data strobe (DQS) is transmitted and
received with data, to be used in capturing data at the
receiver
•DQS is edge-aligned with data for reads and is center-
aligned with data for writes
•Differential clock inputs (CK and CK)
•Four internal banks for concurrent operation
•Data mask (DM) for write data
•DLL aligns DQ and DQS transitions with CK transitions,
also aligns QFC transitions with CK during Read cycles
•Commands entered on each positive CK edge; data and
data mask referenced to both edges of DQS
•Burst lengths: 2, 4, or 8
•CAS Latency: 2, 2.5
•Auto Precharge option for each burst access
•Auto Refresh and Self Refresh Modes
•15.6µs Maximum Average Periodic Refresh Interval
•2.5V (SSTL_2 compatible) I/O
•VDDQ = 2.5V ± 0.2V
•VDD = 2.5V ± 0.2V
•For -6 speed grade : Support PC2700 modules.
•For -66 speed grade : Support PC2400 modules
•Package :
- 66pin TSOP-II
- 60ball 0.8mmx1.0mm pitch CSP
Description
The 128Mb DDR SDRAM is a high-speed CMOS, dynamic
random-access memory containing 134,217,728 bits. It is
internally configured as a quad-bank DRAM.
The 128Mb DDR SDRAM uses a double-data-rate architec-
ture to achieve high-speed operation. The double data rate
architecture is essentially a 2n prefetch architecture with an
interface designed to transfer two data words per clock cycle
at the I/O pins. A single read or write access for the 128Mb
DDR SDRAM effectively consists of a single 2n-bit wide, one
clock cycle data transfer at the internal DRAM core and two
corresponding n-bit wide, one-half-clock-cycle data transfers
at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally,
along with data, for use in data capture at the receiver. DQS
is a strobe transmitted by the DDR SDRAM during Reads
and by the memory controller during Writes. DQS is edge-
aligned with data for Reads and center-aligned with data for
Writes.
The 128Mb DDR SDRAM operates from a differential clock
(CK and CK; the crossing of CK going high and CK going
LOW is referred to as the positive edge of CK). Commands
(address and control signals) are registered at every positive
edge of CK. Input data is registered on both edges of DQS,
and output data is referenced to both edges of DQS, as well
as to both edges of CK.
Read and write accesses to the DDR SDRAM are burst ori-
ented; accesses start at a selected location and continue for
a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an Active
command, which is then followed by a Read or Write com-
mand. The address bits registered coincident with the Active
command are used to select the bank and row to be
accessed. The address bits registered coincident with the
Read or Write command are used to select the bank and the
starting column location for the burst access.
The DDR SDRAM provides for programmable Read or Write
burst lengths of 2, 4 or 8 locations. An Auto Precharge func-
tion may be enabled to provide a self-timed row precharge
that is initiated at the end of the burst access.
As with standard SDRAMs, the pipelined, multibank architec-
ture of DDR SDRAMs allows for concurrent operation,
thereby providing high effective bandwidth by hiding row pre-
charge and activation time.
An auto refresh mode is provided along with a power-saving
power-down mode. All inputs are compatible with the JEDEC
Standard for SSTL_2. All outputs are SSTL_2, Class II com-
patible.
CAS Latency and Frequency
CAS Latency Maximum Operating Frequency (MHz)*
DDR333
(-6) DDR300
(-66)
2133 133
2.5 166 150
* Values are nominal (exact tCK should be used).
NT5DS32M4AT NT5DS32M4AW
NT5DS16M8AT NT5DS16M8AW
128Mb DDR333/300 SDRAM
Preliminary
08/01 2
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Pin Configuration - 400mil TSOP II
1
2
3
4
5
6
9
10
11
12
13
14
7
8
15
16
17
18
19
20
21
22
66
65
64
63
62
61
58
57
56
55
54
53
60
59
52
51
50
49
48
47
46
45
23
24
25
44
43
42
26
27 41
40
28
29
30
31
32
33
39
38
37
36
35
34
VDD
DQ0
VDDQ
NC
DQ1
VSSQ
VDDQ
NC
DQ3
VSSQ
NC
NC
NC
DQ2
VDDQ
NC
NC
VDD
DNU
NC
WE
CAS
RAS
CS
NC
BA0
BA1
VSS
DQ7
VSSQ
NC
DQ6
VDDQ
VSSQ
NC
DQ4
VDDQ
NC
NC
NC
DQ5
VSSQ
DQS
NC
VREF
VSS
DM*
CK
CK
CKE
NC
NC
A11
A9
VDD
NC
VDDQ
NC
DQ0
VSSQ
VDDQ
NC
DQ1
VSSQ
NC
NC
NC
NC
VDDQ
NC
NC
VDD
DNU
NC
WE
CAS
RAS
CS
NC
BA0
BA1
VSS
NC
VSSQ
NC
DQ3
VDDQ
VSSQ
NC
DQ2
VDDQ
NC
NC
NC
NC
VSSQ
DQS
NC
VREF
VSS
DM*
CK
CK
CKE
NC
NC
A11
A9
A10/AP
A0
A1
A2
A3
VDD
A10/AP
A0
A1
A2
A3
VDD
A8
A7
A6
A5
A4
VSS
A8
A7
A6
A5
A4
VSS
Column Address Table
Organization Column Address
32Mb x 4 A0-A9, A11
16Mb x 8 A0-A9
*DM is internally loaded to match DQ and DQS identically.
NT5DS32M4AT
NT5DS16M8AT
32Mb x 4
16Mb x 8
66-pin Plastic TSOP-II 400mil
NT5DS32M4AT NT5DS32M4AW
NT5DS16M8AT NT5DS16M8AW
128Mb DDR333/300 SDRAM
Preliminary
08/01 3
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Pin Configuration - 60 ball ; 0.8mmx1.0mm Pitch ; CSP
A
B
C
D
E
F
G
H
J
K
L
M
A
B
C
D
E
F
G
H
J
K
L
M
32 X 4
16 X 8
1
VSSQ
NC
NC
NC
NC
VREF
NC
VDDQ
VSSQ
VDDQ
VSSQ
VSS
CLK
NC
A11
A8
A6
A4
2
VSS
DQ3
NC
DQ2
DQS
DQM
CLK
CKE
A9
A7
A5
VSS
3
VDD
DQ0
NC
DQ1
DNU
NC
WE
RAS
BA1
A0
A2
VDD
7
NC
VSSQ
VDDQ
VSSQ
VDDQ
VDD
CAS
CS
BA0
A10/AP
A1
A3
8
VDDQ
NC
NC
NC
NC
NC
9
VSSQ
NC
NC
NC
NC
VREF
1
DQ7
VDDQ
VSSQ
VDDQ
VSSQ
VSS
CLK
NC
A11
A8
A6
A4
2
VSS
DQ6
DQ5
DQ4
DQS
DQM
CLK
CKE
A9
A7
A5
VSS
3
VDD
DQ1
DQ2
DQ3
DNU
NC
WE
RAS
BA1
A0
A2
VDD
7
DQ0
VSSQ
VDDQ
VSSQ
VDDQ
VDD
CAS
CS
BA0
A10/AP
A1
A3
8
VDDQ
NC
NC
NC
NC
NC
9
NT5DS32M4AT NT5DS32M4AW
NT5DS16M8AT NT5DS16M8AW
128Mb DDR333/300 SDRAM
Preliminary
08/01 4
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Input/Output Functional Description
Symbol Type Function
CK, CK Input Clock: CK and CK are differential clock inputs. All address and control input signals are sampled
on the crossing of the positive edge of CK and negative edge of CK. Output (read) data is refer-
enced to the crossings of CK and CK (both directions of crossing).
CKE Input
Clock Enable: CKE HIGH activates, and CKE Low deactivates, internal clock signals and device
input buffers and output drivers. Taking CKE Low provides Precharge Power-Down and Self
Refresh operation (all banks idle), or Active Power-Down (row Active in any bank). CKE is syn-
chronous for power down entry and exit, and for self refresh entry. CKE is asynchronous for self
refresh exit. CKE must be maintained high throughout read and write accesses. Input buffers,
excluding CK, CK and CKE are disabled during power-down. Input buffers, excluding CKE, are
disabled during self refresh.
CS Input Chip Select: All commands are masked when CS is registered high. CS provides for external
bank selection on systems with multiple banks. CS is considered part of the command code.
RAS, CAS, WE Input Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.
DM Input
Input Data Mask: DM is an input mask signal for write data. Input data is masked when DM is
sampled high coincident with that input data during a Write access. DM is sampled on both edges
of DQS. Although DM pins are input only, the DM loading matches the DQ and DQS loading.Dur-
ing a Read, DM can be driven high, low, or floated.
BA0, BA1 Input Bank Address Inputs: BA0 and BA1 define to which bank an Active, Read, Write or Precharge
command is being applied. BA0 and BA1 also determines if the mode register or extended mode
register is to be accessed during a MRS or EMRS cycle.
A0 - A11 Input
Address Inputs: Provide the row address for Active commands, and the column address and
Auto Precharge bit for Read/Write commands, to select one location out of the memory array in
the respective bank. A10 is sampled during a Precharge command to determine whether the Pre-
charge applies to one bank (A10 low) or all banks (A10 high). If only one bank is to be precharged,
the bank is selected by BA0, BA1. The address inputs also provide the op-code during a Mode
Register Set command.
DQ Input/Output Data Input/Output: Data bus.
DQS Input/Output Data Strobe: Output with read data, input with write data. Edge-aligned with read data, centered
in write data. Used to capture write data.
NC No Connect: No internal electrical connection is present.
DNU Electrical connection is present. Should not be connected at second level of assembly.
VDDQ Supply DQ Power Supply: 2.5V ± 0.2V.
VSSQ Supply DQ Ground
VDD Supply Power Supply: 2.5V ± 0.2V.
VSS Supply Ground
VREF Supply SSTL_2 reference voltage: (VDDQ / 2) ± 1%.
NT5DS32M4AT NT5DS32M4AW
NT5DS16M8AT NT5DS16M8AW
128Mb DDR333/300 SDRAM
Preliminary
08/01 5
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Ordering Information
Part Number Org. CAS
Latency Clock
(MHz) CAS
Latency Clock
(MHz) Speed Package
NT5DS32M4AT-6 x 4 2.5 166 2133 DDR333
66 pin TSOP-II
NT5DS16M8AT-6 x 8
NT5DS32M4AT-66 x 4 2.5 150 2133 DDR300
NT5DS16M8AT-66 x 8
NT5DS32M4AW-6 x 4 2.5 166 2133 DDR333
60 ball CSP
NT5DS16M8AW-6 x 8
NT5DS32M4AW-66 x 4 2.5 150 2133 DDR300
NT5DS16M8AW-66 x 8
NT5DS32M4AT NT5DS32M4AW
NT5DS16M8AT NT5DS16M8AW
128Mb DDR333/300 SDRAM
Preliminary
08/01 6
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Block Diagram (32Mb x 4)
Receivers
1
DQS
Clk
DLL
RAS
CAS
CK
CSn
WE
CK
Control Logic
Column-Address
Counter/Latch
Mode
11
Command
Decode
A0-A11,
BA0, BA1
CKEn
12
14
I/O Gating
DM Mask Logic
Bank0
Memory
Array
(4096 x 1024 x 8)
Sense Amplifiers
Bank1 Bank2 Bank3
12
10
1
2
2
Refresh Counter
4
44
Input
Register1
1
1
11
8
8
2
8
clk
out
Data
Mask
Data
Clk
COLo
COLo
COLo
clk
in
MUX
DQS
Generator
4
4
4
44
8
DQ0-DQ3,
DM
DQS
1
Read Latch
Write
FIFO
&
Drivers
Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of
the device; it does not represent an actual circuit implementation.
Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidi-
rectional DQ and DQS signals.
Column
Decoder
1024
(x8)
Row-Address MUX
Registers
12
8192
Bank0
Row-Address Latch
& Decoder
4096
Address Register
Drivers
Bank Control Logic
NT5DS32M4AT NT5DS32M4AW
NT5DS16M8AT NT5DS16M8AW
128Mb DDR333/300 SDRAM
Preliminary
08/01 7
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Block Diagram (16Mb x 8)
Receivers
1
DQS
Clk
DLL
RAS
CAS
CK
CSn
WE
CK
Control Logic
Column-Address
Counter/Latch
Mode
10
Command
Decode
A0-A11,
BA0, BA1
CKEn
12
14
I/O Gating
DM Mask Logic
Bank0
Memory
Array
(4096 x 512 x 16)
Sense Amplifiers
Bank1 Bank2 Bank3
12
9
1
2
2
Refresh Counter
8
88
Input
Register1
1
1
11
16
16
2
16
clk
out
Data
Mask
Data
Clk
COLo
COLo
COLo
clk
in
MUX
DQS
Generator
8
8
8
88
16
DQ0-DQ7,
DM
DQS
1
Read Latch
Write
FIFO
&
Drivers
Note: This Functional Block Diagram is intended to facilitate user understanding of the operation of
the device; it does not represent an actual circuit implementation.
Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the bidi-
rectional DQ and DQS signals.
Column
Decoder
512
(x8)
Row-Address MUX
Registers
12
8192
Bank0
Row-Address Latch
& Decoder
4096
Address Register
Drivers
Bank Control Logic
NT5DS32M4AT NT5DS32M4AW
NT5DS16M8AT NT5DS16M8AW
128Mb DDR333/300 SDRAM
Preliminary
08/01 8
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Mode Register Operation
A8 A7 A6 A5 A4
CAS Latency
A3 A2 A1 A0
Burst LengthBT
Address Bus
CAS Latency
A6 A5 A4 Latency
0 0 0 Reserved
0 0 1 Reserved
0 1 0 2
0 1 1 Reserved
1 0 0 Reserved
1 0 1 Reserved
1 1 0 2.5
1 1 1 Reserved
Burst Length
A2 A1 A0 Burst Length
000 Reserved
0 0 1 2
0 1 0 4
0 1 1 8
100 Reserved
101 Reserved
110 Reserved
111 Reserved
BA1 BA0 A11 A10 A9
0* 0* Mode Register
Operating Mode
* BA0 and BA1 must be 0, 0 to select the Mode Register
(vs. the Extended Mode Register).
A11 - A9 A8 A7 A6 - A0 Operating Mode
0 0 0 Valid Normal operation
Do not reset DLL
0 1 0 Valid Normal operation
in DLL Reset
0 0 1 VS** Vendor-Specific
Test Mode
− − − Reserved
A3 Burst
Type
0Sequential
1Interleave
VS** Vendor Specific
NT5DS32M4AT NT5DS32M4AW
NT5DS16M8AT NT5DS16M8AW
128Mb DDR333/300 SDRAM
Preliminary
08/01 9
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Notes:
1. For a burst length of two, A1-A i selects the two-data-element block; A0 selects the first access within the block.
2. For a burst length of four, A2-A i selects the four-data-element block; A0-A1 selects the first access within the block.
3. For a burst length of eight, A3-A i selects the eight-data- element block; A0-A2 selects the first access within the block.
4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block.
Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type
and is selected via bit A3. The ordering of accesses within a burst is determined by the burst length, the burst type and the start-
ing column address, as shown in Burst Definition on page 9.
Read Latency
The Read latency, or CAS latency, is the delay, in clock cycles, between the registration of a Read command and the availability
of the first burst of output data. The latency can be programmed 2 or 2.5 clocks.
If a Read command is registered at clock edge n, and the latency is m clocks, the data is available nominally coincident with
clock edge n + m.
Reserved states should not be used as unknown operation or incompatibility with future versions may result.
Burst Definition
Burst Length Starting Column Address Order of Accesses Within a Burst
A2 A1 A0 Type = Sequential Type = Interleaved
20 0-1 0-1
11-0 1-0
4
0 0 0-1-2-3 0-1-2-3
0 1 1-2-3-0 1-0-3-2
1 0 2-3-0-1 2-3-0-1
1 1 3-0-1-2 3-2-1-0
8
0 0 0 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7
0 0 1 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6
0 1 0 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5
0 1 1 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4
1 0 0 4-5-6-7-0-1-2-3 4-5-6-7-0-1-2-3
1 0 1 5-6-7-0-1-2-3-4 5-4-7-6-1-0-3-2
1 1 0 6-7-0-1-2-3-4-5 6-7-4-5-2-3-0-1
1 1 1 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0
NT5DS32M4AT NT5DS32M4AW
NT5DS16M8AT NT5DS16M8AW
128Mb DDR333/300 SDRAM
Preliminary
08/01 10
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Extended Mode Register Definition
A8A7A6A5A4A3A2A1A0Address Bus
Drive Strength
A1Drive Strength
0Normal
1Reserved
BA1 BA0
Operating Mode
A11 A10 A9
0*1*
* BA0 and BA1 must be 1, 0 to select the Extended Mode Register
Mode Register
Extended
DS DLL
A0DLL
0Enable
1Disable
A11 - A3 A2 - A0 Operating Mode
0Valid Normal Operation
− − All other states
Reserved
(vs. the base Mode Register)
QFC
A2QFC
0Disable
1Enable
(Optional)
NT5DS32M4AT NT5DS32M4AW
NT5DS16M8AT NT5DS16M8AW
128Mb DDR333/300 SDRAM
Preliminary
08/01 11
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NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Commands
Truth Tables 1a and 1b provide a reference of the commands supported by DDR SDRAM devices. A verbal description of each
commands follows.
Auto Precharge
Auto Precharge is a feature which performs the same individual-bank precharge function described above, but without requiring
an explicit command. This is accomplished by using A10 to enable Auto Precharge in conjunction with a specific Read or Write
command. A precharge of the bank/row that is addressed with the Read or Write command is automatically performed upon
completion of the Read or Write burst. Auto Precharge is nonpersistent in that it is either enabled or disabled for each individual
Read or Write command. Auto Precharge ensures that the precharge is initiated at the earliest valid stage within a burst. This is
determined as if an explicit Precharge command was issued at the earliest possible time without violating tRAS(min). The user
must not issue another command to the same bank until the precharge (tRP) is completed.
The NTC DDR SDRAM devices supports the optional tRAS lockout feature. This feature allows a Read command with Auto Pre-
Truth Table 1a: Commands
Name (Function) CS RAS CAS WE Address MNE Notes
Deselect (Nop) HX X X X NOP 1, 9
No Operation (Nop) LH H H XNOP 1, 9
Active (Select Bank And Activate Row) L L H H Bank/Row ACT 1, 3
Read (Select Bank And Column, And Start Read Burst) LHLHBank/Col Read 1, 4
Write (Select Bank And Column, And Start Write Burst) LHL L Bank/Col Write 1, 4
Burst Terminate LH H LXBST 1, 8
Precharge (Deactivate Row In Bank Or Banks) L L HLCode PRE 1, 5
Auto Refresh Or Self Refresh (Enter Self Refresh Mode) L L L HXAR / SR 1, 6, 7
Mode Register Set L L L L Op-Code MRS 1, 2
1. CKE is high for all commands shown except Self Refresh.
2. BA0, BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode Register; BA0 = 1, BA1 = 0 selects
Extended Mode Register; other combinations of BA0-BA1 are reserved; A0-A11 provide the op-code to be written to the selected Mode
Register.)
3. BA0-BA1 provide bank address and A0-A11 provide row address.
4. BA0, BA1 provide bank address; A0-Ai provide column address (where i = 9 for x8 and 9, 11 for x4); A10 high enables the Auto Pre-
charge feature (nonpersistent), A10 low disables the Auto Precharge feature.
5. A10 LOW: BA0, BA1 determine which bank is precharged.
A10 HIGH: all banks are precharged and BA0, BA1 are “Don’t Care.”
6. This command is auto refresh if CKE is high; Self Refresh if CKE is low.
7. Internal refresh counter controls row and bank addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8. Applies only to read bursts with Auto Precharge disabled; this command is undefined (and should not be used) for read bursts with Auto
Precharge enabled or for write bursts
9. Deselect and NOP are functionally interchangeable.
Truth Table 1b: DM Operation
Name (Function) DM DQs Notes
Write Enable L Valid 1
Write Inhibit H X1
1. Used to mask write data; provided coincident with the corresponding data.
NT5DS32M4AT NT5DS32M4AW
NT5DS16M8AT NT5DS16M8AW
128Mb DDR333/300 SDRAM
Preliminary
08/01 12
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charge to be issued to a bank that has been activated (opened) but has not yet satisfied the tRAS(min) specification. The tRAS
Truth Table 2: Clock Enable (CKE)
1. CKE n is the logic state of CKE at clock edge n: CKE n-1 was the state of CKE at the previous clock edge.
2. Current state is the state of the DDR SDRAM immediately prior to clock edge n.
3. Command n is the command registered at clock edge n, and action n is a result of command n.
4. All states and sequences not shown are illegal or reserved.
Current State
CKE n-1 CKEn
Command n Action n Notes
Previous
Cycle Current
Cycle
Self Refresh L L XMaintain Self-Refresh
Self Refresh LHDeselect or NOP Exit Self-Refresh 1
Power Down L L XMaintain Power-Down
Power Down LHDeselect or NOP Exit Power-Down
All Banks Idle HLDeselect or NOP Precharge Power-Down Entry
All Banks Idle HLAuto Refresh Self Refresh Entry
Bank(s) Active HLDeselect or NOP Active Power-Down Entry
H H See “Truth Table 3: Current State
Bank n - Command to Bank n (Same
Bank)” on page 13
1. Deselect or NOP commands should be issued on any clock edges occurring during the Self Refresh Exit (tXSNR) period. A minimum of
200 clock cycles are needed before applying a read command to allow the DLL to lock to the input clock.
NT5DS32M4AT NT5DS32M4AW
NT5DS16M8AT NT5DS16M8AW
128Mb DDR333/300 SDRAM
Preliminary
08/01 13
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Truth Table 3: Current State Bank n - Command to Bank n (Same Bank)
Current State CS RAS CAS WE Command Action Notes
Any HXXX Deselect NOP. Continue previous operation 1-6
LHHH No Operation NOP. Continue previous operation 1-6
Idle
L L H H Active Select and activate row 1-6
LLLHAuto Refresh 1-7
LLLL Mode Register Set 1-7
Row Active
LHLHRead Select column and start Read burst 1-6, 10
LHL L Write Select column and start Write burst 1-6, 10
L L HLPrecharge Deactivate row in bank(s) 1-6, 8
Read
(Auto Precharge
Disabled)
LHLHRead Select column and start new Read burst 1-6, 10
L L HLPrecharge Truncate Read burst, start Precharge 1-6, 8
LH H LBurst Terminate Burst Terminate 1-6, 9
Write
(Auto Precharge
Disabled)
LHLHRead Select column and start Read burst 1-6, 10, 11
LHL L Write Select column and start Write burst 1-6, 10
L L HLPrecharge Truncate Write burst, start Precharge 1-6, 8, 11
1. This table applies when CKE n-1 was high and CKE n is high (see Truth Table 2: Clock Enable (CKE) and after tXSNR / tXSRD has been
met (if the previous state was self refresh).
2. This table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown are those allowed
to be issued to that bank when in that state. Exceptions are covered in the notes below.
3. Current state definitions:
Idle: The bank has been precharged, and tRP has been met.
Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in
progress.
Read: A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
Write: A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
4. The following states must not be interrupted by a command issued to the same bank.
Precharging: Starts with registration of a Precharge command and ends when tRP is met. Once tRP is met, the bank is in the idle
state.
Row Activating: Starts with registration of an Active command and ends when tRCD is met. Once tRCD is met, the bank is in the “row
active” state.
Read w/Auto Precharge Enabled: Starts with registration of a Read command with Auto Precharge enabled and ends when tRP has been
met. Once tRP is met, the bank is in the idle state.
Write w/Auto Precharge Enabled: Starts with registration of a Write command with Auto Precharge enabled and ends when tRP has been
met. Once tRP is met, the bank is in the idle state.
Deselect or NOP commands, or allowable commands to the other bank should be issued on any clock edge occurring during these
states. Allowable commands to the other bank are determined by its current state and according to Truth Table 4.
5. The following states must not be interrupted by any executable command; Deselect or NOP commands must be applied on each positive
clock edge during these states.
Refreshing: Starts with registration of an Auto Refresh command and ends when tRFC is met. Once tRFC is met, the DDR SDRAM is
in the “all banks idle” state.
Accessing Mode Register: Starts with registration of a Mode Register Set command and ends when tMRD has been met. Once tMRD is
met, the DDR SDRAM is in the “all banks idle” state.
Precharging All: Starts with registration of a Precharge All command and ends when tRP is met. Once tRP is met, all banks is in the idle
state.
6. All states and sequences not shown are illegal or reserved.
7. Not bank-specific; requires that all banks are idle.
8. May or may not be bank-specific; if all/any banks are to be precharged, all/any must be in a valid state for precharging.
9. Not bank-specific; Burst terminate affects the most recent Read burst, regardless of bank.
10. Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with
Auto Precharge disabled.
11. Requires appropriate DM masking.
NT5DS32M4AT NT5DS32M4AW
NT5DS16M8AT NT5DS16M8AW
128Mb DDR333/300 SDRAM
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Truth Table 4: Current State Bank n - Command to Bank m (Different bank)
(Part 1 of 2)
Current State CS RAS CAS WE Command Action Notes
Any HX X X Deselect NOP/continue previous operation 1-6
LH H H No Operation NOP/continue previous operation 1-6
Idle X X X X Any Command Otherwise
Allowed to Bank m 1-6
Row Activating,
Active, or
Precharging
L L H H Active Select and activate row 1-6
LHLHRead Select column and start Read burst 1-7
LHL L Write Select column and start Write burst 1-7
L L HLPrecharge 1-6
Read
(Auto Precharge
Disabled)
L L H H Active Select and activate row 1-6
LHLHRead Select column and start new Read burst 1-7
L L HLPrecharge 1-6
Write
(Auto Precharge
Disabled)
L L H H Active Select and activate row 1-6
LHLHRead Select column and start Read burst 1-8
LHL L Write Select column and start new Write burst 1-7
L L HLPrecharge 1-6
1. This table applies when CKE n-1 was high and CKE n is high (see Truth Table 2: Clock Enable (CKE) and after tXSNR / tXSRD has been
met (if the previous state was self refresh).
2. This table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands shown are
those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are cov-
ered in the notes below.
3. Current state definitions:
Idle: The bank has been precharged, and tRP has been met.
Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are
in progress.
Read: A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
Write: A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
Read with Auto Precharge Enabled: See note 10.
Write with Auto Precharge Enabled: See note 10.
4. Auto Refresh and Mode Register Set commands may only be issued when all banks are idle.
5. A Burst Terminate command cannot be issued to another bank; it applies to the bank represented by the current state only.
6. All states and sequences not shown are illegal or reserved.
7. Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with
Auto Precharge disabled.
8. Requires appropriate DM masking.
9. A Write command may be applied after the completion of data output.
10. The Read with Auto Precharge enabled or Write with Auto Precharge enabled states can each be broken into two parts: the access
period and the precharge period. For Read with Auto Precharge, the precharge period is defined as if the same burst was executed with
Auto Precharge disabled and then followed with the earliest possible Precharge command that still accesses all of the data in the burst.
For Write with Auto Precharge, the precharge period begins when tWR ends, with tWR measured as if Auto Precharge was disabled. The
access period starts with registration of the command and ends where the precharge period (or tRP) begins. During the precharge period
of the Read with Auto Precharge Enabled or Write with Auto Precharge Enabled states, Active, Precharge, Read, and Write commands
to the other bank may be applied; during the access period, only Active and Precharge commands to the other bank may be applied. In
either case, all other related limitations apply (e.g. contention between Read data and Write data must be avoided).
NT5DS32M4AT NT5DS32M4AW
NT5DS16M8AT NT5DS16M8AW
128Mb DDR333/300 SDRAM
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Read (With
Auto Precharge)
L L H H Active Select and activate row 1-6
LHLHRead Select column and start new Read burst 1-7,10
LHL L Write Select column and start Write burst 1-7,9,10
L L HLPrecharge 1-6
Write (With
Auto Precharge)
L L H H Active Select and activate row 1-6
LHLHRead Select column and start Read burst 1-7,10
LHL L Write Select column and start new Write burst 1-7,10
L L HLPrecharge 1-6
Truth Table 4: Current State Bank n - Command to Bank m (Different bank)
(Part 2 of 2)
Current State CS RAS CAS WE Command Action Notes
1. This table applies when CKE n-1 was high and CKE n is high (see Truth Table 2: Clock Enable (CKE) and after tXSNR / tXSRD has been
met (if the previous state was self refresh).
2. This table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands shown are
those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are cov-
ered in the notes below.
3. Current state definitions:
Idle: The bank has been precharged, and tRP has been met.
Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are
in progress.
Read: A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
Write: A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated.
Read with Auto Precharge Enabled: See note 10.
Write with Auto Precharge Enabled: See note 10.
4. Auto Refresh and Mode Register Set commands may only be issued when all banks are idle.
5. A Burst Terminate command cannot be issued to another bank; it applies to the bank represented by the current state only.
6. All states and sequences not shown are illegal or reserved.
7. Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with
Auto Precharge disabled.
8. Requires appropriate DM masking.
9. A Write command may be applied after the completion of data output.
10. The Read with Auto Precharge enabled or Write with Auto Precharge enabled states can each be broken into two parts: the access
period and the precharge period. For Read with Auto Precharge, the precharge period is defined as if the same burst was executed with
Auto Precharge disabled and then followed with the earliest possible Precharge command that still accesses all of the data in the burst.
For Write with Auto Precharge, the precharge period begins when tWR ends, with tWR measured as if Auto Precharge was disabled. The
access period starts with registration of the command and ends where the precharge period (or tRP) begins. During the precharge period
of the Read with Auto Precharge Enabled or Write with Auto Precharge Enabled states, Active, Precharge, Read, and Write commands
to the other bank may be applied; during the access period, only Active and Precharge commands to the other bank may be applied. In
either case, all other related limitations apply (e.g. contention between Read data and Write data must be avoided).
NT5DS32M4AT NT5DS32M4AW
NT5DS16M8AT NT5DS16M8AW
128Mb DDR333/300 SDRAM
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Absolute Maximum Ratings
Symbol Parameter Rating Units
VIN, VOUT Voltage on I/O pins relative to VSS −0.5 to VDDQ+ 0.5 V
VIN Voltage on Inputs relative to VSS −0.5 to +3.6 V
VDD Voltage on VDD supply relative to VSS −0.5 to +3.6 V
VDDQ Voltage on VDDQ supply relative to VSS −0.5 to +3.6 V
TAOperating Temperature (Ambient) 0 to +70 °C
TSTG Storage Temperature (Plastic) −55 to +150 °C
PDPower Dissipation 1.0 W
IOUT Short Circuit Output Current 50 mA
Note: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rat-
ing only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this speci-
fication is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
NT5DS32M4AT NT5DS32M4AW
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Capacitance
Parameter Symbol Min. Max. Units Notes
Input Capacitance: CK, CK CI12.0 3.0 pF 1
Delta Input Capacitance: CK, CK delta CI10.25 pF 1
Input Capacitance: All other input-only pins (except DM) CI22.0 3.0 pF 1
Delta Input Capacitance: All other input-only pins (except DM) delta CI20.5 pF 1
Input/Output Capacitance: DQ, DQS, DM CIO 4.0 5.0 pF 1, 2
Delta Input/Output Capacitance: DQ, DQS, DM delta CIO 0.5 pF 1
Output Capacitance: QFC CO12.0 4.0 pF 1
1. VDDQ = VDD = 2.5V ± 0.2V (minimum range to maximum range), f = 100MHz, TA = 25°C, VODC = VDDQ/2, VOPeak -Peak =0.2V.
2. Although DM is an input-only pin, the input capacitance of this pin must model the input capacitance of the DQ and DQS pins. This is
required to match input propagation times of DQ, DQS and DM in the system.
DC Electrical Characteristics and Operating Conditions
(0°C ≤ TA ≤ 70°C; VDDQ = 2.5V ± 0.2V, VDD = + 2.5V ± 0.2V, see AC Characteristics)
Symbol Parameter Min Max Units Notes
VDD Supply Voltage 2.3 2.7 V1
VDDQ I/O Supply Voltage 2.3 2.7 V1
VSS, VSSQ Supply Voltage
I/O Supply Voltage 0 0 V
VREF I/O Reference Voltage 0.49 x VDDQ 0.51 x VDDQ V1, 2
VTT I/O Termination Voltage (System) VREF − 0.04 VREF + 0.04 V1, 3
VIH(DC) Input High (Logic1) Voltage VREF + 0.15 VDDQ + 0.3 V1
VIL(DC) Input Low (Logic0) Voltage − 0.3 VREF − 0.15 V1
VIN(DC) Input Voltage Level, CK and CK Inputs − 0.3 VDDQ + 0.3 V1
VID(DC) Input Differential Voltage, CK and CK Inputs 0.30 VDDQ + 0.6 V1, 4
VIRatio V-I Matching Pullup Current to Pulldown Current Ratio 0.71 1.4 5
IIInput Leakage Current
Any input 0V ≤ VIN ≤ VDD; (All other pins not under test = 0V) − 5 5 µA1
IOZ Output Leakage Current
(DQs are disabled; 0V ≤ Vout ≤ VDDQ − 5 5 µA1
IOH Output Current: Nominal Strength Driver
High current (VOUT= VDDQ -0.373V, min VREF, min VTT)
Low current (VOUT= 0.373V, max VREF, max VTT)
− 16.8 mA 1
IOL 16.8
1. Inputs are not recognized as valid until VREF stabilizes.
2. VREF is expected to be equal to 0.5 VDDQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak
noise on VREF may not exceed ± 2% of the DC value.
3. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and
must track variations in the DC level of VREF.
4. VID is the magnitude of the difference between the input level on CK and the input level on CK
5. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire tempera-ture and
voltage range, for device drain to source voltages for 0.25 volts to 1.0 volts. For a given output, it represents the maximum difference
between pullup and pulldown drivers due to process variation.
NT5DS32M4AT NT5DS32M4AW
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IOHW Output Current: Weak Strength Driver
High current (VOUT= VDDQ -0.763V, min VREF, min VTT)
Low current (VOUT= 0.763V, max VREF, max VTT)
− 9.0 mA 1
IOLW 9.0
DC Electrical Characteristics and Operating Conditions
(0°C ≤ TA ≤ 70°C; VDDQ = 2.5V ± 0.2V, VDD = + 2.5V ± 0.2V, see AC Characteristics)
Symbol Parameter Min Max Units Notes
1. Inputs are not recognized as valid until VREF stabilizes.
2. VREF is expected to be equal to 0.5 VDDQ of the transmitting device, and to track variations in the DC level of the same. Peak-to-peak
noise on VREF may not exceed ± 2% of the DC value.
3. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and
must track variations in the DC level of VREF.
4. VID is the magnitude of the difference between the input level on CK and the input level on CK
5. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire tempera-ture and
voltage range, for device drain to source voltages for 0.25 volts to 1.0 volts. For a given output, it represents the maximum difference
between pullup and pulldown drivers due to process variation.
NT5DS32M4AT NT5DS32M4AW
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128Mb DDR333/300 SDRAM
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AC Characteristics
(Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating Conditions, IDD
Specifications and Conditions, and Electrical Characteristics and AC Timing.)
1. All voltages referenced to VSS.
2. Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply voltage
levels, but the related specifications and device operation are guaranteed for the full voltage range specified.
3. Outputs measured with equivalent load. Refer to the AC Output Load Circuit below.
4. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5V in the test environment, but input timing is still referenced
to VREF (or to the crossing point for CK, CK), and parameter specifications are guaranteed for the specified AC input levels
under normal use conditions. The minimum slew rate for the input signals is 1V/ns in the range between VIL(AC) and
VIH(AC).
5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver effectively switches as a
result of the signal crossing the AC input level, and remains in that state as long as the signal does not ring back above
(below) the DC input low (high) level.
AC Output Load Circuit Diagrams
50Ω
Timing Reference Point
Output
(VOUT)
30pF
VTT
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DQS/DQ/DM Slew Rate
Parameterl Symbol
DDR333
(-6) DDR300
(-66) Unit Notes
Min Max Min Max
DCS/DQ/DM
input slew rate DCSLEW TBD TBD TBD TBD V/ns 1,2
1. Measured between V IH (DC), V IL (DC), and V IL (DC), V IH (DC).
2. DQS, DQ, and DM input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal tran-sition
through the DC region must be monotonic..
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AC Input Operating Conditions (0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC
Characteristics)
Symbol Parameter/Condition Min Max Unit Notes
VIH(AC) Input High (Logic 1) Voltage, DQ, DQS, and DM Signals VREF + 0.31 V1, 2
VIL(AC) Input Low (Logic 0) Voltage, DQ, DQS, and DM Signals VREF − 0.31 V1, 2
VID(AC) Input Differential Voltage, CK and CK Inputs 0.62 VDDQ + 0.6 V1, 2, 3
VIX(AC) Input Crossing Point Voltage, CK and CK Inputs 0.5*VDDQ − 0.2 0.5*VDDQ + 0.2 V1, 2, 4
1. Input slew rate = 1V/ns.
2. Inputs are not recognized as valid until VREF stabilizes.
3. VID is the magnitude of the difference between the input level on CK and the input level on CK.
4. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same.
IDD Specifications and Conditions (0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC
Characteristics)
Symbol Parameter/Condition DDR333
tCK=6ns DDR300
tCK=6.6ns Unit Notes
IDD0
Operating Current: one bank; active / precharge; tRC = tRC (min); DQ, DM, and
DQS inputs changing twice per clock cycle; address and control inputs changing
once per clock cycle 85 mA 1
IDD1
Operating Current: one bank; active / read / precharge; Burst = 2; tRC = tRC
(min); CL = 2.5; IOUT = 0mA; address and control inputs changing once per clock
cycle 110 mA 1
IDD2P Precharge Power-Down Standby Current: all banks idle; power-down mode;
CKE ≤ VIL (max) 15 mA 1
IDD2N Idle Standby Current: CS ≥ VIH (min); all banks idle; CKE ≥ VIH (min);
address and control inputs changing once per clock cycle 35 mA 1
IDD3P Active Power-Down Standby Current: one bank active; power-down mode;
CKE ≤ VIL (max) 15 mA 1
IDD3N Active Standby Current: one bank; active / precharge; CS ≥ VIH (min);
CKE ≥ VIH (min); tRC = tRAS (max); DQ, DM, and DQS inputs changing twice per
clock cycle; address and control inputs changing once per clock cycle 60 mA 1
IDD4R
Operating Current: one bank; Burst = 2; reads; continuous burst; address and
control inputs changing once per clock cycle; DQ and DQS outputs changing
twice per clock cycle; CL = 2.5; IOUT = 0mA 165 mA 1
IDD4W
Operating Current: one bank; Burst = 2; writes; continuous burst; address and
control inputs changing once per clock cycle; DQ and DQS inputs changing twice
per clock cycle; CL = 2.5 150 mA 1
IDD5 Auto-Refresh Current: tRC = tRFC (min) 170 mA 1
IDD6 Self-Refresh Current: CKE ≤ 0.2V 3mA 1, 2
IDD7
Operating current: four bank; four bank interleaving with BL = 4, address and
control inputs randomly changing; 50% of data changing at every transfer;
t RC = t RC (min); I OUT = 0mA. 150 mA 1
1. IDD specifications are tested after the device is properly initialized.
2. Enables on-chip refresh and address counters.
NT5DS32M4AT NT5DS32M4AW
NT5DS16M8AT NT5DS16M8AW
128Mb DDR333/300 SDRAM
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Electrical Characteristics & AC Timing for DDR266/DDR200 - Absolute Specifications
(0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics) (Part 1 of 2)
Symbol Parameter DDR333 DDR300 Unit Notes
Min Max Min Max
tAC DQ output access time from CK/CK − 0.7 + 0.7 − 0.75 + 0.75 ns 1-4
tDQSCK DQS output access time from CK/CK − 0.7 + 0.7 − 0.75 + 0.75 ns 1-4
tCH CK high-level width 0.45 0.55 0.45 0.55 tCK 1-4
tCL CK low-level width 0.45 0.55 0.45 0.55 tCK 1-4
tCK
Clock cycle time
CL = 2.5 6 12 6.6 12 ns 1-4
tCK CL = 2.0 7.5 12 7.5 12 ns 1-4
10 12
tDH DQ and DM input hold time 0.45 0.5 ns 1-4
tDS DQ and DM input setup time 0.45 0.5 ns 1-4
tDIPW DQ and DM input pulse width (each input) 1.75 1.75 ns 1-4
tHZ Data-out high-impedance time from CK/CK − 0.7 + 0.7 − 0.75 + 0.75 ns 1-4, 5
tLZ Data-out low-impedance time from CK/CK − 0.7 + 0.7 − 0.75 + 0.75 ns 1-4, 5
tDQSQ DQS-DQ skew (DQS & associated DQ signals) + 0.4 + 0.5 ns 1-4
tHP minimum half clk period for any given cycle;
defined by clk high (tCH) or clk low (tCL) time
tCH
or
tCL
tCH
or
tCL tCK 1-4
tQH Data output hold time from DQS tHP-tQHS tHP-tQHS tCK 1-4
tDQSS Write command to 1st DQS latching transition 0.75 1.25 0.75 1.25 tCK 1-4
tDQSL,H DQS input low (high) pulse width (write cycle) 0.35 0.35 tCK 1-4
tDSS DQS falling edge to CK setup time (write cycle) 0.2 0.2 tCK 1-4
tDSH DQS falling edge hold time from CK (write cycle) 0.2 0.2 tCK 1-4
tMRD Mode register set command cycle time 2 2 tCK 1-4
tWPRES Write preamble setup time 0 0 ns 1-4, 7
tWPST Write postamble 0.40 0.60 0.40 0.60 tCK 1-4, 6
tWPRE Write preamble 0.25 0.25 tCK 1-4
tIH Address and control input hold time
(fast slew rate) 0.75 0.9 ns 2-4, 9,11,12
tIS Address and control input setup time
(fast slew rate) 0.75 0.9 ns 2-4, 9,11,12
tIH Address and control input hold time
(slow slew rate) 0.8 1.0 ns 2-4, 12-14
tIS Address and control input setup time
(slow slew rate) 0.8 1.0 ns 2-4, 12-14
tIPW Input pulse width 2.2 2.2 ns 2-4, 12
tRPRE Read preamble 0.9 1.1 0.9 1.1 tCK 1-4
tRPST Read postamble 0.40 0.60 0.40 0.60 tCK 1-4
tRAS Active to Precharge command 42 120,000 45 120,000 ns 1-4
tRC Active to Active/Auto-refresh command period 60 65 ns 1-4
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tRFC Auto-refresh to Active/Auto-refresh
command period 72 75 ns 1-4
tRCD Active to Read or Write delay 18 20 ns 1-4
tRAP Active to Read Command with Autoprecharge 18 20 ns 1-4
tRP Precharge command period 18 20 ns 1-4
tRRD Active bank A to Active bank B command 12 15 ns 1-4
tWR Write recovery time 15 15 ns 1-4
tDAL Auto precharge write recovery
+ precharge time
(tWR/tCK)
+
(tRP/tCK)
(tWR/tCK)
+
(tRP/tCK) tCK 1-4,13
tWTR Internal write to read command delay 1 1 tCK 1-4
tXSNR Exit self-refresh to non-read command 75 75 ns 1-4
tXSRD Exit self-refresh to read command 200 200 tCK 1-4
tREFI Average Periodic Refresh Interval 15.6 15.6 µs1-4, 8
Electrical Characteristics & AC Timing for DDR266/DDR200 - Absolute Specifications
(0 °C ≤ TA ≤ 70 °C; VDDQ = 2.5V ± 0.2V; VDD = 2.5V ± 0.2V, See AC Characteristics) (Part 2 of 2)
Symbol Parameter DDR333 DDR300 Unit Notes
Min Max Min Max
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Electrical Characteristics & AC Timing for DDR266/DDR200 - Absolute Specifications
Notes
1. Input slew rate = 1V/ns.
2. The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross:
the input reference level for signals other than CK/CK, is VREF.
3. Inputs are not recognized as valid until VREF stabilizes.
4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is VTT .
5. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
6. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
system performance (bus turnaround) degrades accordingly.
7. The specific requirement is that DQS be valid (high, low, or some point on a valid transition) on or before this CK edge. A
valid
transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were prev-
iously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS
could be HIGH, LOW, or transitioning from high to low at this time, depending on t DQSS .
8. A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
9. For command/address input slew rate ≥ 1.0V/ns. Slew rate is measured between V OH (AC) and V OL (AC).
10. For command/address input slew rate ≥ 0.5V/ns and < 1.0V/ns. Slew rate is measured between VOH (AC) and V OL (AC).
11. CK/CK slew rates are ≥ 1.0V/ns.
12. These parameters guarantee device timing, but they are not necessarily tested on each device, and they may be guara-
nteed by design or tester characterization.
13. For each of the terms in parentheses, if not already an integer, round to the next highest integer. tCK is equal to the actual
system clock cycle time.
NT5DS32M4AT NT5DS32M4AW
NT5DS16M8AT NT5DS16M8AW
128Mb DDR333/300 SDRAM
Preliminary
08/01 25
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
14. An input setup and hold time derating table is used to increase t IS and t IH in the case where the input slew
rate is below 0.5 V/ns.
15. An input setup and hold time derating table is used to increase t DS and t DH in the case where the I/O slew rate is below
0.5 V/ns.
16. An I/O Delta Rise, Fall Derating table is used to increase t DS and t DH) in the case where DQ, DM, and DQS slew rates
differ.
Input Slew Rate delta ( t IS) delta ( t IH) Unit Notes
0.5 V/ns 0 0 ps 1,2
0.4 V/ns +50 0ps 1,2
0.3 V/ns +100 0ps 1,2
1. Input slew rate is based on the lesser of the slew rates determined by either V IH (AC) to V IL (AC) or V IH (DC) to V IL (DC) , similarly for rising
transitions.
2. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on eachdevice.
Input Slew Rate delta ( t DS) delta ( t DH) Unit Notes
0.5 V/ns 0 0 ps 1,2
0.4 V/ns +75 +75 ps 1,2
0.3 V/ns +150 +150 ps 1,2
1. I/O slew rate is based on the lesser of the slew rates determined by either V IH (AC) to V IL (AC) or V IH (DC) to V IL (DC) , similarly for rising
transitions.
2. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on eachdevice.
Input Slew Rate delta ( t DS) delta ( t DH) Unit Notes
0.0 V/ns 0 0 ps 1,2,3,4
0.25 V/ns +50 +50 ps 1,2,3,4
0.5 V/ns +100 +100 ps 1,2,3,4
1. Input slew rate is based on the lesser of the slew rates determined by either V IH (AC) to V IL (AC) or V IH (DC) to V IL (DC) , similarly for rising
transitions.
2. Input slew rate is based on the larger of AC to AC delta rise, fall rate and DC to DC delta rise, fall rate.
3. The delta rise, fall rate is calculated as: [1/(slew rate 1)] - [1/(slew rate 2)]
For example: slew rate 1 = 0.5 V/ns; slew rate 2 = 0.4 V/ns
Delta rise, fall = (1/0.5) - (1/0.4) [ns/V]
= -0.5 ns/V
Using the table above, this would result in an increase in t DS and t DH of 100 ps.
4. These derating parameters may be guaranteed by design or tester characterization and are not necessarily tested on each device.
NT5DS32M4AT NT5DS32M4AW
NT5DS16M8AT NT5DS16M8AW
128Mb DDR333/300 SDRAM
Preliminary
08/01 26
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Package Dimensions (400mil; 66 lead; Thin Small Outline Package)
10.16 ±. 0.13
11.76 ± 0.20
Lead #1
0.65 Basic 0.30 - 0.08
+ 0.03 0.71REF
Detail A
0.10
Seating Plane
Detail A
0.5 ± 0.1
0.05 Min
1.20 Max
0.25 Basic Gage Plane
22.22 ± 0.10
NT5DS32M4AT NT5DS32M4AW
NT5DS16M8AT NT5DS16M8AW
128Mb DDR333/300 SDRAM
Preliminary
08/01 27
© NANYA TECHNOLOGY CORP. All rights reserved.
NANYA TECHNOLOGY CORP. reserves the right to change Products and Specifications without notice.
Package Dimensions ( 60 ball; 0.8mmx1.0mm Pitch; CSP Package)
1.05 0.80
8.5
1.000.50
13.0
1.0
0.80 0.35
1.15
Dia.
0.45
Note : All dimensions are typical unless otherwise stated.
Unit : Millimeters
