SY89113U 2.5V Low Jitter, Low Skew 1:12 LVDS Fanout Buffer with 2:1 Input MUX and Internal Termination General Description The SY89113U is a 2.5V low jitter, low skew, 1:12 LVDS fanout buffer optimized for precision telecom and enterprise server distribution applications. The input includes a 2:1 MUX for clock switchover applications. Unlike other multiplexers, this input includes a unique isolation design that minimizes channel-to-channel crosstalk. The SY89113U distributes clock frequencies from DC to >1GHz guaranteed over temperature and voltage. The SY89113U incorporates a synchronous output enable (EN) so that the outputs will only be enabled/disabled when they are already in the LOW state. CLK0 differential input includes Micrel's unique, 3-pin input termination architecture that directly interfaces to any differential signal (AC- or DC-coupled) as small as 100mV (200mVPP) without any level shifting or termination resistor networks in the signal path. CLK1 differential input includes a new version of Micrel's unique, Any-Input architecture that directly interfaces with single-ended TTL/CMOS logic (including 3.3V logic), single-ended LVPECL, differential (AC- or DC-coupled) LVDS, HSTL, CML, and LVPECL logic levels as small as 200mV (400mVPP). CLK1 input requires external termination. LVDS output swing 325mV into 100 with extremely fast rise/fall time guaranteed to be less than 250ps. The SY89113U operates from a 2.5V5% supply and is guaranteed over the full industrial temperature range of -40C to +85C. The SY89113U is part of (R) Micrel's high-speed, Precision Edge product line. All support documentation can be found on Micrel's web site at: www.micrel.com. Precision Edge (R) Features * Selects between 1 of 2 inputs, and provides 12 precision, low skew LVDS output copies * Guaranteed AC performance over temperature and voltage: - DC to >1GHz throughput - <975ps propagation delay CLK0-to-Q - <250ps rise/fall time - <25ps output-to-output skew * Ultra-low jitter design: - <1psRMS random jitter - <10psPP total jitter (clock) - <1psRMS cycle-to-cycle jitter - <0.7psRMS crosstalk induced jitter * Unique, patent-pending 2:1 input MUX provides superior isolation to minimize channel-to-channel crosstalk * CLK0 input features a unique, patent-pending input termination and VT pin that accepts AC- and DCcoupled inputs (CML, LVPECL, LVDS) * CLK1 accepts virtually any logic standard: - Single-ended: TTL/CMOS (including 3.3V logic), LVPECL - Differential: LVPECL, LVDS, CML, HSTL * 325mV LVDS-compatible output swing * Power supply: 2.5V +5% * Industrial temperature range -40C to +85C * Available in 44-pin (7mm x 7mm) QFN package Applications * * * * Multi-processor server SONET/SDH clock/data distribution Fibre Channel distribution Gigabit Ethernet clock distribution Precision Edge is a registered trademark of Micrel, Inc. Micrel Inc. * 2180 Fortune Drive * San Jose, CA 95131 * USA * tel +1 (408) 944-0800 * fax + 1 (408) 474-1000 * http://www.micrel.com December 2007 M9999-120607 hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY89113U Functional Block Diagram December 2007 2 M9999-120607 hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY89113U Ordering Information(1) Part Number Package Type Operating Range Package Marking SY89113UMY QFN-44 Industrial SY89113U with Pb-Free bar-line indicator Matte-Sn Pb-Free QFN-44 Industrial SY89113U with Pb-Free bar-line indicator Matte-Sn Pb-Free (2) SY89113UMYTR Lead Finish Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25C, DC Electricals only. 2. Tape and Reel. Pin Configuration 44-Pin QFN Truth Table EN CLK_SEL Q /Q H L CLK0 /CLK0 H H CLK1 /CLK1 L X L (1) (1) H Note: 1. Transition occurs on next negative transition of the non-inverted input. December 2007 3 M9999-120607 hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY89113U Pin Description Pin Number Pin Name 1, 6, 11, 22, 34 GND, Exposed Pad 2, 5 CLK0, /CLK0 Pin Function Ground. GND pins and exposed pad must both be connected to the most negative potential of chip the ground. Differential Inputs: This input pair is a differential signal input to the device. Input accepts AC- or DC-coupled signals as small as 100mV (200mVPP). Each pin of the pair internally terminates to a VT pin through 50. Note that this input defaults to an indeterminate state if left open. Please refer to the "CLK0 Input Interface Applications" section for more details. VT0 Input Termination Center-Tap: Each side of the differential input pair CLK0, /CLK0 terminates to the VT pin. The VT pin provides a center-tap to a termination network for maximum interface flexibility. See "CLK0 Input Interface Applications" section for more details. For DC-coupled CML or LVDS inputs, the VT pin is left floating. 4 VREF-AC0 Reference Voltage: This output biases to VCC-1.2V. It is used when AC-coupling the input CLK0. For AC-coupled applications, connect VREF-AC0 to the VT0 pin and bypass with 0.01F low ESR capacitor to VCC. See "CLK0 Input Interface Applications" section for more details. Maximum sink/source current is 1.5mA. Due to the limited drive capability, the VREF-AC0 pin is only intended to drive its respective input pin. 7 SE-TERM Input Termination Pin: When CLK1 is driven by a single-ended TTL/CMOS signal, tie this pin to GND. In all other modes, let this pin float. See "CLK1 Interface Applications" section for more details. CLK1, /CLK1 Differential Inputs: This input pair is a differential signal input to the device. This input accepts Any-Logic standard as small as 200mV (400mVPP). Note that this input defaults to an indeterminate state if left open. Tie either the true or the complement input to ground while the other input is floating. This input can be used for singleended signals (including TTL/CMOS signals from a 3.3V driver). See "CLK1 Input Interface Applications" section for more details. VBB1 Reference Voltage: This output biases to VCC-1.425V. VBB1 is designed to act as a switching reference for the CLK1 and /CLK1 inputs when configured in single-ended PECL input mode. VBB1 can be used for AC-coupling of CLK1, see Figure 4d for details. Maximum sink/source current is 1.5mA. Due to the limited drive capability, the VBB1 pin is only intended to drive its respective input pin. 3 8, 10 9 12 EN This single-ended, TTL/CMOS-compatible input functions as a synchronous output enable. The synchronous enable ensures that enable/disable will only occur when the outputs are in a logic LOW state. Note that this input is internally connected to a 25k pull-up resistor and will default to logic HIGH state (enable) if left open. 13, 23, 28, 33, 43 VCC Positive power supply. Bypass with 0.1F//0.01F low ESR capacitors and place as close to the VCC pins as possible. 44 CLK_SEL This single-ended, TTL/CMOS-compatible input selects the inputs to the multiplexer. Note that this input is internally connected to a 25k pull-up resistor and will default to logic HIGH state if open. 42, 41 40, 39 38, 37 36, 35 32, 31 30, 29 27, 26 25, 24 21, 20 19, 18 17, 16 15, 14 Q0, /Q0 Q1, /Q1 Q2, /Q2 Q3, /Q3 Q4, /Q4 Q5, /Q5 Q6, /Q6 Q7, /Q7 Q8, /Q8 Q9, /Q9 Q10, /Q10 Q11, /Q11 Differential LVDS Outputs: These LVDS output pairs are the precision, low skew copies of the selected input. Please refer to the, "Truth Table" below for details. Unused output pairs should be terminated with 100 across the pair. Each output is designed to drive 325mV into 100. See the "LVDS Output Interface Applications" section for more details. December 2007 4 M9999-120607 hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY89113U Absolute Maximum Ratings(1) Operating Ratings(2) Supply Voltage (VCC) .......................... -0.5V to +4.0V Input Voltage (4, 5) ) .. -0.5V to VCC (Differential Input CLK0, CLK1 Current on Reference Voltage Outputs Source or sink current on VREF-AC0, VBB1..... 2mA Termination Current Source or sink current on VT0 ................ 100mA Input Current Source or sink current on CLK0, /CLK0 ... 50mA Lead Temperature (soldering, 20 sec.) .......... +260C Storage Temperature (Ts) ................. -65C to 150C Supply Voltage (VCC).................. +2.375V to +2.625V Ambient Temperature (TA) ................ -40C to +85C (3) Package Thermal Resistance QFN (JA) Still-Air ................................................ 24C/W QFN (JB) Junction-to-Board ................................. 8C/W DC Electrical Characteristics(6) TA = -40C to +85C, unless otherwise stated. Symbol Parameter VCC Power Supply Condition Min Typ Max Units 2.625 V 240 330 mA 2.375 ICC Power Supply Current RIN Input Resistance (CLK0-to-VT) 45 50 55 RDIFF_IN Differential Input Resistance (CLK0-to-/CLK0) 90 100 110 VIH Input High Voltage (CLK0, /CLK0) (CLK1, /CLK1) VIL VDIFF_IN 1.2 VCC V Note 4 0.2 VCC V Note 5 1.2 3.6 0.1 VCC Input Low Voltage (CLK0, /CLK0) (CLK1, /CLK1) VIN No load, max. VCC V Note 4 0.2 V Note 5 0 V Input Voltage Swing (CLK0, /CLK0) See Figure 1a. 0.1 (CLK1, /CLK1) See Figure 1a. 0.2 V Differential Input Voltage Swing |CLK0-to-/CLK0| See Figure 1b. 0.2 V |CLK1-to-/CLK1| See Figure 1b. 0.4 V VT0 CLK0-to-VT0 (CLK0, /CLK0) VREF-AC0 Output Reference Voltage VCC-1.3 VBB1 Output Reference Voltage VCC-1.525 VCC V 1.28 V VCC-1.2 VCC-1.1 V VCC-1.425 VCC-1.325 V Notes: 1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB. JA and JB values are determined for a 4-layer board in still-air, unless otherwise stated. 4. SE-TERM not connected. 5. Using single-ended TTL/CMOS input signals, SE-TERM connects to GND. See Figure 4f. 6. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. December 2007 5 M9999-120607 hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY89113U LVDS Outputs DC Electrical Characteristics(7) VCC = +2.5V 5%; TA = -40C to +85C; RL = 100 across the output pair, unless otherwise stated. Symbol Parameter Condition Min Typ VOUT Output Voltage Swing Q, /Q See Figure 1a. 250 325 mV VDIFF-OUT Differential Output Voltage Swing Q, /Q See Figure 1b. 500 650 mV VOCM Output Common Mode Voltage VOS Change in VOS between complementary output states 1.125 Max Units 1.275 V 25 mV Max Units LVTTL/CMOS DC Electrical Characteristics(7) VCC = +2.5V 5%; TA = -40C to +85C, unless otherwise stated. Symbol Parameter Condition Min VIH Input HIGH Voltage VIL Input LOW Voltage IIH Input HIGH Current -125 IIL Input LOW Current -300 Typ 2.0 V 0.8 V 30 A A Note: 7. The circuit is designed to meet the DC specifications, shown in the above table, after thermal equilibrium has been established. December 2007 6 M9999-120607 hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY89113U AC Electrical Characteristics(8) VCC = +2.5V 5%; TA = -40C to + 85C, RL = 100 across the output pair, unless otherwise stated. Symbol Parameter Condition fMAX Maximum Operating Frequency VOUT 200mV Min Typ Max Units 1 GHz Propagation Delay tPD CLK0-to-Q VIN 100mV 625 750 975 ps CLK1-to-Q VIN 200mV 700 900 1200 ps 500 700 900 ps CLK_SEL-to-Q tPD Tempco Differential Propagation Delay Temperature Coefficient o 90 fs/ C Set-up Time tS tH tSKEW tJITTER tr, tf EN-to-CLK0 Note 9 100 ps EN-to-CLK1 Note 9 0 ps Hold Time CLK0-to-EN Note 9 500 ps CLK1-to-EN Note 9 600 ps Output-to-Output Skew Note 10 25 ps Part-to-Part Skew CLK0 Note 11 200 ps Part-to-Part Skew CLK1 Note 11 250 ps Cycle-to-Cycle Jitter Note 12 1 psRMS Random Jitter (RJ) Note 13 1 psRMS Total Jitter (TJ) Note 14 10 psPP Adjacent Channel Crosstalk-induced Jitter Note 15 0.7 psRMS Output Rise/Fall Time (20% to 80%) At full output swing. 250 ps 80 150 Notes: 8. High-frequency AC-parameters are guaranteed by design and characterization. 9. Set-up and hold times apply to synchronous applications that intend to enable/disable before the next clock cycle. For asynchronous applications, set-up and hold do not apply. 10. Output-to-output skew is measured between two different outputs under identical input transitions. 11. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature and with no skew of the edges at the respective inputs 12. Cycle-to-cycle jitter definition: the variation of periods between adjacent cycles, Tn - Tn-1 where T is the time between rising edges of the output signal. 13. Random jitter is measured with a K28.7 character pattern, measured at <fMAX. 14. Total jitter definition: with an ideal clock input of frequency <fMAX, no more than one output edge in 1012 output edges will deviate by more than the specified peak-to-peak jitter value. 15. Crosstalk-induced jitter is defined as: the added jitter that results from signals applied to two adjacent channels. It is measured at the output while applying two similar, differential clock frequencies that are asynchronous with respect to each other at the inputs. December 2007 7 M9999-120607 hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY89113U Typical Operating Characteristics VCC = 2.5V, GND = 0, VIN = 400mV, RL = 100 across the output pair; T A = 25C, unless otherwise stated. Functional Characteristics VCC = 2.5V, GND = 0, VIN = 400mV, RL = 100 across the output pair; T A = 25C, unless otherwise stated. December 2007 8 M9999-120607 hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY89113U Single-Ended and Differential Swings Figure 1b. Differential Voltage Swing CLK0 Figure 1a. Single-Ended Voltage Swing CLK0 Timing Diagrams /CLK CLK tPD /Q Q Differential In-to-Differential Out ~ ~ VCC/2 VCC/2 CLK_SEL tPD ~ ~ ~ ~ tPD /Q Q CLK_SEL-to-Differential Out EN VCC/2 /CLK VCC/2 tH tS CLK /Q Q Set-Up and Hold Time EN-to-Differential IN December 2007 9 M9999-120607 hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY89113U Input and Output Stages Figure 2b. CLK0 Differential Input Structure Figure 2a. CLK1 Differential Input Structure CLK0 Input Interface Applications option: may connect VT to VCC Figure 3a. LVPECL Interface (DC-Coupled) Figure 3b. LVPECL Interface (AC-Coupled) Figure 3d. CML Interface (AC-Coupled) Figure 3e. LVDS Interface December 2007 10 Figure 3c. CML Interface (DC-Coupled) M9999-120607 hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY89113U CLK1 Input Interface Applications Figure 4a. CML, LVDS Interface (DC-Coupled) Figure 4b. CML Interface (DC-Coupled) Figure 4c. PECL Interface (DC-Coupled) (See Single-Ended TTL/CMOS Recommended Resistor Table for Recommended Resistor Value R) Figure 4d. PECL Interface (AC-Coupled) December 2007 Figure 4e. PECL Interface (Single-Ended) 11 Figure 4f. TTL/CMOS Interface (Single-Ended) M9999-120607 hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY89113U Single-Ended TTL/CMOS Recommended Resistor Value LVDS Output Interface Applications LVDS specifies a small swing of 325mV typical, on a nominal 1.2V common mode above ground. The common mode voltage has tight limits to permit large variations in ground between an LVDS driver and receiver. Also, change in common mode voltage, as a function of data input, is kept to a minimum, to keep EMI low. The SY89113U can be driven by a TTL/CMOS input signal. See Figure 4f. The resistor R, in Table 1, below is calculated according to the following equation: 1 R = 1.594x - 1 5.057x VCC -1 2 x VCC + VIH + VIL The equation above is used to determine the optimum value of R for best duty cycle. Figure 5a. LVDS Differential Measurement Recommended R () 1.8V CMOS 261 2.5V CMOS 732 3.3V CMOS 1470 Table 1. Single-Ended TTL/CMOS Recommended Resistors Figure 5b. LVDS Common Mode Measurement Related Product and Support Documentation Part Number Function Datasheet Link SY89112U 2.5/3.3V Low Jitter, Low Skew 1:12 LVPECL Fanout Buffer with 2:1 Input MUX and Internal Termination http://www.micrel.com/product-info/products/sy89112u.shtml New Products and Applications www.micrel.com/product-info/products/solutions.shtml HBW Solutions December 2007 12 M9999-120607 hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY89113U Package Information 44-Pin QFN 44-Pin QFN Package Notes: 1. Package meets Level 2 moisture sensitivity classification, and is shipped in dry pack form. 2. Exposed pads must be soldered to a ground for proper thermal management. December 2007 13 M9999-120607 hbwhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY89113U MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http:/www.micrel.com The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2005 Micrel, Incorporated. December 2007 14 M9999-120607 hbwhelp@micrel.com or (408) 955-1690