MSC8144E - Freescale Semiconductor, Inc.

Freescale Semiconductor

Data Sheet: Product Preview Documen t Nu mber: MSC8144E

Rev. 0, 6/2007

This document contains information on a product under development. Freescale reserves

the right to change or discontinue this product without notice.

MSC8144E

FC-PBGA–783

29 mm ×29 mm

• Four StarCore™ SC3400 DSP subsystems, each with an SC3400

DSP core, 16 Kbyte L1 instruction cache, 32 Kbyte L1 data cache,

memory management unit (MMU), extended prog r a mmable

interrupt controller (EPIC), two general-purpose 32-bit timers,

debu g and pro filin g sup po rt, an d low-p ower Wait and Stop

processing modes.

• Chip-level arbitration and system (CLASS) that provides full

fabric non-blocking arbitration between the processing el ements

and other initia tors and the M2 memory, DDR SRAM controller,

device configuration control and status registers, and ot her

targets.

• 128 Kbyte L2 shared instruction cache.

• 512 Kbyte M2 memory for critical data and temporary data

buffering.

• 10 Mbyte 128-b8t wide M3 memory.

• 96 Kbyte boot ROM.

• Three input clocks (shared, global, and differentia l).

• Four PLLs (system, core, global, and serial RapidIO).

• Security Engine (SEC0 optimized to process all the algorithms

associated with IPSec, IKE, WTLS/WAP, SSL/TLS, and 3GPP

using 4 crypto-channels with multi-command chains, integrated

controller for assignment of the six execution units (PKEU, DEU,

AESU, AFEU, MDEU, and KEU0) and the random number

generator (RNG), and XOR engine to accelerate parity checking

for RAID storage appl ications.

• DDR controller with up to a 200 MHz clock (400 MHz data rate),

16/32 bit data bus, support ing up t o 1 Gbyte in up to two ba nks

and support for DDR1 and DDR2.

• DMA controller with 16 bidirectional channels with up to 1024

buffer descri ptors, and progra mmable prior ity, buffer, and

multip lexin g co nf igu r atio n.

• Up to eight inde pendent TDM modules with progra mmable word

size (2, 4, 8, or 16-bi t), hardware-base A-law/μ-law conver s i on ,

up to 128 M bps data ra te for all c hann els, with glu e less inte rfac e

to E1 or T1 framers, and can in t erface wi th H-MVIP/H.110

devices, T SI, and codecs such as AC-97.

• QUICC Engine™ technology subsyst e m with dual RISC

processors, 48 Kbyte multi-master RAM, 48 Kbyte instruct ion

RAM, supporting three communication controllers with one ATM

and tw o Gigabit E thernet interfaces, to offload scheduling task s

from the DSP cores.

– The two Ethernet controllers support 10/100/1000 Mbps

operations via MII/RMII/S MII/RGMII/SGMII and the SGMII

protocol using a 4-pin SerDes interface at 1000 Mbps data rate

only.

– The AT M contro ller supports UTOPIA level II 8/16 bits a t

25/50 MHz in UTOPIA/POS mode with adaptation layer

support AAL0, AAL2, and AAL5.

• PCI designed to comp ly with the PCI specification revision 2.2 at

33 MHz or 66 M Hz with access to all PCI address spaces.

• Serial RapidIO® 1x/4x endpoint corresponds to Specification 1.2

of the RapidIO trade association, and supports read, write,

messa ges, doorbe lls, and mai ntenance a ccesses in inbound mod e,

and messages and doorbells in outbound mode.

• I/O interrupt concentrator consolidates all chip maskable interrupt

and non-maskable interrupt sources and routes them to

INT_OUT, NMI_OUT, and the cores.

• UART that permits full-duplex operation with a bit rate of up to

6.25 Mbps.

• Serial peripheral interface (SPI).

• Four timer modules, each with four configurable16-bit timers.

• Four software watchdog timer (SWT) modules.

• Up to 32 general-purpose input/output (GPIO) ports, 16 of which

can be configur ed as maska b le int err up t inputs.

•I

2C interface that allows booting from EEPROM devices.

• Eight programmable hard war e semaphores.

• Thirt y two virtua l maskable int errupts and one virt ual NMI that

can be generated b y a simple write access.

• Opt ional bootin g via serial R a pidIO por t, PCI, I2C, SPI, or

Ethernet i nterfaces.

Note: This document supports mask set M31H.

Quad Core Digital Signal

Processor

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0

Freesca le Sem ico nd uctor2

Table of Contents

1 Pin Assignments and Reset States . . . . . . . . . . . . . . . . . . . . .4

1.1 FC-PBGA Ba ll La yout Diagrams. . . . . . . . . . . . . . . . . . .4

1.2 Signal List By Ball Location . . . . . . . . . . . . . . . . . . . . . . . 6

2 Ele ctrica l C h a r a cteri stics . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

2.1 Max imum Ra ting s . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25

2.2 Recommended Operating Conditions. . . . . . . . . . . . . .27

2.3 Default Ou tpu t Driver Characteristics . . . . . . . . . . . . . .27

2.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .28

2.5 Powe r Characteristi cs. . . . . . . . . . . . . . . . . . . . . . . . . .28

2.6 DC Electrical Chara c te ristics . . . . . . . . . . . . . . . . . . . .29

2.7 AC Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

3 Hardware Design Considerations. . . . . . . . . . . . . . . . . . . . . .65

3.1 Start-up Sequencing Recommendat ions . . . . . . . . . . . 65

3.2 Power Supply Design Considerations. . . . . . . . . . . . . .66

3.3 Connectivity Guidelines . . . . . . . . . . . . . . . . . . . . . . . .66

3.4 External DDR SDRAM Selection . . . . . . . . . . . . . . . . .75

4 Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

5 Package Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

6 Product D o c u mentatio n . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

7 Revis io n Histor y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77

List of Figures

Figure 1. MSC8144E Block Diagram . . . . . . . . . . . . . . . . . . . . . . . 3

Figure 2. StarCore SC3400 DSP Core Subsyst em Block Diagram 3

Figure 3. MSC8144E FC-PB GA Pac kage, Top View. . . . . . . . . . . 4

Figure 4. MSC8144E FC-PB G A Pac kage, Bo ttom View . . . . . . . . 5

Figure 5. SerDes Reference Clocks Input Stage. . . . . . . . . . . . . 31

Figure 6. Overshoot/Undersho ot Voltage for VIH and VIL. . . . . . . 3 5

Figure 7. St art-Up Sequence with VDD Raised Before VDDIO with

CLKIN Started with VDDIO. . . . . . . . . . . . . . . . . . . . . . . 36

Figure 8. Timing for a Reset Configuration Write. . . . . . . . . . . . . 39

Figure 9. Timing for tDDKHMH . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 10.DDR SDRAM Output Timing. . . . . . . . . . . . . . . . . . . . . 41

Figure 11.DDR AC Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Figure 12. Differential VPP of Transmitt e r o r R e c e i ve r . . . . . . . . . . 4 3

Figure 13.Transmitter Outp u t Complia n ce Mask. . . . . . . . . . . . . . 46

Figure 14.Single Frequency Sinusoidal Jitter Limits . . . . . . . . . . . 48

Figure 15.Receiver Input Compliance Mask . . . . . . . . . . . . . . . . . 49

Figure 16.PCI AC Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

Figure 17.PCI Input AC Timing Measurement Conditions. . . . . . . 51

Figure 18.PCI Output AC T iming Measurement Condition . . . . . . 51

Figure 19.TDM Inputs Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Figure 21.TDM Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 22.UART Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 23.UART Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

Figure 24.Timer T i ming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

Figure 25.MII Management Interface Timing. . . . . . . . . . . . . . . . . 55

Figure 26.MII Transmit AC Timing. . . . . . . . . . . . . . . . . . . . . . . . . 55

Figure 27.AC Test Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 28.MII Receive AC Timing . . . . . . . . . . . . . . . . . . . . . . . . . 56

Figure 29.RMII Transmit and Receive AC Timing . . . . . . . . . . . . . 57

Figure 30.AC Test Load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Figure 31.SMII Mode Signal Timing. . . . . . . . . . . . . . . . . . . . . . . . 58

Figure 32.RGMII AC Timing and Multiplexing s. . . . . . . . . . . . . . . 59

Figure 33.UTOPIA AC Test Load. . . . . . . . . . . . . . . . . . . . . . . . . . 60

Figure 34.UTOPIA AC Timing (Ex te rnal Clock). . . . . . . . . . . . . . . 60

Figure 35.SPI AC Tes t Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Figure 36.SPI AC Timing in Slave Mode (External Clock). . . . . . . 61

Figure 37.SPI AC T iming in Master Mode (Internal Clock) . . . . . . 62

Figure 38.GPIO Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Figure 39.EE Pin Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 40.Tes t Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . 63

Figure 41.Boundary Scan (JTAG) Timing . . . . . . . . . . . . . . . . . . . 64

Figure 42.Test Access Port Timing . . . . . . . . . . . . . . . . . . . . . . . . 64

Figure 43.TRST Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

Figure 44.VDDM3, VDDM3IO and V25M3 Power-on Sequence . . . . . 65

Figure 46.MSC8144E Mechanical Informat ion, 783-ball FC-PBGA

Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0

Freescale Semicond uc tor 3

Figure 1. MSC8144E Block Diagram

Figur e 2. Star Core SC3400 DSP Core Subsystem Block Diagram

JTAG

RMU SRIO

Note: The arrow direction indicat es master or slave.

128-bit at

DDR Interface 16/32-bit at 400 MHz data rate

8 TDMs

DMA

I/O-Interrupt

Concentrator

UART

Clocks

Timers

Reset

Semaphores

Other

DDR

10 Mby tes

Memory

512 Kbytes

Memory

CLASS

128 Kbyt e

ICache

PCI

PCI 32-bit

Ser. Rapi dIO

Subsystem

Modules

QUICC Engine™

Ether-

Dual RISC

ATM

16-bit/8-bit

10/100/ 1000 Mbps

Subsystem

400 MHz

Processors

Eight TDMs 33/66 MHz

1x/4x

256-Channels each

Four DSP

Subsystems

Ether- Boot ROM

I2C

Virtual

Interrupts

Controller

UTOPIA

SPI

net

Security

Engine Core

Instruction

Cache Address

Translation

Task

Protection

Data

Cache

(WTB) (WBB)

EPIC

Interrupts

P-bus

Xa-bus

Xb-bus

DQBus

Debug Support

OCE30

Bus Interface

MMU

Timer

Tw o Internal Bus es

(128 bits wide each)

IQBus

DPU

SC3400

Core

TWB

Write-

Through

Buffer

Write-

Back

Buffer

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0

Pin Assignments and Reset States

Freesca le Sem ico nd uctor4

1 Pin Assignments and Reset States

This section includes diagrams of the MSC8144E package ball grid array layouts and tables showing how the pinouts are

allocated for the package.

1.1 FC-PBGA Ball Layout Diagrams

Top and bottom views of the FC-PBGA package are shown in Figure 3 and Figure 4 with their ball location index number s.

Figure 3. MSC8144E FC-PBGA Package, Top View

MSC8144E

Top View

1342 5678 10 141312119

15 16 17 18 19 20 21 22 23 24 25 26 27 28

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0

Freescale Semicond uc tor 5

Figure 4. MSC8144E FC-PBGA Package, Bottom View

MSC8144E

1342567810 141312119

Bottom View

15 16 17 18 19 20 21 22 23 24 25 26 27

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0

Freesca le Sem ico nd uctor6

1.2 Signal List By Ball Location

Table 1 presents the signal list sorted by ball number. The functionality of multi-functional (multiplexed) pins is separated for

each mode. When designing a board, make sure that the reference supply for each signal is appropriately considered. The

specified reference s upply m ust be tied to the voltage level s pecified in this do cumen t if any of the r ela ted s ignal f unction s are

used (active).

Table 1. Signal List by Ball Number

Ball

Number Signal Name

Power-

Reset

Value

I/O Mult iplexing Mod e 2

Ref.

Supply

0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111)

A2 GND GND

A3 GE2_RX_ER /PCI_AD31 Ethernet 2 PCI Ethernet 2 VDDGE2

A4 VDDGE2 VDDGE2

A5 GE2_RX_DV/PCI_AD30 Ethernet 2 PCI Ethernet 2 VDDGE2

A6 GE2_TD0/PCI_CBE0 Ethernet 2 PCI Ethernet 2 VDDGE2

A7 SRIO_IMP_CAL_RX VDDSXC

A8 Reserved1—

A9 Reserved1—

A10 Reserved1—

A11 Reserved1—

A12 SRIO_RXD0 VDDSXC

A13 VDDSXC VDDSXC

A14 SRIO_RXD1 VDDSXC

A15 VDDSXC VDDSXC

A16 SRIO_REF_CLK VDDSXC

A17 VDDRIOPLL GNDRIOPLL

A18 GNDSXC GNDSXC

A19 SRIO_RXD2/

GE1_SGMII_RX SGMII support on SERDES is enabled by Reset Configuration Word VDDSXC

A20 VDDSXC VDDSXC

A21 SRIO_RXD3/

GE2_SGMII_RX SGMII support on SERDES is enabled by Reset Configuration Word VDDSXC

A22 VDDSXC VDDSXC

A23 SRIO_IMP_CAL_TX VDDSXP

A24 MDQ28 VDDDDR

A25 MDQ29 VDDDDR

A26 MDQ30 VDDDDR

A27 MDQ31 VDDDDR

A28 MDQS3 VDDDDR

B1 Reserved1—

B2 GE2_TD1/PCI_CBE1 Ethernet 2 PCI Ethernet 2 VDDGE2

B3 GE2_TX_EN/PCI_CBE2 Ethernet 2 PCI Ethernet 2 VDDGE2

B4 GE_MDIO Ethernet VDDGE2

B5 GND GND

B6 GE_MDC Ethernet VDDGE2

B7 GNDSXC GNDSXC

B8 Reserved1—

B9 Reserved1—

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0

Freescale Semicond uc tor 7

B10 Reserved1—

B11 Reserved1—

B12 SRIO_RXD0 VDDSXC

B13 GNDSXC GNDSXC

B14 SRIO_RXD1 VDDSXC

B15 GNDSXC GNDSXC

B16 SRIO_REF_CLK VDDSXC

B17 Reserved1—

B18 VDDSXC VDDSXC

B19 SRIO_RXD2/

GE1_SGMII_RX SGMII support on SERDES is enabled by Reset Configuration Word VDDSXC

B20 GNDSXC GNDSXC

B21 SRIO_RXD3/

GE2_SGMII_RX SGMII support on SERDES is enabled by Reset Configuration Word VDDSXC

B22 GNDSXC GNDSXC

B23 GNDSXP GNDSXP

B24 MDQ27 VDDDDR

B25 VDDDDR VDDDDR

B26 GND GND

B27 VDDDDR VDDDDR

B28 MDQS3 VDDDDR

C1 Reserved1—

C2 GE2_RX_CLK/PCI_AD29 Ethernet 2 PCI Ethernet 2 VDDGE2

C3 VDDGE2 VDDGE2

C4 TDM7RSYN/GE2_TD2/

PCI_AD2/UTP_TER TDM PCI Ethernet 2 UTOPIA VDDGE2

C5 TDM7RCLK/GE2_RD2/

PCI_AD0/UTP_RVL TDM PCI Ethernet 2 UTOPIA VDDGE2

C6 VDDGE2 VDDGE2

C7 GE2_RD0/PCI_AD27 Ethernet 2 PCI Ethernet 2 VDDGE2

C8 Reserved1—

C9 Reserved1—

C10 Reserved1—

C11 Reserved1—

C12 VDDSXP VDDSXP

C13 SRIO_TXD0 VDDSXP

C14 VDDSXP VDDSXP

C15 SRIO_TXD1 VDDSXP

C16 GNDSXC GNDSXC

C17 GNDRIOPLL GNDRIOPLL

C18 Reserved1—

C19 VDDSXP VDDSXP

C20 SRIO_TXD2/GE1_SGMII_T

XSGMII support on SERDES is enabled by Reset Configuration Word VDDSXP

Table 1. Signal List by Ball Number (continued)

Ball

Number Signal Name

Power-

Reset

Value

I/O Mult iplexing Mod e 2

Ref.

Supply

0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111)

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0

Freesca le Sem ico nd uctor8

C21 VDDSXP VDDSXP

C22 SRIO_TXD3/GE2_SGMII_T

XSGMII support on SERDES is enabled by Reset Configuration Word VDDSXP

C23 VDDSXP VDDSXP

C24 MDQ26 VDDDDR

C25 MDQ25 VDDDDR

C26 MDM3 VDDDDR

C27 GND GND

C28 MDQ24 VDDDDR

D1 Reserved1—

D2 GE2_RD1/PCI_AD28 Ethernet 2 PCI Ethernet 2 VDDGE2

D3 GND GND

D4 TDM7TDAT/GE2_TD3/

PCI_AD3/UTP_TMD TDM PCI Ethernet 2 UTOPIA VDDGE2

D5 TDM7RDAT/GE2_RD3/

PCI_AD1/UTP_STA TDM PCI Ethernet 2 UTOPIA VDDGE2

D6 GE1_RD0/UTP_RD2/

PCI_CBE2 UTOPIA Ethernet 1 PCI UTOPIA Ethernet 1 UTO PI A VDDGE1

D7 TDM7TCLK/GE2_TCK/

PCI_IDS/UTP_RER TDM PCI Ethernet 2 UTOPIA VDDGE2

D8 Reserved1—

D9 Reserved1—

D10 Reserved1—

D11 Reserved1—

D12 GNDSXP GNDSXP

D13 SRIO_TXD0 VDDSXP

D14 GNDSXP GNDSXP

D15 SRIO_TXD1 VDDSXP

D16 VDDSXC VDDSXC

D17 Reserved1—

D18 Reserved1—

D19 GNDSXP GNDSXP

D20 SRIO_TXD2/GE1_SGMII_T

XSGMII support on SERDES is enabled by Reset Configuration Word VDDSXP

D21 GNDSXP GNDSXP

D22 SRIO_TXD3/GE2_SGMII_T

XSGMII support on SERDES is enabled by Reset Configuration Word VDDSXP

D23 GNDSXP GNDSXP

D24 MDQ23 VDDDDR

D25 VDDDDR VDDDDR

D26 MDQ22 VDDDDR

D27 MDQ21 VDDDDR

D28 MDQS2 VDDDDR

E1 Reserved1—

Table 1. Signal List by Ball Number (continued)

Ball

Number Signal Name

Power-

Reset

Value

I/O Mult iplexing Mod e 2

Ref.

Supply

0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111)

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0

Freescale Semicond uc tor 9

E2 GE1_RX_CLK/UTP_RD6/

PCI_PAR UTOPIA Ethernet 1 PCI UTOPIA Ethernet 1 UTO PIA VDDGE1

E3 GE1_RD2/UTP_RD4/

PCI_FRAME UTOPIA Ethernet 1 PCI UTOPIA Ethernet 1 UTOPIA VDDGE1

E4 GE1_RD1/UTP_RD3/

PCI_CBE3 UTOPIA Ethernet 1 PCI UTOPIA Ethernet 1 UTO PI A VDDGE1

E5 GE1_RD3/UTP_RD5/

PCI_IRDY UTOPIA Ethernet 1 PCI UTOPIA Ethernet 1 UTOPI A VDDGE1

E6 VDDGE1 VDDGE1

E7 GE1_TX_EN/UTP_TD6/

PCI_CBE0 UTOPIA Ethernet 1 PCI UTOPIA Ethernet 1 UTO PI A VDDGE1

E8 Reserved1—

E9 Reserved1—

E10 GND GND

E11 VDD VDD

E12 GND GND

E13 VDD VDD

E14 GND GND

E15 VDD VDD

E16 GND GND

E17 VDD VDD

E18 GND GND

E19 VDD VDD

E20 GND GND

E21 VDD VDD

E22 GND GND

E23 VDDDDR VDDDDR

E24 MDQ20 VDDDDR

E25 GND GND

E26 VDDDDR VDDDDR

E27 GND GND

E28 MDQS2 VDDDDR

F1 Reserved1—

F2 GE1_TX_CLK/UTP_RD0/

PCI_AD31 UTOPIA Ethernet 1 PCI UTOPIA Ethernet 1 UTO PIA VDDGE1

F3 VDDGE1 VDDGE1

F4 GE1_TD3/UTP_TD5/

PCI_AD30 UTOPIA Ethernet 1 PCI UTOPIA Ethernet 1 UTO PIA VDDGE1

F5 GE1_TD1/UTP_TD3/

PCI_AD28 UTOPIA Ethernet 1 PCI UTOPIA Ethernet 1 UTO PIA VDDGE1

F6 GND GND

F7 GE1_TD0/UTP_TD2/

PCI_AD27 UTOPIA Ethernet 1 PCI UTOPIA Ethernet 1 UTO PIA VDDGE1

F8 VDDGE1 VDDGE1

F9 GND GND

Table 1. Signal List by Ball Number (continued)

Ball

Number Signal Name

Power-

Reset

Value

I/O Mult iplexing Mod e 2

Ref.

Supply

0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111)

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0

Freesca le Sem ico nd uctor10

F10 VDD VDD

F11 GND GND

F12 VDD VDD

F13 GND GND

F14 VDD VDD

F15 GND GND

F16 VDD VDD

F17 GND GND

F18 VDD VDD

F19 GND GND

F20 VDD VDD

F21 Reserved1—

F22 VDDDDR VDDDDR

F23 GND GND

F24 MDQ19 VDDDDR

F25 MDQ18 VDDDDR

F26 MDM2 VDDDDR

F27 MDQ17 VDDDDR

F28 MDQ16 VDDDDR

G1 Reserved1—

G2 SRESET4VDDIO

G3 GND GND

G4 PORESET4VDDIO

G5 GE1_COL/UTP_RD1 UTOPIA Ethernet 1 UTOPIA Ethernet 1 UTO PIA VDDIO

G6 GE1_TD2/UTP_TD4/

PCI_AD29 UTOPIA Ethernet 1 PCI UTOPIA Ethernet 1 UTO PIA VDDGE1

G7 GE1_RX_DV/UTP_RD7 UTOPIA Ethernet 1 UTOPIA Ethernet 1 UTOPI A VDDGE1

G8 GE1_TX_ER/UTP_TD7/

PCI_CBE1 UTOPIA Ethernet 1 PCI UTOPIA Ethernet 1 UTO PI A VDDGE1

G9 VDD VDD

G10 GND GND

G11 VDD VDD

G12 GND GND

G13 VDD VDD

G14 GND GND

G15 VDD VDD

G16 GND GND

G17 VDD VDD

G18 GND GND

G19 VDD VDD

G20 GND GND

G21 Reserved1— —

G22 GND GND

Table 1. Signal List by Ball Number (continued)

Ball

Number Signal Name

Power-

Reset

Value

I/O Mult iplexing Mod e 2

Ref.

Supply

0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111)

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0

Freescale Semicond uc tor 11

G23 MBA1 VDDDDR

G24 MA3 VDDDDR

G25 MA8 VDDDDR

G26 VDDDDR VDDDDR

G27 GND GND

G28 MCK0 VDDDDR

H1 Reserved1—

H2 CLKIN VDDIO

H3 HRESET VDDIO

H4 PCI_CLK_IN VDDIO

H5 NMI VDDIO

H6 URXD/GPIO14/IRQ8/

RC_LDF3, 6 RC_LDF UART/GPIO/IRQ VDDIO

H7 GE1_RX_ER/PCI_AD6/

GPIO25/IRQ153, 6 GPIO/

IRQ Ethernet

1PCI GPIO/

IRQ Ethernet 1 VDDIO

H8 GE1_CRS/PCI_AD5 PCI Ethernet

1PCI Ethernet 1 VDDIO

H9 GND GND

H10 VDD VDD

H11 GND GND

H12 VDD VDD

H13 GND GND

H14 VDD VDD

H15 VDD VDD

H16 VDD VDD

H17 GND GND

H18 VDD VDD

H19 GND GND

H20 VDD VDD

H21 VDD VDD

H22 VDDDDR VDDDDR

H23 MBA0 VDDDDR

H24 MA15 VDDDDR

H25 VDDDDR VDDDDR

H26 MA9 VDDDDR

H27 MA7 VDDDDR

H28 MCK0 VDDDDR

J1 Reserved1—

J2 GND GND

J3 VDDIO VDDIO

J4 STOP_BS VDDIO

J5 NMI_OUT4VDDIO

J6 INT_OUT4VDDIO

J7 SDA/GPIO273, 4, 6 I2C/GPIO VDDIO

Table 1. Signal List by Ball Number (continued)

Ball

Number Signal Name

Power-

Reset

Value

I/O Mult iplexing Mod e 2

Ref.

Supply

0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111)

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0

Freesca le Sem ico nd uctor12

J8 VDDIO VDDIO

J9 VDD VDD

J10 GND GND

J11 VDD VDD

J12 GND GND

J13 VDD VDD

J14 GND GND

J15 GND GND

J16 GND GND

J17 VDD VDD

J18 GND GND

J19 VDD VDD

J20 GND GND

J21 GND GND

J22 GND GND

J23 GND GND

J24 VDDDDR VDDDDR

J25 GND GND

J26 VDDDDR VDDDDR

J27 GND GND

J28 VDDDDR VDDDDR

K1 Reserved1—

K2 Reserved1—

K3 Reserved1—

K4 Reserved1—

K5 VDDPLL2A VDDPLL2A

K6 GND GND

K7 VDDPLL0A VDDPLL0A

K8 VDDPLL1A VDDPLL1A

K9 VDD VDD

K10 GND GND

K11 VDD VDD

K12 GND GND

K13 VDD VDD

K14 VDD VDD

K15 VDD VDD

K16 VDD VDD

K17 VDD VDD

K18 GND GND

K19 VDD VDD

K20 GND GND

K21 VDD VDD

K22 VDDDDR VDDDDR

Table 1. Signal List by Ball Number (continued)

Ball

Number Signal Name

Power-

Reset

Value

I/O Mult iplexing Mod e 2

Ref.

Supply

0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111)

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0

Freescale Semicond uc tor 13

K23 MBA2 VDDDDR

K24 MA10 VDDDDR

K25 MA12 VDDDDR

K26 MA14 VDDDDR

K27 MA4 VDDDDR

K28 MVREF VDDDDR

L1 Reserved1—

L2 CLKOUT VDDIO

L3 TMR1/UTP_IR/PCI_CBE3/

GPIO173, 6 UTOPIA TMR/

GPIO UTOPIA PCI UTOPIA VDDIO

L4 TMR4/PCI_PAR/GPIO203,

6/ UTP_REOP TIMER/GPIO PCI TIMER/GPIO VDDIO

L5 GND GND

L6 TMR2/PCI_FRAME/

GPIO183, 6 TIMER/GPIO PCI TIMER/GPIO UTOPIA VDDIO

L7 SCL/GPIO263, 4, 6 I2C/GPIO VDDIO

L8 UTXD/GPIO15/IRQ93, 6 UART/GPIO/IRQ VDDIO

L9 GND GND

L10 VDD VDD

L11 GND GND

L12 VDD VDD

L13 GND GND

L14 VDD VDD

L15 Reserved1GND

L16 VDD VDD

L17 GND GND

L18 VDD VDD

L19 GND GND

L20 VDD VDD

L21 GND GND

L22 GND GND

L23 MCKE1 VDDDDR

L24 MA1 VDDDDR

L25 VDDDDR VDDDDR

L26 GND GND

L27 VDDDDR VDDDDR

L28 MCK1 VDDDDR

M1 Reserved1—

M2 TRST VDDIO

M3 EE0 VDDIO

M4 EE1 VDDIO

M5 UTP_RCLK/PCI_AD13 UTOPIA PCI UTOPIA VDDIO

M6 UTP_RADDR0/PCI_AD7 UTOPIA PCI UTOPIA VDDIO

M7 UTP_TD8/PCI_AD30 UTOPIA PCI UTOPIA VDDIO

Table 1. Signal List by Ball Number (continued)

Ball

Number Signal Name

Power-

Reset

Value

I/O Mult iplexing Mod e 2

Ref.

Supply

0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111)

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0

Freesca le Sem ico nd uctor14

M8 VDDIO VDDIO

M9 VDD VDD

M10 GND GND

M11 VDD VDD

M12 GND GND

M13 VDD VDD

M14 GND GND

M15 VDD VDD

M16 GND GND

M17 VDD VDD

M18 GND GND

M19 VDD VDD

M20 GND GND

M21 VDD VDD

M22 VDDDDR VDDDDR

M23 MCS1 VDDDDR

M24 MA13 VDDDDR

M25 MA2 VDDDDR

M26 MA0 VDDDDR

M27 GND GND

M28 MCK1 VDDDDR

N1 Reserved1—

N2 VDDIO VDDIO

N3 TMS VDDIO

N4 UTP_RD10/PCI_AD145UTOPIA PCI UTOPIA VDDIO

N5 VDDIO Power VDDIO

N6 UTP_RADDR1/PCI_AD8 UTOPIA PCI UTOPIA VDDIO

N7 UTP_TD9/PCI_AD31 UTOPIA PCI UTOPIA VDDIO

N8 TMR3/PCI_IRDY/GPIO193,

6/ UTP_TEOP TIMER/GPIO PCI TIMER/GPIO UTOPIA VDDIO

N9 GND GND

N10 VDDM3 VDDM3

N11 VDD VDD

N12 VDDM3 VDDM3

N13 VDD VDD

N14 VDDM3 VDDM3

N15 VDD VDD

N16 VDDM3 VDDM3

N17 VDD VDD

N18 VDDM3 VDDM3

N19 VDD VDD

N20 VDDM3 VDDM3

N21 GND GND

Table 1. Signal List by Ball Number (continued)

Ball

Number Signal Name

Power-

Reset

Value

I/O Mult iplexing Mod e 2

Ref.

Supply

0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111)

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0

Freescale Semicond uc tor 15

N22 GND GND

N23 MODT1 VDDDDR

N24 MCKE0 VDDDDR

N25 VDDDDR VDDDDR

N26 MA5 VDDDDR

N27 MA6 VDDDDR

N28 MA11 VDDDDR

P1 Reserved1—

P2 TDI5VDDIO

P3 UTP_RD11/PCI_AD15 UTOPIA PCI UTOPIA VDDIO

P4 GND GND

P5 UTP_RADDR3/PCI_AD10 UTOPIA PCI UTOPIA VDDIO

P6 UTP_RADDR2/PCI_AD9 UTOPIA PCI UTOPIA VDDIO

P7 PCI_GNT/GPIO29/IRQ73. 6 GPIO/IRQ PCI GPIO/IRQ VDDIO

P8 PCI_STOP/GPIO30/IRQ23,

6GPIO/IRQ PCI GPIO/IRQ VDDIO

P9 GND GND

P10 GND GND

P11 VDDM3 VDDM3

P12 GND GND

P13 VDDM3 VDDM3

P14 GND GND

P15 VDDM3 VDDM3

P16 GND GND

P17 VDDM3 VDDM3

P18 GND GND

P19 VDDM3 VDDM3

P20 GND GND

P21 GND GND

P22 VDDDDR VDDDDR

P23 MCS0 VDDDDR

P24 MRAS VDDDDR

P25 GND GND

P26 VDDDDR VDDDDR

P27 GND GND

P28 MCK2 VDDDDR

R1 Reserved1—

R2 TCK VDDIO

R3 TDO VDDIO

R4 UTP_RD12/PCI_AD16 UTOPIA PCI UTOPIA VDDIO

R5 UTP_RCLAV_PDRPA/

PCI_AD12 UTOPIA PCI UTOPIA VDDIO

R6 UTP_RADDR4/PCI_AD11 UTOPIA PCI UTOPIA VDDIO

Table 1. Signal List by Ball Number (continued)

Ball

Number Signal Name

Power-

Reset

Value

I/O Mult iplexing Mod e 2

Ref.

Supply

0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111)

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0

Freesca le Sem ico nd uctor16

R7 VDDIO VDDIO

R8 PCI_REQ PCI VDDIO

R9 GND GND

R10 GND GND

R11 GND GND

R12 GND GND

R13 GND GND

R14 GND GND

R15 GND GND

R16 GND GND

R17 GND GND

R18 GND GND

R19 GND GND

R20 GND GND

R21 GND GND

R22 GND GND

R23 MODT0 VDDDDR

R24 MDIC1 VDDDDR

R25 MDIC0 VDDDDR

R26 MCAS VDDDDR

R27 MWE VDDDDR

R28 MCK2 VDDDDR

T1 Reserved1—

T2 UTP_RPRTY/PCI_AD21 UTOPIA PCI UTOPIA VDDIO

T3 UTP_RD13/PCI_AD17 UTOPIA PCI UTOPIA VDDIO

T4 VDDIO VDDIO

T5 UTP_RD14/PCI_AD18 UTOPIA PCI UTOPIA VDDIO

T6 UTP_RD15/PCI_AD19 UTOPIA PCI UTOPIA VDDIO

T7 PCI_TRDY PCI VDDIO

T8 PCI_DEVSEL/GPIO31/

IRQ33, 6 GPIO/IRQ PCI GPIO/IRQ VDDIO

T9 GND GND

T10 GND GND

T11 GND GND

T12 GND GND

T13 GND GND

T14 GND GND

T15 GND GND

T16 GND GND

T17 GND GND

T18 GND GND

T19 GND GND

T20 GND GND

Table 1. Signal List by Ball Number (continued)

Ball

Number Signal Name

Power-

Reset

Value

I/O Mult iplexing Mod e 2

Ref.

Supply

0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111)

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0

Freescale Semicond uc tor 17

T21 GND GND

T22 VDDDDR VDDDDR

T23 GND GND

T24 VDDDDR VDDDDR

T25 GND GND

T26 VDDDDR VDDDDR

T27 GND GND

T28 VDDDDR VDDDDR

U1 Reserved1—

U2 UTP_TCLK/PCI_AD29 UTOPIA PCI UTOPIA VDDIO

U3 UTP_TADDR4/PCI_AD27 UTOPIA PCI UTOPIA VDDIO

U4 UTP_TADDR2 UTOPIA VDDIO

U5 GND GND

U6 UTP_REN/PCI_AD20 UTOPIA PCI UTOPIA VDDIO

U7 PCI_AD26 PCI VDDIO

U8 PCI_AD25 PCI VDDIO

U9 Reserved1VDDIO

U10 VDDM3 VDDM3

U11 GND GND

U12 VDDM3 VDDM3

U13 GND GND

U14 VDDM3 VDDM3

U15 GND GND

U16 VDDM3 VDDM3

U17 GND GND

U18 VDDM3 VDDM3

U19 GND GND

U20 VDDM3 VDDM3

U21 GND GND

U22 GND GND

U23 MDQ7 VDDDDR

U24 MDQ3 VDDDDR

U25 MDQ4 VDDDDR

U26 MDQ5 VDDDDR

U27 MDQ1 VDDDDR

U28 MDQ0 VDDDDR

V1 Reserved1—

V2 UTP_TD10/PCI_CBE0 UTOPIA PCI UTOPIA VDDIO

V3 UTP_TADDR3 UTOPIA VDDIO

V4 UTP_TD1/PCI_PERR UTOPIA PCI UTOPIA VDDIO

V5 UTP_TADDR0/PCI_AD23 UTOPIA PCI UTOPIA VDDIO

V6 UTP_TADDR1/PCI_AD24 UTOPIA PCI UTOPIA VDDIO

V7 UTP_TCLAV/PCI_AD28 UTOPIA PCI UTOPIA VDDIO

Table 1. Signal List by Ball Number (continued)

Ball

Number Signal Name

Power-

Reset

Value

I/O Mult iplexing Mod e 2

Ref.

Supply

0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111)

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0

Freesca le Sem ico nd uctor18

V8 VDDIO VDDIO

V9 Reserved1VDDIO

V10 GND GND

V11 VDDM3 VDDM3

V12 GND GND

V13 VDDM3 VDDM3

V14 GND GND

V15 VDDM3 VDDM3

V16 GND GND

V17 VDDM3 VDDM3

V18 GND GND

V19 VDDM3 VDDM3

V20 GND GND

V21 GND GND

V22 VDDDDR VDDDDR

V23 MDQ2 VDDDDR

V24 VDDDDR VDDDDR

V25 MDQ6 VDDDDR

V26 GND GND

V27 VDDDDR VDDDDR

V28 MDQS0 VDDDDR

W1 Reserved1—

W2 UTP_TD12/PCI_CBE2 UTOPIA PCI UTOPIA VDDIO

W3 UTP_TD11/PCI_CBE1 UTOPIA PCI UTOPIA VDDIO

W4 VDDIO VDDIO

W5 GND GND

W6 UTP_TD15/PCI_IRDY UTOPIA PCI UTOPIA VDDIO

W7 UTP_TD0/PCI_SERR UTOPIA PCI UTOPIA VDDIO

W8 UTP_RSOC/PCI_AD22 UTOPIA PCI UTOPIA VDDIO

W9 Reserved1VDDIO

W10 VDDM3 VDDM3

W11 GND GND

W12 V25M3 V25M3

W13 GND GND

W14 VDDM3 VDDM3

W15 V25M3 V25M3

W16 VDDM3 VDDM3

W17 GND GND

W18 V25M3 V25M3

W19 GND GND

W20 VDDM3 VDDM3

W21 GND GND

W22 GND GND

Table 1. Signal List by Ball Number (continued)

Ball

Number Signal Name

Power-

Reset

Value

I/O Mult iplexing Mod e 2

Ref.

Supply

0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111)

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0

Freescale Semicond uc tor 19

W23 MDQ10 VDDDDR

W24 GND GND

W25 MDQ11 VDDDDR

W26 MDM0 VDDDDR

W27 GND GND

W28 MDQS0 VDDDDR

Y1 Reserved1-

Y2 UTP_TD14/PCI_FRAME UTOPIA PCI UTOPIA VDDIO

Y3 TDM5TSYN/ PCI_AD18/

GPIO123, 6 TDM/GPIO PCI TDM/GPIO VDDIO

Y4 TDM5TCLK/PCI_AD16 TDM PCI TDM VDDIO

Y5 TDM4RCLK/PCI_AD7 TDM PCI TDM VDDIO

Y6 TDM4TSYN/PCI_AD12 TDM PCI TDM VDDIO

Y7 UTP_TPRTY/RC14 RC14 UTOPIA VDDIO

Y8 UTP_TEN/PCI_PAR UTOPIA PCI UTOPIA VDDIO

Y9 Reserved1VDDIO

Y10 GND GND

Y11 VDDM3 VDDM3

Y12 GND GND

Y13 VDDM3 VDDM3

Y14 GND GND

Y15 VDDM3 VDDM3

Y16 GND GND

Y17 VDDM3 VDDM3

Y18 GND GND

Y19 VDDM3 VDDM3

Y20 GND GND

Y21 GND GND

Y22 VDDDDR VDDDDR

Y23 MDQ13 VDDDDR

Y24 VDDDDR VDDDDR

Y25 GND GND

Y26 MDQ9 VDDDDR

Y27 VDDDDR VDDDDR

Y28 MDQ8 VDDDDR

AA1 Reserved1—

AA2 UTP_TD13/PCI_CBE3 UTOPIA PCI UTOPIA VDDIO

AA3 TDM5RSYN/PCI_AD15/

GPIO103, 6 TDM/GPIO PCI TDM/GPIO VDDIO

AA4 TDM5TDAT, AT/PCI_AD17/

GPIO116TDM/GPIO PCI TDM/GPIO VDDIO

AA5 TDM5R CLK/PCI_AD13/

GPIO283, 6 TDM/GPIO PCI TDM/GPIO VDDIO

AA6 GND GND

Table 1. Signal List by Ball Number (continued)

Ball

Number Signal Name

Power-

Reset

Value

I/O Mult iplexing Mod e 2

Ref.

Supply

0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111)

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0

Freesca le Sem ico nd uctor20

AA7 TDM4TCLK/PCI_AD10 TDM PCI TDM VDDIO

AA8 TDM4TDAT/PCI_AD11 TDM PCI TDM VDDIO

AA9 VDDIO VDDIO

AA10 VDDM3 VDDM3

AA11 GND GND

AA12 VDDM3 VDDM3

AA13 GND GND

AA14 VDDM3 VDDM3

AA15 GND GND

AA16 VDDM3 VDDM3

AA17 GND GND

AA18 VDDM3 VDDM3

AA19 GND GND

AA20 VDDM3 VDDM3

AA21 GND GND

AA22 GND GND

AA23 MDQ15 VDDDDR

AA24 MDQ14 VDDDDR

AA25 MDM1 VDDDDR

AA26 MDQ12 VDDDDR

AA27 MDQS1 VDDDDR

AA28 MDQS1 VDDDDR

AB1 Reserved1-

AB2 UTP_TSOC/RC15 RC15 UTOPIA VDDIO

AB3 VDDIO VDDIO

AB4 TDM6RDAT/PCI_AD20/

GPIO5/IRQ113, 6 TDM/GPIO/ IRQ PCI TDM/GPIO/ IRQ VDDIO

AB5 TDM5RDAT/PCI_AD14/

GPIO93, 6 TDM/GPIO PCI TDM/GPIO VDDIO

AB6 TDM6TS YN /PCI_AD24/

GPIO8/ IRQ143, 6 TDM/GPIO/IRQ PCI TDM/GPIO/IRQ VDDIO

AB7 TDM6R CLK/PCI_AD19/

GPIO4/IRQ103, 6 TDM/GPIO/IRQ PCI TDM/GPIO/IRQ VDDIO

AB8 TDM4RSYN/PCI_AD9 TDM PCI TDM VDDIO

AB9 TDM4RDAT/PCI_AD8 TDM PCI TDM VDDIO

AB10 GND GND

AB11 VDDM3 VDDM3

AB12 GND GND

AB13 VDDM3 VDDM3

AB14 GND GND

AB15 VDDM3 VDDM3

AB16 GND GND

AB17 VDDM3 VDDM3

AB18 GND GND

Table 1. Signal List by Ball Number (continued)

Ball

Number Signal Name

Power-

Reset

Value

I/O Mult iplexing Mod e 2

Ref.

Supply

0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111)

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0

Freescale Semicond uc tor 21

AB19 VDDM3 VDDM3

AB20 GND GND

AB21 GND GND

AB22 VDDDDR VDDDDR

AB23 MECC7 VDDDDR

AB24 MECC1 VDDDDR

AB25 MECC4 VDDDDR

AB26 MECC5 VDDDDR

AB27 MECC2 VDDDDR

AB28 ECC_MDQS VDDDDR

AC1 Reserved1—

AC2 UTP_RD9/RC13 RC13 UTOPIA VDDIO

AC3 UTP_RD8/RC12 RC12 UTOPIA VDDIO

AC4 TDM6TCLK/PCI_AD22 TDM PCI TDM VDDIO

AC5 TDM6RSYN/PCI_AD21/

GPIO6/ IRQ123, 6 TDM/GPIO/IRQ PCI TDM/GPIO/IRQ VDDIO

AC6 VDDIO VDDIO

AC7 TDM3TSYN/RC11 RC11 TDM VDDIO

AC8 PCI_AD23/GPIO7/IRQ13/

TDM6TDAT3, 6/UTP_RMOD TDM/GPIO/IRQ PCI TDM/GPIO/IRQ UTOPIA VDDIO

AC9 TDM7TSYN/ PCI_AD 4 TDM PCI rese rved VDDIO

AC10 VDDM3IO VDDM3IO

AC11 GND GND

AC12 VDDM3 VDDM3

AC13 GND GND

AC14 VDDM3 VDDM3

AC15 GND GND

AC16 VDDM3 VDDM3

AC17 GND GND

AC18 VDDM3 VDDM3

AC19 GND GND

AC20 VDDM3IO VDDM3IO

AC21 Reserved1—

AC22 MECC6 VDDDDR

AC23 MECC3 VDDDDR

AC24 ECC_MDM VDDDDR

AC25 VDDDDR VDDDDR

AC26 MECC0 VDDDDR

AC27 VDDDDR VDDDDR

AC28 ECC_MDQS VDDDDR

AD1 Reserved1—

AD2 GPIO13, 6 GPIO VDDIO

AD3 TMR0/GPIO13 TIMER/GPIO VDDIO

Table 1. Signal List by Ball Number (continued)

Ball

Number Signal Name

Power-

Reset

Value

I/O Mult iplexing Mod e 2

Ref.

Supply

0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111)

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0

Freesca le Sem ico nd uctor22

AD4 GPIO23, 6 GPIO VDDIO

AD5 GND GND

AD6 TDM1TCLK TDM VDDIO

AD7 TDM3TDAT/RC10 RC10 TDM VDDIO

AD8 TDM3RSYN/RC9 RC9 TDM VDDIO

AD9 TDM3RDAT/RC8 RC8 TDM VDDIO

AD10 GND GND

AD11 V25M3 V25M3

AD12 GND GND

AD13 VDDM3 VDDM3

AD14 GND GND

AD15 V25M3 V25M3

AD16 GND GND

AD17 VDDM3 VDDM3

AD18 GND GND

AD19 V25M3 V25M3

AD20 GND GND

AD21 Reserved1—

AD22 VDDDDR VDDDDR

AD23 GND GND

AD24 VDDDDR VDDDDR

AD25 GND GND

AD26 VDDDDR VDDDDR

AD27 GND GND

AD28 VDDDDR VDDDDR

AE1 Reserved1—

AE2 GPIO03, 6 GPIO VDDIO

AE3 GPIO33, 6 GPIO VDDIO

AE4 TDM1RCLK TDM VDDIO

AE5 TDM1TSYN/RC3 RC3 TDM VDDIO

AE6 TDM1TDAT/RC2 RC2 TDM VDDIO

AE7 TDM1RSYN/RC1 RC1 TDM VDDIO

AE8 TDM3RCLK/RC16 RC16 TDM VDDIO

AE9 TDM3TCLK TDM VDDIO

AE10 TDM2TDAT/RC6 RC6 TDM VDDIO

AE11 GPIO21/IRQ13. 6 GPIO/IRQ/SPI_SCK VDDIO

AE12 GND GND

AE13 Reserved1—

AE14 GND GND

AE15 Reserved1—

AE16 Reserved1—

AE17 Reserved1—

AE18 GND GND

Table 1. Signal List by Ball Number (continued)

Ball

Number Signal Name

Power-

Reset

Value

I/O Mult iplexing Mod e 2

Ref.

Supply

0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111)

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0

Freescale Semicond uc tor 23

AE19 GND GND

AE20 VDDM3IO VDDM3IO

AE21 Reserved1—

AE22 GND GND

AE23 GND GND

AE24 GND GND

AE25 VDDDDR VDDDDR

AE26 GND GND

AE27 VDDDDR VDDDDR

AE28 GND GND

AF1 Reserved1—

AF2 VDDIO VDDIO

AF3 GND GND

AF4 TDM0R DAT/

RCFG_CLKIN_RNG RCFG_

CLKIN_

RNG

TDM VDDIO

AF5 TDM0TSYN/RCW_SRC2 RCW_

SRC2 TDM VDDIO

AF6 TDM1RDAT/RC0 RC0 TDM VDDIO

AF7 VDDIO VDDIO

AF8 GND GND

AF9 TDM2RDAT/RC4 RC4 TDM VDDIO

AF10 TDM2TCLK TDM VDDIO

AF11 GPIO22/IRQ43, 6 GPIO/IRQ/SPI_MOSI VDDIO

AF12 GND GND

AF13 GND GND

AF14 VDDM3IO VDDM3IO

AF15 GND GND

AF16 GND GND

AF17 Reserved1—

AF18 VDDM3IO VDDM3IO

AF19 GND GND

AF20 Reserved1—

AF21 Reserved1—

AF22 M3_RESET VDDM3IO

AF23 GND GND

AF24 VDDDDR VDDDDR

AF25 GND GND

AF26 VDDDDR VDDDDR

AF27 GND GND

AF28 VDDDDR VDDDDR

AG1 Reserved1—

AG2 GPIO16/IRQ03, 6 GPIO/IRQ VDDIO

AG3 TDM0TCLK TDM VDDIO

Table 1. Signal List by Ball Number (continued)

Ball

Number Signal Name

Power-

Reset

Value

I/O Mult iplexing Mod e 2

Ref.

Supply

0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111)

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0

Freesca le Sem ico nd uctor24

AG4 TDM0RSYN/RCW_SRC0 RCW_

SRC0 TDM VDDIO

AG5 TDM0RCLK TDM VDDIO

AG6 TDM0TDAT/RCW_SRC1 RCW_

SRC1 TDM VDDIO

AG7 TDM2TSYN/RC7 RC7 TDM VDDIO

AG8 TDM2RCLK TDM VDDIO

AG9 TDM2RSYN/RC5 RC5 TDM VDDIO

AG10 GPIO24/IRQ63, 6 GPIO/IRQ/SPI_SL VDDIO

AG11 GPIO23/IRQ53, 6 GPIO/IRQ/SPI_MISO VDDIO

AG12 Reserved1—

AG13 GND GND

AG14 GND GND

AG15 GND GND

AG16 GND GND

AG17 Reserved1—

AG18 Reserved1—

AG19 GND GND

AG20 GND GND

AG21 VDDM3IO VDDM3IO

AG22 GND GND

AG23 GND GND

AG24 GND GND

AG25 VDDDDR VDDDDR

AG26 GND GND

AG27 VDDDDR VDDDDR

AG28 GND GND

AH1 Reserved1—

AH2 Reserved1—

AH3 Reserved1—

AH4 Reserved1—

AH5 Reserved1—

AH6 Reserved1—

AH7 Reserved1—

AH8 Reserved1—

AH9 Reserved1—

AH10 Reserved1—

AH11 Reserved1—

AH12 Reserved1—

AH13 Reserved1—

AH14 Reserved1—

AH15 Reserved1—

AH16 Reserved1—

Table 1. Signal List by Ball Number (continued)

Ball

Number Signal Name

Power-

Reset

Value

I/O Mult iplexing Mod e 2

Ref.

Supply

0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111)

Electrical Characteri stics

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0

Freescale Semicond uc tor 25

2 Electrica l Characteristics

This document contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing

specifications. For additional information, see the MSC8144E Reference Manual.

2.1 Maximum Ratings

In calculating timing requirements, adding a maximum value of one specification to a minimum value of anoth er specification

does not yield a reasonable sum. A maximum specification is calculated using a worst case variation of process parameter values

in one direction. The minimum specification is calculated using the worst case for the same parameters in the opposite direction.

Therefore, a “maximum” value for a specification never occurs in the same device with a “minimum” value for another

specification; adding a maximum to a minimum represents a condition that can never exist.

AH17 Reserved1—

AH18 Reserved1—

AH19 Reserved1—

AH20 Reserved1—

AH21 Reserved1—

AH22 Reserved1—

AH23 Reserved1—

AH24 Reserved1—

AH25 Reserved1—

AH26 Reserved1—

AH27 Reserved1—

AH28 Reserved1—

Notes: 1. Res erved signals should b e disconnected for compatibility with future revisions of the device.

2. For signals with same functionality in all modes the appropriate cells are empty.

3. The choice between GPIO function and other function is by GPIO registers setu p. For configuration details, see Chapter 23,

GPIO in the MSC8144E Reference Manual.

4. Open-drain signal.

5. Internal 20 KΩ pull-up resistor.

6. For signals with GPIO functionality, the open-drain and internal 20 KΩ pull-up resistor can be configured by GPIO register

programming. See Chapte r 23, GPIO of the MSC8144E Reference Manual for configurat ion details.

CAUTION

This device contains circuitry protecting against damage

due to high static voltage or electrical fields; however,

normal precautions should be taken to avoid exceeding

maximum voltage ratings. Reliability is enhanced if unused

inputs are tied to an appropriate logic voltage level (for

example, either GND or VDD).

Table 1. Signal List by Ball Number (continued)

Ball

Number Signal Name

Power-

Reset

Value

I/O Mult iplexing Mod e 2

Ref.

Supply

0 (000) 1 (001) 2 (010) 3 (011) 4 (100) 5 (101) 6 (110) 7 (111)

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0

Electrical Characteristics

Freesca le Sem ico nd uctor26

Table 2 describes the maximum electrical ratings for the MSC8144 E .

Table 2. Absolute Maximum Ratings

Rating Symbol Value Unit

Core supply voltage Vdd –0.3 to 1 .1 V

PLL supply voltage VDDPLL0

VDDPLL1

VDDPLL2

–0 .3 to 1 .1 V

M3 memory Internal voltage VDDM3 –0.3 to 1.32 V

DDR memory supply voltage

• DDR mode

• DDR2 mode

DDR reference voltage

Input DDR voltage

VDDDDR

MVREF

VINDDR

–0.3 to 2.75

–0.3 to 1.98

–0.3 to 0.51 × VDDDDR

–0.3 to VDDDDR + 0.3

Ethernet 1 I/O voltage

Input Ethernet 1 I/O voltage

VDDGE1

VINGE1

–0.3 to 3.465

–0.3 to VDDGE1 + 0.3

Ethernet 2 I/O voltage

Input Ethernet 2I/O voltage

VDDGE2

VINGE2

–0.3 to 3.465

–0.3 to VDDGE2 + 0.3

I/O voltage excluding Ethernet, DDR, M3, and RapidIO lines

Input I/O voltage

VDDIO

VINIO

–0.3 to 3.465

–0 .3 to VDDIO + 0.3

M3 memory I/O and M3 memory char ge pump voltage

Input M3 memory I/O voltage

VDDM3IO

V25M3

VINM3IO

–0.3 to 2.75

–0.3 to VDDM3IO + 0.3

Rapid I/O C voltage VDDSXC –0.3 to 1.21 V

Rapid I/O P voltage VDDSXP –0.3 to 1.26 V

Rapid I/O PLL voltage VDDRIOPLL –0.3 to 1.21 V

Operating temperature TJ–40 to 105 °C

Storage temperature range TSTG –55 to +150 °C

Notes: 1. Functional operating conditions are given in Table 3.

2. Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond

the listed limits may affect device reliability or cause permane nt damage.

3. PLL supply voltage is specified at input of the fil ter and not at pin of the MSC8144E (see Fi gure 4 5 )

Electrical Characteri stics

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0

Freescale Semicond uc tor 27

2.2 Recommended Operating Conditions

Table 3 lists recommen ded operating conditions. Proper device operation outside of these conditions is not guaranteed.

2.3 Default Output Driver Characteristics

Table 4 provides information on the characteristics of the output driver strengths. The values are preliminary estimates.

Table 3. Recommended Operating Conditions

Rating Symbol Min Nominal Max Unit

Core supply voltage VDD 0.97 1.0 1.05 V

PLL supply voltage VDDPLL0

VDDPLL1

VDDPLL2

0.97 1.0 1.05 V

M3 memory Internal voltage VDDM3 1.14 1.2 1.26 V

DDR memory supply voltage

• DDR mode

• DDR2 mode

DDR reference voltage

VDDDDR

MVREF

2.375

1.71

0.49 × VDDDDR

2.5

1.8

0.5 × VDDDDR

2.625

1.89

0.51 × VDDDDR

Ethernet 1 I/O voltage

• 2.5 V mode

• 3.3 V mode

VDDGE1 2.375

3.135 2.5

3.3 2.625

3.465 V

Ethernet 2 I/O voltage

• 2.5 V mode

• 3.3 V mode

VDDGE2 2.375

3.135 2.5

3.3 2.625

3.465 V

I/O voltage excluding Ethernet,

DDR, M3, and RapidIO lines VDDIO 3.135 3.3 3.465 V

M3 memory I/O and M3 charge

pump voltage VDDM3IO

V25M3

2.375 2.5 2.625 V

Rapid I/O C voltage VDDSXC 0.95 1.0 1.05 V

Rapid I/O P voltage

• Short run (haul) mode

• Long run (haul) mode

VDDSXP 0.95

1.14 1.0

1.2 1.05

1.26 V

Rapid I/O PLL voltage VDDRIOPLL 0.95 1.0 1.05 V

Operating temperature range:

• Standard

• Extended TJ

–40

—

105

°C

Note: PLL supply voltage is specified at input of the filter and not at pin of the MSC8144E (see Figure 4 5 ).

Table 4. Output Drive Impedance

Driver Type Output Impedance (Ω)

DDR signal 18

DDR2 signal 18

35 (half strength mode)

PCI signals 25

Rapid I/O signals 100

Other signals 50

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0

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Freesca le Sem ico nd uctor28

2.4 Thermal Characteristics

Table 5 describes thermal characteristics of the MSC8144E for the FC-PBGA packages.

2.5 Power Characteristics

The estimated typical power dissipation for MSC8144E versus the core frequency is shown in Table 6.

The typical power values were measured using an EFR code with the device running at a junction temperature of 25°C. No

peripherals were enabled and the ICache was not enabled. The source code was optimized to use all the ALUs and AGUs and

Table 5. Thermal Characteristics for the MSC8144E

Characteristic Symbol

FC-PBGA

29 × 29 mm5Unit

Natural

Convection 200 ft/min

(1 m/s) airflow

Junction-to-ambient1, 2 RθJA 20 15 °C/W

Junction-to-ambient , four-layer board1, 3 RθJA 15 12 °C/W

Junction-to-board (bottom)4RθJB 7°C/W

Junction-to-case5RθJC 0.8 °C/W

Notes: 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mount ing site (board)

temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal

resistance.

2. Per JEDEC JES D51-2 with the single layer board (JESD51-3) horizontal.

3. Per JEDEC JES D51-6 with the board (JESD51-7) horizontal.

4. Thermal resistance between the die and the printed circuit board per JEDEC JESD 51-8. Board temperature is measured on

the top surface of the board near the package.

5. Thermal resistance between the active surface of the die and the case top surface determined by the cold plate method (MIL

SPEC-883 Method 1012.1) with the calculated case temperature.

Table 6. Power Dissipation

Extended Core Frequency Core Frequency Typical Unit

266 400 TBD W

533 TBD

667 TBD

800 TBD

333 500 TBD W

667 TBD

833 TBD

1000 TBD

400 400 TBD W

600 TBD

800 TBD

1000 TBD

500 500 TBD W

750 TBD

1000 TBD

Note: Measured for 1.0 V core at 25°C junction temperature.

Electrical Characteri stics

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0

Freescale Semicond uc tor 29

all four cores. It was created using CodeWarrior® 3.0. These values are provided as examples only. Power cons ump tion is

application dependent and varies widely. To assure proper board design with regard to thermal dissipatio n and maintaining

proper operating temper atures , ev aluate p ower co nsump t ion for you r applicati on and use the design guidel ines in Section 3 of

this document.

At allowable voltage levels, Table 7 lists the estimated power dissipation on the 1.0-V AVDD supplies for the MSC8144E PLLs.

2.6 DC Electrical Characteristics

This section describes the DC electrical characteristics for the MSC8144E.

2.6.1 DDR SDRAM DC Electrical Characteristics

This section describes the DC electrical specifications for the DDR SDRAM interface of the MSC8144E.

Note: DDR SDRAM uses VDDDDR(typ) = 2.5 V and DDR2 SDRAM us es VDDDDR(typ) = 1.8 V.

2.6.1.1 DDR2 (1.8 V) SDRAM DC Electrical Characteristics

Table 8 provides the recommended operating conditions for the DDR2 SDRAM component(s) of the MSC8144E when

VDDDDR(typ) = 1.8 V.

Table 7. MSC 8144E PLLs Pow er Dissipation

PLL supply Typical Maximum Unit

VDDPLL0 TBD 10 mW

VDDPLL1 TBD 10 mW

VDDPLL2 TBD 10 mW

Note: Typical value is based on VDD = 1.0 V, TA = 70°C, TJ = 105°C.

Table 8. DDR2 SDRAM DC Electrical Characteristics for VDD(typ) = 1.8 V

Parameter/Condition Symbol Min Max Unit

I/O supply voltage1VDDDDR 1.7 1.9 V

I/O reference voltage2MVREF 0.49 × VDDDDR 0.51 × VDDDDR V

I/O termination voltage3VTT MVREF –0.04 MV

REF + 0.04 V

Input high voltage VIH MVREF + 0.125 VDD +0.3 V

Input low voltage VIL –0.3 MVREF – 0.125 V

Output leakage current4IOZ –30 30 μA

Output high current (VOUT = 1.420 V) IOH –13.4 — mA

Output low current (VOUT = 0.280 V) IOL 13.4 — mA

Notes: 1. VDDDDR is expected to be within 50 mV of the DRAM VDD at all times.

2. MVREF is expected to be equal to 0.5 × VDDDDR, and to track VDDDDR DC variations as measured at the receiver.

Peak-to-peak noise on MVREF may not exceed ±2% of the DC value.

3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be

equal to MVREF. This rail should track variations in the DC level of VDDDDR.

4. Output leakage is measured with all outputs are disabled, 0 V ≤ VOUT ≤ VDDDDR.

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0

Electrical Characteristics

Freesca le Sem ico nd uctor30

Table 9 provides the DDR capacitance when VDDDDR(typ) = 1.8 V.

2.6.1.2 DDR (2.5V) SDRAM DC Electrical Characteristics

Table 10 provides the recommended operating conditions for the DDR SDRAM component(s) of the MSC8144E when

VDDDDR(typ) = 2.5 V.

Table 11 provides the DDR capacitance when VDDDDR (typ) = 2.5 V.

Table 12 lists the current draw characteristics for MVREF.

Table 9. DDR2 SDRAM Capacitance for VDDDDR(typ) = 1.8 V

Parameter/Condition Symbol Min Max Unit

Input/output capacitance: DQ, DQS, DQS CIO 68pF

Delta input/output capacitance: DQ, DQS, DQS CDIO —0.5pF

Note: This parameter is sampled. VDDDDR = 1.8 V ± 0.090 V, f = 1 MHz, TA =25°C, V

OUT = VDDDDR/2, VOUT (peak-to-peak) = 0.2 V.

Table 10. DDR SDRAM DC Electrical Characteristics for VDDDDR (typ) = 2.5 V

Parameter/Condition Symbol Min Max Unit

I/O supply voltage1VDDDDR 2.3 2.7 V

I/O reference voltage2MVREF 0.49 × VDDDDR 0.51 × VDDDDR V

I/O termination voltage3VTT MVREF – 0.04 MVREF + 0.04 V

Input high voltage VIH MVREF + 0.15 VDD + 0.3 V

Input low voltage VIL –0.3 MVREF – 0.15 V

Output leakage current4IOZ –30 30 μA

Output high current (VOUT = 1.95 V) IOH –16.2 — mA

Output low current (VOUT = 0.35 V) IOL 16.2 — mA

Notes: 1. VDDDDR is expected to be within 50 mV of the DRAM VDD at all times.

2. MVREF is expected to be equal to 0.5 × VDDDDR, and to track VDDDDR DC variations as measured at the receiver.

Peak-to-peak noise on MVREF may not exceed ±2% of the DC value.

3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be

equal to MVREF. This rail should track variations in the DC level of VDDDDR.

4. Output leakage is measured with all outputs are disabled, 0 V ≤ VOUT ≤ VDDDDR.

Table 1 1. DDR SDRAM Capacitance for VDDDDR (typ) = 2.5 V

Parameter/Condition Symbol Min Max Unit

Input/output capacitance: DQ, DQS CIO 68pF

Delta input/output capacitance: DQ, DQS CDIO —0.5pF

Note: This parameter is sampled. VDDDDR = 2.5 V ± 0.125 V, f = 1 MHz, TA = 25°C, VOUT = VDDDDR/2, VOUT (peak-to-peak) = 0.2 V.

Table 12. Current Draw Characteristics for MVREF

Parameter / Condition Symbol Min Max Unit

Current draw for MVREF IMVREF — 500 μA

Note: The voltage regulator for MVREF must be able to supply up to 500 μA current.

Electrical Characteri stics

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0

Freescale Semicond uc tor 31

2.6.2 Serial RapidIO DC Electrical Characteristics

DC receiver logic levels are not defined since the receiver is AC-coupled.

2.6.2.1 DC Requirements for SerDes Reference Clocks

The SerDes reference clocks SRIO_REF_CLK and SRIO_REF_CLK are AC-coupled differential inputs. Each differential

clock input has an intern al 50 Ω termin ation to GNDSXC. The reference clock must be abl e to drive this ter mination. The

recommended minimum operating voltage is –0.4 V; the recommended maximum operating voltage is 1.32 V; and the

maximum absolute voltag e is 1.72 V.

The maximum average current allowed in each input is 8 mA. This current limitation sets the maximum common mode input

voltage to be less than 0.4 V (0.4 V/50 Ω = 8 mA) while the minimum common mode input level is GNDSXC. For example, a

clock with a 50 /50 duty cycle can be driv en by a current sour ce output that ranges fro m 0 mA to 16 mA ( 0–0.8 V). Th e input is

AC-coupled internally, so, therefore, the exact common mode input voltage is not critical.

Note: This internal AC-couple network does not function cor rectly with reference clock frequencies below 90 MHz.

If the device driving the SRIO_REF_CLK inputs cannot drive 50 Ω to GNDSXC, or if it exceeds the maximum input current

limitations, then it must use external AC-coupling. The minimum differential peak-to-peak amplitude of the input clock is 0.4 V

(0.2 V peak-to-peak per phase). T he maximum differential peak-to-peak amplitude of the input clock is 1.6 V peak-to-peak (see

Figure 5. The termination to GNDSXC allows com patibility with HCSL type reference clocks specified for PCI-Express

applications. Many other low voltage differential type outputs can be used but will probably need to be AC-coupled due to the

limite d common mode input range. LVPECL output s can prod uce too lar ge an amplitude and may need to be source terminated

with a divider network to reduce the amplitude. The amplitude of the clock must be at least a 400 mV dif ferential peak-peak for

single-ended clock. If driven differentially, each signal wire needs to drive 100 mV around common mode voltage. The

differential reference clock (SRIO_REF_CLK/ SRIO_REF_CLK) input is HCSL-compatible DC coupled or LVDS-compatible

with AC-couplin g.

Figure 5. SerDes Reference Clocks Input Stage

2.6.2.2 Spread Spectrum Clock

SRIO_REF_CLK/ SRIO_REF_CLK is designed to work with a spread spectrum clock (0 to 0.5% spr eading at 3033 kHz rate

is allowed), assuming both ends have same reference clock. For better r e sults use a source without significant unintended

modulation.

SRIO_REF_CLK

50 Ω

GNDSXC

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0

Electrical Characteristics

Freesca le Sem ico nd uctor32

2.6.3 PCI DC Electrical Characteristics

The measurements in Table 13 assume the following system conditions:

•T

A = 25 °C

•GND = 0 VDC

Note: The leakage current is measured for nominal conditions.

2.6.4 TDM DC Electrical Characteristics

The measurements in Table 14 assume the following system conditions:

•T

A = 25 °C

•GND = 0 VDC

Note: The leakage current is measured for nominal conditions.

2.6.5 UART DC Electrical Characteristics

TBD

Table 13. PCI DC Electrical Characteristics

Characteristic Symbol Min Max Unit

Supply voltage 3.3 V VDDPCI 3.135 3.465 V

Inp u t h igh voltage VIH 0.5 × VDDPCI 3.465 V

Inp u t lo w vol t age VIL –0.5 0.3 × VDDPCI V

Input Pull-up voltage2VIPU 0.7 × VDDPCI

Input leakage current, 0<VIN <VDDPCI IIN –10 10 μA

Tri-state (high impedance off state) leakage current, 0<VIN <VDDPCI IOZ –10 10 μA

Signal low input current, VIL = 0.4 V2IL–10 10 μA

Signal high input current, VIH = 2.0 V2IH–10 10 μA

Output high voltage, IOH = –0.5 μA,

except open drain pins VOH 0.9 × VDDPCI —V

Output low voltage, IOL= 1.5 μAV

OL —0.1 × VDDPCI V

Input Pin Capacitance CIN 10 pF

Notes: 1. See Figure 6 for undershoot and overshoot voltages.

2. Not tested. Guaranteed by design.

Table 14. TDM DC Electrical Characteristics

Characteristic Symbol Min Max Unit

Supply voltage 3.3 V VDDTDM 3.135 3.465 V

Input high voltage VIH 2.0 3.465 V

Input low voltage VIL –0.3 0.8 V

Input leakage current, 0<VIN <VDDTDM IIN –10 10 μA

Tri-state (high impedance off state) leakage current, IOZ –10 10 μA

Signal input current,1IL–10 10 μA

Output high voltage, IOH = –1.6 mA, VOH 2.4 — V

Output low voltage, IOL= 0.4mA VOL —0.4V

Pin Capacitance Cp 8 pF

Note: Not tested. Guaranteed by design.

Electrical Characteri stics

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0

Freescale Semicond uc tor 33

2.6.6 Ethernet DC Electrical Character istics

The measurements assume:

•T

A = 25 °C

•GND = 0 VDC

2.6.6.1 MII, SMII and RMII DC Electrical Characteristics

2.6.6.2 RGMII DC Electrical Characteristics

Table 15. MII, SMII and RMII DC Electrical Characteristics

Characteristic Symbol Min Max Unit

Supply voltage 3.3 V VDDGE1

VDDGE2

3.135 3.465 V

Input high voltage VIH 2.0 3.465 V

Input low voltage VIL –0.3 0.8 V

Input leakage current, VIN = supply voltage IIN –10 10 μA

Signal low input current, VIL = 0.4 V1IL–10 10 μA

Signal high input current, VIH = 2.4 V1IH–10 10 μA

Output high voltage, IOH = –4 mA, VOH 2.4 3.465 V

Output low voltage, IOL= 4mA VOL —0.4V

Input Pin Capacitance CIN 8pF

Note: Not tested. Guaranteed by design.

Table 16. RGMII DC Electrical Characteristics

Characteristic Symbol Min Max Unit

Supply voltage 2.5V VDDGE1

VDDGE2

2.375 2.625 V

Input high voltage VIH 1.7 2.625 V

Input low voltage VIL –0.3 0.7 V

Input high voltage ac VIH-AC 1.9 — V

Input low voltage ac VIL-AC —0.7V

Input leakage current, VIN = supply voltage IIN –10 10 μA

Signal low input current, VIL = 0.4 V1IL–10 10 μA

Signal high input current, VIH = 2.4 V1IH–10 10 μA

Output high voltage, IOH = –1 mA, VOH 2.0 2.625 V

Output low voltage, IOL= 1 mA VOL —0.4V

Input Pin Capacitance CIN 8pF

Note: Not tested. Guaranteed by design.

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0

Electrical Characteristics

Freesca le Sem ico nd uctor34

2.6.7 ATM/UTOPIA DC Electrical Characteristics

2.6.8 SPI DC Electrical Character istics

Table 18 provides the SPI DC electrical characteristics.

2.6.9 GPIO, EE, CLKIN, JTAG Ports DC Electrical Characteristics

The measurements in Table 19 assume:

•T

A = 25 °C

•GND = 0 VDC

Note: The leakage current is measured for nominal conditions.

Table 17. ATM/UTOPI DC Electrical Characteristics

Characteristic Symbol Min Max Unit

Supply voltage 3.3 V VDDIO 3.135 3.465 V

Input high voltage VIH 2.0 3.465 V

Input low voltage VIL –0.3 0.8 V

Input leakage current, VIN = supply voltage I IN –10 10 μA

Signal low input current, VIL = 0.4 V1IL–10 10 μA

Signal high input current, VIH = 2.4 V1IH–10 10 μA

Output high voltage, IOH = –8 mA, VOH 2.4 3.465 V

Output low voltage, IOL= 8 mA VOL —0.5V

Notes: 1. Not tested. Guaranteed by design.

Table 18. SPI DC Electrical Characteristics

Characteristic Symbol Condition Min Max Unit

Input high voltage VIH 2.0 OVDD+0.3 V

Input low voltage VIL –0.3 0.8 V

Input current IIN ±5 μA

Output high voltage VOH IOH = –8.0 mA 2.4 — V

Output low voltage VOL IOL = 8.0 mA — 0.5 V

Output low voltage VOL IOL = 3.2 mA — 0.4 V

Table 19. GPIO and CLKIN DC Electrical Characteristics

Characteristic Symbol Min Max Unit

Supply voltage 3.3 V VDDIO 3.135 3.465 V

Input leakage current, VIN = supply voltage IIN –10 10 μA

Tri-state (high impedance off state) leakage current, VIN = supply voltage IOZ –10 10 μA

Signal low input current, VIL = 0.4 V2IL–10 10 μA

Signal high input current, VIH = 2.0 V2IH–10 10 μA

Output high voltage, IOH = –2 mA,

except open drain pins VOH 2.4 3.465 V

Electrical Characteri stics

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0

Freescale Semicond uc tor 35

2.7 AC Timings

The following sections include illustrations and tables of clock diagrams, signals, and parallel I/O outputs and inputs.

2.7.1 Start-Up T im ing

Starting the device requires coordination among several input sequences including clocking, reset, and power. Section 2.7.2

describes the clocking characteristics. Section 2.7.3 describes the reset and power-up characteristics. You must use the

following guidelines when starting up an MSC8144E device:

• PORESET and TRST mu st be as sert ed ex ternally f or the d uration of the power -up sequence using the VDDIO (3.3 V)

supply. See Table 24 fo r timin g. TRST deassertion does not have to be synchronized with PORESET deassertion .

During f uncti onal oper at ion when J TAG is not used , TRST can b e a sserted and r emain assert ed after the po wer ramp.

Note: For applications that use M3 memory, M3_RESET should replicate the PORESET sequence timing, but using the

VDDM3IO (2.5 V) supply. See Section 3.1.1, Power-on Sequence for additional design information.

•CLKIN should start toggling at least 32 cycles before the PORESET deassertion to guarantee co rrect device operation

(see Figure 7). 32 cycles should be accounted only after VDDIO reaches its nominal value.

• CLKIN and PCI_CLK_IN should either be stable low during the power-up of VDDIO supply and start their swings after

power-up or should swing within VDDIO range during VDDIO power-up., so their amplitude grows as VDDIO grows

during power-up.

Figure 7 shows a sequence in which VDDIO is raised after VDD and CLKIN begins to toggle with the raise of VDDIO supply.

Output low voltage, IOL= 3.2 mA VOL —0.4V

Notes: 1. See Figure 6 for undershoot and overshoot voltages.

2. Not tested. Guaranteed by design.

Figure 6. Overshoot/Undershoot Voltage for VIH and VIL

Table 19. GPIO and CLKIN DC Electrical Characteristics (continued)

Characteristic Symbol Min Max Unit

GND

GND – 0.3 V

GND – 0.7 V

VIL

VIH

Must not exceed 10% of clock period

VDDIO + 17%

VDDIO + 5%

VDDIO

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0

Electrical Characteristics

Freesca le Sem ico nd uctor36

2.7.2 Clock and Timing Signals

The following sections include a descrip tion of clock s ignal characteristics. Table 20 shows the maximu m frequency valu es for

internal (Core, Reference, Bus and DSI) and external (CLKIN, PCI_CLK_IN and CLKOUT. The user must ensure that

maximum frequency values are not exceeded.

2.7.3 Reset Timing

The MSC8144E has several in puts to the reset logic:

• Power-on reset (PORESET)

• Exter nal hard reset (HRESET)

• Extern a l soft reset (SRESET)

• Software watchdog reset

•JTAG reset

• RapidIO reset

• Software hard reset

• Software soft reset

All MSC8144E reset sources are fed into the reset controller , which takes different actions depending on the source of the reset.

The reset status register indicates the most recent sources to cause a reset. Table 22 describes the reset sources.

Figure 7. Start-Up Seq uence with VDD Raised Before VDDIO with CLKIN Started with VDDIO

Table 20. Clock Frequencies

Characteristic Symbol MIN Max Unit

CLKIN frequency FCLKIN 25 150 MHz

PCI_CLK_IN frequency FPCI_CLK_IN 25 150 MHz

CLKIN duty cycle DCLKIN 40 60 %

PCI_CLK_IN duty c ycle DPCI_CLK_IN 40 60 %

Table 21. Clock Parameters

Characteristic Min Max Unit

CLKIN slew rate 1—V/ns

PCI_CLK_IN sl ew ra te 1 — V/ns

Voltage

Time

3.3 V

DDIO

Nominal

PORESET/TRST asserted

Nominal

CLKIN starts toggling

applie d PORESET

DDIO

applie d

1.0 V

DDIO

= Nominal

Electrical Characteri stics

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0

Freescale Semicond uc tor 37

Table 22. Reset Sources

Table 23 summarizes the reset actions that occur as a result of the different reset sources.

Name Direction Description

Power-on rese t

(PORESET)Input Initiates the power-on reset flow that resets the MSC8144E and configures various attributes of the

MSC8144E. On PORESET, the entire MSC8144E device is reset. All PLLs states is reset, HRESET

and SRESET are driven, the extended cores are reset, and system configuration is sampled. The

reset source and word are configured only when PORESET is asserted.

External hard

reset (HRESET)Input/ Output Initiates the hard reset flow that configures various attributes of the MSC8144E. While HRESET is

asserted, S RES ET is also asserted. HRESET is an open-drain pin. Upon hard reset, HRESET and

SRESET are driven, the extended cores are reset, and system configuration is sampled. Note that

the RCW (reset Configuration Word) is not reloaded during HRESET assertion after out of power on

reset sequence. The reset configuration word is described in the Reset chapter in the MSC8144E

Reference Manual.

External soft reset

(SRESET)Input/ Output Initiates the soft reset flow. The MSC8144E detects an external assertion of SRESET only if it occurs

while the MSC8144E is not asserting reset. SRESET is an open-drain pin. Upon soft reset, SRESET

is driven, the extended cores are reset, and system configuration is maintained.

Host reset

command through

the TAP

Internal When a host reset command is written through the Test Access Port (TAP), the TAP logic asserts the

soft reset signal and an internal soft reset sequence is generated.

Software

watchdog reset Internal When the MSC8144E watchdog count reaches zero, a software watchdog reset is signalled. The

enabled software watchdog event then generates an internal hard reset sequence.

RapidIO reset Internal When t he RapidIO logic asserts the RapidIO hard reset signal, it generates an internal hard reset

sequence.

Software hard

reset Internal A hard reset sequence can be initialized by writing to a memory mapped register (RCR)

Software soft reset Internal A soft reset sequence can be initialized by writing to a memory mapped register (RCR)

Table 23. Reset Actions for Each Reset Source

Reset Action/Reset Source

Power-On Reset

(PORESET)Hard Reset (HRESET) Soft Reset (SRESET)

External only External or Internal

(Software Watch dog ,

Software or RapidIO)

External or

internal

Software

JTAG Command:

EXTEST, CLAMP, or

HIGHZ

Configuration pins sampled (Refer to

Section 2.7.3.2 for details).Yes NoNoNo

PLL state reset Yes No No No

Select reset configuration source Yes No No No

System reset configuration write Yes No No No

HRESET driven Yes Yes No No

IPBus modules reset (TDM, UART, SWT ,

DDRC, IPBus master, GIC, HS, and GPIO) Yes Yes Yes Yes

SRESET driven Yes Yes Yes Depends on command

Extended cores reset Yes Yes Yes Yes

CLASS registers reset Yes Yes Some

registers Some registers

Timers, Performance Monitor Yes Yes No No

Packet Processor, PCI, DMA Yes Yes Most

registers Most registers

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0

Electrical Characteristics

Freesca le Sem ico nd uctor38

2.7.3.1 Power-On Reset (PORESET) Pin

Asserting PORESET initiates the power-on reset flow. PORESET must be asserted extern ally for at least 32 CLKIN cycles after

VDD and VDDIO are both at their nominal levels.

2.7.3.2 Reset Configuration

The MSC8144E has two mechanis ms for wri ting the reset configuration:

• Through the I2C port

• Through external pins

• Through internal hard coded

Twenty-three signals (see Section 1 for signal description details) are sampled during the power-on reset sequence to define the

Reset Word Configuration Source and operating conditions:

• RCW_SRC[2–0]

• RC[16–0]

The RCFG_CLKIN_RNG pin must be valid during power-on or hard reset sequence. The STOP_BS pin must be always valid

and is also sampled during power-on reset sequence for RCW loading from an I2C EEPROM.

2.7.3.3 Reset Timing Tables

Table 24 and Figure 8 describe the reset timing for a reset configuration .

Table 24. T iming for a Reset Configuration Wr it e

No. Characteristics Expression Max Min Unit

1 Required external POR ESE T duration minimum

• 25 MHz <= CLKIN < 44 MHz

• 44 MHz <= CLKIN < 66 MHz

• 66 MHz <= CLKIN < 100 MHz

• 100 MHz <= CLKIN < 133 MHz

32/CLKIN 1280

728

485

320

727

484

320

241

2 Delay from de-assertion of external PORESET to HRESET deassertion for

external pins and hard coded RCW

• 25 MHz <= CLKIN < 66 MHz

• 66 MHz <= CLKIN <= 133 MHz

Delay from de-assertion of external PORESET to HRESET deassertion for

loading RCW the I2C interface

• 25 MHz <= CLKIN < 44 MHz

• 44 MHz <= CLKIN < 66 MHz

• 66 MHz <= CLKIN < 100 MHz

• 100 MHz <= CLKIN < 133 MHz

15369/CLKIN

34825/CLKIN

92545/CLKIN

107435/CLKIN

124208/CLKIN

157880/CLKIN

615

528

3702

2441

1882

1579

233

262

2103

1627

1242

1187

μs

3 Delay from HRESET deassertion to SRESET deassertion

• REFCLK = 25 MHz to 133 MHz 16/CLKIN 640 120 ns

Note: Timings are not tested, but are guaranteed by design.

Electrical Characteri stics

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0

Freescale Semicond uc tor 39

See also Reset Errata for PLL lock and reset duration.

2.7.4 DDR SDRAM AC Timing Specifications

This section describes the AC electrical characteristics for the DDR SDRAM interface.

2.7.4.1 DDR SDRAM Input Timings

Table 25 provides the input AC timing specifications for th e DD R SDRAM when VDD(t yp) = 2 .5 V.

Table 26 provides the input AC timing specifications for th e DD R SDRAM when VDD(t yp) = 1 .8 V.

Table 27 provides the input AC timing specifications for the DDR SDRAM interface.

Figure 8. Timing for a Reset Configuration Write

Table 25. DDR SDRAM Input AC Timing Specifications for 2.5-V Interface

Parameter Symbol Min Max Unit

AC input low voltage VIL —MV

REF – 0.31 V

AC input high voltage VIH MVREF + 0.31 — V

Note: At recommended operating conditions with VDD of 2.5 ± 5%.

Table 26. DDR2 SDRAM Input AC Timing Specifications for 1.8-V Interface

Parameter Symbol Min Max Unit

AC input low voltage VIL —V

REF – 0.25 V

AC input high voltage VIH VREF + 0.25 — V

Note: At recommended operating conditions with VDD of 1.8 ± 5%.

Table 27. DDR SDRAM Input AC Timing Specifications

Parameter Symbol Min Max Unit

Controller Skew for MDQS—MDQ/MECC/MDM1

•400 MHz

•333 MHz

•266 MHz

•200 MHz

tCISKEW –365

–390

–428

–490

365

390

428

490

Notes: 1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit t hat is

captured with MDQS[n]. Subtract this value from the total timing budget.

2. At recommended operating conditions with VDD (1.8 V or 2.5 V) ± 5%

PORESET

HRESET

Input

Output (I/O)

SRESET

Output (I/O)

RCW_SRC2,RCW_SRC1, RCW _SRC 0,STOP_BS and RCFG_CLKIN _RNG

pins must be valid

Reset configuration write

sequence during this

period.

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0

Electrical Characteristics

Freesca le Sem ico nd uctor40

2.7.4.2 DDR SDRAM Output AC Timing Specifications

Table 28 provides the output AC timing specifications for the DDR SDRAM interface.

Table 28. DDR SDRAM Output AC Timing Specifications

Parameter Symbol 1Min Max Unit

MCK[n] cycle time, (MCK[n]/MCK[n] crossing)2tMCK 310ns

ADDR/CMD output setup with respect to MCK3

•400 MHz

•333 MHz

•266 MHz

•200 MHz

tDDKHAS 1.95

2.40

3.15

4.20

—

ADDR/CMD output hold with respect to MCK3

•400 MHz

•333 MHz

•266 MHz

•200 MHz

tDDKHAX 1.95

2.40

3.15

4.20

—

MCSn output setup with respect to MCK3

•400 MHz

•333 MHz

•266 MHz

•200 MHz

tDDKHCS 1.95

2.40

3.15

4.20

—

MCSn output hold with respect to MCK3

•400 MHz

•333 MHz

•266 MHz

•200 MHz

tDDKHCX 1.95

2.40

3.15

4.20

—

MCK to MDQS Skew4tDDKHMH –0.6 0.6 ns

MDQ/MECC /MDM output setup with respect to MDQS5

•400 MHz

•333 MHz

•266 MHz

•200 MHz

tDDKHDS,

tDDKLDS 700

900

1100

1200

—

MDQ/MECC /MDM output hold with respect to MDQS5

•400 MHz

•333 MHz

•266 MHz

•200 MHz

tDDKHDX,

tDDKLDX 700

900

1100

1200

—

MDQS preamble start6tDDKHMP –0.5 × tMCK – 0.6 –0.5 × tMCK +0.6 ns

MDQS epilogue end6tDDKHME –0.6 0.6 ns

Notes: 1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing

(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,

tDDKHAS symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes from the high (H) state until outputs

(A) are setup (S) or output valid time. Also, tDDKLDX symbolizes DDR timing (DD) for the time tMCK mem ory clock reference

(K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.

2. All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V.

3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM /M DQ S. For the

ADDR/CMD setup and hold specifications, it is assumed that the Clock Control register is set to adjust the memory clocks by

1/2 applied cycle.

4. Note that tDDKHMH follows the symbol conventions described in note 1. For example, t DDKHMH describes the DDR timing (DD)

from the rising edge of the MCK(n) clock (KH) until the MDQS signal is valid (MH). tDDKHMH can be modified through control

of the DQSS override bits in the TIMING_CFG_2 register. This will typically be set to the same delay as the clock adjust in the

CLK_CNTL register. The timing parameters listed in the table assume that these 2 parameters have been set to the same

adjustment value. See the MSC8144E Reference Manual for a description and understanding of the timing modifications

enabled by use of these bits.

5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC

(MECC), or data mask (MD M). The data strobe should be centered inside of the data eye at the pins of the microprocessor.

6. All outputs are referenced to the rising edge of MCK(n) at the pins of the microprocessor. Note that tDDKHMP follows the

symbol conventions described in note 1.

7. At recommended operating conditions with VDD (1.8 V or 2.5 V) ± 5%.

Electrical Characteri stics

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0

Freescale Semicond uc tor 41

Figure 9 shows the DDR SDRAM output timing for the MCK to MDQS skew measurement (tDDKHMH).

Figure 10 shows the DDR SDRA M output timing diagram.

Figure 9. Timing for tDDKHMH

Figure 10. DDR SDRAM Output Timing

MDQS

MCK[n]

MCK[n] tMCK

tDDKH M H m ax) = 0. 6 ns

tDDKHMH(min) = –0. 6 ns

MDQS

ADDR/CMD

tDDKHAS, tDDKHCS

tDDKHMH

tDDKLDS

tDDKHDS

MDQ[x]

MDQS[n]

MCK[n]

MCK[n] tMCK

tDDKLDX

tDDKHDX

D1D0

tDDKHAX ,tDDKHCX

Write A0 NOOP

tDDKHME

tDDKHMP

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0

Electrical Characteristics

Freesca le Sem ico nd uctor42

Figure 11 pro vides th e AC test load for the DDR bus.

2.7.5 Serial RapidIO Timing and SGMI I Timing

2.7.5.1 AC Requirements for SRIO_REF_CLK and SRIO_REF_CLK

Table 29 lists AC re quirements.

Figure 11. DDR AC Test Load

Table 29. SDn_REF _CLK and SDn_REF_CLK AC Requirements

Parameter Description Symbol Min Typical Max Units Comments

REFC LK cyc le time tREF — 10 (8, 6.4) — ns 8 ns applies only to serial RapidIO system

with 125-MHz reference clock. 6.4 ns

applies only to serial RapidIO systems with

a 156.25 MHz reference clock.

Note: SGMII uses the 8 ns (125 MHz)

value only.

REFCLK cycle-to-cyc le

jitter tREFCJ — — 80 ps Difference in the period of any two

adjacent REFCLK cycles

Phase jitter tREFPJ –40 — 40 ps Deviation in edge location with respect to

mean edge location

Output Z0 = 50 ΩRL = 50 Ω

VDD/2

Electrical Characteri stics

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0

Freescale Semicond uc tor 43

2.7.5.2 Signal Definitions

LP-Serial links use differential signaling. Th is section defines terms used in the des cri ption and specification of differential

signals. Figure 12 shows how the signals are defined. The figure shows waveforms for either a transmitter output (TD and TD)

or a recei ver in put (RD and RD). Each signal swings between voltage levels A and B, where A > B.

Note: This explanation uses generic TD/TD/RD/RD signal names. These correspond to SRIO_TXD/SRIO_TXD/

SRIO_RXD/SRIO_RXD respectively.

Using these waveforms, the definitio ns are as follows:

1. The transmitter output signal s and th e receiver input signal s TD, TD, RD and RD each have a peak-to-peak voltage

(VPP) swing of A – B.

2. The differential output signal of the transmitter, VOD, is defined as VTD – VTD.

3. The differential input signal of the receiver, VID, is defined as VRD – VRD.

4. The differential output s ignal of the transmitter and the dif ferential input s ignal of the receiver each range fro m A – B

to –(A – B).

5. The peak value of the differential transmitter output signal and the differential receiver input signal is A – B.

6. The value of the differential transmitter output signal and the differential receiver input signal is 2 ×(A – B) VPP.

T o illustrate these definitions using real values, consider the case of a CML (Current Mode Logic) transmitter that has a common

mode voltage of 2 .25 V and each o f its outputs, TD and TD , has a swing that goes between 2.5 V and 2.0 V. Using these va lues,

the peak-to-peak vo ltage swing of the signals TD and TD is 500 mVPP. The differential output signal ranges between 500 mV

and –500 mV. The peak differential voltage is 500 mV. The peak-to-peak differential voltage is 1000 mVPP.

Note: AC electrical specifications are given for transmitter and receiver. Long run and short run interfaces at three baud

rates (a total of six cases) are described. The parameters for the AC electrical specifications are guided by the XAUI

electrical interface specified in Clause 47 of IEEE™ Std 802.3ae-2002™. XAUI has similar application goals to

serial RapidIO. The goal of this standard is that electrical designs for serial RapidIO can reuse electrical designs for

XAUI, suitably modified for applications at the baud intervals and reaches described herein.

2.7.5.3 Equalization

W ith the use of high speed serial links, the interconnect media will cause degradation of the signal at the receiver. Effects such

as Inter-Symbol Interference (ISI) or data dependent jitter are produced. This loss can be large enough to degrade the eye

opening at the receiver beyond what is allowed in the specification. To negate a portion of these effects, equalization can be

used. The most common equalization techniques that can be used are:

• A passive high pass filter network placed at the receiver. This is often referred to as passive equali zation.

• The use of active circuits in the receiver. This is often referred to as adaptive equalization.

Figure 12. Differential VPP of Transmitter or Receiver

Differen tial Peak-Peak = 2

(A – B)

A TD or RD

TD or RD

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0

Electrical Characteristics

Freesca le Sem ico nd uctor44

2.7.5.4 Transmitter Specifications

LP-Serial transmitter electrical and timing sp ecifications are stated in the text and ta b les of th is section. The differen tial return

loss, S11, of the transmitter in each case shall be better than

• –10 dB for (baud frequency)/10 < freq(f) < 625 MHz, and

• –10 dB + 10log(f/625 MHz) dB for 625 MHz ≤ freq(f) ≤ ba ud frequency

The reference impedance for the differential return loss measurements is 100 Ω resistive. Differential return loss includes

contributions from internal circuitry, packaging, and any external components r elated to the driver. The output impedance

requirement applies to all valid output levels. It is recommended that the 20–80% rise/fall time of the transmitter, as measured

at the transmitter output, have a minimum value 60 ps in each case. It is also recommended that the timing skew at the output

of an LP-Serial transmitter between the two signals comprising a differential pair not exceed 25 ps at 1.25 GB, 20 ps at 2.50

GB, and 15 ps at 3.125 GB.

Table 30. Short Run Transmitter AC Timing Specifications—1.25 GBaud

Characteristic Symbol Range Unit Notes

Min Max

Output Voltage, VO–0.40 2.30 V Voltage relative to COMMON of either signal

comprising a differential pair

Differential Output Voltage VDIFFPP 500 1000 mVPP

Determ inis tic Jit ter JD0.17 UIPP

Total Jitt e r JT0.35 UIPP

Multiple output skew SMO 1000 ps Skew at the transmitter output between lanes of a

multilane link

Unit Interval UI 800 800 ps ±100 ppm

Table 31. Short Run Transmitter AC Timing S pecifications—2.5 GBaud

Characteristic Symbol Range Unit Notes

Min Max

Output Voltage, VO–0.40 2.30 V Voltage relative to COMMON of either signal

comprising a differential pair

Differential Output Voltage VDIFFPP 500 1000 mVPP

Determ inis tic Jit ter JD0.17 UIPP

Total Jitt e r JT0.35 UIPP

Multiple Output skew SMO 1000 ps Skew at the transmitter output between lanes of a

multilane link

Unit Interval UI 400 400 ps ±100 ppm

Table 32. Short Run Transmitter AC Timing Specifications—3.125 GBaud

Characteristic Symbol Range Unit Notes

Min Max

Output Voltage, VO-0.40 2.30 V Voltage relative to COMMON of either signal

comprising a differential pair

Differential Output Voltage VDIFFPP 500 1000 mVPP

Determ inis tic Jit ter JD0.17 UIPP

Total Jitt e r JT0.35 UIPP

Multiple output skew SMO 1000 ps Skew at the transmitter output between lanes of a

multilane link

Unit Interval UI 320 320 ps ±100 ppm

Electrical Characteri stics

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0

Freescale Semicond uc tor 45

For each baud rate at which an LP-Serial transmitter is specified to operate, the output eye pattern of the transmitter shall fall

entirely within the unsh aded portion of the transmitter outp ut compliance mask shown in Figure 13 with the parameters

specified in Table 36 when measured at the output pins of the device and the device is driving a 100 Ω ±5% differential resistive

load. The output eye pattern of an LP-Serial transmitter that implements pre-emphasis (to equalize the link and reduce

inter-symbol interference) need only comply with the transmitter outp u t comp liance mask when pre-emphasis is disabled or

minimized.

Table 33. Long Run Transmitter AC Timing Specifications—1.25 GBaud

Characteristic Symbol Range Unit Notes

Min Max

Output Voltage, VO-0.40 2.30 V Voltage relative to COMMON of either signal

comprising a differential pair

Differential Output Voltage VDIFFPP 800 1600 mVPP

Determ inis tic Jit ter JD0.17 UIPP

Total Jitt e r JT0.35 UIPP

Multiple output skew SMO 1000 ps Skew at the transmitter output between lanes of a

multilane link

Unit Interval UI 800 800 ps ±100 ppm

Table 34. Long Run Transmitter AC Timing Specifications—2.5 GBaud

Characteristic Symbol Range Unit Notes

Min Max

Output Voltage, VO-0.40 2.30 V Voltage relative to COMMON of either signal

comprising a differential pair

Differential Output Voltage VDIFFPP 800 1600 mVPP

Determ inis tic Jit ter JD0.17 UIPP

Total Jitt e r JT0.35 UIPP

Multiple output skew SMO 1000 ps Skew at the transmitter output between lanes of a

multilane link

Unit Interval UI 400 400 ps ±100 ppm

Table 35. Long Run Transmitter AC T iming Specifications—3.125 GBaud

Characteristic Symbol Range Unit Notes

Min Max

Output Voltage, VO-0.40 2.30 V Voltage relative to COMMON of either signal

comprising a differential pair

Differential Output Voltage VDIFFPP 800 1600 mVPP

Determ inis tic Jit ter JD0.17 UIPP

Total Jitt e r JT0.35 UIPP

Multiple output skew SMO 1000 ps Skew at the transmitter output between lanes of a

multilane link

Unit Interval UI 320 320 ps ±100 ppm

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0

Electrical Characteristics

Freesca le Sem ico nd uctor46

2.7.5.5 Receiver Specifications

LP-Serial receiver electrical and timing specifications are stated in the text and tab les of this section. Rec eiver input impedance

shall result in a differential return loss better that 10 dB and a common mode return loss better than 6 dB from 100 MHz to 0.8

× baud frequency. This includes contributions from internal circuitry, the package, and any external components related to the

receiver. AC coupling components are included in this requirement. The reference impedance for return loss measurements is

100 Ω resistive for differential return loss and 25 Ω resistive for common mode.

Figure 13. Transmitter Output Compliance Mask

Table 36. Transmitter Differential Output Eye Diagram Parameters

Transmitter Type VDIFFmin (mV) VDIFFmax (m V) A (UI) B (UI)

1.25 GBaud short range 250 500 0.175 0.39

1.25 GBaud long range 400 800 0.175 0.39

2.5 GBaud short range 250 500 0.175 0. 39

2.5 GBaud long range 400 800 0.175 0.39

3.125 GBaud short range 250 500 0.175 0. 39

3.125 GBaud long range 400 800 0.175 0.39

Table 37. Receiver AC Timing Specifications—1.25 GBaud

Characteristic Symbol Range Unit Notes

Min Max

Differential Input Voltage VIN 200 1600 mVPP Measured at receiver

Deterministic Jit ter Tolerance JD0.37 UIPP Measured at receiver

Combined Deterministic and Random

Jitter Tolerance JDR 0.55 UIPP Measured at receiver

VDIFF min

VDIFF max

-VDIFF min

-VDIFF max

0B1-B1

Time in UI

Transmitter Differential Output Voltage

A1-A

Electrical Characteri stics

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0

Freescale Semicond uc tor 47

Total Jitt e r Tolera n ce JT0.65 UIPP Measured at receiver. Total jitter is composed of

three components, deterministic jitter, random jitter

and single frequency sinusoidal jitter. The sinusoidal

jitter may have any amplitude and frequency in the

unshaded region of Figure 1 4 . The sinusoidal jitter

component is included to ensure margin for low

frequency jitter, wander, noise, crosstalk and other

variable system effects.

Multiple Input Skew SMI 24 ns Skew at the receiver input between lanes of a

multilane link

Bit Error Rate BER 10–12

Unit Interval UI 800 800 ps ±100 ppm

Table 38. Receiver AC Timing Specifications—2.5 GBaud

Characteristic Symbol Range Unit Notes

Min Max

Differential Input Voltage VIN 200 1600 mVPP Measured at receiver

Deterministic Jit ter Tolerance JD0.37 UIPP Measured at receiver

Combined Deterministic and Random

Jitter Tolerance JDR 0.55 UIPP Measured at receiver

Total Jitt e r Tolera n ce JT0.65 UIPP Measured at receiver. Total jitter is composed of

three components, deterministic jitter, random jitter

and single frequency sinusoidal jitter. The sinusoidal

jitter may have any amplitude and frequency in the

unshaded region of Figure 1 4 . The sinusoidal jitter

component is included to ensure margin for low

frequency jitter, wander, noise, crosstalk and other

variable system effects.

Multiple Input Skew SMI 24 ns Skew at the receiver input between lanes of a

multilane link

Bit Error Rate BER 10–12

Unit Interval UI 400 400 ps ±100 ppm

Table 39. Receiver AC Timing Specifications—3.125 GBaud

Characteristic Symbol Range Unit Notes

Min Max

Differential Input Voltage VIN 200 1600 mVPP Measured at receiver

Deterministic Jit ter Tolerance JD0.37 UIPP Measured at receiver

Combined Deterministic and Random

Jitter Tolerance JDR 0.55 UIPP Measured at receiver

Total Jitt e r Tolera n ce JT0.65 UIPP Measured at receiver. Total jitter is composed of

three components, deterministic jitter, random jitter

and single frequency sinusoidal jitter. The sinusoidal

jitter may have any amplitude and frequency in the

unshaded region of Figure 1 4 . The sinusoidal jitter

component is included to ensure margin for low

frequency jitter, wander, noise, crosstalk and other

variable system effects.

Multiple Input Skew SMI 22 ns Skew at the receiver input between lanes of a

multilane link

Table 37. Receiver AC Timing Specifications—1.25 GBaud (continued)

Characteristic Symbol Range Unit Notes

Min Max

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0

Electrical Characteristics

Freesca le Sem ico nd uctor48

2.7.5.6 Receiver Eye Diagrams

For each bau d rate at which an LP-Serial receiv er is specified to oper ate, the receiver shall meet the corresponding b it error rate

specification (Table 37, Table 38, and Table 39) when the eye pattern of the receiver test signal (exclusive of sinusoidal jitter)

falls entirely within the unshaded portion of the receiver input compliance mask shown in Figure 15 with the parameter s

specified in Table 40. The eye pattern of the receiver test signal is measured at the input pins of the receiving device with the

device replaced with a 100 Ω ±5% differential resistive load.

Bit Error Rate BER 10–12

Unit Interval UI 320 320 ps ±100 ppm

Figure 14. Single Frequency Sinusoidal Jitter Limits

Table 39. Receiver AC Timing Specifications—3.125 GBaud (continued)

Characteristic Symbol Range Unit Notes

Min Max

8.5 UI p-p

0.10 UI p-p

Sinusoidal

Jitter

Amplitude

22.1 kHz 1.875 MHz 20 MHzFrequency

Electrical Characteri stics

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0

Freescale Semicond uc tor 49

2.7.5.7 Measurement and Test Requirements

Since the LP-Serial electrical specification are guided by the XAUI electrical interface specified in Clause 47 of IEEE Std.

802.3ae-20 02™, the measurement and tes t requirements defined her e are similarly guided by Cl ause 47. In addition, the CJPAT

test pattern defined in Annex 48A of IEEE Std. 802.3ae-2002 is specified as the test pattern for use in eye pattern and jitter

measurements . A nnex 48B of IEEE Std. 802.3ae-2002 is recommended as a reference for additional information on jitter test

methods.

2.7.5.8 Eye Template Measurements

For the purpose of eye template measurements, th e effects of a single-pole high pass filter with a 3 dB point at (baud

frequency)/1667 is applied to the jitter. The data pattern for template measurements is the continuous jitter test pattern (CJPAT)

defined in Annex 48A of IEEE Std. 802.3ae. All lanes of the LP-Serial link shall be active in both the transmit and receive

directions, an d opposite ends of the links shall use as ynchronou s clocks. Four lane implementations shall u se CJPAT as defined

in Annex 48A. Single lane implementations shall use the CJPAT sequence specified in Annex 48A for tr ans mission on lane 0.

The amount of data represented in the eye shall be adequate to ensure that the bit error ratio is less than 10–12. The eye pattern

shall be measured with AC couplin g and the compliance template centered at 0 Volts differential. The left and right edges of

the template shall be aligned with the mean zero crossing points of the measured data eye. The load for this test shall be 100 Ω

resistive ±5% differential to 2.5 GHz.

Figure 15. Receiver Input Compliance Mask

Table 40. Receiver Input Compliance Mask Parameters Exc lusive of Sinusoidal Jitter

Receiver Type VDIFFmin (mV) VDIFFmax (mV) A (UI) B (UI)

1.25 GBaud 100 800 0.275 0.400

2.5 GBaud 100 800 0.275 0.400

3.125 GBaud 100 800 0.275 0.400

VDIFF max

–VDIFF max

VDIFF min

–VDIFF min

Time (UI)

Receiver Differential Input Voltage

A B 1 – B 1 – A

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0

Electrical Characteristics

Freesca le Sem ico nd uctor50

2.7.5.9 Jitter Test Measurements

For the purpose of jitter measurement, the eff ects of a single-pole high pass filter with a 3 dB p oint at (baud frequency)/1667 is

applied to the jitter. The data pattern for jitter measurements is the Continuous Jitter Test Pattern (CJPAT) pattern defined in

Annex 48A of IEEE Std. 802.3 ae. All lanes of the LP-Serial link shall be active in both the transmit and receive directions, and

opposite ends of the links sh all use asynchron ous clocks. Four lane implementations shall use CJPAT as defined in Annex 48A.

Single lane implementat ions shall use the CJPAT sequence specified in Annex 48A for transmis sion on lane 0. Jitter shall be

measured with AC coupling and at 0 V differential. Jitter measurement for the transmitter (or for calibration of a jitter tolerance

setup) shall be performed with a test procedure result ing in a BER curve such as that described in Annex 48B of IEEE Std.

802.3ae.

2.7.5.10 Transmit Jitter

Transmit jitter is measured at the driver ou tput wh en terminated into a load of 100 Ω resistive ±5% differential to 2.5 GHz.

2.7.5.11 Jitter Tolerance

Jitter tolerance is measured at the receiver using a jitter tolerance test signal. This signal is obtained by first producing the sum

of deterministic and random jitter defined in Section 2.7.5.9 and then adjusting the signal amplitude until the data eye contacts

the 6 p oints o f the minimum ey e o pen ing of the receive template shown in Figur e 15 and Table 40. Note that for this to occur ,

the test signal must have vertical waveform symmetry about the average value and have horizontal symmetry (including jitter)

about the mean zero crossing. Eye template measurement requ irements are as defined above. Random jitter is calibrated using

a high pass filter with a low frequency corner at 20 MHz and a 20 dB/decade roll-off below this. The required sinusoidal jitter

specified in Section 8.6 is then added to the signal and the test load is replaced by the receiver being tested.

2.7.6 PCI Timing

This section describes the gen eral AC tim ing parameters of the PCI bus. Table 41 provides the PCI AC timing specifications.

Table 41. PCI AC Timing Spe cifications

Parameter Symbol 33 MHz 66 MHz Unit

Min Max Min Max

Output delay tPCVAL 2.0 11.0 1.0 6.0 ns

High-Z to Valid Output delay tPCON 2.0 — 1.0 — ns

Valid to High-Z Output delay tPCOFF — 28 — 14 ns

Input setup tPCSU 7.0 — 3.0 — ns

Input hold tPCH 0—0—ns

Re se t a ctive ti m e a fter PCI_CLK_IN s t a b le tPCRST-CLK 100 — 100 — μs

Reset active to output float delay tPCRST-OFF — 40 — 40 ns

Reset active time after power stable tPCRST 1—1—ms

HRESET high to first Configuration Access tPCRHFA 32M — 32M — clocks

Notes: 1. See the timing measurement conditions in the PCI 2.2 Local Bus Specifications.

2. All PCI signals are measured from OVDD/2 of the rising edge of PCI_SYNC_IN to 0.4 × OVDD of the signal in question for

3.3-V PCI signaling levels.

3. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered

through the component pin is less than or equal to the leakage current specification.

4. Input timings are measured at the pin.

5. The reset assertion timing requirement for HRESET is in Table 24 and Figure 8

Electrical Characteri stics

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0

Freescale Semicond uc tor 51

Figure 16 provides the AC test load for the PCI.

Figure 17 shows the PCI inp ut AC timing conditions.

Figure 18 shows the PCI output AC timing conditions.

Figure 16. PCI AC Test Load

Figure 17. PCI Input AC Timing Measurement Conditions

Figure 18. PCI Output AC Timing Measurement Condition

Output Z0 = 50 ΩVDD/2

RL = 50 Ω

tPCSU

CLK

Input

tPCH

CLK

Output Delay

tPCVAL

High-Impedance

tPCOFF

Output

tPCON

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0

Electrical Characteristics

Freesca le Sem ico nd uctor52

2.7.7 TDM Timing

Figure 19 shows the TDM input AC ti mi ng.

Note: For some TDM mo des receive data and receive s ync are being inp ut on o ther pins. This timing is va lid fo r them as well.

See the MSC8144E Ref erence Manual .

Figure 20 shows TDMxTSYN AC timing in TSO=0 mode.

Figure 21 shows the TDM Output AC timing

Table 42. TDM Timing

Characteristic Symbol Expression Min Max Units

TDMxRCLK/TDMxTCLK tTDMC TC116 — ns

TDMxRCLK/TDMxTCLK high pulse width tTDMCH (0.5 ± 0.1) × TC 7 — ns

TDMxRCLK/TDMxTCLK low pulse width tTDMCL (0.5 ± 0.1) × TC 7 — ns

TDM receive all input set-up time related to TDMxRCLK

TDMxTSYN input set-up time related to TDMxTCLK in TSO=0 mode tTDMVKH 3.6 — ns

TDM receive all input hold time related to TDMxRCLK

TDMxTSYN input hold time related to TDMxTCLK in TSO=0 mode tTDMXKH 1.9 — ns

TDMxTCLK high to TDMxTDAT output active2tTDMDHOX 2.5 — ns

TDMxTCLK high to TDMxTDAT output valid2tTDMDHOV —9.8ns

All output hold time (except TDMxTSYN) 3tTDMHOX 2.5 — ns

TDMxTCLK high to TDMxTDAT output high impedance2tTDMDHOZ —9.8ns

TDMxTCLK high to TDMxTSYN output valid2tTDMSHOV —9.25ns

TDMxTSYN output hold time3tTDMSHOX 1.6 — ns

Notes: 1. Values are based on a a maximum frequency of 62.5 MHz. The TDM interface supports any frequency below 62.5 MHz.

2. Values are based on 20 pF capacitive load.

3. Values are based on 10 pF capacitive load.

Figure 19. TDM Inputs Signals

Figure 20. TDMxTSYN in TSO=0 mode

TDMxRCLK

TDMxRDAT

TDMxRSYN

tTDMC

tTDMCH tTDMCL

tTDMVKH

tTDMVKH tTDMXKH

tTDMXKH

TDMxTCLK

TDMxTSYN

tTDMVKH tTDMXKH

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0

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Note: For some TDM modes transmit data is being output on other pins. This timing is valid for it as well. See the MSC8144E

Reference Manual

2.7.8 UART Timing

Figure 22 shows the UART input AC timing

Figure 23 shows the UART o utput AC timing

Figure 21. TDM Output Signals

Table 43. UART Timing

Characteristics Symbol Expression Min Max Unit

URXD and UTXD inputs high/low duration TUREFCLK 16 × TREFCLK 160 — ns

URXD and UTXD inputs rise/fall time TUAVKH 6ns

UTXD output rise/fall time TUAVXH 5.5 ns

Note: TUREFCLK = TREFCLK is guaranteed by design.

Figure 22. UART Input Timing

Figure 23. UART Output Timing

TDMxTCLK

TDMxTDAT

TDMxTSYN

tTDMDHOX

tTDMDHOV tTDMDHOZ

tTDMHOX

tTDMC

tTDMCH tTDMCL

tTDMSHOX

tTDMSHOV

UTXD, URXD

TUREFCLK

inputs

TUAVKH TUAVKH

TUREFCLK

UTXD output

TUAVXH TUAVXH

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0

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2.7.9 Timer Timing

Figure 24 shows the timer input AC timing

2.7.10 Ethernet Timing

This section describes the AC electrical characteristics for the Ethernet interface.

There are programmable delay units (PDU) that should be programmed differently for each Interface to meet timing. There is

a general configuration register 4 (GCR4) used to configure the timing. For additi onal information, see the MSC8144E

Reference Manual.

2.7.10.1 Management Interface Timing

Table 44. Timer Timing

Characteristics Symbol Min Unit

TIMERx frequency TTMREFCLK 10.0 ns

TIMERx Input high phase TTMCH 4.0 ns

TIMERx Output low phase TTMCL 4.0 ns

Figure 24. Timer Timing

Table 45. Ethernet Controller Management Interface Timing

Characteristics Symbol Min Max Unit

ETHMDC clock pulse width high tMDCH 32 — ns

ETHMDC to ETHMDIO delay2tMDKHDX 10 70 ns

ETHMDIO to ETHMDC rising edge set-up time tMDDVKH 5—ns

ETHMDC rising edge to ETHMDIO hold time tMDDXKH 0—ns

ETHMDC rise time. tMDCR —10ns

ETHMDC fall time. tMDHF —10ns

Notes: 1. Typical ETHM DC frequency (fMDC) is 2.5 MHz with a 400 ns period (tMDC). The value depends on the source clock. For

example, for a source clock of 267 MHz, the maximum frequency is 8.3 MHz and the minimum frequency is 1.2 MHz. For a

375 MHz clock, the maximum fr equency is 11.7 MHz and the minimum frequency is 1.7 MHz.

2. The value depends on the source clock. For example, for a source clock of 267 MHz, the delay is 70 ns. For a source clock of

333 MHz, the delay is 58 ns.

TTMREFCLK

TTMCL

TMCH

TIMERx (Input)

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0

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2.7.10.2 MII Transmit AC Timing Specifications

Table 46 provides the MII transmit AC timing specificatio ns.

Figure 26 shows the MII transmit AC timing diagram.

2.7.10.3 MII Receive AC Timing Specifications

Table 47 provides the MII receive AC timing specifications.

Figure 25. MII Management Interface Timing

Table 46. MII Transmit AC Timing Specifications

Parameter/Condition Symbol 1Min Max Unit

TX_CLK duty cycle tMTXH/tMTX 35 65 %

TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay tMTKHDX 025ns

TX_CLK data clock rise tMTXR 1.0 4.0 ns

TX_CLK data clock fall tMTXF 1.0 4.0 ns

Notes: 1. Typical TX_CLK period (tMTX) for 10 Mbps is 400 ns and for 100 Mbps is 40 ns.

2. Program GCR4 as 0x00030CC3.

Figure 26. MII Transmit AC Timing

Table 47. MII Receive AC Timing Specifications

Parameter/Condition Symbol 1Min Max Unit

RX_CLK duty cycle tMRXH/tMRX 35 65 %

ETHMDC

ETHMDIO

(Input)

(Output)

MDC tMDCR

tMDCH

tMDDXKH

tMDDVKH

tMDKHDX

tMDHF

TX_CLK

TXD[3:0]

tMTKHDX

tMTX

tMTXH

tMTXR

tMTXF

TX_EN

TX_ER

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0

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Figure 27 provides the AC test load.

Figure 28 shows the MII receive AC timing diagram.

2.7.10.4 RMII Transmit and Receive AC Timing Specifications

Table 48 provides the RMII transmit and receive AC timing specifications.

RXD[3:0], RX_DV, RX_ER set up time to RX_CLK tMRDVKH 10.0 — ns

RXD[3:0], RX_DV, RX_ER hold time to RX_CLK tMRDXKH 2—ns

RX_CLK clock rise tMRXR 1.0 4.0 ns

RX_CLK clock fall time tMRXF 1.0 4.0 ns

Notes: 1. Typical RX_CLK period (tMRX) for 10 Mbps is 400 ns and for 100 Mbps is 40 ns.

2. Program GCR4 as 0x00030CC3.

Figure 27. AC Test Load

Figure 28. MII Receive AC Timing

Table 48. RMII Transmit and Receive AC Timing Specifications

Parameter/Condition S ymbol 1Min Max Unit

REF_CLK duty cycle tRMXH/tRMX 35 65 %

REF_CLK to RMII data TXD[1–0], TX_EN delay tRMTKHDX 210ns

RXD[1–0], CRS_DV, RX_ER setup time to REF_CLK tRMRDVKH 4.0 — ns

RXD[1–0], CRS_DV, RX_ER hold time to REF_CLK tRMRDXKH 2.0 — ns

REF_CLK data clock rise tRMXR 1.0 4.0 ns

REF_CLK data clock fall tRMXF 1.0 4.0 ns

Typical REF_CLK clock period (tRMX) is 20 ns

Notes: 1. Ty pical REF_CLK clock period (t RMX) is 20 ns

2. Program GCR4 as 0x00001405

Table 47. MII Receive AC Timing Specifications (continued)

Parameter/Condition Symbol 1Min Max Unit

Output Z0 = 50 ΩVDD/2

RL = 50 Ω

RX_CLK

RXD[3:0]

tMRDXKH

tMRX

tMRXH

tMRXR

tMRXF

RX_DV

RX_ER tMRDVKH

Valid Data

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0

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Figure 29 shows the RMII transmit and receive AC timing diagram.

Figure 30 provides the AC test load.

2.7.10.5 SMII AC Timing Specification

Figure 31 provides the AC test load.

Figure 29. RMII Transmit and Receive AC Timing

Figure 30. AC Test Load

Table 49. SMII Mode Signal Timing

Characteristics Symbol Min Max Unit

ETHSYNC_IN, ETHRXD to ETHCLOCK rising edge set-up time tSMDVKH 1.5 — ns

ETHCLOCK rising edge to ETHSYNC_IN, ETHRX D hold time tSMDXKH 1.0 — ns

ETHCLOCK rising edge to ETHSYNC, ETHTXD output delay tSMXR 1.5 5.0 ns

Notes: 1. Typical REF_CLK clock period is 8ns

2. Measured using a 5 pF load.

3. Measured using a 15 pF load

4. REF_CLK duty cycle is TBD.

5. Program GCR4 as 0x00002008

REF_CLK

TXD[1–0]

tRMTKHDX

tRMX

tRMXH

tRMXR

tRMXF

TX_EN

RXD[1–0]

tRMRDXKH

CRS_DV

RX_ER tRMRDVKH

Valid Data

Output Z0 = 50 ΩVDD/2

RL = 50 Ω

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0

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Figure 31. SMII Mode Signal Timing

2.7.10.6 RGMII AC Timing Specifications

Table 50 presents the RGMII AC timing specifications for applications requiring an on-board delayed clock.

Table 51 presents the RGMII AC timing specification for applications required non-delayed clock on board.

Table 50. RGMII with On-Board Delay AC Timing Specifications

Parameter/Condition Symbol Min Typ Max Unit

Data to clock output skew (at transmitter) tSKEWT -0.5 — 0.5 ns

Data to clock input skew (at receiver) 2tSKEWR 0.9 — 2.6 ns

Clock cycle duration 3tRGT 7.2 8.0 8.8 ns

Duty cycle for 1000Base-T 4, 5 tRGTH/tRGT 45 50 55 %

Duty cycle for 10BA SE- T and 100BASE-TX 3, 5 tRGTH/tRGT 40 50 60 %

Rise time (20%–80%) tRGTR — — 0.75 ns

Fall time (20%–80%) tRGTF — — 0.75 ns

GTX_CL K125 reference clock period tG12 6—8.0—ns

GTX_C LK125 ref erence clock duty cycle tG125H/tG125 47 — 53 %

Notes: 1. At recommended operating conditions with LVDD of 2.5 V +/- 5%.

2. This implies that PC board design will require clocks to be routed such that an additional trace delay of greater than 1.5 ns will

be added to the associated clock signal.

3. For 10 and 100 Mbps, tRGT scales to 400 ns +/- 40 ns and 40 ns +/- 4 ns, respectively.

4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as long

as the minimum duty cycle is not violated and stretching occurs for no more than three tRGT of the lowest speed transitioned

between.

5. Duty cycle reference is LVdd/2.

6. This symbol is used to represent the external GTX_CLK125 and does not follow the original symbol naming conven tion.

7. GCR4 should be programmed as 0x00001004.

Table 51. RGMII with No On-Board Delay AC Timing Specifications

Parameter/Condition Symbol Min Typ Max Unit

Data to clock output skew (at transmitter) tSKEWT 0.9 — 2.6 ns

Data to clock input skew (at receiver) 2tSKEWR -0.5 — 0.5 ns

Clock cycle duration 3tRGT 7.2 8.0 8.8 ns

Duty cycle for 1000Base-T 4, 5 tRGTH/tRGT 45 50 55 %

Duty cycle for 10BA SE- T and 100BASE-TX 3, 5 tRGTH/tRGT 40 50 60 %

Rise time (20%–80%) tRGTR — — 0.75 ns

Fall time (20%–80%) tRGTF — — 0.75 ns

GTX_CL K125 reference clock period tG12 6—8.0—ns

Valid

ETHCLOCK

ETHSYNC_IN

ETHRXD

ETHSYNC

ETHTXD Valid Valid

tSMXR

tSMDXKH

tSMDVKH

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0

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Figure 32 shows the RGMII AC timi ng and m ultiplexing diagrams.

GTX_C LK125 ref erence clock duty cycle tG125H/tG125 47 — 53 %

Notes: 1. At recommended operating conditions with LVDD of 2.5 V +/- 5%.

2. This implies that PC board design will require clocks to be routed with no additional trace delay

3. For 10 and 100 Mbps, tRGT scales to 400 ns +/- 40 ns and 40 ns +/- 4 ns, respectively.

4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as long

as the minimum duty cycle is not violated and stretching occurs for no more than three tRGT of the lowest speed transitioned

between.

5. Duty cycle reference is LVdd/2.

6. This symbol is used to represent the external GTX_CLK125 and does not follow the original symbol naming conven tion.

7. GCR4 should be programmed as 0x00048120.

Figure 32. RGMII AC Timing and Multiplexing s

Table 51. RGMII with No On-Board Delay AC Timing Specifications (continued)

Parameter/Condition Symbol Min Typ Max Unit

GTX_CLK

tRGT

tRGTH

tSKEWT

TX_CTL

TXD[8:5]

TXD[7:4]

TXD[9]

TXERR

TXD[4]

TXEN

TXD[3:0]

(At Transmitte r)

TXD[8:5][3:0]

TXD[7:4][3:0]

TX_CLK

(At PHY)

RX_CTL

RXD[8:5]

RXD[7:4]

RXD[9]

RXERR

RXD[4]

RXDV

RXD[3:0]

RXD[8:5][3:0]

RXD[7:4][3:0]

RX_CLK

(At PHY)

tSKEWR

tSKEWT

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2.7.11 ATM/UTOPIA Tim ing

Table 52 provides the UTOPIA input and output AC timing specifications.

Figure 33 provides the AC test load for the UTOPIA.

Figure 34 shows the UTOPIA timing with external clock.

Table 52. UTOPIA AC Timing Specifications

Characteristic Symbol Min Max Unit

UTOPIA outputs—External clock delay tUEKHOV 19ns

UTOPIA outputs—External clock High Impedance tUEKHOX 19ns

UTOPIA inputs—External clock input setup time tUEIVKH 4ns

UTOPIA inputs—External clock input hold time tUEIXKH 1ns

Note: Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are

measured at the pin. Although the specifications generally reference the rising edge of the clock, these AC timing diagrams also

apply when the falling edge is the active edge.

Figure 33. UTOPIA AC Test Load

Figure 34. UTOPIA AC Timing (External Clock)

Output Z0 = 50 ΩVDD/2

RL = 50 Ω

UTOPIA CLK (input)

tUEIXKH

tUEIVKH

tUEKHOV

Input Signals:

UTOPIA

Output Signals:

UTOPIA

UEKHOX

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0

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2.7.12 SPI Timing

Table 52 provides the SPI input and output AC timing specifications.

Figure 35 provides the AC test load for the SPI.

Figure 35. SPI AC Test Load

Figure 36 through Figure 37 represent the AC timings from Table 52. Note that although the specifications generally referen ce

the rising edge of the clock, these AC timing diagrams also apply when the falling edge is the active edge.

Figure 36 shows the SPI timings in slave mode (external clock).

Figure 36. SPI AC Timing in Slave Mode (External Clock)

Figure 37 shows the SPI timings in master mode (internal clock).

Table 53. SPI AC Timing Specifications 1

Characteristic Symbol

2Min Max Unit

SPI outputs valid—Master mode (internal clock) delay tNIKHOV 6ns

SPI outputs hold—Master mode (internal clock) delay tNIKHOX 0.5 ns

SPI outputs valid—Slave mode (external clock) delay tNEKHOV 8ns

SPI outputs hold—Slave mode (external clock) delay tNEKHOX 2ns

SPI inputs—Master mode (internal clock input setup time tNIIVKH 4ns

SPI inputs—Master mode (internal clock input hold time tNIIXKH 0ns

SPI inputs—Slave mode (external clock) input setup time tNEIVKH 4ns

SPI inputs—Slave mode (external clock) input hold time t NEIXKH 2ns

Notes:

1. Output specifications are measured fro m the 50 percent level of the rising edge of CLKIN to the 50 percent level of the signal.

Timings are measured at the pin.

2. The symbols for timing specifications follow the pattern of t(first two lett ers of functio nal block)(s ignal)(st at e) (referenc e)(sta te ) for inputs

and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, t NIKHOX symbolizes the internal timing

(NI) for the time SPICLK clock reference (K) goes to the high state (H) until outputs (O) are invalid (X).

Output Z0 = 50 ΩOVDD/

RL = 50 Ω

SPICLK (Input)

tNEIXKH

tNEIVKH

tNEKHOX

Input Signals:

SPIMOSI

(See Note)

Output Sign als :

SPIMISO

(See Note)

Note: The clock edge is selectable on SPI.

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0

Freesca le Sem ico nd uctor62

Figure 37. SPI AC Timing in Master Mode (Internal Clock)

2.7.13 GPIO Timing

Figure 38 shows the GPIO timing.

Table 54. GPIO Timing

Characteristics Symbol Min Max Unit

REFCLK edge to GPIO out valid (GPIO out delay time) tGPKHOV -6.9ns

REFCLK edge to GPIO out not valid (GPIO out hold time) tGPKHOX 1.3 - ns

REFCLK edge to high impedance on GPIO out tGPKHOZ -6.2ns

GPIO in valid to REFCLK edge (GPIO in set-up time) tGPIVKH 3.7 - ns

REFCLK edge to GPIO in not valid (GPIO in hold time) tGPIXKH 0.5 - ns

Figure 38. GPIO Timing

SPICLK (Output)

tNIIXKH

tNIKHOX

Input Signals:

SPIMISO

(See Note)

Output Sign als :

SPIMOSI

(See Note)

Note: The clock edge is selectable on SPI.

tNIIVKH

REFCLK

GPIO

(Output)

GPIO

(Input) Valid

tGPKHOZ

High Impedance

tGPIVKH tGPIXKH

tGPKHOV

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0

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2.7.14 EE Signals

Figure 39 shows the signal behavior of the EE pins.

2.7.14.1 JTAG Signals

Figure 40 Shows the Test Clock Input Timing Diagram

Table 55. EE Pin Timing

Characteristics Symbol Type Min

EE (input) tEEIN Asynchronous 4 core clock periods

EE (output) tEEOUT Synchronous to Core clock 1 core clock period

Notes: 1. The ratio between the core clock and CLKOUT is configured during power-on-reset.

2. Re fe r to Table 1-4 on page 1-6 for details on EE pin functionality.

Figure 39. EE Pin Timing

Table 56. JTAG Timing

Characteristics Symbol All frequenci e s Unit

Min Max

TCK cycle time tTCKX 33.0 — ns

TCK clock high phase measured at VM = 1.6 V tTCKH 13.0 — ns

TCK rise and fall times tTCKR —3.0ns

Boundary scan input data set-up time tBSVKH 0.0 — ns

Boundary scan input data hold time tBSXKH 10.0 — ns

TCK fall to output data valid tTCKHOV — 20.0 ns

TCK fall to output high impedance tTCKHOZ — 24.0 ns

TMS, TDI data set-up time tTDIVKH 0.0 — ns

TMS, TDI data hold time tTDIXKH 5.0 — ns

TCK fall to TDO data valid tTDOHOV — 10.0 ns

TCK fall to TDO high impedance tTDOHOZ — 12.0 ns

TRST assert time tTRST 100.0 — ns

Note: All timings apply to OnCE module data transfers as well as any other transfers via the JTAG port.

Figure 40. Test Clock Input Ti min g

EE out

EE in

tEEIN

tEEOUT

TCK

(Input)

VMVM

TCKX

tTCKH

tTCKR

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Figure 41 Shows the boundary scan (JTAG) timing diagram.

Figure 42 Shows the test access port timing diagram

Figure 43 Shows the TRST timing diagra m.

Figure 41. Boundary Scan (JTAG) Timing

Figure 42. Test Access Port Timing

Figure 43. TRST Timing

TCK

(Input)

Data

Inputs

Data

Outputs

Data

Outputs

Input Data Valid

Output Data Valid

tBSXKH

tBSVKH

tTCKHOV

tTCKHOZ

TCK

(Input)

TDI

(Input)

TDO

(Output)

TDO

(Output)

Input Data Valid

Output Data Valid

TMS

tTDIVKH tTDIXKH

tTDOHOV

tTDOHOZ

TRST

(Input) tTRST

Hardware Design Considerations

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0

Freescale Semicond uc tor 65

3 Hardware Des ign Considerations

The following sections discuss areas to consider when the MSC8144E device is designed into a system.

3.1 Start-up Sequencing Recommendations

3.1.1 Power-on Sequence

Use the following guidelines for power-on sequencing:

• There are no dependencies in power-on/power-off sequence between VDDM3 and VDD supplies.

• There are no dependencies in power-on/power-off sequence between RapidIO supplies: VDDSXC, VDDSXP,

VDDRIOPLL and other MSC8144E supplies.

•V

DDPLL should be coupled with the VDD power rail with extremely low impedance path.

External voltage applied to any input line must not exceed the related to this port I/O supply by more than 0.6 V at any time,

includin g during power-up. Some design s requi re pul l-up voltages a pplied to se lecte d i nput lines during pow er-up for

configuration purposes. This is an acceptable exception to the rule du ring start-up. However , each such input can draw up to 80

mA per input pin per MSC8144E device in the system during start-up. An assertion of the inputs to the high voltage level before

power-up should be with slew rate less than 4V/ns.

The following supplies sh ould rise before any other supplies in any sequence

•V

DD and VDDPLL coupled together

•V

DDM3

After the above supplies rise to 90% of their nominal value the following I/O supplies may rise in any sequence (see Figure 44):

•V

DDGE1

•V

DDGE2

•V

DDIO

•VDDDDR and MVREF coupled one to another. MVREF should be either at same time or after VDDDDR.

•V

DDM3IO

•V

25M3

Note: 1. This recommended power sequencing is different from the MSC8122/MSC8126.

2. If no pins that require VDDGE1 as a reference supply are used (see Table 1), VDDGE1 can be tied to GND.

3. If no pins that require VDDGE2 as a reference supply are used (see Table 1), VDDGE2 can be tied to GND.

4. If the DDR interface is not used, VDDDDR and MVREF can be tied to GND.

5. If the M3 memory is not used, VDDM3, VDDM3IO, and V25M3 can be tied to GND.

6. If the RapidIO interface is not used, VDDSX, VDDSXP, and VDDRIOPLL can be tied to GND.

Figure 44. VDDM3, VDDM3IO and V25M3 Power-on Se quence

VDDM3, VDD, and VDDPLL

90%

I/O supplies

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0

Hardware Design Considerations

Freesca le Sem ico nd uctor66

3.1.2 Start-Up Timing

Section 2.7.1 describes the start-up tim ing.

3.2 Power Supply Design Considerations

3.2.1 PLL Supplies

Each PLL supply must have an external RC filter for the VDDPLL input. The filter is a 10 Ω resistor in series with two 2.2 μF,

low ESL (<0.5 nH) and low ESR capacitors. All three PLLs can connect to a single supply voltage source (such as a voltage

regulator) as long as the external RC filter is applied to each PLL separately (see Figure 45). For optimal noise filtering, place

the circuit as close as possible to its VDDPLL inputs. These traces should be short and direct.

Figure 45. PLL Supplies

3.2.2 Other Supplies

TBD

3.3 Connectivity Guidelines

Note: Although the package actually uses a ball grid array, the more conventional term pin is used to denote signal

connections in this discu ssion.

First, select the pin multiplexing mode to allocate the requ ir ed I/O signals. Then use the guidelines presented in the following

subsections for board des ign and connections. The following conv entions are u sed in d escribing the conn ectivity requirements:

1. GND indicates using a 10 kΩ pull-down resistor (recommended) or a direct connection to the ground plane. Direct

connections to the groun d plane may yield DC current up to 50mA through the I/O supply that adds to overall power

consumption.

MSC8144

VDDPLL0

10 Ω

2.2 μF2.2 μF

VDDPLL0

10 Ω

2.2 μF2.2 μF

VDDPLL0

10 Ω

2.2 μF2.2 μF

Voltage Regulator

Hardware Design Considerations

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0

Freescale Semicond uc tor 67

2. VDD indicates using a 10 kΩ pull-up resistor (recommended) or a direct connection to the appropriate power supply.

Direct connections to the supply may yi eld DC cur rent up to 50mA through the I/O supply that adds to overall power

consumption.

3. Mandatory use of a pull-up or pull-down resistor it is clearly indicated as “pull-up/pull-down”.

4. NC indicates “not connected” and means do not connect anything to the pin.

5. The phrase “in use” indicates a typical pin connection for the required function.

Note: Please see recommendations #1 and #2 as mandatory pull-down or pull-up connection for unused pins in case of

subset interface connection.

3.3.1 DDR Memory Related Pins

This section discusses the various scenarios that can be used with DDR1 and DDR2 memory.

Note: For information about unused differential/non-differential pins in DDR1/DDR2 modes (that is, unused negative lines

of strobes in DDR1), please refer to Table 57.

3.3.1.1 DDR Interface Is Not Used

Table 57. Connectivity of DDR Related Pins When the DDR Interface Is Not Used

Signal Name Pin Connection

MDQ[0–31] NC

MDQS[0–3] NC

MA[0–15] NC

MCK[0–2] NC

MCS[0–1] NC

MDM[0–3] NC

MBA[0–2] NC

MCAS NC

MCKE[0–1] NC

MODT[0–1] NC

MDIC[0–1] NC

MRAS NC

MWE NC

MECC[0–7] NC

ECC_MDM NC

ECC_MDQS NC

MVREF GND

VDDDDR GND

Note: If the DDR controller is not used, disable the internal DDR clock by writing a 1 to the CLK11DIS bit in the System Clock Control

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0

Hardware Design Considerations

Freesca le Sem ico nd uctor68

3.3.1.2 16-Bit DDR Memory Only

Table 58 lists unused pin connection when using 16-bit DDR memory. The 16 most significant data lines are not used.

3.3.1.3 ECC Unused Pin Connections

When the error code corrected mechanism is not used in any 32- or 16-bi t DDR configur atio n, refer to Table 59 to determine

the correct pin connections.

Table 58. Connectivity of DDR Related Pins When Using 16-bit DDR Memory Only

Signal Name Pin connection

MDQ[0–15] in use

MDQ[16–31] pull-up to VDDDDR

MDQS[0–1] in use

MDQS[2–3] pull-down to GND

MDQS[0–1] in use

MDQS[2–3]pull-up to VDDDDR

MA[0–15] in use

MCK[0–2] in use

MCS[0–1]in use

MDM[0–1] in use

MDM[2–3] NC

MBA[0–2] in use

MCAS in use

MCKE[0–1] in use

MODT[0–1] in use

MDIC[0–1] in use

MRAS in use

MWE in use

MVREF 1/2*VDDDDR

VDDDDR 2.5 V or 1.8 V

Table 59. Connectivity of Unused ECC Mechanism Pins

Signal Name Pin connection

MECC[0–7] pull-up to VDDDDR

ECC_MDM NC

ECC_MDQS pull-down to GND

ECC_MDQS pull-up to VDDDDR

Hardware Design Considerations

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0

Freescale Semicond uc tor 69

3.3.2 Serial RapidIO Interface Related Pins

3.3.2.1 Serial RapidIO interface Is Not Used

3.3.2.2 Serial RapidIO Specific Lane Is Not Used

Table 60. Connectivity of Serial RapidIO Interface Related Pins When the RapidIO Interface Is Not Used

Signal Name Pin Connection

SRIO_IMP_CAL_RX GND

SRIO_IMP_CAL_TX GND

SRIO_REF_CLK GND

SRIO_RXD[0–3] GND

SRIO_TXD[0–3] NC

VDDRIOPLL GND

GNDRIOPLL GND

GNDSXP GND

GNDSXC GND

VDDSXP GND

VDDSXC GND

Table 61. Connectivity of Serial RapidIO Related Pins When Specific Lane Is Not Used

Signal Name Pin Connection

SRIO_IMP_CAL_RX in use

SRIO_IMP_CAL_TX in use

SRIO_REF_CLK in use

SRIO_RXDxGNDSXC

SRIO_TXDxNC

VDDRIOPLL in use

GNDRIOPLL in use

GNDSXP GNDSXP

GNDSXC GNDSXC

VDDSXP 1.0 V

VDDSXC 1.0 V

Note: The x indicates the lane number {0,1,2,3} for all unused lanes.

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0

Hardware Design Considerations

Freesca le Sem ico nd uctor70

3.3.3 M3 Memory Related Pins

Table 62. Connectivity of M3 Related Pins When M3 Memory Is Not Used

Signal Name Pin Connection

M3_RESET NC

V25M3 GND

VDDM3 GND

VDDM3IO GND

Hardware Design Considerations

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0

Freescale Semicond uc tor 71

3.3.4 Ethernet Related Pins

3.3.4.1 Ethernet Controller 1 (GE1) Related Pins

Note: Table 63 and Table 64 assume that the alternate function of the specified pin is not used. If the alternate function is

used, connect the pin as required to support that function.

3.3.4.1.1 GE1 Interface Is Not Used

Table 63 assumes that the GE1 signals are not used fo r any purpos e (includin g any multiplexed fu nction s) and that VDDGE1 is

tied to GND.

3.3.4.1.2 Subset of GE1 Pins Required

When only a subset of the whole GE1 interface is used, such as for RMII, the unused GE1 pins shou ld be connected as described

in Table 64. This table assumes that the unused GE1 pins are not used for any purpose (including any multiplexed function) and

that VDDGE1 is tied to either 2.5 V or 3.3 V.

Table 63. Connectivity of GE1 Related Pins When the GE1 Interface Is Not Used

Signal Name Pin Connection

GE1_COL NC

GE1_CRS NC

GE1_RD[0–4] NC

GE1_RX_ER NC

GE1_RX_CLK NC

GE1_RX_DV NC

GE1_SGMII_RX GNDSXC

GE1_SGMII_TX NC

GE1_TD[0–4] NC

GE1_TX_CLK NC

GE1_TX_EN NC

GE1_TX_ER NC

Table 64. Connectivity of GE1 Related Pins When only a subset of the GE1 Interface Is required

Signal Name Pin Connection

GE1_COL GND

GE1_CRS GND

GE1_RD[0–3] GND

GE1_RX_ER GND

GE1_RX_CLK GND

GE1_RX_DV GND

GE1_SGMII_RX GNDSXC

GE1_SGMII_TX NC

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0

Hardware Design Considerations

Freesca le Sem ico nd uctor72

3.3.4.2 Ethernet Controller 2 (GE2) Related Pins

Note: Table 65 and Table 67 assume that the alternate function of the specified pin is not used. If the alternate function is

used, connect the pin as required to support that function.

3.3.4.2.1 GE2 interface Is Not Used

Table 65 assumes that the GE2 pins are not used for any purpose (including any multiplexed function) and that VDDGE2 is tied

to GND.

3.3.4.2.2 Subset of GE2 Pins Required

When only a subset of the whole GE2 interface is used, such as for RMII, the unused GE2 pins shou ld be connected as described

in Table 66. The table assumes that the unused GE2 pins are not used for any p urpose (i ncluding a ny multip lexed func tions)

and that VDDGE2 is tied to either 2.5 V or 3.3 B.

GE1_SGMII_TX NC

GE1_TD[0-3] NC

GE1_TX_CLK GND

GE1_TX_EN NC

GE1_TX_ER NC

Table 65. Connectivity of GE2 Related Pins When the GE2 Interface Is Not Used

Signal Name Pin Connection

GE2_RD[0-3] NC

GE2_RX_CLK NC

GE2_RX_DV NC

GE2_RX_ER NC

GE2_SGMII_RX GNDSXC

GE2_SGMII_TX NC

GE2_TCK Nc

GE2_TD[0–3] Nc

GE2_TX_EN NC

Table 66. Connectivity of GE1 Related Pins When only a subset of the GE1 Interface Is required

Signal Name Pin Connection

GE2_RD[0-3] GND

GE2_RX_CLK GND

GE2_RX_DV GND

GE2_RX_ER GND

GE2_SGMII_RX GNDSXC

Table 64. Connectivity of GE1 Related Pins When only a subset of the GE1 Interface Is required (continued)

Signal Name Pin Connection

Hardware Design Considerations

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0

Freescale Semicond uc tor 73

3.3.4.3 GE1 and GE2 Management Pins

GE_MDC and GE_ MDIO pins should be connected as r equired b y the specified protocol. If neither GE1 nor GE2 is used (that

is, VDDGE2 is connected to GND), Table 67 lists the recommended management pin connections.

3.3.5 UTOPIA Related Pins

Table 68 lists the board connections of the UTOPIA pins when the entire UTOPIA interface is not used or subset of UTOPIA

interface is used. For multiplexing options that select a subset of the UTOPIA interface, use the connections described in

Table 68 for those signals that are not selected. Table 68 assumes that the alternate function of the specified pin is not used. If

the alternate function is used, connect that pin as required to support the selected function.

GE2_SGMII_RX GNDSXC

GE2_SGMII_TX NC

GE2_TCK NC

GE2_TD[0–3] NC

GE2_TX_EN NC

Table 67. Connectivity of GE Management Pins When GE1 and GE2 Are Not Used

Signal Name Pin Connection

GE_MDC NC

GE_MDIO NC

Table 68. Connectivity of UTOPIA Related Pins When UTOPIA Interface Is Not Used

Signal Name Pin Connection

UTP_IR GND

UTP_RADDR[0–4] VDDIO

UTP_RCLAV_PDRPA NC

UTP_RCLK GND

UTP_RD[0–15] GND

UTP_REN VDDIO

UTP_RPRTY GND

UTP_RSOC GND

UTP_TADDR[0–4] VDDIO

UTP_TCLAV NC

UTP_TCLK GND

UTP_TD[0–15] NC

UTP_TEN VDDIO

UTP_TPRTY NC

UTP_TSOC NC

VDDIO 3.3 V

Table 66. Connectivity of GE1 Related Pins When only a subset of the GE1 Interface Is requir ed (continued)

Signal Name Pin Connection

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0

Hardware Design Considerations

Freesca le Sem ico nd uctor74

3.3.6 TDM Interface Related Pins

Table 69 lists the board conn ections of the TDM pins when an entire specific TDM is not used. For multiplexing options that

select a subset of a TDM interface, use the connections described in Table 69 for those signals that are not selected. Table 69

assumes that the alternate f unction of the specifi ed pin is no t used. If the alternate functio n is used, connect that pi n as re quired

to support the selected function.

3.3.7 PCI Related Pins

Table 70 lists the board conn ections of the pins when PCI is not used. Table 70 assumes that the alternate function of the

specified pin is not used. If the alternate function is used, connect that pin as required to support the selected function.

Table 69. Connectivity of TDM Related Pins When TDM Interface Is Not Used

Signal Name Pin Connection

TDMxRCLK GND

TDMxRDAT GND

TDMxRSYN GND

TDMxTCLK GND

TDMTxDAT GND

TDMxTSYN GND

VDDIO 3.3 V

Notes: 1. x = {0, 1, 2,3, 4, 5, 6, 7}

2. In case of subset of TDM interface usage please make sure to disable unused TDM modules. See Chapter 20, TDM, in the

MSC8144E Reference Man ual for details.

Table 70. Connectivity of PCI Related Pins When PCI Is Not Used

Signal Name Pin Connection

PCI_AD[0–31] GND

PCI_CBE[0–3] GND

PCI_CLK_IN GND

PCI_DEVSEL VDDIO

PCI_FRAME VDDIO

PCI_GNT VDDIO

PCI_IDS GND

PCI_IRDY VDDIO

PCI_PAR GND

PCI_PERR VDDIO

PCI_REQ NC

PCI_SERR VDDIO

PCI_STOP VDDIO

PCI_TRDY VDDIO

VDDIO 3.3 V

Hardware Design Considerations

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0

Freescale Semicond uc tor 75

3.3.8 Miscellaneous Pins

Table 71 lists the board conn ections for the pins if they are required by the system design. Table 71 assumes that the alternate

function of the specified pin is not used. If the alternate function is used, connect that pin as required to support the selected

function.

Note: For details on configuration, see the MSC81 44E Reference Manual . For additional information, refer to the MSC8144

Design Checklist (AN3202).

3.4 External DDR SDRAM Selection

TBD

Table 71. Connectivity of Individual Pins When They Are Not Required

Signal Name Pin Connection

CLKOUT NC

EE0 GND

EE1 NC

GPIO[0–31] NC

SCL See the GPIO connectivity guidelines in this table.

SDA See the GPIO connectivity guidelines in this table.

INT_OUT NC

IRQ[0–15] See the GPIO connectivity guidelines in this table.

NMI VDDIO

NMI_OUT NC

RC[0–16] GND

RC_LDF NC

STOP_BS GND

TCK GND

TDI GND

TDO NC

TMR[0–4] See the GPIO connectivity guidelines in this table.

TMS GND

TRST GND

URXD See the GPIO connectivity guidelines in this table.

UTXD See the GPIO connectivity guidelines in this table.

VDDIO 3.3 V

Note: When using I/O multiplexing mode 5 or 6, tie the TDM7TSYN/PCI_AD4 signal (ball number AC9) to GND.

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0

Ordering Information

Freesca le Sem ico nd uctor76

4 Ordering Information

Consult a Freescale Semiconductor sales office or authorized distributor to determine product availability and place an order.

5 Package Information

Part Package Type Spheres Core

Voltage Operating

Temperature

Core

Frequency

(MHz) Order Numbe r

MSC8144E Flip Chip Plastic Ball Grid Array (FC-PBGA) Lead-free 1.0 V –40° to 105°C 800 TBD

0° to 90°C 1000 TBD

Figure 46. MSC8144E Mechanical Information, 783-ball FC-PBGA Package

Notes:

1. All dimensions in millimeters.

2. Dimensioning and tolerancing

per ASME Y14.5M–1994.

3. Maximum solder ball diameter

measured parallel to Datum A.

4. Datum A, the seating plane, is

determined by the spherical

crowns of the solder balls.

5. Parallelism measurement

should exclude any effect of

marking.

6. Capacitors may not be present

on all devices.

7. Caution must be taken not to

short exposed metal capacitor

pads on package top.

CASE NO. 1842-02

Product Documentation

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0

Freescale Semicond uc tor 77

6 Product Documentation

•MSC8144E Technical Data Sheet (MSC8144E). Details the signals, AC/DC characteristics, clock signal

characteristics, package and pinout, and electrical design considerations of the MSC8144E device.

•MSC8144E Reference Manual (MS C8144ERM). Includes func tio nal descriptions of the extended cores and all the

internal subsystems including configuration and pro gram ming information.

•Application Notes. Cover various programming topics related to the StarCore DSP core and the MSC8144E device.

•SC3400 DS P Cor e Refer ence Manual. Covers the SC3400 core architecture, control registers, clock registers, program

control, and in st ru ctio n set .

•MSC8144 SC3400 DSP Core Subsystem Reference Manual. Covers core subsystem architecture, functionality, and

registers.

7 Revision History

Table 72 provides a revision history for this data sheet.

Table 72. Document Revision History

Revision Date Description

0 Feb. 2007 • Initial publi c releas e.

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0

Revision History

Freesca le Sem ico nd uctor78

Revision History

MSC8144E Quad Core Digital Signal Processor Data Sheet, Rev. 0

Freescale Semicond uc tor 79

Document Number: MSC8144E

Rev. 0

6/2007

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