1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
SCLK
FS
SDI
EOC/INT
SDO
DGND
DVDD
CS
A0
A1
A2
A3
CSTART
AVDD
AGND
BGAP
REFM
REFP
AGND
AVDD
A7
A6
A5
A4
TLC3548
DW OR PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
SCLK
FS
SDI
EOC/INT
SDO
DGND
DVDD
CS
A0
A1
CSTART
AVDD
AGND
BGAP
REFM
REFP
AGND
AVDD
A3
A2
TLC3544
DW OR PW PACKAGE
(TOP VIEW)
TLC3544, TLC3548
5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL
ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS
SLAS266C – OCTOBER 2000 – REVISED MAY 2003
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
D14-Bit Resolution
DMaximum Throughput 200 KSPS
DAnalog Input Range 0-V to Reference
Voltage
DMultiple Analog Inputs:
– 8 Channels for TLC3548
– 4 Channels for TLC3544
DPseudodifferential Analog Inputs
DSPI/DSP-Compatible Serial Interfaces With
SCLK up to 25 MHz
DSingle 5-V Analog Supply; 3-/5-V Digital
Supply
DLow Power:
– 4 mA (Internal Reference: 1.8 mA) for
Normal Operation
– 20 µA in Autopower-Down
DBuilt-In 4-V Reference, Conversion Clock
and 8x FIFO
DHardware-Controlled and Programmable
Sampling Period
DProgrammable Autochannel Sweep and
Repeat
DHardware Default Configuration
DINL: ±1 LSB Max
DDNL: ±1 LSB Max
DSINAD: 80.8 dB
DTHD: –95 dB
description
The TLC3544 and TLC3548 are a family of 14-bit resolution high-performance, low-power, CMOS
analog-to-digital converters (ADC). All devices operate from a single 5-V analog power supply and 3-V to 5-V
digital supply. The serial interface consists of four digital inputs [chip select (CS), frame sync (FS), serial
input-output clock (SCLK), serial data input (SDI)], and a 3-state serial data output (SDO). CS (works as SS,
slave select), SDI, SDO, and SCLK form an SPI interface. FS, SDI, SDO, and SCLK form a DSP interface. The
frame sync signal (FS) indicates the start of a serial data frame being transferred. When multiple converters
connect to one serial port of a DSP, CS works as the chip select to allow the host DSP to access the individual
converter . CS can be tied to ground if only one converter is used. FS must be tied to DVDD if it is not used (such
as in an SPI interface). When SDI is tied to DVDD, the device is set in hardware default mode after power-on,
and no software configuration is required. In the simplest case, only three wires (SDO, SCLK, and CS or FS)
are needed to interface with the host.
Copyright 2000 – 2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TLC3544, TLC3548
5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL
ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS
SLAS266C OCTOBER 2000 REVISED MAY 2003
2POST OFFICE BOX 655303 DALLAS, TEXAS 75265
description (continued)
In addition to being a high-speed ADC with versatile control capability, these devices have an on-chip analog
multiplexer (MUX) that can select any analog input or one of three self-test voltages. The sample-and-hold
function is automatically started after the fourth SCLK (normal sampling) or can be controlled by CSTART to
extend the sampling period (extended sampling). The normal sampling period can also be programmed as short
sampling (12 SCLKs) or long sampling (44 SCLKs) to accommodate the faster SCLK operation popular among
high-performance signal processors. The TLC3544 and TLC3548 are designed to operate with low power
consumption. The power saving feature is further enhanced with software power-down/ autopower-down
modes and programmable conversion speeds. The conversion clock (internal OSC) is built in. The converter
can also use an external SCLK as the conversion clock for maximum flexibility. The TLC3544 and TLC3548
have a 4-V internal reference. The converters are specified with unipolar input range of 0-V to 5-V when a 5-V
external reference is used.
AVAILABLE OPTIONS
PACKAGED DEVICES
TA20-TSSOP
(PW) 20-SOIC
(DW) 24-SOIC
(DW) 24-TSSOP
(PW)
0°C to 70°C TLC3544CPW TLC3544CDW TLC3548CDW TLC3548CPW
40°C to 85°C TLC3544IPW TLC3544IDW TLC3548IDW TLC3548IPW
functional block diagram
Analog
MUX
4-V
Reference
Command
Decode
CMR (4 MSBs)
SAR
ADC
OSC
Conversion
Clock
FIFO
X8
Control
Logic
4-Bit
Counter
SDO
EOC/INT
DVDD AVDD
DGND AGND
CSTART
FS
CS
SCLK
SDI CFR
REFM
BGAP
REFP
X8
A0
A1
A2
A3
A4
A5
A6
A7
X4
A0
A1
A2
A3
X
X
X
X
TLC3544, TLC3548
5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL
ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS
SLAS266C OCTOBER 2000 REVISED MAY 2003
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
equivalent input circuit
1.1 k
Max
Ron
MUX
C(sample) = 30 pF Max
VDD
REFM
Ain
Diode Turn on Voltage: 35 V
Equivalent Analog Input Circuit
Equivalent Digital Input Circuit
Digital Input
VDD
Terminal Functions
TERMINAL
NAME
NO. I/O DESCRIPTION
NAME TLC3544 TLC3548
I/O
DESCRIPTION
A0
A1
A2
A3
A0
A1
A2
A3
A4
A5
A6
A7
9
10
11
12
9
10
11
12
13
14
15
16
IAnalog signal inputs. Analog input signals applied to these terminals are internally multiplexed. The
driving source impedance should be less than or equal to 1 k for normal sampling. For larger
source impedance, use the external hardware conversion start signal CSTART (the low time of
CSTART controls the sampling period) or reduce the frequency of SCLK to increase the sampling
time.
AGND 14, 18 18, 22 IAnalog ground return for the internal circuitry. Unless otherwise noted, all analog voltage
measurements are with respect to AGND.
AVDD 13, 19 17, 23 IAnalog supply voltage
BGAP 17 21 I Internal bandgap compensation pin. Install compensation capacitors between BGAP and AGND.
0.1 µF for external reference; 10 µF in parallel with 0.1 µF for internal reference.
CS 8 8 I Chip select. When CS is high, SDO is in high-impedance state, SDI is ignored, and SCLK is
disabled to clock data but works as conversion clock source if programmed. The falling edge of CS
input resets the internal 4-bit counter, enables SDI and SCLK, and removes SDO from
high-impedance state.
If FS is high at CS falling edge, CS falling edge initiates the operation cycle. CS works as slave
select (SS) to provide an SPI interface.
If FS is low at CS falling edge, FS rising edge initiates the operation cycle. CS can be used as chip
select to allow the host to access the individual converter.
CSTART 20 24 I External sampling trigger signal, which initiates the sampling from a selected analog input channel
when the device works in extended sampling mode (asynchronous sampling). A high-to-low
transition starts the sampling of the analog input signal. A low-to-high transition puts the S/H in hold
mode and starts the conversion. The low time of the CSTART signal controls the sampling period.
CSTART signal must be long enough for proper sampling. CSTART must stay high long enough
after the low-to-high transition for the conversion to finish maturely. The activation of CSTART is
independent of SCLK and the level of CS and FS. However, the first CSTART cannot be issued
before the rising edge of the 11th SCLK. T ie this terminal to DVDD if not used.
DGND 6 6 I Digital ground return for the internal circuitry
DVDD 7 7 I Digital supply voltage
TLC3544, TLC3548
5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL
ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS
SLAS266C OCTOBER 2000 REVISED MAY 2003
4POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Terminal Functions (Continued)
TERMINAL
NAME
NO. I/O DESCRIPTION
NAME TLC3544 TLC3548
I/O
DESCRIPTION
EOC(INT) 4 4 O End of conversion (EOC) or interrupt to host processor (INT)
EOC: used in conversion mode 00 only . EOC goes from high to low at the end of the sampling and
remains low until the conversion is complete and data is ready.
INT: Interrupt to the host processor . The falling edge of INT indicates data is ready for output. INT
is cleared by the following CS, FS, or CSTART.
FS 2 2 I Frame sync input from DSP. The rising edge of FS indicates the start of a serial data frame being
transferred (coming into or being sent out of the device). If FS is low at the falling edge of CS, the
rising edge of FS initiates the operation cycle, resets the internal 4-bit counter, and enables SDI,
SDO, and SCLK. T ie this pin to DVDD if FS is not used to initiate the operation cycle.
REFM 16 20 I External low reference input. Connect REFM to AGND.
REFP 15 19 I External positive reference input. When an external reference is used, the range of maximum input
voltage is determined by the difference between the voltage applied to this terminal and to the
REFM terminal. Always install decoupling capacitors (10 µF in parallel with 0.1 µF) between REFP
and REFM.
SCLK 1 1 I Serial clock input from the host processor to clock in the input from SDI and clock out the output
via SDO. It can also be used as the conversion clock source when the external conversion clock
is selected (see Table 2). When CS is low, SCLK is enabled. When CS is high, SCLK is disabled
for the data transfer, but can still work as the conversion clock source.
SDI 3 3 I Serial data input. The first 4 MSBs, ID[15:12], are decoded as one 4-bit command. All trailing bits,
except for the CONFIGURE WRITE command, are filled with zeros. The CONFIGURE WRITE
command requires additional 12-bit data. The MSB of input data, ID[15], is latched at the first falling
edge of SCLK following FS falling edge, if FS starts the operation, or latched at the falling edge of
first SCLK following CS falling edge when CS initiates the operation.
The remaining input data (if any) is shifted in on the rising edge of SCLK and latched on the falling
edge of SCLK. The input via SDI is ignored after the 4-bit counter counts to 16 (clock edges) or a
low-to-high transition of CS, whichever happens first. Refer to the timing specification for the timing
requirements. Tie SDI to DVDD if using hardware default mode (refer to device initialization).
SDO 5 5 O The 3-state serial output for the A/D conversion result. All data bits are shifted out through SDO.
SDO is in the high-impedance state when CS is high. SDO is released after a CS falling edge. The
output format is MSB (OD[15]) first.
When FS initiates the operation, the MSB of output via SDO, OD[15], is valid before the first falling
edge of SCLK following the falling edge of FS.
When CS initiates the operation, the MSB, OD[15], is valid before the first falling edge of SCLK
following the CS falling edge.
The remaining data bits are shifted out on the rising edge of SCLK and are valid before the falling
edge of SCLK. Refer to the timing specification for the details.
In a select/conversion operation, the first 14 bits are the results from the previous conversion (data).
In READ FIFO operation, the data is from FIFO. In both cases, the last two bits are dont care.
In a WRITE operation, the output from SDO is ignored.
SDO goes into high-impedance state at the sixteenth falling edge of SCLK after the operation cycle
is initiated. SDO is in high-impedance state during conversions in modes 01, 10, and 11.
TLC3544, TLC3548
5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL
ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS
SLAS266C OCTOBER 2000 REVISED MAY 2003
5
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature (unless otherwise noted)
Supply voltage, GND to AVDD, DVDD 0.3 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog input voltage range 0.2 V to AVDD +0.2 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog input current 100 mA MAX. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Reference input voltage AVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Digital input voltage range 0.3 V to DVDD + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating virtual junction temperature range, TJ 40°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air industrial temperature range, TA:I suffix 40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
C suffix 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, Tstg 65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1.16 inch) from case for 10 seconds 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
TLC3544, TLC3548
5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL
ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS
SLAS266C OCTOBER 2000 REVISED MAY 2003
6POST OFFICE BOX 655303 DALLAS, TEXAS 75265
general electrical characteristics over recommended operating free-air temperature range,
single-ended input, normal long sampling, 200 KSPS, A VDD = 5 V, external reference (VREFP = 4 V,
VREFM = 0 V) or internal reference, SCLK frequency = 25 MHz, fixed channel at CONV mode 00,
analog input signal source resistance = 25 (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYPMAX UNIT
Digital Input
VIH
High level control in
p
ut voltage
DVDD = 5 V 3.8
V
VIH High-level control input voltage DVDD = 3 V 2.1 V
V
IL
Low-level control input volta
g
eDVDD = 5 V 0.8
V
VIL
Low level
control
in ut
voltage
DVDD = 3 V 0.6 V
IIH High-level input current VI = DVDD 0.005 2.5 µA
IIL Low-level input current VI = DGND 2.5 0.005 µA
Input capacitance 20 25 pF
Digital output
VOH
Hi
g
h-level di
g
ital output,
IO=02mA
DVDD = 5 V 4.2
V
VOH
High level
digital
out ut
,
VOH at 30-pF load IO = 0.2 mA DVDD = 3 V 2.4 V
DVDD =5V
IO = 0.8 mA 0.4
VOL
Low-level di
g
ital output, DVDD = 5 V IO = 50 µA 0.1
V
VOL
Low level
digital
out ut
,
VOL at 30-pF load
DVDD =3V
IO = 0.8 mA 0.4 V
OL
DVDD = 3 V IO = 50 µA 0.1
IOZ
Off-state output current VO = DVDD
CS DV
0.02 1
µA
IOZ
Off state
out ut
current
(high-impedance state) VO = DGND CS = DVDD 10.02 µA
Power Supply
AVDD
Su
pp
ly voltage
4.5 5 5.5 V
DVDD Supply voltage 2.7 5 5.5 V
ICC
Power suppl
AVDD current-
AICC Conversion clock is internal OSC,
EXT reference AVDD =55Vto45V
2.8 3.6
mA
ICC
current DVDD current-
DICC
EXT. reference, AVDD = 5.5 V to 4.5 V,
CS = DGND 1.2 2 mA
ICC(SW)
Sft d l t
For all digital inputs DVDD or
DGND CS =DV
DD
SCLK ON 175 240
µA
ICC(SW) Software
power-down
power
supply
current DGND, CS = DVDD,
AVDD = 5.5 V SCLK OFF 20 µA
ICC(A t d )
Auto
p
ower
-
down
p
ower
su
pp
ly
For all digital inputs DVDD or
DGND AVDD =55V
SCLK ON 175 230
µA
ICC(Autodown)
Autopower
-
down
power
supply
current DGND, AVDD = 5.5 V,
External reference SCLK OFF 20 µA
Operating temperat re
C suffix 0 70
°C
Operating temperature I suffix 40 85 °C
All typical values are at TA = 25°C.
TLC3544, TLC3548
5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL
ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS
SLAS266C OCTOBER 2000 REVISED MAY 2003
7
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
general electrical characteristics over recommended operating free-air temperature range,
single-ended input, normal long sampling, 200 KSPS, A VDD = 5 V, external reference (VREFP = 4 V,
VREFM = 0 V) or internal reference, SCLK frequency = 25 MHz, fixed channel at CONV mode 00,
analog input signal source resistance = 25 (unless otherwise noted) (continued)
PARAMETER TEST CONDITIONS MIN TYPMAX UNIT
Resolution 14 bits
Analog Input
V oltage range 0 Reference V
Leakage current 0.01 0.05 µA
Capacitance 30 pF
Reference
Internal reference voltage 3.85 4 4.07 V
Internal reference temperature
coefficient 100 ppm/°C
Internal reference source current 1.8 2.5 mA
Internal reference startup time 20 ms
VREFP External positive reference voltage 3 5 V
VREFM External negative reference voltage 0 AGND V
No conversion (AVDD = 5 V,
CS = DVDD, SCLK = DGND) 100 M
External reference input impedance Normal long sampling (AVDD = 5 V,
CS = DGND, SCLK = 25 MHz,
External conversion clock) 8.3 12.5 k
External reference current
No conversion (VREFP = AVDD = 5 V,
VREFM = AGND, External reference,
CS = DVDD)1.5 µA
External reference current Normal long sampling (AVDD = 5 V,
CS = DGND, SCLK = 25 MHz external
conversion clock at VREF = 5 V) 0.4 0.6 mA
Throughput Rate
fInternal oscillation frequency DVDD = 2.7 V to 5.5 V 6.5 MHz
Internal OSC, 6.5 MHz minute 2.785
t(conv) Conversion time Conversion clock is external source,
SCLK = 25 MHz (see Note 1) 2.895 µs
Acquisition time Normal short sampling 1.2 µs
Throughput rate (see Note 2) Normal long sampling, fixed channel in mode
00 or 01 200 KSPS
DC AccuracyNormal Long Sampling
ELIntegral linearity error See Note 3 1±0.5 1 LSB
EDDifferential linearity error 1±0.5 1 LSB
EOZero offset error See Note 4 3±0.6 3 LSB
E(g+) Gain error See Note 4 0 5 12 LSB
All typical values are at TA = 25°C.
NOTES: 1. Conversion time t(conv) = (18x4 / SCLK) + 15 ns.
2. This is for a fixed channel in conversion mode 00 or 01. When switching the channels, additional multiplexer setting time is required
to overcome the memory effect of the charge redistribution DAC (refer to Figure 8).
3. Linear error is the maximum deviation from the best fit straight line through the A/D transfer characteristics.
4. Zero offset error is the difference between 0000000000000 and the converted output for zero input voltage; gain error is the
difference between 1 1111111111111 and the converted output for full-scale input voltage. The full-scale input voltage is equal to the
reference voltage being used.
TLC3544, TLC3548
5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL
ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS
SLAS266C OCTOBER 2000 REVISED MAY 2003
8POST OFFICE BOX 655303 DALLAS, TEXAS 75265
general electrical characteristics over recommended operating free-air temperature range,
single-ended input, normal long sampling, 200 KSPS, A VDD = 5 V, external reference (VREFP = 4V,
VREFM = 0 V) or internal reference, SCLK frequency = 25 MHz, fixed channel at CONV mode 00,
analog input signal source resistance = 25 (unless otherwise noted) (continued)
PARAMETER TEST CONDITIONS MIN TYPMAX UNIT
DC AccuracyNormal Short Sampling
ELIntegral linearity error See Note 3 ±0.8 LSB
EDDifferential linearity error ±0.6 LSB
EOZero offset error See Note 4 3±0.6 3 LSB
E(g+) Gain error See Note 4 0 5 12 LSB
AC AccuracyNormal Long Sampling
SINAD
Signal to noise ratio + distortion
fi = 20 kHz 78.6 80.8
dB
SINAD Signal-to-noise ratio + distortion fi = 100 kHz 77.6 dB
THD
Total harmonic distortion
fi = 20 kHz 95 90
dB
THD Total harmonic distortion fi = 100 kHz 88 dB
SFDR
S
p
urious free dynamic range
fi = 20 kHz 90 97
dB
SFDR Spurious free dynamic range fi = 100 kHz 89 dB
ENOB
Effective number of bits
fi = 20 kHz 12.8 13.1
Bits
ENOB Effective number of bits fi = 100 kHz 12.6 Bits
SNR
Signal to noise ratio
fi = 20 kHz 79 81
dB
SNR Signal-to-noise ratio fi = 100 kHz 78 dB
Channel-to-channel isolation (see
Notes 2 and 5) Fixed channel in conversion mode 00, fi = 35 kHz 100 dB
Analog in
p
ut bandwidth
Full power bandwidth, 1 dB 2
MHz
Analog input bandwidth Full power bandwidth, 3 dB 2.5 MHz
AC AccuracyNormal Short Sampling
SINAD
Signal to noise ratio + distortion
fi = 20 kHz 78.9
dB
SINAD Signal-to-noise ratio + distortion fi = 100 kHz 77.6 dB
THD
Total harmonic distortion
fi = 20 kHz 95
dB
THD Total harmonic distortion fi = 100 kHz 88 dB
SNR
Signal to noise ratio
fi = 20 kHz 79
dB
SNR Signal-to-noise ratio fi = 100 kHz 78 dB
ENOB
Effective number of bits
fi = 20 kHz 12.8
Bits
ENOB Effective number of bits fi = 100 kHz 12.6 Bits
SFDR
S
p
urious free dynamic range
fi = 20 kHz 97
dB
SFDR Spurious free dynamic range fi = 100 kHz 89 dB
Channel-to-channel isolation (see
Notes 2 and 5) Fixed channel in conversion mode 00, fi = 35 kHz 100 dB
Analog in
p
ut bandwidth
Full power bandwidth, 1 dB 2
MHz
Analog input bandwidth Full power bandwidth, 3 dB 2.5 MHz
All typical values are at TA = 25°C.
NOTES: 2. This is for a fixed channel in conversion mode 00 or 01. When switching the channels, additional multiplexer setting time is required
to overcome the memory effect of the charge redistribution DAC (refer to Figure 8).
3. Linear error is the maximum deviation from the best fit straight line through the A/D transfer characteristics.
4. Zero offset error is the difference between 0000000000000 and the converted output for zero input voltage; gain error is the
difference between 1 1111111111111 and the converted output for full-scale input voltage. The full-scale input voltage is equal to the
reference voltage being used.
5. It is measured by applying a full-scale of 35 kHz signal to other channels and determining how much the signal is attenuated in the
channel of interest. The converter samples this examined channel continuously . The channel-to-channel isolation is degraded if the
converter samples different channels alternately (refer to Figure 8).
TLC3544, TLC3548
5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL
ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS
SLAS266C OCTOBER 2000 REVISED MAY 2003
9
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range, AVDD = 5 V, DVDD
= 5 V, VREFP = 5 V, VREFM = 0 V, SCLK frequency = 25 MHz (unless otherwise noted)
SCLK, SDI, SDO, EOC and INT
PARAMETERS MIN TYP MAX UNIT
t(1)
Cycle time of SCLK at 25
p
F load
DVDD = 2.7 V 100
ns
tc(1) Cycle time of SCLK at 25-pF load DVDD = 5 V 40ns
tw(1) Pulse width, SCLK high time at 25-pF load 40% 60% tc(1)
t
Rise time for INT EOC at 10 pF load
DVDD = 5 V 6
ns
tr(1) Rise time for INT, EOC at 10-pF load DVDD = 2.7 V 10 ns
t
Fall time for INT EOC at 10 pF load
DVDD = 5 V 6
ns
tf(1) Fall time for INT, EOC at 10-pF load DVDD = 2.7 V 10 ns
tsu(1) Setup time, new SDI valid (reaches 90% final level) before falling edge of SCLK, at 25-pF
load 6ns
th(1) Hold time, old SDI hold (reaches 10% of old data level) after falling edge of SCLK, at
25-pF load 0ns
t
Dela
y
time
,
new SDO valid
(
reaches 90% of final level
)
after SCLK risin
g
DVDD= 5 V 0 10
ns
td(1)
Delay
time
,
new
SDO
valid
(reaches
90%
of
final
level)
after
SCLK
rising
edge, at 10-pF load DVDD = 2.7 V 0 23ns
th(2) Hold time, old SDO hold (reaches 10% of old data level) after SCLK rising edge, at 10-pF
load 0ns
td(2) Delay time, delay from sixteenth SCLK falling edge to EOC falling edge, normal sampling,
at 10-pF load 0 6 ns
td(3) Delay time, delay from the sixteenth falling edge of SCLK to INT falling edge, at 10-pF
load [see the () double dagger note and Note 6] t(conv) t(conv) + 6 µs
The minimum pulse width of SCLK high is 12.5 ns. The minimum pulse width of SCLK low is 12.5 ns.
Specified by design
NOTE 6: For normal short sampling, td(3) is the delay from 16th falling edge of SCLK to INT falling edge.
For normal long sampling, td(3) is the delay from 48th falling edge of SCLK to the falling edge of INT.
Conversion time, t(conv) is equal to 18 × OSC + 15 ns when using internal OSC as conversion clock, or 72 × tc(1) + 15 ns when external
SCLK is conversion clock source.
TLC3544, TLC3548
5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL
ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS
SLAS266C OCTOBER 2000 REVISED MAY 2003
10 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
90%
10%
ID15
OD1 OD0
ID1
Hi-Z
50%
116
OD15
Dont Care ID0
OR
VIH
VIL
tw(1)
tc(1)
tsu(1) th(1)
th(2)
td(1)
td(2) tr(1)
tf(1) td(3)
Hi-Z
Dont Care
tf(1) tr(1)
CS
SCLK
SDI
SDO
EOC
INT
See Note A
See Note B
NOTES: A. For normal long sampling, td(2) is the delay time of EOC low after the falling edge of 48th SCLK.
B. For normal long sampling, td(3) is the delay time of INT low after the falling edge of 48th SCLK.
The dotted line means signal may or may not exist, depending on application. It must be ignored.
Normal sampling mode, CS initiates the conversion, FS must be tied to high. When CS is high, SDO is in Hi-Z; all inputs (FS, SCLK,
SDI) are inactive and are ignored.
Figure 1. Critical Timing for SCLK, SDI, SDO, EOC and INT
TLC3544, TLC3548
5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL
ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS
SLAS266C OCTOBER 2000 REVISED MAY 2003
11
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range, AVDD = 5 V,
DVDD = 5 V, VREFP = 5 V, VREFM = 0 V, SCLK frequency = 25 MHz (unless otherwise noted) (continued)
CS trigger
PARAMETERS MIN TYP MAX UNIT
tsu(2) Setup time, CS falling edge before SCLK rising edge, at 25-pF load 12 ns
td(4) Delay time, delay time from 16th SCLK falling edge to CS rising edge, at 25-pF load 5 ns
tw(2) Pulse width, CS high time at 25-pF load 1 tc(1)
t
Dela
y
time
,
dela
y
from CS fallin
g
ed
g
e to MSB of SDO valid
(
reaches 90% DVDD = 5 V 0 12
ns
td(5)
Delay
time
,
delay
from
CS
falling
edge
to
MSB
of
SDO
valid
(reaches
90%
final level), at 10-pF load DVDD = 2.7 V 0 30ns
td(6) Delay time, delay from CS rising edge to SDO 3-state, at 10-pF load 0 6 ns
td(7)
Delay time delay from CS falling edge to INT rising edge at 10
p
F load
DVDD = 5 V 0 6
ns
td(7) Delay time, delay from CS falling edge to INT rising edge, at 10-pF load DVDD = 2.7 V 0 16ns
Specified by design
For normal short sampling, td(4) is the delay time from 16th SCLK falling edge to CS rising edge.
For normal long sampling, td(4) is the delay time from 48th SCLK falling edge to CS rising edge.
Hi-Z
ID15
OD1 OD0
ID1
116
OD15
Dont Care ID0
OR
tsu(2) td(4) tw(2)
td(7)
td(5)
Hi-Z Hi-Z
Dont Care
VIH
VIL
CS
SCLK
SDI
SDO
EOC
INT
td(6)
Dont Care
OD7OD15
NOTE A: The dotted line means signal may or may not exist, depending on application. It must be ignored.
Normal sampling mode, CS initiates the conversion, FS must be tied to high. When CS is high, SDO is in Hi-Z, all inputs (FS, SCLK,
SDI) are inactive and are ignored. Parts with date code earlier than 13XXXXX have these discrepancies:
(Date code is a 7 digit code next to the TI where the first digit indicates the year and the second digit is the month of production. 13,
in this case, is 2001 and the month of March.)
FS is not ignored even if the device is in microcontroller mode (CS triggered).
FS must be tied to DVDD.
Figure 2. Critical Timing for CS Trigger
TLC3544, TLC3548
5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL
ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS
SLAS266C OCTOBER 2000 REVISED MAY 2003
12 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range, AVDD = 5 V,
DVDD = 5 V, VREFP = 5 V, VREFM = 0 V, SCLK frequency = 25 MHz (unless otherwise noted) (continued)
FS trigger
PARAMETERS MIN TYP MAX UNIT
td(8) Delay time, delay from CS falling edge to FS rising edge, at 25-pF load 0.5 tc(1)
tsu(3) Setup time, FS rising edge before SCLK falling edge, at 25-pF load 0.25×tc(1) 0.5×tc(1)+5 ns
tw(3) Pulse width, FS high at 25-pF load 0.75×tc(1) tc(1) 1.25×tc(1) ns
t
Dela
y
time
,
dela
y
from FS risin
g
ed
g
e to MSB of SDO valid DVDD = 5 V 26
ns
td(9)
Delay
time
,
delay
from
FS
rising
edge
to
MSB
of
SDO
valid
(reaches 90% final level) at 10-pF load DVDD = 2.7 V 30ns
td(10) Delay time, delay from FS rising edge to next FS rising edge at 25-pF load Required
sampling time +
conversion time µs
t
Dela
y
time
,
dela
y
from FS risin
g
ed
g
e to INT risin
g
ed
g
e at DVDD = 5 V 0 6
ns
td(11)
Delay
time
,
delay
from
FS
rising
edge
to
INT
rising
edge
at
10-pF load DVDD = 2.7 V 16ns
Specified by design
ID15
OD1 OD0
ID1
Hi-Z
116
OD15
ID0Dont Care ID15
OD15
OR
td(10)
tw(3)
td(8)
tsu(3)
td(9)
td(11)
Dont Care Dont Care
Dont Care
Hi-Z
VIH
VIL
VOH
VOH
CS
FS
SCLK
SDI
SDO
EOC
INT
NOTE A: The dotted line means signal may or may not exist, depending on application. It must be ignored.
Normal sampling mode, FS initiates the conversion, CS can be tied to low . When CS is high, SDO is in Hi-Z, all inputs (FS, SCLK, SDI)
are inactive and are ignored.
Parts with date code earlier than 13XXXXX have these discrepancies:
(Date code is a 7 digit code next to the TI where the first digit indicates the year and the second digit is the month of production. 13,
in this case, is 2001 and the month of March.)
SDO MSB (OD[15]) comes out from the falling edge of CS instead of FS rising edge in DSP mode (FS triggered).
Figure 3. Critical Timing for FS Trigger
TLC3544, TLC3548
5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL
ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS
SLAS266C OCTOBER 2000 REVISED MAY 2003
13
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
timing requirements over recommended operating free-air temperature range, AVDD = 5 V,
DVDD = 5 V, VREFP = 5 V, VREFM = 0 V, SCLK frequency = 25 MHz (unless otherwise noted) (continued)
CSTART trigger
PARAMETERS MIN TYP MAX UNIT
td(12) Delay time, delay from CSTART rising edge to EOC falling
edge, at 10-pF load 0 15 21 ns
tw(4) Pulse width CSTART low time: tW(L)(CSTART), at 25-pF load t(sample ref)+0.4 Note 7 µs
td(13) Delay time, delay from CSTART rising edge to CSTART falling
edge, at 25-pF load t(conv) +15 Notes 7 and 8 ns
td(14) Delay time, delay from CSTART rising edge to INT falling edge,
at 10-pF load t(conv) +15 Notes 7 and 8 t(conv)+21 ns
td(15) Delay time, delay from CSTART falling edge to INT rising edge,
at 10-pF load 0 6 µs
NOTES: 7. The pulse width of CSTART must be not less than the required sampling time. The delay from CSTART rising edge to following
CSTART falling edge must not be less than the required conversion time. The delay from CST ART rising edge to the INT falling edge
is equal to the conversion time.
8. The maximum rate of SCLK is 25 MHz for normal long sampling and 10 MHz for normal short sampling.
t(conv)
OR
tw(4) td(13)
td(12)
td(14)
td(15)
CSTART
EOC
INT
Extended Sampling
Figure 4. Critical Timing for Extended Sampling (CSTART Trigger)
detailed description
converter
The converters are a successive-approximation ADC utilizing a charge redistribution DAC. Figure 5 shows a
simplified block diagram of the ADC. The sampling capacitor acquires the signal on Ain during the sampling
period. When the conversion process starts, the control logic directs the charge redistribution DAC to add and
subtract fixed amounts of charge from the sampling capacitor to bring the comparator into a balanced condition.
When balanced, the conversion is complete and the ADC output code is generated.
TLC3544, TLC3548
5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL
ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS
SLAS266C OCTOBER 2000 REVISED MAY 2003
14 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
detailed description (continued)
Charge
Redistribution
DAC
Control
Logic
_
+
REFM
Ain ADC Code
Figure 5. Simplified Block Diagram of the Successive-Approximation System
analog input range and internal test voltages
TLC3548 has eight analog inputs (TLC3544 has four) and three test voltages. The inputs are selected by the
analog multiplexer according to the command entered (see Table 1). The input multiplexer is a break-
before-make type to reduce input-to-input noise injection resulting from channel switching.
The TLC3544 and TLC3548 are specified for a unipolar input range of 0-V to 4-V when the internal reference
is selected, and 0-V to 5-V when an external 5-V reference is used.
analog input mode
Two input signal modes can be selected: single-ended input and pseudodifferential input.
_
+
Charge
Redistribution
DAC
Control
Logic
Ain(+)
REFM
ADC Code
S1
Ain()
When sampling, S1 is closed and S2 connects to Ain().
During conversion, S1 is open and S2 connects to REFM.
Figure 6. Simplified Pseudodifferential Input Circuit
Pseudodifferential input refers to the negative input, Ain(); its voltage is limited in magnitude to ±0.2 V . The input
frequency limit of Ain() is the same as the positive input Ain(+). This mode is normally used for ground noise
rejection or dc bias offset.
When pseudodifferential mode is selected, only two analog input channel pairs are available for the TLC3544
and four channel pairs for the TLC3548, because half the inputs are used as the negative input (see Figure 7).
TLC3544, TLC3548
5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL
ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS
SLAS266C OCTOBER 2000 REVISED MAY 2003
15
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
analog input mode (continued)
Analog
MUX SAR
ADC
X8
A0
A1
A2
A3
A4
A5
A6
A7
X4
A0
A1
A2
A3
X
X
X
X
X8
A0(+) Pair A
A1()
A2(+) Pair B
A3()
A4(+) Pair C
A5()
A6(+) Pair D
A7()
X4
A0(+) Pair A
A1()
A2(+) Pair B
A3() Analog
MUX SAR
ADC
Single Ended Pseudodifferential
TLC3548
TLC3544
Figure 7. Pin Assignment of Single-Ended Input vs Pseudodifferential Input
reference voltage
There is a built-in 4-V reference. If the internal reference is used, REFP is internally set to 4-V and REFM is set
to 0-V . The external reference can be applied to the reference-input pins (REFP and REFM) if programmed (see
T able 2). The REFM pin should connect to analog ground. REFP can be 3-V to 5-V . Install decoupling capacitors
(10 µF in parallel with 0.1 µF) between REFP and REFM. Install compensation capacitors (10 µF in parallel with
0.1 µF for internal reference, 0.1 µF only for external reference) between BGAP and AGND.
TLC3544, TLC3548
5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL
ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS
SLAS266C OCTOBER 2000 REVISED MAY 2003
16 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
detailed description (continued)
ideal conversion characteristics
00000000000000
00000000000001
00000000000010
01111111111111
10000000000000
10000000000001
11111111111111
11111111111110
11111111111101
16381
16383
16382
8192
8193
8191
0
1
2
01111111111111
01111111111110
01111111111101
00000000000001
00000000000000
11111111111111
10000000000010
10000000000001
10000000000000
Binary
USB
2s Complement
BTC
1.999878 V 2.000122 V
3.999512 V
Unipolar Analog Input Voltage
Step
Digital Output Code
VREFM = VZS = 0 V
122 µV
488 µV
244 µV
VFS 1 LSB = 3.999756 V
1 LSB = 244 µV
VMS = (VFS + VZS)/2 = 2 V
VREFP = VFS = 4 V
data format
INPUT DATA FORMAT (BINARY) OUTPUT DATA FORMAT READ CONVERSION/FIFO
MSB LSB MSB LSB
ID[15:12] ID[11:0] OD[15:2] OD[1:0]
Command Configuration data field or filled with zeros Conversion result Dont Care
14-BIT
Unipolar Straight Binary Output: (USB)
Zero-scale code = VZS = 0000h, Vcode = VREFM
Mid-scale code = VMS = 2000h, Vcode = VREFP/2
Full-scale code = VFS = 3FFFh, Vcode = VREFT 1 LSB
UnIpolar Input, Binary 2s Complement Output: (BTC)
Zero-scale code = VZS = 2000 h, Vcode = VREFM
Mid-scale code = VMS = 0000h, Vcode = (VREFP VREFM)/2
Full-scale code = VFS = 1FFFh, Vcode = VREFP 1 LSB
TLC3544, TLC3548
5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL
ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS
SLAS266C OCTOBER 2000 REVISED MAY 2003
17
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
detailed description (continued)
operation description
The converter samples the selected analog input signal, then converts the sample into digital output, according
to the selected output format. The converter has four digital input pins (SDI, SCLK, CS, and FS) and one digital
output pin (SDO) to communicate with the host device. SDI is a serial data input pin, SDO is a serial data output
pin, and SCLK is a serial clock from the host device. This clock is used to clock the serial data transfer. It can
also be used as the conversion clock source (see Table 2). CS and FS are used to start the operation. The
converter has a CSTART pin for an external hardware sampling and conversion trigger, and an INT/EOC pin
for interrupt purposes.
device initialization
After power on, the status of EOC/INT is initially high, and the input data register is set to all zeros. The device
must be initialized before starting the conversion. The initialization procedure depends on the working mode.
The first conversion result is ignored after power on.
Hardware Default Mode: Nonprogrammed Mode, Default. After power on, two consecutive active cycles
initiated by CS or FS put the device into hardware default mode if SDI is tied to DVDD. Each of these cycles must
last 16 SCLKs at least. These cycles initialize the converter and load the CFR register with 800h (external
reference, unipolar straight binary output code, normal long sampling, internal OSC, single-ended input,
one-shot conversion mode, and EOC/INT pin as INT). No additional software configuration is required.
Software Programmed Mode: Programmed. When the converter has to be configured, the host must write
A000h into the converter first after power on, then perform the WRITE CFR operation to configure the device.
start of operation cycle
Each operation consists of several actions that the converter takes according to the command from the host.
The operation cycle includes three periods: command period, sampling period, and conversion period. In the
command period, the device decodes the command from the host. In the sampling period, the device samples
the selected analog signal according to the command. In the conversion period, the sample of the analog signal
is converted to digital format. The operation cycle starts from the command period, which is followed by one
or several sampling and conversion periods (depending on the setting) and finishes at the end of the last
conversion period.
The operation cycle is initiated by the falling edge of CS or the rising edge of FS.
CS Initiates The Operation: If FS is high at the falling edge of CS, the falling edge of CS initiates the operation.
When CS is high, SDO is in the high-impedance state, the signals on SDI, and SDO are ignored, and SCLK is
disabled to clock the serial data. The falling edge of CS resets the internal 4-bit counter and enables SDO, SDI,
and SCLK. The MSB of the input data via SDI, ID[15], is latched at the first falling edge of SCLK following the
falling edge of CS. The MSB of output data from SDO, OD[15], is valid before this SCLK falling edge. This mode
works as an SPI interface when CS is used as the slave select (SS). It also can be used as a normal DSP
interface if CS connects to the frame sync output of the host DSP. FS must be tied high in this mode.
FS Initiates The Operation: If FS is low at the falling edge of CS, the rising edge of FS initiates the operation,
resets the internal 4-bit counter , and enables SDI, SDO, and SCLK. The ID[15] is latched at the first falling edge
of SCLK following the falling edge of FS. OD[15] is valid before this falling edge of SCLK. This mode is used
to interface the converter with a serial port of the host DSP. The FS of the device is connected to the frame sync
of the host DSP. When several devices are connected to one DSP serial port, CS is used as chip select to allow
the host DSP to access each device individually. If only one converter is used, CS can be tied low.
After the initiation, the remaining SDI data bits (if any) are shifted in and the remaining bits of SDO (if any) are
shifted out at the rising edge of SCLK. The input data are latched at the falling edge of SCLK, and the output
data are valid before this falling edge of SCLK. After the 4-bit counter reaches 16, the SDO goes to a
high-impedance state. The output data from SDO is the previous conversion result in one shot conversion
mode, or the contents in the top of the FIFO when the FIFO is used (refer to Figure 21).
TLC3544, TLC3548
5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL
ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS
SLAS266C OCTOBER 2000 REVISED MAY 2003
18 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
detailed description (continued)
command period
After the rising edge of FS (FS triggers the operation) or the falling edge of CS (CS triggers the operation), SDI,
SDO, and SCLK are enabled. The first four SCLK clocks form the command period. The four MSBs of input data,
ID[15:12], are shifted in and decoded. These bits represent one of the 4-bit commands from the host, which
defines the required operation (see Table 1, Command Set). The four MSBs of output, OD[15:12], are also
shifted out via SDO during this period.
The commands are SELECT/CONVERSION, WRITE CFR, FIFO READ, SW POWER DOWN, and
HARDWARE DEFAULT mode. The SELECT/CONVERSION command includes SELECT ANALOG INPUT
and SELECT TEST commands. All cause a select/conversion operation. They select the analog signal being
converted, and start the sampling/conversion process after the selection. WRITE CFR causes the configuration
operation, which writes the device configuration information into the CFR register. FIFO READ reads the
contents in the FIFO. SW POWER DOWN puts the device into software power-down mode to save power.
Hardware default mode sets the device into the hardware default mode.
After the command period, the remaining 12 bits of SDI are written into the CFR register to configure the device
if the command is WRITE CFR. Otherwise, these bits are ignored. The configuration is retained in the
autopower-down and software power-down state. If SCLK stops (while CS remains low) after the first eight bits
are entered, the next eight bits can be entered after SCLK resumes. The data on SDI are ignored after the 4-bit
counter counts to 16 (falling edge of SCLK) or the low-to-high transition of CS, whichever happens first.
The remaining 12 bits of output data are shifted out from SDO if the command is SELECT/CONVERSION or
FIFO READ. Otherwise, the data on SDO are ignored. In any case, SDO goes into a high-impedance state after
the 4-bit counter counts to 16 (falling edge of SCLK) or the low-to-high transition of CS, whichever happens first.
Table 1. Command Set (CMR)
SDI Bit D[15:12]
TLC3548 COMMAND
TLC3544 COMMAND
BINARY HEX TLC3548 COMMAND TLC3544 COMMAND
0000b 0h SELECT analog input channel 0 SELECT analog input channel 0
0001b 1h SELECT analog input channel 1 SELECT analog input channel 1
0010b 2h SELECT analog input channel 2 SELECT analog input channel 2
0011b 3h SELECT analog input channel 3 SELECT analog input channel 3
0100b 4h SELECT analog input channel 4 SELECT analog input channel 0
0101b 5h SELECT analog input channel 5 SELECT analog input channel 1
0110b 6h SELECT analog input channel 6 SELECT analog input channel 2
0111b 7h SELECT analog input channel 7 SELECT analog input channel 3
1000b 8h SW POWER DOWN
1001b 9h Reserved (test)
1010b Ah WRITE CFR, the last 12 bits of SDI are written into CFR. This command resets FIFO.
1011b Bh SELECT TEST, voltage = (REFP+REFM)/2 (see Notes 9 and 10)
1100b Ch SELECT TEST, voltage = REFM (see Note 11)
1101b Dh SELECT TEST, voltage = REFP (see Note 12)
1110b Eh FIFO READ, FIFO contents is shown on SDO; OD[15:2] = result, OD[1:0] = xx
1111b Fh Hardware default mode, CFR is loaded with 800h
NOTES: 9. REFP is external reference if external reference is selected, or internal reference if internal reference
is programmed.
10. The output code = mid-scale code + zero offset error + gain error.
11. The output code = zero scale code + zero offset error.
12. The output code = full-scale code + gain error.
TLC3544, TLC3548
5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL
ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS
SLAS266C OCTOBER 2000 REVISED MAY 2003
19
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
detailed description (continued)
Table 2. Configuration Register (CFR) Bit Definition
SDI BIT DEFINITION
D11 Reference select:
0: Internal (4 V) 1: External
D10 Conversion output code format select:
0: USB (unipolar straight binary) 1: Binary 2s complement
D9 Sample period select for normal sampling
0: Long sampling (4X) 44 SCLKs Dont care in extended sampling.
1: Short sampling (1X) 12 SCLKs
D8 Conversion clock source select:
0: Conversion clock = Internal OSC 1: Conversion clock = SCLK/4
D7 Input mode select:
0: Single-ended 1: Pseudodifferential. Pin configuration shown below.
Pin Configuration of TLC3548 Pin Configuration of TLC3544
Pin No. Single-ended Pseudodifferential polarity Pin No. Single-ended Pseudodif ferential polarity
9
10 A0
A1 PLUS
MINUS Pair A 9
10 A0
A1 PLUS
MINUS Pair A
11
12 A2
A3 PLUS
MINUS Pair B 11
12 A2
A3 PLUS
MINUS Pair B
13
14 A4
A5 PLUS
MINUS Pair C
15
16 A6
A7 PLUS
MINUS Pair D
D[6:5] Conversion mode select:
00: One shot mode
01: Repeat mode
10: Sweep mode
11: Repeat sweep mode
D[4:3] Sweep auto sequence select (Note: These bits only take effect in conversion mode 10 and 11.)
[]
TLC3548 TLC3544
Single ended(by ch) Pseudodif ferential (by pair) Single ended (by ch) Pseudodif ferential (by pair)
00: 01234567
01: 02460246
10: 00224466
1 1: 02020202
00: N/A
01: ABCDABCD
10: AABBCCDD
11: ABABABAB
00: 01230123
01: 02020202
10: 00112233
1 1: 00002222
00: N/A
01: ABABABAB
10: N/A
11: AAAABBBB
D2 EOC/INT pin function select:
0: Pin used as INT 1: Pin used as EOC ( for mode 00 only)
D[1:0] FIFO trigger level (sweep sequence length). Dont care in one shot mode.
00: Full (INT generated after FIFO level 7 filled)
01: 3/4 (INT generated after FIFO level 5 filled)
10: 1/2 (INT generated after FIFO level 3 filled)
11: 1/4 (INT generated after FIFO level 1 filled)
sampling period
The sampling period follows the command period. The selected signal is sampled during this time. The device
has three different sampling modes: normal short mode, normal long mode, and extended mode.
Normal Short Sampling Mode: Sampling time is controlled by SCLK. It takes 12 SCLK periods. At the end of
sampling, the converter automatically starts the conversion period. After configuration, normal sampling, except
FIFO READ and WRITE CFR commands, starts automatically after the fourth falling edge of SCLK that follows
the falling edge of CS if CS triggers the operation, or follows the rising edge of FS if FS initiates the operation.
TLC3544, TLC3548
5-V ANALOG, 3-/5-V DIGITAL, 14-BIT, 200-KSPS, 4-/8-CHANNELS SERIAL
ANALOG-TO-DIGITAL CONVERTERS WITH 0-5 V (PSEUDODIFFERENTIAL) INPUTS
SLAS266C OCTOBER 2000 REVISED MAY 2003
20 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
sampling period (continued)
Normal Long Sampling Mode: This mode is the same as normal short sampling, except that it lasts 44 SCLK
periods.
Extended Sampling Mode: The external trigger signal, CSTAR T, triggers sampling and conversion. SCLK is
not used for sampling. SCLK is also not needed for conversion if the internal conversion clock is selected. The
falling edge of CSTART begins the sampling of the selected analog input. The sampling continues while
CSTART is low. The rising edge of CSTART ends the sampling and starts the conversion (with about 15 ns
internal delay). The occurrence of CSTAR T is independent of the SCLK clock, CS, and FS. However, the first
CSTART cannot occur before the rising edge of the 11th SCLK. In other words, the falling edge of the first
CSTART can happen at or after the rising edge of the 11th SCLK, but not before. The device enters the extended
sampling mode at the falling edge of CSTART and exits this mode once CSTART goes to high followed by two
consecutive falling edges of CS or two consecutive rising edges of FS (such as one read data operation followed
by a write CFR). The first CS or FS does not cause conversion. Extended mode is used when a fast SCLK is
not suitable for sampling, or when an extended sampling period is needed to accommodate different input signal
source impedance.
conversion period
The conversion period is the third portion of the operation cycle. It begins after the falling edge of the 16th SCLK
for normal short sampling mode, or after the falling edge of the 48th SCLK for normal long sampling, or on the
rising edge of CSTART (with 15 ns internal delay) for extended sampling mode.
The conversion takes 18 conversion clocks plus 15 ns. The conversion clock source can be an internal oscillator,
OSC, or an external clock, SCLK. The conversion clock i