Single-Phase Energy Measurement IC with
8052 MCU, RTC, and LCD Driver
Data Sheet
ADE5166/ADE5169/ADE5566/ADE5569
Rev. D
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GENERAL FEATURES
Wide supply voltage operation: 2.4 V to 3.7 V
Internal bipolar switch between regulated and battery inputs
Ultralow power operation with power saving modes (PSM)
Full operation: 4.4 mA to 1.6 mA (PLL clock dependent)
Battery mode: 3.3 mA to 400 µA (PLL clock dependent)
Sleep mode
Real-time clock (RTC) mode: 1.7 µA
RTC and LCD mode: 38 µA (LCD charge pump enabled)
Reference: 1.2 V ± 0.1% (10 ppm/°C drift)
64-lead, low profile quad flat, RoHS-compliant package (LQFP)
Operating temperature range: −40°C to +85°C
ENERGY MEASUREMENT FEATURES
Proprietary analog-to-digital converters (ADCs) and digital
signal processing (DSP) provide high accuracy active
(watt), reactive (var), and apparent energy (volt-ampere
(VA)) measurement
<0.1% error on active energy over a dynamic range of
1000 to 1 @ 25°C
<0.5% error on reactive energy over a dynamic range of
1000 to 1 @ 25°C (ADE5169 and ADE5569 only)
<0.5% error on root mean square (rms) measurements
over a dynamic range of 500 to 1 for current (Irms) and
100 to 1 for voltage (Vrms) @ 25°C
Supports IEC 62053-21; IEC 62053-22; IEC 62053-23;
EN 50470-3 Class A, Class B, and Class C; and ANSI C12-16
Differential input with programmable gain amplifiers (PGAs)
supports shunts, current transformers, and di/dt current
sensors (ADE5169 and ADE5569 only)
2 current inputs for antitamper detection in the ADE5166/
ADE5169
High frequency outputs proportional to Irms, active, reactive,
or apparent power (AP)
Table 1. Features Available on Each Part
Part No. Antitamper
Watt,
VA,
Irms, Vrms Var
di/dt
Sensor
Memory
Size
ADE5166 Yes Yes No No 62kB
ADE5169 Yes Yes Yes Yes 32kB or
62kB
ADE5566 No Yes No No 62kB
ADE5569 No Yes Yes Yes 62kB
MICROPROCESSOR FEATURES
8052-based core
Single-cycle 4 MIPS 8052 core
8052-compatible instruction set
32.768 kHz external crystal with on-chip PLL
2 external interrupt sources
External reset pin
Low power battery mode
Wake-up from I/O, temperature change, alarm, and
universal asynchronous receiver/transmitter (UART)
LCD driver operation with automatic scrolling
Temperature measurement
Real-time clock (RTC)
Counter for seconds, minutes, hours, days, months,
and years
Date counter, including leap year compensation
Automatic battery switchover for RTC backup
Operation down to 2.4 V
Ultralow battery supply current: 1.7 µA
Selectable output frequency: 1 Hz to 16 kHz
Embedded digital crystal frequency compensation for
calibration and temperature variation of 2 ppm resolution
Integrated LCD driver
108-segment driver for the ADE5566 and ADE5569
104-segment driver for the ADE5166 and ADE5169
2×, 3×, or 4× multiplexing
4 LCD memory banks for screen scrolling
LCD voltages generated internally or with external resistors
Internal adjustable drive voltages up to 5 V independent
of power supply level
On-chip peripherals
2 independent UART interfaces
SPI or I2C
Watchdog timer
Power supply management with user-selectable levels
Memory: 62 kB flash memory, 2.256 kB RAM
Development tools
Single-pin emulation
IDE-based assembly and C source debugging
ADE5166/ADE5169/ADE5566/ADE5569 Data Sheet
Rev. D | Page 2 of 156
TABLE OF CONTENTS
General Features ............................................................................... 1
Energy Measurement Features ........................................................ 1
Microprocessor Features .................................................................. 1
Revision History ............................................................................... 4
General Description ......................................................................... 5
32 Kb Flash Option ...................................................................... 5
Functional Block Diagrams ............................................................. 5
Specifications ..................................................................................... 7
Energy Metering ........................................................................... 7
Analog Peripherals ....................................................................... 8
Digital Interface ............................................................................ 9
Timing Specifications ................................................................ 11
Absolute Maximum Ratings .......................................................... 16
Thermal Resistance .................................................................... 16
ESD Caution ................................................................................ 16
Pin Configurations and Function Descriptions ......................... 17
Typical Performance Characteristics ........................................... 21
Terminology .................................................................................... 25
Special Function Register (SFR) Mapping .................................. 26
Power Management ........................................................................ 28
Power Management Register Details ....................................... 28
Power Supply Architecture ........................................................ 31
Battery Switchover ...................................................................... 31
Power Supply Management (PSM) Interrupt ......................... 31
Using the Power Supply Features ............................................. 33
Operating Modes ............................................................................ 36
PSM0 (Normal Mode) ............................................................... 36
PSM1 (Battery Mode) ................................................................ 36
PSM2 (Sleep Mode) .................................................................... 36
3.3 V Peripherals and Wake-Up Events ................................... 37
Transitioning Between Operating Modes ............................... 38
Using the Power Management Features .................................. 38
Energy Measurement ..................................................................... 39
Access to Energy Measurement SFRs ...................................... 39
Access to Internal Energy Measurement Registers ................ 39
Energy Measurement Registers ................................................ 42
Energy Measurement Internal Registers Details .................... 43
Interrupt Status/Enable SFRs .................................................... 46
Analog Inputs .............................................................................. 47
Analog-to-Digital Conversion .................................................. 48
Fault Detection (ADE5166/ADE5169 Only) .......................... 52
di/dt Current Sensor and Digital Integrator
(ADE5169/ADE5569 Only) ...................................................... 53
Power Quality Measurements ................................................... 54
Phase Compensation ................................................................. 56
RMS Calculation ........................................................................ 57
Active Power Calculation .......................................................... 59
Active Energy Calculation ........................................................ 62
Reactive Power Calculation (ADE5169/ADE5569 Only) ..... 65
Reactive Energy Calculation (ADE5169/ADE5569 Only) ... 67
Apparent Power Calculation ..................................................... 70
Apparent Energy Calculation ................................................... 70
Ampere-Hour Accumulation ................................................... 72
Energy-to-Frequency Conversion............................................ 73
Energy Register Scaling ............................................................. 73
Energy Measurement Interrupts .............................................. 74
Temperature, Battery, and Supply Voltage Measurements........ 75
Temperature Measurement ....................................................... 77
Battery Measurement ................................................................. 77
External Voltage Measurement ................................................ 78
8052 MCU Core Architecture....................................................... 80
MCU Registers ............................................................................ 80
Basic 8052 Registers ................................................................... 82
Standard 8052 SFRs .................................................................... 84
Memory Overview ..................................................................... 85
Addressing Modes ...................................................................... 86
Instruction Set ............................................................................ 87
Read-Modify-Write Instructions ............................................. 89
Instructions That Affect Flags .................................................. 90
Dual Data Pointers ......................................................................... 92
Interrupt System ............................................................................. 93
Standard 8052 Interrupt Architecture ..................................... 93
Interrupt Architecture ............................................................... 93
Interrupt Registers...................................................................... 93
Interrupt Priority ........................................................................ 94
Interrupt Flags ............................................................................ 95
Interrupt Vectors ........................................................................ 97
Interrupt Latency ........................................................................ 97
Context Saving ............................................................................ 97
Watchdog Timer ............................................................................. 98
Data Sheet ADE5166/ADE5169/ADE5566/ADE5569
Rev. D | Page 3 of 156
Writing to the Watchdog Timer SFR (WDCON, Address
0xC0) ............................................................................................. 99
Watchdog Timer Interrupt......................................................... 99
LCD Driver.................................................................................... 100
LCD Registers ........................................................................... 100
LCD Setup ................................................................................. 103
LCD Timing and Waveforms ................................................. 103
Blink Mode ................................................................................ 104
Scrolling Mode ......................................................................... 104
Display Element Control ......................................................... 104
Voltage Generation .................................................................. 105
LCD External Circuitry ........................................................... 105
LCD Function in PSM2 Mode ............................................... 106
Flash Memory ............................................................................... 107
Flash Memory Overview ......................................................... 107
Flash Memory Organization ................................................... 107
Using the Flash Memory ......................................................... 108
Protecting the Flash Memory ................................................. 111
In-Circuit Programming ......................................................... 113
Flash Memory Organization for the 32 kB Model ............... 114
Timers ............................................................................................ 115
Timer Registers ......................................................................... 115
Timer 0 and Timer 1 ................................................................ 117
Timer 2 ...................................................................................... 118
PLL ................................................................................................. 120
PLL Registers ............................................................................ 120
Real-Time Clock (RTC) .............................................................. 121
Access to RTC SFRs ................................................................. 121
Access to Internal RTC Registers ........................................... 121
RTC SFRs .................................................................................. 122
RTC Registers ........................................................................... 125
RTC Calendar ........................................................................... 126
RTC Interrupts ......................................................................... 127
RTC Crystal Compensation .................................................... 128
UART Serial Interface ................................................................... 129
UART SFRs ................................................................................ 129
UART Operation Modes .......................................................... 132
UART Baud Rate Generation .................................................. 133
UART Additional Features ...................................................... 135
UART2 Serial Interface................................................................. 136
UART2 SFRs .............................................................................. 136
UART2 Operation Modes ........................................................ 138
UART2 Baud Rate Generation ................................................ 138
UART2 Additional Features .................................................... 139
Serial Peripheral Interface (SPI) .................................................. 140
SPI Registers .............................................................................. 140
SPI Pins ....................................................................................... 143
SPI Master Operating Modes .................................................. 144
SPI Interrupt and Status Flags ................................................. 145
I2C-Compatible Interface ............................................................. 146
Serial Clock Generation ........................................................... 146
Slave Addresses .......................................................................... 146
I2C Registers ............................................................................... 146
Read and Write Operations ..................................................... 147
I2C Receive and Transmit FIFOs ............................................. 148
I/O Ports ......................................................................................... 149
Parallel I/O ................................................................................. 149
I/O Registers .............................................................................. 150
Port 0........................................................................................... 153
Port 1........................................................................................... 153
Port 2........................................................................................... 153
Determining the Version of the
ADE5166/ADE5169/ADE5566/ADE5569 ................................ 154
Outline Dimensions ...................................................................... 155
Ordering Guide ......................................................................... 155
ADE5166/ADE5169/ADE5566/ADE5569 Data Sheet
Rev. D | Page 4 of 156
REVISION HISTORY
4/12—Rev. C to Rev. D
Changes to Table 1 ............................................................................. 1
Moved Revision History ................................................................... 4
Added 32 kB Flash Option Section ................................................. 5
Changes to Vrms Measurement Bandwidth Parameter, Table 2 ... 7
Changes to Table 17 ......................................................................... 28
Changes to Figure 39 ....................................................................... 40
Changes to Figure 40 ....................................................................... 41
Changes to RMS Calculation Section, Current Channel RMS
Calculation Section, and Figure 60 ............................................... 57
Changes to Current Channel RMS Offset Compensation
Section, Figure 61, and Figure 62 .................................................. 58
Changes to Figure 63 and Voltage Channel RMS Calculation
Section ............................................................................................... 59
Changes to Figure 74 ....................................................................... 68
Added Flash Memory Organization for the 32 kB Model
Section and Figure 97, Renumbered Sequentially ....................114
Change to Table 127 ......................................................................122
Changes to UART Timer Generated Baud Rates Section ........135
Changes to Table 149.....................................................................137
Removed UART2 TxD2 Signal Modulation Section ................137
Changes to Table 155.....................................................................143
Changes to Table 161.....................................................................150
Changes to Table 167 .................................................................... 151
Changes to Ordering Guide ......................................................... 155
6/10—Rev. B to Rev. C
Changes to Bit 5, Table 161 .......................................................... 148
Changes to Ordering Guide ......................................................... 153
11/09—Rev. A to Rev. B
Deleted RTCCAL Function.......................................... Throughout
Changes to Fault Detection (ADE5166/ADE5169
Only) Section .................................................................................. 51
2/09—Rev. 0 to Rev. A
Added ADE5566/ADE5569 .............................................. Universal
Changes to General Features and Microprocessor Features ........ 1
Change to Figure 29, Figure 30, and Figure 31 .......................... 23
Changes to Figure 46...................................................................... 49
Changes to Figure 59...................................................................... 56
Changes to Figure 61...................................................................... 57
Change to Figure 73 ....................................................................... 67
Changes to Figure 89...................................................................... 95
Changes to Figure 103 ................................................................. 120
Changes to Determining the Version of the
ADE5166/ADE5169/ADE5566/ADE5569 Section .................. 152
Changes to Ordering Guide ........................................................ 153
10/08—Revision 0: Initial Version
Data Sheet ADE5166/ADE5169/ADE5566/ADE5569
Rev. D | Page 5 of 156
GENERAL DESCRIPTION
The ADE5166/ADE5169/ADE5566/ADE55691 integrate the
Analog Devices, Inc., energy (ADE) metering IC analog front
end and fixed function DSP solution with an enhanced 8052 MCU
core, a full RTC, an LCD driver, and all the peripherals to make
an electronic energy meter with an LCD display in a single part.
The ADE measurement core includes active, reactive, and apparent
energy calculations, as well as voltage and current rms measure-
ments. This information is accessible for energy billing by using the
built-in energy scalars. Many power line supervisory features such
as SAG, peak, and zero crossing are included in the energy
measurement DSP to simplify energy meter design.
The microprocessor functionality includes a single-cycle 8052 core,
a full RTC with a power supply backup pin, an SPI or I2C interface,
and two independent UART interfaces. The ready-to-use infor-
mation from the ADE core reduces the requirement for program
memory size, making it easy to integrate complicated design into
62 kB of flash memory.
The ADE5166/ADE5169 include a 104-segment LCD driver and
the ADE5566/ADE5569 include a 108-segment LCD driver, each
with the capability to store up to four LCD screens in memory. This
driver generates voltages capable of driving LCDs up to 5 V.
32 KB FLASH OPTION
A reduced memory version of the ADE5169 is available with
32 kB of flash memory. A description of the flash memory
organization of this model is provided in the Flash Memory
Organization for the 32 kB Model section. All other features
and functionality are identical between the models and no
reference is made in the remainder of this data sheet to the
32 kB model. If using the 32 kB model, 32 kB should therefore
be substituted in any references to 62 kB of flash memory.
1 Patents pending.
FUNCTIONAL BLOCK DIAGRAMS
I
PA
I
N
V
P
V
N
REF
IN/OUT
ENERGY
MEASUREMENT
DSP
OSC
COM0
...
...
COM3
...
CF1
CF2
3V/ 5V LCD
CHARGE P UM P
SINGLE
CYCLE
8052
MCU
ADE5166/ADE5169
V
DCIN
V
BAT
V
DD
V
SWOUT
DGND
AGND
LCDVA
LCDVB
LCDVC
...
FP0
FP15
RTC
SS
SCLK
MISO
MOSI/SDATA
T2
T2EX
T0
T1
LCDVP1
LCDVP2
XTAL2
XTAL1
INT0
INT1
FP16
FP17
FP23
FP22
FP21
FP20
FP19
FP18
FP25
FP24
1.20V
REF
52
53
49
50
I
PB 55
63
54
58
64 61
60 4647 48 45
5
6
FP28
FP27
2
1
7
8
9
10
11
12
13
14
20
35
1
4
15
17
18
16
19
44
14
13
12
57 43 42 39 38 7 6 45 11 43 42 41 40 39 38 37 36 5678 9 1038 39 40 41
PGA2
–
+
PGA1
–
+
PGA1
–
+
ADC
ADC
ADC
TEMP
ADC
VSW
ADC
PROGRAM MEMORY
62kB FLASH
POWER SUPPLY
CONTROL AND
MONITORING
USER RAM
256 BYT E S
USER X RAM
2kB
TEMP
SENSOR
BATTERY
ADC
SPI/I
2
C
SERIAL
INTERFACE
3 × 16-BI T
COUNTER
TIMERS
104-SEGMENT
LCD DRIVER
WATCHDOG
TIMER
PLL
07411-201
LDO
V
INTD
V
INTA
RESET
TxD
UART
SERIAL
PORT
UART2
SERIAL
PORT
UART2
TIMER
RxD
62 56 51
TxD2
44
36
RxD2
38
37
59
DOWNLOADER
DEBUGGER
1-PIN
EMULATOR
LDO
EA
UART
TIMER
POR
P0.7/SS/T1/RxD2
P0.6/SCLK/T0
P0.5/MISO/ZX
P0.4/MOSI/SDATA
P0. 0 ( BCTRL/I NT1/ P 0.0)
P1.0/RxD
P1.1/TxD
P1.2/FP25/ZX
P1.3/T2EX/FP24
P1.6/FP21
P1.7/FP20
P1.4/T2/FP23
P1.5/FP22
P0.1/FP19
P0.2/CF1
P0.3/CF2
P2.0/FP18
P2.1/FP17
P2.2/FP16
P2. 3 ( S DE N/P2. 3/T xD2)
Figure 1. ADE5166/ADE5169 Functional Block Diagram
ADE5166/ADE5169/ADE5566/ADE5569 Data Sheet
Rev. D | Page 6 of 156
IP
IN
VP
VN
REF
IN/OUT
ENERGY
MEASUREMENT
DSP
OSC
COM0
...
...
COM3
...
CF1
CF2
LDO
3V/ 5V LCD
CHARGE P UM P
SINGLE
CYCLE
8052
MCU
ADE5566/ADE5569
FP26
V
DCIN
VBAT
V
DD
V
SWOUT
V
INTD
V
INTA
RESET
DGND
AGND
TxD
UART
SERIAL
PORT
UART2
SERIAL
PORT
UART2
TIMER
LCDVA
LCDVB
LCDVC
...
FP0
FP15
RTC
SS
SCLK
MISO
MOSI/SDATA
RxD
T2
T2EX
T0
T1
LCDVP1
LCDVP2
XTAL2
XTAL1
INT0
INT1
FP16
FP17
FP23
FP22
FP21
FP20
FP19
FP18
FP25
FP24
P0.7/SS/T1/RxD2
P0.6/SCLK/T0
P0.5/MISO/ZX
P0.4/MOSI/SDATA
P0. 0 ( BCTRL/I NT1/ P 0.0)
P1.0/RxD
P1.1/TxD
P1.2/FP25/ZX
P1.3/T2EX/FP24
P1.6/FP21
P1.7/FP20
P1.4/T2/FP23
P1.5/FP22
P2.0/FP18
P2.1/FP17
P2.2/FP16
P2. 3 ( S DE N/P2. 3/T xD2)
P0.1/FP19
P0.2/CF1
P0.3/CF2
1.20V
REF
53
52
55
49
50
63
54
58
64 61
60 62 56 51
TxD2
44
36
RxD2
38
37 46
47 48 45
5
FP28
FP27
2
1
6
7
8
9
10
11
12
13
14
20
35
1
4
15
17
18
16
19
44
14
13
12
57 43 42 39 38 7645 11 43 42 41 40 39 38 37 36 5678910
38 39 40 41
59
PGA2
–
+
PGA1
–
+ADC
ADC
TEMP
ADC
VSW
ADC
PROGRAM MEMORY
62kB FLASH
POWER SUPPLY
CONTROL AND
MONITORING
USER RAM
256 BYT E S
USER X RAM
2kB
TEMP
SENSOR
BATTERY
ADC
SPI/I2C
SERIAL
INTERFACE
3 × 16-BI T
COUNTER
TIMERS
108-SEGMENT
LCD DRIVER
WATCHDOG
TIMER
DOWNLOADER
DEBUGGER
PLL
1-PIN
EMULATOR
LDO
EA
UART
TIMER
POR
07411-001
Figure 2. ADE5566/ADE5569 Functional Block Diagram
Data Sheet ADE5166/ADE5169/ADE5566/ADE5569
Rev. D | Page 7 of 156
SPECIFICATIONS
VDD = 3.3 V ± 5%, AGND = DGND = 0 V, on-chip reference XTALx = 32.768 kHz, TMIN to TMAX = −40°C to +85°C, unless otherwise noted.
ENERGY METERING
Table 2.
Parameter
Min
Max
Unit
Test Conditions/Comments
MEASUREMENT ACCURACY1
Phase Error Between Channels
PF = 0.8 Capacitive ±0.05 Degrees Phase lead: 37°
PF = 0.5 Inductive ±0.05 Degrees Phase lag: 60°
Active Energy Measurement Error2 0.1 % of reading Over a dynamic range of 1000 to 1 at 25°C
AC Power Supply Rejection2 VDD = 3.3 V + 100 mV rms/120 Hz
Output Frequency Variation 0.01 % IPx = VP = ±100 mV rms
DC Power Supply Rejection2 VDD = 3.3 V ± 117 mV dc
Output Frequency Variation
%
Active Energy Measurement Bandwidth1 8 kHz
Reactive Energy Measurement Error2 0.5 % of reading Over a dynamic range of 1000 to 1 at 25°C
Vrms Measurement Error2 0.5 % of reading Over a dynamic range of 100 to 1 at 25°C
Vrms Measurement Bandwidth1 63.7 Hz Fundamental only, mean absolute
measurement
Irms Measurement Error2 0.5 % of reading Over a dynamic range of 500 to 1 at 25°C
Irms Measurement Bandwidth1 3.9 kHz
ANALOG INPUTS
Maximum Signal Levels
±500
mV peak
V
P
− V
N
differential input
ADE5166/ADE5169 ±500 mV peak IPA − IN and IPB − IN differential inputs
ADE5566/ADE5569 ±500 mV peak IP − IN
Input Impedance (DC) 770 kΩ
ADC Offset Error2 ±10 mV PGA1 = PGA2 = 1
mV
PGA1 = 16
Gain Error2
Current Channel ±3 % IPA = IPB = 0.5 V dc or IP = 0.5 V dc
Voltage Channel ±3 % VP − VN = 0.5 V dc
Gain Error Match ±0.2 %
CF1 AND CF2 PULSE OUTPUT
Maximum Output Frequency 21.6 kHz VP − VN = 500 mV peak; IPA − IN = 500 mV for
the ADE5166/ADE5169; IP − IN = 500 mV for
the ADE5566/ADE5569
Duty Cycle 50 % If the CF1 or CF2 frequency > 5.55 Hz
Active High Pulse Width 90 ms If the CF1 or CF2 frequency < 5.55 Hz
FAULT DETECTION3
Fault Detection Threshold
Inactive Input ≠ Active Input 6.25 % of active IPA or IPB active
Input Swap Threshold
Inactive Input > Active Input 6.25 % of active IPA or IPB active
Accuracy Fault Mode Operation
I
PA
Active, I
PB
= AGND
% of reading
Over a dynamic range of 500 to 1
IPB Active, IPA = AGND 0.1 % of reading Over a dynamic range of 500 to 1
Fault Detection Delay 3 Seconds
Swap Delay 3 Seconds
1 These specifications are not production tested but are guaranteed by design and/or characterization data on production release.
2 See the Terminology section for definition.
3 Available only in the ADE5166/ADE5169.
ADE5166/ADE5169/ADE5566/ADE5569 Data Sheet
Rev. D | Page 8 of 156
ANALOG PERIPHERALS
Table 3.
Parameter Min Typ Max Unit Test Conditions/Comments
INTERNAL ADCs (BATTERY, TEMPERATURE, V
DCIN
)
Power Supply Operating Range 2.4 3.7 V Measured on VSWOUT
No Missing Codes1 8 Bits
Conversion Delay2 38 µs
ADC Gain
VDCIN Measurement 15.3 mV/LSB
VBAT Measurement 14.6 mV/LSB
Temperature Measurement 0.83 °C/LSB
ADC Offset
VDCIN Measurement at 3 V 200 LSB
VBAT Measurement at 3.7 V 246 LSB
Temperature Measurement at 25°C 123 LSB
VDCIN Analog Input
Maximum Signal Levels 0 3.3 V
Input Impedance (DC) 1 MΩ
Low VDCIN Detection Threshold 1.09 1.2 1.27 V
POWER-ON RESET (POR)
VDD POR
Detection Threshold 2.5 2.95 V
POR Active Timeout Period 33 ms
VSWOUT POR
Detection Threshold 1.8 2.2 V
POR Active Timeout Period 20 ms
VINTD POR
Detection Threshold 2.0 2.25 V
POR Active Timeout Period 16 ms
VINTA POR
Detection Threshold 2.0 2.25 V
POR Active Timeout Period 120 ms
BATTERY SWITCHOVER
Voltage Operating Range (VSWOUT) 2.4 3.7 V
VDD to VBAT Switching
Switching Threshold (VDD) 2.5 2.95 V
Switching Delay 10 ns When VDD to VBAT switch is activated by VDD
30 ms When VDD to VBAT switch is activated by VDCIN
VBAT to VDD Switching
Switching Threshold (VDD) 2.5 2.95 V
Switching Delay 30 ms Based on VDD > 2.75 V
VSWOUT to VB AT Leakage Current 10 nA VBAT = 0 V, VSWOUT = 3.43 V, TA = 25°C
LCD, CHARGE PUMP ACTIVE
Charge Pump Capacitance Between
LCDVP1 and LCDVP2
100 nF
LCDVA, LCDVB, LCDVC Decoupling Capacitance
470
nF
LCDVA 0 1.9 V
LCDVB 0 3.8 V 1/3 bias mode
LCDVC 0 5.8 V 1/3 bias mode
V1 Segment Line Voltage LCDVA − 0.1 LCDVA V Current on segment line = −2 µA
V2 Segment Line Voltage LCDVB − 0.1 LCDVB V Current on segment line = −2 µA
V3 Segment Line Voltage LCDVC − 0.1 LCDVC V Current on segment line = −2 µA
DC Voltage Across Segment and COMx Pin 50 mV LCDVC − LCDVB, LCDVC − LCDVA, or
LCDVB − LCDVA
Data Sheet ADE5166/ADE5169/ADE5566/ADE5569
Rev. D | Page 9 of 156
Parameter Min Typ Max Unit Test Conditions/Comments
LCD, RESISTOR LADDER ACTIVE
Leakage Current ±20 nA 1/2 and 1/3 bias modes, no load
V1 Segment Line Voltage LCDVA − 0.1 LCDVA V Current on segment line = −2 µA
V2 Segment Line Voltage LCDVB − 0.1 LCDVB V Current on segment line = −2 µA
V3 Segment Line Voltage
LCDVC − 0.1
LCDVC
V
Current on segment line = −2 µA
ON-CHIP REFERENCE Nominal 1.2035 V
Reference Error −2.2 +2.2 mV TA = 25°C, fCORE = 1.024 MHz
Power Supply Rejection 80 dB
Temperature Coefficient1 10 50 ppm/°C fCORE = 1.024 MHz
1 These specifications are not production tested but are guaranteed by design and/or characterization data on production release.
2 Delay between ADC conversion request and interrupt set.
DIGITAL INTERFACE
Table 4.
Parameter Min Typ Max Unit Test Conditions/Comments
LOGIC INPUTS1
All Inputs Except XTAL1, XTAL2, BCTRL,
INT0, INT1, RESET
Input High Voltage, VINH 2.0 V
Input Low Voltage, VINL 0.8 V
BCTRL, INT0, INT1, RESET
Input High Voltage, VINH 1.3 V
Input Low Voltage, VINL 0.8 V
Input Currents
RESET
100
nA
RESET
= V
SWOUT
= 3.3 V
Port 0, Port 1, Port 2 ±100 nA Internal pull-up disabled, input = 0 V or
VSWOUT
−3.75 −8.5 µA Internal pull-up enabled, input = 0 V,
VSWOUT = 3.3 V
Input Capacitance 10 pF All digital inputs
FLASH MEMORY
Endurance2 20,000 Cycles At 25°C
Data Retention3 20 Years TJ = 85°C
CRYSTAL OSCILLATOR4
Crystal Equivalent Series Resistance 30 50 kΩ
Crystal Frequency 32 32.768 33.5 kHz
XTAL1 Input Capacitance 12 pF
XTAL2 Output Capacitance 12 pF
MCU CLOCK RATE (fCORE) 4.096 MHz Crystal = 32.768 kHz and CD bits = 0b000
32 kHz Crystal = 32.768 kHz and CD bits = 0b111
LOGIC OUTPUTS
Output High Voltage, VOH 2.4 V VDD = 3.3 V ± 5%
ISOURCE 80 µA
Output Low Voltage, VOL5 0.4 V VDD = 3.3 V ± 5%
ISINK 2 mA
START-UP TIME6
PSM0 Power-On Time 880 ms VDD at 2.75 V to PSM0 code execution
From Power Saving Mode 1 (PSM1)
PSM1 to PSM0 130 ms VDD at 2.75 V to PSM0 code execution
From Power Saving Mode 2 (PSM2)
PSM2 to PSM1 48 ms Wake-up event to PSM1 code execution
PSM2 to PSM0 186 ms VDD at 2.75 V to PSM0 code execution
ADE5166/ADE5169/ADE5566/ADE5569 Data Sheet
Rev. D | Page 10 of 156
Parameter Min Typ Max Unit Test Conditions/Comments
POWER SUPPLY INPUTS
VDD 3.13 3.3 3.46 V
VBAT 2.4 3.3 3.7 V
INTERNAL POWER SUPPLY SWITCH (VSWOUT)
VBAT to VSWOUT On Resistance 12 Ω VBAT = 2.4 V
VDD to VSWOUT On Resistance 9 Ω VDD = 3.13 V
VBAT to/from VDD Switching Open Time 40 ns
BCTRL State Change and Switch Delay 18 µs
VSWOUT Output Current Drive 6 mA
POWER SUPPLY OUTPUTS
V
INTA
2.3
2.70
V
VINTD 2.3 2.70 V
VINTA Power Supply Rejection 60 dB
VINTD Power Supply Rejection 50 dB
POWER SUPPLY CURRENTS
Current in Normal Mode (PSM0) 4.4 5.3 mA fCORE = 4.096 MHz, LCD and meter active
2.2 mA fCORE = 1.024 MHz, LCD and meter active
1.6 mA fCORE = 32.768 kHz, LCD and meter active
3 3.9 mA fCORE = 4.096 MHz; metering ADC and DSP,
powered down
Current in Battery Mode (PSM1) 3.3 5.05 mA fCORE = 4.096 MHz, LCD active, VB AT = 3.7 V
1 mA fCORE = 1.024 MHz, LCD active
Current in Sleep Mode (PSM2) 38 µA LCD active with charge pump at 3.3 V + RTC,
VBAT = 3.3 V
1.7 µA RTC only, TA = 25°C, VB AT = 3.3 V
1 Specifications guaranteed by design.
2 Endurance is qualified as per JEDEC Standard 22 Method A117 and measured at −40°C, +25°C, +85°C, and +125°C.
3 Retention lifetime equivalent at junction temperature (TJ) = 85°C as per JEDEC Standard 22 Method A117. Retention lifetime derates with junction temperature.
4 Recommended crystal specifications.
5 Test carried out with all the I/Os set to a low output level.
6 Delay between power supply valid and execution of first instruction by 8052 core.
Data Sheet ADE5166/ADE5169/ADE5566/ADE5569
Rev. D | Page 11 of 156
TIMING SPECIFICATIONS
AC inputs during testing were driven at VSWOUT − 0.5 V for Logic 1
and at 0.45 V for Logic 0. Timing measurements were made at VIH
minimum for Logic 1 and at VIL maximum for Logic 0, as shown in
Figure 3.
For timing purposes, a port pin is no longer floating when
a 100 mV change from load voltage occurs. A port pin begins
to float when a 100 mV change from the loaded VOH/VOL level
occurs, as shown in Figure 3.
CLOAD = 80 pF for all outputs, unless otherwise noted. VDD = 2.7 V
to 3.6 V; all specifications TMIN to TMAX, unless otherwise noted.
VSWOUT – 0. 5V
0.45V
0.2VSWOUT + 0. 9V
TEST POINTS
0.2VSWOUT – 0.1V
VLOAD – 0.1V
VLOADVLOAD + 0. 1V
TIMING
REFERENCE
POINTS
VLOAD – 0.1VVLOAD
VLOAD – 0.1V
07411-002
Figure 3. Timing Waveform Characteristics
Table 5. Clock Input (External Clock Driven XTAL1) Parameters
32.768 kHz External Crystal
Parameter Description Min Typ Max Unit
tCK XTAL1 period 30.52 µs
tCKL XTAL1 width low 6.26 µs
tCKH XTAL1 width high 6.26 µs
t
CKR
XTAL1 rise time
9
ns
tCKF XTAL1 fall time 9 ns
1/tCORE Core clock frequency1 1.024 MHz
1 The ADE5166/ADE5169/ADE5566/ADE5569 internal PLL locks onto a multiple (512×) of the 32.768 kHz external crystal frequency to provide a stable 4.096 MHz internal
clock for the system. The core can operate at this frequency or at a binary submultiple defined by the CD bits of the POWCON SFR, Address 0xC5[2:0] (see Table 26).
Table 6. I2C-Compatible Interface Timing Parameters (400 kHz)
Parameter Description Typ Unit
tBUF Bus-free time between stop condition and start condition 1.3 µs
tL SCLK low pulse width 1.36 µs
tH SCLK high pulse width 1.14 µs
tSHD Start condition hold time 251.35 µs
tDSU Data setup time 740 ns
tDHD Data hold time 400 ns
tRSU Setup time for repeated start 12.5 ns
tPSU Stop condition setup time 400 ns
tR Rise time of both SCLK and SDATA 200 ns
tF Fall time of both SCLK and SDATA 300 ns
tSUP1 Pulse width of spike suppressed 50 ns
1 Input filtering on both the SCLK and SDATA suppresses noise spikes of <50 ns.
MSB
tBUF
SDATA (I/O)
SCL K ( I)
STOP
CONDITION START
CONDITION REPEATED
START
LSB ACK MSB
12 TO 7 8 9 1
S(R)
PS
tPSU
tDSU
tSHD
tDHD tDSU tDHD
tSUP
tH
tSUP
tL
tRSU tR
tR
tF
tF
07411-003
Figure 4. I2C-Compatible Interface Timing
ADE5166/ADE5169/ADE5566/ADE5569 Data Sheet
Rev. D | Page 12 of 156
Table 7. SPI Master Mode Timing Parameters (SPICPHA = 1)
Parameter Description Min Typ Max Unit
tSL SCLK low pulse width 2SPIR × tCORE1 ns
tSH SCLK high pulse width 2SPIR × tCORE1 ns
tDAV Data output valid after SCLK edge 3 × tCORE1 ns
tDSU Data input setup time before SCLK edge 0 ns
tDHD Data input hold time after SCLK edge tCORE1 ns
tDF Data output fall time 19 ns
tDR Data output rise time 19 ns
tSR SCLK rise time 19 ns
tSF SCLK fall time 19 ns
1 tCORE depends on the clock divider or the CD bits of the POWCON SFR, Address 0xC5[2:0] (see Table 26); tCORE = 2CD/4.096 MHz.
SCLK
(SPICPOL = 0)
t
DSU
SCLK
(SPICPOL = 1)
MOSI
MISO
MSB LSB
LSB IN
BITS[6:1]
BITS[6:1]
t
DHD
t
DR
t
DAV
t
DF
t
SH
t
SL
t
SR
t
SF
MSB IN
07411-004
Figure 5. SPI Master Mode Timing (SPICPHA = 1)
Data Sheet ADE5166/ADE5169/ADE5566/ADE5569
Rev. D | Page 13 of 156
Table 8. SPI Master Mode Timing Parameters (SPICPHA = 0)
Parameter Description Min Typ Max Unit
tSL SCLK low pulse width 2SPIR × tCORE1 (SPIR + 1) × tCORE1 ns
tSH SCLK high pulse width 2SPIR × tCORE1 (SPIR + 1) × tCORE1 ns
tDAV Data output valid after SCLK edge 3 × tCORE1 ns
tDOSU Data output setup before SCLK edge 75 ns
tDSU Data input setup time before SCLK edge 0 ns
tDHD Data input hold time after SCLK edge tCORE1 ns
tDF Data output fall time 19 ns
tDR Data output rise time 19 ns
tSR SCLK rise time 19 ns
t
SF
SCLK fall time
19
ns
1 tCORE depends on the clock divider or the CD bits of the POWCON SFR, Address 0xC5[2:0] (see Table 26); tCORE = 2CD/4.096 MHz.
SCLK
(SPICPOL = 0)
t
DSU
SCLK
(SPICPOL = 1)
MOSI
MISO
MSB LSB
LSB IN
BITS[6:1]
BITS[6:1]
tDHD
tDR
tDAV
tDF
tDOSU
tSH tSL tSR tSF
MSB IN
07411-005
Figure 6. SPI Master Mode Timing (SPICPHA = 0)
ADE5166/ADE5169/ADE5566/ADE5569 Data Sheet
Rev. D | Page 14 of 156
Table 9. SPI Slave Mode Timing Parameters (SPICPHA = 1)
Parameter Description Min Typ Max Unit
tSS SS to SCLK edge 145 ns
tSL SCLK low pulse width 6 × tCORE1 ns
tSH SCLK high pulse width 6 × tCORE1 ns
tDAV Data output valid after SCLK edge 25 ns
tDSU Data input setup time before SCLK edge 0 ns
tDHD Data input hold time after SCLK edge 2 × tCORE1 + 0.5 µs
tDF Data output fall time 19 ns
tDR Data output rise time 19 ns
tSR SCLK rise time 19 ns
tSF SCLK fall time 19 ns
tSFS SS high after SCLK edge 0 ns
1 tCORE depends on the clock divider or the CD bits of the POWCON SFR, Address 0xC5[2:0] (see Table 26); tCORE = 2CD/4.096 MHz.
MSB
MOSI BITS[6:1]
tDHD
tDSU
MSB IN LSB IN
BITS[6:1] LSB
tDR
tDF
t
DAV
MISO
t
SL
t
SH
t
SR
t
SF
t
SFS
t
SS
SCLK
(SPICPOL = 1)
SCLK
(SPICPOL = 0)
SS
07411-006
Figure 7. SPI Slave Mode Timing (SPICPHA = 1)
Data Sheet ADE5166/ADE5169/ADE5566/ADE5569
Rev. D | Page 15 of 156
Table 10. SPI Slave Mode Timing Parameters (SPICPHA = 0)
Parameter Description Min Typ Max Unit
tSS SS to SCLK edge 145 ns
tSL SCLK low pulse width 6 × tCORE1 ns
tSH SCLK high pulse width 6 × tCORE1 ns
tDAV Data output valid after SCLK edge 25 ns
tDSU Data input setup time before SCLK edge 0 ns
tDHD Data input hold time after SCLK edge 2 × tCORE1+ 0.5 µs
tDF Data output fall time 19 ns
tDR Data output rise time 19 ns
tSR SCLK rise time 19 ns
tSF SCLK fall time 19 ns
tDOSS Data output valid after SS edge 0 ns
tSFS SS high after SCLK edge 0 ns
1 tCORE depends on the clock divider or the CD bits of the POWCON SFR, Address 0xC5[2:0] (see Table 26); tCORE = 2CD/4.096 MHz.
MSB
MOSI BITS[6:1]
t
DHD
t
DSU
LSB IN
BITS[6:1] LSB
t
DR
t
DF
t
DAV
MISO
t
SR
t
SF
t
SFS
t
SS
SCLK
(SPICPOL = 1)
SCLK
(SPICPOL = 0)
SS
t
SH
t
SL
t
DOSS
MSB IN
07411-007
Figure 8. SPI Slave Mode Timing (SPICPHA = 0)
ADE5166/ADE5169/ADE5566/ADE5569 Data Sheet
Rev. D | Page 16 of 156
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 11.
Parameter Rating
VDD to DGND −0.3 V to +3.7 V
VBAT to DGND −0.3 V to +3.7 V
VDCIN to DGND −0.3 V to VSWOUT + 0.3 V
Input LCD Voltage to AGND, LCDVA,
LCDVB, LCDVC1
−0.3 V to VSWOUT + 0.3 V
Analog Input Voltage to AGND, VP, VN,
IP/IPA, IPB, and IN
−2 V to +2 V
Digital Input Voltage to DGND −0.3 V to VSWOUT + 0.3 V
Digital Output Voltage to DGND −0.3 V to VSWOUT + 0.3 V
Operating Temperature Range (Industrial) −40°C to +85°C
Storage Temperature Range −65°C to +150°C
64-Lead LQFP, Power Dissipation
Lead Temperature (Soldering, 30 sec) 300°C
1 When used with external resistor divider.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
θJA is specified for the worst-case condition, that is, a device
soldered in a circuit board for surface-mount packages.
Table 12. Thermal Resistance
Package Type θJA θJC Unit
64-Lead LQFP 60 20.5 °C/W
ESD CAUTION
Data Sheet ADE5166/ADE5169/ADE5566/ADE5569
Rev. D | Page 17 of 156
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
64
VDCIN
63
DGND
62
VINTD
61
VSWOUT
60
VDD
59
VINTA
58
VBAT
57
REFIN/OUT
56
IPB
55
RESET
54
AGND
53
IN
52
IPA
51
EA
50
VN
49
VP
47 XTAL1
46 XTAL2
45 BCTRL/INT1/P0.0
42 P0.3/CF2
43 P0.2/CF1
44 SDEN/P2.3/TxD2
48 INT0
41 P0.4/MOSI/SDATA
40 P0.5/MISO/ZX
39 P0.6/SCLK/T0
37 P1.0/RxD
36 P1.1/TxD
35 FP0
34 FP1
33 FP2
38 P0.7/SS/T1/RxD2
2
COM2/FP28
3
COM1
4
COM0
7
P1.4/T2/FP23
6
P1.3/T2EX/FP24
5
P1.2/FP25/ZX
1
COM3/FP27
8
P1.5/FP22
9
P1.6/FP21
10
P1.7/FP20
12
P2.0/FP18
13
P2.1/FP17
14
P2.2/FP16
15
LCDVC
16
LCDVP2
11
P0.1/FP19
17
LCDVB
18
LCDVA
19
LCDVP1
20
FP15
21
FP14
22
FP13
23
FP12
24
FP11
25
FP10
26
FP9
27
FP8
28
FP7
29
FP6
30
FP5
31
FP4
32
FP3
PIN 1
ADE5166/ADE5169
TOP VIEW
(No t t o Scal e)
07411-010
Figure 9. ADE5166/ADE5169 Pin Configuration
Table 13. Pin Function Descriptions
Pin No. Mnemonic Description
1 COM3/FP27 Common Output 3/LCD Segment Output 27. COM3 is used for the LCD backplane.
2 COM2/FP28 Common Output 2/LCD Segment Output 28. COM2 is used for the LCD backplane.
3 COM1 Common Output 1. COM1 is used for the LCD backplane.
4
COM0
Common Output 0. COM0 is used for the LCD backplane.
5 P1.2/FP25/ZX General-Purpose Digital I/O Port 1.2/LCD Segment Output 25/ZX Output.
6 P1.3/T2EX/FP24 General-Purpose Digital I/O Port 1.3/Timer 2 Control Input/LCD Segment Output 24.
7 P1.4/T2/FP23 General-Purpose Digital I/O Port 1.4/Timer 2 Input/LCD Segment Output 23.
8 P1.5/FP22 General-Purpose Digital I/O Port 1.5/LCD Segment Output 22.
9
P1.6/FP21
General-Purpose Digital I/O Port 1.6/LCD Segment Output 21.
10 P1.7/FP20 General-Purpose Digital I/O Port 1.7/LCD Segment Output 20.
11 P0.1/FP19 General-Purpose Digital I/O Port 0.1/LCD Segment Output 19.
12 P2.0/FP18 General-Purpose Digital I/O Port 2.0/LCD Segment Output 18.
13 P2.1/FP17 General-Purpose Digital I/O Port 2.1/LCD Segment Output 17.
14 P2.2/FP16 General-Purpose Digital I/O Port 2.2/LCD Segment Output 16.
15 LCDVC Output Port for LCD Levels. This pin should be decoupled with a 470 nF capacitor.
16 LCDVP2 Analog Output. A 100 nF capacitor should be connected between this pin and LCDVP1 for the internal LCD
charge pump device.
17, 18 LCDVB, LCDVA Output Ports for LCD Levels. These pins should be decoupled with a 470 nF capacitor.
19 LCDVP1 Analog Output. A 100 nF capacitor should be connected between this pin and LCDVP2 for the internal LCD
charge pump device.
20 to 35 FP15 to FP0 LCD Segment Output 15 to LCD Segment Output 0.
36 P1.1/TxD General-Purpose Digital I/O Port 1.1/Transmitter Data Output (Asynchronous).
37 P1.0/RxD General-Purpose Digital I/O Port 1.0/Receive Data Input (Asynchronous).
38 P0.7/SS/T1/RxD2 General-Purpose Digital I/O Port 0.7/Slave Select When SPI Is in Slave Mode/Timer 1 Input/Receive Data
Input 2 (Asynchronous).
39
P0.6/SCLK/T0
General-Purpose Digital I/O Port 0.6/Clock Output for I
2
C or SPI Port/Timer 0 Input.
40 P0.5/MISO/ZX General-Purpose Digital I/O Port 0.5/Data Input for SPI Port/ZX Output.
41 P0.4/MOSI/SDATA General-Purpose Digital I/O Port 0.4/Data Output for SPI Port/I2C-Compatible Data Line.
ADE5166/ADE5169/ADE5566/ADE5569 Data Sheet
Rev. D | Page 18 of 156
Pin No. Mnemonic Description
42 P0.3/CF2 General-Purpose Digital I/O Port 0.3/Calibration Frequency Logic Output 2. The CF2 logic output gives
instantaneous active, reactive, or apparent power or Irms information.
43 P0.2/CF1 General-Purpose Digital I/O Port 0.2/Calibration Frequency Logic Output 1. The CF1 logic output gives
instantaneous active, reactive, or apparent power or Irms information.
44
SDEN
/P2.3/TxD2
Serial Download Mode Enable/General-Purpose Digital Output Port 2.3/Transmitter Data Output 2
(Asynchronous). This pin is used to enable serial download mode through a resistor when pulled low on
power-up or reset. On reset, this pin momentarily becomes an input, and the status of the pin is sampled.
If there is no pull-down resistor in place, the pin momentarily goes high, and then user code is executed.
If the pin is pulled down on reset, the embedded serial download/debug kernel executes, and this pin remains
low during the internal program execution. After reset, this pin can be used as a digital output port pin (P2.3)
or as Transmitter Data Output 2 (asynchronous).
45 BCTRL/INT1/P0.0 Digital Input for Battery Control/External Interrupt Input 1/General-Purpose Digital I/O Port 0.0. This logic
input connects VDD or VBAT to VSWOUT internally when set to logic high or logic low, respectively. When left
open, the connection between VDD or VBAT and VSWOUT is selected internally.
46 XTAL2 A crystal can be connected across this pin and XTAL1 (see the XTAL1 pin description) to provide a clock
source. The XTAL2 pin can drive one CMOS load when an external clock is supplied at XTAL1 or by the gate
oscillator circuit. An internal 6 pF capacitor is connected to this pin.
47 XTAL1 An external clock can be provided at this logic input. Alternatively, a tuning fork crystal can be connected
across XTAL1 and XTAL2 to provide a clock source. The clock frequency for specified operation is 32.768 kHz.
An internal 6 pF capacitor is connected to this pin.
48 INT0 External Interrupt Input 0.
49, 50
V
P
, V
N
Analog Inputs for Voltage Channel. These inputs are fully differential voltage inputs with a maximum
differential level of ±500 mV for specified operation. This channel also has an internal PGA.
51 EA Input for Emulation. When held high, this input enables the device to fetch code from internal program
memory locations. The ADE5166/ADE5169 do not support external code memory. This pin should not be left
floating.
52, 53 IPA, IN Analog Inputs for Current Channel. These inputs are fully differential voltage inputs with a maximum
differential level of ±500 mV for specified operation. This channel also has an internal PGA.
54 AGND Ground Reference for Analog Circuitry.
55 IPB Analog Input for Second Current Channel. This input is fully differential with a maximum differential level of
±500 mV, referred to IN for specified operation. This channel also has an internal PGA.
56 RESET Reset Input, Active Low.
57
REF
IN/OUT
Access to On-Chip Voltage Reference. The on-chip reference has a nominal value of 1.2 V ± 0.1% and a typical
temperature coefficient of 50 ppm/°C maximum. This pin should be decoupled with a 1 µF capacitor in
parallel with a ceramic 100 nF capacitor.
58 VBAT Power Supply Input from the Battery with a 2.4 V to 3.7 V Range. This pin is connected internally to VDD when
the battery is selected as the power supply.
59 VINTA Access to On-Chip 2.5 V Analog LDO. No external active circuitry should be connected to this pin. This pin
should be decoupled with a 10 µF capacitor in parallel with a ceramic 100 nF capacitor.
60 VDD 3.3 V Power Supply Input from the Regulator. This pin is connected internally to VSWOUT when the regulator is
selected as the power supply. This pin should be decoupled with a 10 µF capacitor in parallel with a ceramic
100 nF capacitor.
61 VSWOUT 3.3 V Power Supply Output. This pin provides the supply voltage for the LDOs and the internal circuitry. This
pin should be decoupled with a 10 µF capacitor in parallel with a ceramic 100 nF capacitor.
62 VINTD Access to On-Chip 2.5 V Digital LDO. No external active circuitry should be connected to this pin. This pin
should be decoupled with a 10 µF capacitor in parallel with a ceramic 100 nF capacitor.
63 DGND Ground Reference for Digital Circuitry.
64 VDCIN Analog Input for DC Voltage Monitoring. The maximum input voltage on this pin is VSWOUT with respect to
AGND. This pin is used to monitor the preregulated dc voltage.
Data Sheet ADE5166/ADE5169/ADE5566/ADE5569
Rev. D | Page 19 of 156
64
VDCIN
63
DGND
62
VINTD
61
VSWOUT
60
VDD
59
VINTA
58
VBAT
57
REFIN/OUT
56 55
RESET
54
AGND
53
IN
52 51
EA
50
VN
49
VP
47 XTAL1
46 XTAL2
45 BCTRL/INT1/P0.0
42 P0.3/CF2
43 P0.2/CF1
44 SDEN/P2.3/TxD2
48 INT0
41 P0.4/MOSI/SDATA
40 P0.5/MISO/ZX
39 P0.6/SCLK/T0
37 P1.0/RxD
36 P1.1/TxD
35 FP0
34 FP1
33 FP2
38 P0.7/SS/T1/RxD2
2
COM2/FP28
3
COM1
4
COM0
7
P1.4/T2/FP23
6
P1.3/T2EX/FP24
5
P1.2/FP25/ZX
1
COM3/FP27
8
P1.5/FP22
9
P1.6/FP21
10
P1.7/FP20
12
P2.0/FP18
13
P2.1/FP17
14
P2.2/FP16
15
LCDVC
16
LCDVP2
11
P0.1/FP19
17
LCDVB
18
LCDVA
19
LCDVP1
20
FP15
21
FP14
22
FP13
23
FP12
24
FP11
25
FP10
26
FP9
27
FP8
28
FP7
29
FP6
30
FP5
31
FP4
32
FP3
PIN 1
ADE5566/ADE5569
TOP VIEW
(No t t o Scal e)
07411-028
IP
FP26
Figure 10. ADE5566/ADE5569 Pin Configuration
Table 14. Pin Function Descriptions
Pin No. Mnemonic Description
1 COM3/FP27 Common Output 3/LCD Segment Output 27. COM3 is used for the LCD backplane.
2 COM2/FP28 Common Output 2/LCD Segment Output 28. COM2 is used for the LCD backplane.
3 COM1 Common Output 1. COM1 is used for the LCD backplane.
4 COM0 Common Output 0. COM0 is used for the LCD backplane.
5
P1.2/FP25/ZX
General-Purpose Digital I/O Port 1.2/LCD Segment Output 25/ZX Output.
6
P1.3/T2EX/FP24
General-Purpose Digital I/O Port 1.3/Timer 2 Control Input/LCD Segment Output 24.
7 P1.4/T2/FP23 General-Purpose Digital I/O Port 1.4/Timer 2 Input/LCD Segment Output 23.
8 P1.5/FP22 General-Purpose Digital I/O Port 1.5/LCD Segment Output 22.
9 P1.6/FP21 General-Purpose Digital I/O Port 1.6/LCD Segment Output 21.
10 P1.7/FP20 General-Purpose Digital I/O Port 1.7/LCD Segment Output 20.
11 P0.1/FP19 General-Purpose Digital I/O Port 0.1/LCD Segment Output 19.
12 P2.0/FP18 General-Purpose Digital I/O Port 2.0/LCD Segment Output 18.
13 P2.1/FP17 General-Purpose Digital I/O Port 2.1/LCD Segment Output 17.
14 P2.2/FP16 General-Purpose Digital I/O Port 2.2/LCD Segment Output 16.
15 LCDVC Output Port for LCD Levels. This pin should be decoupled with a 470 nF capacitor.
16 LCDVP2 Analog Output. A 100 nF capacitor should be connected between this pin and LCDVP1 for the internal LCD
charge pump device.
17, 18 LCDVB, LCDVA Output Ports for LCD Levels. These pins should be decoupled with a 470 nF capacitor.
19 LCDVP1 Analog Output. A 100 nF capacitor should be connected between this pin and LCDVP2 for the internal LCD
charge pump device.
20 to 35 FP15 to FP0 LCD Segment Output 15 to LCD Segment Output 0.
36 P1.1/TxD General-Purpose Digital I/O Port 1.1/Transmitter Data Output (Asynchronous).
37
P1.0/RxD
General-Purpose Digital I/O Port 1.0/Receive Data Input (Asynchronous).
38 P0.7/SS/T1/RxD2 General-Purpose Digital I/O Port 0.7/Slave Select When SPI Is in Slave Mode/Timer 1 Input/Receive Data
Input 2 (Asynchronous).
39 P0.6/SCLK/T0 General-Purpose Digital I/O Port 0.6/Clock Output for I2C or SPI Port/Timer 0 Input.
40 P0.5/MISO/ZX General-Purpose Digital I/O Port 0.5/Data Input for SPI Port/ZX Output.
41 P0.4/MOSI/SDATA General-Purpose Digital I/O Port 0.4/Data Output for SPI Port/I2C-Compatible Data Line.
42 P0.3/CF2 General-Purpose Digital I/O Port 0.3/Calibration Frequency Logic Output 2. The CF2 logic output gives
instantaneous active, reactive, or apparent power or Irms information.