Enpirion® Power Datasheet
EN2392Q I 9A Pow er SoC
Voltage M ode Synchr onous Buck
With Integrated Inductor
Not Recom m ended for New Desi gns
Description
The EN2392QI is a Power System on a Chip
(PowerS oC) DC-DC converter. I t integrates M OSFET
switches, small-signal control circuits, compensation
and an integrated inductor in an advanced
11x10x3mm QFN module. It offers high efficiency,
excellent line and load regulation over temperature.
The EN2392QI operates over a wide input voltage
range and is specifically designed to m eet the precise
voltage and fast transient requirements of high-
performance products. The EN2392QI features
frequency synchro niz ation to an ex ternal clock, powe r
OK output voltage monitor, programmable soft-start
along with thermal and over current protection. T he
device’s advanced circui t design, ultra high switching
frequency and proprietary integrated inductor
technology delivers high-quality, ultra compact, non-
isolated DC-DC conver sion.
The Altera Enpirion solution significantly helps in
system design and productivity by offering greatly
simplified board design, layout and manufacturing
requirements. In addition, overall system level
reliability is improved given the small number of
components required with the Altera Enpirion
solution.
All Altera Enpirion products are RoHS compliant,
halogen free and are compatible with lead-free
manufacturing environments.
Features
• I ntegrated Inductor, M OS FE TS, Contro ller
• Total S olution Size Esti m ate: 235mm2
• Wide I nput V oltage Range: 4.5V – 13.2V
• 1% Initial Output Voltage Accuracy
• M aster/S lave Parallel Operatio n (up to 4 devices)
• Frequency Synchro niz ation (Ex terna l Clock)
• Output E nable P in and P ower OK Signal
• Program m able S oft-Start Tim e
• Pin Com patible w ith EN2390QI
• Under V oltage Lockout P rotection (UVLO)
• Over Current and Short Circuit Protection
• Pre-Bias Startup Protection
• Thermal Soft-Shutdown Protection
• RoHS Com pli ant, M SL Level 3, 260oC Reflow
Applications
• Space Constrained Applications
• Distributed Power Architectures
• Output Voltage Ripple Sensitive Applications
• Beat Frequency Sensitive Applications
• Servers, Em bedded Com puting S ystem s,
LAN/SAN Adapter Cards, RAI D Storage Systems,
Industrial Automation, Test and M easurement,
and Telecommunications
Figure 1. S i m pl i fied A ppl i cat i on Circuit
Figure 2. Hi ghes t E ffi ci enc y i n S m al l est Solution
Size
V
OUT
V
IN
2x
22µF
1206
VOUT
ENABLE
AGND
PVIN
AVIN
PGND PGND
47nF
VFB
R
A
R
B
R
CA
C
A
RCLX
AVINO
PG
BTMP
EN2392QI
SS
VDDB
BGND
FQADJ
4.75k
0.22µF
47nF
R
FS
EN_PB M/S
EAIN R
EA
1µF 1µF
OFF
ON
R
CLX
680pF
SW
4.7Ω C
OUT
Optional
C
BULK
0
10
20
30
40
50
60
70
80
90
100
0123456789
EFFICIENCY (%)
OUTPUT CURRENT (A)
Efficiency vs. Output Current
VOUT = 3.3V
VOUT = 2.5V
VOUT = 1.8V
VOUT = 1.2V
VOUT = 1.0V
CONDITIONS
V
IN
= 12.0V
AVIN = 3.3V
Dual Supply
10107 June 2, 2015 Rev C
EN2392QI
Ordering Information
Part Num be r
Package Markings
TAMBIENT Ratin g (° C)
Package Description
EN2392QI
EN2392QI
-40 to +85
76-pin (11mm x 10mm x 3mm) QFN T&R
EVB-EN2392QI
EN2392QI
QF N E valuati on B oard
Packi ng and Marki ng I nform a tion: www.altera.com/support/reliability/packing/rel-packing-and-marking.html
Pin Assignments (Top View)
Figure 3: P i n O ut Di agram (Top View)
NOTE A: NC pins are not to be electrically connect ed to each other or to any external signal, ground, or voltage. A ll pins
including NC pins must be soldered to the PCB. Failure to follow this guideline may res ult in part malf unction or damage.
NOTE B: Shaded area highlights exposed metal below the package that is not to be mechanically or electrically
connected to t he PCB. Refer to F i gure 16 for det ai l s.
NOT E C : White ‘ dot ’ on top left i s pin 1 i ndi cat or on top of the devi ce package.
NC 1
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
2
3
4
5
6
7
8
9KEEP OUT
KEEP OUT
KEEP OUT
NC 15
NC
NC
NC
16
17
18
77
PGND
10
11
12
13
14
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
VOUT
NC
NC(SW)
NC(SW)
PGND
PGND
PGND
PGND
PGND
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
NC
NC
PGND
PVIN
PVIN
PVIN
PVIN
PVIN
PVIN
PVIN
AVINO
PG
BGND
VDDB
S_IN
BTMP
S_OUT
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39 PVIN
PVIN
PVIN
PVIN
NC(SW)
NC(SW)
FQADJ
NC
RCLX
SS
EAIN
VFB
M/S
AGND
AVIN
ENABLE
POK
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
EN_PB
NC(SW)
57
NC
NC
NC
NC
NC
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10107 June 2, 2015 Rev C
EN2392QI
Pin Description
I/O Legend: P=Power G=Ground NC=No C onnect I=Input O=Output I/O=Input/Output
PIN
NAME
I/O
FUNCTION
1-19, 29,
30, 67, 72-
76 NC NC
NO CONNECT – These pins may be internally connected. Do not connect them to each other or to
any other electric al s ignal. Failur e to follow this guideline may res ult in device damage.
20-28 VOUT O
Regulated c onverter output. Connec t thes e pins to the load and plac e output c apacitor between
thes e pins and PGND pins 33-35.
31, 32, 69-
71 NC(SW) NC
Swi tching node – Thes e pins are internally connected to the c ommon s witc hing node of the internal
MOSFETs. In applic ations where the total output capacitance exc eeds 50% of the maximum allow ed,
a “snubber” ci rcuit consi sting of a series 4.7Ω resistor and a 680pF c apacitor s hould be c onnected
from the NC(SW) pin to the PGND. See Output Capacitor Selection for details.
33-38 PGND G
Input/output power ground. Connec t thes e pins to the ground electrode of the input and output f ilter
capac itors . See V OUT and PV IN pin descriptions f or mor e details .
39-49 PVIN P
Input pow er supply. Connect to input pow er supply. Decouple w ith input capacitor to PGND pins 36-
38.
50 AVINO O
Internal 3.4V linear regulator output. Connect this pin to AVIN for applications w here operation from
a single i nput voltage (PVIN) is required. If AVINO is being used, place a 1µF, X5R, capacitor
between A V INO and A GND as c los e as pos sible to AV INO.
51
PG
I/O
PMOS gate. Place a 47nF, X5R, capacitor between this pin and BTMP.
52
BTMP
I/O
Bottom plate ground. See pin 51 des cription.
53 VDDB O
Inter nal r egulated v oltage us ed f or the internal c ontrol circuitry. Place a 0.22µF, X5R, capacitor
between this pin and BGND.
54
BGND
G
Ground for VDDB. Do not connect BGND to any other ground. See pin 53 des cription.
55 S_IN I
Digital synchronization input. This pin accepts either an input clock to phas e loc k the internal
sw itching frequency or a S_OUT si gnal from another EN2392QI. Leave this pin f loating if not us ed.
56
S_OUT
O
Digital synchronization output. PWM s ignal is output on this pin. Leav e this pin f loating if not us ed.
57 POK O
Power OK is an open drain transistor ( pulled up to A V IN or similar v oltage) us ed f or pow er system
state indic ation. POK is logic high when V OUT is w ithin -10% to +20% of V OUT nominal. Leav e this
pin f loating if not us ed.
58 ENABLE I
Output enable. A pply ing a logic high to this pin enables the output and initiates a s of t-start. Applying
a logic low disables the output. ENA BLE logic cannot be higher than A VIN (ref er to A bsolute
Max imum Ratings). Do not leave f loating. See Pow er Up/Down Sequenc ing s ection f or details .
59
AVIN
P
3.3V I nput pow er supply for the controller. Place a 1µF, X5R, c apacitor between A V IN and A GND
60 AGND G
A nalog gr ound. This is the ground return for the controller . A ll A GND pins need to be c onnected to a
quiet ground.
61 M/S
A logi c l evel low c onf igures the dev ic e as Master and a logic lev el high conf igures the dev ic e as a
Slav e. Connect to ground in s tandalone mode.
62 VFB I/O
External feedback input. The feedback loop is closed through this pin. A voltage divider at VOUT is
used to set the output voltage. The mid-point of the divider is c onnected to V FB. A phas e lead
networ k f rom this pin to V OUT is also required to stabilize the loop.
63 EAIN I
Optional error ampl ifi er input. Allows for customizati on of the control loop for performance
optimization. Leave this pin f loating if not us ed.
64 SS I/O
Soft-start node. The soft-s tart c apacitor is c onnected between this pin and A GND. The v alue of this
capac itor determines the star tup time. See Sof t-Start Oper ation in the Functional Description section
for details.
65 RCLX I/O
Over-current protection setting. Placement of a resistor on this pin will adjust the over-current
protec tion thres hold. See Table 2 for the rec ommended RCLX V alue to s et OCP at the nominal
value spec if ied in the Electrical Charac teristics table. Do not leave this pin floating.
66 FQADJ I/O
A dding a r esis tor (R
FS
) to this pin will adjus t the switching f r equency of the EN2392QI. See Table 1
for s uggested r esistor v alues on RFS for various PVIN/VOUT combi nations to maximize efficiency. Do
not leave this pin f loating.
68 EN_PB I
Enable pre-bias protec tion. Connec t EN_PB direc tly to A V IN to enable the Pr e-Bias Protection
feature. Pull EN_PB directl y to ground to disabl e the feature. Do not leave this pin floating. See Pre-
Bias Operation for details.
77 PGND G
Not a perimeter pin. Dev ic e thermal pad to be c onnected to the s ys tem GND plane f or heat-sinking
purposes.
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10107 June 2, 2015 Rev C
EN2392QI
Absolute Maximum Ratings
CAUTION: Absolute M axi mum ratings are stress rati ngs only. F unc ti onal operation beyond t he recom m ended operat i ng
conditions is not implied. S t ress beyond t he absol ut e m axi m um rat i ngs m ay i m pai r devi c e l i fe. Exposure t o absolute
m axi m um rated c ondi tions for ext ended peri ods m ay affect devi ce reli abi l i t y.
PARAMETER
SYMBOL
MIN
MAX
UNITS
Pin Voltages – PVI N, VOU T, PG
-0.5
15
V
Pin Voltages – ENABLE, S_IN, M/S, POK, EN_PB
-0.5
AV
IN
+ 0.3
V
Pin Voltages – AVI NO, AVIN , ENABLE, S_ IN , S_ O U T, M/S
-0.5
6.0
V
Pin Voltages – VFB, SS, EAIN , R C L X, FQ AD J , VD DB , BTMP
-0.5
2.75
V
Dual Supply PVIN R ising and Falling Sl ew R ate (N ote 1)
25
V/ms
Single Supply PVI N Risi ng and Falling Sle w Rate (Note 1, 2 )
10
V/ms
Storage T emperature Range
T
STG
-65
150
°C
Maximum Operating Junc tion T emperatu re
T
J-ABS Max
150
°C
Ref low T emp, 10 Sec, MSL3 JEDEC J -STD-020A
260
°C
ESD Rating (based on Human Body Model)
2000
V
Recommended Operating Conditions
PARAMETER
SYMBOL
MIN
MAX
UNITS
I nput Voltage Range
PVIN
4.5
13.2
V
AVIN: Controller Supply Volt age
AVIN
2.5
5.5
V
Output Voltage Range (Note 3)
V
OUT
0.75
3.3
V
Output Curr ent
I
OUT
0
9
A
Operating Ambient T emperature
T
A
-40
+85
°C
Operating Junction T emperature
T
J
-40
+125
°C
Thermal Characteristics
PARAMETER
SYMBOL
TYP
UNITS
T hermal Resistance: Junction to A mbient (0 LFM) (Note 4)
θ
JA
15
°C/W
T hermal Resistance: Junction to Cas e (0 LFM)
θ
JC
1.5
°C/W
T hermal Shutdown
T
SD
150
°C
T hermal Shutdown H ysteresi s
T
SDH
35
°C
Note 1: PVIN rising and falling slew rates cannot be outside of specification. PVIN should rise monotonically into
regulation. Filter PVIN w ith proper input bulk c apacitance s o that the input AC ripple in regulation is less than ±1V of t he
regulation vol tage. S ee Input Capaci tor S el ecti on for det ai l s.
Note 2: For ac curat e power up s equencing, use a fast ENA B LE l ogi c (> 3V /100µs) after bot h A VIN and P V IN are hi gh.
Tying ENA B LE to A VIN may res ul t in a st artup delay due to a sl ow E NA B LE logi c.
No te 3: Dropout : M axim um VOUT ≤ VIN - 2.5V
Note 4: Based on 2oz. exter nal copper layers and proper thermal design in line with EIJ /JEDEC JESD51-7 st andard for
high therm al conducti vi ty boards.
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10107 June 2, 2015 Rev C
EN2392QI
Electrical Characteristics
NOTE: VIN=12V, Minim um and Maximum values are over operat i ng am bi ent t em perat ure range unl ess otherwi se not ed.
Typical val ues are at TA = 25° C.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
Operating Input
Voltage PVIN 4.5 13.2 V
Controller Input
Voltage AVIN 3 5.5 V
AVIN U nder Voltage
Lock-out rising AVINUVLOR
Voltage above which UVLO is not
asserted 2.5 2.75 3 V
AVIN U nder Voltage
Lock-out f alling AVINOVLOF
Voltage below which UVLO is
asserted 2.1 2.35 2.6 V
AVIN pin I nput Curr ent
I
AVIN
11
mA
I nternal Linear
Regulator Output
Voltage AVINO 3.4 V
Shut-Dow n Supply
Current
IPVIN
S
PVIN =1 2V, AVI N =3 .4V, ENABLE=0V
2
mA
IAVIN
S
PVIN =1 2V, AVI N =3 .4V, ENABLE=0V
300
µA
Feedback Pin Volt age VFB
Feedback node voltage at:
VIN = 12V, ILOAD = 0, T A = 25°C Only 0.594 0.60 0.606 V
Feedback Pin Volt age VFB
Feedback node voltage at:
4.5V ≤ VIN ≤ 13.2V
0A ≤ ILOAD ≤ 9A, TA = -40 to 85°C
0.588 0.60 0.612 V
Feedback pin Input
Leakage Current IFB
VFB pin input leakage current
(Note 5) -5 5 nA
V
OUT
R ise Time
t
RISE
C
SS
= 47nF (Note 5, Note 6, Note 7)
1.96
2.8
3.64
ms
Soft Start Capacitor
Range CSS_RANGE 10 47 68 nF
Output Capacitance
Range COUT
V
IN
= 12V
VOUT = 3.3V; RFS = 22kΩ
See T able 3 f or other output voltages
(Note 5)
80 200 800 µF
V
IN
= 12V
VOUT ≤ 1.0V; RFS = 3.01kΩ
See T able 3 f or other output voltages
(Note 5)
80 200 2200 µF
Continuous Output
Current IOUT_MAX_CONT Subject to thermal de-rating 0 9 A
Over Current T rip
Level IOCP VI N = 12V 9.2 12
Short Circuit Average
I nput Curr ent IIN_OCP Short = 10mΩ (Note 8) 100 mA
ENABLE Logic High
V
ENABLE_HIGH
4.5V ≤ V
IN
≤ 13.2V; (Note 2)
1.25
AV
IN
V
ENABLE Logic Low
V
ENABLE_LOW
4.5V ≤ V
IN
≤ 13.2V;
0
0.95
V
EN ABL E H ys te r e s i s
EN
HYS
200
mV
ENABLE Lockout
Time TENLOCKOUT 8 ms
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10107 June 2, 2015 Rev C
EN2392QI
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
ENABLE pin Input
Current IENABLE
AVIN = 5.5V
EN ABL E = 1 .8 V ;
EN ABL E = 3 .3 V ;
EN ABL E = 5 .5 V ;
5
11
23
8
18
32
µA
Switching Frequency
F
SW
R
FS
= 3.01kΩ
1.0
MHz
External SYNC Clock
Frequency Lock
Range FPLL_LOCK Range of SYNC clock f requency ( See
Tabl e 1) 0.9 1.8 MHz
S_IN T hreshold – Low
V
S_IN_LO
S_IN Clock Logic Low Level (Note 5)
0.8
V
S_IN T hreshold – High
V
S_IN_HI
S_IN Clock Logic High Level (Note 5)
1.8
2.5
V
S_OUT T hreshold –
Low VS_OUT_LO
S_OUT Clock Logic Low Level
(Note 5) 0.8 V
S_OUT T hreshold –
High VS_OUT_HI
S_OUT Clock Logic High Level
(Note 5) 1.8 2.5 V
POK Lower T hreshold POKLT
Percentage of Nominal Output
Voltage for POK to be Low 90 %
POK Output low
Voltage VPOKL With 4mA Curr ent Sink into POK 0.4 V
POK Output Hi
Voltage VPOKH PVIN Range: 4.5V ≤ VIN ≤ 13.2V AVIN V
POK pin V
OH
leakage
current IPOKL POK High (Note 5) 1 µA
M/S Pin Logic Low
V
T-LOW
T ie Pin to GND
0.8
V
M/S Pin Logic High VT-HIGH
Pull up to AVI N T hrough an External
Resistor REXT 1.8 V
M/S Pin Input Current IM/S REXT = 15kΩ;
AVIN = 3 .4 V;
AVIN = 5 .5 V;
65
175 µA
No te 5: P aram et er not produc ti on tes ted but i s guarant eed by desi gn.
No te 6: Rise t i m e calculation begi ns when AVIN > V UVLO and E NABLE = HIGH.
No te 7: VOUT Rise Ti m e A ccurac y does not i nclude soft-s tart capaci tor tolerance.
No te 8: Output short circuit condition was performed with load impedance that is greater than or equal to 10mΩ.
www.altera.com/enpirion Page 6
10107 June 2, 2015 Rev C
EN2392QI
Typical Performance Curves
0
10
20
30
40
50
60
70
80
90
100
0123456 7 8 9
EFFICIENCY (%)
OUTPUT CURRENT (A)
Efficiency vs. Output Current
VOUT = 3.3V
VOUT = 2.5V
VOUT = 1.8V
VOUT = 1.2V
VOUT = 1.0V
CONDITIONS
V
IN = 12.0V
Single Supply
0
10
20
30
40
50
60
70
80
90
100
0 1 2 3 45678 9
EFFICIENCY (%)
OUTPUT CURRENT (A)
Efficiency vs. Output Current
VOUT = 3.3V
VOUT = 2.5V
VOUT = 1.8V
VOUT = 1.2V
VOUT = 1.0V
CONDITIONS
V
IN
= 12.0V
AVIN = 3.3V
Dual Supply
2
3
4
5
6
7
8
9
10
25 30 35 40 45 50 55 60 65 70 75 80 85
MAXIMUM OUTP UT CURRENT (A)
AMBIENT TEMPER ATURE (°C)
Output Current De-rating
VOUT = 1.0V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
CONDITIONS
V
IN
= 12V
T
JMAX
= 125°C
θ
JA
= 15°C/W
11x10x3mm QFN
No Air Flow
2
3
4
5
6
7
8
9
10
25 30 35 40 45 50 55 60 65 70 75 80 85
MAXIMUM OUTP UT CURRENT (A)
AMBIENT TEMPER ATURE (°C)
Output Current De-rating
with A ir Flow (200fpm)
VOUT = 1.0V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
CONDITIONS
V
IN
= 12V
T
JMAX
= 125°C
θ
JA
= 12.5°C/W
11x10x3mm QFN
Air Flow (200fpm)
2
3
4
5
6
7
8
9
10
25 30 35 40 45 50 55 60 65 70 75 80 85
MAXIMUM OUTP UT CURRENT (A)
AMBIENT TEMPER ATURE (°C)
Output Current De-rating
with A ir Flow (400fpm)
VOUT = 1.0V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
CONDITIONS
V
IN
= 12V
T
JMAX
= 125°C
θ
JA
= 11°C/W
11x10x3mm QFN
Air Flow (400fpm)
2
3
4
5
6
7
8
9
10
25 30 35 40 45 50 55 60 65 70 75 80 85
MAXIMUM OUTP UT CURRENT (A)
AMBIENT TEMPER ATURE (°C)
Output Current De-rating
with Heat Sink
VOUT = 1.0V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
CONDITIONS
V
IN
= 12V
T
JMAX
= 125°C
θ
JA
= 14°C/W
11x10x3mm QFN
Heat Sink -Wakefield
Thermal Solutions
P/N 651-B
www.altera.com/enpirion Page 7
10107 June 2, 2015 Rev C
EN2392QI
Typical Performance Curves
2
3
4
5
6
7
8
9
10
25 30 35 40 45 50 55 60 65 70 75 80 85
MAXIMUM OUTP UT CURRENT (A)
AMBIENT TEMPER ATURE (°C)
Output Current De-rating
w/ Heat Sink and Air Flow (200fpm)
VOUT = 1.0V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
CONDITIONS
V
IN
= 12V
T
JMAX
= 125°C
θ
JA
= 11.5°C/W
11x10x3mm QFN
Air Flow (200fpm)
Heat Sink -Wakefield
Thermal Solutions
P/N 651-B
2
3
4
5
6
7
8
9
10
25 30 35 40 45 50 55 60 65 70 75 80 85
MAXIMUM OUTP UT CURRENT (A)
AMBIENT TEMPER ATURE (°C)
Output Current De-rating
w/ Heat Sink and Air Flow (400fpm)
VOUT = 1.0V
VOUT = 1.2V
VOUT = 1.8V
VOUT = 2.5V
VOUT = 3.3V
CONDITIONS
V
IN
= 12V
T
JMAX
= 125°C
θ
JA
= 10°C/W
11x10x3mm QFN
Air Flow (400fpm)
Heat Sink -Wakefield
Thermal Solutions
P/N 651-B
0.995
0.996
0.997
0.998
0.999
1.000
1.001
1.002
1.003
1.004
1.005
0123456789
O UTPUT VO LTAGE (V)
O UTPUT CURRENT (A)
Output Voltage vs. Output Current
VIN = 8V
VIN = 10V
VIN = 12V
CONDITIONS
V
OUT_NOM
= 1. 0V
1.195
1.196
1.197
1.198
1.199
1.200
1.201
1.202
1.203
1.204
1.205
0 1 2 3 4 5 6 7 8 9
O UTPUT VO LTAGE (V)
O UTPUT CURRENT (A)
Output Voltage vs. Output Current
VIN = 8V
VIN = 10V
VIN = 12V
CONDITIONS
V
OUT_NOM
= 1. 2V
1.795
1.796
1.797
1.798
1.799
1.800
1.801
1.802
1.803
1.804
1.805
0123456789
O UTPUT VO LTAGE ( V)
O UTPUT CURRENT (A)
Output Voltage vs. Output Current
VIN = 8V
VIN = 10V
VIN = 12V
CONDITIONS
V
OUT_NOM
= 1. 8V
2.495
2.496
2.497
2.498
2.499
2.500
2.501
2.502
2.503
2.504
2.505
0 1 2 3 4 5 6 7 8 9
O UTPUT VO LTAGE ( V)
O UTPUT CURRENT (A)
Output Voltage vs. Output Current
VIN = 8V
VIN = 10V
VIN = 12V
CONDITIONS
V
OUT_NOM
= 2. 5V
www.altera.com/enpirion Page 8
10107 June 2, 2015 Rev C
EN2392QI
Typical Performance Curves
1.196
1.197
1.198
1.199
1.200
1.201
1.202
1.203
1.204
-40 -15 10 35 60 85
O UTPUT VO LTAGE ( V)
AM BIENT TEMPERAT URE ( C)
Output Voltage vs. Tempe rature
LOAD = 0A
LOAD = 2A
LOAD = 4A
LOAD = 6A
LOAD = 9A
CONDITIONS
V
IN
= 14V
V
OUT_NOM
= 1. 2V
1.196
1.197
1.198
1.199
1.200
1.201
1.202
1.203
1.204
-40 -15 10 35 60 85
O UTPUT VO LTAGE ( V)
AM BIENT TEMPERAT URE ( C)
Output Voltage vs. Tempe rature
LOAD = 0A
LOAD = 2A
LOAD = 4A
LOAD = 6A
LOAD = 9A
CONDITIONS
V
IN
= 12V
V
OUT_NOM
= 1. 2V
1.196
1.197
1.198
1.199
1.200
1.201
1.202
1.203
1.204
-40 -15 10 35 60 85
O UTPUT VO LTAGE ( V)
AM BIENT TEMPERAT URE ( C)
Output Voltage vs. Tempe rature
LOAD = 0A
LOAD = 1A
LOAD = 2A
LOAD = 3A
LOAD = 4A
CONDITIONS
V
IN
= 10V
V
OUT_NOM
= 1. 2V
1.196
1.197
1.198
1.199
1.200
1.201
1.202
1.203
1.204
-40 -15 10 35 60 85
O UTPUT VO LTAGE ( V)
AM BIENT TEMPERAT URE ( C)
Output Voltage vs. Tempe rature
LOAD = 0A
LOAD = 1A
LOAD = 2A
LOAD = 3A
LOAD = 4A
CONDITIONS
V
IN
= 8V
V
OUT_NOM
= 1. 2V
0
1
2
3
4
5
6
7
8
9
10
2 4 6 8 10 12 14 16
INDIVIDUAL OUT PUT CURRENT (A)
TOTAL OUTPUT CURRENT (A)
Par allel C ur ren t Shar e Br eakdown
MASTER
SLAVE
IDEAL
CONDITIONS
EN2390QI
V
IN
= 12V
V
OUT
= 1. 2V
www.altera.com/enpirion Page 9
10107 June 2, 2015 Rev C
EN2392QI
Typical Performance Characteristics
ENABLE
Enable Startup/Shutdown Waveform (0A)
CONDITIONS
VIN = 12V, VOUT = 1 .8 V, Load = 0A, Css = 47nF
CIN = 2x22µF(1206) , CO U T = 2x47µF(1206)+ 100µF( 1206)
VOUT
POK
LOAD
ENABLE
Enable Startup/Shutdown Waveform (3A)
CONDITIONS
VIN = 12V, VOUT = 1 .8 V, Load = 3A, Css = 47nF
CIN = 2x22µF(1206) , CO U T = 2x47µF(1206)+ 100µF( 1206)
VOUT
POK
LOAD
ENABLE
Enable Startup/Shutdown Waveform (6A)
CONDITIONS
VIN = 12V, VOUT = 1 .8 V, Load = 6A, Css = 47nF
CIN = 2x22µF(1206) , CO U T = 2x47µF(1206)+ 100µF( 1206)
VOUT
POK
LOAD
ENABLE
Enable Startup/Shutdown Waveform (9A)
CONDITIONS
VIN = 12V, VOUT = 1 .8 V, Load = 9A, Css = 47nF
CIN = 2x22µF(1206) , CO U T = 2x47µF(1206)+ 100µF( 1206)
VOUT
POK
LOAD
PVIN
Power Up Waveform (0A)
VOUT
POK
LOAD
CONDITIONS
VIN = 12V, VOUT = 1 .8 V, Load = 9A, Css = 47nF
CIN = 2x22µF(1206) , CO U T = 2x47µF(1206)+ 100µF( 1206)
PVIN
Power Up Waveform (4.5A)
VOUT
POK
LOAD
CONDITIONS
VIN = 12V, VOUT = 1 .8 V, Load = 4.5A, Css = 47nF
CIN = 2x22µF(1206) , CO U T = 2x47µF(1206)+ 100µF( 1206)
www.altera.com/enpirion Page 10
10107 June 2, 2015 Rev C
EN2392QI
Typical Performance Characteristics
PVIN
Power Up Waveform (6A)
VOUT
POK
LOAD
CONDITIONS
VIN = 12V, VOUT = 1 .8 V, Load = 6A, Css = 47nF
CIN = 2x22µF(1206) , CO U T = 2x47µF(1206)+ 100µF( 1206)
PVIN
Power Up Waveform (9A)
VOUT
POK
LOAD
CONDITIONS
VIN = 12V, VOUT = 1 .8 V, Load = 9A, Css = 47nF
CIN = 2x22µF(1206) , CO U T = 2x47µF(1206)+ 100µF( 1206)
VOUT = 1V
(AC Coupled)
Output Ripple at 20MHz Bandw idth
CONDITIONS
VIN = 12V, CIN = 2x22µF ( 1206) , COUT = 2x47µF + 100µF (1206)
VOUT = 1.8V
(AC Coupled)
VOUT = 3.3V
(AC Coupled)
LOAD = 0A
20mV / DIV
VOUT = 1V
(AC Coupled)
Output Ripple at 20MHz Bandw idth
CONDITIONS
VIN = 12V, CIN = 2x22µF ( 1206) , COUT = 2x47µF + 100µF (1206)
VOUT = 1.8V
(AC Coupled)
VOUT = 3.3V
(AC Coupled)
LOAD = 9A
20mV / DIV
VOUT = 1V
(AC Coupled)
Output Ripple at 500M Hz Bandwidth
CONDITIONS
VIN = 12V, CIN = 2x22µF ( 1206) , COUT = 2x47µF + 100µF (1206)
VOUT = 1.8V
(AC Coupled)
VOUT = 3.3V
(AC Coupled)
LOAD = 0A
20mV / DIV
VOUT = 1V
(AC Coupled)
Output Ripple at 500M Hz Bandwidth
CONDITIONS
VIN = 12V, CIN = 2x22µF ( 1206) , COUT = 2x47µF + 100µF (1206)
VOUT = 1.8V
(AC Coupled)
VOUT = 3.3V
(AC Coupled)
LOAD = 9A
20mV / DIV
www.altera.com/enpirion Page 11
10107 June 2, 2015 Rev C
EN2392QI
Typical Performance Characteristics
VOUT
(A C C ouple d)
Load Transient f rom 0 to 3 A (V
OUT
=1V)
CONDITIONS
VIN = 12V, VOUT = 1.0V
CIN = 2x22µF (1206)
CO UT = 2 x 47µF (1206) + 100µF (1206)
Using Best Performance Configuration
LOAD
VOUT
(A C C ouple d)
Load Transient from 0 to 4.5A (V
OUT
=1V)
CONDITIONS
VIN = 12V, VOUT = 1.0V
CIN = 2x22µF (1206)
CO UT = 2 x 47µF (1206) + 100µF (1206)
Using Best Performance Configuration
LOAD
VOUT
(A C C ouple d)
Load Transient f rom 0 to 6 A (V
OUT
=1V)
CONDITIONS
VIN = 12V, VOUT = 1.0V
CIN = 2x22µF (1206)
CO UT = 2 x 47µF (1206) + 100µF (1206)
Using Best Performance Configuration
LOAD
VOUT
(A C C ouple d)
Load Transient f rom 0 to 9 A (V
OUT
=1V)
CONDITIONS
VIN = 12V, VOUT = 1.0V
CIN = 2x22µF (1206)
CO UT = 2 x 47µF (1206) + 100µF (1206)
Using Best Performance Configuration
LOAD
VOUT
(A C C ouple d)
Load Transient f rom 0 to 3 A (V
OUT
=3.3V)
CONDITIONS
VIN = 12V, VOUT = 3.3V
CIN = 2x22µF (1206)
CO UT = 2 x 47µF (1206) + 100µF (1206)
Using Best Performance Configuration
LOAD
VOUT
(A C C ouple d)
Load Tr ansient from 0 to 4.5A (V
OUT
=3.3V)
CONDITIONS
VIN = 12V, VOUT = 3.3V
CIN = 2x22µF (1206)
CO UT = 2 x 47µF (1206) + 100µF ( 1206)
Using Best Performance Configur ation
LOAD
www.altera.com/enpirion Page 12
10107 June 2, 2015 Rev C
EN2392QI
Typical Performance Characteristics
VOUT
(A C C ouple d)
Load Transient f rom 0 to 6 A (V
OUT
=3.3V)
CONDITIONS
VIN = 12V, VOUT = 3.3V
CIN = 2x22µF (1206)
CO UT = 2 x 47µF (1206) + 100µF (1206)
Using Best Performance Configuration
LOAD
VOUT
(A C C ouple d)
Load Transient f rom 0 to 9 A (V
OUT
=3.3V)
CONDITIONS
VIN = 12V, VOUT = 3.3V
CIN = 2x22µF (1206)
CO UT = 2 x 47µF (1206) + 100µF (1206)
Using Best Performance Configuration
LOAD
PVIN = 12V
Pre-Bias Startup Waveform
VOUT
ENABLE
Max Pre-Bias
<100% of Nominal
CONDITIONS
VIN = 12V (Single Supply Only)
VOUT = 1.0V, Load = 0A, Css = 47nF
CIN = 2x22µF(1206), COUT = 2x47µF(1206)+100µF(1206)
PVIN = 12V
Pre-Bias Shutdown W aveform
VOUT
ENABLE
CONDITIONS
VIN = 12V (Single Supply Only)
VOUT = 1.0V, Load = 0A, Css = 47nF
CIN = 2x22µF(1206), COUT = 2x47µF(1206)+100µF(1206)
VOUT is held low
for another ~6ms
www.altera.com/enpirion Page 13
10107 June 2, 2015 Rev C
EN2392QI
Functional Block Diagram
Soft Start
Power
Good
Logic
Band Gap
Reference
Voltage Reference Generator
Compensation
Network
Thermal Limit
UVLO
Current Limit Gate Drive
PLL/Sawtooth
Generator
FQADJ
ENABLE
SS
AGND
POK
AVIN
VFB
PGND
VOUT
NC(SW)
PVIN
S_IN
Error
Amp
PWM
Comp
(+)
(-)
(-)
(+)
Digital I/O
S_OUT
To PLL
EN2392QI
Linear
Regulator AVINO
300k
180k
M/S
Compensation
Network
EAIN
PG
BTMP
BGND
VDDB
7.5k
EN_PB
Fi gure 4: F unct i onal B l ock Diagram
Functional Description
Synchr onous Buck Conver t e r
The EN2392QI is a highly integrated synchronous,
buck converter with integrated controller, power
MOSFET switches and integrated inductor. The
nom inal input voltage (PV I N) range is 4.5V to 13.2V
and can support up to 9A of continuous output
current. The output voltage is programmed using
an external resistor divider network. The control
loop utiliz es a Type IV Voltage-Mode compensation
network and maximizes on a low-noise PWM
topology. Much of the compensation circuitry is
internal to the device. However, a phase lead
capacitor is required along with the output voltage
feedback resistor divider to complete the Type IV
compensation network.. The high switching
frequency of the EN2392QI enables the use of
sm all size input and output filter capacitors, as well
as a wide loop bandwidth within a small foot print.
Protection Features:
The power supply has the following protection
features:
• Over Current and Short Circuit Protection
• Thermal Soft-Shutdown with Hysteresis
• AVIN Under-Vol tage Lockout Prote ction
• Pre-B ias P rotection
Additional Features:
• Sw itching Frequency S ynchr onization.
• Program m able S oft-Start
• Pow er OK Output M onitoring
www.altera.com/enpirion Page 14
10107 June 2, 2015 Rev C
EN2392QI
Modes of Operation
The EN2392QI is designed to be powered by either
a single input supply (PVIN) or two separate
supplies: one for PVIN and the other for AVIN. T he
EN2392QI is not “hot pluggable.” Refer to the PVIN
Slew Rate specification on page 4.
Single Input Supply Application (PVIN Only):
Fi gure 5: Singl e Input S uppl y S chem at i c
In single input supply mode, the EN2392QI only
requires one input voltage rail (typically 12V). The
EN2392QI has an internal linear regulator that
converts PVIN to 3.3V. The output of the linear
regulator is provided on the AVINO pin once the
device is enabled. AVINO should be connected to
AVIN . Also, in this single supply application, pla ce a
resistor (RVB) between VDDB and AVIN, as shown
in Figure 5. Altera recommends RVB=4.75kΩ.
Dual Input Supply Application (PVIN and AVIN) :
Fi gure 6: Dual Input Supply S chem atic
In dual input supply mode, two input voltage rails
are required (typically 12V for PVIN and 3.3V for
AVIN). Refer to Figure 6 for the recommended
schematic for a dual input supply application.
Since AVINO is not used, it can be left open.
ENABLE O per ati on
The ENABLE pin provides a means to enable
normal operation or to shut down the device. A
logic high will enable the converter into normal
operation. When the E N A BLE pin i s asserted (high )
the device will under go a nor mal soft-start. A lo g ic
lo w will disable the converter. A logic low will power
down the device in a controlled manner and the
device is subsequently shut down. The ENABLE
signal has to be low for at least the ENABLE
Lockout Tim e (8m s) in order for the device to be re-
enabled. To ensure accurate startup sequencing
the E N A BLE/DIS AB LE si gnal should be faster than
3V/100µs. A slower ENABLE/DISABLE signal may
result in a delayed startup and shutdow n response.
Do not leave ENABLE floating.
Pre-Bias Operation
The EN2392QI has a Pre-Bias feature which will
allow the regulator to startup into a pre-charged
output. The pre-biased output voltage must be
below the nominal regulation voltage; otherwise,
damage may occur during startup and shutdown.
To use this feature, the EN2392QI must be
configured to Single Supply mode, set to
standalone operation (no parallel operation) and
follow the instructions below:
• The EN_PB pin must be pulled high to AVIN
• A resistor divider must be connected from
PVIN to ENABLE to Ground (10k on top,
2.26k on the bottom) to ensure proper
shutdown. The resistor divider will disable
the device when PVIN falls below
approximately 6.8V. The resistor divider
values m ay be adjusted accordingly to m eet
PVIN requirements. See Figure X.
• PVIN rail should be in regulation (>4.5V)
prior to being enabled.
• Since the ENABLE pin is tied to the resistor
divider to PVIN, an open drain (such as the
POK signal of another regulator or
Sequencer) should be tied to ENABLE in
order to keep the device disabled while the
PVIN rail rises into regulation.
• Once the PVIN rail is in regulation, the
ENABLE may be pulled high through the
resistor divider .
• The ENABLE rise time must be faster than
3V/100us.
The output will start up from the Pre-Bias voltage
into regulati on m onotonically if the instructions ar e
followed; otherwise, the P re-Bi as Protection featu r e
may not function properly and the device will
startup into a Pre-Bias output voltage. Starting up
VOUT
VIN
2x
22µF
1206
VOUT
ENABLE
AGND
PVIN
AVIN
PGND PGND
47nF
VFB
R
A
R
B
R
CA
C
A
RCLX
AVINO
PG
BTMP
EN2392QI
SS
VDDB
BGND
FADJ
4.75k
0.22µF
47nF
R
FS
EN_PB M/S
EAIN
R
EA
10k
2.26k
1µF 1µF
R
CLX
C
OUT
V
OUT
V
IN
2x
22µF
1206
VOUT
ENABLE
AGND
PVIN
AVIN
PGND PGND
47nF
VFB
RA
RB
RCA
CA
RCLX
AVINO
PG
BTMP
EN2392QI
SS
VDDB
BGND
FQADJ
0.22µF
47nF
RFS
1µF
EN_PB M/S
OFF
ON
EAIN
REA
V
AVIN
RCLX
COUT
www.altera.com/enpirion Page 15
10107 June 2, 2015 Rev C
EN2392QI
into a Pre-Bias voltage without the Pre-Bias
Protection feature enabled can lead to device
damage. When using the Pre-Bias feature, the
device must be disabled using the ENABLE pin
prior to PVIN falling out of regulation (<4.5V),
otherwise damage may occur during shutdown. To
disable the Pre-Bias feature pull the EN_PB pin
directly to ground. Do not leave the EN_PB pin
floating. See Typical Performance Characteristics
for an example of Pre-Bias Protection. See F igure
X for a typical schematic with Pre-Bias Protection
enabled.
V
OUT
V
IN
2x
22µF
1206
VOUT
ENABLE
AGND
PVIN
AVIN
PGND PGND
47nF
VFB
R
A
R
B
R
CA
C
A
RCLX
C
OUT
AVINO
PG
BTMP
EN2392QI
SS
VDDB
BGND
FQADJ
4.75k
1µF
0.22µF
47nF
R
FS
1µFEN_PB
M/S
EAIN
R
EA
10k
2.26k
R
CLX
Need Fast
ENABLE Logic
(>3V/100us)
Figure X. Pre-Bias Applicat ion Circuit
Frequency Synchronization
The switching frequency of the EN2392QI can be
phase-locked to an external clock source to move
unwanted beat frequencies out of band. The
internal switching clock of the EN2392QI can be
phase locked to a clock signal applied to the S_IN
pin. An acti vity detector recogniz es the prese nc e o f
an external clock signal and automatically phase-
locks the internal oscillator to this external clock.
Phase-lock will occur as long as the input clock
frequency is in the range of 0.9M H z to 1.8M Hz . Th e
external clock frequency must be within ±10% of
the nominal switching frequency set by the RFS
resistor. It is recommended to use a synchronized
clock frequency close to the typical frequency
recommendations in Table 1. A 3.01kΩ resistor
from FQADJ to ground is recommended for clock
frequencies within ±10% of 1MHz. When no clock
is present, the device reverts to the free running
frequency of the internal oscillator set by the RFS
resistor.
The efficiency performance of the EN2392QI for
various P VI N/VOU T com binations can be opti mize d
by adjusting the switching frequency. Table 1
shows recommended RFS values for various
PVIN/VOUT combinations in order to optimize
performance of the EN2392QI. Using higher RFS
resistor values are allowed. Do not use lower RFS
values than recommendations as that may set the
frequency too low and cause inductor saturation.
When synchronizing multiple devices, use the
highest recommended switching frequency of the
devices.
Fi gure 9. RFS vers us S wi t chi ng F requenc y
PVIN
VOUT
RFS
Typ ical fsw
12V
3.3V
22k
1.42 MHz
2.5V
10k
1.3 MHz
1.8V
4.87k
1.15 MHz
1.5V
3.01k
1.0 MHz
1.2V
3.01k
1.0 MHz
≤1.0V
3.01k
1.0 MHz
Ta bl e 1: Recom m ended RFS Values.
Soft-Start Operation
Soft start is a means to ramp the output voltage
gradually upon start-up. The output voltage rise
time is controlled by the choice of soft-start
capacitor, which is placed between the SS pin and
the A GN D pin. During start-up of the converter, th e
reference voltage to the error amplifier is linearly
increased to its final level by an internal current
source of approx im ately 10µA . The soft-sta rt tim e i s
m easured from when VIN > VUVLOR and ENABLE pin
voltage crosses its logic high threshold to when
VOUT reaches i ts program m ed value. The total soft-
start time can be calculated by:
Soft Star t Time ( ms) : TSS ≈ Css [nF] x 0.06
Typical soft-start time is approximately 2.8ms with
SS capacitor value of 47nF.
0.600
0.800
1.000
1.200
1.400
1.600
1.800
0 2 4 6 8 10 12 14 16 18 20 22
SWITCHING FREQUENCY (MHz)
R
FS
RESIST OR V ALUE (kΩ)
Rfs v s. SW Frequency
CONDITIONS
V
IN
= 6V to 12V
V
OUT
= 0.8V to 3.3V
www.altera.com/enpirion Page 16
10107 June 2, 2015 Rev C
EN2392QI
P OK Op e r a tio n
The POK signal is an open drain signal ( r equires a
pull up resistor to AVIN or similar voltage) from the
converter indicating the output vol tage is within the
specified range. Typically, a 100kΩ or lower
resistance is used as the pul l-up r esistor. The POK
signal will be logic high (AVIN) when the output
voltage is above 90% of the programmed voltage
level. If the output voltage is below this point, the
POK signal will be a logic low. The POK signal can
be used to sequence down-stream converters by
tying to their enable pins.
Over Current Protection
The current limit function is achieved by sensing
the current flowing through a high-side sense
PFET. If the current exceeds the OCP threshold,
the switching cycle is terminated and an OCP
counter is incremented. If the counter value
reaches 32 OCP cycles, the device will shut down
as described below. If there are 8 consecutive
cycles that do not exceed the OCP threshold, the
counter will reset. Once the OCP counter has
reached 32 cycles, the MOSFET switches will tri-
state and the soft start capaci tor w ill be discharged .
After appr oximately 32ms the device will attempt a
restart. If the OCP condition persists, the device
will enter a hiccup mode until the OCP condition is
removed. The OCP trip point depends on PVIN,
VOUT, RCLX, RFS and is meant to protect the
device from damage. OCP is not an adjustable
threshold. Follow Table 2 for recommended RCLX
and RFS values to set the current limit above 9A
under normal operating conditions. Not following
Table 2 may result in current limit being too low or
too high.
Note: Do not leave RCLX pin floating.
PVIN
VOUT
RCLX
RFS
4.5V to
13.2V
3.3V
31.6k
22k
2.5V
34.8k
10k
1.8V
35.7k
4.87k
1.5V
34.8k
3.01k
1.2V
39.2k
3.01k
≤1.0V
40.2k
3.01k
Ta bl e 2: Recom m ended RCLX Values
Thermal Overload Protection
Thermal shutdown circuit will disable device
operation when the junction temperature exceeds
approximately 150°C. The device will go through a
soft-shutdown and allow the output to discharge in
a controlled manner. This prevents excessive
output ringing in the event of a thermal fault
condition. After a thermal shutdown event, when
the junction temperature drops by approximately
35°C, the converter will re-start with a normal soft-
start.
AVIN Under-Voltage Lock-Out (UVLO)
Internal circuits ensure that the converter will not
start sw itching unti l the AVIN input voltage is above
the specified minimum voltage. Hysteresis, input
de-glitch and output leadin g edge blanking ensures
high noise immunity and prevents false UVLO
triggers.
Master / Slave (Parallel) Op eration:
Figure 10. Parallel Cur r ent Matching
Up to four EN2392QI devices may be connected in
a Master/Slave configuration to handle larger load
currents. The maximum output current for each
parallel device will need to be de-rated by 20
percent so that no devices will over curr ent due to
current mis-match. The Master device’s switching
clock may be phase-locked to an external clock
source via the S_IN pin or left open and use its
default switching frequency. The device is placed in
Master mode by pulling the M/S pin low or in Slave
m ode by pulli ng M/S pin high. Note that the M /S pin
is also pulled low for standalone mode. In Master
mode, the internal PWM signal is output on the
S_OUT pin. This PWM signal from the Master is
fed to the S lave device at its S_IN input. The Slave
device acts like an extension of the power FETs in
the Master. The inductor in the Slave prevents
crow-bar currents from Master to Slave due to
timing delays. Parallel operation in dual supply
mode is shown in Figure 11. Single supply mode
operation may also be implemented similar ly. Note
that only critical components are shown. The red
0
1
2
3
4
5
6
7
8
9
10
246810 12 14 16
INDIVIDUAL OUT PUT CURRENT (A)
TOTAL OUTPUT CURRENT (A)
Par allel C ur rent Shar e Br eakdown
MASTER
SLAVE
IDEAL
CONDITIONS
EN2390QI
VIN = 12V
VOUT = 1.2V
www.altera.com/enpirion Page 17
10107 June 2, 2015 Rev C
EN2392QI
text and red lines indicate the important parallel
operation connections and care should be taken in
layout to ensure low impedance between those
paths. The parallel curre nt m atching is illustrated in
Figure 10.
Figure 11. Parallel Operation Illustration
VOUT
VIN
22µF
1206
VOUT
ENA
AGND
SS
PVIN
AVIN
PGND PGND
EN2392QI
(MASTER)
47nF
VFB
R
A
R
B
R
1
C
A
FQADJ
2x
47µF
1206
M/S
S_OUT
22µF
1206
VOUT
ENA
AGND
PVIN
AVIN
PGND PGND
EN2392QI
(SLAVE)
FQADJ
2x
47µF
1206
M/S
S_IN
VFB
open
SS
47nF
AVIN
AVIN
Note 2:
The Master and Slave VOUTs should be
connected with very low impedance as
shown by the double red line connections
in parallel.
Note 3:
The Master and Slave PGNDs should be
connected with very low impedance as shown by
the double red line connections in parallel.
Note 1:
The Master and Slave VINs should be connected
with very low impedance as shown by the double
red line connections in parallel.
Note 4:
Up to 3 Slaves may
be used in parallel
with the Master
Slave #1
www.altera.com/enpirion Page 18
10107 June 2, 2015 Rev C
EN2392QI
Application Information
Output Voltage Programming and Loop
Compensation
The EN2392QI uses a Type IV Voltage Mode
compensation network. Type IV Voltage Mode
control is a proprietary Altera Enpirion control
scheme that maximizes control loop bandwidth to
deliver excellent load transient responses and
maintain output regulation with pin point accuracy.
For ease of use, most of this network has been
customized and is integrated within the device
package.
The EN2392QI output voltage is progra m m ed usin g
a simple resistor divider network (RA and RB). The
feedback voltage at VFB is nominally 0.6V. RA is
predetermined based on Table 5 and RB can be
calculated based on Figure 12. The values
recommended for COUT, CA, RCA and REA make up
the external compensation of the EN2392QI. It will
vary with each PVIN and VOUT combination to
optimize on performance. The EN2392QI solution
can be optimized for either smallest size or highest
performance. Please see Table 5 for a list of
recom m ended RA, CA, RCA, REA and COUT values for
each solution. Since VFB is a sensitive node, do
not touch the VFB node while the device is in
operation as doing so may introduce parasitic
capacitance into the control loop that causes the
device to behave abnormally and damage may
occur.
Figure 12: VOUT Resistor Divider & Compensation
Components. See T able 5 for details.
In put C apacitor S election
The EN2392QI requires two 22µF/1206 input
capacitors. Low-cost, low-ESR ceramic capacitors
should be used as input capacitors for this
converter. The dielectric must be X5R or X7R
rated. Y5V or eq ui valent dielec tric formulations
must not be used as these lose too much
capacitance with freq uen cy, temper at ur e and
bias voltage. In some applications, lower value
capacitors are needed in parallel with the larger,
capacitors in order to provide high frequency
decoupling. Distance from the input power source
to the input of the device creates parasitic
inductance which can increase input ripple during
startup or in steady state operation. Be sure the
input is properly filtered with additional bulk
capacitance so that the input AC ripple on PVIN is
less than 1V peak-to-peak. Placing capacitors in
parallel reduces the impedance and will result in
lower ripple voltage. Table 2 contains a list of
recommended input capacitors.
Recommended Input Capacitors
Description
MFG
P/N
22µF, 16V, X5R,
10%, 1206 Murata GRM31CR61C226ME15
22µF, 16V, X5R,
20%, 1206
Taiyo
Yuden EMK316ABJ226ML-T
Ta bl e 2: Rec om mended Input Capaci tors
Ou tpu t C apacitor Selection
As seen from Table 5, the EN2392QI has been
optimized for use with one 100µF/1206 plus two
47µF/1206 outpu t capacit ors for best perform ance.
For smallest solution size, various combinations of
output capacitance may be used. See Table 5 for
details. Low ESR ceramic capacitors are required
with X5R or X7R rated dielectric formulation. Y5V
or equivalent dielectric formulations must not be
used as these lose too much capacitance with
frequency, temperature and bias voltage. Table 4
contains a list of recommended output capacitors.
Extra bulk capacitor s may be used to improve load
transient response at the load. The maximum
output capacitance allowed on the EN2392QI
depends on the output voltage. Table 3 shows the
maximum output capacitance based on output
voltage. The m ax im um output capacitance i ncludes
all capacitors connected from the output power
plain to ground.
V
OUT
VOUT
PGND
VFB
R
A
R
B
R
CA
C
A
C
OUT
EAIN
R
EA
R
A
V
FB
V
FB
V
OUT
x-
=
V
FB
= 0.6V
EN2392QI
www.altera.com/enpirion Page 19
10107 June 2, 2015 Rev C
EN2392QI
VOUT
RFS
COUT_MAX
Snubber
3.3V
22k
800µF
4.7Ω + 680pF
2.5V 10k 1200µF 4.7Ω + 680pF
1.8V 4.87k 1600µF 4.7Ω + 680pF
1.5V
3.01k
1800µF
4.7Ω + 680pF
1.2V
3.01k
2000µF
4.7Ω + 680pF
≤1.0V 3.01k 2200µF 4.7Ω + 680pF
Table 3: M axim um O ut put Capac i t ance
If the maximum output capacitance in the
application exceeds 50% of the COUT_MAX value
in Table 3, then a “snubber ” circuit is required (See
Figure 1). The “snubber” circuit is a series re sisto r
and capacitor from the NC(SW) pin to PGND. T he
“snubber” values are optimized for the EN2392QI
and should be followed to within 10% of the
recommendations. Due to the added power
dissipation, using the “snubber” will decrease the
converter efficiency by around 1 percent. It is
recommended to use at least a ¼W resistor at
1206 case siz e or greater due to power dissipation.
The capacitor should be at least 0603 case size.
Since additional bulk capacitance changes the LC
double pole of the Voltage Mode Control
architecture, be sure to have at least 4mΩ of
separation between the feedback sense point and
the additional bul k capacitor s. Be sure to follow the
Best Performance external compensation
recommendations in Table 5.
The output capacitance can also influence the
output ripple. Output ripp le voltage is determ ine d b y
the aggregate output capacitor impedance.
Capacitor impedance, denoted as Z, is comprised
of capacitive reactance, effective series resistance,
ESR, and effective series inductance, ESL
reactance.
Placing output capacitors in parallel reduces the
impedance and will hence result in lower ripple
voltage.
nTotal
ZZZZ 1
...
111
21
+++=
Recommended Output Capacitors
Description
MFG
P/N
47µF, 6.3V , X5R,
20%, 1206
Murata GRM31CR60J476ME19L
47µF, 10V, X5R,
20%, 1206
Taiyo
Yuden LMK316BJ476ML-T
22µF, 10V, X5R,
20%, 0805
Panasonic ECJ-2FB1A226M
22µF, 10V, X5R,
20%, 0805
Taiyo
Yuden
LMK212BJ226MG-T
100µF, 6.3V , X5R,
20%, 1206
Murata GRM31CR60J107ME39L
Taiyo
Yuden
JMK316BJ107ML-T
Table 4: Rec om m ended O ut put Capac i t ors
www.altera.com/enpirion Page 20
10107 June 2, 2015 Rev C
EN2392QI
Best Performance
Smalle st Solution Siz e
CIN = 2x22µF/1206
CIN = 2x22µF/1206
COUT = 100µF/1206 + 2x47µF/1206
V
OUT
≤ 1.8V, C
OUT
= 2x47µF /0805
1.8V < VOUT ≤ 3.3V, COUT = 2x47µF /1206
R
A
= 200 kΩ
R
A
= 75k
PVIN
(V) VOUT
(V) CA
(pF) RCA
(kΩ) REA
(kΩ) Ripple
(mV) Deviation
(mV) PVIN
(V) VOU
T (V)
C
A
(pF
)
R
CA
(kΩ
)
REA
(kΩ)
Rippl
e
(mV)
Deviatio
n (mV)
13.2V
0.9V 15 18 0 5.83 44
13.2V
0.9V 18 8.2 Open 15 93
1.2V
15
22
0
7.22
48
1.2V
18
8.2
Open
21
104
1.5V
18
22
0
8.63
38
1.5V
18
8.2
Open
27
110
1.8V
15
22
0
10.8
50
1.8V
18
8.2
Open
35
120
2.5V 27 5.1 33 14.6 72
2.5V 15 8.2 Open 54 150
3.3V
22
8.2
33
26.1
76
3.3V
10
8.2
Open
81
215
12V
0.9V
27
18
0
5.21
40
12V
0.9V
27
5.1
Open
15
96
1.2V 22 22 0 6.7 36
1.2V 27 5.1 Open 21 104
1.5V
18
22
0
8.98
44
1.5V
27
5.1
Open
27
112
1.8V 18 22 0 10 50
1.8V 27 5.1 Open 34 130
2.5V
27
5.1
33
12.6
76
2.5V
22
5.1
Open
52
162
3.3V
22
8.2
33
23.6
72
3.3V
15
5.1
Open
77
221
10V
0.9V
27
18
0
5.01
44
10V
0.9V
56
2
Open
15
99
1.2V 22 22 0 6.28 40
1.2V 56 2 Open 20 107
1.5V
18
22
0
8.57
54
1.5V
39
2
Open
26
122
1.8V
18
22
0
9.44
60
1.8V
39
2
Open
33
126
2.5V 33 5.1 33 11 64
2.5V 33 2 Open 50 169
3.3V
27
8.2
33
21.6
68
3.3V
22
2
Open
71
241
8V
0.9V
27
18
0
4.9
44
8V
0.9V
100
0
Open
15
108
1.2V
22
22
0
5.82
48
1.2V
100
0
Open
20
113
1.5V 22 22 0 7.48 56
1.5V 82 0 Open 25 122
1.8V
22
22
0
8.01
54
1.8V
68
0
Open
31
136
2.5V
33
5.1
33
10.7
76
2.5V
47
0
Open
46
183
3.3V 27 8.2 33 20.5 84
3.3V 33 0 Open 62 253
6.6V
0.9V
33
18
0
4.58
46
6.6V
0.9V
100
0
Open
14
121
1.2V 27 22 0 5.28 54
1.2V 100 0 Open 19 128
1.5V
27
22
0
6.44
54
1.5V
100
0
Open
24
138
1.8V
22
22
0
7.2
58
1.8V
100
0
Open
29
149
2.5V
33
5.1
33
11.4
84
2.5V
68
0
Open
41
188
3.3V
33
8.2
33
18.4
96
3.3V
47
0
Open
53
239
5V
0.9V
39
18
0
4.1
54
5V
0.9V
100
0
Open
13
152
1.2V
33
22
0
5.1
62
1.2V
100
0
Open
18
161
1.5V
27
22
0
6.2
66
1.5V
100
0
Open
22
177
1.8V
27
22
0
7.02
68
1.8V
100
0
Open
25
183
2.5V
39
5.1
33
9.84
104
2.5V
100
0
Open
33
216
Table 5 : RA, C A, RCA and R EA Values f or Various PVIN /VOUT Combinations: B est Perf ormanc e vs. Small es t Sol ution
Size. Use the equations in Figure 12 to calculat e RB. Output Ripple is measured at no load and Nominal
Deviation is for a 9A load transient step in one direction. For a voltage in between the specified output voltages,
choose compensa tion values of the lower output voltage setting.
www.altera.com/enpirion Page 21
10107 June 2, 2015 Rev C
EN2392QI
Thermal Considerations
Therm al consideratio ns are im porta nt power supply
design facts that cannot be avoided in the real
world. Whenever there are power losses in a
system, the heat that is generated by the power
dissipation needs to be accounted for. The Altera
Enpirion PowerSoC helps alleviate some of those
concerns.
The Altera Enpirion EN2392QI DC-DC converter is
packaged in a 10x11x3mm 76-pin QFN package.
The QF N package is constructed with copper lead
frames that have exposed thermal pads. The
exposed thermal pad on the package should be
soldered directly on to a copper ground pad on the
printed circuit board (PCB) to act as a heat sink.
The r ecommended maximum junction temperature
for continuous operation is 125°C. Continuous
operation above 125°C may reduce long-term
reliability. The device has a thermal overload
protection circuit designed to turn off the device at
an approximate junction temperature value of
150°C.
The following example and calculations illustrate
the thermal performance of the EN2392QI.
Example:
VIN = 12V
VOUT = 1.2V
IOUT = 9A
First calculate the output power .
POUT = 1.2V x 9A = 10.8W
Next, determine the input power based on the
efficiency (η) shown in F igure 13.
Figure 13: Effici ency vs. Output Current
For VIN = 12V, VOUT = 1.2V at 9A, η ≈ 82%
η = POUT / PIN = 82% = 0. 82
PIN = POUT / η
PIN ≈ 10.8W / 0.8 ≈ 13.17W
The pow er dissipation (PD) is the power loss in the
system and can be calculated by subtracting the
output power from the input power .
PD = PIN – POUT
≈ 13.17W – 10.8W ≈ 2.37W
With the power dissipation known, the tem perature
rise in the device may be estimated based on the
theta JA value (θJA). The θJA parameter estimates
how m uch the tem perature w ill rise in the device for
every watt of pow er dissipation. The EN2392QI has
a θJA value of 15 ºC/W without airflow.
Determine the change in temperature (ΔT) based
on PD and θJA.
ΔT = PD x θJA
ΔT ≈ 2.37W x 15°C/W = 35.56°C ≈ 36°C
The junction temperature (TJ) of the device is
approximately the ambient temperature (TA) plus
the change in temperature. We assume the initial
ambient temperature to be 25°C.
TJ = TA + ΔT
TJ ≈ 25°C + 36°C ≈ 61°C
The maximum operating junction temperature
(TJMAX) of the device is 125°C, so the device can
operate at a higher ambient temperature. The
m ax i m um am bient tem perature (TAMAX) allow ed can
be calculated.
TAMAX = TJMAX – PD x θJA
≈ 125°C – 36°C ≈ 89°C
The m ax im um am bient tem perature the device can
reach is 89°C gi ven the input and output cond itio n s.
Note that the efficiency will be slightly lower at
higher temperatures and this calculation is an
estimate. Check De-rating Curves for guaranteed
maximum output current over temperature.
0
10
20
30
40
50
60
70
80
90
100
0123456789
EFFICIENCY (%)
OUTPUT CURRENT (A)
Efficiency vs. Output Current
VOUT = 3.3V
VOUT = 2.5V
VOUT = 1.8V
VOUT = 1.2V
VOUT = 1.0V
CONDITIONS
V
IN
= 12.0V
AVIN = 3.3V
Dual Supply
www.altera.com/enpirion Page 22
10107 June 2, 2015 Rev C
EN2392QI
Layout Recommendation
Figure 15: Cri t i cal Com ponent Lay out for Mi ni m um
Footprint (Top Layer). See Fi gure 14 for s chemati c .
Thi s l ayout onl y s hows t he cri t i cal com ponents and top
layer traces for minimum footprint in single-supply,
master mode. Alternate circuit configurations & other
low-power pins need to be connected and routed
according to customer application. Please see the
Gerber files at www.altera.com/enpirion for det ail s on al l
layers.
Recommendation 1: Input and output filter
capacitors should be placed on the same side of
the PCB, and as close to the EN2392QI package
as possible. They should be connected to the
device with very short and wide traces. Do not use
thermal reliefs or spokes when connecting the
capacitor pads to the respectiv e nodes. The +V a n d
GND traces between the capacitors and the
EN2392QI should be as close to each other as
possible so that the gap between the two nodes is
minimized, even under the capacitor s.
Re comme ndation 2: The PGND connections for
the input and output capacitors on layer 1 need to
have a slit between them in order to provide some
separation betw een input and output current loops.
Recommendation 3: The system ground plane
should be the first layer immediately below the
surface layer. This ground plane should be
conti nuous and un-interrupted below the converter
and the input/output capacitors.
Recommendation 4: The therm al pad underneath
the component must be connected to the system
ground plane through as many vias as possible.
The drill diameter of the vias should be 0.33mm,
and the vi as m ust have at least 1 oz. copper plating
on the inside wall, making the finished hole size
around 0.20-0.26mm. Do not use thermal reliefs or
spokes to connect the vias to the ground plane.
This connection provides the path for heat
dissipation from the converter.
Recommendation 5: Multiple small vias (the same
size as the thermal vias discussed in
recommendation 4) should be used to connect
ground terminal of the input capacitor and output
capacitors to the system ground plane. It is
preferred to put these vias along the edge of the
G ND c o pper closest to the +V copper. These vias
connect the input/output filter capacitors to the
GND plane, and help reduce parasitic inductances
in the input and output curre nt loops. If vias cannot
be placed under the capacitor s, then place them on
both si des of the slit in the top layer PGND copper.
Recommendation 6: AVIN is the power supply for
the small-signal control circuits. AVINO powers
AVIN in single supply mode. AVIN and AVINO
should have a decoupling capacitor close to each
of their pins. Refer to F igure 15.
Recommendation 7: The layer 1 metal under the
device must not be more than shown in Figure13.
Refer to the section regarding Exposed Metal on
Bottom of Package. As with any switch-mode
DC/DC converter, try not to run sensitive signal or
control lines underneath the converter package on
other layer s.
Recommendation 8: The VOUT sense point should
be just after the last output fil ter capacitor . K eep t h e
sense trace short in order to avoid noise coupling
into the node. Contact Altera MySupport for any
remote sensing applications.
Recommendation 9: Keep RA, CA, RB, and RCA
close to the V FB pin (Refer to Figure 15). The VFB
pin is a high-impedance, sensitive node. Keep the
trace to this pin as short as possible. Whenever
possible, connect RB dir ectly to the AGND instead
of going through the GND plane.
Recommendation 10: Follow all the layout
recommendations as close as possible to optimize
performance. Altera provides schematic and layout
reviews for all customer designs. Contact Altera
MySupport
for detailed support
(www.altera.com/mysupport).
www.altera.com/enpirion Page 24
10107 June 2, 2015 Rev C
EN2392QI
Design Considerations for Lead-Frame Based Modules
Expose d Me tal on B ottom of Package
Lead-frames offer many advantages in thermal performance, in reduced electrical lead resistance, and in
overall foot print. However, they do require some special consider ations.
I n the assem bly process lead fram e constructio n requ ires that, for m echanica l suppor t, som e of the lead-frame
canti levers be ex posed at the point w here wire-bond or internal passives are attached. This results in several
small pads being exposed on the bottom of the package as shown in Figure 16.
Only the therm al pad and the perim eter pads are to be m echani ca lly or electrica lly connec ted to the PC board.
The PC B top layer under the EN2392QI should be clear of any m etal (copper pou rs, tra ces, or vias) ex cept for
the therm al pad. The “shaded-ou t” are a in Figure 16 represents the area that should be clear of any metal on
the top layer of the PCB. Any layer 1 metal under the shaded-out area runs the risk of undesirable shorted
connections even if it is covered by solder mask.
The solder stencil aperture should be smaller than the PCB ground pad. T his will pr event excess solder from
causing bridging between adjacent pins or other exposed metal under the package. Please consult the
EN2392QI QFN P ackage S ol dering G ui del ines for more details and recommendations.
Fi gure 16: Lead-F rame exposed m et al (B ott om Vi ew)
Shaded area hi ghl ights exposed m et al that i s not to be m echani call y or electri cal ly connec ted t o the P CB .
www.altera.com/enpirion Page 25
10107 June 2, 2015 Rev C
EN2392QI
Package and Mechanical
Fi gure 18: EN2392QI P ac kage Di m ens i ons (B ott om V i ew)
Packi ng and Marki ng I nform a tion: www.altera.com/support/reliability/packing/rel-packing-and-marking.html
Contact Information
Altera Corporation
101 Innovation D rive
San Jos e, CA 95134
Phone: 408-544-7000
www.altera.com
© 2013 Altera Corporation—Confident ial. All rights reserved. ALT ERA, ARRI A, CYC LON E, ENPIRI ON , HA RDC OPY, M AX, M EGACORE, NIOS, QUART US and STRA T IX
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trademarks or service marks are the propert y of their respec tive holders as describe d at w w w .altera. c om/c ommon/ legal. ht ml. Alte ra w arrants performance of its s emiconduc t or
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www.altera.com/enpirion Page 27
10107 June 2, 2015 Rev C
