BCM®Bus Converter Rev 1.5 vicorpower.com
Page 1 of 25 07/2015 800 927.9474
BCM®Bus Converter
Fixed Ratio DC-DC Converter
S
NRTL
CUS
CUS
®
S
NRTL
CUS
CUS
®
BCM384x120y1K5ACz
Features
•Up to 1500 W continuous output power
• 2208 W/in3power density
• 97.4 % peak efficiency
• 4,242 Vdc isolation
•Parallel operation for multi-kW arrays
•OV, OC, UV, short circuit and thermal protection
• 2361 through-hole ChiP package
n 2.402 ” x 0.990 ” x 0.286 ”
( 61.00 mm x 25.14 mm x 7.26 mm)
Typical Applications
• 380 DC Power Distribution
• High End Computing Systems
• Automated Test Equipment
• Industrial Systems
• High Density Power Supplies
• Communications Systems
• Transportation
Product Description
The VI Chip® Bus Converter (BCM®) is a high eciency
Sine Amplitude Converter™ (SAC™), operating from a 260 to
410 VDC primary bus to deliver an isolated, ratiometric output
from 8.1 to 12.8 VDC.
The BCM384x120y1K5ACz oers low noise, fast transient
response, and industry leading eciency and power density. In
addition, it provides an AC impedance beyond the bandwidth
of most downstream regulators, allowing input capacitance
normally located at the input of a POL regulator to be located at
the primary side of the BCM module. With a primary to
secondary K factor of 1/32 , that capacitance value can be
reduced by a factor of 1024 x, resulting in savings of board area,
material and total system cost.
Leveraging the thermal and density benefits of Vicor’s ChiP
packaging technology, the BCM module oers flexible thermal
management options with very low top and bottom side
thermal impedances. Thermally-adept ChiP-based power
components, enable customers to achieve low cost power
system solutions with previously unattainable system size,
weight and eciency attributes, quickly and predictably.
This product can operate in reverse direction, at full rated
power, aer being previously started in forward direction.
Product Ratings
VPRI = 384 V ( 260 – 410 V) PSEC= up to 1500 W
VSEC = 12 V ( 8.1 – 12.8 V)
(NO LOAD)K = 1/32
BCM®Bus Converter Rev 1.5 vicorpower.com
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BCM384x120y1K5ACz
Typical Application
BCM384x120y1K5ACz+ Point of Load
BCM
VAUX
EN
+VPRI
–VPRI
+VSEC
–VSEC
VPRI
enable/disable
switch
FUSE
ISOLATION BOUNDRY
PRIMARY SECONDARY
SOURCE_RTN
CI_BCM_ELEC
TM
POL
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BCM384x120y1K5ACz
Pin Configuration
12
A
B
C
D
E
F
G
H
+VPRI
+VSEC
TOP VIEW
2361 ChiP Package
I
–VSEC1
–VSEC1
+VSEC
+VSEC
–VSEC1
+VSEC
–VSEC1
+VPRI J
+VPRI K
+VPRI L
A’
B’
C’
D’
E’
F’
G’
H’
I’
J’
K’
L’
+VSEC
–VSEC2
–VSEC2
+VSEC
+VSEC
–VSEC2
+VSEC
–VSEC2
–VPRI
TM
EN
VAUX
Pin Descriptions
Pin Number Signal Name Type Function
I1, J1, K1, L1 +VPRI PRIMARY POWER Positive primary transformer power terminal
I’2 TM OUTPUT Temperature Monitor; Primary side referenced signals
J’2 EN INPUT Enables and disables power supply; Primary side referenced
signals
K’2 VAUX OUTPUT Auxilary Voltage Source; Primary side referenced signals
L’1 -VPRI
PRIMARY POWER
RETURN Negative Primary transformer power terminal
A1, D1, E1, H1, A’2,
D’2, E’2, H’2 +VSEC SECONDARY POWER Positive secondary transformer power terminal
B1, C1, F1, G1,
B’2, C’2, F’2, G’2 -VSEC*
SECONDARY POWER
RETURN Negative secondary transformer power terminal
*For proper operation an external low impedance connection must be made between listed -VSEC1 and -VSEC2 terminals.
BCM®Bus Converter Rev 1.5 vicorpower.com
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BCM384x120y1K5ACz
Absolute Maximum Ratings
The absolute maximum ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause permanent damage to the device.
Parameter Comments Min Max Unit
+VPRI_DC to –VPRI_DC -1 480 V
VPRI_DC or VSEC_DC slew rate
(operational) 1 V/µs
+VSEC_DC to –VSEC_DC -1 15 V
TM to –VPRI_DC
-0.3
4.6 V
EN to –VPRI_DC 5.5 V
VAUX to –VPRI_DC 4.6 V
Part Ordering Information
Device Input Voltage
Range Package Type Output
Voltage x 10
Temperature
Grade
Output
Power Revision Package
Size Version
BCM 384 x 120 y 1K5 A C z
BCM = BCM 384 = 260 to 410 V P =
ChiP Through Hole 120 = 12 V T = -40 to 125 °C
M = -55 to 125 °C 1K5 = 1,500 W A C = 2361 0 = Analog
R = Reversible
Standard Models
All products shipped in JEDEC standard high profile (0.400” thick) trays (JEDEC Publication 95, Design Guide 4.10).
Part Number VIN Package Type VOUT Temperature Power Package Size
BCM 384 P 120 T 1K5 AC0 260 to 410 V ChiP Through Hole 12 V
8.1 to 12.8 V -40 °C to 125 °C 1,500 W 2361
BCM 384 P 120 M 1K5 AC0 260 to 410 V ChiP Through Hole 12 V
8.1 to 12.8 V -55 °C to 125 °C 1,500 W 2361
BCM 384 P 120 T 1K5 ACR 260 to 410 V ChiP Through Hole 12 V
8.1 to 12.8 V -40 °C to 125 °C 1,500 W 2361
BCM 384 P 120 M 1K5 ACR 260 to 410 V ChiP Through Hole 12 V
8.1 to 12.8 V -55 °C to 125 °C 1,500 W 2361
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BCM384x120y1K5ACz
Electrical Specifications
Specifications apply over all line and load conditions, unless otherwise noted; Boldface specifications apply over the temperature range of -40 °C ≤ TINTERNAL
≤ 125 °C (T-Grade); All other specifications are at TINTERNAL = 25 ºC unless otherwise noted.
Attribute Symbol Conditions / Notes Min Typ Max Unit
General Powetrain PRIMARY to SECONDARY Specification (Forward Direction)
Primary Input Voltage range,
continuous VPRI_DC 260 410 V
VPRI µController VµC_ACTIVE VPRI_DC voltage where µC is initialized,
(ie VAUX = Low, powertrain inactive) 130 V
PRI to SEC Input Quiescent Current IPRI_Q
Disabled, EN Low, VPRI_DC = 384 V 2 mA
TINTERNAL ≤ 100 ºC 4
PRI to SEC No Load Power
Dissipation PPRI_NL
VPRI_DC = 384 V, TINTERNAL = 25 ºC 11 17
W
VPRI_DC = 384 V 5.9 25
VPRI_DC = 260 V to 410 V, TINTERNAL = 25 ºC 19
VPRI_DC = 260 V to 410 V 27
PRI to SEC Inrush Current Peak IPRI_INR_PK
VPRI_DC = 410 V, CSEC_EXT = 1000 µF, RLOAD_SEC = 50 %
of full load current 10 A
TINTERNAL ≤ 100 ºC 15
DC Primary Input Current IPRI_IN_DC At ISEC_OUT_DC = 125 A, TINTERNAL ≤ 100 ºC 4.1 A
Transformation Ratio KPrimary to secondary, K = VSEC_DC / VPRI_DC, at no load 1/32 V/V
Secondary Output Power
(continuous) PSEC_OUT_DC Specified at VPRI_DC = 410 V 1500 W
Secondary Output Power (pulsed) PSEC_OUT_PULSE Specified at VPRI_DC = 410 V; 10 ms pulse, 25% Duty
cycle, PSEC_AVG = 50 % rated PSEC_OUT_DC 2000 W
Secondary Output Current
(continuous) ISEC_OUT_DC 125 A
Secondary Output Current (pulsed) ISEC_OUT_PULSE 10 ms pulse, 25% Duty cycle, ISEC_OUT_AVG = 50 % rated
ISEC_OUT_DC 167 A
PRI to SEC Efficiency (ambient) ηAMB
VPRI_DC = 384 V, ISEC_OUT_DC = 125 A 96.2 97
%VPRI_DC = 260 V to 410 V, ISEC_OUT_DC = 125 A 95.2
VPRI_DC = 384 V, ISEC_OUT_DC = 62.5 A 96.5 97.4
PRI to SEC Efficiency (hot) ηHOT VPRI_DC = 384 V, ISEC_OUT_DC = 125 A 95.8 97 %
PRI to SEC Efficiency
(over load range) η20% 25 A < ISEC_OUT_DC < 125 A 90 %
PRI to SEC Output Resistance
RSEC_COLD VPRI_DC = 384 V, ISEC_OUT_DC = 125 A, TINTERNAL = -40 °C 1.10 1.50 1.80
mΩRSEC_AMB VPRI_DC = 384 V, ISEC_OUT_DC = 125 A 1.50 1.85 2.30
RSEC_HOT VPRI_DC = 384 V, ISEC_OUT_DC = 384 A, TINTERNAL = 100 °C 1.80 2.30 2.70
Switching Frequency FSW Frequency of the Output Voltage Ripple = 2x FSW 0.95 1.00 1.05 MHz
Secondary Output Voltage Ripple VSEC_OUT_PP
CSEC_EXT = 0 µF, I SEC_OUT_DC = 125 A, VPRI_DC = 384 V,
20 MHz BW 195 mV
TINTERNAL ≤ 100 ºC 250
Primary Input Leads Inductance
(Parasitic) LPRI_IN_LEADS Frequency 2.5 MHz (double switching frequency),
Simulated lead model 7 nH
Secondary Output Leads Inductance
(Parasitic) LSEC_OUT_LEADS Frequency 2.5 MHz (double switching frequency),
Simulated lead model 0.64 nH
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BCM384x120y1K5ACz
Electrical Specifications (Cont.)
Specifications apply over all line and load conditions, unless otherwise noted; Boldface specifications apply over the temperature range of -40 °C ≤ TINTERNAL
≤ 125 °C (T-Grade); All other specifications are at TINTERNAL = 25 ºC unless otherwise noted.
Attribute Symbol Conditions / Notes Min Typ Max Unit
General Powetrain PRIMARY to SECONDARY Specification (Forward Direction) Cont.
Effective Primary Capacitance
(Internal) CPRI_INT Effective Value at 384 VPRI_DC 0.37 µF
Effective Secondary Capacitance
(Internal) CSEC_INT Effective Value at 12 VSEC_DC 208 µF
Effective Secondary Output
Capacitance (External) CSEC_OUT_EXT Excessive capacitance may drive module into SC
protection 1000 µF
Effective Secondary Output
Capacitance (External) CSEC_OUT_AEXT CSEC_OUT_AEXT Max = N * 0.5 * CSEC_OUT_EXT MAX, where
N = the number of units in parallel
Protection PRIMARY to SECONDARY (Forward Direction)
Auto Restart Time tAUTO_RESTART Startup into a persistent fault condition. Non-Latching
fault detection given VPRI_DC > VPRI_UVLO+ 292.5 357.5 ms
Primary Overvoltage Lockout
Threshold VPRI_OVLO+ 420 434.5 450 V
Primary Overvoltage Recovery
Threshold VPRI_OVLO- 410 424 440 V
Primary Overvoltage Lockout
Hysteresis VPRI_OVLO_HYST 10.5 V
Primary Overvoltage Lockout
Response Time tPRI_OVLO 100 µs
Primary Undervoltage Lockout
Threshold VPRI_UVLO- 195 221 250 V
Primary Undervoltage Recovery
Threshold VPRI_UVLO+ 225 243 255 V
Primary Undervoltage Lockout
Hysteresis VPRI_UVLO_HYST 15 V
Primary Undervoltage Lockout
Response Time tPRI_UVLO 100 µs
Primary Undervoltage Startup Delay tPRI_UVLO+_DELAY
From VPRI_DC = VPRI_UVLO+ to powertrain active, EN
floating, (i.e One time Startup delay form application
of VPRI_DC to VSEC_DC)
20 ms
Primary Soft-Start Time tPRI_SOFT-START From powertrain active. Fast Current limit protection
disabled during Soft-Start 1 ms
Secondary Output Overcurrent Trip
Threshold ISEC_OUT_OCP 135 170 210 A
Secondary Output Overcurrent
Response Time Constant tSEC_OUT_OCP Effective internal RC filter 3 ms
Secondary Output Short Circuit
Protection Trip Threshold ISEC_OUT_SCP 187 A
Secondary Output Short Circuit
Protection Response Time tSEC_OUT_SCP 1 µs
Overtemperature Shutdown
Threshold tOTP+ Temperature sensor located inside controller IC 125 °C
Overtemperature Recovery
Threshold tOTP– 105 110 115 °C
Undertemperature Shutdown
Threshold tUTP Temperature sensor located inside controller IC;
Protection not available for M-Grade units. -45 °C
Undertemperature Restart Time tUTP_RESTART Startup into a persistent fault condition. Non-Latching
fault detection given VPRI_DC > VPRI_UVLO+ 3 s
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BCM384x120y1K5ACz
Attribute Symbol Conditions / Notes Min Typ Max Unit
General Powetrain SECONDARY to PRIMARY Specification (Reverse Direction)
Secondary Input Voltage range,
continuous VSEC_DC 8.1 12.8 V
SEC to PRI No Load Power
Dissipation PSEC_NL
VSEC_DC = 12 V, TINTERNAL = 25ºC 11 17
W
VSEC_DC = 12 V 5.9 25
VSEC_DC = 8.1 V to 12.8 V, TINTERNAL = 25ºC 19
VSEC_DC = 8.1 V to 12.8 V 20
DC Secondary Input Current ISEC_IN_DC At IPRI_DC = 3.9 A, TINTERNAL ≤ 100ºC 127 A
Primary Ouptut Power (continuous) PPRI_OUT_DC Specified at VSEC_DC = 12.8 V 1500 W
Primary Output Power (pulsed) PPRI_OUT_PULSE Specified at VSEC_DC = 12.8 V; 10 ms pulse,
25% Duty cycle, PPRI_AVG = 50 % rated PPRI_OUT_DC 2000 W
Primary Output Current (continuous) IPRI_OUT_DC 3.9 A
Primary Output Current (pulsed) IPRI_OUT_PULSE 10 ms pulse, 25% Duty cycle,
IPRI_OUT_AVG = 50 % rated IPRI_OUT_DC 5.2 A
SEC to PRI Efficiency (ambient) ηAMB
VSEC_DC = 12 V, IPRI_OUT_DC = 3.9 A 96.2 97
%VSEC_DC = 8.1 V to 12.8 V, IPRI_OUT_DC= 3.9 A 95.2
VSEC_DC = 12 V, IPRI_OUT_DC = 1.95 A 96.5 97.4
SEC to PRI Efficiency (hot) ηHOT VSEC_DC = 12 V, IPRI_OUT_DC = 3.9 A 96.2 97 %
SEC to PRI Efficiency (over load
range) η20% 0.78 A < IPRI_OUT_DC < 3.9 A 90 %
SEC to PRI Output Resistance
RPRI_COLD VSEC_DC = 12 V, IPRI_OUT_DC = 3.9 A, TINTERNAL = -40°C 2100 2400 2700
mΩRPRI_AMB VSEC_DC = 12 V, IPRI_OUT_DC = 3.9 A 2500 2700 2900
RPRI_HOT VSEC_DC = 12 V, IPRI_OUT_DC = 3.9 A, TINTERNAL = 100°C 2900 3150 3400
Primary Output Voltage Ripple VPRI_OUT_PP
CPRI_OUT_EXT = 0 µF, I PRI_OUT_DC = 3.9 A,
VSEC_DC = 12 V, 20 MHz BW 6250 mV
TINTERNAL ≤ 100ºC 9600
Electrical Specifications (Cont.)
Specifications apply over all line and load conditions, unless otherwise noted; Boldface specifications apply over the temperature range of -40 °C ≤ TINTERNAL
≤ 125 °C (T-Grade); All other specifications are at TINTERNAL = 25 ºC unless otherwise noted.
BCM®Bus Converter Rev 1.5 vicorpower.com
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BCM384x120y1K5ACz
Attribute Symbol Conditions / Notes Min Typ Max Unit
Protection SECONDARY to PRIMARY (Reverse Direction)
Secondary Overvoltage Lockout
Threshold VSEC_OVLO+ Module latched shutdown with VPRI_DC < VPRI_UVLO-_R 13.1 13.6 14.1 V
Secondary Overvoltage Lockout
Response Time tPRI_OVLO 100 µs
Secondary Undervoltage Lockout
Threshold VSEC_UVLO- Module latched shutdown with VPRI_DC < VPRI_UVLO-_R 3.4 3.75 4.1 V
Secondary Undervoltage Lockout
Response Time tSEC_UVLO 100 µs
Primary Undervoltage Lockout
Threshold VPRI_UVLO-_R
Applies only to reversilbe products in forward and in
reverse direction; IPRI_DC ≤ 20 while VPRI_UVLO-_R
< VPRI_DC < VPRI_MIN
110 120 130 V
Primary Undervoltage Recovery
Threshold VPRI_UVLO+_R Applies only to reversilbe products in forward and in
reverse direction; 120 130 150 V
Primary Undervoltage Lockout
Hysteresis VPRI_UVLO_HYST_R Applies only to reversilbe products in forward and in
reverse direction; 10 V
Primary Output Overcurrent Trip
Threshold IPRI_OUT_OCP Module latched shutdown with VPRI_DC < VPRI_UVLO-_R 4.2 5.3 6.6 A
Primary Output Overcurrent
Response Time Constant tPRI_OUT_OCP Effective internal RC filter 3 ms
Primary Short Circuit Protection Trip
Threshold IPRI_SCP Module latched shutdown with VPRI_DC < VPRI_UVLO-_R 5.8 A
Primary Short Circuit Protection
Response Time tPRI_SCP 1 µs
Electrical Specifications (Cont.)
Specifications apply over all line and load conditions, unless otherwise noted; Boldface specifications apply over the temperature range of -40 °C ≤ TINTERNAL
≤ 125 °C (T-Grade); All other specifications are at TINTERNAL = 25 ºC unless otherwise noted.
BCM®Bus Converter Rev 1.5 vicorpower.com
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BCM384x120y1K5ACz
65
80
95
110
125
140
155
170
185
260275290305320335350365380395410
Secondary Output Current (A)
Primary Input Voltage (V)
ISEC_OUT_DC ISEC_OUT_PULSE
Secondary Output Power (W)
Primary Input Voltage (V)
750
900
1050
1200
1350
1500
1650
1800
1950
2100
260275290305320335350365380395410
PSEC_OUT_DC PSEC_OUT_PULSE
Figure 1 — Specified thermal operating area
Figure 2 — Specified electrical operating area using rated RSEC_HOT
Secondary Output Capacitance
(% Rated CSEC_EXT_MAX)
Secondary Output Current (% I
SEC_OUT_DC
)
0
10
20
30
40
50
60
70
80
90
100
110
0 10 20 30 40 50 60 70 80 90 100 110
Primary/Secondary
Output Power (W)
Case Temperature (°C)
0
200
400
600
800
1000
1200
1400
1600
1800
35 45 55 65 75 85 95 105 115 125
Top only at temperature
Leads at temperature
Top and leads at
temperature
Top, leads, & belly at
temperature
Figure 3 — Specified Primary start-up into load current and external capacitance
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BCM384x120y1K5ACz
Signal Characteristics
Specifications apply over all line, load conditions, unless otherwise noted; Boldface specifications apply over the temperature range of -40 °C ≤ TINTERNAL
≤ 125 °C (T-Grade); All other specifications are at TINTERNAL = 25 ºC unless otherwise noted.
Temperature Monitor
• The TM pin is a standard analog I/O configured as an output from an internal µC.
• The TM pin monitors the internal temperature of the controller IC within an accuracy of ±5°C.
• µC 250 kHz PWM output internally pulled high to 3.3 V.
SIGNAL TYPE STATE ATTRIBUTE SYMBOL CONDITIONS / NOTES MIN TYP MAX UNIT
DIGITAL
OUTPUT
Startup Powertrain active to TM
time tTM 100 µs
Regular
Operation
TM Duty Cycle TMPWM 18.18 68.18 %
TM Current ITM 4 mA
Recommended External filtering
TM Capacitance (External) CTM_EXT Recommended External filtering 0.01 µF
TM Resistance (External) RTM_EXT Recommended External filtering 1 kΩ
Specifications using recommended filter
TM Gain ATM 10 mV / °C
TM Voltage Reference VTM_AMB 1.27 V
TM Voltage Ripple VTM_PP
RTM_EXT = 1 K Ohm, CTM_EXT = 0.01 uF, VPRI_DC
= 384 V, ISEC_DC = 125 A 28 mV
TINTERNAL ≤ 100ºC 40
Enable / Disable Control
• The EN pin is a standard analog I/O configured as an input to an internal µC.
• It is internally pulled high to 3.3 V.
• When held low the BCM internal bias will be disabled and the powertrain will be inactive.
• In an array of BCMs, EN pins should be interconnected to synchronize startup and permit startup into full load conditions.
SIGNAL TYPE STATE ATTRIBUTE SYMBOL CONDITIONS / NOTES MIN TYP MAX UNIT
ANALOG
INPUT
Startup EN to Powertrain active
time tEN_START VPRI_DC > VPRI_UVLO+, EN held low both
conditions satisfied for T > tPRI_UVLO+_DELAY 250 µs
Regular
Operation
EN Voltage Threshold VEN_TH 2.3 V
EN Resistance (Internal) REN_INT Internal pull up resistor 1.5 kΩ
EN Disable Threshold VEN_DISABLE_TH 1 V
BCM®Bus Converter Rev 1.5 vicorpower.com
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BCM384x120y1K5ACz
Auxiliary Voltage Source
• The VAUX pin is a standard analog I/O configured as an output from an internal µC.
• VAUX is internally connected to µC output as internally pulled high to a 3.3 V regulator with 2% tolerance, a 1% resistor of 1.5 kΩ.
• VAUX can be used as a "Ready to process full power" flag. This pin transitions VAUX voltage after a 2 ms delay from the start of powertrain activating,
signaling the end of softstart.
• VAUX can be used as "Fault flag". This pin is pulled low internally when a fault protection is detected.
SIGNAL TYPE STATE ATTRIBUTE SYMBOL CONDITIONS / NOTES MIN TYP MAX UNIT
ANALOG
OUTPUT
Startup Powertrain active to VAUX
time tVAUX Powertrain active to VAUX High 2 ms
Regular
Operation
VAUX Voltage VVAUX 2.8 3.3 V
VAUX Available Current IVAUX 4 mA
VAUX Voltage Ripple VVAUX_PP
50 mV
TINTERNAL ≤ 100ºC 100
VAUX Capacitance
(External) CVAUX_EXT 0.01 µF
VAUX Resistance (External) RVAUX_EXT VPRI_DC < VµC_ACTIVE 1.5 kΩ
Fault VAUX Fault Response Time tVAUX_FR From fault to VVAUX = 2.8 V, CVAUX = 0 pF 10 µs
Signal Characteristics (Cont.)
Specifications apply over all line, load conditions, unless otherwise noted; Boldface specifications apply over the temperature range of -40 °C ≤ TINTERNAL
≤ 125 °C (T-Grade); All other specifications are at TINTERNAL = 25 ºC unless otherwise noted.
BCM®Bus Converter Rev 1.5 vicorpower.com
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BCM384x120y1K5ACz
BCM Module Timing diagram
EN
TM
+VPRI
BIDIR
INPUT
+VSEC
OUTPUT
VPRI_DCINPUT TURN-ON
SECONDARY OUTPUT
TURN-ON
PRIMARY INPUT OVER
VOLTAGE
VPRI_DCINPUT RESTART
ENABLE PULLED LOW
ENABLE PULLED HIGH
SHORT CIRCUIT EVENT
PRIMARY INPUT VOLTAGE
TURN-OFF
OUTPUT
OUTPUT
VAUX
EN & VAUX INTERNAL Pull-up
STARTUP OVER VOLTAGE ENABLE CONTROL
OVER CURRENT
SHUTDOWN
µc INITIALIZE
VPRI_OVLO-
VPRI_OVLO+
VPRI_UVLO+
VµC_ACTIVE
VNOM
VPRI_UVLO-
tSEC_OUT_SCP
tPRI_UVLO+_DELAY
tVAUX tAUTO-RESTART
>
tPRI_UVLO+_DELAY
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BCM384x120y1K5ACz
FAULT
SEQUENCE
TM Low
EN High
VAUX Low
Powertrain Stopped
VμC_ACTIVE < VPRI_DC < VPRI_UVLO+
VPRI_DC > VPRI_UVLO+
tPRI_UVLO+_DELAY
expired
ONE TIME DELAY
INITIAL STARTUP
Fault
Auto-
recovery
ENABLE falling edge,
or OTP detected
Input OVLO or UVLO,
Output OCP,
or UTP detected
ENABLE falling edge,
or OTP detected
Input OVLO or UVLO,
Output OCP,
or UTP detected
Short Circuit detected
Application
of input voltage to V
PRI_DC
SUSTAINED
OPERATION
TM PWM
EN High
VAUX High
Powertrain Active
STARTUP SEQUENCE
TM Low
EN High
VAUX Low
Powertrain Stopped
STANDBY SEQUENCE
TM Low
EN High
VAUX Low
Powertrain Stopped
High Level Functional State Diagram
Conditions that cause state transitions are shown along arrows. Sub-sequence activities listed inside the state bubbles.
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BCM384x120y1K5ACz
Application Characteristics
Product is mounted and temperature controlled via top side cold plate, unless otherwise noted. All data presented in this section are collected data form
primary sourced units processing power in forward direction.See associated figures for general trend data.
PRI to SEC, Power Dissipation (W)
Primary Input Voltage (V)
- 40°C 25°C 90°C
TTOP SURFACE CASE:
4
6
8
10
12
14
16
18
20
260277293310327343360377393410
Case Temperature (ºC)
260 V 384 V 410 V
PRI to SEC, Full Load Efficiency (%)
VPRI:
95
96
97
98
-40-200 20406080100
PRI to SEC, Efficiency (%)
Secondary Output Current (A)
260 V 384 V 410 V
VPRI :
0
8
16
24
32
40
48
56
64
72
80
88
87
88
89
90
91
92
93
94
95
96
97
98
0.0 12.5 25.0 37.5 50.0 62.5 75.0 87.5 100.0 112.5 125.0
η
PD
PRI to SEC, Power Dissipation
Figure 4 — No load power dissipation vs. VPRI_DC Figure 5 — Full load efficiency vs. temperature; VPRI_DC
Figure 6 — Efficiency and power dissipation at TCASE = -40 °C
PRI to SEC, Efficiency (%)
Secondary Output Current (A)
260 V 384 V 410 V
VPRI :
0
8
16
24
32
40
48
56
64
72
80
88
87
88
89
90
91
92
93
94
95
96
97
98
0.0 12.5 25.0 37.5 50.0 62.5 75.0 87.5 100.0 112.5 125.0
η
PD
PRI to SEC, Power Dissipation
Secondary Output Current (A)
260 V 384 V 410 V
VPRI:
PRI to SEC, Efficiency (%)
0
8
16
24
32
40
48
56
64
72
80
88
87
88
89
90
91
92
93
94
95
96
97
98
0.0 12.5 25.0 37.5 50.0 62.5 75.0 87.5 100.0 112.5 125.0
η
PD
PRI to SEC, Power Dissipation
Figure 7 — Efficiency and power dissipation at TCASE = 25 °C
Case Temperature (°C)
125 AISEC_OUT:
0
1
2
3
-40 -20 0 20 40 60 80 100
PRI to SEC, Output Resistance (mΩ)
Figure 8 — Efficiency and power dissipation at TCASE = 90 °C Figure 9 — RSEC vs. temperature; Nominal VPRI_DC
ISEC_DC = 100 A at TCASE = 90 °C
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Figure 12 — 0 A– 125 A transient response:
CPRI_IN_EXT = 10 µF, no external CSEC_OUT_EXT
Figure 11 — Full load ripple, 10 µF CPRI_IN_EXT; No external
CSEC_OUT_EXT.Board mounted module, scope setting :
20 MHz analog BW
Secondary Output Current (A)
384 V
VPRI:
0
50
100
150
200
250
300
350
0.0 12.5 25.0 37.5 50.0 62.5 75.0 87.5 100.0 112.5 125.0
Secondary Output Voltage Ripple (mV)
Figure 10 — VSEC_OUT_PP vs. ISEC_DC ; No external CSEC_OUT_EXT.Board
mounted module, scope setting : 20 MHz analog BW
Figure 13 — 125 A – 0 A transient response:
CPRI_IN_EXT = 10 µF, no external CSEC_OUT_EXT
Figure 14 — Start up from application of VPRI_DC= 384 V, 50 % IOUT,
100% CSEC_OUT_EXT
Figure 15 — Start up from application of EN with pre-applied
VPRI_DC = 384 V, 50 % ISEC_DC, 100% CSEC_OUT_EXT
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General Characteristics
Specifications apply over all line, load conditions, unless otherwise noted; Boldface specifications apply over the temperature range of -40 °C ≤ TINTERNAL
≤ 125 °C (T-Grade); All other specifications are at TINTERNAL = 25 ºC unless otherwise noted.
Attribute Symbol Conditions / Notes Min Typ Max Unit
Mechanical
Length L 60.87 / [2.396] 61.00 / [2.402] 61.13 / [2.407] mm/[in]
Width W 24.76 / [0.975] 25.14 / [0.990] 25.52 / [1.005] mm/[in]
Height H 7.21 / [0.284] 7.26 / [0.286] 7.31 / [0.288] mm/[in]
Volume Vol Without Heatsink 11.13 / [0.679] cm3/[in3]
Weight W 41 / [1.45] g/[oz]
Lead finish
Nickel 0.51 2.03
µmPalladium 0.02 0.15
Gold 0.003 0.051
Thermal
Operating Temperature TINTERNAL
BCM384T120P1K5AC0 (T-Grade)
BCM384T120P1K5ACR (T-Grade) -40 125 °C
BCM384M120P1K5AC0 (M-Grade)
BCM384M120P1K5ACR (M-Grade) -55 125 °C
Thermal Resistance Top Side ΦINT-TOP
Estimated thermal resistance to maximum
temperature internal component from
isothermal top
1.14 °C/W
Thermal Resistance Leads ΦINT-LEADS
Estimated thermal resistance to
maximum temperature internal
component from isothermal leads
1.35 °C/W
Thermal Resistance Bottom Side ΦINT-BOTTOM
Estimated thermal resistance to
maximum temperature internal
component from isothermal bottom
1.07 °C/W
Thermal Capacity 34 Ws/°C
Assembly
Storage temperature
BCM384T120P1K5AC0 (T-Grade)
BCM384T120P1K5ACR (T-Grade) -55 125 °C
BCM384M120P1K5AC0 (M-Grade)
BCM384M120P1K5ACR (M-Grade) -65 125 °C
ESD Withstand ESDHBM Human Body Model, "ESDA / JEDEC JDS-001-2012" Class I-C (1kV to < 2 kV)
ESDCDM Charge Device Model, "JESD 22-C101-E" Class II (200V to < 500V)
BCM®Bus Converter Rev 1.5 vicorpower.com
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[1] Product is not intended for reflow solder attach.
General Characteristics
Specifications apply over all line, load conditions, unless otherwise noted; Boldface specifications apply over the temperature range of -40 °C ≤ TINTERNAL
≤ 125 °C (T-Grade); All other specifications are at TINTERNAL = 25 ºC unless otherwise noted.
Soldering[1]
Peak Temperature Top Case 135 °C
Safety
Isolation voltage / Dielectric test VHIPOT
PRIMARY to SECONDARY 4,242
VDC
PRIMARY to CASE 2,121
SECONDARY to CASE 2,121
Isolation Capacitance CPRI_SEC Unpowered Unit 620 780 940 pF
Insulation Resistance RPRI_SEC At 500 Vdc 10 MΩ
MTBF
MIL-HDBK-217Plus Parts Count - 25°C
Ground Benign, Stationary, Indoors /
Computer
2.31 MHrs
Telcordia Issue 2 - Method I Case III; 25°C
Ground Benign, Controlled 3.41 MHrs
Agency Approvals / Standards
cTUVus "EN 60950-1"
cURus "UL 60950-1"
CE Marked for Low Voltage Directive and RoHS Recast Directive, as applicable
BCM®Bus Converter Rev 1.5 vicorpower.com
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BCM384x120y1K5ACz
C01
C02
Q01
C03
C04
C05
C06
C07
C08
C09
C10
L01
Current Flow detection
+ Forward IIN sense
IPRI_DC
Startup
Circuit
+VPRI
/4
SEPIC EN
Cr
COUT
+VSEC
-VSEC
+VPRI
-VPRI
EN
TM PWM
TM
EN
VAUX
Differential Current
Sensing
Half-Bridge Synchronous
Rectification
Primary Stage
Fast Current
Limit
Analog Controller
Digital Controller
SEPIC
Cntrl On/Off
Temperature
Sensor
Q02
Q03
Q04
Q05
Q06
Q07
Q08
Lr
Secondary Stage
Q09
+Vcc
-Vcc
3.3v
Linear
Regulator
+VPRI
/4
( +VPRI
/4 ) - X
Slow Current
Limit
Modulator
Primary and
Secondary Gate
Drive Transformer
1.5 kΩ
1.5 kΩ
Soft-Start
VAUX
Over-Temp
Under-Temp
Over Voltage
UnderVoltage
Startup /
Re-start Delay
Q10
BCM Module Block Diagram
The Sine Amplitude Converter (SAC™) uses a high frequency resonant
tank to move energy from Primary to secondary and vice versa. (The
resonant tank is formed by Cr and leakage inductance Lr in the power
transformer windings as shown in the BCM module Block Diagram).
The resonant LC tank, operated at high frequency, is amplitude
modulated as a function of input voltage and output current. A small
amount of capacitance embedded in the primary and secondary stages
of the module is sucient for full functionality and is key to achieving
high power density.
The BCM384x120y1K5ACz SAC can be simplified into the preceeding
model.
At no load:
VSEC = VPRI • K (1)
K represents the “turns ratio” of the SAC.
Rearranging Eq (1):
K= VSEC (2)
VPRI
In the presence of load, VOUT is represented by:
VSEC = VPRI • K – ISEC • RSEC (3)
and IOUT is represented by:
ISEC = IPRI –I
PRI_Q (4)
K
ROUT represents the impedance of the SAC, and is a function of the
RDSON of the input and output MOSFETs and the winding resistance of
the power transformer. IQrepresents the quiescent current of the SAC
control, gate drive circuitry, and core losses.
The use of DC voltage transformation provides additional interesting
attributes. Assuming that RSEC = 0 Ω and IPRI_Q = 0 A, Eq. (3) now
becomes Eq. (1) and is essentially load independent, resistor R is now
placed in series with VIN.
The relationship between VPRI and VSEC becomes:
VSEC = (VPRI –I
PRI •RIN) •K (5)
Substituting the simplified version of Eq. (4)
(IPRI_Q is assumed = 0 A) into Eq. (5) yields:
VSEC = VPRI •K – ISEC •RIN •K2(6)
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+
–
+
–
V
OUT
C
OUT
V
IN
V•I
K
+
–
+
–
C
IN
I
OUT
RC
OUT
I
Q
R
OUT
RC
IN
31 mA
1/32 • ISEC 1/32 • VPRI
CPRI_INT_ESR
21.5 mΩ
0.124 nH
122 mΩ
208 µF
IPRI_Q
LPRI_IN_LEADS = 7 nH ISEC
VPRI
R
SAC
K = 1/32
Vin
Vout
+
–
VPRI
VSEC
RIN
SAC™
K = 1/32
Figure 17 — K = 1/32 Sine Amplitude Converter
with series input resistor
Figure 16 — BCM module AC model
CSEC_INT
LSEC_OUT_LEADS = 0.64 nH
LPRI_INT = 0.56 µH
CPRI_INT
0.37 µF
1.85 mΩ
RSEC
CSEC_INT_ESR
53 µΩ
VSEC
Sine Amplitude Converter™ Point of Load Conversion
This is similar in form to Eq. (3), where RSEC is used to represent the
characteristic impedance of the SAC™. However, in this case a real R on
the primary side of the SAC is eectively scaled by K2with respect
to the secondary.
Assuming thatR=1Ω,theeective R as seen from the secondary side is 1
mΩ,withK= 1/32 .
A similar exercise should be performed with the additon of a capacitor
or shunt impedance at the primary input to the SAC. A switch in series
with VPRI is added to the circuit. This is depicted in Figure 18.
A change in VPRI with the switch closed would result in a change in
capacitor current according to the following equation:
IC(t) = C dVPRI (7)
dt
Assume that with the capacitor charged to VPRI, the switch is opened
and the capacitor is discharged through the idealized SAC. In this case,
IC=I
SEC •K (8)
substituting Eq. (1) and (8) into Eq. (7) reveals:
ISEC =C•dISEC (9)
K2dt
The equation in terms of the output has yielded a K2scaling factor for
C, specified in the denominator of the equation.
A K factor less than unity results in an eectively larger capacitance on
the secondary output when expressed in terms of the input. With a
K= 1/32 as shown in Figure 18, C=1 μF would appear as C= 1024 μF
when viewed from the secondary.
Low impedance is a key requirement for powering a high-current, low-
voltage load eciently. A switching regulation stage should have
minimal impedance while simultaneously providing appropriate
filtering for any switched current. The use of a SAC between the
regulation stage and the point of load provides a dual benefit of scaling
down series impedance leading back to the source and scaling up shunt
capacitance or energy storage as a function of its K factor squared.
However, the benefits are not useful if the series impedance of the SAC
is too high. The impedance of the SAC must be low, i.e. well beyond the
crossover frequency of the system.
A solution for keeping the impedance of the SAC low involves
switching at a high frequency. This enables small magnetic components
because magnetizing currents remain low. Small magnetics mean small
path lengths for turns. Use of low loss core material at high frequencies
also reduces core losses.
The two main terms of power loss in the BCM module are:
nNo load power dissipation (PPRI_NL): defined as the power
used to power up the module with an enabled powertrain
at no load.
nResistive loss (RSEC): refers to the power loss across
the BCM® module modeled as pure resistive impedance.
PDISSIPATED= PPRI_NL + PRSEC (10)
Therefore,
PSEC_OUT = PPRI_IN –P
DISSIPATED = PRI_IN –P
PRI_NL –P
RSEC (11)
The above relations can be combined to calculate the overall module
eciency:
h
=
PSEC_OUT =PPRI_IN –P
PRI_NL –P
RSEC (12)
PIN PIN
=VPRI •IPRI –P
PRI_NL –(I
SEC)2•RSEC
VIN •IIN
=1 –
(
PPRI_NL + (ISEC)2•RSEC
)
VPRI •IPRI
C
S
SAC
K = 1/32
Vin
Vout
+
–
VPRI
VSEC
C
SAC™
K = 1/32
Figure 18 — Sine Amplitude Converter with input capacitor
S
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Input and Output Filter Design
A major advantage of SAC™ systems versus conventional PWM
converters is that the transformer based SAC does not require external
filtering to function properly. The resonant LC tank, operated at
extreme high frequency, is amplitude modulated as a function of input
voltage and output current and eciently transfers charge through the
isolation transformer. A small amount of capacitance embedded in the
primary and secondary stages of the module is sucient for full
functionality and is key to achieving power density.
This paradigm shi requires system design to carefully evaluate
external filters in order to:
nGuarantee low source impedance:
To take full advantage of the BCM module’s dynamic
response, the impedance presented to its input terminals
must be low from DC to approximately 5 MHz. The
connection of the bus converter module to its power
source should be implemented with minimal distribution
inductance. If the interconnect inductance exceeds
100 nH, the input should be bypassed with a RC damper
to retain low source impedance and stable operation. With
an interconnect inductance of 200 nH, the RC damper
may be as high as 1 μF in series with 0.3 Ω. A single
electrolytic or equivalent low-Q capacitor may be used in
place of the series RC bypass.
nFurther reduce input and/or output voltage ripple without
sacrificing dynamic response:
Given the wide bandwidth of the module, the source
response is generally the limiting factor in the overall
system response. Anomalies in the response of the source
will appear at the output of the module multiplied by its
K factor.
nProtect the module from overvoltage transients imposed
by the system that would exceed maximum ratings and
induce stresses:
The module primary/secondary voltage ranges shall not be
exceeded. An internal overvoltage lockout function
prevents operation outside of the normal operating input
range. Even when disabled, the powertrain is exposed
to the applied voltage and power MOSFETs must
withstand it.
Total load capacitance at the output of the BCM module shall not
exceed the specified maximum. Owing to the wide bandwidth and low
output impedance of the module, low-frequency bypass capacitance
and significant energy storage may be more densely and eciently
provided by adding capacitance at the input of the module. At
frequencies <500 kHz the module appears as an impedance of RSEC
between the source and load.
Within this frequency range, capacitance at the input appears as
eective capacitance on the output per the relationship
defined in Eq. (13).
CSEC_EXT =CPRI_EXT (13)
K2
This enables a reduction in the size and number of capacitors used in a
typical system.
Thermal Considerations
The ChiP package provides a high degree of flexibility in that it presents
three pathways to remove heat from internal power dissipating
components. Heat may be removed from the top surface, the bottom
surface and the leads. The extent to which these three surfaces are
cooled is a key component for determining the maximum power that is
available from a ChiP, as can be seen from Figure 1.
Since the ChiP has a maximum internal temperature rating, it is
necessary to estimate this internal temperature based on a real thermal
solution. Given that there are three pathways to remove heat from the
ChiP, it is helpful to simplify the thermal solution into a roughly
equivalent circuit where power dissipation is modeled as a current
source, isothermal surface temperatures are represented as voltage
sources and the thermal resistances are represented as resistors. Figure
19 shows the “thermal circuit” for a VI Chip® BCM module 2361 in an
application where the top, bottom, and leads are cooled. In this case,
the BCM power dissipation is PDTOTAL and the three surface
temperatures are represented as TCASE_TOP, TCASE_BOTTOM, and TLEADS. This
thermal system can now be very easily analyzed using a SPICE
simulator with simple resistors, voltage sources, and a current source.
The results of the simulation would provide an estimate of heat flow
through the various pathways as well as internal temperature.
Alternatively, equations can be written around this circuit and
analyzed algebraically:
TINT – PD1 • 1.24 = TCASE_TOP
TINT – PD2 • 1.24 = TCASE_BOTTOM
TINT – PD3 • 7 = TLEADS
PDTOTAL = PD1+ PD2+ PD3
Where TINT represents the internal temperature and PD1, PD2, and PD3
represent the heat flow through the top side, bottom side, and leads
respectively.
+
–
+
–
+
–
MAX INTERNAL TEMP
TCASE_BOTTOM(°C) TLEADS(°C) TCASE_TOP(°C)
Power Dissipation (W)
Thermal Resistance Top
Thermal Resistance Bottom Thermal Resistance Leads
+
–
+
–
MAX INTERNAL TEMP
TCASE_BOTTOM(°C) TLEADS(°C) TCASE_TOP(°C)
Power Dissipation (W)
Thermal Resistance Top
Thermal Resistance Bottom Thermal Resistance Leads
Figure 19 — Top case, Bottom case and leads thermal model
Figure 20 — Top case and leads thermal model
1.14 °C / W
1.07 °C / W 1.35 °C / W
1.14 °C / W
1.07 °C / W 1.35 °C / W
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Figure 20 shows a scenario where there is no bottom side cooling. In
this case, the heat flow path to the bottom is le open and the
equations now simplify to:
TINT – PD1 • 1.24 = TCASE_TOP
TINT – PD3 • 7 = TLEADS
PDTOTAL = PD1+ PD3
Figure 21 shows a scenario where there is no bottom side and leads
cooling. In this case, the heat flow path to the bottom is le open and
the equations now simplify to:
TINT – PD1 • 1.24 = TCASE_TOP
PDTOTAL = PD1
Please note that Vicor has a suite of online tools, including a simulator
and thermal estimator which greatly simplify the task of determining
whether or not a BCM thermal configuration is valid for a given
condition. These tools can be found at:
http://www.vicorpower.com/powerbench.
Current Sharing
The performance of the SAC™ topology is based on ecient transfer of
energy through a transformer without the need of closed loop control.
For this reason, the transfer characteristic can be approximated by an
ideal transformer with a positive temperature coecient series
resistance.
This type of characteristic is close to the impedance characteristic of a
DC power distribution system both in dynamic (AC) behavior and for
steady state (DC) operation.
When multiple BCM modules of a given part number are connected in
an array they will inherently share the load current according to the
equivalent impedance divider that the system implements from the
power source to the point of load.
Some general recommendations to achieve matched array impedances
include:
nDedicate common copper planes within the PCB
to deliver and return the current to the modules.
nProvide as symmetric a PCB layout as possible among modules
nAn input filter is required for an array of BCMs in order to
prevent circulating currents.
For further details see AN:016 Using BCM Bus Converters
in High Power Arrays.
Fuse Selection
In order to provide flexibility in configuring power systems
VI Chip® modules are not internally fused. Input line fusing
of VI Chip products is recommended at system level to provide thermal
protection in case of catastrophic failure.
The fuse shall be selected by closely matching system
requirements with the following characteristics:
nCurrent rating
(usually greater than maximum current of BCM module)
nMaximum voltage rating
(usually greater than the maximum possible input voltage)
nAmbient temperature
nNominal melting I2t
nRecommend fuse: ≤ 5 A Bussmann PC-Tron
Reverse Operation
BCM modules are capable of reverse power operation. Once the unit is
started, energy will be transferred from secondary back to the primary
whenever the secondary voltage exceeds VPRI • K. The module will
continue operation in this fashion for as long as no faults occur.
Transient operation in reverse is expected in cases where there is
significant energy storage on the output and transient voltages appear
on the input.
The BCM384T120P1K5ACR and BCM384M120P1K5ACR are both
qualified for continuous operation in reverse power condition. A
primary voltage of VPRI_DC > VPRI_UVLO+_R must be applied first allowing
primary reference controller and power train to start. Continuous
operation in reverse is then possible aer a successful startup.
BCM
®
1
R
0_1
Z
IN_EQ1
Z
OUT_EQ1
Z
OUT_EQ2
V
SEC
Z
OUT_EQn
Z
IN_EQ2
Z
IN_EQn
R
0_2
R
0_n
BCM
®
2
BCM
®
n
Load
DC
V
PRI
+
Figure 22 — BCM module array
+
–
MAX INTERNAL TEMP
TCASE_BOTTOM(°C) TLEADS(°C) TCASE_TOP(°C)
Power Dissipation (W)
Thermal Resistance Top
Thermal Resistance Bottom Thermal Resistance Leads
Figure 21 — Top case thermal model
1.14 °C / W
1.07 °C / W 1.35 °C / W
BCM®Bus Converter Rev 1.5 vicorpower.com
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BCM384x120y1K5ACz
BCM Module Through Hole Package Mechanical Drawing and Recommended Land Pattern
TM
EN
VAUX
+VPRI
+VPRI
+VPRI
+VPRI –VPRI
+VSEC
+VSEC
+VSEC
+VSEC
–VSEC1
–VSEC1
–VSEC1
–VSEC1
+VSEC
–VSEC2
–VSEC2
+VSEC
+VSEC
–VSEC2
–VSEC2
+VSEC
BCM®Bus Converter Rev 1.5 vicorpower.com
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Revision History
Revision Date Description Page Number(s)
1.4 05/15 Previous version of part #BCM380x475y1K2A30 n/a
1.5 07/21/15 Multiple updates. Additional new products. all
Analog HV BCM qualified for continuous reversible operations.
BCM®Bus Converter Rev 1.5 vicorpower.com
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Vicor’s comprehensive line of power solutions includes high density AC-DC and DC-DC modules and
accessory components, fully configurable AC-DC and DC-DC power supplies, and complete custom
power systems.
Information furnished by Vicor is believed to be accurate and reliable. However, no responsibility is assumed by Vicor for its use. Vicor makes no
representations or warranties with respect to the accuracy or completeness of the contents of this publication. Vicor reserves the right to make
changes to any products, specifications, and product descriptions at any time without notice. Information published by Vicor has been checked and
is believed to be accurate at the time it was printed; however, Vicor assumes no responsibility for inaccuracies. Testing and other quality controls are
used to the extent Vicor deems necessary to support Vicor’s product warranty. Except where mandated by government requirements, testing of all
parameters of each product is not necessarily performed.
Specifications are subject to change without notice.
Vicor’s Standard Terms and Conditions
All sales are subject to Vicor’s Standard Terms and Conditions of Sale, which are available on Vicor’s webpage or upon request.
Product Warranty
In Vicor’s standard terms and conditions of sale, Vicor warrants that its products are free from non-conformity to its Standard Specifications (the
“Express Limited Warranty”). This warranty is extended only to the original Buyer for the period expiring two (2) years after the date of shipment
and is not transferable.
UNLESS OTHERWISE EXPRESSLY STATED IN A WRITTEN SALES AGREEMENT SIGNED BY A DULY AUTHORIZED VICOR SIGNATORY, VICOR DISCLAIMS
ALL REPRESENTATIONS, LIABILITIES, AND WARRANTIES OF ANY KIND (WHETHER ARISING BY IMPLICATION OR BY OPERATION OF LAW) WITH
RESPECT TO THE PRODUCTS, INCLUDING, WITHOUT LIMITATION, ANY WARRANTIES OR REPRESENTATIONS AS TO MERCHANTABILITY, FITNESS FOR
PARTICULAR PURPOSE, INFRINGEMENT OF ANY PATENT, COPYRIGHT, OR OTHER INTELLECTUAL PROPERTY RIGHT, OR ANY OTHER MATTER.
This warranty does not extend to products subjected to misuse, accident, or improper application, maintenance, or storage. Vicor shall not be liable
for collateral or consequential damage. Vicor disclaims any and all liability arising out of the application or use of any product or circuit and assumes
no liability for applications assistance or buyer product design. Buyers are responsible for their products and applications using Vicor products and
components. Prior to using or distributing any products that include Vicor components, buyers should provide adequate design, testing and
operating safeguards.
Vicor will repair or replace defective products in accordance with its own best judgment. For service under this warranty, the buyer must contact
Vicor to obtain a Return Material Authorization (RMA) number and shipping instructions. Products returned without prior authorization will be
returned to the buyer. The buyer will pay all charges incurred in returning the product to the factory. Vicor will pay all reshipment charges if the
product was defective within the terms of this warranty.
Life Support Policy
VICOR’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS
PRIOR WRITTEN APPROVAL OF THE CHIEF EXECUTIVE OFFICER AND GENERAL COUNSEL OF VICOR CORPORATION. As used herein, life support
devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and whose failure to perform
when properly used in accordance with instructions for use provided in the labeling can be reasonably expected to result in a significant injury to the
user. A critical component is any component in a life support device or system whose failure to perform can be reasonably expected to cause the
failure of the life support device or system or to affect its safety or effectiveness. Per Vicor Terms and Conditions of Sale, the user of Vicor products
and components in life support applications assumes all risks of such use and indemnifies Vicor against all liability and damages.
Intellectual Property Notice
Vicor and its subsidiaries own Intellectual Property (including issued U.S. and pending patent applications) relating to the products described in this
data sheet. No license, whether express, implied, or arising by estoppel or otherwise, to any intellectual property rights is granted by this document.
Interested parties should contact Vicor's Intellectual Property Department.
The products described on this data sheet are protected by the following U.S. Patents Numbers:
6,911,848; 6,930,893; 6,934,166; 7,145,786; 7,782,639; 8,427,269 and for use under 6,975,098 and 6,984,965.
Vicor Corporation
25 Frontage Road
Andover, MA, USA 01810
Tel: 800-735-6200
Fax: 978-475-6715
email
Customer Service: custserv@vicorpower.com
Technical Support: apps@vicorpower.com
BCM384x120y1K5ACz