WS57C128FB HIGH SPEED 16K x 8 CMOS EPROM KEY FEATURES Standard EPROM Pinout DIP and Surface Mount Packaging Available Very Fast Access Time 35 ns Low Power Consumption EPI Processing Latch-up Immunity Up to 200 mA GENERAL DESCRIPTION The WS57C128FB is a High Performance 128K UV Erasable Electrically Programmable Read Only Memory. It is manufactured with an advanced CMOS technology which enables it to operate at Bipolar speeds while consuming only 90 mA. Two major features of the WS5/C128FB are its Low Power and High Speed. These features make it an ideal solution for applications which require fast access times, low power, and non-volatility. Typical applications include systems which do not utilize mass storage devices and/or are board space limited. The WS57C128FB is configured in the standard EPROM pinout which provides an easy upgrade path for systems which are currently using standard EPROMs. The EPROMsS are available in both 600 Mil DIP packages, and both J-leaded and leadless surface mount packages. MODE SELECTION PIN CONFIGURATION PINS |} ] | __ MODE PGM | CE | OE | Vpp | Vcc JOUTPUTS TOP VIEW CERDIP Read X | Vir | Vir [Voc | Yoo | Pout Output x | x |v lVvecly High Z V Disable IH | CC | *cc 9 Vpp [1 2810 Voc. Ayo 2 271] PGM Standb xX |v x |v Vv High Z A783 2601 Ars andby IH cc | Vcc g moa 25H] Ay Program Vv Vv Vv Vv V D As [5 2410 Ag 9 IL IL 1H_ | YpP | Yoo IN A Oe 23i1 aay Program A, 07 22{] OE Verify Vin | Vir | Vir | Ypp | Yoo | Pout aos 2111 Ayo A, 09 201] CE Program . Ag (10 191] Oo, Inhibit x VIH x Vpp Vec High Z Qo Cl 14 18 0 Og o, 0 12 170] Os X can be Vj or Vip. mei i O, 13 16[] O,4 0; Op 9 NG Oz 04 Os GND [] 14 151] 03 Oo PRODUCT SELECTION GUIDE PARAMETER WS57C128FB-35 | WS57C128FB-45 | WS57C128FB-55 | WS57C128FB-70 Address Access Time (Max) 35 ns 45 ns 55 ns 70 ns Chip Select Time (Max) 35 ns 45 ns 55 ns 70 ns Output Enable Time (Max) 20 ns 25 ns 25 ns 25 ns = | Return to Main MenuWS57C128FB ABSOLUTE MAXIMUM RATINGS* NOTICE: Stresses above those listed under "Absolute Maximum Storage Temperature..............::00cees 65to + 150C ; a Ratings" may cause permanent damage to the device. Voltage on any Pin with This is a stress rating only and functional operation of Respect to Ground ............0::::cceeeereeeeeeees 0.6V to +7V the device at these or any other conditions above Vpp with Respect to Ground............0...... 0.6V to + 13V those indicated in the operational sections of this ESD Protection ........0...0::cccccceecceeeceeeteeeteeseeeeeeees >2000V specification is not implied. Exposure to absolute maximum rating conditions for extended periods of OPERATING RANGE time may affect device reliability. RANGE TEMPERATURE Voc Commercial 0 to +70C +5V + 10% Industrial 40C to +85C +5V + 10% Military 55C to +125C +5V + 10% DC READ CHARACTERISTICS Over Operating Range with Vpp = Vec SYMBOL PARAMETER TEST CONDITIONS MIN MAX | UNITS Vit Input Low Voltage (Note 5) 0.1 0.8 Vv Vin Input High Voltage (Note 5) 2.0 Voc + 0.3 Vv Vo. Output Low Voltage lo. = 16 MA 0.4 Vv Vou Output High Voltage lon =-4 MA 2.4 V Ispi Voc Standby Current (CMOS) | (Notes 1 and 3) 500 yA Ispe Voc Standby Current (TTL) (Notes 2 and 3) 15 mA lect Voc Active Current (CMOS) (Notes 7 and 4) renal a0 WA Outputs Not Loaded Military 40 mA loce Voc Active Current (TTL) (Notes 2 and 4) a = a Outputs Not Loaded Military 60 mA Ipp Vpp Supply Current Vpp = Voc 100 YA Vpp Vpp Read Voltage Voc 0.4 Voc Vv li Input Leakage Current Vin = 5.5V or Gnd -10 10 yA llo Output Leakage Current Vout = 5.5 V or Gnd -10 10 HA NOTES: 1. CMOS inputs: GND + 0.3V or Vog + 0.3V. 4. Add 4 mA/MHz for A.C. power component. 2. TTL inputs: V\_ < 0.8V, Vi, 2 2.0V. 3. Add 1 mA/MHz for A.C. power component. 5. These are absolute voltages with respect to device ground pin and include all overshoots due to system and/or tester noise. Do not attempt to test these values without suitable equipment. AC READ CHARACTERISTICS Over Operating Range with Vpp = Voc PARAMETER SYMBOL |57C128FB-35 |57C128FB-45 | 57C128FB-55 | 57C128FB-70| ig MIN MAX MIN MAX MIN MAX MIN MAX Address to Output Delay tacc 35 45 55 70 CE to Output Delay tor 35 45 55 70 OE to Output Delay tor 20 25 25 25 ns Cuipu Disable or a : : : Address to Output Hold tou 0 0 0 0 3-8WS57C128FB AC READ TIMING DIAGRAM ADDRESSES VALID tace _ tou CE t toe ] tor OE L ~~ OUTPUTS ct VALID by >| tbr CAPACITANCE( T, = 25C, f = 1 MHz SYMBOL PARAMETER CONDITIONS TYP() MAX UNITS Cin Input Capacitance Vin = OV 4 6 pF Cout Output Capacitance Vout = OV 8 12 pF Cypp Vpp Capacitance Vpp=0V 18 25 pF NOTES: 6. This parameter is only sampled and is not 100% tested. 7. Typical values are for T, = 25C and nominal supply voltages. TEST LOAD (High Impedance Test Systems) A.C. TESTING INPUT/OUTPUT WAVEFORM 2.01 V D.U.T. 97.5 30 pF (INCLUDING SCOPE AND JIG L CAPACITANCE) 3.0 2.0 )) 2.0 > TEST < POINTS 0.0 0.8 ( 0.8 5 A.C. testing inputs are driven at 3.0 V for a logic "1" and 0.0 V for a logic "0." Timing measurements are made at 2.0 V fora logic "1" and 0.8 V for a logic "0". NOTE: 8. Provide adequate decoupling capacitance as close as possible to this device to achieve the published A.C. and D.C. parameters. A 0.1 microfarad capacitor in parallel with a 0.01 microfarad capacitor connected between Vcc and ground is recommended. Inadequate decoupling may result in access time degradation or other transient performance failures.WS57C128FB PROGRAMMING INFORMATION DC CHARACTERISTICS (T, = 25 + 5C, Voc = 6.25 V + 0.25 V, Vpp = 12.75 + 0.25 V) (lon = 4 MA) SYMBOLS PARAMETER MIN MAX UNITS , eon 0 Le IPP Proctamning Pulse (Cee PGM = V,,) 60 mA loc Voc Supply Current 30 mA Vor at Sma) During Verify 0.4 Vv Vou Output High Voltage During Verify oA Vv NOTE: 9. Voc must be applied either coincidentally or before Vpp and removed either coincidentally or after Vpp. 10. Vpp must not be greater than 13 volts including overshoot. During CE = PGM = V/,, Vpp must not be switched from 5 volts to 12.5 volts or vice-versa. 11. During power up the PGM pin must be brought high (2 V),,) either coincident with or before power is applied to Vpp. AC CHARACTERISTICS (1, = 25 45, Vog = 6.25 V + 0.25 V, Vpp = 12.75 + 0.25 V) SYMBOLS PARAMETER MIN TYP MAX UNITS tas Address Setup Time 2 Us tcEs Chip Enable Setup Time 2 Us tors Output Enable Setup Time 2 Us tos Data Setup Time 2 Us tay Address Hold Time 0 Us tou Data Hold Time 2 Us tor Chip Disable to Output Float Delay 0 130 ns tor Data Valid From Output Enable 130 ns tvs Vpp Setup Time 2 Us tow PGM Pulse Width 100 200 Us PROGRAMMING WAVEFORM ADDRESSES ADDRESS STABLE tas | _ DATA DATA IN STABLE DATA OUT tos > ton Vpp Vpp Vec tys | _ Vin CE ViL tces > Vin "-71 L PGM ViL tpw _ Vin OE ViL 3-10WS57C128FB ORDERING INFORMATION PART NUMBER SPEED PACKAGE PACKAGE TEMPERATURE MANUFACTURING (ns) TYPE DRAWING RANGE PROCEDURE WS57C128FB-35D 35 | 28PinCERDIP,0.6"| D2 Comm't Standard WS57C128FB-45D 45 | 28PinCERDIP,0.6"} D2 Comm! Standard WS57C128FB-45DMB | 45 | 28PinCERDIP,0.6"} D2 Military MIL-STD-883C WS57C128FB-45J 45 | 32 Pin PLDCC JA Comm't Standard WS57C128FB-45L 45 | 32PinCLDCC L3 Comm't Standard WS57C128FB-55CMB | 55 | 32 Pad CLLCC ce Military MIL-STD-883C WS57C128FB-55D 55 | 28PinCERDIP,0.6"} D2 Comm't Standard WS57C128FB-55DMB | 55 | 28PinCERDIP,0.6"} D2 Military MIL-STD-883C WS57C128FB-70D 70 |28PinCERDIP,0.6"} D2 Comm'l Standard WS57C128FB-70DM 70 |28PinCERDIP,0.6"} D2 Military Standard WS57C128FB-70DMB | 70 | 28PinCERDIP,0.6"} D2 Military MIL-STD-883C NOTE: 12. The actual part marking will not include the initials "WS." PROGRAMMING/ALGORITHMS/ERASURE/PROGRAMMERS REFER TO PAGE 5-1 The WS57C128FB is programmed using Algorithm D shown on page 5-9. 3-11 | Return to Main Menu