Universal Operational Amplifier
Single, Dual, Quad (MSOP/TSSOP)
Evaluation Module
With Shutdown
October 1999 Mixed-Signal Products
User’s Guide
SLOU055
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
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In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
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Copyright 1999, Texas Instruments Incorporated
iii
Chapter Title—Attribute Reference
Preface
Related Documentation From Texas Instruments
J
Amplifiers, Comparators, and Special Functions Data Book
(literature number SL YD01 1 and SL YD012). This data book contains
data sheets and other information on the TI operational amplifiers
that can be used with this evaluation module.
J
Operational Amplifier Supplement Data Book
(literature number
SLOD002). This data book contains data sheets and other
information on the TI operational amplifiers that can be used with this
evaluation module.
J
Power Management Products Data Book
(literature numbers
SLVD003, SLVD004, and SLVD005). This data book contains data
sheets and other information on the TI shunt regulators that can be
used with this evaluation module.
FCC Warning
This equipment is intended for use in a laboratory test environment only. It
generates, uses, and can radiate radio frequency energy and has not been
tested for compliance with the limits of computing devices pursuant to subpart
J of part 15 of FCC rules, which are designed to provide reasonable protection
against radio frequency interference. Operation of this equipment in other
environments may cause interference with radio communications, in which
case the user at his own expense will be required to take whatever measures
may be required to correct this interference.
Trademarks
TI is a trademark of Texas Instruments Incorporated.
PowerPAD is a trademark of Texas Instruments Incorporated.
iv
Running Title—Attribute Reference
v
Chapter Title—Attribute Reference
Contents
1 Introduction 1-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.1 Design Features 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Power Requirements 1-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Evaluation Module Layout 2-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.1 Physical Considerations 2-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Area 100 – Single Device SOIC 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 Area 200 – Dual Device MSOP PowerPAD 2-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.4 Area 300 – Quad Device TSSOP PowerPAD 2-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.5 General PowerPAD Design Considerations 2-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.6 General Power Dissipation Considerations 2-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.7 EVM Component Placement 2-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.8 EVM Board Layout 2-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Example Circuits 3-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1 Schematic Conventions 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 Inverting Amplifier 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 Non-Inverting Amplifier 3-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4 Differential Amplifier 3-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5 Sallen-Key Low-Pass Filter 3-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6 Sallen-Key High-Pass Filter 3-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7 Two Operational Amplifier Instrumentation Amplifier 3-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.8 Quad Operational Amplifier Instrumentation Amplifier 3-10. . . . . . . . . . . . . . . . . . . . . . . . . . .
Running Title—Attribute Reference
vi
Figures
2–1 Area 100 Schematic—Single Device, MSOP (8-pin) 2-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–2 Area 200 Schematic—Dual Device, MSOP PowerPAD (10-pin) 2-4. . . . . . . . . . . . . . . . . . . . .
2–3 Area 300 Schematic—Quad Device, TSSOP PowerPAD (16-pin) 2-6. . . . . . . . . . . . . . . . . . . .
2–4 Views of Thermally Enhanced DGN Package 2-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–5 PowerPAD PCB Etch and Via Pattern 2-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–6 Maximum Power Dissipation vs Free-Air Temperature 2-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–7 EVM Component Placement 2-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–8 EVM Board Layout—Top 2-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2–9 EVM Board Layout—Bottom 2-12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–1 Inverting Amplifier With Dual Supply Using Area 100 3-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3–2 Non-Inverting Amplifier With Single Supply Using Area 100 3-3. . . . . . . . . . . . . . . . . . . . . . . . .
3–3 Single Operational Amplifier Differential Amplifier With Single Supply Using Area 100 3-4. .
3–4 Sallen-Key Low-Pass Filter With Dual Supply Using Area 200 3-5. . . . . . . . . . . . . . . . . . . . . . .
3–5 Sallen-Key High-Pass Filter With Single Supply Using Area 200 3-7. . . . . . . . . . . . . . . . . . . . .
3–6 Two Operational Amplifier Instrumentation Amplifier With Single Supply Using Area 200 3-9
3–7 Quad Operational Amplifier Instrumentation Amplifier With Dual Supply Using Area 300 3-11
Table
2–1 Dissipation Rating Table 2-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1-1
Introduction
Introduction
This user ’s guide describes the universal operational amplifier single, dual,
quad (MSOP/TSSOP) evaluation module (EVM) with shutdown (SLOP247).
The EVM simplifies evaluation of Texas Instruments surface-mount op amps
with or without shutdown feature.
Topic Page
1.1 Design Features 1–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.2 Power Requirements 1–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 1
Design Features
1-2
Introduction
1.1 Design Features
The EVM board design allows many circuits to be constructed easily and
quickly. There are three circuit development areas on the board. Area 100 is
for a single operational amplifier (op amp), with or without shutdown. It also
features offset nulling pin pads and can use the MSOP PowerPAD package.
Area 200 is for a dual op amp, with shutdown. Like area 100, it uses the MSOP
PowerP AD package. Area 300 is for a quad op amp, with or without shutdown,
and is designed for the TSSOP PowerP AD package. Although all three areas
are designed for PowerPAD devices, non-PowerPAD packages will work on
the EVM PCB as well. A few possible circuits include:
-
Voltage follower
-
Noninverting amplifier
-
Inverting amplifier
-
Simple or algebraic summing amplifier
-
Difference amplifier
-
Current to voltage converter
-
Voltage to current converter
-
Integrator/low-pass filter
-
Differentiator/high-pass filter
-
Instrumentation amplifier
-
Sallen-Key filter
The EVM PCB is of two-layer construction, with a ground plane on the solder
side. Circuit performance should be comparable to final production designs.
1.2 Power Requirements
The devices and designs that are used dictate the input power requirements.
Three input terminals are provided for each area of the board:
Vx+ Positive input power for area x00 i.e., V1+ ⇒ area 100
GNDx Ground reference for area x00 i.e., GND2 ⇒ area 200
Vx– Negative input power for area x00 i.e., V3– ⇒ area 300
Each area has four bypass capacitors – two for the positive supply, and two
for the negative supply . Each supply should have a 1-µF to 10-µF capacitor for
low frequency bypassing and a 0.01-µF to 0.1-µF capacitor for high frequency
bypassing.
When using single-supply circuits, the negative supply is shorted to ground by
bridging C104 or C105 in area 100, C209 or C210 in area 200, or C311 or C312
in area 300. Power input is between Vx+ and GNDx. The voltage reference
circuitry is provided for single-supply applications that require a reference
voltage to be generated.
2-1
Evaluation Module Layout
Evaluation Module Layout
This chapter shows the universal operational amplifier single, dual, quad
(MSOP/TSSOP) evaluation module (EVM) with shutdown board layout,
schematics of each area, and describes the relationships between the three
areas.
Topic Page
2.1 Physical Consideration 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.2 Area 100 — Single Device MSOP 2–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.3 Area 200 — Dual Device MSOP PowerPAD 2–4. . . . . . . . . . . . . . . . . . . . . .
2.4 Area 300 — Quad Device TSSOP PowerPAD 2–5. . . . . . . . . . . . . . . . . . . .
2.5 General PowerPAD Design Considerations 2–7. . . . . . . . . . . . . . . . . . . . . .
2.6 General Power Dissipation Considerations 2–9. . . . . . . . . . . . . . . . . . . . . .
2.7 Component Placement 2–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.8 Board Layout 2–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Chapter 2
Physical Considerations
2-2
Evaluation Module Layout
2.1 Physical Considerations
The EVM board has three circuit development areas. Each area can be
separated from the others by breaking along the score lines. The circuit layout
in each area supports an op amp package, voltage reference, and ancillary
devices. The op amp package is unique to each area as described in the
following paragraphs. The voltage reference and supporting devices are the
same for all areas. Surface-mount or through-hole components can be used
for all capacitors and resistors on the board.
The voltage reference can be either surface-mount or through-hole. If surface
mount is desired, the TLV431ACDBV5 or TLV431AIDBV5 adjustable shunt
regulators can be used. If through hole is desired, the TLV431ACLP,
TLV431AILP, TL431CLP, TL431ACLP, TL431ILP or TL431AILP adjustable
shunt regulators can be used. Refer to Texas Instruments’
Power Supply
Circuits Data Book
(literature number SL VD002) for details on usage of these
shunt regulators.
Each passive component (resistor or capacitor) has a surface-mount 1206
footprint with through holes at 0.2″ spacing on the outside of the 1206 pads.
C105, C106, C107, C207, C208, C209, C312, C314, and C315 have a
surface-mount 1210 footprint with through holes at 0.2″ spacing on the outside
of the 1210 pads. Therefore, either surface-mount or through-hole parts can
be used. The potentiometer for the offset nulling feature in area 100 can also
be either a surface-mount or a through-hole unit.
Figures 2–1 through 2–3 show schematics for each of the board areas. The
schematics show all components that the board layout can accommodate.
These should only be used as reference, since not all components will be used
at any one time.
Physical Considerations
2-3
Evaluation Module Layout
2.2 Area 100—Single Device MSOP
Area 100 uses 1xx reference designators, and is compatible with a single op
amp, with or without shutdown, packaged as an 8-pin MSOP, with or without
PowerPAD. This surface-mount package is designated by a DGK
(non-PowerPAD) and DGN (PowerPAD) suffix in TI part numbers, as in
TxxxxCDGK, TxxxxIDGN, etc.
Offset nulling can be extremely important in some applications. The EVM
accommodates TI IC op amps that provide this feature. The input offset can
be adjusted by connecting a 100 kΩ potentiometer between terminals 1 and
5 of the device and connecting the wiper to VCC– via a resistor (R101) as
shown below. This resistor is used to fine tune the offset adjustment. For
example, when using the TLC070 or TLC071 device and a 100 kΩ nulling
potentiometer, the offset voltage adjustment is ±10 mV when R101 is 5.6 kΩ
and ±3 mV when R101 is 20 kΩ.
When using the non-shutdown version of the device, pin 8 of the IC is a no
connect.
Figure 2–1 shows the area 100 schematic.
Figure 2–1.Area 100 Schematic—Single Device, MSOP (8 pin)
C107 C108
C105 C104
V1+
V1–
V1+
GND1
V1–
Power Supply Bypass
+
–
14
3
2
V1+
V1–
R112
C109
R114 C110
R110
R109
R104
R103
R102
R105
C101
C102
OUT
A101–
A102–
A103+
A104+
U101 SD
C103
R106 A1 FLT
6
8
7
5
R101
R111
U102
R113
V oltage Reference
V1+ VREF1
R108
C106
V1–
R107
Physical Considerations
2-4
Evaluation Module Layout
2.3 Area 200—Dual Device MSOP PowerPAD
Area 200 uses 2xx reference designators, and is compatible with dual op
amps, with shutdown, packaged as a 10-pin MSOP PowerP AD. This package
is designated by a DGS (non-PowerPAD), and DGQ (PowerPAD) suffix in TI
part numbers, as in TxxxxCDGQ. When using a PowerPAD device, the
PowerPAD on the bottom of the package must be soldered to the PCB. If the
appropriate equipment for soldering the PowerPAD to the PCB is not available,
thermal grease can be used to improve the heat transfer into the PCB.
Figure 2–2 shows the area 200 schematic.
Figure 2–2.Area 200 Schematic—Dual Device, MSOP PowerPAD (10 pin)
B2/SD
C206 C207
C209 C210
V2+
V2–
V2+
GND2
V2–
Power Supply Bypass
+
–
10
1
4
3
2
V2+
V2–
R212
C215
R216 C211
R221
R220
R218
R219
R217
R215
C212
C213
A2OUT
1/2 Dual Op Amp
A201–
A202–
A203+
A204+
+
–
R206
C202
R207 C203
R204
R203
R205
R201
R202
R209
C204
C201
B2OUT
1/2 Dual Op Amp
B201–
B202–
B203+
B204+
U201a
U201b
9
7
8
C214
R214 A2 FLT
C205
R208 B2 FLT
A2/SD
5
6
R211
U202
R213
V oltage Reference
V2+ VREF2
R210
C208
Physical Considerations
2-5
Evaluation Module Layout
2.4 Area 300—Quad Device TSSOP PowerPAD
Area 300 uses 3xx reference designators, and is compatible with quad op
amps, with or without shutdown, packaged in a 16-pin TSSOP PowerPAD.
This surface-mount package is designated by a PW (non-PowerPAD) or a
PWP (PowerPAD) suffix in TI part numbers, as in TxxxxIPWP. When using a
PowerPAD device, the PowerPAD on the bottom of the package must be
soldered to the PCB. If the appropriate equipment for soldering the PowerPAD
to the PCB is not available, thermal grease can be used to improve the heat
transfer into the PCB.
When using the non-shutdown version of the device, ensure that the IC is
aligned at the top of the IC pad array—the last two PCB pads will be unused.
Figure 2–3 shows the area 300 schematic.
Physical Considerations
2-6
Evaluation Module Layout
Figure 2–3.Area 300 Schematic—Quad Device TSSOP PowerPAD (16 pin)
C313 C314
C311 C312
V3+
V3–
V3+
GND3
V3–
Power Supply Bypass +
–
4
1
13
3
2
V3+
V3–
R302
C301
R304 C302
R301
R303
R305
R306
R308
R307
C304
C303
A3 OUT
A301–
A302–
A303+
A304+
U301A
C305
R309 A3 FLT
AB3/SD
8
+
–7
5
6
R318
C308
R314 C310
R310
R312
R317
R313
R315
R311
C307
C309
B3 OUT
B301–
B302–
B303+
B304+ U301B
C306
R316 B3 FLT
+
–10
12
11
R325
C316
R323 C317
R323
R324
R326
R327
R329
R328
C318
C319
C3 OUT
C301–
C302–
C303+
C304+
U301C
C320
R330
CD3/SD
9
+
–16
14
15
R339
C321
R331 C324
R332
R333
R334
R335
R336
R337
C322
C325
D3 OUT
D301–
D302–
D303+
D304+ U301D
C323
R338
C3 FLT
D3 FLT
R320
U302
R319
V oltage Reference
V1+ VREF3
R321
C315
General PowerPAD Design Considerations
2-7
Evaluation Module Layout
2.5 General PowerPAD Design Considerations
The T exas Instruments thermally-enhanced DGN, DGQ, and PWP packages, which are members
of the PowerPAD family of packages. This package is constructed using a downset leadframe
upon which the die is mounted [see Figure 2–4(a) and Figure 2–4(b)]. This arrangement results
in the lead frame being exposed as a thermal pad on the underside of the package [see Figure
2–4(c)]. Because this thermal pad has direct thermal contact with the die, excellent thermal
performance can be achieved by providing a good thermal path away from the thermal pad.
The PowerPAD package allows for both assembly and thermal management in one
manufacturing operation. During the surface-mount solder operation (when the leads are being
soldered), the thermal pad can also be soldered to a copper area underneath the package.
Through the use of thermal paths within this copper area, heat can be conducted away from the
package into either a ground plane or other heat dissipating device.
The PowerPAD package represents a breakthrough in combining the small area and ease of
assembly of the surface mount with the, heretofore, awkward mechanical methods of heatsinking.
Figure 2–4.Views of Thermally Enhanced DGN Package
DIE
Side View (a)
End View (b) Bottom View (c)
DIE
Thermal
Pad
NOTE A: The thermal pad is electrically isolated from all terminals in the package.
Although there are many ways to properly heatsink this device, the following steps illustrate the
recommended approach.
1) Prepare the PCB with a top side etch pattern as shown in Figure 2–5.
There should be etch for the leads as well as etch for the thermal pad.
Figure 2–5.PowerPAD PCB Etch and Via Pattern
Thermal pad area:
68 mils x 70 mils with 5 vias
(Via diameter = 13 mils) 78 mils x 94 mils with 9 vias
(Via diameter = 13 mils)
Single or Dual
Quad
2) Place five holes (single or dual) or nine holes (quad) in the area of the
thermal pad. These holes should be 13 mils in diameter . Keep them small
so that solder wicking through the holes is not a problem during reflow.
3) Additional vias may be placed anywhere along the thermal plane outside
of the thermal pad area. This helps dissipate the heat generated by the IC.
These additional vias may be larger than the 13-mil diameter vias directly
under the thermal pad. They can be larger because they are not in the
thermal pad area to be soldered so that wicking is not a problem.
General PowerPAD Design Considerations
2-8
Evaluation Module Layout
4) Connect all holes to the internal ground plane.
5) When connecting these holes to the ground plane, do not use the typical
web or spoke via connection methodology . Web connections have a high
thermal resistance connection that is useful for slowing the heat transfer
during soldering operations. This makes the soldering of vias that have
plane connections easier. In this application, however, low thermal
resistance is desired for the most efficient heat transfer. Therefore, the
holes under the device package should make their connection to the
internal ground plane with a complete connection around the entire
circumference of the plated-through hole.
6) The top-side solder mask should leave the terminals of the package and
the thermal pad area with its five holes exposed. The bottom-side solder
mask should cover the five holes of the thermal pad area. This prevents
solder from being pulled away from the thermal pad area during the reflow
process.
7) Apply solder paste to the exposed thermal pad area and all of the IC
terminals.
8) With these preparatory steps in place, the IC is simply placed in position
and run through the solder reflow operation as any standard
surface-mount component. This results in a part that is properly installed.
Correct PCB layout and manufacturing techniques are critical for achieving
adequate transfer of heat away from the PowerPAD IC package. For more
general information on the PowerPAD package and its thermal characteristics,
see the Texas Instruments Technical Brief,
PowerPAD Thermally Enhanced
Package
(SLMA002).
General Power Dissipation Considerations
2-9
Evaluation Module Layout
2.6 General Power Dissipation Considerations
For a given θJA, the maximum power dissipation is shown in Figure 2–6 and is calculated by the
following formula:
PD
+ǒ
TMAX–TA
q
JA
Ǔ
Where: PD= Maximum power dissipation of Txxxx IC (watts)
TMAX= Absolute maximum junction temperature (150°C)
TA= Free-air temperature (°C)
θJA = θJC + θCA
θJC = Thermal coefficient from junction to case
θCA = Thermal coefficient from case to ambient air (°C/W)
Figure 2–6.Maximum Power Dissipation vs Free-Air Temperature
TJ = 150°C
4
3
2
0
–55 –25 5
Maximum Power Dissipation – W
5
6
MAXIMUM POWER DISSIPATION
vs
FREE-AIR TEMPERATURE
7
35
1
TA – Free-Air Temperature – °C
PWP Package
Low-K Test PCB
θJA = 29.7°C/W
DGN Package
Low-K Test PCB
θJA = 52.3°C/W
PDIP Package
Low-K Test PCB
θJA = 104°C/W
SOT -23 Package
Low-K Test PCB
θJA = 324°C/W
65 95 125
SOIC Package
Low-K Test PCB
θJA = 176°C/W
NOTE A: Results are with no air flow and using JEDEC Standard Low-K test PCB.
Table 2–1.Dissipation Rating Table
PACKAGE PowerPAD θJC
(°C/W) θJA
(°C/W) TA ≤ 25°C
POWER RATING
DGK (8) 54.23 259.96 424 mW
DGN (8) YES 4.7 52.7 2.37 W
DGS (10) 54.1 257.71 424 mW
DGQ (10) YES 4.7 52.3 2.39 W
PW (16) 28.7 161.4 700 mW
PWP (16) YES 2.07 29.7 4.21 W
EVM Component Placement
2-10
Evaluation Module Layout
2.7 EVM Component Placement
Figure 2–7 shows component placement for the EVM board.
Figure 2–7.EVM Component Placement
EVM Board Layout
2-11
Evaluation Module Layout
2.8 EVM Board Layout
Figures 2–8 and 2–9 show the EVM top and bottom board layouts,
respectively.
Figure 2–8.EVM Board Layout—Top
EVM Board Layout
2-12
Evaluation Module Layout
Figure 2–9.EVM Board Layout—Bottom
3-1
Example Circuits
Example Circuits
This chapter shows and discusses several example circuits that can be
constructed using the universal operational amplifier EVM. The circuits are all
classic designs that can be found in most operational amplifier design books.
Topic Page
3.1 Schematic Conventions 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.2 Inverting Amplifier 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.3 Noninverting Amplifier 3–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.4 Differential Amplifier 3–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.5 Sallen-Key Low-Pass Filter 3–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.6 Sallen-Key High-Pass Filter 3–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.7 Two Operational Amplifier Instrumentation Amplifier 3–8. . . . . . . . . . . .
3.8 Quad Operational Amplifier Instrumentation Amplifier 3–10. . . . . . . . .
Chapter 3
Schematic Conventions
3-2
Example Circuits
3.1 Schematic Conventions
Figures 3–1 through 3–6 show schematic examples of circuits that can be
constructed using the universal operational amplifier EVM with shutdown. The
components that are placed on the board are shown in bold. Unused
components are blanked out. Jumpers and other changes are noted. These
examples are only a few of the many circuits that can be built.
3.2 Inverting Amplifier
Figure 3–1 shows area 100 equipped with a single operational amplifier
configured as an inverting amplifier using dual power supplies.
Basic setup is done by choice of input and feedback resistors. The transfer
function for the circuit as shown is:
VOUT
+*
VIN R112
R109
To cancel the ef fects of input bias current, set R105 = R112 || R109, or use a
0-Ω jumper for R105 if the operational amplifier is a low input bias operational
amplifier.
Figure 3–1.Inverting Amplifier With Dual Supply Using Area 100
C107 C108
C105 C104
V1+
V1–
V1+
GND1
V1–
Power Supply Bypass
+
–76
4
3
2
V1+
V1–
R112
C109
R114 C110
R110
R109
R104
R103
R102
R105
C101
C102
A OUT
A101–
A102–
A103+
A104–
R111 C
RAU102
R113
V oltage Reference
U101
V1+
VREF1
R108
+
–Vin
VOUT = –VIN R112
R109
R105 = R112 II R109,
or Short if Using Low
Input Bias Op Amp
Not Used
0.1 µF 10 µF
0.1 µF 10 µF
8SD
A1 FLT
R106
C103
C106
+
–
1
3
2
V1–
5
R101
R107
Optional
5.6 k
100 k
6
Noninverting Amplifier
3-3
Example Circuits
3.3 Noninverting Amplifier
Figure 3–2 shows area 100 equipped with a single operational amplifier
configured as a noninverting amplifier with single-supply power input.
Basic setup is done by choice of input and feedback resistors. The transfer
function for the circuit as shown is:
VOUT
+
VIN
ǒ
1
)
R112
R109
Ǔ)
VREF1
The input signal must be referenced to VREF1.
To cancel the ef fects of input bias current, set R102 = R112 || R109, or use a
0-Ω jumper for R102 if the operational amplifier is a low input bias operational
amplifier.
The TL431 adjustable precision shunt regulator, configured as shown,
provides a low impedance reference for the circuit at about 1/2 V1+ in a 3 V
system. Another option is to adjust resistors R113 and R111 for the desired
VREF1 voltage. The formula for calculating VREF1 is:
VREF1
+
1.24 V
ǒ
R111
)
R113
R113
Ǔ
Figure 3–2.Noninverting Amplifier With Single Supply Using Area 100
C107 C108
C105 C104
V1+
V1–
V1+
GND1
V1–
Power Supply Bypass
+
–
7
6
4
3
2
V1+
V1–
R112
C109
R114 C110
R110
R109
R104
R103
R102
R105
C101
C102
1 OUT
A101+
A102–
A103+
A104–
R111 C
RAU102 = TLV431ACDBV5
R113
Voltage Reference
U101
V1+
VREF1 = 1.24 V
R108
+
–
Vin
Jumper
0.1 µF 10 µF
Jumper
Jumper 102 – to VREF1 VOUT = VIN R112
R109
R102 = R112 II R109,
or Short if Using Low Input
Bias Op Amp
Input Signal With
Reference to VREF1
2.2 kΩ
()
1 + + VREF4
8SD
1 FLT
R106
C103
C106
10 µF
+
–
1
3
2
V1–
5
R101
R107
Optional
5.6 k
100 k
6
Differential Amplifier
3-4
Example Circuits
3.4 Differential Amplifier
Figure 3–3 shows area 100 equipped with a single operational amplifier
configured as a differential amplifier using a voltage reference and single
power supply.
Basic setup is done by choice of input and feedback resistors. The transfer
function for the circuit as shown is:
VOUT
+
VIN
ǒ
R112
R109
Ǔ)
VREF1
Where R112
R109
+
R102
R103
The TLV431 adjustable precision shunt regulator, configured as shown,
provides a low impedance reference for the circuit at about 1/2 V1+ in a 3-V
system. Another option is to adjust resistors R111 and R113 for the desired
VREF1 voltage. The formula for calculating VREF1 is:
VREF1
+
1.24 V
ǒ
R111
)
R113
R113
Ǔ
Figure 3–3.Single Operational Amplifier Differential Amplifier With Single Supply Using
Area 100
C107 C108
C104
V1+
V1–
V1+
GND1
V1–
Power Supply Bypass
+
–
7
6
4
3
2
V1+
V1–
R112
C109
R114 C110
R110
R109
R104
R103
R102
R105
C101
C102
1OUT
101–
102–
103+
104+
R111 C
RAU102
R113
V oltage Reference
U101
V1+
VREF1 = 1.24 V
R108
+
–Vin
Vout = Vin R112
R109
R112
R109
Jumper
Jumper
TLV431ACDBV5
Jumper 104+ to VREF1
=R102
R103
()
+ VREF1
0.1 µF 10 µF
2.2 kΩA1 FLT
R106
C103
81/SD
C105
C106
10 µF
Sallen-Key Low-Pass Filter
3-5
Example Circuits
3.5 Sallen-Key Low-Pass Filter
Figure 3–4 shows area 200 equipped with a dual operational amplifier
configured as a second-order Sallen-Key low-pass filter using dual-power
supplies.
Basic setup is done by proper choice of resistors R and mR and capacitors C
and nC. The transfer function is:
VOUT
VIN
+
1
1
*ǒ
f
fo
Ǔ
2
)ǒ
j
Q
Ǔǒ
f
fo
Ǔ
Where: fo
+
1
2
p
mn
Ǹ
RC
And
Q
+
mn
Ǹ
m
)
1
Figure 3–4.Sallen-Key Low-Pass Filter With Dual Supply Using Area 200
C206 C207
C209 C210
V2+
V2–
V2+
GND2
V2–
Power Supply Bypass
+
–
10 1
4
3
2
V2+
V2–
R212
C215
R216 C211
R221
R220
R218
R219
R217
R215
C212
C213
A2OUT
1/2 Dual Op Amp
A201–
A202–
A203+
A204+
+
–9
7
8
R206
C202
R207 C203
R204
R203
R205
R201
R202
R209
C204
C201
B2OUT
1/2 Dual Op Amp
B201–
B202–
B203+
B204+
R211 C
RAU202
R213
V oltage Reference
V2+
VREF2
U201A
U201B
R210
Jumper
+
–
mR R
nC
Jumper
Jumper
Not Used
Not Used
Vout
Vin
Vin
=1
1– (f/fo)2 + (j/Q)(f/fo)
fo = 1
2π √mn RC
Q = √mn
m+1
0.1µF10µF
0.1µF10µF
5A2/SD
R214 A2 FLT
C214
6 B2/SD
R208 B2 FLT
C205
C208
Sallen-Key High-Pass Filter
3-6
Example Circuits
3.6 Sallen-Key High-Pass Filter
Figure 3–5 shows area 200 equipped with a dual operational amplifier
configured as a second-order Sallen-Key high-pass filter using single-supply
power input.
Basic setup is done by proper choice of resistors R and mR and capacitors C
and nC. Note that capacitors should be used for components R201 and R205,
and a resistor for C201. The transfer function for the circuit as shown is:
VOUT
+
VIN
ȧ
ȧ
ȧ
ȡ
Ȣ
*ǒ
f
fo
Ǔ
2
1
)ǒ
j
Q
Ǔǒ
f
fo
Ǔ*ǒ
f
fo
Ǔ
2
ȧ
ȧ
ȧ
ȣ
Ȥ
)
VREF2
Where: fo
+
1
2
p
mn
Ǹ
RC
And Q
+
mn
Ǹ
n
)
1
The TL431 adjustable precision shunt regulator, configured as shown,
provides a low impedance reference for the circuit at about 1/2 V2+ in a 5 V
system. Another option is to adjust resistors R211 and R213 for the desired
VREF2 voltage. The formula for calculating VREF2 is:
VREF2
+
2.50 V
ǒ
R211
)
R213
R213
Ǔ
Sallen-Key High-Pass Filter
3-7
Example Circuits
Figure 3–5.Sallen-Key High-Pass Filter With Single Supply Using Area 200
C206 C207
C209 C210
V2+
V2–
V2+
GND2
V2–
Power Supply Bypass
+
–
10 1
4
3
2V2+
V2–
R212
C215
R216 C211
R221
R220
R218
R219
R217
R215
C212
C213
A2OUT
1/2 Dual Op Amp
A201–
A202–
A203+
A204+
+
–
R206
C202
R207 C203
R204
R203
R202
R201
R209
C204
C201
B2OUT
1/2 Dual Op Amp
B201–
B202–
B204+
B203+
R211 C
RAU202
R213
V oltage Reference
U201A
U201B
V2+
VREF2 = 2.5 V
R210 9
7
8
+
–Vin
Jumper
Not Used
Jumper
Jumper
R205
CnC
Jumper
mR
TL431ACLP
Jumper
0.1 µF 10 µF
fo = 1
2π √mn RC
Q = √mn
m+1
VOUT = VIN –(f/fo)2
1+(j/Q)(f/fo) – (f/fo)2+ VREF2
Jumper B204 + to VREF2
2.2 kΩ
5A2/SD
A2 FLT
6B2/SD
B2 FLT
C208
10 µF
R208
C205
R214
C214
R
Two Operational Amplifier Instrumentation Amplifier
3-8
Example Circuits
3.7 Two Operational Amplifier Instrumentation Amplifier
Figure 3–6 shows area 200 equipped with a dual operational amplifier
configured as a two-operational-amplifier instrumentation amplifier using a
voltage reference and single power supply.
Basic setup is done by choice of input and feedback resistors. The transfer
function for the circuit as shown is:
VOUT
+
VIN
ǒ
1
)
2R212
R220
)
R212
R221
Ǔ)
VREF2
Where R212 = R206 and R221 = R203
To cancel the effects of input bias current, set R217 = R212 || R220 and set
R202 = R206 ||R203, or use a 0-Ω jumper for R217 and R202 if the operational
amplifier is a low input bias operational amplifier.
The TLV431 adjustable precision shunt regulator, configured as shown,
provides a low impedance reference for the circuit at about 1/2 V2+ in a 3 V
system. Another option is to adjust resistors R211 and R213 for the desired
VREF2 voltage. The formula for calculating VREF2 is:
VREF2
+
1.24 V
ǒ
R211
)
R213
R213
Ǔ
Two Operational Amplifier Instrumentation Amplifier
3-9
Example Circuits
Figure 3–6.Two Operational Amplifier Instrumentation Amplifier With Single Supply Using
Area 200
C206 C207
C209 C210
V2+
V2–
V2+
GND2
V2–
Power Supply Bypass
+
–
10
1
4
3
2
V2+
V2–
R212
C215
R216 C211
R221
R220
R218
R219
R217
R215
C212
C213
A2OUT
1/2 Dual Op Amp
A201–
A202–
A203+
A204+
+
–
R206
C202
R207 C203
R204
R203
R201
R202
R209
C204
C201
B2OUT
1/2 Dual Op Amp
B201–
B202–
B204+
B203+
R211 C
RAU202
R213
Voltage Reference
U201A
U201B
V2+
VREF2 = 1.24 V
R210
9
7
8
+
–
Vin
Jumper
Jumper
R205
TLV431ACDBV5
Jumper
0.1 µF 10 µF
JumperJumper
VOUT = Vin(1+ + )+ VREF2
2R212
R220 R212
R221
Jumper A201 – to B2OUT
R212 = R206
R221 = R203
R202 = R206 II R203
or Short if Using Low Input
Bias Op Amp
Jumper VREF2 to B202–
Jumper
A202– to B201–
R217 = R212 II R220
or Short if Using Low Input
Bias Op Amp
2.2 kΩ
6B2/SD
B2 FLT
R208
C205
5A2/SD
A2 FLT
R214
C214
C208
10 µF
Quad Operational Amplifier Instrumentation Amplifier
3-10
Example Circuits
3.8 Quad Operational Amplifier Instrumentation Amplifier
Figure 3–7 shows area 300 equipped with a quad operational amplifier
configured as a quad-operational-amplifier instrumentation amplifier using a
dual power supply.
Basic setup is done by choice of input and feedback resistors. The transfer
function for the circuit as shown is:
VOUT
+ǒ
VINB
*
VINA
Ǔǒ
R303
)
2(R302)
R303
Ǔ)
R325
R309
Where R302 = R318, R309 = R316, and R325 = R329
AV
+ǒ
R303
)
2(R302)
R303
Ǔ)
R325
R309
+
101 as shown
To cancel the effects of offset errors, adjust V adj (D304+) by applying an extra
signal.
Quad Operational Amplifier Instrumentation Amplifier
3-11
Example Circuits
Figure 3–7.Quad Operational Amplifier Instrumentation Amplifier With Dual Supply Using
Area 300
+
–
4
1
13
3
2
V3+
V3–
R302
C301
R304 C302
R301
R303
R305
R306
R308
R307
C304
C303
A3 OUT
A301–
A302–
A303+
A304+
U301A
C305
R309 A3 FLT
AB3/SD
8
+
–7
5
6
R318
C308
R314 C310
R310
R312
R317
R313
R315
R311
C307
C309
B3 OUT
B301–
B302–
B303+
B304+ U301B
C306
R316
B3 FLT
+
–10
12
11
R325
C316
R323 C317
R323
R324
R326
R327
R329
R328
C318
C319
C3 OUT
C301–
C302–
C303+
C304+
U301C
C320
R330
CD3/SD
9
+
–16
14
15
R339
C321
R331 C324
R332
R333
R334
R335
R336
R337
C322
C325
D3 OUT
D301–
D302–
D303+
D304+ U301D
C323
R338
C3 FLT
D3 FLT
C313 C314
C311 C312
V3+
V3–
GND3
Power Supply Bypass
2.5 = V3+
2.5 = V3–
10 µF
10 µF
0.1 µF
0.1 µF
R320
U302
R319
V oltage Reference
V3+ VREF3
R321
C315
10 kΩ
10 kΩ
10 kΩ
10 kΩ
5 kΩ
5 kΩ
100 Ω
Jumpers
Jumpers
Jumpers
Jumper
Jumper
+
–
VINA
+
–
VINB
+
–
Vadj
3-12
Example Circuits
