ASIX ELECTRONICS CORPORATION Release Date: 04/27/2012
4F, NO.8, Hsin Ann Rd., Science-based I n d u strial Park, Hsin-Chu City, Taiwan, R.O.C. 300
TEL: 886-3-579-9500 FAX: 886-3-579-9558 http://www.asix.com.tw
1
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Features Document No: AX88613/V1.04/04/27/12
3-port 10/100M Ethernet Switch integrated with two
10/100M PHYs, three MACs, a switching fabric, a
packet buffer memory and a configurable
MII/Rev-MII or R MII/Rev-RMII interface for th e 3rd
port access from external device
Fast Ethernet MAC/PHY
IEEE 802.3 10Base-T/100Base-TX compatible
Supports full-duplex operation with IEEE 802.3x
flow control and half d uplex with b ackp ressure
10/100M PHY supports twisted pair crossover
detection and auto-corr e c tion (HP Auto-MDIX)
Supports Wake-on-LAN by Microsoft Wakeup
Frame, Magic Packet and link status change
detection
Switc hing Fabric
Performs non-blocking wire-speed for w ardi ng and
filtering
Embeds 32KB SRAM for packet buffering
Supports bro a dcast storm filtering
Support per queue and per port ingress and egress
programmable rate limit control
Integrates two-way Address-Lookup engine and
table for 1K MAC addresses
Supports Routing Table/IGMP/VLAN Table
access through SPI read/write operation
Supports 802.1D Spanning Tree Protocol and
802.1w Rapid Spanning Tree Protocol
QoS
Supports Quality-of-Service for port-based,
802.1p VLAN and IPv4 TOS/IPv6 COS packets
with four pr iority queues
Supports RFC2475 DiffServ-based
VLAN
Supports up to 3 VLAN groups for port-based
VLAN an d 16 VLAN entries for 802. 1Q tag-based
VLAN func tio n s
Supports Double tagging 802.1Q-in-802.1Q
Function for WAN access
Security
Supports ingress port security mode, incoming
pac ket s with unknown sour ce MAC address could
be dropped
Supports eight Security MAC Registrations
Supports 802.1X port-based Authorization
Multicast
Supports GM RP/GVRP/GARP packet snooping
Supports up to 1K Multicast Group (shared with
L2 MAC table)
Supports eight IGMP Multicast IP address
snooping
Support IPv4 IGMP and IPv6 ICMP/MLD
(Multicast Listener Discovery) Snooping
Monitoring
Supports RMON group 1, 2, 3 and 9 counter
(RFC1213)
Supp ort s Ethernet-like MIB counter (RFC 1643)
Supports Bridge MIB counter (RFC 1493)
Egress/Ingress Port Mirroring
Sniffer functio n s:
Source/Destination Port
DA/SA
VLAN ID
Ethernet Packet Type
IPv4/IPv6 Protocol
IPv4/IPv6 TCP/UDP Port Number
Optional Interf aces Supported:
MII or Reverse-MII
RMII or Reverse-RMII
Optional serial E E PROM
SPI
Sin gle 3.3V pow er s upply w ith options for 1.8V, 2. 5V
and 3.3V I/O voltage support
Integrates an on-chip vo lta ge r e gulat o r r eq ui ri ng onl y
a single power supply of 3.3V
Integrates an on-chip oscillator and PLL requiring
only a 25MHz crystal to operate
Integrates on-chip power-on reset circuit
80-pin EPAD LQFP RoHS compliant package
Operating temp er ature range: 0°C to 70°C
Product Description
The AX88613 is a 3-port 10/100M Ethernet switch with two built-i n 10/100M PHY and one configurable MII/Rev -MII or
RMII/Rev-RMII interface for managed switch applications. The switch supports up to 1K MAC address, Port-based
VLAN an d 16 t a g -based VL AN grou p. It al s o prov i de s powerful Q oS fun ct i on i n c luding IPv 4 TOS/IPv 6 CO S f or voi ce ,
video, audio and data traffic classification. The switch controller provides network system manufacturers the ideal
platform for building smart and cost-effective switches. The AX88613 3-port 10/100M single-chip switch controller
combines the benefits of network simplicity, flexibility and high integration. Its highly integrated feature set enables
network system manufacturers to build low cost, low density, high performance, non-blocking intelligent Ethernet
switches.
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AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
Block Diagram
Target Applications
3-port Managed Switch, Residential Gateway
VoIP Phone, Triple and Quad Play
Media Converter/FTTx CPE, Industri al Ethernet
Single Board Computer (SBC)
Ethernet Traffic Generator/Analyzer and Packet Monitoring
3
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
Copyright © 2008-2012 ASIX Electronics Corporation. All rights reserved.
DISCLAIMER
No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical,
including photocopying and recording, for any purpose, without the express written permission of ASIX. ASIX may make
changes to the product sp e c ifications and descriptions in this document at any time, without notice.
ASIX provides this doc ument “as is” without warranty of any kind, either expressed or implied, including without
limitation warranties of merchantability, fitness for a particular purpose, and non-infringement.
Designers must not rely on the absence or characteristics of any features or registers marked “reserved”, “undefined” or
“NC”. ASIX reserves these for future definition and shall have no responsibility whatsoever for conflicts or
incompatibilities arising from future changes to them. Always contact ASIX to get the latest document before starting a
design of ASIX products.
TRADEMARKS
ASIX, the ASIX logo are regist ered trademark s of ASIX Electronics C orporation. All oth er trademarks are the property of
their respective owners.
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AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
Table of Contents
1.0 OVERVIEW ......................................................................................................................................................... 9
1.1 GENERAL DESCRIPTION ....................................................................................................................................... 9
1.2 BLOCK DIAGRAM ................................................................................................................................................ 9
1.3 PINOUT DIAGRAM.............................................................................................................................................. 10
1.3.1 Host Port : MII Mode ............................................................................................................................... 10
1.3.2 Host P ort : Reverse MII Mode ................................................................................................................. 11
1.3.3 Host Port : RMII Mode............................................................................................................................. 12
1.3.4 Host Port : Reverse RMII Mode ............................................................................................................... 13
2.0 PIN DESCRIPTIONS ........................................................................................................................................ 14
2.1 PORT 0 PHY INTERFACE ................................................................................................................................... 14
2.2 PORT 1 PHY INTERFACE ................................................................................................................................... 15
2.3 PORT 2 INTERFACE ............................................................................................................................................ 16
2.3.1 MII Mode ................................................................................................................................................. 16
2.3.2 Reverse MII Mode .................................................................................................................................... 17
2.3.3 RMII Mode ............................................................................................................................................... 18
2.3.4 Reverse RMII/MDIO Interface ................................................................................................................. 18
2.3.5 Po rt 2 Multi-Function Pin Summary ......................................................................................................... 19
2.4 SPI SLAVE INTERFACE ...................................................................................................................................... 19
2.5 EEROM INTERFACE ......................................................................................................................................... 19
2.6 MISCELLANEOUS IO PIN FUNCTION................................................................................................................... 20
3.0 FUNCTIONAL DESCRIPTION ....................................................................................................................... 21
3.1 OVERVIEW ........................................................................................................................................................ 21
3.2 CLOCK ............................................................................................................................................................... 22
3.3 BUILT-IN POWER-ON-RESET ............................................................................................................................. 22
3.4 BUILT-IN VOLTAGE REGULATOR ....................................................................................................................... 22
3.5 TWO BUILT-IN 10/100M BASE-TX FAST ETHERNET DSP-BASED PHY ............................................................ 23
3.6 BASIC MAC FUNCTION ..................................................................................................................................... 26
3.7 BASIC SWITCH FUNCTION .................................................................................................................................. 27
3.8 VLAN SUPPORT ................................................................................................................................................ 31
3.9 IEEE 802.1D SPANNING TREE .......................................................................................................................... 33
3.10 QOS OPERATION ............................................................................................................................................... 34
3.11 SECURITY OPERATION ....................................................................................................................................... 36
3.12 RMON COUNTER SUPPORT............................................................................................................................... 38
3.13 LAYER 2/3/4 SNIFFER FUNCTION SUPPORT ........................................................................................................ 40
3.14 IPV4 IGMP AND IPV6 ICMP/MLD SNOOPING ................................................................................................. 42
3.15 WAKE-ON-LAN FUNCTION SUPPORT ................................................................................................................ 43
3.16 POWER MANAGEMENT ....................................................................................................................................... 46
3.17 AUTO-POLLING FUNCTION ................................................................................................................................ 47
3.18 PORT MIRRORING .............................................................................................................................................. 47
3.19 SERIAL EEPROM PROTOCOL ............................................................................................................................ 47
4.0 INTERFACE....................................................................................................................................................... 49
4.1 MII INTERFACE ................................................................................................................................................. 49
4.1.1 MII Interface Set-Up Procedure ............................................................................................................... 49
4.2 REVERSE MII INTERFACE .................................................................................................................................. 50
4.2.1 Reverse MII Interface Set-Up Procedure .................................................................................................. 50
4.3 RMII AND REVERSE RMII INTERFACE .............................................................................................................. 51
4.3.1 RMII Mode Reference connection ........................................................................................................... 51
4.3.2 RMII Interface Set-Up Procedure ............................................................................................................. 51
4.3.3 Reverse RMII Mode Reference connection: (Only support 100 Full Duplex mode)................................ 52
4.3.4 Reverse RMII Interface Set-Up Procedure ............................................................................................... 53
4.4 SLAVE SERIAL PERIPHERAL INTERFACE (SPI) ................................................................................................... 54
5.0 INTERNA L R EGISTER CONFIGURATION ................................................................................................ 56
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AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
5.1 AX88613 REGISTER DEFINITION ....................................................................................................................... 56
5.1.1 Chip r evision ID and Reset Register (CIRR) ............................................................................................ 59
5.1.2 PHY0 /PHY1 Co nfiguration Register (PCR) ........................................................................................... 60
5.1.3 PHY0/PHY1 Sta tus Register (PSR) ......................................................................................................... 62
5.1.4 Globa l MAC Configuration Register (G M CR) ......................................................................................... 63
5.1.5 Layer 2 Global Configuration Register (LGCR)....................................................................................... 64
5.1.6 Layer 2 Learning/Aging/OneSA Control R egister (LLCR) ...................................................................... 67
5.1.7 Layer 2 Routing Table Entry Read/W rite Register (LRCR0 and LRCR1) ............................................... 68
5.1.8 802.1D and Port-based VLAN Configuration Regist er (PVCR) .............................................................. 69
5.1.9 Sniffer Functi on Confi guration Register (SFCR0 , SFCR1, S F CR2) ....................................................... 70
5.1.9.1 Sniffer Function Configuration Register 0 (SFCR0) ............................................................................................. 70
5.1.9.2 Sniffer Function Configuration Register 1 (SFCR1) ............................................................................................. 71
5.1.9.3 Sniffer Function Configuration Register 2 (SFCR2) ............................................................................................. 72
5.1.10 QoS Prio r ity Mapping Table Re gist er (QPTR) ........................................................................................ 72
5.1.11 802.1Q-in-1Q (Double-Tagging) Setup Register (QSR) .......................................................................... 73
5.1.12 Port Pair and MDC Contro l Register (PPMR).......................................................................................... 73
5.1.13 MDIO Re ad/W rite Co ntrol Re gist er (MRCR) .......................................................................................... 74
5.1.14 Security Mac Control Register ................................................................................................................. 75
5.1.14.1 Security Mac 0 Control Register (SM0CR0, S M 0CMR1)................................................................................ 76
5.1.14.2 Security Mac 1 Control Register (SM1CR0, S M 1CR1) ................................................................................... 77
5.1.14.3 Security Mac 2 Control Register (SM2CR0, S M 2CR1) .................................................................................. 78
5.1.14.4 Security Mac 3 Control Register (SM3CR0, S M 3CR1) ................................................................................... 79
5.1.14.5 Security Mac 4 Control Register (SM4CR0, S M 4CR1) .................................................................................. 80
5.1.14.6 Security Mac 5 Control Register (SM5CR0, S M 5CR1) ................................................................................... 81
5.1.14.7 Security Mac 6 Control Register (SM6CR0, S M 6CR1) ................................................................................. 82
5.1.14.8 Security Mac 7 Control Register (SM7CR0, S M 7CR1) ................................................................................. 83
5.1.15 VLAN Entry Registers .............................................................................................................................. 84
5.1.15.1 VLAN Entry 0 Register (VER0) ....................................................................................................................... 84
5.1.15.2 VLAN Entry 1 Register (VER1) ....................................................................................................................... 84
5.1.15.3 VLAN Entry 2 Register (VER2) ....................................................................................................................... 84
5.1.15.4 VLAN Entry 3 Register (VER3) ....................................................................................................................... 85
5.1.15.5 VLAN Entry 4 Register (VER4) ....................................................................................................................... 85
5.1.15.6 VLAN Entry 5 Register (VER5) ....................................................................................................................... 85
5.1.15.7 VLAN Entry 6 Register (VER6) ....................................................................................................................... 86
5.1.15.8 VLAN Entry 7 Register (VER7) ....................................................................................................................... 86
5.1.15.9 VLAN Entry 8 Register (VER8) ....................................................................................................................... 86
5.1.15.10 VLAN Entry 9 Register (VER9) ....................................................................................................................... 87
5.1.15.11 VLAN Entry 10 Register (VER10 ) ................................................................................................................... 87
5.1.15.12 VLAN Entry 11 Register (VER11) ................................................................................................................... 87
5.1.15.13 VLAN Entry 12 Register (VER12 ) ................................................................................................................... 88
5.1.15.14 VLAN Entry 13 Register (VER13 ) ................................................................................................................... 88
5.1.15.15 VLAN Entry 14 Register (VER14 ) ................................................................................................................... 88
5.1.15.16 VLAN Entry 15 Register (VER15 ) ................................................................................................................... 89
5.1.16 IGMP Table Read /Write Contro l Register (ITCR) ................................................................................... 89
5.1.17 LED Control Register (LCR) .................................................................................................................... 90
5.1.18 RMON Control Regist er (RCR) ............................................................................................................... 91
5.1.19 RMON Dat a Register (RDR) .................................................................................................................... 92
5.1.20 DSCP QoS mapping table Register (DQR) .............................................................................................. 93
5.1.21 Interrupt Status and Mask Register (ISMR) ............................................................................................. 95
5.1.22 User-Defined Sniffer Packet Type Register (USTR) ................................................................................ 97
5.1.23 Wake-On-LAN Configur atio n R egister (WCR) ....................................................................................... 98
5.1.24 Wake-ON-LAN Setup Re gist er (WSR) .................................................................................................. 100
5.1.25 Port 0 Wakeup Frame Mask0 ~ 2 Register (P0WMR0, P0WMR1, P 0 WMR2) ..................................... 100
5.1.26 Por t 0 Wakeup Fra me CRC Ma sk 0 ~ 2 Re gis t er (P0W CR0, P0WCR1, P 0WCR2) .............................. 101
5.1.27 Port 1 Wakeup Frame Mask0 ~ 2 Register (P1WMR0, P1WM R1, P1WMR2) ..................................... 101
5.1.28 Por t 1 Wakeup Fra me CRC Ma sk 0 ~ 2 Re gis t er (P1W CR0, P1WCR1, P 1WCR2) .............................. 102
5.1.29 Auto-Polling Control Register (ACR) .................................................................................................... 102
5.1.30 EEROM Control Register (ECR) ........................................................................................................... 104
5.1.31 Boot Loader Control Register (BLCR) ................................................................................................... 105
5.1.32 IO Pad Pull-Up/Pull-Down Contro l Register (IOCR) ............................................................................ 105
5.1.33 Multicast IP for IGMP Snooping Entry 0 - 7 Register (IER0 ~ IER7) .................................................. 106
6
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
5.1.33.1 Multicast IP Entry 0 Register (IER0) .............................................................................................................. 106
5.1.33.2 Multicast IP Entry 1 Register (IER1) .............................................................................................................. 106
5.1.33.3 Multicast IP Entry 2 Register (IER2) .............................................................................................................. 106
5.1.33.4 Multicast IP Entry 3 Register (IER3) .............................................................................................................. 107
5.1.33.5 Multicast IP Entry 4 Register (IER4) .............................................................................................................. 107
5.1.33.6 Multicast IP Entry 5 Register (IER5) .............................................................................................................. 107
5.1.33.7 Multicast IP Entry 6 Register (IER6) .............................................................................................................. 108
5.1.33.8 Multicast IP Entry 7 Register (IER7) .............................................................................................................. 108
5.1.34 Port 2 Slave MDC/MDIO Register 0 (P2SMR0) ................................................................................... 108
5.1.35 Port 2 Slave MDC/MDIO Register 1 (P2SMR1) ................................................................................... 109
5.1.36 Port 2 Slave MDC/MDIO Register 2 (P 2 SMR2) ................................................................................... 109
5.1.37 Port 2 Slave MDC/MDIO Register 3 (P2SMR3) ................................................................................... 109
5.1.38 Port 2 Multicast MAC Filters Register (P2MFR0 ~ P2MFR15) ............................................................ 110
5.1.38.1 Port 2 Multicast MAC Filters Register 0 (P2MFR0) ...................................................................................... 110
5.1.38.2 Port 2 Multicast MAC Filters Register 1 (P2MFR1) ...................................................................................... 110
5.1.38.3 Port 2 Multicast MAC Filters Register 2 (P2MFR2) ...................................................................................... 111
5.1.38.4 Port 2 Multicast MAC Filters Register 3 (P2MFR3 ) ...................................................................................... 111
5.1.38.5 Port 2 Multicast MAC Filters Register 4 (P2MFR4) ...................................................................................... 112
5.1.38.6 Port 2 Multicast MAC Filters Register 5 (P 2MFR5) ...................................................................................... 112
5.1.38.7 Port 2 Multicast MAC Filters Register 6 (P2MFR6) ...................................................................................... 113
5.1.38.8 Port 2 Multicast MAC Filters Register 7 (P2 M FR7) ...................................................................................... 113
5.1.38.9 Port 2 Multicast MAC Filters Register 8 (P2MFR8) ...................................................................................... 114
5.1.38.10 Port 2 Multicast MAC Filters Register 9 (P2MFR9) ...................................................................................... 114
5.1.38.11 Port 2 Multicast MAC Filters Register 10 (P2MFR1 0) .................................................................................. 115
5.1.38.12 Port 2 Multicast MAC Filters Register 11 (P2MFR11) .................................................................................. 115
5.1.38.13 Port 2 Multicast MAC Filters Register 12 (P2MFR1 2) .................................................................................. 116
5.1.38.14 Port 2 Multicast MAC Filters Register 13 (P2MFR13) .................................................................................. 116
5.1.38.15 Port 2 Multicast MAC Filters Register 14 (P2MFR1 4) .................................................................................. 117
5.1.38.16 Port 2 Multicast MAC Filters Register 15 (P2MFR15) .................................................................................. 117
5.1.39 Interface Configuration Register (ICR) .................................................................................................. 118
5.1.40 Sleep Mode Exit Register (SMER) ......................................................................................................... 119
5.1.41 General Purpose Timer Configuration Register (GTCR) ....................................................................... 119
5.1.42 Por t 0 MAC Configurat i on Register (P0MCR) ...................................................................................... 119
5.1.43 Port 0 802.1p QoS Mapping Table Register (P0QMTR) ....................................................................... 121
5.1.44 Port 0 802.1Q Configuration for UnTag Frame Register (P0QCR) ....................................................... 121
5.1.45 Port 0 RX per Queue Rate Limit Control Register 0 (P0RQR0) ............................................................ 121
5.1.46 Port 0 RX per Queue Rate Limit Control Register 1 (P0RQR1) ............................................................ 122
5.1.47 Port 0 TX pe r Queue Rate Limit Control Register 0 (P0TQR0) ............................................................ 122
5.1.48 Port 0 TX pe r Queue Rate Limit Control Register 1 (P0TQR1) ............................................................ 122
5.1.49 Port 0 Rate Limit Control Register (P 0RLR).......................................................................................... 123
5.1.50 Port 0 Rate Limit Timer Register (P0RLTR) ......................................................................................... 123
5.1.51 Port 0 Flow Control High/Low Watermark Register (P0 FCR) ............................................................... 123
5.1.52 Port 0 Queue Weighting Configuration Register (P0QW R) ................................................................... 124
5.1.53 Port 0 DA MAC Address Register (P0DAR0, P0ADR1) ....................................................................... 124
5.1.54 Por t 1 MAC Configurat i on Register (P1MCR) ...................................................................................... 125
5.1.55 Port 1 802.1p QoS Mapping Table Register (P1QMTR) ....................................................................... 126
5.1.56 Port 1 802.1Q Configuration for UnTag Frame Register (P1QCR) ....................................................... 127
5.1.57 Port 1 RX per Queue Rate Limit Control Register 0 (P1RQR0) ............................................................ 127
5.1.58 Port 1 RX per Queue Rate Limit Control Register 1 (P1RQR1) ............................................................ 127
5.1.59 Port 1 TX pe r Queue Rate Limit Control Register 0 (P1TQR0) ............................................................ 127
5.1.60 Port 1 TX pe r Queue Rate Limit Control Register 1 (P1TQR1) ............................................................ 128
5.1.61 Port 1 Rate Limit Control Register (P 1RLR).......................................................................................... 128
5.1.62 Port 1 Rate Limit Timer Register (P1RLTR) ......................................................................................... 128
5.1.63 Port 1 Flow Control High/Low Watermark Register (P1 FCR) ............................................................... 128
5.1.64 Port 1 Queue Weighting Configuration Register (P1QW R) ................................................................... 129
5.1.65 Port 1 DA MAC Address Register (P1DAR0, P1ADR1) ....................................................................... 129
5.1.66 Por t 2 MAC Configurat i on Register (P2MCR) ...................................................................................... 130
5.1.67 Port 2 802.1p QoS Mapping Table Register (P2QMTR) ....................................................................... 131
5.1.68 Port 2 802.1Q Configuration for UnTag Frame Register (P2QCR) ....................................................... 132
5.1.69 Port 2 RX per Queue Rate Limit Control Register 0 (P2RQR0) ............................................................ 132
5.1.70 Port 2 RX per Queue Rate Limit Control Register 1 (P2RQR1) ............................................................ 132
7
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
5.1.71 Port 2 TX pe r Queue Rate Limit Control Register 0 (P2TQR0) ............................................................ 132
5.1.72 Port 2 TX pe r Queue Rate Limit Control Register 1 (P2TQR1) ............................................................ 133
5.1.73 Port 2 Rate Limit Control Register (P 2RLR).......................................................................................... 133
5.1.74 Port 2 Rate Limit Timer Register (P2RLTR) ......................................................................................... 133
5.1.75 Port 2 Flow Control High/Low Watermark Register (P2 FCR) ............................................................... 133
5.1.76 Port 2 Queue Weighting Configuration Register (P2QW R) ................................................................... 134
5.1.77 Port 2 DA MAC Address Register (P2DAR0, P2DAR1) ....................................................................... 134
5.1.78 Output Clock Select Register (OCSR) .................................................................................................... 134
5.2 PHY REGISTER DESCRIPTION .......................................................................................................................... 135
5.2.1 Basic Mode Control Register (BMCR) .................................................................................................. 135
5.2.2 Basic Mode Status Register (BMSR) ..................................................................................................... 136
5.2.3 PHY Identifier Register 1 (PHYIDR1) ................................................................................................... 137
5.2.4 PHY Identifier Register 2 (PHYIDR2) ................................................................................................... 137
5.2.5 Auto-Negotiation Advertisement Register (ANAR) ............................................................................... 138
5.2.6 Auto-Negotiation Link Partner Ability Register (ANLPAR) .................................................................. 139
5.2.7 Auto-Negotiation Expa nsion Register (ANER) ...................................................................................... 140
5.3 REVERSE MODE PHY REGISTER DESCRIPTION ............................................................................................... 141
5.3.1 Basic Mode Control Register (Rev_BMCR) .......................................................................................... 141
5.3.2 Basic Mode Status Register (Rev_BMSR) ............................................................................................. 142
5.3.2 Auto-Negotiation Advertisement Register (Rev_ANAR) ....................................................................... 143
5.3.3 Auto-Negotiation Link Partner Ability Register (Rev_ANLPAR) ......................................................... 144
5.3.4 Local User-Defined Control Register (Rev_LUCR) ............................................................................... 144
5.3.5 Remote User-Defined Control Register (Rev_RUCR) ........................................................................... 144
6.0 ELECTRICA L SPECIFICA TION AND TIMING ....................................................................................... 145
6.1 DC CHARACTERISTICS .................................................................................................................................... 145
6.1.1 Absolute Ma xi mum Ratings ................................................................................................................... 145
6.1.2 Recommended Operating Condition ....................................................................................................... 145
6.1.3 DC Char acter i st i cs of 3. 3V I/O (VCC3IO = 3.3V) ................................................................................ 146
6.1.4 DC Characteristics of 2.5 V I/O (VCC3IO = 2.5V) ............................................................................... 146
6.1.5 DC Char acter i st i cs of 1. 8 V I/O (VCC3IO = 1.8V) ............................................................................... 147
6.1.6 DC Characteristics of Voltage Regulator................................................................................................ 148
6.2 THERMAL CHARACTERISTICS .......................................................................................................................... 149
6.3 POWER CONSUMPTION .................................................................................................................................... 150
6.4 POWER-UP SEQUENCE ..................................................................................................................................... 151
6.5 AC SPECIFICATIONS ......................................................................................................................................... 152
6.5.1 Clock T iming .......................................................................................................................................... 152
6.5.2 Serial EE PROM T iming ......................................................................................................................... 153
6.5.3 MII Interface Timing .............................................................................................................................. 154
6.5.4 Station Management Timing ................................................................................................................... 155
6.5.5 Reverse MII Timing ............................................................................................................................... 156
6.5.6 Reverse RMII Timing ............................................................................................................................. 157
6.5.7 SPI Timing.............................................................................................................................................. 158
6.5.8 10/100 M Ethernet PHY Interface Timing .............................................................................................. 159
7 PACKAGE INFORMATION ............................................................................................................................. 160
8 ORDERING INFORMATION ........................................................................................................................... 162
REVISION HISTORY ................................................................................................................................................. 163
8
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
List of Figures
FIG 1 AX88613 BLOCK DIAGRAM .................................................................................................................................. 9
FIG 2 AX88613 MII MODE PINOUT DIAGRAM ............................................................................................................... 10
FIG 3 AX88613 REVERSE MII MODE PINOUT DIAGRAM ................................................................................................ 11
FIG 4 AX88613 RMII MODE PINOUT DIAGRAM ............................................................................................................. 12
FIG 5 AX88613 REVERSE RMII MODE PINOUT DIAGRAM ............................................................................................. 13
FIG 7 BUILT-IN 10/100M BASE-TX ETHERNET PHY ARCHITECTURE ............................................................................. 23
FIG 8 POWER-UP AND POWER-DOWN OPERATION ........................................................................................................... 24
FIG 9 LOOP-BACK D AT A PATH WHEN INTERNAL LOOP-BACK FUNCTION IS ENABLED ....................................................... 25
FIG 10 ROUTING TABLE FORMAT ..................................................................................................................................... 27
FIG 11 VLAN TABLE FORMAT ......................................................................................................................................... 28
FIG 12 IGMP TABLE FORMAT .......................................................................................................................................... 29
FIG 13 HOST PORT MULTICAST FILTER TABLE FORMAT................................................................................................... 29
FIG 14 FORWARDING PROCESS ......................................................................................................................................... 30
FIG 15 802.1Q VLAN TAG FRAME FORMAT .................................................................................................................... 31
FIG 16 IPV4 FRAME FORMAT ........................................................................................................................................... 34
FIG 17 IPV6 FRAME FORMAT ........................................................................................................................................... 35
FIG 18 RX/TX BANDWIDTH FILTERING AND QOS MAPPING DATA FLOW .......................................................................... 35
FIG 19 IPV6 FRAME FORMAT ........................................................................................................................................... 42
FIG 20 WAKE-ON -LAN APPLICATION ............................................................................................................................. 43
FIG 21 SPI SINGLE WRITE TIMING DIAGRAM ................................................................................................................... 54
FIG 22 SPI BURST-WRITE TIMING DIAGRAM .................................................................................................................... 54
FIG 23 SPI SINGLE READ TIMING DIAGRAM ..................................................................................................................... 55
FIG 24 SPI BURST-READ TIMING DIAGRAM ..................................................................................................................... 55
List of Tables
TABLE 1 PHY OPERATION MODE SETTING BY PCR OPMODE [2:0] .............................................................................. 24
TABLE 2 DOUBLE TAGGING ACCESS PORT AND UPLINK PORT TX OPERATION ................................................................ 33
TABLE 3 IEEE 802.1X PORT-BASED AUTHORIZATION .................................................................................................... 36
TABLE 4 SECURITY MAC FILTERING FUNCTION TABLE ................................................................................................... 38
TABLE 5 RMON COUNTER MAPPING TABLE ................................................................................................................... 39
TABLE 6 LAYER 2 SNIFFER TABLE ................................................................................................................................... 40
TABLE 7 IPV4 SNIFFER TABLE ......................................................................................................................................... 40
TABLE 8 IPV6 SNIFFER TABLE ......................................................................................................................................... 41
TABLE 9 NEXT HEADER TABLE ....................................................................................................................................... 42
TABLE 10 POWER MANAGEMENT STATUSES ................................................................................................................. 46
TABLE 11 EEPROM SIZE MAPP ING (PD: TIE A 4.7K OHM PULL-DOWN RESISTOR TO GROUND PU: TIE A 4.7K OHM
PULL-UP RESISTOR TO VCC) .......................................................................................................................................... 47
TABLE 12 REGISTER MAPPING TABLE ........................................................................................................................... 58
9
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
1.0 Overview
1.1 General Description
The AX88613 is a 3-port 10/100M Ethernet switch with two built-in 10/100M PHY and one configurable MII or RMII
interface for managed switch application. The switch supports up to 1K MAC address, Port-based VLAN and 16
tag-base d VLAN g roup. It al so provides pow erf ul QoS functions include IPv 4 TOS/IPv6 CO S for v oice, v ideo, au dio and
data traffic classification. T he switch controller provides network system manufacturers the ideal platform for building
intelligent and cost-effective switches.
The AX88613 is a 3-port 10/100 BASE-T single chip switch controllers combine the benefits of network simplicity,
flexibility and high inte gra ti on. Its highly integrated feature set enables network system manufacturers to build low cost,
low densi ty, high performance, and non-blocking intelligent Ethernet switches.
Basically the AX88613 supports non-bl ocking wire-speed forwarding rate and no Head-of-Line (HOL) blocking issue.
The AX 88613 provides tw o flow -control mechanism s to avoid loss of data: an optional jamm ing based backpressure fl ow
control in the half-duplex operation and IEEE 802.3x in the full-duplex mode.
1.2 Block Diagram
Fig 1 AX88613 BLOCK DIAGRAM
10
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
1.3 Pinout Diagram
1.3.1 Host Port : MII Mode
Fig 2 AX88613 MII Mode Pinout Diagram
11
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
1.3.2 Host Port : Reverse MII Mode
AX88613
Host Port : Reverse-MII Mode
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
60 NC
59 NC
58 NC
57 NC
56 P2_COL
55 P2_CRS
54 P2_RX_CLK
53 VCCK
52 P2_RXD0
51 P2_RXD1
50 NC
49 NC
48 NC
47 P2_RXD2
46 P2_RXD3
45 P2_RX_DV
44 VCC3IO
43 GND
42 NC
41 VCCK
40 NC
39 INT
38 PME
37 NC
36 SPI_CLK
35 VCCK
34 P1_LED0
33 P1_LED1
32 GND
31 VCC3IO
30 MODE2
29 MODE1
28 MODE0
27 RST_N
26 V18
25 VCCAH
24 GNDA
23 P1_GND18A
22 P1_TXON
21 P1_TXOP
NC
P2_TX_EN
P2_TXD3
P2_TXD2
VCC3IO
MISO
SS
MOSI
P2_TXD1
P2_TXD0
P2_TX_CLK
P2_MDIO
VCCK
P2_MDC
P0_LED0
P0_LED1
SK
DIO
CS
GND
P0_GND18A
P0_TXON
P0_TXOP
P0_VCC18A
P0_RXIN
P0_RXIP
P0_GND33A
P0_VCC33A
P0_RSET_BG
P0_VCC18A
P0_XTLN
P0_XTLP
P0_GND18A
P1_VCC18A
P1_RSET_BG
P1_VCC33A
P1_GND33A
P1_RXIP
P1_RXIN
P1_VCC18A
Fig 3 AX88613 Reverse MII Mode Pinout Diagram
12
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
1.3.3 Host Port : RMII Mode
AX88613
Host Port : RMII Mode
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
60 NC
59 NC
58 NC
57 NC
56 P2_COL
55 P2_CRS
54 P2_REFCLKO
53 VCCK
52 P2_TXD0
51 P2_TXD1
50 NC
49 NC
48 NC
47 NC
46 NC
45 P2_TX_EN
44 VCC3IO
43 GND
42 NC
41 VCCK
40 NC
39 INT
38 PME
37 NC
36 SPI_CLK
35 VCCK
34 P1_LED0
33 P1_LED1
32 GND
31 VCC3IO
30 MODE2
29 MODE1
28 MODE0
27 RST_N
26 V18
25 VCCAH
24 GNDA
23 P1_GND18A
22 P1_TXON
21 P1_TXOP
NC
P2_CRSDV
NC
NC
VCC3IO
MISO
SS
MOSI
P2_RXD1
P2_RXD0
P2_REFCLK
P2_MDIO
VCCK
P2_MDC
P0_LED0
P0_LED1
SK
DIO
CS
GND
P0_GND18A
P0_TXON
P0_TXOP
P0_VCC18A
P0_RXIN
P0_RXIP
P0_GND33A
P0_VCC33A
P0_RSET_BG
P0_VCC18A
P0_XTLN
P0_XTLP
P0_GND18A
P1_VCC18A
P1_RSET_BG
P1_VCC33A
P1_GND33A
P1_RXIP
P1_RXIN
P1_VCC18A
Fig 4 AX88613 RMII Mode Pinout Diagram
13
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
1.3.4 Host Port : Reverse RMII Mode
AX88613
Host Port : Reverse-RMII Mode
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
60 NC
59 NC
58 NC
57 NC
56 P2_COL
55 P2_CRS
54 P2_TX_CLK
53 VCCK
52 P2_RXD0
51 P2_RXD1
50 NC
49 NC
48 NC
47 NC
46 NC
45 P2_RX_DV
44 VCC3IO
43 GND
42 NC
41 VCCK
40 NC
39 INT
38 PME
37 NC
36 SPI_CLK
35 VCCK
34 P1_LED0
33 P1_LED1
32 GND
31 VCC3IO
30 MODE2
29 MODE1
28 MODE0
27 RST_N
26 V18
25 VCCAH
24 GNDA
23 P1_GND18A
22 P1_TXON
21 P1_TXOP
NC
P2_TX_EN
NC
NC
VCC3IO
MISO
SS
MOSI
P2_TXD1
P2_TXD0
P2_RX_CLK
P2_MDIO
VCCK
P2_MDC
P0_LED0
P0_LED1
SK
DIO
CS
GND
P0_GND18A
P0_TXON
P0_TXOP
P0_VCC18A
P0_RXIN
P0_RXIP
P0_GND33A
P0_VCC33A
P0_RSET_BG
P0_VCC18A
P0_XTLN
P0_XTLP
P0_GND18A
P1_VCC18A
P1_RSET_BG
P1_VCC33A
P1_GND33A
P1_RXIP
P1_RXIN
P1_VCC18A
Fig 5 AX88613 Reverse RMII Mode Pinout Diagram
14
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
2.0 Pin D escriptions
I/O Definition: The following terms describe the AX88613 pin-out. The follo wing abbreviations are used in following
Tables. (Assume VCC3IO = 3.3V)
I18
Input 1.8V
PU
Pull Up
I3
Input 3.3V
PD
Pull Down
O18
Output 1 .8V
P
Power Pin
O3
Output 3 .3V
NC
No Conne c t
B18
Bi-directional 1.8V
OD
Open Dra in
B3
Bi-directional 3.3V
T
Tri-state
AB
Analog Bi-directional
8mA
8 mA drive strength
A
Analog
16mA
16 mA drive strength
2.1 Port 0 PHY Interface
Signal Name
I/O
Pin No.
Description
P0_TXOP,
P0_TXON
AB
3
2
Transmit Differential Data Pair for PHY0.
The differential data is transmitted to the media on the TXOP/TXON signal pair
in MDI mode or received differential data input positive pin in MDIX mode.
P0_RXIP,
P0_RXIN
AB
6
5
Receive Differential Data Pair for PHY0.
The differential data is received from the media on the RXIP/RXIN signal pair
in MDI mode or transmitted differential data output negative pin
in MDIX
mode.
P0_XTLN,
I18
11
25Mhz ± 50 PPM crystal or oscillator clock input. A 25 MHz parallel-resonant
crystal may be connected between these pins to stabilize the internal oscillator.
This clock is needed for the embedded 10/100M Ethernet PHY to operate.
P0_XTLP
O18
12
25MHz Crystal Feedback Output. This output is used in crystal connection only.
It must be left open when P0_XTLN is driven
with an external 25MHz
oscillator.
P0_RSET_BG
AO
9
Off-chip resistor. Connect 12.1Kohm ± 1% resistor to analog ground.
P0_LED0 B3/8mA 75
Port 0 PHY LED 0 signal output. Please configure LCR [7:0] to select LED
output function.
P0_LED1
B3/8mA
76
Port 0 PHY LED 1 signal output. Please configure LCR [15:8] to select LED
output function.
P0_VCC18A
P/A
4, 10
1.8V power supply for internal PHY Analog c ircui t
P0_VCC33A
P/A
8
3.3V power supply for internal PHY Analo g circ uit.
P0_GND18A
P/A
1,13
1.8V Ground for int ernal PHY Analog circuit
P0_GND33A
P/A
7
3.3V Ground for int ernal PHY Analog circuit.
15
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
2.2 Port 1 PHY Interface
Signal Name
I/O
Pin No.
Description
P1_TXOP,
P1_TXON
AB
AB
21
22
Transmit Differential Data Pair for PHY1.
The differential data is transmitted to the media on the TXOP/TXON
signal pair in MDI mode or received diff eren tial data input positive pin
in
MDIX mode.
P1_RXIP,
P1_RXIN
AB
AB
18
19
Receive Differential Data Pair for PHY1.
The differenti al data is received from the m edia on the RXIP/RXIN signal
pair in MDI mode or transmitted differential data input positive pin
in
MDIX mode.
P1_RSET_BG
AO
15
Off-chip resistor. Connect 12.1Kohm ± 1% resistor to ground.
P1_LED0
B3/8m
A
34
Port 1 PHY LED 0 signal output. Please configure LCR [7:0] to select
LED output func tion.
P1_LED1
B3/8m
A
33
Port 1 PHY LED 1 signal output. Please co nfigure LCR [15 :8] to select
LED output function.
P1_VCC18A
P/A
20, 14
1.8V power supply for internal PHY Analo g circ uit
P1_VCC33A
P/A
16
3.3V power supply for internal PHY Analo g circ uit.
P1_GND18A
P/A
23
1.8V Ground for int ernal PHY Analog circuit
P1_GND33A
P/A
17
3.3V Ground for int ernal PHY Analog circuit.
16
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
2.3 Port 2 Interface
2.3.1 MII Mode
Signal Name
I/O
Pin No.
Description
P2_RX_CLK
I3
71
Port 2 Receive clock input
P2_RX_COL
I3
56
Port 2 Receive collision signal. Collision signal is driven high by PHY
when the collision is de te c te d.
P2_RX_CRS I3 55 Port 2 Receive carrier sense. Carrier sense signal is asser t ed high
asynchronously by the PHY when either transmit or receive medium is
non-idle.
P2_RX_DV I3 62 Port 2 Receive data valid. P2_RX_DV is
asserted high when valid data is
present on receive data bus [3:0].
P2_RXD0
I3
70
Port 2 Receive data bit 0 synchronousl y with respec t to the rising edge of
P2_RX_CLK.
P2_RXD1
I3
69
Port 2 Receive data bit 1 synchronousl y with respec t to the rising edge of
P2_RX_CLK.
P2_RXD2
I3
64
Port 2 Receive data bit 2 synchronousl y with respec t to the rising edge of
P2_RX_CLK.
P2_RXD3 I3 63 Port 2 Receive data bit 3. Synchronously with respect to the rising edge of
P2_RX_CLK.
P2_TX_CLK
I3
54
Port 2 Tr a nsmit clock input
P2_TX_EN
O3/8mA
45
Port 2 Tr a nsmit data enable. P2_TX_EN is asserted high to indicate a
valid transmit data bus [3:0]
P2_TXD0 O3/8mA 52 Port 2 Transmit data bit 0 synchronously with respect to the rising edge of
P2_TX_CLK.
P2_TXD1 O3/8mA 51 Port 2 Transmit data bit 1 synchronously with r
espect to the risin g edge of
P2_TX_CLK.
P2_TXD2
O3/8mA
47
Port 2 Transmit data bit 2 synchronously w ith respect to the rising edge of
P2_TX_CLK.
P2_TXD3
O3/8mA
46
Port 2 Transmit data bit 3 sy nchronously with respect to the rising edge of
P2_TX_CLK.
P2_MDIO B3/8mA/T 72 MII management data. Serial data input/output transferred from/to the
externally co nnected MAC device. The transfer protocol should conform
to the IEEE 802.3u MII spec.
P2_MDC O3/8mA 74 MII management clock output to PHY. All data transferred on
MII1_MDIO are synchronized to the rising edge of this clock. The
frequency of MII1_MDC is 1MHz.
17
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
2.3.2 Reverse MII Mode
Signal Name
I/O
Pin No.
Description
P2_TX_CLK
O3/8mA
71
Port 2 Transmit Clock. This clock is provided to supply to the
P2_TX_CLK of externally connected Ethernet MAC device with MII
P2_TX_EN
I3
62
Port 2 Transmit valid signal. P2_TX_EN is asserted high to indicate a
valid P2_TXD0-3. It should be driven s ynchronously with respect to the
rising edge of P2_TX_CLK by the externally connected Ethernet MAC
device with MII.
P2_TXD0
I3
70
Port 2 Transmit Data 0. P2_TXD0 should be driven synchronousl y with
respect to the rising edge of P2_TX_CLK by the externally connected
Ethernet MAC device with MII.
P2_TXD1
I3
69
Port 2 Transmit Data 1. P2_TXD1 should be driven synchronousl y with
respect to the rising edge of P2_TX_CLK by the externally connected
Ethernet MAC device with MII.
P2_TXD2
I3
64
Port 2 Transmit Data 2. P2_TXD2 should be driven synchronously with
respect to the rising edge of P2_TX_CLK by the externally connected
Ethernet MAC device with MII.
P2_TXD3
I3
63
Port 2 Transmit Data 3. P2_TXD3 should be driven synchronousl y with
respect to the rising edge of P2_TX_CLK by the externally connected
Ethernet MAC device with MII.
P2_RX_CLK
O3/8mA
54
Port 2 Receive clock. This clock is provided to su pply t o the P2_RX_C LK
of externally connected Ethernet MAC device with MII. This pin is
tri-stated in isolate mode.
P2_RX_DV
O3/8mA
45
Port 2 Receive data enable. P2_RX_DV is asserted high to indicate a valid
receive data bus [3:0]
P2_RXD0
O3/8mA
52
Port 2 Receive data bit 0 synchronously with resp ect to the rising e dge o f
P2_RX_CLK.
P2_RXD1 O3/8mA 51 Port 2 Receive data bit 1 synchronously with respe
ct to the rising edge of
P2_RX_CLK.
P2_RXD2
O3/8mA
47
Port 2 Receive data bit 2 synchronously with resp ect to the rising e dge o f
P2_RX_CLK.
P2_RXD3
O3/8mA
46
Port 2 Receive data bit 3 synchronously with resp ect to the rising e dge o f
P2_RX_CLK.
P2_CRS
I3
55
Port 2 Carrier Sense. Please connect this signal to external P2_TX_EN
signal.
P2_COL I3 56 Pull-Down with a 4.7KOhm resistor to ground. Reverse MII mode only
support full duplex.
P2_MDIO
B3/8mA/T
72
Station Managem ent Data. Serial data input/output transferred from/to the
externally co nnected MAC device. The transfer protocol should conform
to the
IEEE 802.3u MII spec.
P2_MDC I3 74 Station Management clock input from the externally co nnected Ethernet
MAC device. A ll data transf erred on MDIO are syn chronized to the rising
edge of this clock.
18
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
2.3.3 RMII Mode
Signal Name
I/O
Pin No.
Description
P2_REFCLK
I3
71
Port 2 50MHz RMII reference clock input ± 50 PPM with a duty cycle
between 35% and 65% inclusive.
P2_CRSDV
I3
62
Port 2 Receive data valid synchronously w ith respect to the rising edge of
P2_REFCLK. P2_CRSDV i s asserted high when valid data is present on
receive data bus [1:0].
P2_RXD0
I3
70
Port 2 Receive data bit 0 synchronousl y with respec t to the rising edge of
P2_RX_CLK.
P2_RXD1 I3 69 Port 2 Receive data bit 1 synchrono us ly with respect to the rising e dge of
P2_RX_CLK.
P2_REFCLKO
O3/8mA
54
Port 2 50MHz reference clock output if ICR [14] is set to one.
P2_TX_EN
O3/8mA
45
Port 2 T r ansmit data enable. P2_TX_EN is asserted high to indicate a
valid transmit data bus [1:0]
P2_TXD0 O3/8mA 52 Port 2 Transmit data bit 0 synchronously with respect to the rising edge of
P2_TX_CLK.
P2_TXD1
O3/8mA
51
Port 2 Transmit data bit 1 synchronously w ith respect to the rising edge of
P2_TX_CLK.
P2_MDIO
B3/8mA/T
72
MII management data. Serial d a ta inp ut/outp ut tra nsferre d from/to the
externally co nnected MAC device. The transfer protocol should conform
to the IEEE 802.3u MII spec.
P2_MDC
O3/8mA
74
MII manag ement clock output to PH Y . All data transferred on MDIO ar e
synchronized to the rising e dge of this cl ock. The frequency of MDC is
1MHz.
P2_CRS
I3
55
Pull-Down with a 4.7K ohm resistor to ground
P2_COL
I3
56
Pull-Down with a 4.7K ohm resistor to ground
2.3.4 Reverse RMII/MDIO Interface
Signal Name
I/O
Pin No.
Description
P2_REFCLK
I3
71
Port 2 50MHz RMII reference clock input ± 50 PPM with a duty cycle
between 35% and 65% inclusive.
P2_TX_EN
I3
62
Port 2 T r ansmit data enable. P2_TX_EN is asserted high to indicate a
valid transmit data bus [1:0].
P2_TXD0
I3
70
Port 2 Transmit data bit 0 synchronously w ith respect to the rising edge of
P2_TX_CLK.
P2_TXD1 I3 69 Port 2 Transmit data bit 1 synchronously with respect to the rising edge of
P2_TX_CLK.
P2_CRSDV
O3/8mA
45
Port 1 Receive data enable synchronous l y with respect to the rising edge
of P2_REFCLK. P2_CRSDV is asserted high to indicate a valid receive
data bus [1:0].
P2_RXD0
O3/8mA
52
Port 2 Receive data bit 0 synchronousl y with respec t to the rising edge of
P2_TX_CLK.
P2_RXD1
O3/8mA
51
Port 2 Receive data bit 1 synchrono us ly with respect to the rising e dge of
P2_TX_CLK.
P2_REFCLKO
O3/8mA
54
Port 2 50 MHz Reference clock output if ICR [14] is set t o one.
P2_MDIO B3/8mA/T 72 MII management data. Serial d a ta inp ut/outp ut tra nsferre d from/to the
externally
connected MAC device. The transfer protocol should conform
to the IEEE 802.3u MII spec.
P2_MDC I3 74 MII manag ement clock
output to PHY. All data transferred on MDIO are
synchronized to the rising e dge of this cl ock. The frequency of MDC is
1MHz.
P2_CRS
I3
55
Pull-Down with a 4.7K ohm resistor to ground
P2_COL
I3
56
Pull-Down with a 4.7K ohm resistor to ground
19
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
2.3.5 Port 2 Multi-Function Pin Summary
AX88613
Pin # MII Mode Reverse MII Mo de RMII Mode Reverse RM II Mode
71
P2_RX_CLK
P2_TX_CLK
P2_REFCLK
P2_REFCLK
56
P2_RX_COL
Pull-Down
Pull-Down
Pull-Down
55
P2_RX_CRS
P2_CRS
Pull-Down
Pull-Down
62
P2_RX_DV
P2_TX_EN
P2_CRSDV
P2_TX_EN
70
P2_RXD0
P2_TXD0
P2_RXD0
P2_TXD0
69
P2_RXD1
P2_TXD1
P2_RXD1
P2_TXD1
64
P2_RXD2
P2_TXD2
NC
NC
63
P2_RXD3
P2_TXD3
NC
NC
54
P2_TX_CLK
P2_RX_CLK
P2_REFCLKO
P2_REFCLKO
45
P2_TX_EN
P2_RX_DV
P2_TX_EN
P2_CRSDV
52
P2_TXD0
P2_RXD0
P2_TXD0
P2_RXD0
51
P2_TXD1
P2_RXD1
P2_TXD1
P2_RXD1
47
P2_TXD2
P2_RXD2
NC
NC
46
P2_TXD3
P2_RXD3
NC
NC
72
P2_MDIO
P2_MDIO
P2_MDIO
P2_MDIO
74
P2_MDC
P2_MDC
P2_MDC
P2_MDC
2.4 SPI Slave Interface
Signal Name
I/O
Pin No.
Description
SPI_CLK
I3
36
SPI Interface clock (1MHz)
MOSI
I3
68
Master output s lave input
MISO
B3/8mA/T
66
Master input sla ve output
SS
I3
67
Slave select
2.5 EEROM Interface
Signal Name
I/O
Pin No.
Description
CS
B5/8mA/PD
79
EEPROM chip select signal
PU: Pull-Up with a 4.7K ohm resistor to VCC
PD: Pull-Down with a 4.7K ohm resistor to ground
EEPROM size
SK
CS
N/A (default)
PD
PD
1K(93C46)
PD
PU
2K(93C56)
PU
PD
4K(93C66)
PU
PU
DIO
B5/8mA/T
78
EEPROM bi-direction data signal. This pin should connect to EEPROM’s
DO and DI pin.
SK
B5/8mA/PD
77
EEPROM clock (1MHz)
20
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
2.6 Miscellaneous IO Pin Function
Signal Name
I/O
Pin No.
Description
MODE2,
MODE1,
MODE0
I5
I5
I5
30
29
28
SPI Mode Enable
MODE2 : Pull-down with a 4.7K ohm resistor to ground
MODE1 : Pull-up with a 4.7K ohm resistor to VCC
MODE0 : Pull- up with a 4.7K ohm resistor to VCC
RST_N
I5
27
Chip Reset pin. Active low.
PME
O
38
Po wer Management Event. T his pin is used to indicate that a power
management event has occurred.
INT O 39 Interrupt signal outp ut . Interrupt polarity can be programmed by setting
GMCR register bit [2 7].
VCCAH
P
25
Internal Regulator 3.3 Volt DC power input
V18
P
26
Internal Regulator 1.8 Vo lt DC power output.
GNDA
P
24
Internal Regulator a nalog ground pin
VCCK
P
35,41,53,73
1.8 Volt. DC Power Supply for core logic
VCC3IO
P
31,44,65
Support 1.8V, 2.5V or 3.3 multi voltage DC Power Supply for IO pad
GND
P
32,43,80
Ground
21
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
3.0 Functional Description
3.1 Overview
In essence , the AX88613 de vice i s a hi ghly integ rated Lay er 2 sw itch . It support s three 10/ 100M ports w ith on -chip PHYs.
It also supports integ rated switching logic, packet qu euing m em ory and packet storag e m em ory. The A X88613 is capable
of store-and-forwarding packets at wire speed on all ports regardless of packet size. It is a low cost solution f or two or three
ports Ethernet switch design. After a power on reset, the AX88613 provides a serial SPI bus interface, which can direct
access internal configure registers through SPI read/write operation. The AX88613 can easily be configured to support
QoS, IEEE 802.3x flow control threshold setting, broadcast storm control and other functions.
The packet-forwardi ng engine ins ide t he AX88613 uses the packet header information (e.g., DA, SA, VLAN, QoS etc.)
extracted and decoded by the packet decoder. It pr o cesses this header information and uses the result (list of destination
port numbers, VLAN identifier etc.) to do following process:
‧ Layer 2 Switching
‧ Head-Of-Line Blocking P revention
‧ QoS, including port-based, 802.1P priority tags, IPv4 TOS/IPv6 COS/ DiffSer ve packets with four priority queues
‧ Broadcast Storm Prevention
‧ Security Operation, include 802.1x, VLAN filtering, and MAC address Restriction.
‧ Egress/Ingress Bandwidth Control
‧ Port Mirroring/Sniffer Function
‧ Filtering/Forwarding Control Frame
‧ VLANs, including port-based and tag-based IEEE 802.1Q VLANs.
‧ Two Built-in 10/100M Ethernet PHY IP power down control and configuration
‧ IPv4 IGMP and IPv6 ICMP/MLD (Multicast Listener Discovery) snooping
‧ IEEE 802.1D Spanning Tree
‧ Double-tagging (1Q -in-1Q) processing
‧ RMON Counters for network management
‧ Microsoft Wake-Up Frame Detection, Magic Packet Detection, Link Status Change Detection
‧ Power Management
22
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
3.2 Clock
The AX88613 only needs one external 25 MHz crystal or oscillator, via pins P0_XTLP/P0_XTLN, to provide the
reference clock to th e internal PHY0’s PLL circuit and generate a f ree-run 100Mhz clock source for the A X88613 intern al
usage a nd a 25Mhz clock source for the 2 nd embedded Etherne t P HY usage. The AX88613 provides RX and TX clocks
(25Mhz output) in Rev erse MII mode or 50Mhz reference output in Reverse RMII m ode. These output clocks are derived
from the internal 100Mhz PLL circuit. The external 25Mhz crystal spec is listed in belo w table.
Parameter
Symbol
Typical Value
Nominal Frequency Fo
25.000000MHz
Oscillation Mode
Fundamental
Frequency Tolerance(@25℃) ±30ppm
Operation Temperature Range 0℃ ~ +70℃
Aging ±3ppm/year
The External 25MHz Crystal Specifications
For the 25MHz oscillator, its f eedback resistor isn’t integrated into the 25MHz oscillator, so it is necessary to add 1Mohm
feedback resistor on external circuit.
3.3 Built-in Power-On-Reset
The AX88613 integrates an in ternal power-on-reset circuit, wh ich can simplify the external reset circuitry on PCB design.
The power-on-reset circuit g enerates a reset pul se to reset sy stem l ogic after 1.8V core power ram ping up to 1.2V (typical
threshold). The extern al hardware reset input pin, RST_N, is fed directly to the input of the power-on-reset circuit an d can
also be used as additional h ardware reset source to reset t he system logic. The user can read CIRR [16] ChipInitDone bit
to check if the initialization of the chip is finished after reset back to high.
3.4 Built-in Voltage Regulator
The AX88613 integrates an internal 3. 3V to 1.8V low-dropout-volta ge and low-standby-current voltage regulator. T he
internal regulator provides up to 300mA of driving current for the 1.8V core/analog power of the chip to satisfy the
worst-case power consumption scenario. The internal regulator can operate in stand-by mode to consume less current
when the required driving current is less than 30mA. The stand-by mode regist e r i s loc at e d in PCR [31]. F or more details
on voltage regulator DC characteristic, please refer to 6.3.2.
Note: T he AX88613’s built-in 3.3V to 1.8V Voltage Regulator can be disabled easily by connecting the V18 p in to the
external 1.8V pow er source and conn ect a 0 Ohm resistor between VCC A H an d V18 pins. To disable the built-in voltage
regulator might reduce the AX88613 operating temperature about 5°C if heat is the key concern in your design.
23
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
3.5 Two Built-in 10/100M Base-TX Fast Ethernet DSP-Based PHY
There are two 10/100M Base-TX Fast Ether net DSP-Based PHY built in the AX88613. The basic feature is fully
compliant with 100 BASE-TX and 10 BASE-T PMD level standard (802.3u, FDDI-TP-PMD and 802.3)
‧ Supports MDI/MD IX aut o cr osso ver funct i on (Auto-MDIX)
‧ Supports parallel and serial control interface
‧ Supports MII interface
‧ DSP-based highly integrated embedded Ethernet twisted-pair symbol transceiver solution
‧ DSP-based adap tive line equalizer for superior immunity to noise and inter-symbol interface
‧ Full compliance with 100 BASE-TX and 10 BASE-T PMD level standards (IEEE 802.3u, FDDI-TP-PMD and IEEE
802.3)
‧ DSP-controlled symbol timing recovery circuit
‧ Baseline wander corrective circuits comp ensates data dependent offset due to AC coupling transformer
‧ Mult i functio n LED out put
‧ Full-duplex and Half-Duplex
Fig 7 Built-in 10/100M Base-TX Ethernet PHY architecture
Adaptive Equalizer
The cable’s amplitude and phase distortio ns will cause inter-symbol interface (ISI), which make clock and data recovery
impossible. This design eliminates these distortions by automatically adjusting the we ights of the feedback equalizer and
feed-forward equalizer to match the inverse of cable impulse response.
Baseline Compensation
The transmitter sends DC and AC signals as a pair . Bo th the receiving side and tr ansmitting side have a transformer that
blocks the DC signals. When the AC signal loses its DC component, the AC signal becomes distorted. This design
provides a circuit th at restores the DC com ponent to its corresponding A C signal and delivers them as a complete signal to
the receiver.
24
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
Link Monitor/Signal Detect
When the receiver receives a signal, the receiver will detect the signal’s level. If the signal level is above 400mV in
100BASE-TX mode, the receiver w il l send a Sig nal Det ector (SD) signal to the MII. If the level is below 400mV, the SD
signal will then be de-asserted in 722us.
Carrier Detect
The Physical Coding Sub-layer (PCS) checks Physical Medium Attachment (PMA) data to see if the packets meet IEEE
802.3-defined preamble (J/K/pac kets in 100BASE-TX) standards. If the packets are correct, the PCS sub-layer will start
to process the data and send it to MII.
4B/5B Coding
The Physical Coding Sub-layer (PCS) converts received/transmitted data according to IEEE 802.3-defined coding
standards, suc h a s 4B/5B and scrambling/de-scrambling.
MII Serial Manag ement Interface
The MII serial management interface (SMI) is the IEEE 802.3-defined serial coding control interface. Every register in
this design can be read or write accessed through this interface.
Auto-Negotiation
The 10/ 100M Base PHY can au t om at icall y neg otiat e its operating modes w ith oth er PHY devices over twisted pair cable
connections. Clause 28 of the IEEE 802.3u defines the auto negotiation mechanism.
Opmode [2]
Opmode [1]
Opmode [0]
Description
0
0
0
Auto-negotiation enable with all capabilities
0
0
1
Auto-negotiation enable with 100 BASE-TX FDX/HDX ability
0
1
0
Auto-negotiation enable with 10 BASE-T FDX/HDX ability
0
1
1
Reserved
1
0
0
Manual selection of 100 BASE-TX FDX
1
0
1
Manual selection of 100 BASE-TX HDX
1
1
0
Manual selection of 10 BASE-T FDX
1
1
1
Manual selection of 10 BASE-T HDX
Table 1 PHY Opera tion Mode Setting by PCR OPMODE [2:0]
Power-up Co ntrol Flow a nd Power-down Operation
In the power-down state, the PCR register power-down bit must be dr iven t o high; in all o ther states the power-down bit
must be driven to low. During the reset pe rio d, the PCR register Phyreset b it must be driven to low for about 500 ns and
then dri ven to high; I n no rmal c onditio n PCR Phyreset bit is d ri ven t o hi gh. F or B a nd-gap, PLL, and crystal PAD stable
issue, the power-on state must b e longer tha n 60 ms.
Fig 8 Power-up and Power-down Operation
Normal Power-Down Power-On Reset Normal
Power down0/1
PCR[1]/[17]
Phyreset0/1
PCR[0]/[16]
> 60 ms
25
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
Built-in 10/100 PHY( P0 or P1)
Tx Data from switch core
Rx Data Loop-back from TX
PMD/
PMA
PCS
MII
IF
MAC
Power-down mode through MD IO interface
Set PHY register BMCR bit 11 to high to enter th e power-down mode. At this time, PLL, band-gap, and XTLP (Crystal)
are alive, and the other clocks and blocks within PHY module a re off. This ope ration ca n go through MDIO int erfac e or
using register w rite process on MDIO regi ster. It is recomm ended pow er-down the PHY0 through MDIO to keep the core
clock alive so the switch operation and the register read/write control can still working.
PHY Loop-back Function Support
The loop-back function can be enabled by programmed the PHY BMCR register bit 14 loop-back enable bit through
MDIO interface or through the AX88613 PCR register loop-back bit. If this bit is set to one, then the entire data stream
received from MII TX interface will be forward to MII RX and returned back to switch core engine
TXOP/N
RXIP/N
Fig 9 Loop-back data path when internal loop-back function is enabled
Programmable LED Output Functio n
The A X88613 i s abl e to s upport a us er prog ram m a ble L ED ou tpu t f un cti on. The re are s ix LE D si gn al ou tpu ts from PHY:
speed, full-duplex, collision, RX activity, TX activity and link status. The user can assign any of these function outputs to
the LED pins by programmed LCR register.
Access PHY Registers
The AX 88613 support s direct control of th e inte rnal PHY throu gh soft ware conf iguration reg isters. The user can program
PCR to contr ol int ernal PHY 0 and PHY1 opera tions incl udin g PHY ID, O peration Mode, Loop-back, Power-dow n M ode
and software reset functions. The user can also access internal PHY register through MDIO interface or program PPMR
and MRCR CPU read/write register. The AX88613 converts these read/write setting into MDIO access command
indirectly.
Power-Saving Function
The AX 88613 su pports pow er-saving function on both internal PHY. When PCR [15] power-saving bit is set to zero, the
hardware logic will enable auto-detect function and r eset t he unused logic blo ck within the PHY module. If PCR [15]
power-saving bit is set to one then software takes the control and program the PCR [13] to enable the power-saving on
PHY0 and PCR [29] for PHY1.When the power-saving function is enable, the TX module will constantly send out idle
pulse and waiting to b e link up again if t he cable is plug in a gain.
26
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
3.6 Basic MAC Function
Full Duplex 802.3x Flow Control
In full duplex mode, the AX88613 supports the standard flow control mechanism defined in respect to IEEE 802.3x
standard. It enables th e stopping of rem ote node transmiss ions via a PAUSE f rame inform ation interaction. When space of
the packet buffer is less than the initialization setting threshold value, the AX88613 will send out a PAUSE-ON packet
with pause time equal to “0xFFF” to stop th e rem ote n ode trans mi ssi on. Then , the A X88613 w ill send ou t a PAU SE-OFF
packet with pause time equal to zero to inform the remote node to retransmit packet if it has enough space to receive
packets. When the AX88613 receives a PAUSE-ON packet from remote node, the AX88613 will finish the current
transmit process and wait for PAUSE-OFF packet to re-start transmit process.
Half Dupl e x B a ck Pressure Control
In h alf du plex m ode, t he A X88613 provides a backpr essu re contr ol me chan ism to av oid dropping packet s duri ng n etw ork
congestion. When the packet buffer size is less than the threshold value, the AX88613 will send a JAM pattern from the
low threshold value port if it senses an incoming packet, thus for cing a collision to make the remote node tr ansmission
back off and will e ffectively avoid dropping packets. And then the AX88613 will not send o ut a JAM packet until it has
enough sp a ce to receive one p acket. In GMCR register, if bit [23 ] ContinueSendJam bit is set to one then the AX88613
will never stop backpressure (Only for 10Mps).
Broadcast Storming Prevention
The AX88613 can enable broadcast storm filtering control by MaxStorm [1:0](defined in GMCR [15:14]). This allows
lim itation of the num ber of broadcast packets into the sw itch, and can be im plemented on a per port basis. The thres hold of
number of broadcast packets is set to 64/48/32. When enabled (i.e., MaxStorm [1:0] is not 00), each port will drop
broadcast packets (Destination MAC ID is ff ff ff ff ff ff) after receiving 64/48/32 continuous broadcast packets. The
counter will be reset to 0 every 1 second or when receiving any non-broadcast packets (Destin ation MA C ID is not ff ff ff
ff ff ff).
When disabled (i.e., MaxStorm [1:0] is 00), or the number of non-unicast packets received at the port is not over the
programmed threshold, the switch will forward the packet to all the po rts (e xcept the receiving po rt) within the VLANs
specified at the recei ving po rt.
Head-Of-Line Blocking Prevention
The AX88613 incorporates a simple mechanism to prevent Head-Of-Line blocking problems when flow control is
disabled. The AX886 13 will first check the destination address of the incoming packet when the flo w contr o l funct io n is
disabled. If the destination port is congested, then the AX88613 will discard this packet to avoid blocking the next packet
in line.
RX Packet filtering and TX CRC Regeneration
The AX88613 discards Ethernet fram e packet size less than 64 bytes and can be programmed to accept Ethernet frame size
up to MPL [10:0] in GMCR (defau lt valu e is 1522). The RX MAC w i ll drop error packets, CRC error packets, and pause
packets. Transmit MAC can re-calculate new CRC if GMCR [26] is set t o one.
Late Collision and Back-Off control
If a transmit packet experiences collision after 512 bit time of transmiss ion, it’s called late collision and the packet will be
dropped. The A X 88613 h a s an opt i on i n G MC R [13] NoAbor t to for MA C ne v e r abort when exceed maximum collision
limit if it is set to one and used only in half-duplex mode. GMCR [21] SuperMac bit can reduce back-off count and
collision when in half-duplex mode and set to one.
27
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
3.7 Basic Switch Function
Address Lookup Memory
The switch engine make s us e of internal SRAMs to store the routing address tables used. The internal tables are:
‧ 1024-Entry MAC address table
‧ 16-Entry VLAN tag table (full range 4K VLAN ID support)
‧ 16-Entry Multicast Filter Table to limit multicast traffic to Port 2 (Host port)
‧ 8-Entry IGMP Table
Routing-Table Format
The MAC address table is u sed for L2 forw arding, source address learning and read/write specif ied entries by the user. Its
format is list below.
Routing Table Entry
Description
MAC Address [47:0]
Ethernet MAC address [47:0] (Unicast or Multicast)
Aging_cntr [2:0]
Routing table agin g timer. The timer w ill automatically clear Valid bit when tim e out reach.
Valid
The forwarding information in this entry is valid if this bit is set to one.
SourcePort ID [1:0]
Source port number of this MAC address:
00 : Port 0, 01 : Port 1 or 10 : Port 2.
FilterSA Incoming packet will be dropped if received packet’s SA MAC matches with this MAC
address and this bit is set to be 1.
FilterDA Incoming packet will be dr opped if received packet’s DA MAC matches with this MAC
address and this bit is set to be 1.
Static
When set to one, The information of this entry will be frozen and will not be replace with
any new learned SA.
MC Drop
Drop received multicast packet if received multicast packet’s DA MAC matches with this
MAC address and the Static b it is set to one.
MC Port Map [2:0] Define Multicast Group Port Map. {Port2, Port 1, Port 0}
If received m ulticast packet’s DA MAC match es with this MAC address and Static bit is set
to one, the switch will forward this multicast packet to the same group defined in this field.
0
Fig 10 Rout i ng Ta ble F ormat
Routing Table Read/W r ite
The switch supports 1K MAC routing table entries for switching. Two-way d ynamic address learning is performed when
W ay 0 Way 1
Routing Table is a two-way 512X57
0 512 memory . A n d th e in dex method can be linear
or XOR hashing by setting up LGCR
[7] hash bit.
511 1023
Entry Format: 56 55 54 53:52 51 50:48 47:0
Unicast
MAC [0]=0
Static
FilterDA
FilterSA
SourcePort ID
Valid
Aging_cntr[2:0]
MAC Address
[47:0]
Multicast
MAC [0]=1
Static MC Drop MC Port Map[2:0] N/A MAC Ad dress
[47:0]
MAC[47:0]
Hashing
28
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
a good unicast packet is completely received. Total 1K routing table entry can be indirectly read or write through the
LRCR0 and LRCR1 registers.
1. Setup MAC address
2. Setup source port, page and filtering information for unicast MAC and MC Dr op, MC port map for multicast MAC
3. Set static bit for multicast MAC or unicast MAC that do n’t want to be aging out
4. Set Write_RT or Read _RT bit if write/read o peration is pe rformed.
5. Clear Write_RT or Read_RT b it once finish the command
The user can flush the ro uting table by enabl i ng Flush_RT bit within LRCR1 .
Example: Write an Entry int o the Ro uting Table
1. Setting up LRCR0 and L RCR1 register MA C inform ation include MAC_addr [47:0], source port ID, filtering control
and static bit value.
2. Enable write process b y setting the Write_RT bit to o ne.
3. Write 0 to the Wr ite _RT bit to clear write proc e ss.
MAC A ddress Learning and Aging
The AX88613 is able to automatically learning new MAC address and update source port, time stamp, and valid
information whenever receiving good frame with unknown source MAC address. The AX88613 provides an option to
lear n once or stop lea rning by configur ing LLCR. T he routing ta ble also has a pro grammab le aging out t imer i n LLCR
[24:16]. Default value is 0x1FF.and each step is about 1.34 second.
Only the learned address en tries are s ch eduled in t he ag i n g module. The addre s s aging func ti on is supported f or t opol og y
changes such as an address moving from one port to the other. That is, one station does not t ransmit an y packet for a period
of time. When this happens, the belonging MAC address will be aged out (removed) f rom the address table. The agin g out
time can be programmed automatically through the EEPROM or CPU write configuration, its d efault value is about 68 7
seconds. And aging function can enable or disable by the user. Normally, disabling aging fu nction is for security purpose.
Aging timer is located in LLCR [24:16].
VLAN Table
The VLAN tag table is used to determine the multiple outgoing ports for L2 broadcast packets and to tag the VLAN
identity onto each incoming untagged frame. There are 16 VLAN table entries located in the VER0 ~ VER15. Its format
is list in the following table.
VLAN Tab l e Entry
Description
Forward_map [2:0] Forwarding information for this VLAN ID.(1: Fo rward 0:Filter)
[0]: Port 0
[1]: Port 1
[2]: Port 2
Tag_map [2:0]
Output tag o r un-tag information for this VLAN ID.( 1: Tag, 0: Unt ag)
[0]: Port 0
[1]: Port 1
[2]: Port 2
VLAN ID [11:0]
Full range VLAN ID can be programmed here. Note: 0x000 and 0xFFF is reserved for
management purpose.
Valid
Valid bit for this VLAN ID and mapping information.
17 16:6 5:3 2:0
Valid VLAN ID [11:0] Tag_map [2:0] Forward_map [2:0]
Fig 11 VLAN Table Format
If the 802.1Q function is enabled, the switch engine will look-up this table and forward tag or un-tag packet to the
corresponding output ports. Once the 802.1Q is enabled then the user should not turn on port-based VLAN functio n on
LGCR [20 ].
IGMP Table
29
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
There are eight multicast IP entries in this table from IER0 to IER7. Its format is list below:
IGMP Table
Entry
Description
IP [27:0]
Lower 28 bits of IP address. Assume IP
address bi t [ 31:28] is 1110 (i.e.,
multicast IP
address).
Port_map [2:0]
Port mapping information
Valid
Valid bit
31
30:28
27:0
Valid
Port_map [2:0]
IP [27:0]
Fig 12 IGMP Table Format
When the IGMP snooping function is enabled, the switch engine will look-up this table and copy the packet to the
corresponding ports if the receiving packet is a multicast IP packet (IP [31:28]=1110), IP [27:0] is found in this table and
the valid bit is set to one.
Host Port Multicast Filter Table
There are 16 Multicast Filter entries in th is table f rom P2MFR0 to P2MFR15. If any one of the valid bits within the table
is set to one t hen any multicast packets forwarding to the host port whose DA MAC addre ss is not matc h with the valid
entry’s HM AC fie ld will be dropped on Host Port (Port 2). The multicast MAC entry in this table only co ntains last 23
MAC address bits (from bit [24] to bit [47]), which m eans only the last 23 bits will be compared. If none of the valid is set
then no multicast packet will be filtered.
The forwarding engi ne only sends multicast packets to the host port when all four of the following conditions are valid:
1. The inco ming packe t ’s DA MAC last 23 bits matches up with one of the 16 entry’s HMAC field [22:0],
2. DA MAC is a multicast packet
3. Source port information matches with the From Port 0 bit or the From Port 1 bit
4. Valid bit is set to o ne
An y mult i ca s t pa cket th at s upposed to forw ar d to t he host port (por t 2) n ot meet all th e s e four condit i on s will be dropped
if any of these entry has valid bit set to one.
NOTE: Assume the expected MAC address is 01-23-45-67-89-AB then the HMAC [22:0] should be 67-89-AB.
Multic ast Table
Entry
Description
MAC [22:0]
Lower 23 bits MAC address
From Port 0
Only allowed this multicast MAC from Port 0
From Port 1
Only allowed this multicast MAC from Port 1
Valid
Valid bit
25
24 23 22:0
Valid From Port 1 From Port 0 MAC [22:0]
Fig 13 Host Port Multicast Filter Table Fo rmat
30
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
Packet Filtering and L2 Forwarding Process
The switch uses a simple store-and-forward algorith m as a packet switching method. After receiving incoming packets, the
switch will store the packet to the embedded 32K byte packet buffer memory first. The forwarding engine will look up the
VLAN table, the Spanning Tree Status Table, the Address-Lookup Table (Routing Table), the Multicast Filtering Table,
the IGMP table and decide the forwarding ports. Only the good receiving packets will be forward. Conditions of good
packets are below:
1. CRC is correct.
2. 64 Bytes <= Packet Length <= Maximum Packet Length
3. SA MAC address and DA MAC address should not be the same
RX TX
Fig 14 Forwarding Process
The switch engine receives good Ethernet frame from the Receive MAC. The Fig 14 shows how the forwarding process
performs insi de the AX88 613 switching engine.
1. First if the receive Ethernet frame is a tag fram e and if 802.1Q function is enabled then the switch w ill go through the
VLAN table and chec k forwarding informatio n base d on the VLAN group information.
2. If 802.1D is enabled and spanning tree status is checked then the switch will decide whether to co ntinue forwarding
process or drop the packet.
3. The switch performs routing table look-up b ased on the DA MAC hashing i ndex approa ch.
4. The Host Por t Multicast Filter Table checks if the incoming multicast MAC address matches with any valid entries
found in this table. If DA is not a legal MAC entry f rom the expect source port and the table has valid entry, then the
packet will be dropped.
5. If IGMP is enable d, then the switch engine will forward the multicast packet if destination IP found in the table.
6. If sniffer function is enabled and the packet matches with the sniffer condition, then the packet will be copied to the
sniffer port.
7. The switch engine also examines the packet for security purpose. There are eight extra security MACs defined in the
AX88613 to enhance security function. Any illegal packet will be dropped if the packet cannot pass the internal
security check.
8. If the port mirror function is turned on then the incoming packet will be duplica te d to the mirror po rt.
Host Port Software Switching Function
The AX88613 also supports host port software switching function. When the GMCR [29] is set to one, all incoming
packets from port 0 and port 1 forward to the host port will be inserted an extra byte before CRC field to indicate source
port information. If GMCR bit [28] is set to one, then software will provide forwarding information in the last byte of
payload and the AX88613’s switch engine will decode last 2-bit information and forward to corresponding ports. T he
softwar e can take over the switch engine and control forwarding function. If the last two bits are 00 then the packet will
forward to port 0. If the last two bits are 01 then the packet will forward to port 1.
VLAN
Table
Check
Spanning
Tree State
Check
Routing
Table
Lookup
HostPort
Mult. IP
Filtering
IGMP
Table
Sniffer
Check
Security
Check
Port
Mirror
31
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
3.8 VLAN Support
Port-Based VLAN
The AX88613 supports three port-based VLAN groups to ease the administration of logical groups of stations that can
comm unicat e as if they w ere on the sam e LA N, and it can m ove, add or change nu mbers of these groups. This meth od can
effectively prevent the broadcast storming from interfering w ith the transm ission performance between ports. If port-based
VLA N i s en able d, th e ports belon ging t o di fferent g roups a re indepe n dent. On l y the desti n at i on port of broadcast packets
in the same group will be allowed. Furthermore, this method of the VLAN group dividing is very useful to avoid
unnecessary broadcast packets and increase security.
Overlapping port-groups are all owed during s ome operations. For exam ple, two VLA N groups can share an y port, and all
the packet- forw arding operation s between thes e tw o groups remain independent except for the overlapping port. Only t he
overlapping port can use the same destination MAC address for two different VLAN port-groups and receive bro adcast
packets from two different VLAN groups. The Port-based VLAN provide a very simple approach to VLAN function.
The user need to enable L GCR [20] Port-based VLA N ena ble bit an d program PVCR to set up port-based VLAN per-port
mapping informati on before using this function.
Tag-Based V LA N
Virtual LANs are used to form broadcast domains of hosts etc. on the network, thus ensuring that broadcast traffic is
limited. VLANs also add som e intra-networking security features. VLANs are identified within a 4 Byte tag attached to the
packet.
6 bytes
6 bytes
2 bytes
2bytes TAG Fie l d
DA [47:0]
SA [47:0]
81-00
3bits
1bits
12bits
----
Priority
CFI
VID [11:0]
Fig 15 802.1Q VLAN Tag Frame Format
There are two types of VLA N tagging options: Implicit and Explicit. Explicitly tagged packets are 802.1Q compatible. In
this case, the VL AN tag is already attached to th e incomi ng packet by the source. Im plicitly tagged packets have n o tag on
the inp ut, but a re tagge d in the AX88613. They are tagged based on the port, sub-net, MAC address or protocol of the
packet. If no tagging is required in the output (defined in the address look-up results), the AX88613 w ill de-t ag the pack et
before transmission.
According to 802.1Q (1998 p.39), packets can be untagged, priority-tagged or VLAN-tagged at the input, but only
untagged or VLAN-tagged at the output.
The VLAN classification is the first step to be performed before the VLAN table lookup. To classify a u n iqu e VID v alu e
to a received frame is defined as follows:
1. VLAN-tagged fram e: If the tag ged VID = 0 (i.e., Null VID or priority tag), then replaced w ith port's PVID value. Else
its tagged VID value i s us ed.
2. Non-VLAN-tagged frame: Append with por t's PVID val ue and Priority field. (Default PVID=0x001)
After the unique 12-bits VID is cla ssified, the AX88 613 then loo ks up the port mapping information in the VLAN table,
processes the incoming VLAN packet with the ingress/egr ess rule and then forward this packet to the valid destination
ports with specified tagging control process. NOTE: VID=0x000 and 0xFFF are reserved VLAN ID.
32
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
Ingress/Egress rule:
1. Ingress frame type control: to admit all frames or to admit only VLAN-tagged frames.
2. Ingres s fi ltering control: to filter the E ther net frame received fro m a port that is not included in the classified VLAN
group member. That is, if VLAN ID of this receiving port is not list in the VLAN table port mapping field then this
packet will be dropped.
3. Egress frame ty pe control: if this port is configured to be the untagged member set of VID entry then all the forwarding
packets to this port will passing the untag packets out. The VL AN table en try has a t ag-untag field to define whether
to tag or t o untag on specific output p orts.
The user needs to enable LGCR [22] 802.1Q enable bit, and build up VLAN table by filling in VLAN entry through
register wr ite op eration between VER0 (entry1) and VER15 (entry16) before processing VLAN function.
Ingre s s rule
1. Priority packet (VID = 0) is taken as untagged packet.
2. If (Untagged packet or priority packet)
{If (Tagged-frame only) then drop t his untagged packet.
Else
{If (Destination Po r t e xist on VLAN Table)
Forward this packet to Destination Port.
Else
Drop this packet
}
}
Note:
Untagged frame will be add ed VID and QoS filed, using the PVID & QoS setting of the receive port.
Priority Packet will be replaced it’s VID field with the PVID of the receive port, but n o chan g e t o QoS fi eld.
3. If (Tagged Frame)
{If the port that received this packet is not in member set of VID in this packet
{ If (Ingress filter disable)
{If (Destination Po rt exist on VLAN Table)
forward this packet to Destination Port.
else
drop this packet
}
else
drop this packet.}
else
{If (Destination Port exist on VLAN Table)
forward this packet to Destination Port.
else
drop this packe}
}
Egress rule:
If (this port in Untagged member set of this VID in this packet)
{Take the tag off and transmit this packet}
Else
{Tra nsmit this packet}
33
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
802.1Q-in-1Q Double Tagging Support
The AX88613 supports double tagging if the LGCR [15] QinQ enable bit is set to one. The QSR rgi_sptag [15:0] is
defined as service provider tag when
1. The Receiving Port is the Access Port
2. The Receiving Port is the Uplink Port and the receiving tag does not match with the QSR rgi_tpid [1 5:0] *
If both these conditions are true then service provider tag will be asserted.
Note: Make sure VLAN ID in rgi_tpid [11:0] is a valid entry and can be found on VLAN Table Entry.
When t he egress port i s an access port then the service provider tag will be removed.
The us er c an conf i g u r e a cce s s port or uplink port by pr og ra mmed addres s P0MC R / P1MC R / P2MC R [15] u pl i n k port bit.
RX Port Type
RX Frame Type
TX (Access Port)
TX (Uplink Port)
Access Port
Un-Tag
Untag
One Tag ( SP tag)
Access Port
One Tag ( tag)
One Tag ( tag)
Double Tag (SP tag + tag)
Access Port
Double Tag (tag1+tag2)
Double Tag (SP tag + tag2)
Triple T ag (SP tag+SP T ag+tag2)
Uplink Port
Un-tag
Un-Tag
One Tag ( SP tag)
Uplink Port
One ta g (tag==tpid)
Un-tag
One Tag ( SP tag)
Uplink Port
One tag (tag! = tpid)
One ta g (SP tag)
Double Tag (SP tag+tag)
Uplink Port
Double tag (tag==tp id)
One ta g (tag)
Double Tag (SP Tag + tag)
Uplink Port
Double tag (tag! =tpid)
Double tag (SP tag +tag)
Trip le Tag (SP tag+SP tag+tag)
Table 2 Double Tagging Access Port and Uplink Port TX operation
Table 2 shows how the AX88613 handle double-tagging functi on when RX port i s configured t o Access port or Uplink
port and receiving Ethernet frame is untag, one t ag, d oubl e-tag frame.
3.9 IEEE 802.1D Spanning Tree
The AX 88613 has t he capabi lity to s upport im plem en tation of th e IEEE 802.1D Spann ing Tree Protocol. A ll ports can be
programmed to be in the port state as required by the spanning tree protocol. If the Spanning Tree Protocol option is
enabled, BPDUs are identified and treated according to port state. All five states defined in IEEE 802.1 D are supported:
Blocking, Listening, Learning, Forwarding and Disab le d. The following is performed in the different states:
Blocking - No frame relay (to prevent f rame duplication due t o multiple paths ). Forwarding and learn in g are disabled
but BPDUs will still be received and sent to the p ro cessor. The Ethernet frame is forwarded to the CPU if it is a BP DU
fram e and the fram e is discarded otherw ise. All outgoing f rames except outgoing BPDUs will be m asked from the path to
the PHY.
Listening - Preparing to participate in frame relay. Forwarding and learning are disabled but BPDUs will still be
received and sent to the processor. That is, the frame is forwarded to the CPU if it is a BPDU frame and the frame is
discarded otherwise. All outgoing Ethernet frames except outgoing BPDUs will be masked from the path to the PHY.
Learning - Preparing to participate in frame relay. If the port is in the Learning State, all source addresses of the
incoming Ethernet frames f rom the PHY w ill be learned. All incoming Ethernet frames except incoming BPDUs from the
PHY will be discarded after being learned, all outgoing Eth ernet frames except outgoing BPDUs will be m asked from the
path to the PHY. That is, forwarding is disabled but learning is enabled. BPDUs are received and sent to the processor.
Forwarding - Participating in frame relay. If the port is in the Forwarding State, the frame is forwarded to the CPU if
it is a BPDU frame. All source addresses of the incoming Ethernet frames from the PHY will be learned and then
forwarded based on the switch routing decision. All outgoing Ethernet frames will be transmitted to the PHY.
Disabled. No p a rticipation in frame relay or Spanning Tree algorithm. Both forwarding and learning are disabled.
BPDUs are discarded.
34
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
The AX88613 pass all the BPDU packets to the CPU port and enable the CPU to implement the spannin g tree algorithm .
The default values are the Bridge group address and the All LANs bridge management group address according to
802.1D.The user can find Spanning Tree status bit information in PVCR [5:4](Port 2). [3:2] (Port1) and [1:0] (Port 0).
Note: Blo c king and Listening is the same ope r a tion for the AX88613.
3.10 QoS Operation
Based on market trends, networking increasingly demands support data, voice and video streams. The switch not only
controls data packet but also provides service of multimed ia data. The AX88613 provides four priority queues on each
port. The AX88613 identifies the packets as high priority based o n several types of QoS priority information:
• Port-based priority
• 802.1P/Q VLAN priority tag
• IPv4 TOS/IPv6 COS/DiffServ (DSCP ) prior ity information
Port-Based Priority (Port Pair Priority)
The AX88613 provides two Port-Pairs for bandwidth management. The user can assign any two ports as one Port-Pair
with internal registers setting . All traffic between these two defined port-pair ports’ packets will always map to the
configur ed p riori ty que ue in the PPMR [11:10]. That is, t he two Port-Pair ports will obtain more bandwidth than other
ports when congested. If PPMR AllBit is s et to one and Port Pair is defined to the same port number then all the traffic in
and out of the switch will for ward to this monitor po r t. Por t Pair control register is locate d in PPM R.
802.1P-Based Priority
When the 802.1P VLAN tag priority applies, the AX88613 recognizes th e 802.1Q VLAN t ag frames an d extracts the 3-bit
User-defined Priority information from the VLAN ta g. T he AX88613 has a programmable 8-to-4 priority-mapping table
to convert receiving VLAN tag frame’s 3 priority bits into one of the internal 4 queues. Therefore, VLAN tagged frames
with User-defined Priority value = 0~7 will be mapped to the AX88613 ‘s in t er n al queue i (i =0~ 3). The m appi ng table is
located in P0QMTR/P1QMTR/P2QMTR and can be update through register read/write or pre-configured in EEPROM.
IPv4/IPv6 Priority
The AX 88613 s u ppor ts bot h I Pv 4 an d I Pv6 Pri ori t y mappi n g to help diff ere n tial traffic pattern and improve QoS quality
between voice, data, multim edia, and VOIP and network m anagement. The IPv4 TOS (Type of Service) and the IPv6 COS
(Class of Service) table are located in QPTR.
The user can build an 8-to-4 QoS m apping table by filling in the mapping queue number (0-3). There is a global enable bit
to turn on the mapping table function and it is located in LGCR [1] COS_En and LGCR [2] TOS_En. The LGCR [0]
QoSSel is def ined w h ether to conv ert upper 3 bits [5: 3] or low er 3 bits [2:0] of COS/TOS as Priority table index. (Default
is upper 3 bits, w hich is IP Precedence) The VLA N tagged fram e and 6-bit DS-field in the IPv4 an d IPv6 fram e format are
shown below:
6 bytes
6 bytes
4 bytes
2 bytes
4 bits
4 bits
6 bits
DA SA 802.1Q Tag
(Optional) 08-00 Version
IPv4=0100 IHL TOS [0:5]=
DSCP field ----
Fig 16 IPv4 Frame Format
35
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
6 bytes
6 bytes
4 bytes
2 bytes
4 bits
6 bits
DA
SA
802.1Q Tag
(Optional)
86-DD
Version
Ipv6=0110
COS [0:5]=
DSCP field
----
Fig 17 IPv6 Frame Format
DiffServ-Based Priority
The AX88613 identifies TCP/IP Differentiated Services Code point (DSCP) priority information from the DSCP-field
defined in RFC2474, if TCP/IP's TOS/DiffServ (DS) based priority is applied. The DSCP field byte for the IPv4 is a
Type-of-Service (TOS) octet and for IPv6 is a Traffic-Class octet.
The recommended DiffServ Code point is defined in RFC2597 to classify the traffic into different service classes. The
AX88613 extracts the code point value of DSCP-fields from IPv4 and IPv6 packets, and recognizes the priority of the
incoming IP packet following user-defined QoS mapping table (DQR). Recommend mapping priority example is list
below:
High priority: if the DS-field = (EF, Expected Forwarding:) 101110
(AF, Assured Forwarding:) 001010; 010010; 011010; 100010
(Network Control:) 110000 and 111000
Low priority: if the DS-field = other values.
The 6-bit DSCP field with 64 possibilities can be fully decoded and mapped to internal four queues through register
setting. The DSCP mapping table is located in DQR0~DQR3 and total 64 DSCP level is able to assign to any queue from
0 to 3 within switch core engine. There is a Table mapping enable bit located in LGCR [3] DSCP _En t o turn o n DSCP
mapping functio n.
QoS Mapping Or de r and Flow
If the flow control is enabled then all the traff ic w ithin the port will m ap to queue 0, which m eans no QoS within that port.
By default,IPv4/IPv6 DSCP priority mapping > IPv6 priority mapping or IPv4 priority mapping > VLAN priority
mapping. If LGCR [8] VLAN_QoS_En is set to one then VLAN QoS priority mapping will override the mapping result.
There is a per-queue weighting register located in address P0QWR/P1QWR/P2QWR to program weighting on each
queue . The higher the weighting value, the more traffic bandwidth will be scheduled o ut from that queue.
Fig 18 Rx/Tx Bandwidth Filtering and QoS Map ping Data Flow
The AX88613 QoS flow and traffic shaping flow is shown in the Figure 18. The per-port ingress rate limit control will
drop the packets that exceed the ingress bandwidth threshold value defined in the register P0RLR [11:0], P1 RLR [11:0]
and P2RLR [11:0]. If LGCR 1P_En is set to one then receiving packet will reference QoS mapping table in the register
P0QMTR, P1QMTR and mapping t he VLA N QoS value to the i nternal queu e 0 ~ 3. If LGCR COS _En is enabled and the
receiving packet is an IPv6 packet then the COS map ping table located in the QPT R will convert the 3-bit QoS value to
one of the internal queues (0~3). If LGCR TOS_En is enabled and the incoming packet is an IPv4 packet then the TOS
mapping table located in the QPTR register will map the 3-bit QoS value to one of the internal queues. If LGCR DSCP_En
is enabled and the receiving packet is an IPv4 or IPv6 packet then 6-bit QoS (64 levels) mapping table located in the
DQR0/DQR1/DQR2/D QR3 register will map this QoS value to an internal assigned queue.
The DSCP mapping table has higher priority if both DSCP_En and TOS_En (or COS_En) are enabled. The RX Per queue
rate limit f ilter will f ilter out packets that exceed the per-queue thresh old register v alue def ined in t he regis ter P0RQR0/1,
P1RQR0/1 and P2RQR0/1.
Ingress
Rate
Limit
(Per port)
VLAN
QoS
Mapping
Table
COS/TOS/
Diff-Serv
Mapping
Table
Per-queue
Rate Limit
Filter
Packet
Buffer
Memory
Egress
Rate
Limit
Filter
36
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
The egress rate limit filter will make sure the output port or output queue traffic has its own bandwidth that constraint in the
per port threshold register P0RLR, P1RLR and P2RLR and per queue rate limit register P0TQR0/1, P1TQR0/1 and
P2TQR0/1.
Bandwidth Control Scheme
The band width control logic will set the maximum bandwidth that each port/queue can support. The AX88613 provides
12 bits programmable bandwidth setting from 0 to 12.5 M byte (100MBps) with 4K bytes pe r unit. In ha lf duplex mode ,
the receivin g side (ingress) will drop packe ts or sen d JAM if total receiving bytes exceed th e bandwidth threshold. On the
transmitting side (egress), if total transmit bytes goes over the threshold limit, then the AX88 613 will stop tra nsmitting
data out until rate limit timer is reach, and then transmit data again. The rate limit timer is located in
P0RLTR/P1RLTR/P2RLTR and default value is one second. The default ingress and egress rate limit value is 0xFFF
means no bandwidt h constraint on ingress port and egress por t.
Under full duplex m ode, if the receivin g data exceed the bandw idth threshold, the bandwidth control scheme w ill send the
802.3x PAUSE fram e out if Flow Control fun ction is enabled. If the receiving port turn off the flow control function, then
the bandwidth control scheme will drop the exceeding packets if receiving packets exceed the bandwidth threshold. The
AX88613 also supports both ingre ss and e gress per queues rate limit control from 0 to 100M Bps.
3.11 Security Operation
The AX88613 provides the following types of security functions:
‧ Port-based SA Restriction
‧ IEEE 802.1x Port-Based Authorization
‧ 802.1Q VLAN Ingress Check
‧ Rout i ng Ta ble security handli ng
‧ Eight Special Security Entry Restriction
Port-based SA MAC Restriction
The AX88613 provides source MAC address security support. When OneSAEn bits (LLCR [31:29]) is turned on, then the
configu re port will learn th e first receivin g packet’s SA MAC address and stop learnin g. The switch core will only receive
packets with the matched SA MAC address. Any packets with different SA MAC address will be dropp ed.
If LL CR [28:26] OneSARst bits is toggled from one to zero then the origin al secure SA MAC address will be reset and the
configure port will learn a new source MAC address again if OneSAEn bits is still turn on and make sure the “StopLearn”
bit in LGCR [5] is set to one when One SA function is enabled.
802.1x Port-Based Authorization
The AX88613 provides a global 802.1x enable bit in LGCR [21] and per port 802.1x function enable bits in
P0MCR/P1MCR/P2MCR [11] to turn on the 802.1x function. When 802.1x function is enabled, all the 802.1x frames
will forward to host/CPU port. The AX88613 will detect the 802.1x packet if the incoming packet’s Ethernet Type field is
0x888E or DA MAC address is 0x0180C2000003 and forward the 802.1x control packet to CPU or host port.
Port State
Unauthorized
Authorized
Receive EAPOL packets to CPU with
port information
Yes
Yes
Transmit EAPOL packets from CPU
(CPU has the ability to specify which
port to send EAPOL packets)
Yes
Yes
Receive normal p ackets
No
Yes
Trans mit normal packets
No
Yes
Table 3 IEEE 802.1x Port-Based Authorization
37
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
Note - use Et hern et Ty pe (0x 888E) an d spec ial M AC A ddress =0x 0180_C200_0003 t o ident ify EAPO L pack ets. That
is, the AX88613 only exam ine Ethernet ty pe field or DA MAC address. If Ethernet type is 0x888E or DA MAC addre ss
is 0x0180C2000003, then it is EAPOL 80 2.1x control packet.
802.1Q VLAN Ingress Check
If “IngressFilter” bit in PVCR [10:8 ] is set to one, the VLAN ingress checker will verify if the packet’s r eceiving port
informati on belo nging to the proper VLAN ID group. For example, if port 1 receives a tag frame with VID=4 and the
VLAN Table VID=4 entry‘ s port ma p information doesn’t include Port 1, th en if the IngressFilter function is enabled then
this frame will be dropped.
Routing Table Security Handl ing
1. Freeze Whole Routing Table
If the “StopLearn” bit in LGCR [5] is set to one, then all entries within the routing table will be freeze and stop learning
new MAC address and aging function will also be disabled. This mode could be used if increased security is required.
2. Freeze Specific Entry inside Routing Table
If the routing table entry’s “ Static” bit is set to one, then the entry’s MAC address will be fixed and will not be update by
any n ew learned MAC address. This mode could be us e d if increased security on some special MAC address is required.
3. Filter DA/SA matched Packet
If the “FilterEn” bit in LGCR [4] is turn on, then the Filter_DA and the Filter_SA control function in the routing table entry
wi ll be enabled. Any receiving packets ’s DA MA C address that match w ith the routing table entry ’s MAC address has thi s
Filter_DA bit set to one, then the forwarding engine will drop this packet. The same filter function can apply to the
Filter_SA bit. If the receiving SA MAC address has the same MAC address entry inside the routing table and its Filter_SA
bit is enabled then the forwarding engine will drop this packet.
The u ser can turn on DA or SA Match-and-Drop function on any entry within the routing table. For example, an Ethernet
frame who’s DA is 0x001234567800 w ill be dropped by the A X88613 if the routing table has an entry w i th MA C address
equal to 0x001234567800 and Filter_DA bit is set to one.
38
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
Eight Special Security M A C Ent ry Support
The AX88613 provides additional eight special MAC entries (SM0 CR ~ SM7 CR) for extra security protectio n support.
The user can use these eight special security MAC entries for their DA or SA Match-and-Drop filtering pro tection. For
example, the forwarding engine will drop any Ethernet packets with SA MAC a ddress equ al to 0x 055555555550 if one of
the Security MAC Entries set to SA Match-and-Drop mode with MAC address programmed to be 0x055555555550.
Please make sure Security MAC address and source port information is matched when p rogrammed these security MAC
address.
Registeter
Filter_DA
Filter_SA
Filter_Pair
Description
Security MAC0 ~ 7
1
0
0
Drop packet if DA match with Security MAC
Security MAC0 ~ 7
0
1
0
Drop packet if SA match with Security MAC
Security MAC0
Security MAC1
1
0
0
1
1
1
Drop packet if either DA match with Security MAC0 or
SA match with Security MAC1 (must enable by pair)
Security MAC2
Security MAC3
1
0
0
1
1
1
Drop packet if either DA match with Security MAC2 or
SA match with Security MAC3 (must enable by pair)
Security MAC4
Security MAC5
1
0
0
1
1
1
Drop packet if either DA match with Security MAC4 or
SA match with Security MAC5 (must enable by pair)
Security MAC6
Security MAC7
1
0
0
1
1
1
Drop packet if either DA match with Security MAC6 or
SA match with Security MAC7 (must enable by pair)
Security MAC0
Security MAC1
0
1
1
0
1
1
Drop packet if either SA match with Security MAC0 or
DA match with Security MAC1 (must enable by pair)
Security MAC2
Security MAC3
0
1
1
0
1
1
Drop packet if either SA match with Security MAC2 or
DA match with Security MAC3 (must enable by pair)
Security MAC4
Security MAC5
0
1
1
0
1
1
Drop packet if either SA match with Security MAC4 or
DA match with Security MAC5 (must enable by pair)
Security MAC6
Security MAC7
0
1
1
0
1
1
Drop packet if either SA match with Security MAC6 or
DA match with Security MAC7 (must enable by pair)
Table 4 Security MAC Filtering function table
Note1: When enable Filter_Pair function, please make sure MAC0 and MAC1 (or MAC2 and MAC3 or MAC4 and
MAC5 or MAC6 and MAC7) ‘s Filter_Pair b it both set to one.
Note2: When there is any conf lict betw een thes e eight secu rity MA Cs and routin g table entry , the security MAC w ill have
higher priority than the routing table entry if the same MAC found on both location.
3.12 RMON Counter Support
The AX88613 provides 30 counters to statistic events in each port for r emote network monitor. T he counters ar e listed
below. All counters are 32-bit wide except the Rx Byte c ounter and TX Byte counter, which are 64-bit. The p rior ity of a
read counter request from the host port is always higher than the updating process. All counters will be automatically
cleared in system-reset period or by setting the register RCR bit [4] ClrAllCounter to one.
Offset
Counter
Description
0x00
Rx Pa cket Counter
The total number of packets received (include bad packets)
0x01
Rx Good Packet Counter
The total number of good packets received.
0x02
Rx Byte Counter (low 32 bit)
The total number of bytes received (include bad packets).
0x03
Rx Byte Counter (high 32 bi t)
0x04
Rx Broadcast Packet Counter
The total number of good broadcast packets received.
0x05
Rx Multicast Packet Counter
The total number of good multicast packets received.
0x06
Rx PAUSE Frame Counter
The total number of PAUSE frames received.
0x07 Rx Packet Lengt h C ounter 1 The total number of packets received that length is less than 64 bytes
(include bad packets).
39
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
0x08
Rx Pa cket Lengt h C ounter 2
The total n um ber of packet s received th at length is 64 bytes (in clude bad
packets).
0x09 Rx Packet Length Counter 3
The total num ber of packets received that l ength is between 65 bytes and
127 bytes (include bad packets).
0x0A
Rx Pa cket Lengt h C ounter 4
The total number of packets received that length is between 128 bytes
and 255 bytes (include bad packets).
0x0B Rx Pa cket Lengt h C ounter 5 The total number of packets received that length is between 256 bytes
and 511 bytes (include bad packets).
0x0C
Rx Pa cket Lengt h C ounter 6
The total number of packets received that length is between 512 bytes
and 1023 bytes (include bad packets).
0x0D Rx Packet Length Co unter 7
The total number of packets received that length is between 1024 bytes
and maximum bytes (include bad packets).
0x0E
Rx Pa cket Lengt h C ounter 8
The total number of packets received that length is lo nger maximum
bytes (include bad packets).
0x0F
Rx CRC Error P acket Co unte r
The total number of packets with CRC error received.
0x10
Rx Alignment Er ror Pa cket Counter
The total number of packets with Alignment error received.
0x11
Fragment Error Counter
The total number of packets received th at are les s th an 64 by tes, bu t h as
an either CRC error or Alignment Error.
0x14
Tx Pac ket Counter
The total number of packets tra nsmitted or aborted.
0x15
Tx G ood Packet Counter
The total number of good packets transmitte d successfully.
0x16
Tx Byte Counter (low 32 bit)
The total number of bytes transmitted or aborted.
0x17
Tx Byte Counter (high 32 bit )
0x18
Tx Broadcast Packet Counter
The total number of good broadcast packets transmitted successfully.
0x19
Tx Multicast Packet Counter
The total number of good multicast packets transmitted successfully.
0x1A
Tx PAUSE F rame Counter
The total number of PAUSE frames transmitted.
0x1B
Tx Collision Counter
The total number of collisio ns oc c urr e d.
0x1C Tx Packet with one Collision
Counter
The total num ber of packets transm i tted succes sfu lly w hi ch experienced
one collision.
0x1D
Tx Pac ket with Multiple Collision
Counter
The total num ber of packets transm i tted succes sfu lly w hi ch experienced
multiple collisions.
0x1E Tx Excessive Collision Counter The total number of packets aborted due to experienced excessive
collisions.
0x1F
Tx Late Collision Counter
The total number of packets experienced late collisions.
Table 5 RMON Counter Mapping Table
RMON counter access
The AX88613 provides indirect access to all the RMON counters. The register RCR [14:8](RmonAddr [6:0]) provides
Port ID number (RmonAddr [6:5]) and the RMON counter offset address (RmonAddr [4:0]) and the register RDR
provides the RMON data information. A ll R MON coun ters can be clear th roug h RC R [4] RMON coun ter clear bit which
is write one clear bit.
For example, if the user likes to read the port 1 RX good packet counter value
1. Write 0x0000A100 to the RCR register
2. Read RDR register to get the po rt 1 RX good pa cket c ounter value
40
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
3.13 Layer 2/3/4 Sniffer Function Support
The AX88613 provides multi-layer sniffer function include source port or destination port, Layer 2 DA or SA MAC
address, Ethernet Packet Ty pe, VLAN ID, Lay er 3 IPv4 or IPv6 protocol and lay er 4 IPv4 or IPv 6 TCP/UDP sour ce port
number and destination port number. The user can program SFCR0 ~ SFCR1, define the sniffer port and monitor all kind
of sniffer packets in-and–out of switc h engine from the assi gned sni ffe r port.
The eight extra security MAC regis ters defined in SM0CR ~ SM7CR can al so provide the snif fer DA/S A match function
by enabled sniffer_DA, sniffer_SA or sniffer_Pair bits which is similar to the filter function list on the table 4.
The AX88613 can select the following types of packet and copy these user specify packets to the sniffer port. Please
reference SFCR0/SFCR1/SFCR2 register descriptions for more detail sniffer function usage.
1. Source port
2. Destinatio n port
3. Sourc e a nd D e stinatio n Port
4. DA MAC match
5. S A MAC match
6. Both DA MAC and SA MAC match
7. VLAN VID [11:0] match (user-defined sniffer VID, SFCR1 [27:16])
8. Layer 2 Ethernet Packet Type Sniffer Function
There are seven pre-defined Ethernet packet type and one user defined Ethernet packet to select.
Layer 2 Sniffer Type
(SFCR0 [31:24])
Ethernet Type
Field
Protocol Type
[0]
0x0806
ARP
[1]
0x8035
RARP
[2]
0x8847 or 0x8848
MPLS Unicast
MPLS Multicast
[3]
0x888E
802.1X
[4]
0x8137
IPX/SNAP
[5]
0x8040
NetBIOS
[6]
0x8863(default)
User -defined in USTR [15:0] (Default Type: PPP oE Discovery)
[7]
0x8864
PPPOE Session
Table 6 Layer 2 Sniffer Table
9. Layer 3 IPv4 Protocol Sniffer Function
IPv4 Snif fer Type
(SFCR1 [7:0])
Protocol Index
Protocol Type
[0]
ALL
(Ethernet Type=0x0800)
ALL IPv4 Packets
[1]
6
TCP
[2]
17
UDP
[3]
89
OSPF
[4]
46
RSVP
[5]
115(default)
User-defined in USTR [23:16] (Default: L2TP)
[6]
1
ICMPv4
[7]
2
IGMP
Table 7 IPv4 Sni ffer Table
41
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
10. Layer 3 IPv6 Protocol Sniffer Function
IPv6 Snif fer Type
(SFCR1 [14:8])
Protocol Index
Protocol Type
[0]
ALL
(Ethernet Type=0x86DD)
ALL IPv6 Packets
[1]
6
TCP
[2]
17
UDP
[3]
89
OSPF
[4]
46
RSVP
[5]
115(default)
User -defined in USTR [23:16] (Default: L2TP)
[6]
1
ICMPv6
Table 8 IPv6 Sni ffer Table
11. Layer 4 IPv4/IPv6 TCP/UDP Source Port or/and Destination Port number match
- Sniffer Source Port
- Sniffer Destination Port
- Sniffer b oth Source and Destinatio n Po rt
The AX88613 only supports one IPv4/IPv6 TDP/UDP User-defined Source Port and Destination Port number to
sniffer, which is located in SFCR2 [15:0] and SFCR2 [31:16].
The SFCR0 Sniffer Configuration register is list below:
[0]
[1]
[2]
[3]
[4]
[6]
[7]
[8]
[9]
[10]
[11]
[12]
[13]
[14]
Source
Port Dest.
Port SA
Match DA
Match VID
Match Packet
Type
Match
IPv4
TCP Src
Match
IPv4
TCP Dst
Match
IPv4
UDP Src
Match
IPv4
UDP Dst
Match
IPv6
TCP Src
Match
IPv6
TCP Dst
Match
IPv6
UDP Src
Match
IPv6
UDP Dst
Match
[15]
[16:17]
[18]
[19]
[20]
[21]
[22]
[23]
Sniffer
Enable
Sniffer
Port
Source
Port 0
Source
Port 1
Source
Port 2
Dest
Port 0
Dest
Port 1
Dest
Port 2
How to set up t he sniffer function?
1. Bit [15] Sniffer Enable need to be one
2. Define the sniffer po rt location in bit [ 17:16] where all the matched pa c kets will cope to this sniffer port
3. If [6] is set to one then check the following options
‧ SFCR0 L2_Type[7:0]: select multiple Layer 2 Ethernet type of packets from Table 6.
‧ SFCR1 IPv4_Type[7:0]: select multiple IPv4 protocols from Table 7.
‧ SFCR1 IPv6_Type[7:0]: select multiple IPv6 protocols from Table 8.
4. If bit [4] is set to one then check SFCR1 SnifferVI D for VLAN VID comparison
5. Sniffer equation: (AND any one from [0:1], [2:3], [4]) AND [6] AND (AND any one from [7:14]) AND
(AND any one from [18:23])
Note1: Any zero on Bit [0:4] and [6] will be removed from of this AND equation.
Note2: Any zero on [18:23] will be removed from the AND function
Note3: Only one source port number and destination number is supported. The IPv4 source port and destination
port function will has higher priority than the IPv6 if both turn on at the same time.
42
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
3.14 IPv4 IGMP and IPv6 ICMP/MLD Snooping
The AX88613 supports IPv4 IGMP (Internet Group Management Protocol) and IPv6 ICMP MLD (Multicast Listener
Discover y) snooping functi on.
IPv4 IGMP Snooping
The LG C R [13] I GMP_En need t o s et t o on e t o en abl e IPv4 IGMP snooping functi on. I f LG C R [14] IGMP_Mode is set
to one then all receiving IPv4 IGMP packets will only forward to CPU port. If LGCR [14] IGMP_Mode is s et to zero then
the switch engine will make a extra copy of the packet to CPU port plus normal forwarding process.
IPv6 Sno oping
The ITCR [7: 2] IPv6_Snooping configuration register defines a few different kind of IPv6 snooping function. The bit [7]
IPv6 snooping enable bit need to set to one if any of the configure bit fro m bit [2] to bit [6 ] is turn on. Please reference
ITCR register for further detail.
4 bits
8 bits
20 bits
Version
Traffic Class
Flow Label
2 bytes
1 byte
1 byte
Payload Length
Next Header
Hop Limit
4 bytes
Source IP Address [127:96]
Source IP Address [95:64]
Source IP Address [63:32]
Source IP Address [31:0]
Destination IP Address [127:96]
Destination IP Address [95:64]
Destination IP Address [63:32]
Destination IP Address [31:0]
Next header1
(If next header=0)
Payload
Fig 19 IPv6 Frame Format
Next Header/Next Header1
Protocol
0
Hop-by-hop Options (NOTE: special processing)
1
ICMPv4
43
Routing (Type0)
44
Fragment
51
Encapsulating Security Payload
58
ICMPv6
60
Destination Options
Table 9 Next Header Tab le
IPv6/ICMPv4 M ulticast Snooping
If ITCR bit [ 2] and bit [ 7] both set to 1 and the following conditions match then the packet will forward to CPU port.
‧ IPv6 Multicast packet
‧ Next header = 1 or next header =0 and next header1 = 1
‧ Hop Limit =1
43
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
IPv6/ICMPv6 M ulticast Snooping (MLD Snooping)
If ITCR bit [3] and bit [7] both set to 1 and the following conditions match then the packet will forward to CPU port.
‧ IPv6 Multicast packet
‧ Next header = 58 or next header =0 and next header1 = 58
‧ Hop Limit =1
IPv6/ICMPv4 Snooping
If ITCR bit [4] and bit [7] both set to 1 and the following conditions match then the packet will forward to CPU port.
‧ IPv6 packet
‧ Next header = 1 or next header =0 and next header1 = 1
‧ Hop Limit =1
IPv6/ICMPv6 Snooping
If ITCR bit [ 5] and bit [ 7] both set to 1 and the following conditions match then the packet will forward to CPU por t.
‧ IPv6 packet
‧ Next header = 58 or next header =0 and next header1 = 58
‧ Hop Limit =1
IPv6/Miscellaneous Snooping
If ITCR bit [ 6] and bit [ 7] both set to 1 and the following conditions match then the packet will forward to CPU por t.
‧ IPv6 packet
‧ Next header = 43, 44, 50, 51 and 60 or next header =0 and next header1 = 43, 44, 50, 51 and 60
‧ Hop Limit =1
3.15 Wake-On-LAN Function Support
The AX88613 supports three different kinds of wake-up mechanism: Link-Status Change, Magic Packet and Microsoft
Wake-Up Fram e detection . The user can program the WCR regi st er to conf ig u re an y of these three w ak e-up mecha ni s ms
on Port 0 and/or Port 1. The AX88613 provides the PME (Power Management Event) output pin to pass the information
to host processor. The polarity of PME signal can also configure in WCR [22:20]. They are active low, level high, level
low, pulse high and pulse low to select.
Port 0
Internet 1.Reset PME
2. Sleep
Power On/Off
Port 1 PME
Fig 20 Wake-On -LAN Application
AX88613
Power Supply
Processor
44
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
Remote Wake-up Process (Microsoft Wake-up Frame Mode)
The Fig 29 shows one of the Wake -On-LAN applications with the power supply control. The AX88613 can detect the
wake up eve nt and t he P ME si gnal will tri gger t he po wer supp ly to tur n on cor e pro cess a nd bri ng up the whole system
remotely.
The user can enable Microsof t Wake-u p fun ction, set the PME sign al polarities an d enable w akeu p frame detection m ode
first. Port 0 and Port 1 will detect Microsoft wake-up frame from the incoming traffic. When receiving the expected
wake-up fram e pattern, the AX88613 will tog gle the PME signal. On ce the power su pply is up, the processor or the sys tem
will be powered up and re-initialize the AX88613 to normal state. The processor can reset the PME signal and
programmed th e AX88613 back to th e wakeup f ra me detection mode. And th e power supply w il l tu rn of f th e core power
automatically.
Sleep Mode Process
The processor can turn on s leep m ode by w riti ng on e to the regis ter WCR bit [19] to clear the sleep m ode status an d w rite
one to WCR bit [17] to enter the sleep mode. The AX88613 will then disable the internal clock and power down both
internal PHY and s tay in the power sav in g st ate. The host processor can write address 0x1F4 with any valu e to exit sleep
mode and back to normal state.
Link-Status Change Dete ction
There are two internal PHY built-in the AX88613. Any time when the internal PHY’s PSR LinkDone0 or LinkDone1
status c hanges ( one-to-zero o r zero-to-one) and t he Link-Status Change W ake-up option in the WCR register b it [0 ] for
port 0 or bit [5] f or port 1 is e nabled, t hen the A X88613 w ill de tect a l ink-status ch ange w akeup even t and generate a v alid
PME signal to inform the host processor .
Mag ic Packet Detection
The Magic Packet technology is used to remotely wake up a sleeping or powered off PC on a network. The user can turn
on Magic Packet enable bit for port 0 and port 1 from the WCR regis ter bit [1] and bit [6]. Once th e AX88613 has been put
into the Magic Packet mode, it scans all incoming Ethernet frames addressed to the node for a specific data sequence,
which indicates to the controller that this is a Magic Packet frame.
A Magic Packet frame m ust also meet th e basic requirem ents for the Ethernet frame, such as SOURCE MAC ADDRESS,
DESTINATION MAC ADDR ESS (w hi ch m ay be the receiv ing station' s IEEE address or a MULTICAST address which
includes the BROADCAST address), and good CRC. The specific sequence consists of 16 duplications of the IEEE
address of this node, with no breaks or interruptions. This sequence can be located anyw here within the packet, but must be
preceded by a sy n chronizati on s tream . The sy nchron ization stream allow s the scan nin g st ate m achin e to be mu ch sim pler.
The syn ch ronizat ion s tream is defined as 6 bytes of 0xFF. The device will also accept a BROADCAST frame, as long as
the 16 duplications of the IEEE address matches the address of the machine to be awakened. If the IEEE address for a
particular node on the network is 0x112233445566, then the AX88613 scans for the data sequence
(Assuming an Ethernet Frame):
DA + SA + Mis c. + F F FF FF F F F F FF 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22
33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55
66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 11 22 33 44 55 66 + Misc. + CRC.
There are no other restrictions on a Magic Packet frame. For instance, the sequence could be in a TCP/IP packet, an IPX
packet, etc. The fram e may be bridged or routed across the network, with ou t aff ectin g its ability to wake up a node at the
destination of the frame.
If the AX88613 scans a frame and does not find the specific sequence shown above, it discards the frame and takes no
further action. If the controller detects the data sequence, however, then it alerts the PC's power management circuitry to
wake up the system.
45
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
A Wake-up fram e is a s pecial data packet contai n in g th e Eth ern et address of th e remote network card. Somewhere in this
frame should exist a byte stream (magic sequence) composed by, at the least, 16 times the repetition of the Ethernet
address and preceded by a synchronization stream of 6 bytes of 0xFF.
The following steps provide a simple way to set-up Magic Packet Detection process.
1. Enable EnMagicPa c ket bit in WCR bit [1] for Por t 0 and bit [6 ] for Po r t 1
2. Program expected repeat MAC address for Port 0 (P0DAR0 [31:0] and P0DAR1 [15:0]) and for Port 1 (P1DAR0
[31:0] and P1DAR1 [15:0])
Microsoft Wake-up frame Detection
The AX88613 su pports three program mable filter ru les that help to locate the expected pattern within the receiving packet.
If the Microsof t wakeup frame detecti on mode is enabled (in D1 state), the remote wakeup function receives all Ethernet
fram es and ch ecks each fram e again st th e enabled filter patterns and recogn izes th e f rame as a remote wak e-up frame if it
passes the MAC address filtering and CRC value match.
The AX88613 uses a programmable byte mask and a programmab le pattern offset for each of the three supported filters.
The AX88613 also provides an option to cascade three programmable filters together. The thr ee pattern detectors can
operate simultaneously or sequentially based on the cascade register within the WCR Encascade0 [1:0] or Encascade1
[1:0].
The byte m ask is a 32-bit field that specifies wh ether the next 32 contiguous bytes right after the offset location sh ou l d be
calculated CRC valu e or not. If bit [j] in th e by te m ask is set to one, then the detection logic will calculate the byte [offset
+j]’s CRC value. Once the detection logic scans through all the mask location and calculates all the mask bytes’ CRC32
value. The calculated CRC value will be compare against to the expected CRC value in P 0WCR and P 1WCR’s rgi_crc
value to decide if the receiving frame has the expected pattern.
The WSR register defines both port 0 and port 1 three offset index registers. Each unit in the offset register represents a
double word offset (four bytes). For example, if P0_offset0 is 0x1 then the first mask byte will start from the fourth byte
location. If filter 0 and filter 1is cascade and P0_offset1 is 0x2 then the second mask byte will start from the 44th byte
location. (4x1+ 32 + 2x4 = 44)
1) If En_cascade0/1 [1:0] = 00 (No cascade)
P0/P1_en_da_cmp
i j k
32 bytes vs. mask bits
Filter 0:
P0/P1_offset0 [3:0] 32 mask bits vs 32 bytes
Filter 1:
P0/P1_offset1 [3:0]
32 mask bits vs 32 bytes
Filter 2:
P0/P1_offset2 [3:0]
1. First, make sure receive CRC is good.
2. If WSR [15] P0_en_da_cmp is set to one, then compare receive DA MAC [47:0] against expect MAC [47:0]
in P0DAR0 and P0DAR1 register value.
3. The three wake-up filter index will move to its offset starting position i , j, k.
Where i = P0_offset0 [3:0] x 4, j =P0_offset1 [3:0] x 4 and k =P0_offset2 [3:0] x 4
DA SA Payload CRC
100…………….111
101010…………001111
01100………0011
46
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
4. From i, j, k to i+31, j+31, k+31 byte position, scan through the next 32 bytes data and calculate CRC32 if
corresponding mask bit is set to one. For example if Port 0 P0WMR make register is 0xC000_0003, then
filter0 will only calculate i, i+1, i+30 , a nd i+ 31 CRC value.
5. Compare rgi_crc register (P0WCR) against calculated CRC value from filter 0, 1, and 2.
6. If any one matches, then it is consider as remote wake-up frame and the AX88613 will enable PME event
signal.
2) If En_cascade0/1 [1:0] = 11 (cascade all three filters together)
P0/P1_en_da_cmp
i j k
32 bytes vs. mask bits
Filter 0:
P0/P1_offset0 [3:0] P0/P1_offset1[3:0] P0/P1_offset2[3:0]
1. First make sure receive CRC is good.
2. If WSR [15] P0_en_da_cmp is s et t o one, th en compare receive DA MA C [47:0] agains t ex pect MA C [47:0]
in P0DAR0 and P0DAR1 register value.
3. The filter index will move to its offset starting position i, j, k. where i = P0_offset0 [3:0] x 4, j = i + 32 +
P0_offset1 [3:0] x 4 and k = j + 32 + P0_offset2 [3:0] x 4
4. From i, j, k t o i+31, j+31, k +31 byt e positi on, sc an th rough the n ext t hree 32 by te da ta and ca lcul ate CRC 32 if
correspon ding ma sk bit is se t to one. For exam ple if Port 0 address 10Ch m ake reg ister is 0xC000_0003, then
filter0 will only calculate i, i+1, i+30 , a nd i+ 31 CRC value.
5. Compare rgi_crc register (P0WCR) against the calculated CRC value from filter 0.
6. If calculated CRC matches the CRC register value, then it is considered a remote wake-up frame and the
AX88613 will enable the PM E e vent signal.
The user can use the AX88613’s cascade function, en_da_cmp DA match function and the three mask registers to
generate any kind of match pattern they need and create their own wake-up frame.
3.16 Power management
The AX 88613 s u pport s power-saving modes to allow applications to minimize power co nsumption. Ther e is o ne normal
operation power state, D0 and two power saving states: D1 wake-up mode, and D2 sleep mode. The Wake-On-LAN
Configuration Register (WCR) is able to enable these pow er man agemen t modes. In D 1 power savin g state, the AX88613
supports Wake-on-LAN function. In D2 power saving state, the AX88613 will power dow n all functional block and clocks
to minim ize power consumption. After a wakeup event, the AX88613 will revert back to the normal operation power s tate.
When the AX88613 is in either D1 or D2 power saving mode, the host port can write “Clear Sleep Mode Register”
(SMER) and return the AX88613 back to the D0 state. The Power is reduced to v arious modules by disabling the cl ocks as
outlined in the tab le below.
AX88613
D0
(Normal Mode) D1
(Wake-up Mode) D2
(Sleep Mode)
Core Cl ock
On
On
Off
Interface
On
Off
Off
WOL Logic
On
Rx Block On
Off
PHY
On
On
Off
Table 10 Power Management Statuses
DA MAC SA MAC Payload CRC
100…………….111
101010…………001111
01100………0011
47
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
3.17 Auto-Polling Function
The AX88613 supports PHY management through the serial MDIO/MDC interface. That is, the AX88613 accesses
related regis ter of PHYs via MDIO/MDC in terface after pow er on reset. The AX88613 wil l periodically and conti nuously
poll and update the link status and link partner’s ability which include speed, duplex mode, and 802.3x flow control
capable status of the connected PHY devices through MDIO/MDC serial interface.
3.18 Port Mirroring
Port mirroring is a fun ction that mirrors or duplicates traffic from one “m irror port” to a “target port”. The m irror or target
port mirroring can be set up for each p or t indi vidua lly to mirr or e ither inc oming p acke ts o r outgo ing p acke ts. Inco ming
and outgoing traffic need not be mirrored to the same port. Unidirectional traffic on a port can only be mirrored to the
target port. Only correct packets that would normally be handled by the AX88613 will be mirrored. Packets with CRC
errors and collision fragments etc are not mirrored.
- Ingress mirroring: Traffic received on a port will be sent to the mirror port as well as to any other addressed port.
- Egress mirroring: Traffic sent out on a port will also be sent to the mirror p ort.
3.19 Serial EEPROM Protocol
The serial EEPROM interface is responsible for reading configuration data automatically from the external serial
EEPROM or writing data from internal register into external serial EEPROM. The AX88613 can automatically be
configured from an external serial EEPROM. If a properly conf igured EEPROM is detected by the AX88613 at pow er-up,
hard reset or host set a reload EEPROM request, the co nsta nts o f E EP RO M data will be auto loading to internal register
address space automatically. The EEPROM size is detected during the reset cycl e from pull-up/pull-down state found on
CS and S K pins.
EEPROM size
SK
CS
N/A (default)
PD
PD
1K-bit (93C46)
PD
PU
2K-bit (93C56)
PU
PD
4K-bit (93C66)
PU
PU
Table 11 EEPROM Size mapping (PD: tie a 4.7K ohm pull-dow n res i s tor to groun d PU: ti e a 4.7K oh m pull-up resistor
to VCC)
EEPROM Data Format:
Address [9:2]
Data [31:24]
Data [23:16]
Data [15:8]
Data [7:0 ]
48
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
EEPROM Address
EEPROM Contents
0
Address [9:2] (1
St
W rite Command)
1
Data [31:24]
2
Data [23:16]
3
Data [15:8]
4
Data [7:0 ]
5
Address [9:2] (2nd Write C ommand )
6
Data [31:24]
7
Data [23:16]
8
Data [15:8]
9
Data [7:0 ]
:
:
:
:
:
:
All the registers within the AX88613 are 32-bit wide that’s why the EEPROM data format includes an address [9:2] and
four bytes of the data. The AX88613 will auto-configure the internal registers based on the write commands in the
EEPROM contents after the hardware reset operation or the reload EEPROM operation. The Address [9:2] field defines
the internal register address [9:2], and the 4-byte data fields define the write data value. For example, when the Address
[9:2] = 0x8C and the Data [31:0] = 0x12345678, the AX88613 will write 0x12345678 into the address 0x230 P0ADR0
register.
Note: If the data format is “00 -- -- -- --“ and “FF -- -- -- --“ then they will be translated to wait state comm and. The address
[9:2] = 0x00 and 0xFF are reserved. The AX88613 will ignore this write command and continue move to next write
command. Normally, the EEPROM reader will read through all 1K/2K/4K pre-defined address space. There is a speed-up
end of the EEPROM read process c om m an d by as sig n the addres s [9:2] to 0x00 and the Data [31:0] to 0x 84149435 at the
end of the last valid write command.
The following is a sample EE PROM code to set up the internal PH Y 0 and PHY1 function.
01 11 01 10 01 //Turn On PHY0 and PHY1 (PCR)
37 03 04 02 01 //Enable LED function (LCR)
0F 90 18 80 2C //Set Phy0 Reg24.2=1 internal PHY Link speed-up (MRCR)
00 00 00 00 00 // Wait
0F 91 18 80 2c //Set Phy1 Reg24.2=1 internal PHY Link speed-up (M RCR)
00 00 00 00 00
0F 90 10 10 00 //Set Phy0 Reg16.12=1 internal PHY Link speed-up (MRCR)
00 00 00 00 00
0F 91 10 10 00 //Set Phy 1 Reg16.12=1 internal PHY Link speed-up (MRCR)
00 00 00 00 00
0F 90 04 05 E1 //Set Phy0 Pause capability (MRCR)
00 00 00 00 00
0F 91 04 05 E1 //Set Phy1 Pause capability (MRCR)
00 00 00 00 00
0F 90 00 33 00 //Restart Phy0 Auto-negotiation (MRCR)
00 00 00 00 00
0F 91 00 33 00 //Restart Phy1 Auto-negotiation (MRCR)
00 00 00 00 00
50 33 00 11 10 //Auto polling enable (ACR)
00 00 00 00 00 / or apply “00 84 14 94 35” End Command here to stop process
: : : : :
00 00 00 00 00 // End of 1K/2K/4K pre-defined EEPROM address space
49
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
4.0 Interface
4.1 MII Interface
The AX88613 host port to external PHY connection when configured to MII mode.
1.5Kohm Pull-Up
4.1.1 MII Interface Set-Up Procedure
Enable MII Interface on Port 2:
1 Set ICR bit [18] and bit [30] to 1.
ICR [18]: Port 2 MII Enable
ICR [30]: Port 2 MDIO Link Enable
2 Set ACR bit [26] and bit [30] to 1 and Define Port 2’s PHY ID on ACR [20:16]
ACR [26]: Enable Port 2 Auto-Polling Function
ACR [30]: Enable Port 2 Auto-Flow-Control-Polling Function
AX88613
P2_RX_DV
P2_RXD3
P2_RXD2
P2_RXD1
P2_RXD0
P2_RX_CLK
P2_TX_CLK
P2_TX_EN
P2_TXD3
P2_TXD2
P2_TXD1
P2_TXD0
P2_RX_CRS
P2_RX_COL
P2_MDC
P2_MDIO
External PHY
RX_DV
RXD3
RXD2
RXD1
RXD0
RX_CLK
TX_CLK
TX_DV
TXD3
TXD2
TXD1
TXD0
RX_CRS
RX_COL
MDC
MDIO
50
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
4.2 Reverse MII Interface
1.5Kohm Pull-Up
4.2.1 Reverse MII Interface Set-Up Procedure
Enable Reverse MII Interface on Port 2:
1 Set ICR [26] to 1. (Enable Reverse MII Interface on Port 2)
2 Set P2SMR0 bit [31] and bit [30] to 1 and Define Port 2’s MDIO PHY ID on P2SMR0 [4:0]
P2SMR0 [31]: Port 2 Slave-MDIO Interface Enable
P2SMR0 [30]: Port 2 Slave-MDIO PHY Address Enable
3 Set P2MCR Port 2’s MAC Configuration Register
P2MCR [0]: Enable Port 2 MAC Function
P2MCR [3]: Port 2 Speed Configuration
P2MCR [4 ]: Por t 2 Duplex Selection
P2MCR [7]: Port 2 Flow-Contro l ON /O FF Sele c tion
P2MCR [8]: Port 2 CRC Check Functio n
AX88613
MII0/1_TX_EN
MII0/1_TXD3
MII0/1_TXD2
MII0/1_TXD1
MII0/1_TXD0
MII0/1_TX_CLK
MII0/1_RX_CLK
MII0/1_RX_DV
MII0/1_RXD3
MII0/1_RXD2
MII0/1_RXD1
MII0/1_RXD0
MII0/1_RX_CRS
MII0/1_RX_COL
MII0/1_MDC
MII0/1_MDIO
External MAC MII of
Embedded MCU
TX_EN
TXD3
TXD2
TXD1
TXD0
TX_CLK
RX_CLK
RX_DV
RXD3
RXD2
RXD1
RXD0
MDC
MDIO
RXCRS
RXCOL
51
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
4.3 RMII and Reverse RMII Interface
4.3.1 RMII Mode Reference connection
1.5Kohm Pull-up
The AX88613 can use either external system reference 50 MHz clock (figure above) or internal generated 50MHz
reference clock (figure below) as RMII reference clock input.
1.5Kohm Pull-up
4.3.2 RMII Interface Set-Up Procedure
Enable RMII Interface on Port 2:
1 Set OCSR [7:0] = 0x41 to use internal 50MHz clock divide from core 100MHz.
2 Set ICR [30], [14], [6] and [2] to 1.
ICR [2]: Enable Port 2 RMII internal clock
ICR [6]: Enable Port 2 RMII Interface MUX
ICR [14]: Enable Port 2 RMII 50MHz Reference Clock O utput
ICR [30]: Enable Port 2 MDIO Communication Interface
3 Set ACR bit [26] and bit [30] to 1 and Define Port 2’s PHY ID on ACR [20:16]
ACR [26]: Enable Port 2 Auto-Polling Function
ACR [30]: Enable Port 2 Auto-Flow-Control-Polling Function
AX88613
P2_CRSDV
P2_RXD1
P2_RXD0
P2_REFCLK
P2_TX_EN
P2_TXD1
P2_TXD0
P2_MDC
P2_MDIO
External PHY
CRS_DV
RXD1
RXD0
REF_CLK
TX_EN
TXD1
TXD0
MDC
MDIO
50MHz OSC
AX88613
P2_CRSDV
P2_RXD1
P2_RXD0
P2_REFCLK
P2_REFCLKO
P2_TX_EN
P2_TXD1
P2_TXD0
P2_MDC
P2_MDIO
External PHY
CRS_DV
RXD1
RXD0
REF_CLK
TX_EN
TXD1
TXD0
MDC
MDIO
52
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
4.3.3 Reverse RMII Mode Reference connection: (Only support 100 Full Duplex mode)
The AX88613 is able to generate a 50MHz clock output after power on reset plus 2ms delay.
1.5Kohm Pull-Up
The AX88613 can use system ‘s 50MHz reference clock as Reverse RMII reference clock source.
1.5Kohm Pull-Up
AX88613
P2_TX_EN
P2_TXD1
P2_TXD0
P2_REFCLK
P2_REFCLKO
P2_CRSDV
P2_RXD1
P2_RXD0
P2_MDC
P2_MDIO
External MAC MII of
Embedded MCU
TX_EN
TXD1
TXD0
TX_CLK
CRS_DV
RXD1
RXD0
MDC
MDIO
AX88613
P2_TX_EN
P2_TXD1
P2_TXD0
P2_REFCLK
P2_CRSDV
P2_RXD1
P2_RXD0
P2_MDC
P2_MDIO
External MAC MII of
Embedded MCU
TX_EN
TXD1
TXD0
TX_CLK
CRS_DV
RXD1
RXD0
MDC
MDIO
50MHz
OSC
53
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
4.3.4 Reverse RMII Interface Set-Up Procedure
Enable Reverse RMII Interface on Port 2:
1 Set OCSR [7:0] = 0x41 to use internal 50MHz clock divide from core 100MHz.
2 Set P2SMR0 bit [31] and bit [30] to 1 and Define Port 2’s MDIO PHY ID on P2SMR0 [4:0]
P2SMR0 [31]: Port 2 Slave-MDIO Interface Enable
P2SMR0 [30]: Port 2 Slave-MDIO PHY Address Enable
3 Set ICR [14], [10], [6] and [2] to 1.
ICR [2]: Enable Port 2 RMII internal clock
ICR [6]: Enable Port 2 RMII Interface MUX
ICR [10]: Enable Reverse RMII Ending option if necessary
ICR [14]: Enable Port 2 RMII 50MHz Reference Clock Output
4 Set P2MCR Port 2’s MAC Configuration Register
P2MCR [0]: Enable Port 2 MAC Function
P2MCR [3]: Port 2 Speed Configuration
P2MCR [4 ]: Por t 2 Duplex Selection
P2MCR [7]: Port 2 Flow-Contro l ON /O FF Sele c tion
P2MCR [8]: Port 2 CRC Che ck Function
54
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
4.4 Slave Serial Peripheral Interface (SPI)
The Serial Peripheral Interface (SPI) controller provides a full-duplex, synchronous serial communication interface (4
wires: SPI_CLK, SS, MOSI, MISO) to flexibly w ork with nu merous peripheral devices or micro-controller with SPI. The
SPI slave controller supports comm un ication w ith external m icro-controller with SPI master. Please turn off auto-polling
functio n in ACR register when start SPI re a d or write opera tion to avoid the co nflict.
SPI Data Write Format :
A[1
A[0
D[7]
D[6
D[5
D[4
D[3
D[2]
D[1
D[0]
write_data[7:0]write_data[7:0]addr[11:0]writewrite
SPI_CLK
MOSI
MISO
SS
Fig 21 SPI Single Wr ite Timing Diagram
A[11]
A[0]
D[7]
D[0]
D[7]
D[0]
addr+N's data... addr+N's data...
addr ' s dataaddr ' s data
addr[11:0]writewrite
SPI_CLK
MOSI
MISO
SS
Fig 22 SPI Burst-Write Timing Diagram
{1000, Addr[11:0]} Data0 ………………………
55
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
SPI Data Read Format :
A[11
A[0]
D[7]
D[6]
D[5]
D[4]
D[3
D[2]
D[1
D[0]
read_data[7:0]read_data[7:0]
addr[11:0]readread
SPI_CLK
MOSI
MISO
SS
Fig 23 SP I Single Read T iming Diagram
A[11]
A[0]
D[7]
D[0]
D[7]
D[0]
addr+N's data... addr+N's data...addr ' s dataaddr ' s data
addr[11:0]
readread
SPI_CLK
MOSI
MISO
SS
Fig 24 SPI Burst-Read Timing Diagram
{0100,Addr[11:0]} Data0[7:0] Data1[7:0]……………………… DataN[7:0]
56
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
5.0 Internal Register Configuration
5.1 AX88613 Register Definition
The following set of registers allows read/write operations through host port interface for direct managing and
programming of the AX88613.
Address
NAME
Description
Default V alue
0x000
CIRR
Chip ID and Reset Register
0x9D000003
0x004
PCR
PHY0/PHY1 Configur atio n R egiste r
0x11009000
0x008
PSR
PHY0/PHY1 Status Register
0x0101BFBF
0x00C
GMCR
Global MAC Configuration Register
(Max packet size, Broadcast Storm Setting)
0x048735F2
0x010
LGCR
Layer 2 Global Configuration Register (1Q, 1D, 1X, 1P, IGMP..)
0xFC000000
0x014
LLCR
Layer 2 Le arning/ Aging/OneSA Contro l Register
0x01FF7777
0x018
LRCR0
Layer 2 Routing Table Entry Read/Write Co nfiguration Register 0
0x00000000
0x01C
LRCR1
Layer 2 Routing Table Entry Read/Write Co nfiguration Register 1
0x00000000
0x020
PVCR
802.1D, Port-based VLAN Control Register
0x00000000
0x024
SFCR0
Sniffer Function C onfiguratio n Registe r 0
0x00000000
0x028
SFCR1
Sniffer Function C onfiguratio n Registe r I
0x00000000
0x02C
SFCR2
Sniffer Function C onfiguratio n Registe r 2
0x00000000
0x030
QPTR
QoS Priority Mapping Tab le Register
0xFA50FA50
0x034
QSR
802.1Q-in-1Q(Double-Tagging) Setup Register
0x81000000
0x038
PPMR
Port Pair and M D C Contro l Register
0x00310000
0x03C
MRCR
MDIO Read/Write Confi gurati on Regis ter
0x00000000
0x050
SM0CR0
Security Mac 0 Control Register 0
0x00000000
0x054
SM0CR1
Security Mac 0 Control Register 1
0x00000000
0x058
SM1CR0
Security Mac 1 Control Register 0
0x00000000
0x05C
SM1CR1
Security Mac 1 Control Register 1
0x00000000
0x060
SM2CR0
Security Mac 2 Control Register 0
0x00000000
0x064
SM2CR1
Security Mac 2 Control Register 1
0x00000000
0x068
SM3CR0
Security Mac 3 Control Register 0
0x00000000
0x06C
SM3CR1
Security Mac 3 Control Register 1
0x00000000
0x070
SM4CR0
Security Mac 4 Control Register 0
0x00000000
0x074
SM4CR1
Security Mac 4 Control Register 1
0x00000000
0x078
SM5CR0
Security Mac 5 Control Register 0
0x00000000
0x07C
SM5CR1
Security Mac 5 Control Register 1
0x00000000
0x080
SM6CR0
Security Mac 6 Control Register 0
0x00000000
0x084
SM6CR1
Security Mac 6 Control Register 1
0x00000000
0x088
SM7CR0
Security Mac 7 Control Register 0
0x00000000
0x08C
SM7CR1
Security Mac 7 Contro l Register 1
0x00000000
0x090
VER0
VLAN Enrty 0 Register
0x00000000
0x094
VER1
VLAN Enrty 1 Register
0x00000000
0x098
VER2
VLAN Enrty 2 Register
0x00000000
0x09C
VER3
VLAN Enrty 3 Register
0x00000000
0x0A0
VER4
VLAN Enrty 4 Register
0x00000000
0x0A4
VER5
VLAN Enrty 5 Register
0x00000000
0x0A8
VER6
VLAN Enrty 6 Register
0x00000000
0x0AC
VER7
VLAN Enrty 7 Register
0x00000000
0x0B0
VER8
VLAN Enrty 8 Register
0x00000000
0x0B4
VER9
VLAN Enrty 9 Register
0x00000000
57
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
0x0B8
VER10
VLAN Enrty 10 Register
0x00000000
0x0BC
VER11
VLAN Enrty 11 Register
0x00000000
0x0C0
VER12
VLAN Enrty 12 Register
0x00000000
0x0C4
VER13
VLAN Enrty 13 Register
0x00000000
0x0C8
VER14
VLAN Enrty 14 Register
0x00000000
0x0CC
VER15
VLAN Enrty 15 Registe r
0x00000000
0x0D8
ITCR
IGMP Table Rea d/Write Control Register
0x00000000
0x0DC
LCR
LED Control Register
0x00000000
0x0E0
RCR
RMON Control Register
0x00000000
0x0E4
RDR
RMON Data Register
0x00000000
0x0E8
DQR0
DSCP QoS Mapping Table Register 0
0x00000000
0x0EC
DQR1
DSCP QoS Mapping Table Register 1
0x00000000
0x0F0
DQR2
DSCP QoS Mapping Table Register 2
0x00000000
0x0F4
DQR3
DSCP QoS Mapping Table Register 3
0x00000000
0x0F8
ISMR
Interrupt Status and Mask Register
0xFFFF0000
0x100
USTR
User-Defined Sniffer Packet Type Register
0x73738863
0x104
WCR
Wake-On-LAN Configuration Register
0x00500000
0x108
WSR
Wake-On-LAN Setup Register
0x00000000
0x10C
P0WMR0
Port 0 Wake-On-LAN Wake -up Frame Mask Register 0
0x00000000
0x110
P0WMR1
Port 0 Wake-On-LAN Wake-up Frame Mask Register 1
0x00000000
0x114
P0WMR2
Port 0 Wake-On-LAN Wake -up Frame Mask Register 2
0x00000000
0x118
P0WCR0
Port 0 Wake-On-LAN Wake -up Frame CRC Register 0
0x00000000
0x11C
P0WCR1
Port 0 Wake-On-LAN Wake -up Frame CRC Register 1
0x00000000
0x120
P0WCR2
Port 0 Wake-On-LAN Wake -up Frame CRC Register 2
0x00000000
0x124
P1WMR0
Port 1 Wake-On-LAN Wake -up Frame Mask Register 0
0x00000000
0x128
P1WMR1
Port 1 Wake-On-LAN Wake -up Frame Mask Register 1
0x00000000
0x12C
P1WMR2
Port 1 Wake-On-LAN Wak e-up Frame Mask Register 2
0x00000000
0x130
P1WCR0
Port 1 Wake-On-LAN Wake -up Frame CRC Register 0
0x00000000
0x134
P1WCR1
Port 1 Wake-On-LAN Wake -up Frame CRC Register 1
0x00000000
0x138
P1WCR2
Port 1 Wake-On-LAN Wake -up Frame CRC Register 2
0x00000000
0x13C
OCSR
Output Clock Select Register
0x00000000
0x140
ACR
Auto-polling Control Registers
0x70000000
0x144
ECR
EEROM Contro l Registers
0x00000000
0x148
BLCR
Boot Loader Control Register
0x00000000
0x14C
IOCR
IO Pad Control Register
0x00000000
0x150
IER0
IGMP Entry 0 Register
0x00000000
0x154
IER1
IGMP Entry 1 Register
0x00000000
0x158
IER2
IGMP Entry 2 Register
0x00000000
0x15C
IER3
IGMP Entry 3 Register
0x00000000
0x160
IER4
IGMP Entry 4 Register
0x00000000
0x164
IER5
IGMP Entry 5 Register
0x00000000
0x168
IER6
IGMP Entry 6 Register
0x00000000
0x16C
IER7
IGMP Entry 7 Registe r
0x00000000
0x1A0
P2SMR0
Port 2 Slave MDIO Register 0
0x00000001
0x1A4
P2SMR1
Port 2 Slave MDIO Register 1
0x78293100
0x1A8
P2SMR2
Port 2 Slave MDIO Register 2
0x0DE105E1
0x1AC
P2SMR3
Port 2 Slave MDIO Register 3
0x00000000
0x1B0
P2MFR0
Port 2 Multicast Filter Register 0
0x00000000
0x1B4
P2MFR1
Port 2 Multicast Filter Register 1
0x00000000
0x1B8
P2MFR2
Port 2 Multicast Filter Register 2
0x00000000
0x1BC
P2MFR3
Port 2 Multicast Filter Register 3
0x00000000
0x1C0
P2MFR4
Port 2 Multicast Filter Register 4
0x00000000
0x1C4
P2MFR5
Port 2 Multicast Filter Register 5
0x00000000
0x1C8
P2MFR6
Port 2 Multicast Filter Register 6
0x00000000
0x1CC
P2MFR7
Port 2 Multicast Filter Register 7
0x00000000
58
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
0x1D0
P2MFR8
Port 2 Multicast Filter Register 8
0x00000000
0x1D4
P2MFR9
Port 2 Multicast Filter Register 9
0x00000000
0x1D8
P2MFR10
Port 2 Multicast Filter Register 10
0x00000000
0x1DC
P2MFR11
Port 2 Multicast Filter Register 11
0x00000000
0x1E0
P2MFR12
Port 2 Multicast Filter Register 12
0x00000000
0x1E4
P2MFR13
Port 2 Multicast Filter Register 13
0x00000000
0x1E8
P2MFR14
Port 2 Multicast Filter Register 14
0x00000000
0x1EC
P2MFR15
Port 2 Multicast Filter Register 15
0x00000000
0x1F0
ICR
Interface Configuration Register
0x00000000
0x1F4
SMER
Sleep Mode Exit Register
0x00000000
0x1FC
GTCR
General Purpose Timer Configuration Register
0x00000000
0x200
P0MCR
Port 0 MAC Configuration Register
0x00000100
0x204
P0QMTR
Port 0 802.1p QoS Mapping Table Register
0x0000FA50
0x208
P0QCR
Port 0 802.1Q Co nfi guration for UnTag Fr ame Register
0x00000001
0x20C
P0RQR0
Port 0 RX Queue0/1 Rate Limit Control Register
0x0FFF0FFF
0x210
P0RQR1
Port 0 RX Queue2/3 Rate Limit Control Register
0x0FFF0FFF
0x214
P0TQR0
Port 0 TX Queue0 /1 Rate Limit Control Register
0x0FFF0FFF
0x218
P0TQR1
Port 0 TX Queue2 /3 Rate Limit Control Register
0x0FFF0FFF
0x21C
P0RLR
Port 0 Rate Limit Register
0x0FFF0FFF
0x220
P0RLTR
Port 0 Rate Limit Timer Register
0x05F5E100
0x224
P0FCR
Port 0 Flow Control High/Low watermark Register
0x00001428
0x228
P0QWR
Po rt 0 Per Queue Weighting Register
0x0000FFFF
0x230
P0DAR0
Port 0 DA MAC Address Regist er 0
0x00000000
0x234
P0DAR1
Port 0 DA MAC Address Registe r 1
0x00000000
0x240
P1MCR
Port 1 MAC Configuration Register
0x00000100
0x244
P1QMTR
Port 1 802.1p QoS Mapping Table Register
0x0000FA50
0x248
P1QCR
Port 1 802.1Q Co nfi guration for UnTag Frame Register
0x00000001
0x24C
P1RQR0
Port 1 RX Queue0/1 Rate Limit Control Register
0x0FFF0FFF
0x250
P1RQR1
Port 1 RX Queue2/3 Rate Limit Control Register
0x0FFF0FFF
0x254
P1TQR0
Port 1 TX Queue0 /1 Rate Limit Control Register
0x0FFF0FFF
0x258
P1TQR1
Port 1 TX Queue2 /3 Rate Limit Control Register
0x0FFF0FFF
0x25C
P1RLR
Port 1 Rate Limit Register
0x0FFF0FFF
0x260
P1RLTR
Port 1 Rate Limit Timer Register
0x05F5E100
0x264
P1FCR
Port 1 Flow Control High/Low watermark Register
0x00001428
0x268
P1QWR
Po rt 1 Per Queue Weighting Register
0x0000FFFF
0x270
P1DAR0
Port 1 DA MAC Address Regist er 0
0x00000000
0x274
P1DAR1
Port 1 DA MAC Address Regist er 1
0x00000000
0x280
P2MCR
Port 2 MAC Configuration Register
0x00000100
0x284
P2QMTR
Port 2 802.1p QoS Mapping Table Register
0x0000FA50
0x288
P2QCR
Port 2 802.1Q Configuration for UnTag Frame Register
0x00000001
0x28C
P2RQR0
Port 2 RX Queue0/1 Rate Limit Control Register
0x0FFF0FFF
0x290
P2RQR1
Port 2 RX Queue2/3 Rate Limit Control Register
0x0FFF0FFF
0x294
P2TQR0
Port 2 TX Queue0 /1 Rate Limit Control Register
0x0FFF0FFF
0x298
P2TQR1
Port 2 TX Queue2 /3 Rate Limit Control Register
0x0FFF0FFF
0x29C
P2RLR
Port 2 Rate Limit Register
0x0FFF0FFF
0x2A0
P2RLTR
Port 2 Rate Limit Timer Register
0x05F5E100
0x2A4
P2FCR
Port 2 Flow Control High/Low watermark Register
0x00001428
0x2A8
P2QWR
Po rt 2 Per Queue Weighting Register
0x0000FFFF
0x2B0
P2DAR0
Port 2 DA MAC Address Regist er 0
0x00000000
0x2B4
P2DAR1
Port 2 DA MAC Address Regist er 1
0x00000000
Table 12 Register Mapping Table
59
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
5.1.1 Chip revision ID and Reset Register (CIRR)
Address 0x000
Bit Name
Default
Value
R/W
Function
[2:0] Chip_mode 011 R Chip_mode: (read only)
011: SPI interface
[3]
Reserved
0
R
Reserved
[5:4] Prom_mode 00 R EEROM mode: EEROM memory size (read only)
00: NO EEROM
01: 1K-bit (93C46)
10: 2K-bit (93C56)
11: 4K-bit (93C66)
Please reference Table 11 for detail information.
The host CPU should read this value first to know the maximum address
size
of the EEPROM device before read/write or clear the EEPROM
data through
ECR register. The EEPROM size i s detected during the power-on
reset from
pull-up or pull-down state found on CS and SK pins.
[6]
Reserved
0
RW
Reserved
[7]
Reserved
0
R
Reserved
[11:8]
Chip_rev [3:0]
0010
RW
Chip revision ID
[15:12]
Reserved
0000
R
Reserved
[16]
ChipInitDone
0
R
Chip Initialization process finished (read only)
Chip Initialization process includes all the internal embedded
SRAM
initialization proc ess and EEPROM load ing process. T he host
CPU s hould
constantly keep polling this bit to check if the AX88613 is st
ill in
initialization process before read or write operation into
any internal
registers.
1: Complete the whole chip initialization pr ocess
0: Still waiting the whole chip initialization process to be done
The host CPU need to poll this bit first to confirm the
AX88613 exit the
initialization process after the following situation:
1. Power-on process
2. Back from power down state like the D1 state or the D2 state
3. Reload the EEPROM data (set Boot_En=1 in BLCR)
[23:17]
Reserved
0x00
R
Reserved
[24]
Reserved
1
RW
Always set to one when wri te CIRR
[25]
Reserved
0
R
Reserved
[27:26]
Reserved
11
RW
Always set to “11” when write CIRR
[28]
Wrst_n
1
RW
Switch core (exclude WOL related logic) reset, active low
1: Normal (Default)
0: Reset switch core
This bit used to reset the AX88613 switch core block for power down
functio n. Before the chip enter the D2 sleep mode, the CPU should set this
bit to zero to reset sw itch core block, and then enter the
D2 sleep mode. A fter
exit the D2 sleep mode, the CP U should set this bit to 1 to let the
AX88613
switch core function to nor mal work state.
[30:29]
Reserved
00
R
Reserved
[31] Chip rese t 1 RW Whole Chip Software Reset
1: Normal (Default)
0: Reset the whole chip
60
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
5.1.2 PHY0 /PHY1 Configuration Register (PCR)
Address 0x004
Bit
Name
Default
Value
R/W
Function
[0]
Phy reset0
0
RW
PHY0 r e set signal. Act ive lo w and s hould be longer than 500ns.
1: Normal
0: Reset internal PHY0 (Default)
The host CPU should write one to enable PHY0 back to normal state.
[1]
Power down0
0
RW
PHY0 Po wer Down. Active high.
1: PHY0 power down
0: Normal (Default)
NOTE: PHY0 Power down will turn off core clock and shut down the chip.
[2]
Reserved
0
R
Reserved
[3]
Loopback0
0
RW
PHY0 Loop-Back mode. Active high.
1: PHY0 Look-back enable
0: PHY0 Loop-back disable (Default)
If the value is changed, new setting will effective after Phy_reset0 is r eset.
[6:4] Opmode0 000 RW PHY0 Operation mode
000: Auto-negotiation mode
001: Auto-negotiation with 100 BASE-TX FDX/HDX ability
010: Auto-negotiation with 10 BASE-T FDX/HDX ability
011: Reserved
100: Manual selection of 100 BASE-TX FDX
101: Manual selection of 100 BASE-TX HDX
110: Manual selection of 10 BASE-T FDX
111: Manual selection of 10 BASE-T HDX
If the value i s changed, new sett ing will effective after Phy_reset0 is reset.
[7]
Reserved
0
RW
Always set to zero
[12:8]
Phyid0
10000
RW
Programmable PHY0 ID Re gist ers. This addre ss i s used when multiple PHY
are accessed through management interface. If the value is changed , new
setting will effective after Phy_reset0 is reset. The default value is 10000.
[13] PowerSaving0 0 RW PHY0 Power Saving Mode
1: PHY Power Saving State
0: Normal State (Default)
[14]
Reserved
0
R
Reserved
[15] SWPowerSaving
1 RW Software Power S aving Control
1: Software Control the internal PHY Power Saving State (Default)
0: Hardware Power Saving State Auto-detect function Enable
[16] Phy reset1 0 RW PHY1 reset signal. Active l ow and sho uld b e longer tha n 500ns.
1: Normal
0: Reset internal PHY1 (Default)
The host CPU should write one to enable PHY1 back to normal state.
[17]
Power down1
0
RW
PHY1 Po wer Down. Active high.
1: PHY1 power down
0: Normal (Default)
[18]
Reserved
0
RW
Reserved
[19]
Loopback1
0
RW
PHY1 Loop-Back mode. Active high.
1: PHY1 Look-back enable
0: PHY1 Loop-back disable (Default)
If the value is changed, new setting will effective after Phy_reset1 is reset.
[22:20] Opmode1 000 RW PHY1 Operation mode
000: Auto-negotiation mode
001: Auto-negotiation with 100 BASE-TX FDX/HDX ability
010: Auto-negotiation with 10 BASE-T FDX/HDX ability
61
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
011: Reserved
100: Manual selection of 100 BASE-TX FDX
101: Manual selection of 100 BASE-TX HDX
110: Manual selection of 10 BASE-T FDX
111: Manual selection of 10 BASE-T HDX
If the value i s changed, new sett ing will effective after Phy_reset1 is re set.
[23]
Reserved
0
R
Always set to zero
[28:24]
Phyid1
10001
RW
Programmable PHY1 ID Re gist ers. This addre ss i s used when multiple PHY
are accessed through management interface. If the value is changed , new
setting will effective after Phy_reset1 is reset. The default value is 10001.
[29]
PowerSaving1
0
RW
PHY1 Power Saving Mode
1: PHY Power Saving State
0: Normal State (Default)
[30]
Reserved
0
R
Reserved
[31]
Rgi_standby
0
RW
Regulator stand-by mode enable bit. Allowed range 1.8 ~ 3.3 Volt
1: Stand-by mode
0: Normal operation
62
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
5.1.3 PHY0/PHY1 Status Register (PSR)
Address 0x008
Bit
Name
Default
Value
R/W
Function
[0]
Speed0
1
R
PHY0 Link Speed Status
0: 100MBps
1: 10MBps
[1]
Duplex0
1
R
PHY0 Full Duplex Mode Sta tus
0: Full Dup l ex Mo de
1: Half Duplex Mode
[2]
Reserved
1
R
Reserved
[3]
RX0
1
R
PHY0 Receive activity
0: RX traffic passing
1: No Traffic
[4] TX0 1 R PHY0 Transmit activity
0: TX traffic passing
1: No Traffic
[5]
COL0
1
R
PHY0 Co llisio n Status
0: Collision Detect
1: No Collision
[6]
Link0
0
R
PHY0 Link St atus
1: Link up
0: Link D own
[7]
Reserved
1
R
Reserved
[8]
Speed1
1
R
PHY1 Link Speed Status
0: 100MBps
1: 10MBps
[9]
Duplex1
1
R
PHY1 Duplex Mode Status
0: Full Dup l ex Mo de
1: Half Duplex Mode
[10]
Reserved
1
R
Reserved
[11]
RX1
1
R
PHY1 Receive activity
0: RX traffic passing
1: No RX Traffic
[12] TX1 1 R PHY1 Tran smit activity
0: TX traffic passing
1: No TX Traffic
[13]
COL1
1
R
PHY1 Co llisio n Status
0: Collision Detect
1: No Collision
[14]
Link1
0
R
PHY1 Link St atus
1: Link U p
0: Link D own
[16:15]
Reserved
11
R
Reserved
[17]
Cable_Off0
0
R
PHY0 Cable Off Status
0: Normal State
1: PHY0 Cable Off
[24:18]
Reserved
0x40
R
Reserved
[25]
Cable_Off1
0
R
PHY1 Cable Off Status
0: Normal State 1: PHY1 Cable O ff
[31:26]
Reserved
0x00
R
Reserved
63
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
5.1.4 Global MAC Configuration Register (GMCR)
Address 0x00C
Bit
Name
Default
Value
R/W
Function
[10:0]
MPL
0x5F2
RW
Programm able m axim u m packet si ze allow ed to be received range from 64 to
2047.Default value is 1522.
[11]
Reserved
0
R
Reserved
[12]
Reserved
1
RW
Always set to one
[13] NoAbort 1 RW Force the internal
MAC never abort when exceed maximum collision limit if
this bit is set to one and used only in half duplex mode
1: Active
0: Disable
[15:14]
MaxStorm
00
RW
Broadcast Storm control
This function enables each port to drop broadcast packet when continuous
received broadcast packet exceed the following pre-define limit numbers
00: Disable Broadcast Storm control
01: 32 Broadcast frames
10: 48 Broadcast frames
11: 64 Broadcast frames
[19:16]
Reserved
0111
RW
Reserved
[20]
Reserved
0
R
Reserved
[21]
SuperMac
0
RW
Reduce back-off count and collision when MAC is in half duplex mod e if set
to one
[22]
PTO
0
RW
Pause Type Only:
Receive MAC will only detect Eth ernet Type= 0x8808
and OP code = 0001 as
Pause frame if this bit is set to one.
1: Enable
0: Disable
[23] CSJ 1 RW Continue Send Jam: Never Stop Backpressure when set to one (
Only for
10Mps)
1: Enable
0: Disable
[24]
Reserved
0
R
Reserved
[25]
Reserved
0
RW
Reserved
[26] GenCRC 1 RW Enable the generation of CRC.
1: MAC TX will recalculate CRC
0: NOT append CRC
[27]
Int_hl
0
RW
Set Interrupt polarity.
1: Active high
0: Active low
[28]
Reserved
0
RW
Reserved
[29]
Reserved
0
RW
Reserved
[30] Cnt_Preamble 0 RW Add 8 preamble bytes when calc ulate rate limit count if this bit is set to one.
1: Count preamble bytes
0: Disable
[31]
Reserved
0
RW
Always set to zero.
64
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
5.1.5 Layer 2 Global Configuration Register (LGCR)
Address 0x010
Bit
Name
Default
Value
R/W
Function
[0]
QoSSel
0
RW
Select lower3 bit of COS/TO S fi eld as Qo S Value when COS/TOS_En is o n
and this bit is set to one
. Otherwise, COS/TOS upper 3 bits will be the default
QoS value.
1: Select [2 :0] as QoS index value
0: Select [5 :3] as QoS index value
[1]
COS_En
0
RW
Enable Qo S mapping t able (convert from eight queue s t o four queues) for
IPv6 frame Traffic class (TC) field .
If QoSSel=1, then TC [4:2] will be the QoS entry to the mapping table.
If QoSSel=0, then TC [7:5] will be the QoS entry to the mapping table.
COS mapping table is located in QP TR.
1: IPv6 COS QoS mapping table enable
0: Disable
[2]
TOS_En
0
RW
Enable QoS mapping table (convert from eight queues to four queue s) for
IPv4 frame Type of Service (TOS) field.
If QoSSel=1, then TOS [4:2] will be the QoS entry to the mapping table .
If QoSSel=0, then TOS [7:5] will be the QoS entry to the mapping table .
TOS mapping table is loc a te d in QPTR.
1: IPv4 TOS QoS mapping table enable
0: DIsable
[3]
DSCP_En
0
RW
Enable DSCP QoS Mapping table for IPv4/IPv6 TOS/COS [7:2] if [1] or [2]
are also enabled. There are 64 QoS level start from ToS/TC [7:2]=0 to
ToS/TC [7:2]=63 when DSCP i s enabled. DSCP M a pping table is locate d in
DQR.
Note: QoS priority DSCP > COS/TO S > VLAN and make sure either
COS_En or TOS_En is also enabled.
1: DSCP mapping enable
0: Disable
[4] Filter_En 0 RW
Enable Filtering packet when SA or DA match in Routing Table or Security
Mac. If this bit and DA filter bit in Routing Table entry both set to one then
the
packet will be dropped if DA MAC match. If this
bit and SA filter bit in
Routing Table entry both set to one then
the packet will be dropped if SA
MAC match.
If this bit and DA filter bit in Security MAC entry both set to one then
the
packet will be dropped if DA MAC matches. (Please reference SM0CR
~
SM7CR Security MAC table) If this
bit and SA filter bit in Security MAC
entry both set to one then the packet will be dropped if SA MAC matches
.
(SM0CR ~ SM7CR Security MAC table)
1: Routing Table Filter Function Enable
0: Disable
[5]
Stop_Learn
0
RW
Disable Le arning a nd Aging of Layer 2 Routing Tab le,
If DA is not found in the Layer 2 Rout ing Table, then this packet will be
dropped. No SA MAC will be learned and NO MAC entry will be aged out
once this bit is set to one
1: St op Le arning a nd aging disable
0: Disable
[6]
ARPtoCPU
0
RW
Send ARP Packet to CPU por t when this bit is set to one.
1: Enable ARP packet to CPU port
0: Disable
[7]
Hash
0
RW
Hashing method used in the AX88613 internal 2-way 512byte Routing Table
lookup al gorithm.
0: Linear hashing (Index [8:0]=MAC [8:0] a s Routing table inde x)
1: XOR hashing (Index [8:0] = MAC [44:36] ^ MAC [35:27] ^ MAC [26:18]
65
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
^ MAC [17:9] ^ MAC [8:0])
[8]
VLAN_QoS_En
0
RW
VLAN QoS priority will be higher than IPv4/IPv6 TOS/COS if this bit is set to
one. Else QoS mapping priority will be DSCP > ToS/TC > VLAN
Note: If the Flow Control bit is set to one then QoS will always be 0 (map to
queue 0).
1: VLAN Ta g QoS ha s hi gher p rio rity than I Pv4 / IPv6/DSC P
0: Disable
[9]
Reserved
0
RW
Always set 0 when write GMCR register.
[10]
MCoverVLAN
0
RW
Multicast packet to tra nsmit over VLAN boundary. Effective only when 802.
is enabled.
1: Enable
0: Disable
[11]
Reserved
0
RW
Reserved
[12]
CtrlPktToCPU
0
RW
CtrlPktToCPU =1, Control Pa c ket (DA [47:0] = 0x0180_C200_0000~
0x0180_C200_00FF) will forward to CPU Port only.
CtrlPktToCPU =0, Control Pa c ket (DA [47:0] = 0x0180_C200_0000~
0x0180_C200_00FF) will broadcast.
[13] IGMP_En 0 RW Enable IGMPv4 Forwarding Table look-up process (IER0 ~ IER7 eight
IGMP entry locatio n)
1: IGMP Enable
0: Disable
[14]
IGMP_Mode
0
RW
If IGMP En=1 and IGMP_Mode=1, all IGMPv4 packets w i ll be forwarded to
CPU port.
If IGMP_En=1 and IGMP_Mode=0, all IGMPv4 packet will be copied to CP
[15]
QinQ_En
0
RW
Enable 802.1 QinQ (Double-Tagging) Function.
Please also conf igu re P0MCR/P1MCR/P2MCR [15] uplink_port if necessary
NOTE: Please make sure 1Q_En is set to 1 when QinQ_EN is enabled.
1: QinQ Enable
0: Disable
[16]
1X_En
0
RW
Enable 802.1X function. When enabled, all 802.1X c ontrol frame will be sent
to CPU port with Port_ID atta c hed after end of last payload. Each port’
s ON/
OFF is defined in the Per-P ort Setting: P0MCR/P 1MCR/P2MCR [11].
802.1X frame include MAC ID= 0x
0180c2000003 or Ethernet Packet Type=
0x888E frames.
1: 802.1X Enable
0: Disable
[17]
GMRP_En
0
RW
Enable GMRP control packet forwarding to CPU port if set to one.
Ethernet frames with DA MAC = 0x0180c2000020 are GMRP frames.
1: GMRP packet to CPU Enable
0: Disable
[18] GVRP_En 0 RW Enable GVRP control packet forwarding to CPU port if set to one.
Ethernet frames with DA MAC = 0x0180c2000021 are GVRP frames.
1: GVRP p a c ket to CPU Enable
0: Disable
[19]
GARP_En
0
RW
Enable GARP control packet forwarding to CPU port if set to one.
Ethernet frames with DA MAC = 0x0180c2000010 are GARP frames.
1: GARP packet to CPU Enable
0: Disable
[20] VLAN_En 0 RW E nable non-802.1Q Port base VLAN function. T otal 3 VLAN group will be
support. These Port-based VLAN groups are configured in PV CR
1: Port-Based VLAN Enable
0: Disable
[21]
1P_En
0
RW
Enable 802.1P prio rity frame function. When enabled, the priority field [2:0]
in Tag header can be re-mapping to internal 4 que ues. The M a pping table is
located in P0QMTR/P1QMTR/P2QMTR.
1: 802.1P priority enable
0: Disable
[22]
1Q_En
0
RW
Enable 802.1Q port-base VLAN function. There are 16 VLAN table en tries in
66
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
the VLA N f orw arding table. VLAN table entry is defined in VER0 ~ VER15.
VID can be configured between 1 and 4094.
Note: 1Q_EN and VLAN_En can’t enable at the same time!
1: 802.1Q Enable
0: Disable
[23]
1D_En
0
RW
Enable Spanning Tree (802.1D) function support.
The 802.1D per Port State is defined i n PVCR.
1: 802.1D Enable
0: Disable
[24] StO 0 RW Strict Ordering function Enable.
When set to one, all inco ming traffic to outp ut queue will base on following
Order: Q0-Q1-Q2-Q3-Q0-Q1-Q2-Q3… when the traffic is in congestion.
1: schedule T X packet with Strict ordering
0: Disable
[25]
Q0_Ig
0
RW
Ignore Q0 when conges tion dete ct.
If switch is congested, Q0 will be scheduled last.
1: I gnore queue 0 whenever there is a c ongestion
0: Disable
[31:26]
JamLimit
0x3F
RW
JAM Limit count. De fault val ue is 0x3F.
67
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
5.1.6 Layer 2 Learning/Aging/OneSA Control Register (LLCR)
Address 0x014
Bit
Name
Default
Value
R/W
Function
[2:0]
Reserved
111
RW
Reserved
[3]
Reserved
0
R
Reserved
[6:4]
Reserved
111
RW
Reserved
[7]
Reserved
0
R
Reserved
[10:8]
Reserved
111
RW
Reserved
[11]
Reserved
0
R
Reserved
[14:12] Learn_En 111 RW When Set to 0, per port SA MAC learning function will be disabled.
For example, if we like to achieve per port security function on port 1.
Setup
procedure is list below:
1. Disable Aging. (LGCR [5] Stop_learn)
2. Enabled port 1 learning enable bit. All the learned SA Mac address
will
store in the routing table if no ha shing
collision or hashing collision is less
than 2.
3. Disable po rt 1 learning function and enabled aging. The learned SA
Mac
address will not aging out.
.
Exclude port 1 from default flood ing register.
With the above procedure, per port security fun
ction can limit the MAC
address that can be only access from the specific port.
Learn_En[2:0] = {Port2,Port1,Port0}.
[15]
Reserved
0
R
Reserved
[24:16]
AgingTimer
0x1FF
RW
Programmable Aging timer for flushing routing table. Default value is 0x1FF.
[25]
Reserved
0
R
Reserved
[28:26] OneSARst 000 RW Res et One S A func t ion o f Port N. (N=0,1,2)
Set 1 to reset One SA function. When reset, Port N will clear previous
learning
SA MAC ad dress and r estart to learn a new SA MAC address.
OneSARst[2:0] = {Port2,Port1,Port0}.
[31:29]
OneSAEn
000
RW
Enable One SA function of Port N (N=0,1,2)
One SA function means Port N will only learn and forward the
first
successfully received packet’s SA MAC address.
The switch will continue
forwarding the following pa ckets but without learning the new SA.
If enable One SA function on port N, then the Lea rn_ E n b it sho ul d also
set 0
for port N.
OneSAEn[2:0] = {Port2,Port1,Port0}.
68
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
5.1.7 Layer 2 Routing Table Entry Read/Write Register (LRCR0 and LRCR1)
Address 0x018 (LRCR0)
Bit
Name
Default
Value
R/W
Function
[7:0]
MAC_address
[47:40]
0x00
RW
MAC address [47:40] Routing table MAC address entry
[15:8]
MAC_address
[39:32]
0x00
RW
MAC address [39:32]
[23:16]
MAC_address
[31:24]
0x00
RW
MAC address [31:24]
[31:24]
MAC_address
[23:16]
0x00
RW
MAC address [23:16]
Addre ss 0x01 C(LRCR1)
Bit
Name
Default
Value
R/W
Function
[7:0]
MAC_address
[15:8]
0x00
RW
MAC address [15:8]
[15:8]
MAC_address
[7:0]
0x00
RW
MAC address [7:0]
[17:16]
SrcPort
00
RW
Source port where this Mac Address is located.
00: Source Port 0
01: Source Port 1
10: Source Port 2
[18]
Filter_SA
0
RW
Filter_SA function.
Drop the receiving packet if the receiving packet’s SA MAC address match
with this MAC address and this bit is set to one.
[19]
Filter_DA
0
RW
Filter DA function.
Drop the recei ving packet if it’s DA MAC address match with the MAC
address and this bit is set to one.
[20]
Static
0
RW
Static bit.
1: Freeze the entry and ne ver agi ng out
0: Normal (Default)
[21] Flush_Done 0 R Routing tabl e flush done b it (read only)
If CPU set LRCR1 [29] to 1 (Flush_RT), then CPU will keep polling this bit to
confirm if the routing table completes flushing function.
1: Routing table flush done.
0: Routing table still flushing.
[23:22]
Search_Port
00
RW
Auto-search routing table source port entry
00: search port 0 entry
01: search port 1 entry
10: search port 2 enrty
11: not allo wed
[24]
RT_Valid
0
R
Entry is valid if set to one (read only)
1: valid entry
0: empty entry
[25]
RT_End
0
R
Used in Continuously search mode to designate the end of routing table is
reached. Read only.
[26]
RT_N
0
RW
Routing Ta ble Page (2–way 512 Routing Table entry)
0: page 0,
1: page 1
[27]
Conti_RD_RT
0
RW
Continue READ next valid entry inside routing table
[28]
By_Port
0
RW
Read routing table continuously.
Please configure Search_port first.
[29]
Flush_RT
0
RW
Clear all 1K routing table entries to 0 if this bit is set to o ne.
69
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
[30]
Read_RT
0
RW
Read Routing Table.
This bit needs to clear to 0 before the read start.
[31]
Write_RT
0
WC
Write entry into Routing Table. LRCR0 andLRCR1’s MAC address, SrcPort,
Static, Filter_DA, and Filter_SA inform ation
need to be ready before thi s bit
set.
5.1.8 802.1D and Port-based VLAN Configuration Register (PVCR)
Address 0x020
Bit
Name
Default
Value
R/W
Function
[1:0]
1Dport0St
00
RW
Port 0 1D Port State
“00” = blocking, disable
“01” = listening
“10” = learning
“11" = forwarding
LGCR [23] D1_En need to enable.
[3:2]
1Dport1St
00
RW
Port 1 1D Port State
“00” = blocking, disable
“01” = listening
“10” = learning
“11" = forwarding
LGCR [23] D1_En need to enable.
[5:4]
1Dport2St
00
RW
Port 2 1D Port State
“00” = blocking, disable
“01” = listening
“10” = learning
“11" = forwarding
LGCR [23] D1_En need to enable.
[7:6]
Reserved
00
R
Reserved
[10:8]
IngressFilter
000
RW
When enabled, Discard non-member VLAN packets for Tag-based VLAN
process.
For example:
if Port 1 receive a tag frame with VID=4 but the VLAN group
information doesn’t include Po rt 1 itself, then if this bit is set to one then
the
frame will be dropped.
LGCR[22] 1Q_En need to enable.
[15:11]
Reserved
0x00
R
Reserved
[18:16] VLANgrp0 000 RW Port 0 Port-Base VLAN configuration register is used to define non-
802.1Q
VLAN. Support total 3 Non-802.1Q VLAN.
LGCR [20] VLAN_En need to enable first.
[19]
Reserved
0
R
Reserved
[22:20] VLANgrp1 000 RW Port 1 Port-Base VLAN configuration register is used to define non-
802.1Q
VLAN. Support total 3 Non-802.1Q VLAN.
LGCR [20] VLAN_En need to enable first.
[23]
Reserved
0
R
Reserved
[26:24] VLANgrp2 000 RW Port 2 Port-Base VLAN configuration register is used to define non-
802.1Q
VLAN. Support total 3 Non-802.1Q VLAN.
LGCR [20] VLAN_En need to enable first.
[31:27]
Reserved
0x00
R
Reserved
70
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
5.1.9 Sniffer Function Configuration Register (SFCR0, SFCR1, SFCR2)
Sniffer Function C onfiguratio n regist er p rovides the following sniffer functions:
(1)SP_DP_sniffer
(2)DA_SA_sniffer
(3)VLAN_VID_sniffer
(4)P acket Type_sniffer
(1), (2), (3) and (4) conditions should be all match unless any o f these conditions ( 1 to 4) had default value zero.
5.1.9.1 Sniffer Function Configuration Register 0 (SFCR0)
Address 0x024
Bit Name
Default
Value R/W Function
[1:0]
SP_DP_sniffer
00
RW
00: None
01: Sniffer Source Port
10: Sniffer Destination P ort
11: Sniffer Source Port & Destination Port
[3:2]
DA_SA_sniffer
00
RW
00: None
01: SA Match
10: DA Match
11: SA & DA Match
[4] VLAN_VID_sniff
er 0 RW 0: None
1: VID Match
When enabled, u s e SFCR1 SnifferVID to sniffer packets.
[5]
Reserved
0
RW
[6]
Packet_ype_sniffe
r
0
RW
0: None
1: Packet Type Match
When enabled, Use L2_Type or IPv4_Type or IPv6_Type [7:0] or IP_Port with
SFCR2 to sniffer Packet.
[14:7]
IP_Port_sniffer
0x00
RW
0x00: None
0x01: IP_V4 TCP Source Port Match
0x02: IP_V4 TCP Destination Port Match
0x03: IP_V4 TCP Destination P ort Match & Source Port Match
0x04: IP_V4 UDP Source Port Mat ch
0x08: IP_V4 UDP Destination Po rt Match
0x0C: IP_V4 UDP Destination Port Match & Sour ce Po rt Match
0x10: IP_V6 TCP Source Port Match
0x20: IP_V6 TCP Destination Port Match
0x30: IP_V6 TCP Destination P ort Match & Source Port Match
0x40: IP_V6 UDP Source Port Mat ch
0x80: IP_V6 UDP Destination Port Match
0xC0: IP_V6 UDP Destination Port Match & Sour ce Po rt Match
Note: Write Port number i n SFCR2
[15] SnifferEn 0 RW Enabl e sniffer function
When t he incoming packet matches sniffer conditio n, that packet will be
duplicated to sniffer port.
Snifferi ng condition can be b ased on the follo wing rule:
1. Source Po rt or Destination P ort
2. DA o r SA
3. VID
4. Ethernet Packet Type
5. IPv4 Source Port/De stinatio n Port
6. IPv6 Source Port/Destination Por t
[17:16] SnifferPort 00 RW The assigned sniffer port. All packets that m atch the Sniffer rule
will duplicate
to this sniffer port.
[20:18] SniffSrcPort 000 RW Sniffer Source Port.
Sniffer Packet that received by Port N. (N=0,1,2) The user can select all 3
ports at the same time . For example, Select Port 0, 1 as Sniffer Source Port,
71
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
then
set register value to 01 1. All the packets receive from port 0 and por t 1 will
duplicate to the a ssigned sniffer port.
[23:21] SniffDstPort 000 RW Sniffer Destination Port. Sniffer Packet that transmit to Port N . (N=0,1 , 2).
The user can select up to 3 ports at the sam e time. For
exam ple, Select Port 0,1
as Sniffer Destination Port, Set re gister value to 011. And all the packets
transmit to port 0 and port1 will duplicate to the assigned sniffer port.
[31:24]
L2_Type
0x00
RW
Sniffer Layer 2 Ethernet Packet Type:
Type_L2 [0]: ARP (0x0806),
Type_L2 [1]: RARP (0x8035)
Type_L2 [2]: MPLS Packet (0x8847 unicast or 0x8848 multicast)
Type_L2 [3]: 802.1X (0x888E)
Type_L2 [4]: IPX/SNAP (0x8137)
Type_L2 [5] : N e t Bios (0x8040)
Type_L2 [6]: B ased o n USTR User-Defined packet type
(Default: PPPOE Discovery 0x8863)
Type_L2 [7]: PPPOE Session (0x8864)
5.1.9.2 Sniffer Function Configuration Register 1 (SFCR1)
Address 0x028
Bit Name
Default
Value
R/W
Function
[7:0] IPv4_Type 0x00 RW IPv4 Pr otocol Filter
Type_IPV4 [0]: IP Packet (Type_L2=0x0800
and not incl ude Type_IPV4 [ 1]
~ Type_IPV4 [7])
Type_IPV4 [1]: TCP (Protocol=6)
Type_IPV4 [2]: UDP (Protocol=17)
Type_IPV4 [3]: OSPF (Protocol=89)
Type_IPV4 [4]: RSVP (Protocol=46)
Type_IPV4 [5]: Based on USTR User-Defined IPv4 packet type
(Default: L2TP Protocol=115)
Type_IPV4 [6]: ICMP (Protocol=1)
Type_IPV4 [7]: IGMP (Protocol=2)
[14:8]
IPv6_Type
0x00
RW
IPv6 Next Header Filter
Type_I PV6 [0]: IP Packet (Type_L2= 0x86DD
and not include Type_IPV6
[1] ~ Type_IPV6 [6])
Type_IPV6 [1]: TCP (Protocol=6)
Type_IPV6 [2]: UDP (Protocol=17)
Type_IPV6 [3]: OSPF (Protocol=89)
Type_IPV6 [4]: RSVP (Protocol=46)
Type_IPV6 [5]: Based on USTR User-Defined IPv6 packet type
(Default: L2TP Protocol=115)
Type_IPV6 [6]: ICMP (Protocol=1)
[15]
Reserved
0
R
Reserved
[27:16]
SnifferVID
0x000
RW
Sniffer VLAN ID (VID range from 0 to 4095)
[31:28]
Reserved
0000
R
Reserved
72
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
5.1.9.3 Sniffer Function Configuration Register 2 (SFCR2)
Address 0x02C
Bit
Name
Default
Value
R/W
Function
[15:0]
Src_Port
0x0000
RW
Valid when SFCR0
IP_Port
is selected. Source Port number on
Layer 3 protocol (IPv4 TCP/UDP or IPv6 TCP/UDP) matches this Src_Port
value.
For example, when IP_Port == 0x01, and Sniffer condition is “IPv4 TCP
Source Port Match “. When Source Port number from the i ncoming TCP
Packet matches with this Src_Port value, t hen this p a c ket will be duplicate d
and forward to the assigne d Sniffer Po rt.
[31:16]
Dst_Port
0x0000
RW
Valid when SFCR0
IP_Port
is selected Destination P ort number on Layer 3
protocol (IPv4 TCP/UDP or IPv6 TCP/UDP) matches this Dst_Port value
For example, when IP_Port == 0x02, and Sniffer condition is “IPv4 TCP
Destination Port Matc h “. When Dest ination Port of incoming TCP Packet
matches with this Dst_Port value, then this packet will be duplicated and
forward to the assigned Sniffer Port.
5.1.10 QoS Priority Mapping Table Register (QPTR)
Address 0x030
Bit
Name
Default
Value
R/W
Function
[1:0]
TOS0
00
RW
TO S Mapping Table.This table covert IPv4 QoS (Type of Service [7:5] or
[4:2] depend on LGCR [0] QoSSel) 3 bit value to any one of the 4 queue s
within buffer mana gement unit within the s witch engine.
If TOS [2:0]==0 then priority value map to ToS0 [1:0]
[3:2]
TOS1
00
RW
If TOS [2:0]==1 then pr iority value map to ToS1 [1:0]
[5:4]
TOS2
01
RW
If TOS [2:0]==2 then pr iority value map to ToS2 [1:0]
[7:6]
TOS3
01
RW
If TOS [2:0]==3 then pr iority value map to ToS3 [1:0]
[9:8]
TOS4
10
RW
If TOS [2:0]==4 then pr iority value map to ToS4 [1:0]
[11:10]
TOS5
10
RW
If TOS [2:0]==5 then pr iority value map to ToS5 [1:0]
[13:12]
TOS6
11
RW
If TOS [2:0]==6 then pr iority value map to ToS6 [1:0]
[15:14]
TOS7
11
RW
If TOS [2:0]==7 then prio rity value map to T oS7 [1:0]
[17:16]
COS0
00
RW
COS Mapping Table.This table convert IPv6 QoS (Traffic Class [7:5] or [4:2]
depend on LGCR [0] QoSSel) 3 bit value to any one of the 4 queues within
buffer mana gement unit within the s witch engine.
If COS [2:0]= = 0 then priority value map to CoS0 [1:0]
[19:18]
COS1
00
RW
If COS [2:0]= = 1 then priority value map to CoS1 [1:0]
[21:20]
COS2
01
RW
If COS [2:0]= = 2 then priority value map to CoS2 [1:0]
[23:22]
COS3
01
RW
If COS [2:0]= = 3 then priority value map to CoS3 [1:0]
[25:24]
COS4
10
RW
If COS [2:0]= = 4 then priority value map to CoS4 [1:0]
[27:26]
COS5
10
RW
If COS [2:0]= = 5 then priority value map to CoS5 [1:0]
[29:28]
COS6
11
RW
If COS [2:0]= = 6 then priority value map to CoS6 [1:0]
[31:30]
COS7
11
RW
If COS [2:0]= = 7 then priority value map to CoS7 [1:0]
73
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
5.1.11 802.1Q-in-1Q (Double-Tagging) Setup Register (QSR)
Address 0x034
Bit
Name
Default
Value
R/W
Function
[15:0]
Rgi_sptag
0x0000
RW
Service Provider Tag Register.
When P VCR [15] QinQ i s set to one, T he Service Pro vide r TAG will be
inserted into the frame if
1. Receive Port is Access Por t (P0MCR/P 1MCR/P2MCR [15]=0)
or
2. Receive Port is Uplink Port (P0MCR/P1MCR/P2MCR [15]=1) and
rgi_tpid is not matched with VLAN Ta g
When Egress port is Access Port then the Service Provider TAG will be
removed.
[31:16]
Rgi_tpid
0x8100
RW
VLAN Tag Register.(Default ox8100)
When 1Q-in-1Q is turned ON (PVCR [15]=1) , rgi_tpid (type ID) will be
compared against all the incomin g packet s’ V L A N Tag field if receive port
is
an Uplink_Port ( P0MCR/P1MCR/P2MCR [15]=1).
5.1.12 Port Pair and MDC Control Register (PPMR)
Address 0x038
Bit
Name
Default
Value
R/W
Function
[3:0]
PortPairP0
0000
RW
Define port pair 0 on PortPairP0 [3:2] and PortPairP0 [1:0]
[7:4]
PortPairP1
0000
RW
Define port pair 1 on PortPairP1 [7:6] and PortPairP1 [5:4]
[9:8] AllBit 00 RW [8]: If set to o ne then Port Pair0 will pass all packets based o n PortP a irPri
[11:10] queue setting
[9]: if set to 1 then Port Pair 1 will pass all packets based on PortPairPri
[11:10] queue setting
Note: [3:0] and [7:4 ] should set to the same port!!
[11:10]
PortPairPri
00
RW
Pre-defined Port Pair prior ity queue number.
Assign port pair traffic on dedicate queue.
[14:12]
Reserved
000
R
Reserved
[15]
PortpairEn
0
RW
Enable Port Pair function
[23:16]
MDC_cyc
0x31
RW
This register is used to set MDC frequency, defau lt value is 0x31, mean s MDC
frequency is 1MHz. Minimum value = 0x4 , Maximum value=0xFF
The lower the value, the higher the frequency.
[24]
Reserved
0
RW
Reserved. Always set 0 when wr ite PPMR r e gister.
[31:25]
Reserved
0x00
R
Reserved
74
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
5.1.13 MDIO Read/Write Control Register (MRCR)
Address 0x03C
Bit
Name
Default
Value
R/W
Function
[15:0]
Data
0x0000
RW
MDIO data [15:0]
When CPU set MDIO read command register to 1, The MDC/M
DIO
controller will show the read data from PHY register here.
When CPU set MDIO write command register to 1, The
MDC/MDIO
controller will write this register data to the PHY r e gister.
[20:16]
Reg_addr
00000
RW
PHY Register address. CPU should set this register to let the MDC/MDIO
controller knows which PHY register to be accessed.
Please reference 5.2
PHY register address offset.
[23:21]
Reserved
000
R
Reserved
[28:24]
Phy_addr
00000
RW
PHY Physical ID. CPU should set this register to let the MDC/MDIO
contr olle r know what PHY ID to be accessed.
[29]
MDIORD_ok
0
R
MDIO data valid
After CPU set the MDIO read comm and regis ter to one, CPU
should continue
polling this bit to confirm that the
MII management interface read cycle is
done and Data [15:0] is also valid.
After CPU set the
MDIO write command register to one, CPU should continue
polling this bit to confirm that the
MII management interface write cycle is
done.
1: MII management interface read/write cycle is done.
0: MII management interface read/write cycle is not done.
[30] MDIORead 0 WC MDIO Read command to PHY
1: Read command
0: Idle
CPU should set this bit to one to let the MDC/MDI O contro ller p erform MI I
management interface read cycle. CPU also needs to program
the reg_addr
and phy_addr value in MRCR first.
[31] MDIOWrite 0 WC MDIO Write command to PHY
1: Write c ommand
0: Idle
CPU should set this bit to one to let the MDC/MDI O contro ller p erform MI I
management interface write cycle. CPU also needs
to set the reg_addr ,
phy_addr and Data register in MRCR first.
75
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
5.1.14 Security Mac Control Register
There are eight extra security MAC addresses in the AX88613.Each Security MAC register can be set for the
following purpose:
1. As a supplement to the limit of 2-w ay hashing routing table. When hashing collision happens, these security
MAC registers can be set by CPU to avoid flooding.
2. Sniffer function: Duplicate packets to the assigned Sniffer Port when DA or SA or DA & SA m atch. Snif fer
Pair b it (SnifferPair) must be enabled in pair.
For Example, assume Security MAC0 and MAC1 are paired.
i. Set SM0CR1 and SM1CR1 both SnifferPair[20] bits to one
ii. Set SM0CR1 Sniffer_SA and SM1CR1 Sniffer_DA to one
iii. Set SFCR0 DA_SA_sniffer=2’b11
iv. Chose Sniffer port in SFCR0’s SnifferPort.
Then any packets w ith a SA MAC address m atch ed w ith the secu rity Mac0 and DA MA C address m atch ed
with security MAC1 will forward to the assigned sniffer port..
3. Security fu nction: Filtering packets w hen DA or SA or DA & SA m atch. Drop Pair bit (Filter_Pair) must be
enabled in pair also.
Note1: Security MAC 0 and Security MAC 1 can be paired if SnifferPair or Filter_Pair bit is set to one.
Security MAC 2 and Secu rity MAC 3, Security MA C 4 and Secu rit y MAC 5, Secu rity MAC 6 and
Security MAC 7, can all be paired together.
Note2: En_RT and Filter_DA/SA and DA_SA_sniffer (SnifferEn=1) can’t enable at the same time!
Note3: MAC address and source port information need to be matched!
4. Support 802.1X security function: The global 802.1X enable b it in LGCR 1X _En a nd Per port 802.1X
enable bits in PMCR0/PMCR1/PMCR2 1XsecurityON need to enable first before turn on the X1SA_match
security function within these security MAC registers.
76
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
5.1.14.1 Security Mac 0 Control Register (SM0CR0, SM0CMR1)
Address 0x050 (SM0CR0)
Bit
Name
Default
Value
R/W
Function
[7:0]
MAC_address 0
[47:40]
0x00
RW
Security MAC address 0 [47:40]
[15:8]
MAC_address 0
[39:32]
0x00
RW
Security MAC address 0 [39:32]
[23:16]
MAC_address 0
[31:24]
0x00
RW
Security MAC address 0 [31:24]
[31:24]
MAC_address 0
[23:16]
0x00
RW
Security MAC address 0 [23:16]
Address 0x054 (SM0CR1)
Bit
Name
Default
Value
R/W
Function
[7:0]
MAC_address 0
[15:8]
0x00
RW
Security MAC address 0 [15:8]
[15:8]
MAC_address 0
[7:0]
0x00
RW
Security MAC address 0 [7:0]
[17:16]
Src_Port
00
RW
Source Port ID.
[18]
Sniffer_SA
0
RW
Copy the packet to the Sniffe r P ort if SA MAC matches with the security
MAC add ress 0.
1: Enable Sniffer SA
0: Disable
[19] Sniffer_DA 0 RW Copy the packet to the Sniffer Port if DA MAC matches with the security
MAC add ress 0.
1: Enable Sniffer DA
0: Disable
[20]
SnifferPair
0
RW
Copy the packet to the Sniffer Port if DA MAC or SA MAC matches w ith the
security MAC address 0 and DA MAC or SA MAC matches the security
MAC add ress 1.
1: Enable Sniffer Pair
0: DIsable
[26:21]
Reserved
0x00
R
Reserved
[27] X1_SAMatch 0 RW Forward the packet if SA MAC m at ches w ith th e
security MAC Address 0 if
the 802.1X is enabled, else drop the packet.
1: Enable 802.1X SA Match
0: Disable
[28]
Filter_Pair
0
RW
Drop the packet if DA MAC or SA MAC matches with the security MAC
Addres s 0 & DA MAC or SA MAC match es w ith the
security MAC Address
1.
1: Enable Filter Pair
0: Disable
[29] Filter_SA 0 RW Drop the packet if SA MAC matches with the security MAC address 0.
1: Enable Filter SA
0: Disable
[30]
Filter_DA
0
RW
Drop the packet if DA MAC matches with the security MAC address 0.
1: Enable Filter DA
0: Disable
[31]
En_RT
0
RW
Enable r outing function if DA matches with the security MAC address 0.
1: E nable routing function
0: Disable
77
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
5.1.14.2 Security Mac 1 Control Register (SM1CR0, SM1CR1)
Address 0x058 (SM1CR0)
Bit
Name
Default
Value
R/W
Function
[7:0]
MAC_address 1
[47:40]
0x00
RW
Security MAC address 1 [47:40]
[15:8]
MAC_address 1
[39:32]
0x00
RW
Security MAC address 1 [39:32]
[23:16]
MAC_address 1
[31:24]
0x00
RW
Security MAC address 1 [31:24]
[31:24]
MAC_address 1
[23:16]
0x00
RW
Security MAC address 1 [23:16]
Address 0x05C (SM1CR1)
Bit
Name
Default
Value
R/W
Function
[7:0]
MAC_address 1
[15:8]
0x00
RW
Security MAC address 1 [15:8]
[15:8]
MAC_address 1
[7:0]
0x00
RW
Security MAC address 1 [7:0]
[17:16]
Src_Port
00
RW
Source Port ID.
[18]
Sniffer_SA
0
RW
Copy the packet to the Sniffe r P ort if S A MAC matches with the security
MAC add ress 1.
1: Enable Sniffer SA
0: Disable
[19]
Sniffer_DA
0 RW Copy the packet to the Sniffer Port if DA MAC matches with the security
MAC add ress 1.
1: Enable Sniffer DA
0: Disable
[20]
SnifferPair
0
RW
Copy the packet to the Sniffer Port if DA MAC or SA MAC matches w ith the
security MAC address 0 and DA MAC or SA MAC matches the security
MAC add ress 1.
1: Enable Sniffer Pair
0: DIsable
[26:21]
Reserved
0x00
R
Reserved
[27] X1_SAMatch 0 RW Forward the packet if SA MAC m atches w ith the
security MAC Address 1 if
the 802.1X is enabled, else drop the packet.
1: Enable 802.1X SA Match
0: Disable
[28]
Filter_Pair
0
RW
Drop the packet if DA MAC or SA MAC matches with the security MAC
Addres s 0 & DA MAC or SA MAC match es with th e
security MAC Address
1.
1: Enable Filter Pair
0: Disable
[29] Filter_SA 0 RW Drop the p acket if SA MAC matches with the security MAC address 1.
1: Enable Filter SA
0: Disable
[30]
Filter_DA
0
RW
Drop the packet if DA MAC matches with the security MAC add ress 1.
1: Enable Filter DA
0: Disable
[31]
En_RT
0
RW
Enable r outing function if DA matches with the security MAC address 1.
1: E nable routing function
0: Disable
78
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
5.1.14.3 Security Mac 2 Control Register (SM2CR0, SM2CR1)
Address 0x060 (SM2CR0)
Bit Name
Default
Value R/W
Function
[7:0]
MAC_address 2
[47:40]
0x00
RW
Security MAC address 2 [47:40]
[15:8]
MAC_address 2
[39:32]
0x00
RW
Security MAC address 2 [39:32]
[23:16]
MAC_address 2
[31:24]
0x00
RW
Security MAC address 2 [31:24]
[31:24]
MAC_address 2
[23:16]
0x00
RW
Security MAC address 2 [23:16]
Address 0x064 (SM2CR1)
Bit
Name
Default
Value
R/W
Function
[7:0]
MAC_address 2
[15:8]
0x00
RW
Security MAC address 2 [15:8]
[15:8]
MAC_address 2
[7:0]
0x00
RW
Security MAC address 2 [7:0]
[17:16]
Src_Port
00
RW
Source Port ID.
[18]
Sniffer_SA
0
RW
Copy the packet to the Sniffe r P ort if SA MAC matches with the security
MAC add ress 2.
1: Enable Sniffer SA
0: Disable
[19]
Sniffer_DA
0
RW
Copy the packet to the Sniffer Port if D A MAC matches with the security
MAC add ress 2.
1: Enable Sniffer DA
0: Disable
[20]
SnifferPair
0
RW
Copy the packet to the Sniffer Port if DA MAC or SA MAC matches w ith the
security MAC address 2 and DA MAC or SA MAC matches the security
MAC add ress 3.
1: Enable Sniffer Pair
0: Disable
[26:21]
Reserved
0x00
R
Reserved
[27]
X1_SAMatch
0
RW
Forward the pack et if S A MA C m atch es w ith the security MAC Address 2 if
the 802.1X is enabled, else drop the packet.
1: Enable 802.1X SA Match
0: Disable
[28]
Filter_Pair
0
RW
Drop the packet if DA MAC or SA MAC matches with the security MAC
Addres s 2 & DA MAC or SA MAC match es w ith the
security MAC Address
3.
1: Enable Filter Pair
0: Disable
[29] Filter_SA 0 RW Drop the packet if SA MAC matches with the security MAC address 2.
1: Enable Filter SA
0: Disable
[30] Filter_DA 0 RW Drop the packet if DA MAC matches with the security MAC address 2.
1: Enable Filter DA
0: Disable
[31]
En_RT
0
RW
Enable r outing function if DA matches with the security MAC address 2.
1: E nable routing function
0: Disable
79
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
5.1.14.4 Security Mac 3 Control Register (SM3CR0, SM3CR1)
Address 0x068 (SM3CR0)
Bit
Name
Default
Value
R/W
Function
[7:0]
MAC_address 3
[47:40]
0x00
RW
Security MAC address 3 [47:40]
[15:8]
MAC_address 3
[39:32]
0x00
RW
Security MAC address 3 [39:32]
[23:16]
MAC_address 3
[31:24]
0x00
RW
Security MAC address 3 [31:24]
[31:24]
MAC_address 3
[23:16]
0x00
RW
Security MAC address 3 [23:16]
Address 0x06C (SM3CR1)
Bit
Name
Default
Value
R/W
Function
[7:0]
MAC_address 3
[15:8]
0x00
RW
Security MAC address 3 [15:8]
[15:8]
MAC_address 3
[7:0]
0x00
RW
Security MAC address 3 [7:0]
[17:16]
Src_Port
00
RW
Source Port ID.
[18]
Sniffer_SA
0
RW
Copy the packet to the Sniffe r P ort if SA MAC matches with the security
MAC add ress 3.
1: E nabl e Sniffer SA
0: Disable
[19] Sniffer_DA 0 RW Copy the packet to the Sniffer Port if DA MAC matches with the security
MAC add ress 3.
1: Enable Sniffer DA
0: Disable
[20]
SnifferPair
0
RW
Copy the packet to the Sniffer Port if DA MAC or SA MAC m atches w ith the
security MAC address 2 and DA MAC or SA MAC matches the security
MAC add ress 3.
1: Enable Sniffer Pair
0: Disable
[26:21]
Reserved
0x00
R
Reserved
[27] X1_SAMatch 0 RW Forward the packet if SA MAC m atches w ith th e
security MAC Address 3 if
the 802.1X is enabled, else drop the packet.
1: Enable 802.1X SA Match
0: Disable
[28]
Filter_Pair
0
RW
Drop the packet if DA MAC or SA MAC matches with the security MAC
Addres s 2 & DA MAC or SA MAC match es w ith the
security MAC Address
3.
1: Enable Filter Pair
0: Disable
[29] Filter_SA 0 RW Drop the packet if SA MAC matches with the security MAC address 3.
1: Enable Filter SA
0: Disable
[30]
Filter_DA
0
RW
Drop the packet if DA MAC matches with the security MAC address 3.
1: Enable Filter DA
0: Disable
[31]
En_RT
0
RW
Enable r outing function if DA matches with the security MAC address 3.
1: E nable routing function
0: Disable
80
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
5.1.14.5 Security Mac 4 Control Register (SM4CR0, SM4CR1)
Address 0x070 (SM4CR0)
Bit Name
Default
Value R/W
Function
[7:0]
MAC_address 4
[47:40]
0x00
RW
Security MAC address 4 [47:40]
[15:8]
MAC_address 4
[39:32]
0x00
RW
Security MAC address 4 [39:32]
[23:16]
MAC_address 4
[31:24]
0x00
RW
Security MAC address 4 [31:24]
[31:24]
MAC_address 4
[23:16]
0x00
RW
Security MAC address 4 [23:16]
Address 0x074 (SM4CR1)
Bit
Name
Default
Value
R/W
Function
[7:0]
MAC_address 4
[15:8]
0x00
RW
Security MAC address 4 [15:8]
[15:8]
MAC_address 4
[7:0]
0x00
RW
Security MAC address 4 [7:0]
[17:16]
Src_Port
00
RW
Source Port ID.
[18]
Sniffer_SA
0
RW
Copy the packet to the Sniffe r P ort if SA MAC matches with the security
MAC add ress 4.
1: Enable Sniffer SA
0: Disable
[19]
Sniffer_DA
0
RW
Copy the packet to the Sniffer Port if D A MAC matches with the security
MAC add ress 4.
1: Enable Sniffer DA
0: Disable
[20]
SnifferPair
0
RW
Copy the packet t o the Sniffer Port if DA MAC or SA MAC m atches with the
security MAC address 4 and DA MAC or SA MAC matches the security
MAC add ress 5.
1: Enable Sniffer Pair
0: Disable
[26:21]
Reserved
0x00
R
Reserved
[27]
X1_SAMatch
0
RW
Forward the packet if SA MAC matches with the security MAC Addre ss 4 if
the 802.1X is enabled, else drop the packet.
1: Enable 802.1X SA Match
0: Disable
[28]
Filter_Pair
0
RW
Drop the packet if DA MAC or SA MAC matches with the security MAC
Addres s 4 & DA MAC or SA MA C matches with the
security MAC Address
5.
1: Enable Filter Pair
0: Disable
[29] Filter_SA 0 RW Drop the packet if SA MAC matches with the security MAC address 4.
1: Enable Filter SA
0: Disable
[30] Filter_DA 0 RW Drop the packet if DA MAC matches with the security MAC address 4.
1: Enable Filter DA
0: Disable
[31]
En_RT
0
RW
Enable r outing function if DA matches with the security MAC address 4.
1: E nable routing function
0: Disable
81
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
5.1.14.6 Security Mac 5 Control Register (SM5CR0, SM5CR1)
Address 0x078 (SM5CR0)
Bit
Name
Default
Value
R/W
Function
[7:0]
MAC_address 5
[47:40]
0x00
RW
Security MAC address 5 [47:40]
[15:8]
MAC_address 5
[39:32]
0x00
RW
Security MAC address 5 [39:32]
[23:16]
MAC_address 5
[31:24]
0x00
RW
Security MAC address 5 [31:24]
[31:24]
MAC_address 5
[23:16]
0x00
RW
Security MAC address 5 [23:16]
Address 0x07C (SM5CR1)
Bit
Name
Default
Value
R/W
Function
[7:0]
MAC_address 5
[15:8]
0x00
RW
Security MAC address 5 [15:8]
[15:8]
MAC_address 5
[7:0]
0x00
RW
Security MAC address 5 [7:0]
[17:16]
Src_Port
00
RW
Source Port ID.
[18]
Sniffer_SA
0
RW
Copy the packet to the Sniffe r P ort if SA MAC matches with the security
MAC add ress 5.
1: Enable Sniffer SA
0: Disable
[19] Sniffer_DA 0 RW Copy the packet to the Sni ffer Po rt if DA MAC matches with the security
MAC add ress 5.
1: Enable Sniffer DA
0: Disable
[20]
SnifferPair
0
RW
Copy the packet t o the Sniffer Port if DA MAC or SA MAC m atches with the
security MAC address 4 and DA MAC or SA MAC matches the security
MAC add ress 5.
1: Enable Sniffer Pair
0: Disable
[26:21]
Reserved
0x00
R
Reserved
[27] X1_SAMatch 0 RW Forward the packet if S A MA C matches with the
security MAC Address 5 if
the 802.1X is enabled, else drop the packet.
1: Enable 802.1X SA Match
0: Disable
[28]
Filter_Pair
0
RW
Drop the packet if DA MAC or SA MAC matches with the security MAC
Addres s 4 & DA MAC or SA MA C matches with the
security MAC Address
5.
1: Enable Filter Pair
0: Disable
[29] Filter_SA 0 RW Drop the packet if SA MAC matches with the security MAC address 5.
1: Enable Filter SA
0: Disable
[30]
Filter_DA
0
RW
Drop the packet if DA MAC matches with the security MAC address 5.
1: Enable Filter DA
0: Disable
[31]
En_RT
0
RW
Enable r outing function if DA matches with the security MAC address 5.
1: E nable routing function
0: Disable
82
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
5.1.14.7 Security Mac 6 Control Register (SM6CR0, SM6CR1)
Address 0x080(SM6CR0)
Bit Name
Default
Value R/W
Function
[7:0]
MAC_address
6 [47:40]
0x00
RW
Security MAC address 6 [47:40]
[15:8]
MAC_address
6
[39:32]
0x00
RW
Security MAC address 6 [39:32]
[23:16]
MAC_address
6 [31:24]
0x00
RW
Security MAC address 6 [31:24]
[31:24]
MAC_address
6 [23:16]
0x00
RW
Security MAC address 6 [23:16]
Address 0x084 (SM6CR1)
Bit
Name
Default
Value
R/W
Function
[7:0]
MAC_address
6 [15:8]
0x00
RW
Security MAC address 6 [15:8]
[15:8]
MAC_address
6
[7:0]
0x00
RW
Security MAC address 6 [7:0]
[17:16]
Src_Port
00
RW
Source Port ID.
[18]
Sniffer_SA
0
RW
Copy the packet to the Sniffe r P ort if SA MAC matches with the security
MAC add ress 6.
1: Enable Sniffer SA
0: Disable
[19]
Sniffer_DA
0
RW
Copy the packet to the Sniffer Port if D A MAC matches with the security
MAC add ress 6.
1: Enable Sniffer DA
0: Disable
[20]
SnifferPair
0
RW
Copy the packet t o the Sniffer Port if DA MAC or SA MAC matches w ith the
security MAC address 6 and DA MAC or SA MAC matches the security
MAC add ress 7.
1: Enable Sniffer Pair
0: Disable
[26:21]
Reserved
0x00
R
Reserved
[27]
X1_SAMatch
0
RW
Forward the packet if SA MAC matches with the security MAC Address 6 if
the 802.1X is enabled, else drop the packet.
1: Enable 802.1X SA Match
0: Disable
[28]
Filter_Pair
0
RW
Drop the packet if DA MAC or SA MAC matches with the security MAC
Addres s 6 & DA MAC or SA MA C matches with the secur
ity MAC Address
7.
1: Enable Filter Pair
0: Disable
[29]
Filter_SA
0
RW
Drop the packet if SA MAC matches with the security MAC address 6.
1: Enable Filter SA
0: Disable
[30]
Filter_DA
0
RW
Drop the packet if DA MAC matches with the security MAC address 6.
1: Enable Filter DA
0: Disable
[31] En_RT 0 RW Enable r outing func tion if DA matches with the security MAC address 6.
1: E nable routing function
0: Disable
83
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
5.1.14.8 Security Mac 7 Control Register (SM7CR0, SM7CR1)
Address 0x088 (SM7CR0)
Bit
Name
Default
Value
R/W
Function
[7:0]
MAC_address
7 [47:40]
0x00
RW
Security MAC address 7 [47:40]
[15:8]
MAC_address
7
[39:32]
0x00
RW
Security MAC address 7 [39:32]
[23:16]
MAC_address
7 [31:24]
0x00
RW
Security MAC address 7 [31:24]
[31:24]
MAC_address
7 [23:16]
0x00
RW
Security MAC address 7 [23:16]
Address 0x08C (SM7CR1)
Bit
Name
Default
Value
R/W
Function
[7:0] MAC_addr
ess 7
[15:8]
0x00 RW Security MAC address 7 [15:8]
[15:8] MAC_addr
ess 7
[7:0]
0x00 RW Security MAC address 7 [7:0]
[17:16]
Src_Port
00
RW
Source Port ID.
[18]
Sniffer_SA
0
RW
Copy the packet to the Sniffe r P ort if SA MAC matches with the security
MAC add ress 7.
1: Enable Sniffer SA
0: Disable
[19]
Sniffer_DA
0
RW
Copy the packet to the Sniffer Port if D A MAC matches with the security
MAC add ress 7.
1: Enable Sniffer DA
0: Disable
[20]
SnifferPair
0
RW
Copy the packet t o the Sniffer Port if DA MAC or SA MAC m atches with the
security MAC address 6 and DA MAC or SA MAC matches the security
MAC add ress 7.
1: Enable Sniffer Pair
0: Disable
[26:21]
Reserved
0x00
R
Reserved
[27]
X1_SAMatch
0
RW
Forward the packet if SA MAC matches with the security MAC Addre ss 7 if
the 802.1X is enabled, else drop the packet.
1: Enable 802.1X SA Match
0: Disable
[28]
Filter_Pair
0
RW
Drop the packet if DA MAC or SA MAC matches with the security MAC
Addres s 6 & DA MAC or SA MA C matches with the
security MAC Address
7.
1: Enable Filter Pair
0: Disable
[29]
Filter_SA
0
RW
Drop the packet if SA MAC matches with the security MAC address 7.
1: Enable Filter SA
0: Disable
[30]
Filter_DA
0
RW
Drop the packet if DA MAC matches with the security MAC address 7.
1: Enable Filter DA
0: Disable
[31] En_RT 0 RW Ena ble routing function if DA matches with the security MAC address 7.
1: E nable routing function
0: Disable
84
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
5.1.15 VLAN Entry Registers
5.1.15.1 VLAN Entry 0 Register (VER0)
Address 0x090
Bit
Name
Default
Value
R/W
Function
[2:0]
Forward
000
RW
VLAN group forwarding information {Port2, Port1, Port0}
1: Same VLAN group port
0: Not Same VLAN group
[5:3] Tag 000 RW Define output packet with Tag or without Tag control
{Port2, Port1, Port0}
1: Tag frame
0: Un-Tag frame
[17:6]
VID
0x000
RW
Full range VID (1 ~ 4095)
[18] Valid 0 RW VLAN Entry 0 Valid bit
1: Valid
0: Not valid
[31:19]
Reserved
0x0000
R
Reserved
5.1.15.2 VLAN Entry 1 Register (VER1)
Address 0x094
Bit
Name
Default
Value
R/W
Function
[2:0] Forward 000 RW VLAN group forwarding information {Port2, Port1, Port0}
1: Same VLAN group port
0: Not Same VLAN group
[5:3]
Tag
000
RW
Define output packet with Tag o r without Tag control
{Port2, Port1, Port0}
1: Tag frame
0: Un-Tag frame
[17:6]
VID
0x000
RW
Full range VID (1 ~ 4095)
[18]
Valid
0
RW
VLAN Entry 0 Valid bit
1: Valid
0: Not valid
[31:19]
Reserved
0x0000
R
Reserved
5.1.15.3 VLAN Entry 2 Register (VER2)
Address 0x098
Bit Name
Default
Value R/W
Function
[2:0]
Forward
000
RW
VLAN group forwarding information {Port2, Port1, Port0}
1: Same VLAN group port
0: Not Same VLAN group
[5:3]
Tag
000
RW
Define output packet with Tag or without Tag control
{Port2, Port1, Port0}
1: Tag frame
0: Un-Tag frame
[17:6]
VID
0x000
RW
Full range VID (1 ~ 4095)
[18]
Valid
0
RW
VLAN Entry 0 Valid bit
1: Valid
0: Not valid
[31:19]
Reserved
0x0000
R
Reserved
85
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
5.1.15.4 VLAN Entry 3 Register (VER3)
Address 0x09C
Bit
Name
Default
Value
R/W
Function
[2:0] Forward 000 RW VLAN group forwarding information {Port2, Port1, Port0}
1: Same VLAN group port
0: Not Same VLAN group
[5:3]
Tag
000
RW
Define output packet with Tag or without Tag control
{Port2, Port1, Port0}
1: Tag frame
0: Un-Tag frame
[17:6]
VID
0x000
RW
Full range VID (1 ~ 4095)
[18]
Valid
0
RW
VLAN Entry 0 Valid bit
1: Valid
0: Not valid
[31:19]
Reserved
0x0000
R
Reserved
5.1.15.5 VLAN Entry 4 Register (VER4)
Address 0x0A0
Bit
Name
Default
Value
R/W
Function
[2:0]
Forward
000
RW
VLAN group forwarding information {Port2, Port1, Port0}
1: Same VLAN group port
0: Not Same VLAN group
[5:3]
Tag
000
RW
Define output packet with Tag or without Tag control
{Port2, Port1, Port0}
1: Tag frame
0: Un-Tag frame
[17:6]
VID
0x000
RW
Full range VID (1 ~ 4095)
[18] Valid 0 RW VLAN Entry 0 Valid bit
1: Valid
0: Not valid
[31:19]
Reserved
0x0000
R
Reserved
5.1.15.6 VLAN Entry 5 Register (VER5)
Address 0x0A4
Bit
Name
Default
Value
R/W
Function
[2:0]
Forward
000
RW
VLAN group forwarding information {Port2, Port1, Port0}
1: Same VLAN group port
0: Not Same VLAN group
[5:3] Tag 000 RW Define output packet with Tag or without Tag control
{Port2, Port1, Port0}
1: Tag frame
0: Un-Tag frame
[17:6]
VID
0x000
RW
Full range VID (1 ~ 4095)
[18]
Valid
0
RW
VLAN Entry 0 Valid bit
1: Valid
0: Not valid
[31:19]
Reserved
0x0000
R
Reserved
86
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
5.1.15.7 VLAN Entry 6 Register (VER6)
Address 0x0A8
Bit
Name
Default
Value
R/W
Function
[2:0]
Forward
000
RW
VLAN group forwarding information {Port2, Port1, Port0}
1: Same VLAN group port
0: Not Same VLAN group
[5:3]
Tag
000
RW
Define output packet with Tag or without Tag control
{Port2, Port1, Port0}
1: Tag frame
0: Un-Tag frame
[17:6]
VID
0x000
RW
Full range VID (1 ~ 4095)
[18] Valid 0 RW VLAN Entry 0 Valid bit
1: Valid
0: Not valid
[31:19]
Reserved
0x0000
R
Reserved
5.1.15.8 VLAN Entry 7 Register (VER7)
Address 0x0AC
Bit
Name
Default
Value
R/W
Function
[2:0]
Forward
000
RW
VLAN group forwarding information {Port2, Port1, Port0}
1: Same VLAN group port
0: Not Same VLAN group
[5:3]
Tag
000
RW
Define output packet with Tag or without Tag control
{Port2, Port1, Port0}
1: Tag frame
0: Un-Tag frame
[17:6]
VID
0x000
RW
Full range VID (1 ~ 4095)
[18] Valid 0 RW VLAN Entry 0 Valid bit
1: Valid
0: Not valid
[31:19]
Reserved
0x0000
R
Reserved
5.1.15.9 VLAN Entry 8 Register (VER8)
Address 0x0B0
Bit
Name
Default
Value
R/W
Function
[2:0]
Forward
000
RW
VLAN group forwarding information {Port2, Port1, Port0}
1: Same VLAN group port
0: Not Same VLAN group
[5:3]
Tag
000
RW
Define output packet with Tag or without Tag control
{Port2, Port1, Port0}
1: Tag frame
0: Un-Tag frame
[17:6]
VID
0x000
RW
Full range VID (1 ~ 4095)
[18] Valid 0 RW VLAN Entry 0 Valid bit
1: Valid
0: Not valid
[31:19]
Reserved
0x0000
R
Reserved
87
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
5.1.15.10 VLAN Entry 9 Register (VER9)
Address 0x0B4
Bit
Name
Default
Value
R/W
Function
[2:0]
Forward
000
RW
VLAN group forwarding information {Port2, Port1, Port0}
1: Same VLAN group port
0: Not Same VLAN group
[5:3]
Tag
000
RW
Define output packet with Tag or without Tag cont rol
{Port2, Port1, Port0}
1: Tag frame
0: Un-Tag frame
[17:6]
VID
0x000
RW
Full range VID (1 ~ 4095)
[18] Valid 0 RW VLAN Entry 0 Valid bit
1: Valid
0: Not valid
[31:19]
Reserved
0x0000
R
Reserved
5.1.15.11 VLAN Entry 10 Register (VER10)
Address 0x0B8
Bit
Name
Default
Value
R/W
Function
[2:0]
Forward
000
RW
VLAN group forwarding information {Port2, Port1, Port0}
1: Same VLAN group port
0: Not Same VLAN group
[5:3]
Tag
000
RW
Define output packet with Tag or without Tag control
{Port2, Port1, Port0}
1: Tag frame
0: Un-Tag frame
[17:6]
VID
0x000
RW
Full range VID (1 ~ 4095)
[18] Valid 0 RW VLAN Entry 0 Valid bit
1: Valid
0: Not valid
[31:19]
Reserved
0x0000
R
Reserved
5.1.15.12 VLAN Entry 11 Register (VER11)
Address 0x0BC
Bit
Name
Default
Value
R/W
Function
[2:0]
Forward
000
RW
VLAN group forwarding information {Port2, Port1, Port0}
1: Same VLAN group port
0: Not Same VLAN group
[5:3]
Tag
000
RW
Define output packet with Tag or without Tag control
{Port2, Port1, Port0}
1: Tag frame
0: Un-Tag frame
[17:6]
VID
0x000
RW
Full range VID (1 ~ 4095)
[18] Valid 0 RW VLAN Entry 0 Valid bit
1: Valid
0: Not valid
[31:19]
Reserved
0x0000
R
Reserved
88
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
5.1.15.13 VLAN Entry 12 Register (VER12)
Address 0x0C0
Bit
Name
Default
Value
R/W
Function
[2:0]
Forward
000
RW
VLAN group forwarding information {Port2, Port1, Port0}
1: Same VLAN group port
0: Not Same VLAN group
[5:3]
Tag
000
RW
Define output packet with Tag or without Tag control
{Port2, Port1, Port0}
1: Tag frame
0: Un-Tag frame
[17:6]
VID
0x000
RW
Full range VID (1 ~ 4095)
[18] Valid 0 RW VLAN Entry 0 Valid bit
1: Valid
0: Not valid
[31:19]
Reserved
0x0000
R
Reserved
5.1.15.14 VLAN Entry 13 Register (VER13)
Address 0x0C4
Bit
Name
Default
Value
R/W
Function
[2:0]
Forward
000
RW
VLAN gro up forwarding i nformation {Port2, Port1, Port0}
1: Same VLAN group port
0: Not Same VLAN group
[5:3]
Tag
000
RW
Define output packet with Tag or without Tag control
{Port2, Port1, Port0}
1: Tag frame
0: Un-Tag frame
[17:6]
VID
0x000
RW
Full range VID (1 ~ 4095)
[18] Valid 0 RW VLAN Entry 0 Valid bit
1: Valid
0: Not valid
[31:19]
Reserved
0x0000
R
Reserved
5.1.15.15 VLAN Entry 14 Register (VER14)
Address 0x0C8
Bit
Name
Default
Value
R/W
Function
[2:0]
Forward
000
RW
VLAN group forwarding information {Port2, Port1, Port0}
1: Same VLAN group port
0: Not Same VLAN group
[5:3]
Tag
000
RW
Define output packet with Tag or without Tag control
{Port2, Port1, Port0}
1: Tag frame
0: Un-Tag frame
[17:6]
VID
0x000
RW
Full range VID (1 ~ 4095)
[18] Valid 0 RW VLAN Entry 0 Valid bit
1: Valid
0: Not valid
[31:19]
Reserved
0x0000
R
Reserved
89
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
5.1.15.16 VLAN Entry 15 Register (VER15)
Address 0x0CC
Bit
Name
Default
Value
R/W
Function
[2:0]
Forward
000
RW
VLAN group forwarding information {Port2, Port1, Port0}
1: Same VLAN group port
0: Not Same VLAN group
[5:3]
Tag
000
RW
Define output packet with Tag or without Tag control
{Port2, Port1, Port0}
1: Tag frame
0: Un-Tag frame
[17:6]
VID
0x000
RW
Full range VID (1 ~ 4095)
[18] Valid 0 RW VLAN Entry 0 Valid bit
1: Valid
0: Not valid
[31:19]
Reserved
0x0000
R
Reserved
5.1.16 IGMP Table Read/Write Control Register (ITCR)
Address 0x0D8
Bit
Name
Default
Value
R/W
Function
[0]
MC_Src_Filter
0
RW
Layer 2 Multicast Source Port Filter Enable
1: Drop the multicast packet if source port isn’t belong to this multicast group
0: Broadcast the multicast pack et
if source port is not belong to this multicast
group
For example, Assume the static multicast MAC address (01-00-00-00-00-
01)
in t h e routing tabl e on l y register por t 0 a n d port 1 a s port map group, if
port 2
receive this registered multicast packet then forwarding engine will either
drop or bro a dcast this multicast packet depend on MC_Sr c _Filter setting.
[1] MCIP_Mode 0 RW IGMP Multicast IP Mode Enable.
0: Drop this multicast IP packet if not found
in the IGMP table entries (IER0 ~
IER7)
1: Broadcast the unknown IP multicast packet
if not found in the IGMP tab le
entries (IER0 ~ IER7)
[6:2]
IPv6_Snooping
00000
RW
6 Snooping Control Register
[0]: Snooping IPv6 ICMPv4 packet to CPU port
The following condition need to be matched:
1. IPv6 Multicast Packet
2. Next header =1 or Next header =0 and extend Next header1=1
3. Hop limit = 1
[1]: Snooping IPv6 ICMPv6 packet to CPU port.
The following condition need to be matched:
1. IPv6 Multicast Packet
2. Next header =58 or Next header =0 and extend Next header1=58
3. Hop limit = 1
[2]: Snooping all the ICMPv4/IPv6 Packets and hop limit=1 to the CPU port.
[3]: Snooping all the ICMPv6/IPv6 Packets and hop limit=1 to the CPU port.
[
4]: S noopin g all t he IPv6 pa ckets w ith Ne xt h eader = 43, 44, 50, 51 an d 60 to
the CPU por t.
[7]
IPv6_Snooping
En
0
RW
IP v6 Snoopi ng function Enab le
1: Enable IPv6_Snooping [4:0] function
0: Normal (Default)
[9:8]
Reserved
00
RW
Reserved
90
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
[15:10]
Reserved
000000
R
Reserved
[17:16]
Reserved
00
RW
Reserved
[23:18]
Reserved
000000
R
Reserved
[25:24]
Reserved
00
RW
Reserved
[31:26]
Reserved
000000
R
Reserved
5.1.17 LED Control Register (LCR)
Address 0x0DC
Bit Name
Default
Value
R/W
Function
[7:0] Sel_led0 0x00 RW Select LED PIN0 o utp ut function
[7] FullDuplex/Collision
[6] 10Base-T
[5] Collision
[4] TX activity
[3] RX activity
[2] Link/Act.
[1] Full duplex
[0] 100Base-TX
NOTE: The user can turn on multiple functions at the same time.
For exam ple, Sel_led0=0
0011000 then any RX or TX activity w ill turn on the
LED light on LED0 pi n.
[15:8]
Sel_led1
0x00
RW
Select LED PIN1 output function
[7] Full Duplex/Collision
[6] 10Base-T
[5] Collision
[4] TX activity
[3] RX activity
[2] Link/Act.
[1] Full duplex
[0] 100Base-TX
NOTE: The user can turn on multiple functions at the same time.
[23:16]
Reserved
0x00
RW
Always assign zero
[25:24] En_led 00 RW Enable PHY0 or PHY1’s LED signal output otherwise LED will stay high
(turn off)
00: Turn off both PHY0 and PHY1 LED function
01: Enable PHY0 LED function
10: Enable PHY1 LED function
11: Enable both PHY0 and PHY1 LED function
[31:26]
Reserved
0x00
R
Reserved
91
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
5.1.18 RMON Control Register (RCR)
Address 0x0E0
Bit
Name
Default
Value
R/W
Function
[3:0]
TxMaxCols
0000
RW
Define the collision count for RMON counter offset 0x1D TX Packet with
Multiple Collision Counter.
For example, TxMaxCols=0101 then the RMON offset 0x1D multiple
collision counter will be ba sed on the collision count=5 to count the collision
events.
[4]
ClrAllCounter
0
WC
Write 1 to Clear all RMON counters of all ports.
[7:5]
Reserved
000
R
Reserved
[14:8]
RmonAddr [6:0]
0x00
RW
RmonAddr [6:5] is port address index
00: Port 0
01: port 1
10: port 2
RmonAddr [4:0] is the RMON counter offset address. There are
30 counters
per port. Please reference RDR for each counter’s function.
[15]
CpuRdRmon
0
WC
Write 1 to read RMON
[31:16]
Reserved
0x0000
R
Reserved
Note: Pause Frame will not be counted as multicast frame. The RMON multicast counter will not
include pause frame count.
92
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
5.1.19 RMON Data Register (RDR)
Address 0x0E4
Bit
Name
Default
Value
R/W
Function
[31:0]
RmonData
0x0000
0000
R
RMON Data value [31:0]
Rmon
Addr
Counter Description
0x00
Rx Pa cket Counter
The total number of packets received (include bad packets)
0x01
Rx Good Packet Counter
The total number of good packets received.
0x02
Rx Byte Counter (low 32 bit)
The total number of bytes received (include bad packets).
0x03
Rx Byte Counter (high 32 bi t)
0x04
Rx Broadcast Packet Counter
The total number of good broadcast packets received.
0x05
Rx Multicast Packet Counter
The total number of good multicast packets received.
0x06
Rx PAUSE Frame Counter
The total number of PAUSE frames received.
0x07
Rx Pa cket Lengt h C ounter 1
The total number o f packets received that length is less than 64 bytes
(include bad packets).
0x08
Rx Pa cket Lengt h C ounter 2
The total num ber of packets received that lengt h is 64 bytes (include bad
packets).
0x09 Rx Pa cket Lengt h C ounter 3 The total nu m ber of packets r
eceived that len gth is betw een 65 bytes and
127 bytes (include bad packets).
0x0A Rx Packe t Length Co unt er 4 The total number of packets received that length is between 128 bytes
and 255 bytes (include bad packets).
0x0B Rx P acket Le ngth Counter 5 The total number of packets received that length is between 256 bytes
and 511 bytes (include bad packets).
0x0C Rx Packet Length Count er 6 The total number of packets received that length is between 512 bytes
and 1023 bytes (include bad packets).
0x0D Rx Packet Length Co unter 7 The total number of packets received that length is between 1024 b ytes
and maximum bytes (include bad packets).
0x0E
Rx Pa cket Lengt h C ounter 8
The total number of packets received that length is longer maximum
bytes (include bad packets).
0x0F
Rx CRC Error P acket Co unte r
The total number of packets with CRC error received.
0x10
Rx Alignment Er ror Pa cket
Counter
The total number of packets with A li gn ment error received and less t han
maximum packet size.
0x11
Fragment Error Counter
The total number of packets received that are less than 64 bytes, but has
an either CRC error or Alignment Error.
0x14
TX Packet Counter
The total number of packets tra nsmitted or aborted.
0x15
TX Good Packet Counter
The total number of good packets transmitted successfully.
0x16
TX Byte Counter (low 32 bit)
The total number of bytes transmitted or aborted.
0x17
TX Byte Counte r (high 32 bit)
0x18
TX Broadcast Packet Counter
The total number of good broadcast packets transmitted successfully.
0x19
TX Multicast Packet Counter
The total number of good multicast packets transmitted successfully.
0x1A
TX PAUSE Frame Counter
The total number of PAUSE frames transmitted.
0x1B
TX Collision Counter
The total number of collisio ns oc c urr e d.
0x1C TX Packet with one Collision
Counter
The total number of packets transmitted successfully which experienced
one collision.
0x1D TX Packet with Multiple
Collision Counter
The total number of packets transmitted successfully which experienced
multiple collisions.
0x1E TX Excessive Collision Counter The total number of packets aborted due to experienced excessive
collisions.
0x1F
TX Late Collision Counter
The total number of packets experienced late collisions.
93
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
5.1.20 DSCP QoS mapping table Register (DQR)
Address 0x0E8 (DQR0)
Bit
Name
Default
Value
R/W
Function
[31:0]
DSCP0
0x0000
0000
RW
Map DSCP [5:0] (Refer to Fig 17) 64 level into one of the internal 4
possible queues
[1:0]: Mapping to inter nal queue (0 ~ 3) when DSCP [5:0]=0
[3:2]: Mapping to inter nal queue (0 ~ 3) when DSCP [ 5:0]=1
[5:4]: Mapping to inter nal queue (0 ~ 3) when DSCP [5:0]=2
[7:6]: Mapping to inter nal queue (0 ~ 3) when DSCP [5:0]=3
[9:8]: Mapping to inter nal queue (0 ~ 3) when DSCP [5:0]=4
[11:10]: Mapping to i nternal que ue (0 ~ 3) when DSCP [5:0]=5
[13:12]: Mapping to i nternal que ue (0 ~ 3) when DSCP [5:0]=6
[15:14]: Mapping to i nternal que ue (0 ~ 3) when DSCP [5:0]=7
[17:16]: Mapping to i nternal que ue (0 ~ 3) when DSCP [5:0]=8
[19:18]: Mapping to i nternal que ue (0 ~ 3) when DSCP [5:0]=9
[21:20]: Mapping to i nternal que ue (0 ~ 3) when DSCP [5:0]=10
[23:22]: Mapping to i nternal que ue (0 ~ 3) when DSCP [5:0]=11
[25:24]: Mapping to i nternal que ue (0 ~ 3) when DSCP [5:0]=12
[27:26]: Mapping to i nternal que ue (0 ~ 3) when DSCP [5:0]=13
[29:28]: Mapping to inter nal queue (0 ~ 3) when DSCP [ 5:0]=14
[31:30]: Mapping to inter nal queue (0 ~ 3) when DSCP [ 5:0]=15
Address 0x0EC (DQR1)
Bit
Name
Default
Value
R/W
Function
[31:0]
DSCP1
0x0000
0000
RW
Map DSCP [5:0] 64 level into internal 4 possible queues
[1:0]: Mapping to inter nal queue (0 ~ 3) when DSCP [5:0]=16
[3:2]: Mapping to inter nal queue (0 ~ 3) when DSCP [5:0]=17
[5:4]: Mapping to inter nal queue (0 ~ 3) when DSCP [5:0]=18
[7:6]: Mapping to inter nal queue (0 ~ 3) when DSCP [5:0]=19
[9:8]: Mapping to internal queue (0 ~ 3) when DSCP [5:0]=20
[11:10]: Mapping to i nternal que ue (0 ~ 3) when DSCP [5:0]=21
[13:12]: Mapping to i nternal que ue (0 ~ 3) when DSCP [5:0]=22
[15:14]: Mapping to i nternal que ue (0 ~ 3) when DSCP [5:0]=23
[17:16]: Mapping to internal queue (0 ~ 3) when DSCP [ 5:0]=24
[19:18]: Mapping to i nternal que ue (0 ~ 3) when DSCP [5:0]=25
[21:20]: Mapping to i nternal que ue (0 ~ 3) when DSCP [5:0]=26
[23:22]: Mapping to i nternal que ue (0 ~ 3) when DSCP [5:0]=27
[25:24]: Mapping to i nternal que ue (0 ~ 3) when DSCP [5:0]=28
[27:26]: Mapping to i nternal que ue (0 ~ 3) when DSCP [5:0]=29
[29:28]: Mapping to i nternal que ue (0 ~ 3) when DSCP [5:0]=30
[31:30]: Mapping to inter nal queue (0 ~ 3) when DSCP [ 5:0]=31
94
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
Address 0x0F0 (DQR2)
Bit
Name
Default
Value
R/W
Function
[31:0]
DSCP2
0x0000
0000
RW
Map DSCP [5:0] 64 level into internal 4 possible queues
[1:0]: Mapping to inter nal queue (0 ~ 3) when DSCP [5:0]=32
[3:2]: Mapping to inter nal queue (0 ~ 3) when DSCP [5:0]=33
[5:4]: Mapping to internal queue (0 ~ 3) when DSCP [5:0]=34
[7:6]: Mapping to inter nal queue (0 ~ 3) when DSCP [5:0]=35
[9:8]: Mapping to inter nal queue (0 ~ 3) when DSCP [5:0]=36
[11:10]: Mapping to i nternal que ue (0 ~ 3) when DSCP [5:0]=37
[13:12]: Mapping to i nternal que ue (0 ~ 3) when DSCP [5:0]=38
[15:14]: Mapping to i nternal que ue (0 ~ 3) when DSCP [5:0]=39
[17:16]: Mapping to i nternal que ue (0 ~ 3) when DSCP [5:0]=40
[19:18]: Mapping to i nternal que ue (0 ~ 3) when DSCP [5:0]=41
[21:20]: Mapping to i nternal que ue (0 ~ 3) when DSCP [5:0]=42
[23:22]: Mapping to i nternal que ue (0 ~ 3) when DSCP [5:0]=43
[25:24]: Mapping to i nternal que ue (0 ~ 3) when DSCP [5:0]=44
[27:26]: Mapping to i nternal que ue (0 ~ 3) when DSCP [5:0]=45
[29:28]: Mapping to i nternal que ue (0 ~ 3) when DSCP [5:0]=46
[31:30]: Mapping to i nternal que ue (0 ~ 3) when DSCP [5:0]=47
Address 0x0F4 (DQR3)
Bit
Name
Default
Value
R/W
Function
[31:0]
DSCP3
0x0000
0000
RW
Map DSCP [5:0] 64 level into internal 4 possible queues
[1:0]: Mapping to inter nal queue (0 ~ 3) when DS CP [5:0]=48
[3:2]: Mapping to inter nal queue (0 ~ 3) when DSCP [5:0]=49
[5:4]: Mapping to inter nal queue (0 ~ 3) when DSCP [5:0]=50
[7:6]: Mapping to inter nal queue (0 ~ 3) when DSCP [5:0]=51
[9:8]: Mapping to inter nal queue (0 ~ 3) when DSCP [5:0]=52
[11:10]: Mapping to i nternal que ue (0 ~ 3) when DSCP [5:0]=53
[13:12]: Mapping to i nternal que ue (0 ~ 3) when DSCP [5:0]=54
[15:14]: Mapping to i nternal que ue (0 ~ 3) when DSCP [5:0]=55
[17:16]: Mapping to i nternal que ue (0 ~ 3) when DSCP [5:0]=56
[19:18]: Mapping to i nternal que ue (0 ~ 3) when DSCP [5:0]=57
[21:20]: Mapping to i nternal que ue (0 ~ 3) when DSCP [5:0]=58
[23:22]: Mapping to i nternal que ue (0 ~ 3) when DSCP [5:0]=59
[25:24]: Mapping to i nternal que ue (0 ~ 3) when DSCP [5:0]=60
[27:26]: Mapping to internal queue (0 ~ 3) when DSCP [5:0]=61
[29:28]: Mapping to i nternal que ue (0 ~ 3) when DSCP [5:0]=62
[31:30]: Mapping to i nternal que ue (0 ~ 3) when DSCP [5:0]=63
95
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
5.1.21 Interrupt Status and Mask Register (ISMR)
Address 0x0F8
Bit
Name
Default
Value
R/W
Function
[0]
AgingOut_st
0
RW
Routing Ta ble entry aging out interrupt status bit
This interrupt indica te s one of routing table e ntry was aging out.
CPU needs to write one to clear this interrupt status.
1:interrupt active.
0:interrupt inactive.
When one of routing table entry w as aging out, the
interrupt status will chang e
to active. Nothing to do with the mask bit.
[1]
NewLearn_st
0
RW
Routing Ta ble l earn new SA entry interrupt status bit
This interrupt indica te s the routing table learns a new sour ce MAC address.
CPU needs to write one to clear this interrupt status.
1:interrupt active.
0:interrupt inactive.
When learning a new source MAC address, the
interrupt status will chang e to
active. Nothing to do with the mask bit
[2] CPIError_st 0 RW CPI Err or detection interrupt status bit
CPU needs to write one to clear this interrupt status.
1:interrupt active.
0:interrupt inactive.
When CPI dete c t e rror, the inter r up t status will change to active.
[3]
CPOEmpty_st
0
RW
CPO Empty inter rupt status bit
CPU needs to write one to c le a r this interr upt status.
1:interrupt active.
0:interrupt inactive.
When CPO FIFO is empty then this interrupt status will change to active.
[4]
CPIFlowCtrlO
n_st
0
RW
CPI Flow Control On interrupt status bit
CPU needs to write one to clear this interrupt status.
1:interrupt active.
0:interrupt inactive.
When CPI flow control is on then this interrupt status will change to active.
[5] CPIFlowCtrlOf
f_st 0 RW CPI Flow Control Off interrupt status bit
CPU needs to write one to clear this interrupt status.
1:interrupt active.
0:interrupt inactive.
When CPI flow control off is detected then this interrupt status w ill chang e to
active.
[6] LinkChange_st 0 RW Port0~2 link change when aut o-polling enable interrup t status bit.
This interrupt indicate one of three ports has a link change e vent detected.
CPU needs to write one to clear this interrupt status.
1:interrupt active.
0:interrupt inactive.
When l ink change event occur s, the interrupt status will change to active.
Auto-pol ling function needs to be enabled for this interrupt.
[11:7]
Reserved
00000
RW
Reserved
[12] TimerUp_st 0 RW General Timer up interrupt status bit
This interrupt indica te G e ner a l Timer (STCR) is up.
CPU needs to write one to clear this interrupt status.
1:interrupt active.
0:interrupt inactive.
When timer reaches the limit, the inter rupt status will change to active.
TimerUp_St interrupt status has nothing to do with the mask bit.
[13]
SlaveMDIO_st
0
RW
Slave MDC/MDIO receive write command interrupt status bit
When port 2 con fi gures to Rev erse MII/RMII m ode, CPU needs to enable
the
96
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
Slave MDC/MDIO function to let external MII/RMII MAC to perform MII
management read/write operation. If the external MII/RMII MAC performs
MII management write c ycle, this interrupt b it will active.
CPU needs to write one to clear this interrupt.
1:interrupt active.
0:interrupt inactive.
When the Slave MDC /MDIO receives write com m and, the interrupt status
bit
will become active.
[14] GPIO_Int_st 0 R G PIO interrup t status bit
CPU needs to write one to clear this interrupt status.
1:interrupt active.
0:interrupt inactive.
[15]
Reserved
0
R
Reserved
[16]
AgingOut_mk
1
RW
Routing Ta ble entry aging out interrupt mask bit
When this mask bit is set to one, the
hardware INT pin will mask out
AgingOut i nterrupt.
1: M ask AgingOut interrupt on INT pin.
0: Unmask AgingO ut interrup t on INT pin.
[17] NewLearn_mk 1 RW Routing Tab l e lea rn new SA entry interrupt mask bit
When this mask bit is set to one, the
hardware INT pin will mask out
NewLearn interrupt.
1: M ask NewLear n inter rupt on IN T pin.
0: Unmask N ewLearn interrupt o n INT pin.
[18]
CPIError_mk
1
RW
CPI Error detection interrupt mask bit
When this mask bit is set to one, the
hardw are INT pin w ill m ask ou t CPI Error
interrupt.
1: Mask CPIError interrup t on INT pin.
0: Unmask CPIError interrupt on INT pin.
[19]
CPOEmpty_m
k
1
RW
CPO Empty inter rupt mask bit
When this mask bit is set to one, the
hardware INT pin will mask out CPO
empty interrupt.
1: Mask CPOEmpty interrupt on INT pin.
0: Unmask CPOEmpty interrupt on INT pin.
[20]
CPIFlowCtrlO
n_mk
1
RW
CPI Flow Control On interrupt mask bit
When this mask bit is set to one, the
hardware INT pin will mask out
CPIFlowCtrlOn interrupt.
1: Mask CPIFlowCtrlOn interrupt on INT pin.
0: Unmask CPIFlowCtrlOn interrup t on I NT pin.
[21] CPIFlowCtrlOf
f_mk 1 RW CPI Flow Control Off interrupt mask bit
When this mask bit is set to one, the
hardware INT pin will mask out
CPIFlowCtrlOff interrupt.
1: Mask CPIFlowCtrlOff interrupt on INT pin.
0: Unmask CPIFlowCtrlOff interrupt on INT pin.
[22]
LinkChange_m
k
1
RW
Po rt0 ~2 link change when aut o-polling enable interrup t mask bit
When this mask bit is set to one, the hardware INT pin will mask out
LinkChange interrupt.
1: Mask LinkChange inte rrupt on INT pin.
0: Unmask LinkChange interrupt on INT pin.
[27:23]
Reserved
11111
RW
Reserved
[28]
TimerUp_mk
1
RW
Internal Hardware Timer up interrupt mask bit
When this mask bit is set to one, the h ardware INT pin will m ask out TimerUp
interrupt.
1: Mask TimerUp interrupt on INT pin.
0: Unmask TimerUp interrup t on I NT pin.
[29] SlaveMDIO_m
k 1 RW Slave MDC/MDIO receive write command interrupt mask bit
When this mask bit is set to one, the
hardware INT pin will mask out
SlaveMDIO interrupt.
1: Mask SlaveMDIO inte rrupt on INT pin.
97
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
0: Unmask SlaveMDIO interrupt on IN T pin.
[30]
GPIO_Int_mk
1
RW
GPIO interr up t mask bit
When this mask bit is set to one, the
hardware INT pin will mask out
GPIO_Int interrupt.
1: Mask GPIO_Int inter rupt on INT pin.
0: Unmask GPIO_Int interrupt on INT pin.
[31]
Reserved
1
RW
Reserved
5.1.22 User-Defined Sniffer Packet Type Register (USTR)
Address 0x100
Bit
Name
Default
Value
R/W
Function
[15:0]
EthType [15:0]
0x8863
RW
User-Defined Sniffer Ethernet Packet Type register
(Default: 0x8863 Seccsion Discovery)
If the SFCR0 Type_L2 [6] is set to one, then the sniffer logic will copy the
packet to sniffer port if the pac kets layer 2 p rotoco l matches with this value.
[23:16]
IPv4Type [7:0]
0x73
RW
User-Defined Sniffer IPv4 Packet Protoco l register
(Default: 0x73 L2TP)
If the SFCR1 Type_IP v4 [5] is set to one, then the sniffer logic will copy the
packet to sniffer port if the pac kets IPv4 protocol matches with this value.
[31:24]
IPv6Type [7:0]
0x73
RW
User-Defined Sniffer IPv6 Packet Protoco l register
(Default: 0x73 L2TP)
If the SFCR1 Type_IP v6 [5] is set to one, then the sniffer logic will copy the
packet to sniffer port if the pac kets IPv6 protocol matches with this value.
98
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
5.1.23 Wake-On-LAN Configuration Register (WCR)
Address 0x104
Bit
Name
Default
Value
R/W
Function
[0]
En_linkchange
0
0
RW
Enable Por t 0 link s tatus c hange as one of the wake up condition.
Wakeup condition: PHY0 link done status toggle
from low to high or high to
low.
1: Enable
0: Disable
[1]
En_MagicPack
et0
0
RW
Enable Port 0 Magic Packet detection as one of the wake up condition.
Wakeup condition:
Detect 0xFFFFFFFFFFFF follow by repeated 16 times
DA_MAC (P0DAR0) pattern
anywhere within the payload and good CRC
value present.
1: Enable
0: Disable
[2]
En_WakeUpfr
ame0
0
RW
Enable Port 0 Microsoft wakeup frame detector as one of the wakeup
condition.
Wakeup condition: Calculate CRC value across
all the mask bits that match
the expected CRC value and the packet has a good CRC value in the end.
1: Enable
0: Disable
[4:3] En_cascade0
[1:0] 00 RW Enable cascade function on Port 0
01: cascade offset0 and offset1 together
10: cascade offset1 and offset2 together
11: cascade offset0, offset1, and offset2 all three pointer together
00: disable cascade function
[5] En_linkchange
1 0 RW Enable Port 1 link status cha nge as one of the wake up c ondition
Wakeup condition: PHY1 link done status toggle
from low to high or high to
low.
1: Enable
0: Disable
[6]
En_MagicPack
et1
0
RW
Enable Port 1 Magic Packet detection as one of the wake up condition.
Wakeup condition:
Detect 0xFFFFFFFFFFFF follow by repeated 16 times
DA_MAC (P0DAR0) pattern
anywhere within the payload and good CRC
value present.
1: Enable
0: Disable
[7]
En_WakeUpfr
ame1
0
RW
Enable Port 1 Microsoft wakeup frame detector as one of the wakeup
condition.
Wakeup condition: Calculate CRC value across
all the mask bits that match
the expected CRC value and the packet has a good CRC value in the end.
1: Enable
0: Disable
[9:8]
En_cascade1
[1:0]
00
RW
Enable cascade function on Port 1
01: cascade offset0 and offset1 together
10: cascade offset1 and offset2 together
11: cascade offset0-2 all three pointer together
00: disable cascade function
[10]
Wakeup_switc
hon
0
RW
1: Switch-ON mode enabled when thi s bit is set to one.
During the wakeup mode, the switch will
continue switching packet
between port 0 and port 1.
0: Switch-OFF mode, disable switching packet when in wakeup mod e.
[13:11]
Reserved
000
R
Reserved
[14]
Wake_up0
0
R
Wakeup Event detect on port 0
1: Port 0 wake up
0: Port 0 not wake up
99
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
[15]
Wake_up1
0
R
Wakeup event detect on port 1
1: Port 1 wake up
0: Port 1 not wake up
[16] Wakeup mode 0 RW 1: Enable Wake-On-LAN detection function
0: Disable Wakeup mode
[17] Sleep mode 0 RW 1: Sleep/Suspend Mode. The switch will turn off
all the internal cloc ks. And
the chip is in the minimum power consumption state.
0: Disable sleep mode
The user can w rite any value to address 0x1F4(SMER) t o exit the sleep m ode!
[18]
Clear_wakeup
0
RW
Clear wakeup signal when CPU is already inform to wake up by writing one
to clear the wakeup s tatus.
1: Clear the wake up mode
0: Normal (Default)
[19] Clear_
sleep_status 0 RW In norm al mode, write one to clear the
sleep mode status w hen back from sleep
mode operation.
1: Clear sleep mode status bit
0: Normal
[20]
Wakeup_level
1
RW
1: define PME pin is level sensitive.
0: define PME pin is active low or tri-state.
[21]
Wakeup_pulse
0
RW
1: define PME pin is a pulse signal.
0: define PME pin is a level signal.
[22]
Wakeup_active
1
RW
PME pin active state
1: PME pin is active high
0: PME pin is active low
Wakeup_level=
1
Wakeup_pulse
=0
Wakeup_pulse=1
Wakeup_active
=0
Low
____ _____
|___|
Wakeup_active
=1
High
____
____| |___
Wakeup_level=0
(Default Hi-Z, active low)
zzzzzzz zzzzzz
|_____|
[23] Reset_pme 0 RW Reset PME pin to d efault value before re-start W O L dete c tion
1: Reset PME
0: Normal
[24] Linkchange_st
atus[0] 0 R Li nk change st atus o n port 0
1: Link c hange event found on p ort 0
0: Idle
[25]
MagicPacket_s
tatus[0]
0
R
Magic frame detection status on port 0
1: Magic Frame found on port 0
0: Idle
[26]
WakeUpframe
_status[0]
0
R
Microsoft wakeup detection status on port 0
1: Microsoft wakeup frame found on port 0
0: Idle
[27] Linkchange_st
atus[1] 0 R Li nk change st atus o n port 1
1: Link c hange event found on p ort 1
0: Idle
[28] MagicPacket_s
tatus[1] 0 R Magic frame detection status on port 1
1: Magic Frame found on port 1
0: Idle
[29]
WakeUpframe
_status[1]
0
R
Microsoft wakeup detection status on port 1
1: Microsoft wakeup frame found on port 1
0: Idle
[30]
Reserved
0
R
Reserved
[31]
PME
0
R
Power Management Enable status (Read only)
PME pin status
100
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
5.1.24 Wake-ON-LAN Setup Register (WSR)
Address 0x108
Bit
Name
Default
Value
R/W
Function
[3:0]
P0_offset0
0000
RW
Filter 0 Double-word Offset pointer for mask0 register on Port 0.
For example, if P0_offset0=3 then the mask0 index register will start from
Ethernet Packet type field (byte 11 after DA and SA MAC)
[7:4]
P0_offset1
0000
RW
Filter 1 Double word Offset pointer for mask1 regi s t er o n Po rt 0
[11:8]
P0_offset2
0000
RW
Filter 2 Double word Offset pointer for mask2 regi s t er o n Po rt 0
[14:12]
P0_en_mask
[2:0]
000
RW
Enable mask byte for 3 different possible filter rules on P ort 0
[15]
En_da_cmp
0
RW
Enable DA comparison as one of the wakeup condition for Port 0. (P0DAR0,
P0DAR1)
[19:16]
P0_offset0
0000
RW
Filter 0 Double word Offset pointer for mask0 regi s t er o n Po rt 1
[23:20]
P0_offset1
0000
RW
Filter 1 Double word Offset pointer for mask1 regi s t er on Port 1
[27:24]
P0_offset2
0000
RW
Filter 2 Double word Offset pointer for mask2 regi s t er o n Po rt 1
[30:28]
P0_en_mask
[2:0]
000
RW
Enable mask byte for 3 different possible filter rules on P ort 1
[31]
En_da_cmp
0
RW
Enable DA comparison as one of the wakeup condition on Por t 1. (P1DAR0,
P1DAR1)
5.1.25 Port 0 Wakeup Frame Mask0 ~ 2 Register (P0WMR0, P0WMR1, P0WMR2)
Address 0x10C (P0WMR0)
Bit
Name
Default
Value
R/W
Function
[31:0]
rgi_mask0
0x0000
0000
RW
Wake-up fram e masked byt e for m ask 0 on Port 0. Each bit i s represent a by te.
For example, if rgi_mask0=0xc0000000 then the CRC calculation will only
calculate the first and 2
nd
byte after the P0_o ffset0 pointer locatio n
Address 0x110 (P0WMR1)
Bit Name
Default
Value
R/W
Function
[31:0] rgi_mask1 0x0000
0000 RW Wake-up frame masked byte for mask1 for Port 0
Address 0x114 (P0WMR2)
Bit
Name
Default
Value
R/W
Function
[31:0]
rgi_mask2
0x0000
0000
RW
Wake-up frame masked byte for mask2 for Port 0
101
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
5.1.26 Port 0 Wakeup Frame CRC Mask 0 ~ 2 Register (P0WCR0, P0WCR1, P0WCR2)
Address 0x118 (P0WCR0)
Bit
Name
Default
Value
R/W
Function
[31:0]
rgi_crc0
0x0000
0000
RW
Wake-up frame expected CRC value for mask0 register on Port 0. This is the
pre-calculated mask byte data’s expected CRC value for filter rule 0 .
Address 0x11C (P0WCR1)
Bit
Name
Default
Value
R/W
Function
[31:0] rgi_crc1 0x0000
0000 RW Wake-up frame expected CRC value for mask1 register on Port 0.
This is the pre-calculated mask byte data’s expected CRC value for filter rul
e
1.
Address 0x120 (P0WCR2)
Bit
Name
Default
Value
R/W
Function
[31:0]
rgi_crc2
0x0000
0000
RW
Wake-up frame expected CRC value for mask2 register on Port 0.
This is the pre-
calculated mask byte data’s expected CRC value for filter rule
2.
5.1.27 Port 1 Wakeup Frame Mask0 ~ 2 Register (P1WMR0, P1WMR1, P1WMR2)
Address 0x124 (P1WMR0)
Bit
Name
Default
Value
R/W
Function
[31:0] rgi_mask0 0x0000
0000
RW Wake-up frame masked byte for mask0 for Port 1
Address 0x128 (P1WMR1)
Bit
Name
Default
Value
R/W
Function
[31:0]
rgi_mask1
0x0000
0000
RW
Wake-up frame masked byte for mask1 for Port 1
Address 0x12C (P1WMR2)
Bit
Name
Default
Value
R/W
Function
[31:0] rgi_mask2 0x0000
0000
RW Wake-up frame masked byte for mask2 for Port 1
102
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
5.1.28 Port 1 Wakeup Frame CRC Mask 0 ~ 2 Register (P1WCR0, P1WCR1, P1WCR2)
Address 0x130 (P1WCR0)
Bit
Name
Default
Value
R/W
Function
[31:0]
rgi_crc0
0x0000
0000
RW
Wake-up frame expected CRC value for mask0 register on Port 1.
This is the pre-calculated mas k by t e data’ s ex pected CRC val
ue for filter rule
0.
Address 0x134 (P1WCR1)
Bit Name
Default
Value
R/W
Function
[31:0]
rgi_crc0
0x0000
0000
RW
Wake-up frame expected CRC value for mask1 register on Port 1.
This is the pre-calculated mask byte data’s expected CRC value for filter rul
e
1.
Address 0x138 (P1WCR2)
Bit
Name
Default
Value
R/W
Function
[31:0] rgi_crc2 0x0000
0000 RW Wake-up frame expected CRC value for mask2 register on Port 1.
This is the pre-
calculated mask byte data’s expected CRC value for filter rule
2.
5.1.29 Auto-Polling Control Register (ACR)
Address 0x140
Bit
Name
Default
Value
R/W
Function
[4:0] P0_phy_addr
[4:0]
00000 RW Port 0 Polling internal PHY ID r egister
[7:5]
Reserved
000
R
Reserved
[12:8]
P1_phy_addr
[4:0]
00000
RW
Port 1 Polling internal P HY I D r egister
[15:13]
Reserved
000
R
Reserved
[20:16]
P2_phy_addr
[4:0]
00000
RW
Port 2 Polling external PHY ID register
[21]
P0_poll_sel
0
RW
1: Auto-polling logic will Check BMCR register ( PHY addr. 0x0) status to
make decision on port 0 speed and duplex
0: Auto-polling logic will check ANAR register (PHY address 0x4) sta tus to
make decision on port 0 speed and duplex. (default )
[22] P1_poll_sel 0 RW 1: Auto-polling logic will Check BMCR register (PHY add r . 0x0) status to
make decision on port 1 speed and duplex
0: Auto-polling logic will check ANAR register (PHY address 0x4) sta tus to
make decision on port 1 speed and duplex. (default )
[23]
P2_poll_sel
0
RW
1: Auto-polling logic will Check BMCR register ( PHY addr. 0x0) status to
make decision on port 2 speed and duplex
0: Auto-polling logic will check ANAR register (PHY address 0x4) sta tus to
make decision on port 2 speed and duplex. (default )
[24] P0_poll_en 0 RW Enable Por t 0 Auto-polling function
If set to one then h ardw are w ill auto-polling internal P
HY register setting and
update Port 0 Mac Control Register (P0MCR) enable, speed, and duplex
information.
103
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
[25]
P1_poll_en
0
RW
Enable Port 1 Auto-polling function.
If set to one then h ardw are w ill auto-
polling internal PHY register setting and
update Port
1 Mac Control Register (P1MCR) enable, speed, and duplex
information.
[26]
P2_poll_en
0
RW
Enable Port 2 Auto-polling function.
If port 2 is configured as a MII or RMII interface and connected with an
external PHY, then this bit should set to one.
If thi s bit is set to one then the AX8861 3 will auto-
polling the external PHY
register setting and update Port 2 Mac Control Register (P2 M CR) enable bit,
speed, and duplex information.
[27]
Reserved
0
R
Reserved
[28] P0_poll_fc 1 RW Enable Port 0 Auto-polling Flow control function.
Auto-
polling PHY0’s register and update flow control information on Port 0
setting.
If PHY0 is in full duple x mode then
1: port 0 MAC Flow control depend on PHY0 and PHY0’s
link partne r PHY
pause capability
0: port 0 MAC disable Flow control
If PHY0 is in hal f duplex mode then
1: port 0 MAC enable Flow control
0: port 0 MAC disable Flow control
[29] P1_poll_fc 1 RW Enable Port 1 Auto-polling Flow control function.
Auto-polling PHY1’s register and update flow control information on P
ort 1
setting.
If PHY1 is in full duple x mode then
1: port 1 MAC Flow control depend on PHY1 and PHY1’s
link partne r PHY
pause capability
0: port 1 MAC disable Flow control
If PHY1 is in hal f duplex mode then
1: port 1 MAC enable Flow control
0: port 1 MAC disable Flow control
[30]
P2_poll_fc
1
RW
Enable Port 2 Auto-polling Flow control function.
Auto-polling external
PHY register and update flow control information on
Port 2 setting.
If external PHY i s in full duplex mode the n
1: port 2 MAC Flow control depend on external PHY and it’s
link partner
PHY’s pause capability
0: port 2 MAC disable Flow control
If external PHY is in half duplex mode then
1: port 2 MAC enable Flow control
0: port 2 MAC disable Flow control
[31]
Reserved
0
R
Reserved
104
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
5.1.30 EEROM Control Register (ECR)
Address 0x144
Bit
Name
Default
Value
R/W
Function
[21:0]
Eeprom_data
[21:0]
0x0000
00
RW
EEROM data [21:0]
When EEROM size=”01”: EEROM data [21:0] = {0000,SB, opcode [1:0]
,
Addr [6:0], Data [7:0]}
When EEROM size=”10 or 11”: EEROM data [21:0] = {00,SB, opcode [1:0]
,
Addr [8:0], Data [7:0]}
SB means StartBit, always set to one.
Please also reference your EEPROM
device datasheet.
[23:22]
Reserved
00
RW
Reserved
[24]
Eeprom_Check
Busy
0
RW
Enable Hardw are busy state checking function when w rite or erase EEPROM.
With write or erase command, the EEP ROM needs
about 10 ms to finish the
command. If set this bit to 1, the EEPROM controller will check the
EEPROM
busy state until the EEPROM return to ready state.
And the EEPROM controller then set Eeprom_valid to 1.
If set this bit to 0 then the EEPROM controller will never check the
EEPROM
busy state, CPU should wait 10ms for next command.
[26:25]
Reserved
00
R
Reserved
[28:27] Eeprom_size
[1:0] 00 RW EEROM si ze
00: reserve
01: 1K Bit (93c46)
10: 2K Bit (93c56)
11: 4K Bit (93c66)
When CPU sends the read or write command to the EEP ROM, CPU needs to
set these two bits first. So the EEPROM controller knows the address space.
[29]
Reserved
0
RW
Reserved
[30] Eeprom_valid 0 R EE ROM valid
CPU needs p olling this bit to confirm the EEPROM controller has
finish the
read, write or erase command.
In the read command, Eeprom_valid=1 means Eeprom_data
[7:0] is valid
data.
1: finish the read/write command.
0: not yet fi ni s h the read/write command.
[31]
Eeprom_req
0
WC
EEROM request (write one clear)
CPU sets this bit to one to pass the command to the EEPROM device.
The
command is include in the Eeprom_data[21:0] register. I f CPU wants to
send
the read/write com man d to the EEPROM, CPU needs to read the Prom_m
ode
register in CIRR first to make sure EEPROM addressable size.
CPU also needs to check the B ootFinish or the
ChipInitDone bits to co nfirm
that the Boot lo a der module complete the load ing and stay in idle state.
105
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
5.1.31 Boot Loader Control Register (BLCR)
Address 0x148
Bit
Name
Default
Value
R/W
Function
[15:0]
Reserved
0x0000
R
Reserved
[29:16]
Reserved
0x0000
R
Reserved
[30] BootFinish 0 R Boot loader operation done (read only)
After power-on or hardware reset, the boot loader module will check the
Prom_mode register in the CIRR, if the prom _m ode[1:0] i s not “00” , then
the
boot loader module will enable the eeprom controller to read the EEPROM
data and configure all the AX88613 inter nal r e gister s.
When the boot loader m odule fi nishe s loading the EEPROM data, then
this bit
will set to 1.
1: Boot loader module has finish loading and stay in idle state.
0: Boor loader module has not fi nish loading or prom_mode [1:0] is “00”.
[31]
Boot_En
0
RW
Software start boot loader process when set to one.
CPU can set this bit to 1 to force the boot loader module reload the
EEPROM
data and reconfigure all the AX88613 inter nal r e gisters
after ChipInitDone is
set to 1.
When set this bit to 1, both the BootF inish and the
ChipInitDone will clear to
0 , and the n C PU ne eds polling the BootFinish or the ChipInitDone status to
confirm the B oot loader module finish the process and stay in idle state.
5.1.32 IO Pad Pull-Up/Pull-Down Control Register (IOCR)
Address 0x14C
Bit
Name
Default
Value
R/W
Function
[4:0]
Rgi_pupd
00000
RW
IO Pad Pull-up and Pull-down control register.
[0]: P ull d own the following IO pin when set to one
CPU_DATA8 ~ CPU_DATA15
[1]: P ull d own the following IO pin when set to one
CPU_DATA16 ~ CPU_DATA31
[2]: P ull up the follo wing IO pin when set to one
CPU_DATA16 ~ CPU_DATA31
[3]: P ull d own the following port 0 MII inp ut pins when set to one.
P0_MDIO, P0_MDC, MII0_RXD0 ~ MII0_RXD3, MII0_RX_DV,
MII0_RX_COL, MII0_RX_CRS, MII0_RX_CLK, MII0_TX_CLK.
[4]: P ull d own the following port 1 MII input pi ns when set to one.
P1_MDIO, P1_MDC, MII1_RXD0 ~ MII1_RXD3, MII1_RX_DV,
MII1_RX_COL, MII1_RX_CRS, MII1_RX_CLK, MII1_TX_CLK.
[31:5]
Reserved
0x0000
000
R
Reserved
106
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
5.1.33 Multicast IP for IGMP Snooping Entry 0 - 7 Register (IER0 ~ IER7)
5.1.33.1 Multicast IP Entry 0 Register (IER0)
Address 0x150
Bit
Name
Default
Value
R/W
Function
[27:0]
MulticastIP
0x0000
000
RW
Multicast IP [27:0] (IP [31:28] should be 1110 if multicast IP )
[30:28]
Multicastportm
ap
000
RW
Multicast port map [30:28] {Port 2, Port 1, Port 0}
Note: LGCR [14] IGMP mode will override this mapping if DIP with IGMP
protocol received.
[31] Valid 0 RW Valid
1: Entry valid
0: Entry invalid
5.1.33.2 Multicast IP Entry 1 Register (IER1)
Address 0x154
Bit
Name
Default
Value
R/W
Function
[27:0] MulticastIP 0x0000
000
RW Multicast IP [27 :0] (IP [31:28] should be 1110)
[30:28] Multicastportm
ap 000 RW Multicast port map [30:28]
Note: LGCR [14] IGMP mode will override this mapping if DIP with IGMP
protocol received.
[31] Valid 0 RW Valid
1: Entry valid
0: Entry invalid
5.1.33.3 Multicast IP Entry 2 Register (IER2)
Address 0x158
Bit Name
Default
Value
R/W
Function
[27:0] MulticastIP 0x0000
000 RW Multicast IP [27:0] (IP [31:28] should be 1110)
[30:28] Multicastportm
ap 000 RW Multicast port map [30:28]
Note: LGCR [14] IGMP mode will override this mapping if D IP with IGMP
protocol received.
[31]
Valid
0
RW
Valid
1: Entry valid
0: Entry invalid
107
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
5.1.33.4 Multicast IP Entry 3 Register (IER3)
Address 0x15C
Bit
Name
Default
Value
R/W
Function
[27:0]
MulticastIP
0x0000
000
RW
Multicast IP [27:0] (IP [31:28] should be 1110)
[30:28]
Multicastportm
ap
000
RW
Multicast port map [30:28]
Note: LGCR [14] IGMP mode will override this mapping if DI P with IGMP
protocol received.
[31]
Valid
0
RW
Valid
1: Entry valid
0: Entry invalid
5.1.33.5 Multicast IP Entry 4 Register (IER4)
Address 0x160
Bit
Name
Default
Value
R/W
Function
[27:0]
MulticastIP
0x0000
000
RW
Multicast IP [27:0] (IP [31:28] should be 1110)
[30:28]
Multicastportm
ap
000
RW
Multicast port map [30:28]
NOTE: LGCR [14] IGMP mode will override this mapping if DIP
with IGMP
protocol received.
[31] Valid 0 RW Valid
1: Entry valid
0: Entry invalid
5.1.33.6 Multicast IP Entry 5 Register (IER5)
Address 0x164
Bit
Name
Default
Value
R/W
Function
[27:0] MulticastIP 0x0000
000 RW Multicast IP [27 :0] (IP [31:28] should be 1110)
[30:28] Multicastportm
ap 000 RW Multicast port map [30:28]
NOTE: LGCR [14] IGMP mode w ill override this mapping if DIP
with IGMP
protocol received.
[31]
Valid
0
RW
Valid
1: Entry valid
0: Entry invalid
108
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
5.1.33.7 Multicast IP Entry 6 Register (IER6)
Address 0x168
Bit
Name
Default
Value
R/W
Function
[27:0]
MulticastIP
0x0000
000
RW
Multicast IP [27:0] (IP [31:28] should be 1110)
[30:28]
Multicastportm
ap
000
RW
Multicast port map [30:28]
NOTE: L GCR [14] IGMP m ode w ill override this mapping if DIP
with IGMP
protocol received.
[31]
Valid
0
RW
Valid
1: Entry valid
0: Entry invalid
5.1.33.8 Multicast IP Entry 7 Register (IER7)
Address 0x16C
Bit
Name
Default
Value
R/W
Function
[27:0]
MulticastIP
0x0000
000
RW
Multicast IP [27:0] (IP [31:28] should be 1110)
[30:28]
Multicastportm
ap
000
RW
Multicast port map [30:28]
NOTE: LGCR [14] IGMP m ode will override this m apping if DIP
with IGMP
protocol received.
[31] Valid 0 RW Valid
1: Entry valid
0: Entry invalid
5.1.34 Port 2 Slave MDC/MDIO Register 0 (P2SMR0)
Address 0x1A0
Bit
Name
Default
Value
R/W
Function
[4:0]
Slavephyaddr
00001
RW
Port 2 slave MDC/MDIO PHY add r ess
[29:5]
Reserved
0x0000
000
R
Reserved
[30]
Reserved
0
RW
Always set 0 when write P2SMR0 register.
[31]
slave_en
0
RW
Port 0 Slave MDIO Enable bit
109
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
5.1.35 Port 2 Slave MDC/MDIO Register 1 (P2SMR1)
Address 0x1A4
Bit
Name
Default
Value
R/W
Function
[15:0]
Slavedata
[15:0]
0x3100
RW
PHY register address 0x0 data registers
[31:16]
Slavedata
[31:16]
0x7829
RW
PHY register address 0x1 data r egisters
5.1.36 Port 2 Slave MDC/MDIO Register 2 (P2SMR2)
Address 0x1A8
Bit Name
Default
Value R/W
Function
[15:0]
Slavedata
[47:32]
0x
05E1
RW
PHY register address 0x4 data registers
[31:16]
Slavedata
[63:48]
0x
0DE1
RW
PHY register address 0x5 data registers
5.1.37 Port 2 Slave MDC/MDIO Register 3 (P2SMR3)
Address 0x1AC
Bit Name
Default
Value
R/W
Function
[15:0] Slavedata
[79:64] 0x0000 RW P HY register address 0x10 data registers
[31:16]
Slavedata_w
0x0000
WC
Configurable PHY register address 0x11 data registers
110
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
5.1.38 Port 2 Multicast MAC Filters Register (P2MFR0 ~ P2MFR15)
Note: Only the following pre-assi gned 16 multicast packets are able to forward to Port 2 if any of these entry is
enabled. A ll m ulticast packets f orward to port 2 not i n this table w ill be dropped!! If none of th e Enable bit is set
then this table will be disabled!!
5.1.38.1 Port 2 Multicast MAC Filters Register 0 (P2MFR0)
Address 0x1B0
Bit
Name
Default
Value
R/W
Function
[7:0]
DA0 [47:40]
0x00
RW
Multicast DA0 MAC Address [47:40]
[15:8]
DA0 [39:32]
0x00
RW
Multicast DA0 MAC Address [39:32]
[22:16]
DA0 [31:25]
0x00
RW
Multicast DA0 MAC Address [31:25]
[23]
SourcePort0
0
RW
This multicast DA0 MAC packet is from Port 0.
[24]
SourcePort1
0
RW
This multicast DA0 MAC packet is from Port 1.
{SourcePort1, SourcePort0}
01: Limit this DA0 MAC multicast packet must from port 0 o ther wise will
be dropped.
10: Limit this DA0 MAC multicast packet must from port 1 o ther wise will
be dropped.
11: This DA0 MAC multicast packet can from port 0 or port 1.
00: Always drop this DA0 MAC multicast packet
[25]
Enable
0
RW
Entry is valid.
1: Enable Port 2 M ulticast DA0 MAC Filter check on this entry
0: Disable
[31:26]
Reserved
0x00
R
Reserved
5.1.38.2 Port 2 Multicast MAC Filters Register 1 (P2MFR1)
Address 0x1B4
Bit
Name
Default
Value
R/W
Function
[7:0]
DA1 [47:40]
0x00
RW
Multicast DA1 MAC Address [47:40]
[15:8]
DA1 [39:32]
0x00
RW
Multicast DA1 MAC Address [39:32]
[22:16]
DA1 [31:25]
0x00
RW
Multicast DA1 MAC Address [31:25]
[23]
SourcePort0
0
RW
This multicast DA1 MAC packet is from Port 0.
[24] SourcePort1 0 RW This multicast DA1 MAC packet is from Po rt 1.
{SourcePort1, SourcePort0}
01: Limit this DA1 MAC multicast packet must from port 0 o ther wise will
be dropped.
10: Limit this DA1 MAC multicast packet must from port 1 otherwise will
be dropped.
11: This DA1 MAC multicast packet can from port 0 or port 1.
00: Always drop this DA1 MAC multicast packet
[25]
Enable
0
RW
Entry is valid.
1: Enable Port 2 M ulticast DA1 M AC Filter check on this entry
0: Disable
[31:26]
Reserved
0x00
R
Reserved
111
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
5.1.38.3 Port 2 Multicast MAC Filters Register 2 (P2MFR2)
Address 0x1B8
Bit
Name
Default
Value
R/W
Function
[7:0]
DA2 [47:40]
0x00
RW
Multicast DA2 MAC Address [47:40]
[15:8]
DA2 [39:32]
0x00
RW
Multicast DA2 MAC Address [39:32]
[22:16]
DA2 [31:25]
0x00
RW
Multicast DA2 MAC Address [31:25]
[23]
SourcePort0
0
RW
This multicast DA2 MAC packet is from Port 0.
[24]
SourcePort1
0
RW
This multicast DA2 MAC packet is from Port 1.
{SourcePort1, SourcePort0}
01: Limit this DA2 MAC multicast packet must from port 0 o ther wise will
be dropped.
10: Limit this DA2 MAC multicast packet must from port 1 o ther wise will
be dropped.
11: This DA2 MAC multicast packet can from port 0 or port 1.
00: Always drop this DA2 MAC multicast packet
[25] Enable 0 RW E ntry is valid.
1: Enable Port 2 M ulticast DA2 M AC Filter check on this entry
0: Disable
[31:26]
Reserved
0x00
R
Reserved
5.1.38.4 Port 2 Multicast MAC Filters Register 3 (P2MFR3)
Address 0x1BC
Bit
Name
Default
Value
R/W
Function
[7:0]
DA3 [47:40]
0x00
RW
Multicast DA3 MAC Address [47:40]
[15:8]
DA3 [39:32]
0x00
RW
Multicast DA3 MAC Address [39:32]
[22:16]
DA3 [31:25]
0x00
RW
Multicast DA3 MAC Address [31:25]
[23]
SourcePort0
0
RW
This multicast DA3 MAC packet is from Por t 0.
[24] SourcePort1 0 RW This multicast DA3 MAC packet is from Po rt 1.
{SourcePort1, SourcePort0}
01: Limit this DA3 MAC multicast packet must from port 0 o ther wise will
be dropped.
10: Limit this DA3 MAC multicast packet must from port 1 o ther wise will
be dropped.
11: This DA3 MAC multicast packet can from port 0 or port 1.
00: Always drop this DA3 MAC multicast packet
[25]
Enable
0
RW
Entry is valid.
1: Enable Port 2 M ulticast DA3 MAC Filter check on this entry
0: Disable
[31:26]
Reserved
0x00
R
Reserved
112
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
5.1.38.5 Port 2 Multicast MAC Filters Register 4 (P2MFR4)
Address 0x1C0
Bit
Name
Default
Value
R/W
Function
[7:0]
DA4 [47:40]
0x00
RW
Multicast DA4 MAC Address [47:40]
[15:8]
DA4 [39:32]
0x00
RW
Multicast D A4 M AC Address [39:32]
[22:16]
DA4 [31:25]
0x00
RW
Multicast DA4 MAC Address [31:25]
[23]
SourcePort0
0
RW
This multicast DA4 MAC packet is from Port 0.
[24]
SourcePort1
0
RW
This multicast DA4 MAC packet is from Port 1.
{SourcePort1, SourcePort0}
01: Limit this DA4 MAC multicast packet must from port 0 o ther wise will
be dropped.
10: Limit this DA4 MAC multicast packet must from port 1 o ther wise will
be dropped.
11: This DA4 MAC multicast packet can from port 0 or port 1.
00: Always drop this DA4 MAC multicast packet
[25] Enable 0 RW E ntry is valid.
1: Enable Port 2 M ulticast DA4 M AC Filter check on this entry
0: Disable
[31:26]
Reserved
0x00
R
Reserved
5.1.38.6 Port 2 Multicast MAC Filters Register 5 (P2MFR5)
Address 0x1C4
Bit
Name
Default
Value
R/W
Function
[7:0]
DA5 [47:40]
0x00
RW
Multicast DA5 MAC Address [47:40]
[15:8]
DA5 [39:32]
0x00
RW
Multicast DA5 MAC Address [39:32]
[22:16]
DA5 [31:25]
0x00
RW
Multicast DA5 MAC Address [31:25]
[23]
SourcePort0
0
RW
This multicast DA5 MAC packet is from Port 0.
[24] SourcePort1 0 RW This multicast DA5 MAC packet is from Po rt 1.
{SourcePort1, SourcePort0}
01: Limit this DA5 MAC multicast packet must from port 0 o ther wise will
be dropped.
10: Limit this DA5 MAC multicast packet must from port 1 otherwise will
be dropped.
11: This DA5 MAC multicast packet can from port 0 or port 1.
00: Always drop this DA5 MAC multicast packet
[25]
Enable
0
RW
Entry is valid.
1: Enable Port 2 M ulticast DA5 MAC Filter check on this entry
0: Disable
[31:26]
Reserved
0x00
R
Reserved
113
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
5.1.38.7 Port 2 Multicast MAC Filters Register 6 (P2MFR6)
Address 0x1C8
Bit
Name
Default
Value
R/W
Function
[7:0]
DA6 [47:40]
0x00
RW
Multicast DA6 MAC Address [47:40]
[15:8]
DA6 [39:32]
0x00
RW
Multicast DA6 MAC Address [39:32]
[22:16]
DA6 [31:25]
0x00
RW
Multicast DA6 MAC Address [31:25]
[23]
SourcePort0
0
RW
This multicast DA6 MAC packet is from Port 0.
[24]
SourcePort1
0
RW
This multicast DA6 MAC packet is from Port 1.
{SourcePort1, SourcePort0}
01: Limit this DA6 MAC multicast packet must from port 0 o ther wise will
be dropped.
10: Limit this DA6 MAC multicast packet must from port 1 o ther wise will
be dropped.
11: This DA6 MAC multicast packet can from port 0 or port 1.
00: Always drop this DA6 MAC multicast packet
[25] Enable 0 RW E ntry is valid.
1: Enable Port 2 M ulticast DA6 M AC Filter check on this entry
0: Disable
[31:26]
Reserved
0x00
R
Reserved
5.1.38.8 Port 2 Multicast MAC Filters Register 7 (P2MFR7)
Address 0x1CC
Bit
Name
Default
Value
R/W
Function
[7:0]
DA7 [47:40]
0x00
RW
Multicast DA7 MAC Address [47:40]
[15:8]
DA7 [39:32]
0x00
RW
Multicast DA7 MAC Address [39:32]
[22:16]
DA7 [31:25]
0x00
RW
Multicast DA7 MAC Address [31:25]
[23]
SourcePort0
0
RW
This multicast DA7 MAC packet is from Port 0.
[24] SourcePort1 0 RW This multicast DA7 MAC packet is from Po rt 1.
{SourcePort1, SourcePort0}
01: Limit this DA7 MAC multicast packet must from port 0 o ther wise will
be dropped.
10: Limit this DA7 MAC multicast packet must from port 1 o ther wise will
be dropped.
11: This DA7 MAC multicast packet can from port 0 or port 1.
00: Always drop this DA7 MAC multicast packet
[25]
Enable
0
RW
Entry is valid.
1: Enable Port 2 M ulticast DA7 MAC Filter check on this entry
0: Disable
[31:26]
Reserved
0x00
R
Reserved
114
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
5.1.38.9 Port 2 Multicast MAC Filters Register 8 (P2MFR8)
Address 0x1D0
Bit
Name
Default
Value
R/W
Function
[7:0]
DA8 [47:40]
0x00
RW
Multicast DA8 MAC Address [47:40]
[15:8]
DA8 [39:32]
0x00
RW
Multicast DA8 MAC Address [39:32]
[22:16]
DA8 [31:25]
0x00
RW
Multicast DA8 MAC Address [31:25]
[23]
SourcePort0
0
RW
This multicast DA8 MAC packet is from Port 0.
[24]
SourcePort1
0
RW
This multicast DA8 MAC packet is from Port 1.
{SourcePort1, SourcePort0}
01: Limit this DA8 MAC multicast packet must from port 0 otherwise will
be dropped.
10: Limit this DA8 MAC multicast packet must from port 1 o ther wise will
be dropped.
11: This DA8 MAC multicast packet can from port 0 or port 1.
00: Always drop this DA8 MAC multicast packet
[25] Enable 0 RW E ntry is valid.
1: Enable Port 2 M ulticast DA8 M AC Filter check on this entry
0: Disable
[31:26]
Reserved
0x00
R
Reserved
5.1.38.10 Port 2 Multicast MAC Filters Register 9 (P2MFR9)
Address 0x1D4
Bit
Name
Default
Value
R/W
Function
[7:0]
DA9 [47:40]
0x00
RW
Multicast DA9 MAC Address [47:40]
[15:8]
DA9 [39:32]
0x00
RW
Multicast DA9 MAC Address [39:32]
[22:16]
DA9 [31:25]
0x00
RW
Multicast DA9 MAC Address [31:25]
[23]
SourcePort0
0
RW
This multicast DA9 MAC packet is from Port 0.
[24] SourcePort1 0 RW This multicast DA9 MAC packet is from Po rt 1.
{SourcePort1, SourcePort0}
01: Limit this DA9 MAC multicast packet must from port 0 o ther wise will
be dropped.
10: Limit this DA9 MAC multicast packet must from port 1 o ther wise will
be dropped.
11: This DA9 MAC multicast packet can from port 0 or port 1.
00: Always drop this DA9 MAC multicast packet
[25]
Enable
0
RW
Entry is valid.
1: Enable Port 2 M ulticast DA9 MAC Filter check on this entry
0: Disable
[31:26]
Reserved
0x00
R
Reserved
115
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
5.1.38.11 Port 2 Multicast MAC Filters Register 10 (P2MFR10)
Address 0x1D8
Bit
Name
Default
Value
R/W
Function
[7:0]
DA10 [47:40]
0x00
RW
Multicast DA10 MAC Address [47:40]
[15:8]
DA10 [39:32]
0x00
RW
Multicast DA10 MAC Address [39:32]
[22:16]
DA10 [31:25]
0x00
RW
Multicast DA10 MAC Address [31:25]
[23]
SourcePort0
0
RW
This multicast DA10 MAC packet is from Port 0.
[24]
SourcePort1
0
RW
This multicast DA10 MAC packet is from Port 1.
{SourcePort1, SourcePort0}
01: Limit this DA 10 MAC multicast packet must
from port 0 otherwise will
be dropped.
10: Limit this DA 10 MAC multicast packet m us t from port 1 otherwise w ill
be dropped.
11: This DA10 MAC multicast packet can from port 0 or port 1.
00: Always drop this DA10 M AC multicast packet
[25] Enable 0 RW E ntry is valid.
1: Enable Port 2 M ulticast DA10 MAC Filter check on this entry
0: Disable
[31:26]
Reserved
0x00
R
Reserved
5.1.38.12 Port 2 Multicast MAC Filters Register 11 (P2MFR11)
Address 0x1DC
Bit
Name
Default
Value
R/W
Function
[7:0]
DA11 [47:40]
0x00
RW
Multicast DA11 MAC Address [47:40]
[15:8]
DA11 [39:32]
0x00
RW
Multicast DA11 MAC Address [39:32]
[22:16]
DA11 [31:25]
0x00
RW
Multicast DA11 MAC Address [31:25]
[23]
SourcePort0
0
RW
This multicast DA11 MAC packet is from Port 0.
[24] SourcePort1 0 RW This multicast DA11 MAC packet is from Port 1.
{SourcePort1, SourcePort0}
01: Limit this DA 11 MAC multicast packet m us t from port 0 otherwise w ill
be dropped.
10: Limit this DA 11 MAC multicast packet m us t from port 1 otherwise w ill
be dropped.
11: This DA11 MAC multicast packet can from port 0 or port 1.
00: Always drop this DA11 M AC multicast packet
[25]
Enable
0
RW
Entry is valid.
1: Enable Port 2 M ulticast DA11 MAC Filter check on this entry
0: Disable
[31:26]
Reserved
0x00
R
Reserved
116
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
5.1.38.13 Port 2 Multicast MAC Filters Register 12 (P2MFR12)
Address 0x1E0
Bit
Name
Default
Value
R/W
Function
[7:0]
DA12 [47:40]
0x00
RW
Multicast DA12 MAC Address [47:40]
[15:8]
DA12 [39:32]
0x00
RW
Multicast DA12 MAC Address [39:32]
[22:16]
DA12 [31:25]
0x00
RW
Multicast DA12 MAC Address [31:25]
[23]
SourcePort0
0
RW
This multicast DA12 MAC packet is from Port 0.
[24]
SourcePort1
0
RW
This multicast DA12 MAC packet is from Port 1.
{SourcePort1, SourcePort0}
01: Limit this DA 12 MAC multicast
packet must from port 0 otherwise w ill
be dropped.
10: Limit this DA 12 MAC multicast packet m us t from port 1 otherwise w ill
be dropped.
11: This DA12 MAC multicast packet can from port 0 or port 1.
00: Always drop this DA12 M AC multicast packet
[25] Enable 0 RW E ntry is valid.
1: Enable Port 2 M ulticast DA12 MAC Filter check on this entry
0: Disable
[31:26]
Reserved
0x00
R
Reserved
5.1.38.14 Port 2 Multicast MAC Filters Register 13 (P2MFR13)
Address 0x1E4
Bit
Name
Default
Value
R/W
Function
[7:0]
DA13 [47:40]
0x00
RW
Multicast DA13 MAC Address [47:40]
[15:8]
DA13 [39:32]
0x00
RW
Multicast DA13 MAC Address [39:32]
[22:16]
DA13 [31:25]
0x00
RW
Multicast DA13 MAC Address [31:25]
[23]
SourcePort0
0
RW
This multicast DA13 MAC packet is from Port 0.
[24] SourcePort1 0 RW This multicast DA13 MAC packet is from Port 1.
{SourcePort1, SourcePort0}
01: Limit this DA 13 MAC multicast packet m us t from port 0 otherwise w ill
be dropped.
10: Limit this DA 13 MAC multicast packet m ust f rom port 1 otherwise
will
be dropped.
11: This DA13 MAC multicast packet can from port 0 or port 1.
00: Always drop this DA13 M AC multicast packet
[25]
Enable
0
RW
Entry is valid.
1: Enable Port 2 M ulticast DA13 MAC Filter check on this entry
0: Disable
[31:26]
Reserved
0x00
R
Reserved
117
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
5.1.38.15 Port 2 Multicast MAC Filters Register 14 (P2MFR14)
Address 0x1E8
Bit
Name
Default
Value
R/W
Function
[7:0]
DA14 [47:40]
0x00
RW
Multicast DA14 MAC Address [47:40]
[15:8]
DA14 [39:32]
0x00
RW
Multicast DA14 MAC Address [39:32]
[22:16]
DA14 [31:25]
0x00
RW
Multicast DA14 MAC Address [31:25]
[23]
SourcePort0
0
RW
This multicast DA14 MAC packet is from Port 0.
[24]
SourcePort1
0
RW
This multicast DA14 MAC packet is from Port 1.
{SourcePort1, SourcePort0}
01: Limit this DA 14 MAC
multicast packet m us t from port 0 otherwise w ill
be dropped.
10: Limit this DA 14 MAC multicast packet m us t from port 1 otherwise w ill
be dropped.
11: This DA14 MAC multicast packet can from port 0 or port 1.
00: Always drop this DA14 M AC multicast packet
[25] Enable 0 RW E ntry is valid.
1: Enable Port 2 M ulticast DA14 MAC Filter check on this entry
0: Disable
[31:26]
Reserved
0x00
R
Reserved
5.1.38.16 Port 2 Multicast MAC Filters Register 15 (P2MFR15)
Address 0x1EC
Bit
Name
Default
Value
R/W
Function
[7:0]
DA15 [47:40]
0x00
RW
Multicast DA15 MAC Address [47:40]
[15:8]
DA15 [39:32]
0x00
RW
Multicast DA15 MAC Address [39:32]
[22:16]
DA15 [31:25]
0x00
RW
Multicast DA15 MAC Address [31:25]
[23]
SourcePort0
0
RW
This multicast DA15 MAC packet is from Port 0.
[24] SourcePort1 0 RW This multicast DA15 MAC packet is from Port 1.
{SourcePort1, SourcePort0}
01: Limit this DA 15 MAC multicast packet m us t from port 0 otherwise w ill
be dropped.
10: Limit this DA 15 MAC multicast packet must from port 1
otherwise w ill
be dropped.
11: This DA15 MAC multicast packet can from port 0 or port 1.
00: Always drop this DA15 M AC multicast packet
[25]
Enable
0
RW
Entry is valid.
1: Enable Port 2 M ulticast DA15 MAC Filter check on this entry
0: Disable
[31:26]
Reserved
0x00
R
Reserved
118
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
5.1.39 Interface Configuration Register (ICR)
Address 0x1F0
Bit
Name
Default
Value
R/W
Function
[1:0]
Reserved
00
RW
Always assign zero
[2]
ClkGen_EN
0
RW
Enable port 2 RMII to MII clock generator, active high
1: Enable i f R MII interface is also turn on
0: Disable
[3]
Reserved
0
R
Reserved
[5:4]
Reserved
00
RW
Always assign zero
[6] RMII_EN 0 RW Enable Port 2 RMII Interface Enable, act ive high
1: Enable RMII IO MUX selection logic
0: Disable
[7]
Reserved
0
R
Reserved
[9:8]
Reserved
00
RW
Always assign zero
[10]
RevRMII_Opti
on
0
RW
Enable Port 2 RevRMII ending option, active high.
If the ending option is set to one then the RMII interface logic will check and
make sure at the end of each frame append a pulse (high and low) on vali d
signal to indicate an EOF symbol.
1: Append a EOF pattern at the end of transaction
0: Normal (Default)
[11]
Reserved
0
R
Reserved
[13:12]
Reserved
00
RW
Always assign zero
[14]
CLK50_EN
0
RW
Output 50 MHz clock output for Reverse RMII for external chip reference
clock. Output 50MHz clock on pin# 54 P2_REFCLKO.
1: 50MHz clock output enable
0: Disable
[15]
Reserved
0
R
Reserved
[17:16]
Reserved
00
RW
Always assign zero
[18]
MII_EN
0
RW
Enable IO Pad select MUX for Port 2 MII interface signals, active high
1: Enable MI I IO MUX selection logic
0: Disable
[19]
MII_Low
0
RW
This bit should always assign to one !
[21:20
Reserved
00
RW
Always assign zero
[23:22]
Reserved
00
R
Reserved
[25:24]
Reserved
00
RW
Always assign zero
[26]
RevMII_EN
0
RW
Enable IO Pad select output MUX for TX clock and RX clock as outp ut
signal, active high.
1: Enable Port 2 RevMII interface logic
0: Disable
[27]
Reserved
0
R
Reserved
[29:28]
Reserved
00
RW
Always assign zero
[30]
MDC_EN
0
RW
Enable IO Pad select MUX for MDIO Interface, active high
1: Enable Port 2 MDIO interface
0: Disable
[31]
Reserved
0
R
Reserved
119
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
5.1.40 Sleep Mode Exit Register (SMER)
Address 0x1F4
Bit
Name
Default
Value
R/W
Function
[31:0]
Sleep_mode_e
xit
0x0000
0000
WC
Any write comm and to this address w ill cause the chip exit the sleep mode and
back to normal mode operation.
5.1.41 General Purpose Timer Configuration Register (GTCR)
The General Purpose Timer can be used for software to count a precise time
Address 0x1FC
Bit
Name
Default
Value
R/W
Function
[29:0]
Ti mer [29:0]
0x0000
0000
RW
The General Purpose Timer counter register (10ns pe r unit).
[31:30]
Timer_mode
[1:0]
00
RW
Internal Timer mode select
00: Disable General Timer function
01: Active the timer-up interrupts status (ISMR [12]) when the timer is done,
then the timer will auto re-start the increment process.
10: Active the timer-up interrupts st atus (ISMR [12]) when the timer is done,
then the timer will re-start only after the software clear the timer-
up
interrupt status.
11: Reserved
5.1.42 Port 0 MAC Configuration Register (P0MCR)
Address 0x200
Bit
Name
Default
Value
R/W
Function
[0] MAC_Enable 0 RW Enable Por t 0 MAC function
When Port 0 Auto-
Polling function is disabled (ACR [24] = 0), CPU is able to
read or write this register and enable or disable M AC function.
When Port 0 Auto-
Polling function is enabled (ACR [24] =1), The
Auto-
Polling logic take control of this register and CPU can only read this bit
to know if Port 0 MAC is being enabled or not.
1: Enable Port 0 MAC function
0: Disable Port 0 MAC function
[2:1]
Reserved
00
R
Reserved
[3]
Speed100/10
0
RW
Set Port 0 MAC Speed to 100MBps or 10MBps.
When Port 0 Auto-
Polling function is disabled (ACR [24] = 0), CPU is able to
read or write this register and set MAC working speed.
When Port 0 Auto-
Polling function is enabled (ACR [24] =1), The
Auto-
Polling logic take control of this register and CPU can only read this bit
to know Port 0 MAC’s working speed.
1: Set Port 0 MAC speed to 100MBps
0: Set Port 0 MAC speed to 10MBps
[4]
Full_Duplex
0
RW
Set Port 0 Full or Half Duplex mode
When Port 0 Auto-
Polling function is disabled (ACR [24] = 0), CPU is able to
read or write this register and set Port 0 MAC duplex mode.
When Port 0 Auto-Polling function i
s enabled (ACR [24] =1), The
120
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
Auto-Polling logic take control of this register and CPU can only read this bit
to know Port 0 MAC’s duplex mode.
1: Set Port 0 MAC working at Full Duplex mode
0: Set Port 0 MAC working at Half Duplex mode
[6:5]
Reserved
00
R
Reserved
[7] FlowCtrl_ON 0 RW Flow Control Enable when set to one
When Port 0 Auto-
Polling function is disabled (ACR [24] = 0), CPU is able to
read or write this register and set Port 0 M AC flow control mode.
When Port 0 Auto-Polling function is enabled
(ACR [24] =1), The
Auto-
Polling logic take control of this register and CPU can only read this bit
to know Port 0 MAC’s flow control mode.
1: Enable Port 0 M AC Flow Control function
0: Disable Port 0 M AC Flow Control function
[8]
CRC_Check
1
RW
Enable Port 0 MAC CRC check function when set to one
1: Enable Port MAC 0 CRC check function
0: Disable Port 0 MAC CRC check function
[9]
Reserved
0
RW
Reserved
[10]
AcceptAll
0
RW
1: Accept all packet even illegal (oversize, undersize, crc error..).
0: Only accept legal packet.
NOTE: The undersize p a c ket will add pa dding within the RX MAC.
[11]
1XsecurityON
0
RW
Enable P ort 0 802.1X function when set to one
1: Enable Port 0 802.1X l function
Note: LGCR [16] 1X_En also need to set to 1
0: Disable Port 0 802.1X function
[12] RXStop 0 RW Drop the RX MAC incoming packet s when this bit is set to one
1: Drop all the receiving packets
0: Disable RXStop function.
[13]
TXStop
0
RW
Stop TX from Transmit the packets when this bit is set to one.
1: Stop tra nsmit packets
0: Disbale TXStop function
[14]
Reserved
0
R
Reserved
[15]
Uplink_Port
0
RW
Valid only when 802.1QinQ double tagging function (LGCR [15]) is enabled.
1: Uplink_Port
0: Access_Port.
[16]
EnRXRate
0
RW
Port 0 Ingress Rate Limit Function
1: Enable Port 0 RX Rate limit function
0: Disable Port 0 RX Rate limit function
[17]
EnTXRate
0
RW
Port 0 Egress Rate Limit Function
1: Enable Port 0 TX Rate limit function
0: Disable Port 0 TX Rate limit function
[18] DAMatch_Ena
ble 0 RW If this bit is set to one, any receiving packet wh o’s DA MAC is not match with
the pre-defined Register address 0x230
, 0x234 MAC address, the packet will
be dropped except Multicast and Broadcast packets.
1: Port 0 Only pass multicast, broadcast packet and unicast with DA match
Port 0’s DA MAC setting in register s P0D AR0 and P0DAR1.
0: Disable DAMatch_Enable function
[19]
Reserved
0
RW
Reserved
[31:20]
Reserved
0x000
R
Reserved
121
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
5.1.43 Port 0 802.1p QoS Mapping Table Register (P0QMTR)
Address 0x204
Bit
Name
Default
Value
R/W
Function
[1:0]
RX_QoS0
00
RW
802.1p QoS Mapping Table: (mapping f rom 8 qu eue to on e of internal four
queues)
Internal Qo S value when RX packet’s QoS = 0
[3:2]
RX_QoS1
00
RW
Internal Qo S value when RX packet’s QoS = 1
[5:4]
RX_QoS2
01
RW
Internal QoS val ue when RX packet’s QoS = 2
[7:6]
RX_QoS3
01
RW
Internal Qo S value when RX packet’s QoS = 3
[9:8]
RX_QoS4
10
RW
Internal Qo S value when RX packet’s QoS = 4
[11:10]
RX_QoS5
10
RW
Internal Qo S value when RX packet’s QoS = 5
[13:12]
RX_QoS6
11
RW
Internal QoS val ue when RX packet’s QoS = 6
[15:14]
RX_QoS7
11
RW
Internal Qo S value when RX packet’s QoS = 7
[18:16]
Reserved
000
RW
Reserved
[19]
Reserved
0
R
Reserved
[26:20]
Reserved
0x00
RW
Reserved
[27]
Reserved
0
R
Reserved
[31:28]
Reserved
0000
RW
Reserved
5.1.44 Port 0 802.1Q Configuration for UnTag Frame Register (P0QCR)
Address 0x208
Bit
Name
Default
Value
R/W
Function
[11:0]
PVID
0x001
RW
VLAN ID value (1 ~ 4095, default 1)
[12]
CF
0
RW
CF Flag
[15:13]
QoS
000
RW
QoS value
[31:16]
Reserved
0x0000
R
Reserved
* This Tag information will be inserted when untag frame is received.
5.1.45 Port 0 RX per Queue Rate Limit Control Register 0 (P0RQR0)
Address 0x20C
Bit
Name
Default
Value
R/W
Function
[11:0]
Rx_q0_rate
0xFFF
RW
Port 0 RX queue 0 rate limit (4K bytes per unit )
The default value 0xFFF means disable RX queue 0 rate limit.
[15:12]
Reserved
0000
R
Reserved
[27:16]
Rx_q1_rate
0xFFF
RW
Port 0 RX queue 1 rate limit (4K bytes pe r unit)
The default value 0xFFF means disable RX queue 1 rate limit.
[31:28]
Reserved
0000
R
Reserved
122
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
5.1.46 Port 0 RX per Queue Rate Limit Control Register 1 (P0RQR1)
Address 0x210
Bit
Name
Default
Value
R/W
Function
[11:0]
Rx_q2_rate
0xFFF
RW
Port 0 RX queue 2 rate limit (4K bytes per unit )
The default value 0xFFF means disable RX queue 2 rate limit.
[15:12]
Reserved
0000
R
Reserved
[27:16]
Rx_q3_rate
0xFFF
RW
Port 0 RX queue 3 rate limit (4K bytes pe r unit)
The default value 0xFFF means disable RX queue 3 rate limit.
[31:28]
Reserved
0000
R
Reserved
5.1.47 Port 0 TX per Queue Rate Limit Control Register 0 (P0TQR0)
Address 0x214
Bit
Name
Default
Value
R/W
Function
[11:0]
Tx_q0_rate
0xFFF
RW
Port 0 TX q ueue 0 r a te limit (4K bytes per uni t)
The default value 0xFFF means disable TX queue 0 rate limit.
[15:12]
Reserved
0000
R
Reserved
[27:16]
Tx_q1_rate
0xFFF
RW
Port 0 TX queue 1 rate limit (4K bytes per unit)
The default value 0xFFF means disable TX queue 1 rate limit.
[31:28]
Reserved
0000
R
Reserved
5.1.48 Port 0 TX per Queue Rate Limit Control Register 1 (P0TQR1)
Address 0x218
Bit Name
Default
Value
R/W
Function
[11:0] Tx_q2_rate 0xFFF RW Port 0 TX que ue 2 rate limit (4K bytes per uni t)
The default value 0xFFF means disable TX queue 2 rate limit.
[15:12]
Reserved
0000
R
Reserved
[27:16] Tx_q3_rate 0xFFF RW Port 0 TX queue 3 rate limit (4K bytes p er unit)
The default value 0xFFF means disable TX queue 3 rate limit.
[31:28]
Reserved
0000
R
Reserved
123
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
5.1.49 Port 0 Rate Limit Control Register (P0RLR)
Address 0x21C
Bit
Name
Default
Value
R/W
Function
[11:0]
ingress_rate
0xFFF
RW
Port 0 RX rate limit (4K bytes per unit)
For example, if ingress_rate=16 means port 0 can receive 64K byte within
P0RLTR Cycle_time window (one second).
0xFFF means disable RX per po r t rate limit.
[15:12]
Reserved
0000
R
Reserved
[27:16]
egress_rate
0xFFF
RW
Port 0 T X per po rt rate limit (4K bytes per unit)
0xFFF means disable TX pe r port ra te limit.
[31:28]
Reserved
0000
R
Reserved
5.1.50 Port 0 Rate Limit Timer Register (P0RLTR)
Address 0x220
Bit Name
Default
Value R/W
Function
[26:0]
Cycle_time
0x5F5E
100
RW
Per por t timer for ra te limit calculation. (Default 1 sec.)
1 Second = 10 ^ 8 ns = 0x5F5E100 x 10ns
(100MHz clock cycle time)
[31:27]
Reserved
00000
R
Reserved
5.1.51 Port 0 Flow Control High/Low Watermark Register (P0FCR)
Address 0x224
Bit Name
Default
Value
R/W
Function
[7:0] FCHW 0x28 RW Flow Control High-water mark [7:0]: RX accumulate page count high water
level, once internal R X receiving page counter higher than t his thre s hold and
Flow control is enabled, then TX MAC will send Pause ON Frame out to
informal remote PHY stop sending packets.
[15:8]
FCLW
0x14
RW
Flow Control Low-w ater mark [7:0]: When Flow control is enabled and pause
is ON, RX receiv ing page counter if lower than this low w ater m ark value then
TX MAC will send pause OFF frame to inform remote PHY back to normal
state.
[31:16]
Reserved
0x0000
R
Reserved
124
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
5.1.52 Port 0 Queue Weighting Configuration Register (P0QWR)
Address 0x228
Bit
Name
Default
Value
R/W
Function
[3:0]
Q0_Weight
1111
RW
Q0 weighting control fo r B MU scheduler module usage.
The default value is 1111 means disable weighting control.
Otherwise buffer management unit will schedule TX output packet based on
Q0/Q1/Q2 /Q 3 weighting distribution.
[7:4]
Q1_Weight
1111
RW
Q1 weighting control fo r B MU scheduler module usage
[11:8]
Q2_Weight
1111
RW
Q2 weighting control fo r B MU scheduler module usage
[15:12]
Q3_Weight
1111
RW
Q3 weighting control fo r B MU scheduler module usage
[31:16]
Reserved
0x0000
R
Reserved
5.1.53 Port 0 DA MAC Address Register (P0DAR0, P0ADR1)
Address 0x230 (P0ADR0)
Bit
Name
Default
Value
R/W
Function
[7:0]
DAMAC0
[47:40]
0x00
RW
Default DA MAC0 address for Port 0 only valid when DAMatc hEn is set to
one.(P0MCR [18])
DA MAC0 address [47:40]
[15:8]
DAMAC0
[39:32]
0x00
RW
DA MAC0 address [39:32]
[23:16]
DAMAC0
[31:24]
0x00
RW
DA MAC0 address [31:24]
[31:24] DAMAC0
[23:16]
0x00 RW DA MAC0 address [23:16]
Address 0x234 (P0ADR1)
Bit Name
Default
Value R/W
Function
[7:0]
DAMAC0
[15:8]
0x00
RW
Default DA MAC0 address for Port 0 only valid when DAMatc hEn is set to
one. (P0MCR [18])
DA MAC0 address [15:8]
[15:8]
DAMAC0
[7:0]
0x00
RW
DA MAC0 address [7:0]
[31:16]
Reserved
0x0000
R
Reserved
125
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
5.1.54 Port 1 MAC Configuration Register (P1MCR)
Address 0x240
Bit
Name
Default
Value
R/W
Function
[0]
MAC_Enable
0
RW
Enable Port 1 MAC function
When Port 1 Auto-
Polling function is disabled (ACR [25] = 0), CPU is able to
read or write this register and enable or disable MAC function.
When Port 1 Auto-Polling function is enabled (ACR [2 5] = 1), The
Auto-Pollin
g logic tak e control of this register and CPU can only read this bit
to know if Port 1 MAC is being enabled or not.
1: Enable Port 1 MAC function
0: Disable Port 1 MAC function
[2:1]
Reserved
00
R
Reserved
[3]
Speed100/10
0
RW
Set Port 1 MAC Speed to 100MBps or 10MBps.
When Port 1 Auto-
Polling function is disabled (ACR [25] = 0), CPU is able to
read or write this register and set MAC working speed.
When Port 1 Auto-Polling function is enabled (ACR [2 5] = 1), The
Auto-Polling logic take control of this r
egister and CPU can only read this bit
to know Port 1 MAC’s working speed.
1: Set Port 1 MAC speed to 100MBps
0: Set Port 1 MAC speed to 10MBps
[4] Full_Duplex 0 RW Set Port 1 Full or H a lf Duplex mode
When Port 1 Auto-Polling function is disabled (ACR [2
5] = 0), CPU i s able t o
read or write this register and set Port 1 MAC duplex mode.
When Port 1 Auto-Polling function is enabled (ACR [2 5] = 1), The
Auto-
Polling logic take control of this register and CPU can only read this bit
to know Port 0 MAC’s duplex mode.
1: Set Port 1 MAC working at Full Duplex mode
0: Set Port 1 M AC working at Half Duplex mode
[6:5]
Reserved
00
R
Reserved
[7]
FlowCtrl_ON
0
RW
Flow Control Enable when set to one
When Port 1 Auto-Polling function is disabled (ACR [25] = 0), CPU is
able to
read or write this register and set Port 0 M AC flow control mode.
When Port 1 Auto-Polling function is enabled (ACR [2 5] = 1), The
Auto-
Polling logic take control of this register and CPU can only read this bit
to know Port 1 MAC’s flow control mode.
1: Enable Port 1 M AC Flow Control function
0: Disable Port 1 M AC Flow Control function
[8]
CRC_Check
1
RW
Enable Port 1 MAC CRC check function when set t o one
1: Enable Port 1 MAC CRC check function
0: Disable Port 1 MAC CRC check function
[9]
Reserved
0
RW
Reserved
[10]
AcceptAll
0
RW
1: Accept all packet even illegal (oversize, undersize, crc error..).
0: Only accept legal packet.
NOTE: The undersize p a c ket will add pa dding within the RX MAC.
[11] 1XsecurityON 0 RW Enable Port 1 802.1X function when set to o ne
1: Enable Port 1 802.1X l function
Note: LGCR [16] 1X_En also need to set to 1
0: Disable Port 1 802.1X function
[12]
RXStop
0
RW
Drop the RX MAC incoming packets when this bit is set to o ne
1: Drop all the receiving packets
0: Disable RXSt op func tion.
[13]
TXStop
0
RW
Stop TX from Transmit the packets when this bit is set to one.
1: Stop tra nsmit packets
0: Disbale TXStop function
126
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
[14]
Reserved
0
R
Reserved
[15]
Uplink_Port
0
RW
Valid only when 802.1QinQ double tagging function (LGCR [15]) is enabled.
1: Uplink_Port
0: Access_Port.
[16]
EnRXRate
0
RW
Port 1 Ingress Rate Limit Function
1: Enable Port 1 RX Rate limit function
0: Disable Port 1 RX Rate limit function
[17] EnTXRate 0 RW Port 1 E gre ss Rate Limit Function
1: Enable Port 1 TX Rate limit function
0: Disable Port 1 TX Rate limit function
[18]
DAMatch_Ena
ble
0
RW
If this bit is set to one, any receiving packet who’s DA MAC is not match with
the pre-defined Register address 0x230
, 0x234 MAC address, the packet will
be dropped except Multicast and Broadcast packets.
1: Port 1 Only pass multicast, broadcast packet and unicast with DA match
Port 1’s DA MAC setti ng in register s P1D AR0 and P1DAR1.
0: Disable DAMatch_Enable function
[19]
Reserved
0
RW
Reserved
[31:20]
Reserved
0x000
R
Reserved
5.1.55 Port 1 802.1p QoS Mapping Table Register (P1QMTR)
Address 0x244
Bit
Name
Default
Value
R/W
Function
[1:0]
RX_QoS0
00
RW
802.1p QoS Mapping Table:
This table converts eight QoS value to one of the i nterna l four que ues. The
AX88613 only support 0,1, 2 and 3.
Internal Qo S value when RX packet’s QoS = 0
[3:2]
RX_QoS1
00
RW
Internal Qo S value when RX packet’s QoS = 1
[5:4]
RX_QoS2
01
RW
Internal Qo S value when RX packet’s QoS = 2
[7:6]
RX_QoS3
01
RW
Internal Qo S value when RX packet’s QoS = 3
[9:8]
RX_QoS4
10
RW
Internal Qo S value when RX packet’s QoS = 4
[11:10]
RX_QoS5
10
RW
Internal Qo S value when RX packet’s QoS = 5
[13:12]
RX_QoS6
11
RW
Internal Qo S value when RX packet’s QoS = 6
[15:14]
RX_QoS7
11
RW
Internal QoS val ue when RX packet’s QoS = 7
[18:16]
Reserved
000
RW
Reserved
[19]
Reserved
0
R
Reserved
[26:20]
Reserved
0x00
RW
Reserved
[27]
Reserved
0
R
Reserved
[31:28]
Reserved
0x0
RW
Reserved
127
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
5.1.56 Port 1 802.1Q Configuration for UnTag Frame Register (P1QCR)
Address 0x248
Bit
Name
Default
Value
R/W
Function
[11:0]
PVID
0x001
RW
VLAN ID value (1 ~ 4095, default 1)
[12]
CF
0
RW
CF Flag
[15:13]
QoS
000
RW
QoS value
[31:16]
Reserved
0x0000
R
Reserved
* This Tag information will be inserted when untag frame is received.
5.1.57 Port 1 RX per Queue Rate Limit Control Register 0 (P1RQR0)
Address 0x24C
Bit
Name
Default
Value
R/W
Function
[11:0]
Rx_q0_rate
0xFFF
RW
Port 1 RX queue 0 rate limit (4K bytes per unit )
The default value 0xFFF means disable RX queue 0 rate limit.
[15:12]
Reserved
0000
R
Reserved
[27:16]
Rx_q1_rate
0xFFF
RW
Port 1 RX queue 1 rate limit (4K bytes pe r unit)
The default value 0xFFF means disable RX queue 1 rate limit.
[31:28]
Reserved
0000
R
Reserved
5.1.58 Port 1 RX per Queue Rate Limit Control Register 1 (P1RQR1)
Address 0x250
Bit
Name
Default
Value
R/W
Function
[11:0] Rx_q2_rate 0xFFF RW P ort 1 RX q ueue 2 rate limit (4K bytes per unit)
The default value 0xFFF means disable RX queue 2 rate limit.
[15:12]
Reserved
0000
R
Reserved
[27:16]
Rx_q3_rate
0xFFF
RW
Port 1 RX queue 3 rate limit (4K bytes pe r unit)
The default value 0xFFF means disable RX queue 3 rate limit.
[31:28]
Reserved
0000
R
Reserved
5.1.59 Port 1 TX per Queue Rate Limit Control Register 0 (P1TQR0)
Address 0x254
Bit Name
Default
Value
R/W
Function
[11:0]
Tx_q0_rate
0xFFF
RW
Port 1 TX q ueue 0 r a te limit (4K bytes per uni t)
The default value 0xFFF means disable TX queue 0 rate limit.
[15:12]
Reserved
0000
R
Reserved
[27:16] Tx_q1_rate 0xFFF RW Port 1 TX queue 1 rate limit (4K bytes p er unit )
The default value 0xFFF means disable TX queue 1 rate limit.
[31:28]
Reserved
0000
R
Reserved
128
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
5.1.60 Port 1 TX per Queue Rate Limit Control Register 1 (P1TQR1)
Address 0x258
Bit
Name
Default
Value
R/W
Function
[11:0]
Tx_q2_rate
0xFFF
RW
Port 1 TX q ueue 2 ra te limit (4K bytes per unit)
The default value 0xFFF means disable TX queue 2 rate limit.
[15:12]
Reserved
0000
R
Reserved
[27:16]
Tx_q3_rate
0xFFF
RW
Port 1 TX queue 3 rate limit (4K bytes per unit)
The default value 0xFFF means disable TX queue 3 rate limit.
[31:28]
Reserved
0000
R
Reserved
5.1.61 Port 1 Rate Limit Control Register (P1RLR)
Address 0x25C
Bit
Name
Default
Value
R/W
Function
[11:0]
ingress_rate
0xFFF
RW
Port 1 RX rate limit (4K bytes per unit)
For example, if ingress_rate=16 means port 0 can receive 64K byte within
P0RLTR Cycle_time window (one second).
0xFFF means disable RX per po r t rate limit.
[15:12]
Reserved
0000
R
Reserved
[27:16] egress_rate 0xFFF RW Port 1 TX per port rate limit (4K bytes per unit)
0xFFF means disable TX per port rate limit.
[31:28]
Reserved
0000
R
Reserved
5.1.62 Port 1 Rate Limit Timer Register (P1RLTR)
Address 0x260
Bit
Name
Default
Value
R/W
Function
[26:0]
Cycle_time
0x5F5E
100
RW
Per p ort timer for rate limit calculation. (Default 1 sec.)
2 Second = 10 ^ 8 ns = 0x5F5E100 x 10ns
(100MHz clock cycle time)
[31:27]
Reserved
00000
R
Reserved
5.1.63 Port 1 Flow Control High/Low Watermark Register (P1FCR)
Address 0x264
Bit
Name
Default
Value
R/W
Function
[7:0]
FCHW
0x28
RW
Flow Control High-water mark [7:0]: RX accumulate page count high water
level, once internal R X receiving page counter higher than t his thre s hold and
Flow control is enabled, then TX MAC will send Pause ON Frame out to
informal remote PHY stop sending packets.
[15:8] FCLW 0x14 RW Flow Control Low-w ater mark [7:0]:
When Flow control is en abled and pause
is ON, RX receiv ing page counter if lower than this low w ater m ark value then
TX MAC will send pause OFF frame to inform remote PHY back to normal
state.
[31:16]
Reserved
0x0000
R
Reserved
129
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
5.1.64 Port 1 Queue Weighting Configuration Register (P1QWR)
Address 0x268
Bit
Name
Default
Value
R/W
Function
[3:0]
Q0_Weight
1111
RW
Q0 weighting control fo r B MU scheduler module usage.
The default value is 1111 means disable weighting control.
Otherwise buffer management uni t will schedule TX output packet based on
Q0/Q1/Q2 /Q 3 weighting distribution.
[7:4]
Q1_Weight
1111
RW
Q1 weighting control fo r B MU scheduler module usage
[11:8]
Q2_Weight
1111
RW
Q2 weighting control fo r B MU scheduler module usage
[15:12]
Q3_Weight
1111
RW
Q3 weighting control fo r B MU scheduler module usage
For example if Q0_Weight=1, Q1_Weight=2, Q2_Weight=4 and
Q3_We ight=8 then the output p a c kets will have this ratio 8:4:2:1 if all the
packets are the same size. The weighting here will based on the page count.
There are 128 bytes in a page.
[31:16]
Reserved
0x0000
R
Reserved
5.1.65 Port 1 DA MAC Address Register (P1DAR0, P1ADR1)
Address 0x270 (P1ADR0)
Bit
Name
Default
Value
R/W
Function
[7:0]
DAMAC1
[47:40]
0x00
RW
Default DA MAC1 address for Port 1 only valid when DAMatchE n is set to
one.(P1MCR [18])
DA MAC1 address [47:40]
[15:8] DAMAC1
[39:32] 0x00 RW DA MAC1 address [39:32]
[23:16] DAMAC1
[31:24] 0x00 RW DA MAC1 address [31:24]
[31:24] DAMAC1
[23:16] 0x00 RW DA MAC1 address [23:16]
Address 0x274 (P1ADR1)
Bit
Name
Default
Value
R/W
Function
[7:0]
DAMAC1
[15:8]
0x00
RW
Default DA MAC1 address for Port 1 only valid when DAMatc hEn is set to
one. (P1MCR [18])
DA MAC1 address [15:8]
[15:8]
DAMAC1
[7:0]
0x00
RW
DA MAC1 address [7 : 0]
[31:16]
Reserved
0x0000
R
Reserved
130
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
5.1.66 Port 2 MAC Configuration Register (P2MCR)
Address 0x280
Bit
Name
Default
Value
R/W
Function
[0]
MAC_Enable
0
RW
Enable Port 2 MAC function
When Port 2 Auto-Polling function is disabled (ACR [26] =
0), CPU is able to
read or write this register and enable or disable MAC function.
When Port 2 Auto-Polling function is enabled (ACR [2 6] = 1), The
Auto-
Polling logic take control of this register and CPU can only read this bit
to know if Port 2 MAC is being enable d or not.
1: Enable Port 2 MAC function
0: Disable Port 2 MAC function
[2:1]
Reserved
00
R
Reserved
[3]
Speed100/10
0
RW
Set Port 2 MAC Speed to 100MBps or 10MBps.
When Port 2 Auto-
Polling function is disabled (ACR [26] = 0), CPU is able to
read or write this register and set MAC working speed.
When Port 2 Auto-Polling function is enabled (ACR [2 6] = 1), The
Auto-
Polling logic take control of this register and CPU can only read this bit
to know Port 2 MAC’s working speed.
1: Set Port 2 MAC speed to 100MBps
0: Set Port 2 MAC speed to 10MBps
[4] Full_Duplex 0 RW Set Port 2 Full or H a lf Duplex mode
When Port 2 Auto-
Polling function is disabled (ACR [26] = 0), CPU is able to
read or write this register and set Port 1 MAC duplex mode.
When Port 2 Auto-Pol ling function is enabled ( ACR [26] =1), The
Auto-
Polling logic take control of this register and CPU can only read this bit
to know Port 2 MAC’s duplex mode.
1: Set Port 2 MAC working at Full Duplex mode
0: Set Port 2 M AC working at Half Dup l ex mode
[6:5]
Reserved
00
R
Reserved
[7]
FlowCtrl_ON
0
RW
Flow Control Enable when set to one
When Port 2 Auto-
Polling function is disabled (ACR [26] = 0), CPU is able to
read or write this register and set Port 0 M AC flow control mode.
When Port 2 Auto-Polling function is enabled ( ACR [26] =1), The
Auto-
Polling logic take control of this register and CPU can only read this bit
to know Port 2 MAC’s flow control mode.
1: Enable Port 2 M AC Flow Control function
0: Disable Port 2 M AC Flow Control function
[8]
CRC_Check
1
RW
Enable Port 2 MAC CRC check function when set t o one
1: Enable Port 2 MAC CRC check function
0: Disable Port 2 MAC CRC check function
[9]
Reserved
0
RW
Reserved
[10]
AcceptAll
0
RW
1: Accept all packet even illegal (oversize, undersize, crc error..).
0: Only accept legal packet.
NOTE: The undersize p a c ket will add pa dding within the RX MAC.
[11] 1XsecurityON 0 RW Enable Port 2 802.1X function when set to one
1: Enable Port 2 802.1X l function
Note: LGCR [16] 1X_En also need to set to 1
0: Disable Port 2 802.1X function
[12]
RXStop
0
RW
Drop the RX MAC incoming packets when this bit is set to o ne
1: Drop all the receiving packets
0: Disable RXStop function.
[13]
TXStop
0
RW
Stop TX from Transmit the packets when this bit is set to one.
1: Stop tra nsmit packets
0: Disbale TXStop function
131
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
[14]
Reserved
0
R
Reserved
[15]
Uplink_Port
0
RW
Valid only when 802.1QinQ double tagging function (LGCR [15]) is enabled.
1: Uplink_Port
0: Access_Port.
[16]
EnRXRate
0
RW
Port 2 Ingress Rate Limit Function
1: Enable Port 2 RX Rate limit function
0: Disable Port 2 RX Rate limit function
[17] EnTXRate 0 RW Port 2 E gre ss Rate Limit Function
1: Enable Port 2 TX Rate limit function
0: Disable Port 2 TX Rate limit function
[18]
DAMatch_Ena
ble
0
RW
If this bit is set to one, any receivin g packet w ho’s DA MAC is not match with
the pre-defined Register address 0x230
, 0x234 MAC address, the packet will
be dropped except Multicast and Broadcast packets.
1: Port 2 Only pass multicast, broadcast packet and unicast with DA match
Port 2’s DA MAC setti ng in register s P2D AR0 and P2DAR1.
0: Disable DAMatch_Enable function
[19]
Reserved
0
RW
Reserved
[31:20]
Reserved
0x000
R
Reserved
5.1.67 Port 2 802.1p QoS Mapping Table Register (P2QMTR)
Address 0x284
Bit
Name
Default
Value
R/W
Function
[1:0]
RX_QoS0
00
RW
802.1p QoS Mapping Table:
This table converts eight QoS value to one of the i nterna l four que ues. The
AX88613 only support 0,1, 2 and 3.
Internal Qo S value when RX packet’s QoS = 0
[3:2]
RX_QoS1
00
RW
Internal Qo S value when RX packet’s QoS = 1
[5:4]
RX_QoS2
01
RW
Internal Qo S value when RX packet’s QoS = 2
[7:6]
RX_QoS3
01
RW
Internal Qo S value when RX packet’s QoS = 3
[9:8]
RX_QoS4
10
RW
Internal Qo S value when RX packet’s QoS = 4
[11:10]
RX_QoS5
10
RW
Internal Qo S value when RX packet’s QoS = 5
[13:12]
RX_QoS6
11
RW
Internal Qo S value when RX packet’s QoS = 6
[15:14]
RX_QoS7
11
RW
Internal Qo S value when RX packet’s QoS = 7
[18:16]
Reserved
000
RW
Reserved
[19]
Reserved
0
R
Reserved
[26:20]
Reserved
0x00
RW
Reserved
[27]
Reserved
0
R
Reserved
[31:28]
Reserved
0x0
RW
Reserved
132
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
5.1.68 Port 2 802.1Q Configuration for UnTag Frame Register (P2QCR)
Address 0x288
Bit
Name
Default
Value
R/W
Function
[11:0]
PVID
0x001
RW
VLAN ID value (1 ~ 4095, default 1)
[12]
CF
0
RW
CF Flag
[15:13]
QoS
00
RW
QoS value
[31:16]
Reserved
0x0000
R
Reserved
* This Tag information will be inserted when untag frame is received.
5.1.69 Port 2 RX per Queue Rate Limit Control Register 0 (P2RQR0)
Address 0x28C
Bit
Name
Default
Value
R/W
Function
[11:0]
Rx_q0_rate
0xFFF
RW
Port 2 RX queue 0 rate limit (4K bytes per unit )
The default value 0xFFF means disable RX queue 0 rate limit.
[15:12]
Reserved
0000
R
Reserved
[27:16]
Rx_q1_rate
0xFFF
RW
Port 2 RX queue 1 rate limit (4K bytes per unit)
The default value 0xFFF means disable RX queue 1 rate limit.
[31:28]
Reserved
0000
R
Reserved
5.1.70 Port 2 RX per Queue Rate Limit Control Register 1 (P2RQR1)
Address 0x290
Bit
Name
Default
Value
R/W
Function
[11:0] Rx_q2_rate 0xFFF RW P ort 2 RX queue 2 rate limit (4K bytes per unit)
The default value 0xFFF means disable RX queue 2 rate limit.
[15:12]
Reserved
0000
R
Reserved
[27:16]
Rx_q3_rate
0xFFF
RW
Port 2 RX queue 3 rate limit (4K bytes pe r unit)
The default value 0xFFF means disable RX queue 3 rate limit.
[31:28]
Reserved
0000
R
Reserved
5.1.71 Port 2 TX per Queue Rate Limit Control Register 0 (P2TQR0)
Address 0x294
Bit Name
Default
Value
R/W
Function
[11:0]
Tx_q0_rate
0xFFF
RW
Port 2 TX q ueue 0 r a te limit (4K bytes per uni t)
The default value 0xFFF means disable TX queue 0 rate limit.
[15:12]
Reserved
0000
R
Reserved
[27:16] Tx_q1_rate 0xFFF RW Port 2 TX queue 1 rate limit (4K bytes p er unit )
The default value 0xFFF means disable TX queue 1 rate limit.
[31:28]
Reserved
0000
R
Reserved
133
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
5.1.72 Port 2 TX per Queue Rate Limit Control Register 1 (P2TQR1)
Address 0x298
Bit
Name
Default
Value
R/W
Function
[11:0]
Tx_q2_rate
0xFFF
RW
Port 2 TX q ueue 2 r a te limit (4K bytes per uni t)
The default value 0xFFF means disable TX queue 2 rate limit.
[15:12]
Reserved
0000
R
Reserved
[27:16]
Tx_q3_rate
0xFFF
RW
Port 2 TX queue 3 rate limit (4K bytes per unit)
The default value 0xFFF means disable TX queue 3 rate limit.
[31:28]
Reserved
0000
R
Reserved
5.1.73 Port 2 Rate Limit Control Register (P2RLR)
Address 0x29C
Bit
Name
Default
Value
R/W
Function
[11:0]
ingress_rate
0xFFF
RW
Port 0 RX rate limit (4K bytes per unit)
For example, if ingress_rate=16 means port 0 can receive 64K byte within
P0RLTR Cycle_time window (one second).
0xFFF means disable RX per port rate limit.
[15:12]
Reserved
0000
R
Reserved
[27:16]
egress_rate
0xFFF
RW
Port 0 TX per port rate limit (4K bytes per unit)
0xFFF means disable TX pe r port ra te limit.
[31:28]
Reserved
0000
R
Reserved
5.1.74 Port 2 Rate Limit Timer Register (P2RLTR)
Address 0x2A0
Bit Name
Default
Value
R/W
Function
[26:0] Cycle_time 0x5F5E
100 RW Per po r t timer for ra te limit calculation. (Default 1 sec.)
3 Second = 10 ^ 8 ns = 0x5F5E100 x 10ns
(100MHz clock cycle time)
[31:27]
Reserved
00000
R
Reserved
5.1.75 Port 2 Flow Control High/Low Watermark Register (P2FCR)
Address 0x2A4
Bit
Name
Default
Value
R/W
Function
[7:0]
FCHW
0x28
RW
Flow Control High-water mark [7:0]: RX accumulate page count high water
level, once internal R X receiving page counter higher than t his thre s hold an
d
Flow control is enabled, then TX MAC will send Pause ON Frame out to
informal remote PHY stop sending packets.
[15:8]
FCLW
0x14
RW
Flow Control Low-w ater mark [7:0]: When Flow control is enabled and pause
is ON, RX receiv ing page counter if lower than this low water mark value then
TX MAC will send pause OFF frame to inform remote PHY back to normal
state.
[31:16]
Reserved
0x0000
R
Reserved
134
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
5.1.76 Port 2 Queue Weighting Configuration Register (P2QWR)
Address 0x2A8
Bit
Name
Default
Value
R/W
Function
[3:0]
Q0_Weight
1111
RW
Q0 weighting control fo r B MU scheduler module usage.
The default value is 1111 means disable weighting control.
Otherwise buffer management unit will schedule TX output packet based on
Q0/Q1/Q2 /Q 3 weighting distribution.
[7:4]
Q1_Weight
1111
RW
Q1 weighting control fo r B MU scheduler module usage
[11:8]
Q2_Weight
1111
RW
Q2 weighting control fo r B MU scheduler module usage
[15:12]
Q3_Weight
1111
RW
Q3 weighting control fo r B MU scheduler module usage
For example if Q0_Weight=1, Q1_Weight=2, Q2_Weight=4 and
Q3_We ight=8 then the output p a c kets will have this ratio 8:4:2:1 if all the
packets are the same size. The weighting here will based on the page count.
There are 128 bytes in a page.
[31:16]
Reserved
0x0000
R
Reserved
5.1.77 Port 2 DA MAC Address Register (P2DAR0, P2DAR1)
Address 0x2B0 (P2DAR0)
Bit
Name
Default
Value
R/W
Function
[7:0]
DAMAC2
[47:40]
0x00
RW
Default DA MAC2 address for Port 2 only valid when DAMatc hEn is set to
one.(P2MCR [18])
DA MAC2 address [47:40]
[15:8]
DAMAC2
[39:32]
0x00
RW
DA MAC2 address [39:32]
[23:16]
DAMAC2
[31:24]
0x00
RW
DA MAC2 address [31:24]
[31:24]
DAMAC2
[23:16]
0x00
RW
DA MAC2 address [23:16]
Address 0x2B4 (P2DAR1)
Bit Name
Default
Value R/W Function
[7:0]
DAMAC2
[15:8]
0x00
RW
Default DA MAC2 address for Port 2 only valid when DAMatc hEn is set to
one. (P2MCR [18])
DA MAC2 address [15:8]
[15:8]
DAMAC2
[7:0]
0x00
RW
DA MAC2 address [7:0]
[31:16]
Reserved
0x0000
RW
Reserved
5.1.78 Output Clock Select Register (OCSR)
Address 0x13C
Bit
Name
Default
Value
R/W
Function
[7:0]
OCSR[7:0]
0x00
RW
0x41 : Enable internal 50 MHz clock (divi der-by 2 from PHY PLL) as RMII
50MHz reference clock source.
0x00 : Default Value
[31:8]
Reserved
0x00000
0
RW
Reserved for debug purpose.
135
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
5.2 PHY Register Description
Address Register
Name Function Default
Value
0x00
BMCR
Basic Mode Control Register, basic register
0x3100
0x01
BMSR
Basic Mode status registers, basic register
0x7809
0x02
PHYIDR1
PHY Identifier register 1 extended register
0x003B
0x03
PHYIDR2
PHY Identifier register 2 extended register
0x1871
0x04
ANAR
Auto negotiation advertisement register extended register
0x01E1
0x05
ANLPAR
Auto negotiation link partner ability register, extended register
0x01E0
0x06
ANER
Auto nego tia tion expansion register, extended register
0x0000
0x07
Reserved
Reserved and currently not supported
0x0000
0x08 – 0x13
Reserved
IEEE 802.3u reserved
0x0000
5.2.1 Basic Mode Control Register (BMCR)
Address 0x00
Bit Name
Default
Value
R/W
Function
[6:0]
Reserved
X
RO
PCI configure register: Device selects timing.
[7] Collision_test 0 RW Collision test:
1 = Collision test enable
0 = Normal operation
[8]
Duplex_mode
1
RW
Duplex mode:
1 = Full duplex operation
0 = Normal operation
[9]
Restart_autone
gotiation
0
RW
Restart auto negotiation:
1 = Restart auto negotiation
0 = Normal operation
[10]
Isolate
0
RW
Isolate:
1 = Isolate
0 = Normal operation
[11] Powerdown 0 RW Power down:
1 = Power down
0 = Normal operation
[12]
Auto-negotiati
on_enable
1
RW
Auto negotiation enable:
1 = Auto negotiation enabled
Bit 8 and 1 3 of this register are ignored when this bit is set to one
0 = Auto negotiation disabled
Bit 8 and 1 3 of this register determine the link speed and mode.
[13] Speed_selectio
n 1 RW Speed Select
1 = 100 Mb/s
0 = 10Mb/s
[14] Loopback 0 RW Loopback:
1 = Loopback enable
0 = Normal Operation
[15]
Reset
0
RW
Reset
1 = Software reset
0 = Normal Operation
136
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
5.2.2 Basic Mode Status Register (BMSR)
Address 0x01
Bit
Name
Default
Value
R/W
Function
[0]
Extended_capa
bility
1
RO
Extended capability:
0 = Basic register capable only
1 = Extended register capable
[1]
Jabber_detect
0
RO
Jabber detect:
0 = No Jabber co ndition is detected
1 = Jabber condition is detected
[2] Link_status 0 RO Link Status:
0 = Link is not established
1 = Valid link is established (100 Mbps or 10 Mbps operation)
[3]
Autonegotiatio
n_ability
1
RO
Auto negotiation ability:
0 = T his IP is not able to perform auto-negotiation
1 = T his IP is able to perform auto-negotiation
[4]
Remote_fault
0
RO
Remote fault:
0 = No remote fault condition detected
1 = Remote fault condition detected (cleared on read or by a chip reset)
[5]
Autonegotiatio
n_complete
0
RO
Auto negotiation complete:
0 = Auto negotiation pro c e ss is not co mplete
1 = Auto negotiation pro c e ss is co mplete
[6] MF_preamble_
suppression 0 RO Management Frame (MF) preamble suppression:
0 = This IP will not accept management frames with preamble suppressed
1 = This IP will accept management frames with preamble suppressed
[10:7]
Reserved
0
RO
Reserved:
Write as a 0, read as “don’t care”
[11]
10BASE-T_hal
f-duplex
1
RO
10 BASE-T half-duplex capable:
0 = This IP is not able to perform in 10 BASE-T half-duplex mode
1 = This IP is able to perform in 10 BASE-T half-duplex mode
[12]
10BASE-T_ful
l-duplex
1
RO
10 BASE-T full-duplex capable:
0 = This IP is not able to perform in 10 BASE-T fu ll-duplex mode
1 = This IP is able to perform in 10 BASE-T full -duplex mode
[13]
100BASE-TX
_half-duplex
1
RO
100 BASE-TX half-duplex capable:
0 = This IP is not able to perform in 100 BASE-TX half-duplex mode
1 = This IP is able to perform in 100 BASE-TX half-duplex mode
[14] 100BASE-TX
_full-duplex 1 RO 100 BASE-TX full-duplex capable:
0 = This IP is not able to perform in 100 BASE-T X full-duplex mode
1 = This IP is able to perform in 100 BASE-TX ful l-duplex mode
[15] 100BASE-T4 0 RO 100 BASE-T4 capable:
0 = This IP is not able to perform in 100 BASE-T4 mode
1 = This IP is able to perform in 100 BASE-T4 mode
137
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
5.2.3 PHY Identifier Register 1 (PHYIDR1)
Address 0x02
Bit
Name
Default
Value
R/W
Function
[15:0]
OUI_MSB
0x003B
RO
OUI’s most significant bits:
This register stor e s bits 3 to 18 of the OUI to bits 1 5 to 0 o f this register
respectively.
The most significant two bits of the OUI are ignor e d.
This re gis ter is prog ram mable by s ett in g PHY IDRG 2 [15:0] and PHYIDRG3
[15:0].
5.2.4 PHY Identifier Register 2 (PHYIDR2)
Address 0x03
Bit Name
Default
Value R/W
Function
[3:0]
MDL_REV
0x1
RO
Model revision number:
Four bits of PHY revision number are mappe
d to bits 3 to 0 (most significant
bit to bit 9 )
This re gis ter is prog ram mable by s ett in g PHY IDRG 2 [15:0] and PHYIDRG3
[15:0]
[9:4]
VNDR_MDL
0x07
RO
Vendor model number.
[15:10]
OUI_LSB
0x06
RO
OUI’s least significant bits:
Bits 19 to 24 of the OUI are mapped to bits 15 to 10 of this register
respectively.
This re gis ter is prog ram mable by s ett in g PHY IDRG 2 [15:0] and PHYIDRG3
[15:0].
138
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
5.2.5 Auto-Negotiation Advertisement Register (ANAR)
Address 0x04
Bit
Name
Default
Value
R/W
Function
[4:0]
Selector
00001
RW
Protocol selectio n b its:
These bits contain the binary encoded protocol selector supported by this
PHY. 00001 indicates that this PHY supports IEEE 802.3 CSMA/CD.
[5]
10_HD
1
RW
10 BASE-T half-duplex support:
0 = 10 BASE-T ha lf-duplex is not supported by this PHY .
1 = 10 BASE-T ha lf-duplex is supported by this PHY.
[6] 10_FD 1 RW 10 BASE-T full-duplex support:
0 = 10 BASE-T full-duplex is not supported by this PHY.
1 = 10 BASE-T full-duplex is supported by this PHY.
[7]
TX_HD
1
RW
100 BASE-TX half-duplex support:
0 = 100 BASE-TX half-duplex is not supported by this PHY.
1 = 100 BASE-TX half-duplex is supported by this PHY.
[8]
TX_FD
1
RW
100 BASE-T X full-duplex support:
0 = 100 BASE-TX full duplex is not supported by this PHY.
1 = 100 BASE-TX ful l dup lex is supported by this PHY.
[9]
T4
0
RO
100 BASE-T4 support:
0 = 100 BASE-T4 is not supported by this PHY.
1 = 100 BASE-T4 is supported by this PHY.
[10] Pause 1 RW Pause:
0 = Pause operation is not enabled
1 = Pause operation is enabled for full-duplex links
[12:11]
Reserved
X
RW
Reserved.
Write as a 0, read as “don’t care”
[13]
RF
0
RW
Remote fault: (not supported)
0 = No fault detected
1 = Fault condition detected and advertised
[14]
ACK
0
RO
Acknowledge:
0 = Not acknowledged
1 = Link partner ability data reception acknowledged
[15]
NP
0
RO
Next page indication:
0 = No next page available
1 = Next page available
The PH Y do es not s upport t he next page func t ion
139
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
5.2.6 Auto-Negotiation Link Partner Ability Register (ANLPAR)
Address 0x05
Bit
Name
Default
Value
R/W
Function
[4:0]
Selector
00000
RW
Protocol selectio n b its:
Link partner’s binary encoded protocol selector
[5]
10_HD
1
RW
10 BASE-T half-duplex support:
0 = 10 BASE-T ha lf-duplex is not supported by link partner
1 = 10 BASE-T ha lf-duplex is supported by link partner
[6]
10_FD
1
RW
10 BASE-T full-duplex support:
0 = 10 BASE-T full duplex is not suppor te d by link partner.
1 = 10 BASE-T full-duplex is supported by link partner.
[7] TX_HD 1 RW 100 BASE-TX hal f-duplex support:
0 = 100 BASE-TX half-duplex is not supported by link partner.
1 = 100 BASE-TX half-duplex is supported by link partner.
[8]
TX_FD
1
RW
100 BASE-T X full-duplex support:
0 = 100 BASE-TX full duplex is not supported by link partner.
1 = 100 BASE-TX full-duplex is supported by link partner.
[9]
T4
0
RO
100 BASE-T4 support:
0 = 100 BASE-T4 is not supported by link partner.
1 = 100 BASE-T4 is supported by link partner.
[10]
Pause
0
RW
Pause:
0 = Pause operation is not supported by link partner
1 = Pause operation is supported by link partner
[12:11] Reserved X RW Reserved.
Write as a 0, read as “don’t care”
[13] RF 0 RW Remote fault: (not suppo rted)
0 = No remote fault detected by link partner
1 = Remote fault detected by link partner
[14]
ACK
0
RO
Acknowledge:
0 = Not acknowledged
1 = Link partner ability data reception acknowledged
[15]
NP
0
RO
Next page indication:
0 = Link par t ner is not next page enable
1 = Link partner is Next page enable
140
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
5.2.7 Auto-Negotiation Expansion Register (ANER)
Address 0x06
Bit
Name
Default
Value
R/W
Function
[0]
LP_AN_AB
0
RO
Link partner auto -negotiatio n enab le :
0 = Link par t ner auto-negotiation is not supported
1 = Link par t ner auto-negotiation is suppor te d
[1]
Page_RX
0
RO
New page received:
0 = New page is not received
1 = New page is received
[2] NP_AB 0 RO PHY next page enable:
0 = PHY is not next page enable
1 = PHY is next page enable
[3]
LP_NP_AB
0
RO
Link partner next page enable:
0 = Link par t ner is not next page enable
1 = Link partner is next page enable
[4]
PDF
0
RO
Parallel detection fault:
0 = No fault detected
1 = Fault detected via the parallel detection function
[15:5]
Reserved
0
RO
Reserved
Write as a 0, read as “don’t care”
141
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
5.3 Reverse Mode PHY Register Description
Address
Register
Name
Function Default
Value
0x00 Rev_BMCR Basic Mode Control Register, basic register 0x3100
0x01
Rev_BMSR
Basic Mode status registers, basic register
0x7809
0x04
Rev_ANAR
Auto negotiation advertisement register
extended register
0x05E1
0x05
Rev_ANLPAR
Auto negotiation link partner ability register,
extended register
0x01E0
0x10
Rev_LUCR
Local User-Defined Control Register
0x0000
0x11
Rev_RUCR
Remote User-Defined Control Register
0x0000
NOTE1: The AX88613 only support MDC/MDIO write on Rev_BMCR loopback function and Rev_RUCR register
NOTE2: The Rev_BMSR Link_status will set to one when P0MCR/P1MCR/P 2MCR [0] MAC_Enable is set to one.
5.3.1 Basic Mode Control Register (Rev_BMCR)
Address 0x00
Bit
Name
Default
Value
R/W
Function
[6:0]
Reserved
0
RO
PCI configure register: Device select timing.
[7]
Collision_test
0
RO
Collision test:
1 = Collision test enable
0 = Normal operation
[8]
Duplex_mode
1
RO
Duplex mode:
1 = Full duplex operation
0 = Normal operation
[9]
Restart_autone
gotiation
0
RO
Restart auto negotiation:
1 = Restart auto negotiation
0 = Normal operation
[10] Isolate 0 RO Isolate:
1 = Isolate
0 = Normal operation
[11]
Powerdown
0
RO
Power down:
1 = Power down
0 = Normal operation
[12]
Auto-negotiati
on_enable
1
RO
Auto negotiation enable:
1 = Auto negotiation enabled
Bit 8 and 13 of this register are ignor e d when this bit is set to one
0 = Auto negotiation disabled
Bit 8 and 1 3 of this register determine the link speed and mode.
[13]
Speed_selectio
n
1
RO
Speed Select
1 = 100 Mb/s
0 = 10Mb/s
[14]
Loop_back
0
RW
Loop back:
1 = Loop back enable
0 = Normal Operation
[15]
Reset
0
RO
Reset
1 = Software reset
0 = Normal Operation
142
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
5.3.2 Basic Mode Status Register (Rev_BMSR)
Address 0x01
Bit
Name
Default
Value
R/W
Function
[0]
Extended_capa
bility
1
RO
Extended capability:
0 = Basic register capable only
1 = Extended register capable
[1]
Jabber_detect
0
RO
Jabber detect:
0 = No Jabber co ndition is detected
1 = Jabber condition is detected
[2] Link_status 0 RO Link St atus:
0 = Link is not established
1 = Valid link is established (100 Mbps or 10 Mbps operation)
[3]
Autonegotiatio
n_ability
1
RO
Auto negotiation ability:
0 = T his IP is not able to perform auto-negotiation
1 = T his IP is able to perform auto-negotiation
[4]
Remote_fault
0
RO
Remote fault:
0 = No remote fault condition d e te c te d
1 = Remote fault condition detected (cleared on read or by a chip reset)
[5]
Autonegotiatio
n_complete
0
RO
Auto negotiation complete:
0 = Auto negotiation pro c e ss is not co mplete
1 = Auto negotiation pro c e ss is co mplete
[6] MF_preamble_
suppression 0 RO Management Frame (MF) preamble suppression:
0 = This IP will not accept management frames with preamble suppressed
1 = This IP will accept management frames with preamble suppressed
[10:7]
Reserved
0
RO
Reserved:
Write as a 0, read as “don’t care”
[11]
10BASE-T_hal
f-duplex
1
RO
10 BASE-T half-duplex capable:
0 = This IP is not able to perform in 10 BASE-T half-duplex mode
1 = This IP is able to perform in 10 BASE-T half-duplex mode
[12]
10BASE-T_ful
l-duplex
1
RO
10 BASE-T full-duplex capable:
0 = This IP is not able to perform in 10 BASE-T fu ll-duplex mode
1 = This IP is able to perform in 10 BASE-T full -duplex mode
[13]
100BASE-TX
_half-duplex
1
RO
100 BASE-TX half-duplex capable:
0 = This IP is not able to perform in 100 BASE-TX half-duplex mode
1 = This IP is able to perform in 100 BASE-TX half-duplex mode
[14] 100BASE-TX
_full-duplex 1 RO 100 BASE-TX full-duplex capable:
0 = This IP is not able to perform in 100 BASE-T X full-duplex mode
1 = This IP is able to perform in 100 BASE-TX full-duplex mode
[15] 100BASE-T4 0 RO 100 BASE-T4 capable:
0 = This IP is not able to perform in 100 BASE-T4 mode
1 = This IP is able to perform in 100 BASE-T4 mode
143
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
5.3.2 Auto-Negotiation Advertisement Register (Rev_ANAR)
Address 0x04
Bit
Name
Default
Value
R/W
Function
[4:0]
Selector
00001
RO
Protocol selectio n b its:
These bits contain the binary encoded protocol selector supported by this
PHY. 00001 indicates that this PHY supports IEEE 802.3 CSMA/CD.
[5]
10_HD
1
RO
10 BASE-T half-duplex support:
0 = 10 BASE-T half-duplex is not supported by this PHY.
1 = 10 BASE-T ha lf-duplex is supported by this PHY.
[6] 10_FD 1 RO 10 BASE-T full-duplex support:
0 = 10 BASE-T full-duplex is not supported by this PHY.
1 = 10 BASE-T full-duplex is supported by this PHY.
[7]
TX_HD
1
RO
100 BASE-TX half-duplex support:
0 = 100 BASE-TX half-duplex is not supported by this PHY.
1 = 100 BASE-TX half-duplex is supported by this PHY.
[8]
TX_FD
1
RO
100 BASE-T X full-duplex support:
0 = 100 BASE-TX full duplex is not supported by this PHY.
1 = 100 BASE-TX full duplex is supported by this PHY.
[9]
T4
0
RO
100 BASE-T4 support:
0 = 100 BASE-T4 is not supported by this PHY.
1 = 100 BASE-T4 is supported by this PHY.
[10] Pause 1 RO Pause:
0 = Pause operation is not enabled
1 = Pause operation is enabled for full-duplex links
[12:11]
Reserved
0
RO
Reserved.
Write as a 0, read as “don’t care”
[13]
RF
0
RO
Remote fault: (not supported)
0 = No fault detected
1 = Fault condition detected and advertised
[14]
ACK
0
RO
Acknowledge:
0 = Not acknowledged
1 = Link partner ability data reception acknowledged
[15]
NP
0
RO
Next page indication:
0 = No next page available
1 = Next page available
The PH Y do es not s upport t he next page func t ion
144
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
5.3.3 Auto-Negotiation Link Partner Ability Register (Rev_ANLPAR)
Address 0x05
Bit
Name
Default
Value
R/W
Function
[4:0]
Selector
00000
RO
Protocol selectio n b its:
Link partner’s binary encoded protocol selector
[5]
10_HD
1
RO
10 BASE-T half duplex support:
0 = 10 BASE-T half duplex not supported by link partner
1 = 10 BASE-T half duplex supported by link partner
[6]
10_FD
1
RO
10 BASE-T full duplex support:
0 = 10 BASE-T full duplex not supported by link partner.
1 = 10 BASE-T full duplex supported by link partner.
[7] TX_HD 1 RO 100 BASE-T X half d uplex support:
0 = 100 BASE-TX half duplex not supported by link partner.
1 = 100 BASE-TX half duplex supported by link partner.
[8]
TX_FD
1
RO
100 BASE-TX full duplex support:
0 = 100 BASE-TX full duplex not supported by link partner.
1 = 100 BASE-TX full duplex supported by link partner.
[9]
T4
0
RO
100 BASE-T4 support:
0 = 100 BASE-T4 is not supported by link partner.
1 = 100 BASE-T4 is supported by link partner.
[10]
Pause
0
RO
Pause:
0 = Pause operation is not supported by link partner
1 = Pause operation is suppor te d by link partner
[12:11] Reserved X RO Reserved.
Write as a 0, read as “don’t care”
[13] RF 0 RO Remote fault: (not supported)
0 = No remote fault detected by link partner
1 = Remote fault detected by link partner
[14]
ACK
0
RO
Acknowledge:
0 = Not acknowledged
1 = Link partner ability data reception acknowledged
[15]
NP
0
RO
Next page indication:
0 = Link par t ner is not next page enable
1 = Link partner is Next page enable
5.3.4 Local User-Defined Control Register (Rev_LUCR)
Address 0x10
Bit
Name
Default
Value
R/W
Function
[15:0] LocalUser-
Data
0x0000 RW User-Defined Local Control Data information
5.3.5 Remote User-Defined Control Register (Rev_RUCR)
Address 0x11
Bit Name Default
Value R/W
Function
[15:0]
RemoteUse
r-Data
0x0000
RO
User-Defined Remote Control Data information
145
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
6.0 ELECTRICAL SPECIFICATION AND TIMING
6.1 DC Characteristics
6.1.1 Absolute Maximum Ratings
Description
Rating
Units
VCCK (Core power supply),
VCC18(voltage regul ator),
P0_VCC18A, P1_VCC18A (analog power supply for oscillator, PLL, PHY)
-0.3 to 2.16
V
VCC3IO (power supply for 3.3V I/O),
VCCAH(volta ge regul ator),
P0_VCC33A, P1_VCC33A (analog power supply for bandgap)
-0.3 to 4.0
V
Storage Temperature
-40 to 150
°C
I
IN
(DC input current)
20 mA
I
OUT
(Output short circuit current)
20
mA
Note: Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation
should be restricted in the recommended operating condition section of this datasheet. Exposure to absolute
maximum rating condition for extended periods may affect device reliability
6.1.2 Recommended Operating Condition
Symbol
Parameter
Min
Typ
Max
Unit
VCCK
Digital core power supply
1.62
1.8
1.98
V
P0_VCC18A,
P1_VCC18A Analog core power supply 1.62 1.8 1.98 V
VCCAH
Power s upply of on-chip vo l tage regulator
2.97
3.3
3.63
V
VCC3IO
Power supply of 3.3V I/O
2.97
3.3
3.63
V
P0_VCC33A,
P1_VCC33A
Analog power supply for bandgap
2.97
3.3
3.63
V
VIN18
Input voltage of 1.8 V I/O
0
1.8
1.98
V
V
IN3
Input voltage of 3.3 V I/O
0
3.3
3.63
V
T
j
Commercial j unction operating temperature
-40
25
125
℃
T
a
Commercial oper ating temperature
0
-
70
℃
146
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
6.1.3 DC Characteristics of 3.3V I/O (VCC3IO = 3.3V)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VCC3I
O
Power supply of 3.3V I/O 3.3V I/O 2.97 3.3 3.63 V
VCCK
Power supply of internal core cells and
I/O-to-core interface
1.8V 1.62 1.8 1.98 V
Tj Juncti on temperat ure -40 25 125 ℃
Vil
Input low volta ge
LVTT L spe c.
0.8
V
Vih
Input high voltage
2.0
V
Vt-
Schmitt-tri gger negative threshold voltage
LVTT L spe c.
0.8
V
Vt+
Schmitt-tri gger negative threshold voltage
2.0
Vol
Output low voltage
Iol = 2 ~ 12 mA
-
-
0.4
V
Voh
Output high voltage
Ioh = -2 ~ -12 mA
2.4
-
-
V
Rpu Input pul l-up resistance
V
in
= 0V
40 75 190 KΩ
Rpd
Input pull-down resistance
V
in
= VCC3I
O
40
75
190
K
Ω
Iin Input leaka ge current Vi n = VCC3IO or 0V
-5 ±1 5 μA
Input leaka ge current with pull-up resistance
Vin = 0V
-15
-45
-90
μ
A
Input leakage current with pull-down resi stance
Vin = VCC3 IO
15
45
90
μ
A
IOZ Tri-state output leakage c urre nt -10 ±1 10 μA
6.1.4 DC Characteristics of 2.5 V I/O (VCC3IO = 2.5V)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VCC3I
O
Power supply of 2.5V I/O
2.5V I/O
2.25
2.5
2.75
V
VCCK
Power supply of internal core cells and
I/O-to-core interface
1.8V
1.62
1.8
1.98
V
Tj
Junct ion tempera ture
-40
25
125
℃
Vil Input low voltage CMOS spec. 0.25*
VCC3IO
V
Vih
Input high voltage
0.625*
VCC3IO
V
Vt- Schmitt-trigger negative threshold voltage CMOS spec. 0.25*
VCC3IO
V
Vt+
Schmitt-trigger ne gative threshold voltage
0.625*
VCC3IO
Vol
Output low voltage
Iol =1.1 ~ 6.68mA
-
-
0.4
V
Voh
Output high voltage
Ioh = -1.1 ~ -6.6mA
1.85
-
-
V
Rpu
Input pull-up resistance
V
in
= 0V
40
110
290
K
Ω
Rpd
Input pull-down resistance
V
in
= VCC3I
O
40
110
290
K
Ω
Iin
Input leaka ge current
Vin = VCC3 IO or 0V
-5
±
1
5
μ
A
Input leaka ge current with pull-up resistance
Vin = 0V
-7
-23
-62
μ
A
Input leakage current with pull-down resi stance
Vin = VCC3 IO 7 23 62 μA
IOZ Tri-state output leakage current -10 ±1 10 μA
147
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
6.1.5 DC Characteristics of 1.8 V I/O (VCC3IO = 1.8V)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VCC3I
O
Power supply of 1.8V I/O 1.8V I/O 1.62 1.8 1.98 V
VCCK
Power supply of internal core cells and
I/O-to-core interface
1.8V 1.62 1.8 1.98 V
Tj Juncti on temperat ure -40 25 125 ℃
Vil
Input low volta ge
CMOS spec.
0.3*
VCC3IO
V
Vih Input high voltage 0.7*
VCC3IO
V
Vt-
Schmitt-tri gger negative threshold voltage
CMOS spec.
0.3*
VCC3IO
V
Vt+
Schmitt-tri gger negative threshold voltage
0.7*
VCC3IO
Vol
Output low voltage
Iol = 0.7 ~ 4.2mA
-
-
0.4
V
Voh
Output high voltage
Ioh = -0.7 ~ -4.2mA
0.7*
VCC3IO
-
-
V
Rpu Input pul l-up resistance
V
in
= 0V
80 200 510 KΩ
Rpd
Input pull-down resistance
V
in
= VCC3I
O
80
200
510
K
Ω
Iin
Input leakage current
Vin = VCC3 IO or 0V
-5
±
1
5
μ
A
Input leaka ge current with pull-up resistance Vin = 0V -3 -9 -25 μA
Input leakage current with pull-down resi stance
Vin = VCC3 IO
3
9
25
μ
A
I
OZ
Tri-state output leakage current
-10
±
1
10
μ
A
148
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
6.1.6 DC Characteristics of Voltage Regulator
Symbol
Description
Conditions
Min
Typ
Max
Unit
VCCAH
Power supply of on-chip
voltage regu lator.
2.7
3.3
3.6
V
Tj Operating junction
temperature.
-40 25 125 ℃
Iload_v18
Drivi ng curr ent.
Normal operation,
-
-
300
mA
Driving current.
Standby mode enabled,
-
-
30
mA
V18
Output voltage o f on-chip
voltage regulator.
VCCAH = 3.3V After trimming
1.71
1.8
1.89
V
VCCAH = 2.7V
Iload_v18=300mA
1.71
1.8
1.89
VCCAH=3.6V STB=1
Iload_v18_stb=30 mA Tj=25℃
1.71
1.8
1.89
VCCAH=3.3V STB=1
Iload_v18_stb=30 mA Tj=25℃ 1.71 1.8 1.89
Vdrop Dropout voltage. △V18F = -1%,
Iload_v18 = 10mA
- 0.1 0.2 V
△V18
(△VCCAH x V18) Line regulation. VCCAH = 2.7 ~ 3.6V,
Iload_v18 = 50mA - 0.2 0.4 %/V
△V18
(△Iload_v18 x V18)
Load regulation.
VCCAH = 3.3V,
1mA ≦ Iload_v18 ≦ 300mA
-
0.006
0.012
%/mA
△V18
△Tj
Temperature coefficient.
VCCAH = 3.3V,
-40℃ ≦ Tj ≦ 125℃
Iload_v18=10mA
-
0.1
0.2
mV/
℃
Iq_25
℃
Quiescent current at 25
℃.
VCCAH = 3.3V, STB = 0
-
100
165
μ
A
VCCAH = 3.3V, STB = 1
-
70
100
μ
A
Iq_125℃ Quiescent current at 125 ℃.
VCCAH = 3.3V, STB = 0 - 125 185 μA
VCCAH = 3.3V, STB = 1
-
85
115
μ
A
Idis
Disable current
1
3
μ
A
Cout Output external capacitor. 0.1 1 - μF
△Vtransient
Voltage drop due to current
transient effect
VCCAH = 3.3V Cout = 1
μ
F
Tr = T f = 10 ns
0.3
V
ESR
Allowable effective series
resistance of external
capacitor.
-
0.5
1
Ω
149
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
6.2 Thermal Characteristics
A. Junct ion to a mbient ther mal resista nc e, JA
θ
Symbol
Min
Typ
Max
Units
JA
θ
- 25.2 -
o
C/W
B. Junction to case thermal resistance,
JC
θ
Symbol
Min
Typ
Max
Units
JC
θ
- 9.6
o
C/W
Note: JA
θ
,
JC
θ
defined as below
JA
θ
=
PTT AJ −
, JC
θ
=
PTT CJ −
TJ: maximum junction temperat ure
TA: ambient o r environment te mperature
TC: the top center of comp ound surface temperature
P: input power (watts)
150
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
6.3 Power Consumption
Device only
Power measurements base on 3.3V/25 °C condition with the help of current probe.
AX88613
Both Ports @
10BASE-T
Half-Duplex*1
Both Ports @
100BASE-TX
Full-Duplex *1
D1
RemoteWake-up
Mode*2
D2
Sleep Mode*3
Both Ports in
PHY
Power-Down*4
Units
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
Min
Typ
Max
3.3V*5
52
35
20
2
~1
mA
1.8V*6
152
270
37
4
~1
mA
Total
204
346
57
6
~1
mA
673
1142
188
20
~1
mW
*1: 100% utilization on both ports.
*2: PHY0 Power-On, PHY1 Power-Down, Remote Wake-up function enable for Port 0, core clock ON
*3: Both PHY Power-Down, core clock ON, Write any data to SMER to go back normal mode
*4: Both PHY Power-Down, core clock OFF
*5: 3.3V current include VCC3IO + P0_VCC3A3 + P1_VCC3A3
*6: 1.8V current include VCCK + P0_VCC18A + P1_VCC18A
Note: The transformer will consume additional 40mA @3.3V for 100BASE-TX and 100mA @3.3V for 10BASE-T
Device and system components
This is the total of Ethernet connectivity solution, which includes ext ernal components s uch as the Eth ernet magn etic,
EEPROM, etc.
Power measurements base on 3.3V/25 °C condition.
Item
Test Conditi ons (Typica l C ondition)
AX88613
Units
Min
Typ
Max
1
10BASE-T o peration (Both Ports, Half-Duplex)
1333
mW
2
100BASE-TX o peration (Both Po r ts, Full-Duplex)
1340
mW
3
Cabl e unplug under power saving mode (B oth Por t s )
607
mW
4
D1 WOL mode (Port 0 PHY Power-On, Port 1 PHY
Power-Down, Remote Wake-up supported for port 0)
353
mW
5
D2 Slee p mode (Both Ports, Remote Wake-up not su pport ed)
20
mW
6.
PHY power down (Both Ports)
<1
mW
151
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
6.4 Power-up Sequence
At power-up, the AX88613 requires the VCC3IO/VCC3A3 power supply to rise to nominal opera ting voltage within
Trise3 and the V18F/VCCK/VCC18A power supply to rise to no minal oper a ting voltage within Trise2.
RST_N
T3
XTLN
T4
Symbol
Parameter
Condition
Min
Typ
Max
Unit
T1
3.3V power supply rise time
From 0V to 3.3V
0.5
-
10
ms
T2
1.8V power supply rise time
From 0V to 1.8V
-
-
10
ms
T12
3.3V rise to 1.8V r ise time delay
-5
-
5
ms
T3
System Reset rise time after the
clock is stable
From VCCIO =
3.3V and VCCK =
1.8V to RST_N
going high
200
us
T4 Oscillator stable time From VCCK =
1.8V
805 us
NOTE: Please read the register 0x000 [16] ChipInitDone to check if the chip has finish initialized process.
0V
3.3V
T1
0V
1.8V
T2
T12
V18F/VCCK/VCC18A
VCC3IO/VCC3A3
152
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
6.5 AC specifications
Notice that the following AC timing specifications for output pins are based on CL (Output
load)=50pF.
6.5.1 Clock Timing
XTLP
TP_XTLP
TH_XTLP TL_XTLP
Symbol
Parameter
Condition
Min
Typ
Max
Unit
TP XTL25P
XTLP clock cycle time
-
40.0
-
ns
TH XTL25P
XT LP clock high t ime
-
20.0
-
ns
TL XTL25P
XTLP clock low time
-
20.0
-
ns
V
IH
VIL
153
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
6.5.2 Serial EEPROM Timing
ThTs
TlcsTlcsThcsTscs
TodTdv
TclkTclkTclTclTchTch
SK
D IO ( a s OUTPU T)
CS
DIO (as INP UT)
Symbol
Description
Min
Typ
Max
Unit
Tclk
SK clock cycle time
-
1000
-
ns
Tch
SK clock high time
-
500
-
ns
Tcl
SK clock low time
-
500
-
ns
Tdv
DIO output valid to SK rising e dge time
500
-
-
ns
Tod
SK rising edge to DIO output delay time
500
-
-
ns
Tscs
CS output valid to SK rising e dge time
500
-
-
ns
Thcs
SK falli ng edge t o CS invalid time
510
-
-
ns
Tlcs
Min imu m CS low time
2050
-
-
ns
Ts
DIO input setup time
10
-
-
ns
Th
DIO input hold time
30
-
-
ns
154
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
6.5.3 MII Interface Timing
TthTts
TtclkTtcl TtclkTtclTtchTtch
TXCLK
TXE N / TX D[3 :0 ]
TXCLK: Port 2 MII Transmit clock. (P2_TX_CLK)
TXD: Port 2 MII TX Data bus include P2_TXD0, P2_TXD1, P2_TXD2, and P2_TXD3.
TXEN: Port 2 MII Transmit Enable (P2_TX_EN)
Symbol
Description
Min
Typ
Max
Unit
Ttclk
TXCLK cloc k cycle time *1
-
40.0
-
ns
Ttch
TXCLK cloc k high time *2
-
20.0
-
ns
Ttcl
TXCLK cloc k low time *2
-
20.0
-
ns
Tts
TXD [3:0], TXEN setup to rising TXCLK
23.0
-
-
ns
Tth
TXD [3: 0], TXE N hold from rising TXCLK
7.0
-
-
ns
TrhTrs
TrclkTrcl TrclkTrclTrchTrch
RXCLK
RXDV / RXD[3:0]
RXCLK: Port 2 MI I Receive clock. (P2_RX_CLK)
RXD: Port 2 MII RX Data bus include P2_RXD0, P2_RXD1, P2_RXD2, and P2_RXD3.
RXDV: Port 2 MII Receive Data Valid (P2_RX_DV)
Symbol
Description
Min
Typ
Max
Unit
Trclk RXC LK clock cycle time *1
-
40.0
-
ns
Trch
RXCLK clock high time *2
-
20.0
-
ns
Trcl RXCLK clock low time *2
-
20.0
-
ns
Trs
RXD [3:0], RXDV setup to rising RXCLK
5.0
-
-
ns
Trh RXD [3:0], RXDV hold from rising TXCLK
3.5
-
-
ns
*1: For 10Mb ps, the typical value of Ttclk and Trclk shall scale to 400ns.
*2: For 10Mb ps, the typical value of Ttch, Ttcl, T r ch, and Trcl shall scale to 200ns.
155
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
6.5.4 Station Management Timing
ThTs
Tod
TclkTclk
TdTdTchTch
MDC
MD I O(as OUTPUT)
MDIO (a s IN PUT)
MAC mode w i th MII: MDC=Output
Symbol
Description
Min
Typ
Max
Unit
Tclk
MDC clock cycle time
-
1000
-
ns
Tch
MDC clock high time
-
500
-
ns
Tcl
MDC clock lo w time
-
500
-
ns
Tod
MDC clock rising edge to MDI O output delay
0.5
-
-
Tclk
Ts
MDIO data input setup time
10
-
-
ns
Th
MDIO data input hold time
30
-
-
ns
PHY/Dual-PHY mode with Reverse MII/RMII: MDC=Input
Symbol
Description
Min
Typ
Max
Unit
Tclk
MDC clock cycle time
-
1000
-
ns
Tch
MDC clock high time
-
500
-
ns
Tcl
MDC clock lo w time
-
500
-
ns
Tod
MDC clock rising edge to MDI O output delay
0
-
300
ns
Ts
MDIO data input setup time
10
-
-
ns
Th
MDIO data input hold time
30
-
-
ns
156
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
6.5.5 Reverse MII Timing
TrhTrs
TclkTcl TclkTclTchTch
RXCLK
RXD[3:0]
RXDV
RXCLK: Port 2 MII Transmit clock. (P2_RX_CLK)
RXD: Port 2 MII Transmit Data bus include P2_RXD0, P2_RXD1, P2_RXD2, and P2_RXD3.
RXDV: Port 2 MII Transmit Data Valid (P 2 _RX_DV)
Symbol
Description
Min
Typ
Max
Unit
Tclk
Clo c k c ycle time
-
40.0
-
ns
Tch
Clo c k high time
-
20.0
-
ns
Tcl
Clo c k low time
-
20.0
-
ns
Trs
RXD [3:0], RXDV setup to rising RXCLK
10.0
-
-
ns
Trh
RXD [3:0], RXDV hold from rising
RX
CLK
10.0
-
-
ns
TthTts
TclkTcl TclkTclTchTch
TXCLK
TXD[3:0]
TXEN
TXCLK: Port 2 MII Receive clock. (P2_TX_CLK)
TXD: Port 2 MII Receive Data bus include P2_TXD0, P2_TXD1, P2_TXD2, and P2_TXD3.
TXEN: Port 2 MII Receive Data Valid (P2_T X _EN)
Symbol
Description
Min
Typ
Max
Unit
Tts
TXD [3: 0], TXE N setup to rising TXCLK
11.0
-
-
ns
Tth TXD [ 3:0], TXE N hold from rising
TX
CLK
2.0
-
-
ns
157
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
6.5.6 Reverse RMII Timing
Tref_rhTref_rs
Tref_clk
Tref_cl Tref_clk
Tref_cl
Tref_chTref_ch
REFCLK_I
RXD[1:0]
CRSDV
RXCLK: Port 2 MII Transmit clock. (MII0_RX_CLK)
RXD: Port 2 MII Transmit Data Bus includes P2_RXD0 and P2_RXD1.
RXDV: Port 2 MII Transmit Data Valid (P 2 _RX_DV)
Symbol
Description
Min
Typ
Max
Unit
Tref_clk
Clo c k c ycle time
-
20.0
-
ns
Tref_ch
Clo c k high time
-
10.0
-
ns
Tref_cl
Clo c k low time
-
10.0
-
ns
Tref_rs
RXD [1:0], CRSDV setup to rising REFCLK_I
4.0
-
-
ns
Tref_rh
RXD [1 : 0], CRSDV hold from rising
REFCLK_I
2.0
-
-
ns
Tref_thTref_ts
Tref_clk
Tref_cl Tref_clk
Tref_cl
Tref_chTref_ch
REFCLK_I
TXD[1:0]
TXEN
TXCLK: Port 2 MII Receive clock. (P2_TX_CLK)
TXD: Port 2 MII Receive Data bus includes P2_TXD0 and P2_TXD1.
TXEN: Port 2 MII Receive Data Valid (P2 _ TX_EN)
Symbol
Description
Min
Typ
Max
Unit
Tref_ts
TXD [1: 0], TXE N setup to rising REFCLK_I
4.0
-
-
ns
Tref_th TX D [ 1: 0], TXE N hold from rising
REFCLK_I
2.0
-
-
ns
158
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
6.5.7 SPI Timing
MSB
MSB
SSsu
SSidleSSidle
SShdSSsu
DhdDsuDhd
Dsu
FclkFclk
SPI_CLK
MOSI
MISO
SS
SPI Slave Controller Timing Table:
Symbol
Description
Min
Typ
Max
Unit
Fclk
SPI_CLK clock frequency.
-
1
MHz
Dsu
MOSI data setup time before SPI_SCLK posedge.
10
-
-
ns
Dhd
MOSI data hold time after SPI_SCLK posedge.
30
-
-
ns
SSsu
SS setup time before SPI_SCLK posedge.
10
-
-
ns
SShd
SS hold time after SPI_SCLK posedge.
30
-
-
ns
SSidle
SPI_SS negation to next SPI_SS ac tive time
3
-
-
Spi_clk
159
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
6.5.8 10/100M Ethernet PHY Interface Timing
10/100M Ethernet PHY Transmitter Waveform and Spec
Symbol
Description
Condition
Min
Typ
Max
Units
Peak-to-peak differential output voltage
10BASE-T mode
4.4
5
5.6
V
Vtxa *2
Peak-to-peak differential output voltage
100BASE-TX mode
1.9
2
2.1
V
Tr / Tf
Signal rise / fall time
100BASE-TX mode
3
4
5
ns
Output jitter
100BASE-TX mode, scrambled idle
signal
-
-
1.4
ns
Vtxov
Overshoot
100BASE-TX mode
-
-
5
%
10/100M Ethernet PHY Receiver Spec
Symbol
Description
Condition
Min
Typ
Max
Units
Receiver input impedance
10
-
-
K
Ω
Differential squelch voltage
10BASE-T mode
300
400
500
mV
Common mode input voltage
2.97
3.3
3.63
V
Maximum error-free cable length
100
-
-
meter
Tr: from 10% to 90%
+Vtxov
0V
+Vtxa
160
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
7 PACKAGE INFORMATION
The AX88613 80 Pin LQFP Package
Exposed Pad (E-PAD) Information:
The AX88613 has an exposed pad to help transfer heat from the silicon wafer to the PCB. This metallic exposed pad
should be tied to ground. The exposed pad position is centered with reference to the body.
161
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
162
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
8 Ordering Information
Part N umber
Description
AX88613 LF
80 PIN, LQFP/E-PAD Package, Commercial grade 0°C to +70 °C (Green, Lead-Free)
163
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
Revision History
Revision
Date
Comment
V0.10
2008/04/17
Initial Release.
V0.20
2009/03/06
*Add MLD Snooping information (3.15)
*Add EEPROM information (3.19)
*Update pinout information ( 2.1 ~ 2.3 )
Rename P0_VCC18D to P0_VCC18A and P1_VCC18D to P1_VCC18A
Rename P0_GND18D to P0_VCC18A and P1_GND18D to P1_VCC18A
*Update Power Consumption Table on 6.4
*Add INT pin (2.6)
V1.00
2009/04/30
*Update 3.12 and 5.1.19 RMON Information
Remove unused counter on address 0x12 and 0x13
*Add thermal characteristics table (6.2)
*Add power-saving function desc ription (3.5)
*Add IP v6 MLD snooping function (3.15)
*Add EEPROM sample code (3.20)
*Add P HY power-saving control bit (5.1.2)
*Add P HY cable-off status information (5.1.3)
*Add sniffer register IPv4/IPv6 information (5.1.9)
*Add IO pad pull-up and pul l-down control register (5.1.32)
*Add multi-voltage 3.3V, 2.5V and 1.8V I/O support (6.3.1 ~ 6.3.3)
* Change bi-dire c tional IO pad abbreviations to B (2.0)
* Add 50MHz RMII reference clock spec. on 2.3.3 and 2.3.4 P2_REFCLK
V1.01
2009/09/18
*Modify some descriptions of RMON counter access in Section 3.12.
*Modify some descriptions of RCR register in Section 5.1.18.
*Add Section 5.1.78 to add the descriptions of OCSR re gis t er.
V1.02
2010/03/11
1. Added 1.8V power consumption information in Section 6.3.
2. Added the wide operating temperature range (-40 to +75°C) information in
Features page.
V1.03
2011/06/16
1. Removed the wide operating temperature range information in Features page.
2. Added copyright legal header information.
V1.04
2012/04/27
1. Updated the IC package information in Section 7.
164
AX88613
3-Port 10/100M Fast Ethernet Switch Controller
Copyright © 2008-2012 ASIX Electro nics Cor poratio n. All rights reserved.
4F, No. 8, Hsin Ann Rd., HsinChu Science Park,
HsinChu, Taiwan, R.O.C.
TEL: 886-3-5799500
FAX: 886-3-5799558
Email: support@asix.com.tw
Web: http://www.asix.com.tw