1
Rev. 6/30/03 SP3223 +3.0V to +5.5V RS-232 Transceivers © Copyright 2003 Sipex Corporation
SP3223/3243
Intelligent +3.0V to +5.5V RS-232 Transceivers
The SP3223 and SP3243 products are RS-232 transceiver solutions intended for portable or
hand-held applications such as notebook and palmtop computers. The SP3223 and SP3243
use an internal high-efficiency, charge-pump power supply that requires only 0.1µF capacitors
in 3.3V operation. This charge pump and Sipex's driver architecture allow the SP3223/
SP3243 series to deliver compliant RS-232 performance from a single power supply ranging
from +3.3V to +5.0V. The SP3223 is a 2-driver/2-receiver device, and the SP3243 is a
3-driver/5-receiver device ideal for laptop/notebook computer and PDA applications.
The SP3243 includes one complementary receiver that remains alert to monitor an external
device's Ring Indicate signal while the device is shutdown.
The AUTO ON-LINE® feature allows the device to automatically "wake-up" during a shutdown
state when an RS-232 cable is connected and a connected peripheral is turned on. Otherwise,
the device automatically shuts itself down drawing less than 1µA.
■ Meets true EIA/TIA-232-F Standards
from a +3.0V to +5.5V power supply
■ Interoperable with EIA/TIA-232 and
adheres to EIA/TIA-562 down to a +2.7V
power source
■ AUTO ON-LINE® circuitry automatically
wakes up from a 1µA shutdown
■ Minimum 120Kbps data rate under load
■ Regulated Charge Pump Yields Stable
RS-232 Outputs Regardless of VCC
Variations
■ ESD Specifications:
+2kV Human Body Model
DESCRIPTION
SELECTION TABLE
Applicable U.S. Patents - 5,306,954; and other patents pending.
eciveDseilppuSrewoP232-SR srevirD 232-SR srevieceR lanretxE stnenopmoC ENIL-NOOTUA
®
yrtiucriC etatS-3LTTfo.oN sniP
3223PSV5.5+otV0.3+22sroticapac4SEYSEY02
3423PSV5.5+otV0.3+35sroticapac4SEYSEY82
®
Rev. 6/30/03 SP3223 +3.0V to +5.5V RS-232 Transceivers © Copyright 2003 Sipex Corporation
2
NOTE 1: V+ and V- can have maximum magnitudes of 7V, but their absolute difference cannot exceed 13V.
ABSOLUTE MAXIMUM RATINGS
These are stress ratings only and functional operation
of the device at these ratings or any other above those
indicated in the operation sections of the specifications
below is not implied. Exposure to absolute maximum
rating conditions for extended periods of time may
affect reliability and cause permanent damage to the
device.
VCC.......................................................-0.3V to +6.0V
V+ (NOTE 1).......................................-0.3V to +7.0V
V- (NOTE 1)........................................+0.3V to -7.0V
V+ + |V-| (NOTE 1)...........................................+13V
ICC (DC VCC or GND current).........................+100mA
Input Voltages
TxIN, ONLINE,
SHUTDOWN, EN (SP3223).................-0.3V to +6.0V
RxIN...................................................................+15V
Output Voltages
TxOUT...............................................................+15V
RxOUT, STATUS.......................-0.3V to (VCC + 0.3V)
Short-Circuit Duration
TxOUT.....................................................Continuous
Storage Temperature......................-65°C to +150°C
Unless otherwise noted, the following specifications apply for VCC = +3.0V to +5.5V with TAMB = TMIN to TMAX.
Typical values apply at VCC = +3.3V or +5.0V and TAMB = 25°C.
SPECIFICATIONS
RETEMARAP.NIM.PYT.XAMSTINUSNOITIDNOC
SCITSIRETCARAHCCD
,tnerruCylppuS ENIL-NOOTUA
®
0.101µA,DNG=ENILNO,nepoNIxRllA V=NWODTUHS
CC
V=NIxT,
CC
ro
V,DNG
CC
T,V3.3+=
BMA
C°52+=
nwodtuhS,tnerruCylppuS0.101µAV=NIxT,DNG=NWODTUHS
CC
ro
V,DNG
CC
T,V3.3+=
BMA
C°52+=
,tnerruCylppuS ENIL-NOOTUA
®
delbasiD 3.00.1AmV=NWODTUHS=ENILNO
CC
,
V,daolon
CC
T,V3.3+=
BMA
C°52+=
STUPTUOREVIECERDNASTUPNICIGOL
dlohserhTcigoLtupnI WOL HGIH0.2 8.0 VV
CC
NIxT,V0.5+roV3.3+=,
(NE 3223PS ,ENILNO,)
NWODTUHS
tnerruCegakaeLtupnI10.0±0.1± µA,NWODTUHS,ENILNO,NE,NIxT
T
BMA
C°52+=
tnerruCegakaeLtuptuO50.0±01± µAdelbasidsrevieceR
WOLegatloVtuptuO4.0VI
TUO
Am6.1=
HGIHegatloVtuptuOV
CC
6.0-V
CC
1.0-VI
TUO
Am0.1-=
Power Dissipation per package
28-pin PDIP (derate 16.0mW/oC above+70oC).....1300mW
20-pin SSOP (derate 9.25mW/oC above +70oC)....750mW
20-pin TSSOP (derate 11.1mW/oC above +70oC)..900mW
28-pin SOIC (derate 12.7mW/oC above +70oC)...1000mW
28-pin SSOP (derate 11.2mW/oC above +70oC)....900mW
3
Rev. 6/30/03 SP3223 +3.0V to +5.5V RS-232 Transceivers © Copyright 2003 Sipex Corporation
RETEMARAP.NIM.PYT.XAMSTINUSNOITIDNOC
STUPTUOREVIRD
gniwSegatloVtuptuO0.5±4.5±V K3htiwdedaolstuptuorevirdllA Ω
T,DNGot
BMA
C°52+=
ecnatsiseRtuptuO003 ΩV
CC
V,V0=-V=+V=
TUO
V2±=
tnerruCtiucriC-trohStuptuO53± 07± 06± 001± Am V
TUO
V0=
V
TUO
=V51±
tnerruCegakaeLtuptuO52± µAV
CC
,V5.5otV0.3roV0=
V
TUO
delbasidsrevirD,V21±=
STUPNIREVIECER
egnaRegatloVtupnI51-51V
WOLdlohserhTtupnI6.02.1VV
CC
V3.3=
WOLdlohserhTtupnI8.05.1VV
CC
V0.5=
HGIHdlohserhTtupnI5.14.2VV
CC
V3.3=
HGIHdlohserhTtupnI8.14.2VV
CC
V0.5=
siseretsyHtupnI3.0V
ecnatsiseRtupnI357kΩ
ENIL-NOOTUA
®
V=NWODTUHS,DNG=ENILNO(SCITSIRETCARAHCYRTIUCRIC
CC
)
WOLegatloVtuptuOSUTATS4.0VI
TUO
Am6.1=
HGIHegatloVtuptuOSUTATSV
CC
6.0-VI
TUO
Am0.1-=
srevirDotdlohserhTrevieceR t(delbanE
ENILNO
)002 µS51erugiF
evitageNroevitisoPrevieceR HGIHSUTATSotdlohserhT
t(
HSTS
)
5.0 µS51erugiF
evitageNroevitisoPrevieceR WOLSUTATSotdlohserhT
t(
LSTS
)
02 µS51erugiF
SPECIFICATIONS (continued)
Unless otherwise noted, the following specifications apply for VCC = +3.0V to +5.5V with TAMB = TMIN to TMAX.
Typical values apply at VCC = +3.3V or +5.0V and TAMB = 25°C.
Rev. 6/30/03 SP3223 +3.0V to +5.5V RS-232 Transceivers © Copyright 2003 Sipex Corporation
4
SPECIFICATIONS (continued)
Unless otherwise noted, the following specifications apply for VCC = +3.0V to +5.5V with TAMB = TMIN to TMAX.
Typical values apply at VCC = +3.3V or +5.0V and TAMB = 25°C.
Figure 1. Transmitter Output Voltage VS. Load
Capacitance for the SP3223 Figure 2. Slew Rate VS. Load Capacitance for the
SP3223
TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise noted, the following performance characteristics apply for VCC = +3.3V, 120Kbps data rate, all drivers
loaded with 3KΩ, 0.1µF charge pump capacitors, and TAMB = +25°C.
6
4
2
0
-2
-4
-6
Transmitter Output Voltage [V]
Load Capacitance [pF]
Vout+
Vout-
500 1000 1500
0
14
12
10
8
6
4
2
0
Slew Rate [V/µs]
Load Capacitance [pF]
+Slew
-Slew
0 500 1000 1500 2000
RETEMARAP.NIM.PYT.XAMSTINUSNOITIDNOC
SCITSIRETCARAHCGNIMIT
etaRataDmumixaM021532spbkR
L
K3= ΩC,
L
evitcarevirdeno,Fp0001=
yaleDnoitagaporPrevieceR t
LHP
t
HLP
3.0 3.0 µsC,tuptuorevieceRottupnirevieceR
L
Fp051=
emiTelbanEtuptuOrevieceR002snnoitarepolamroN
emiTelbasiDtuptuOrevieceR002snnoitarepolamroN
wekSrevirD001005snt|
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52=
o
C
wekSrevieceR0020001snt|
LHP
t-
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etaRwelSnoigeR-noitisnarT03/VµsV
CC
R,V3.3=
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o
,C roV0.3+otV0.3-morfnekatstnemerusaem V0.3-otV0.3+
5
Rev. 6/30/03 SP3223 +3.0V to +5.5V RS-232 Transceivers © Copyright 2003 Sipex Corporation
Figure 3. Supply Current VS. Load Capacitance when
Transmitting Data for the SP3223 Figure 4. Transmitter Output Voltage VS. Load
Capacitance for the SP3243
Figure 5. Slew Rate VS. Load Capacitance for the
SP3243 Figure 6. Supply Current VS. Load Capacitance when
Transmitting Data for the SP3243
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise noted, the following performance characteristics apply for VCC = +3.3V, 120Kbps data rate, all drivers
loaded with 3KΩ, 0.1µF charge pump capacitors, and TAMB = +25°C.
40
35
30
25
20
15
10
5
0
Supply Current [mA]
Load Capacitance [pF]
118KHz
60KHz
10KHz
0 500 1000 1500 2000
6
4
2
0
-2
-4
-6
Transmitter Output Voltage [V]
Load Capacitance [pF]
Vout+
Vout-
500 1000 1500 2000 2500
0
16
14
12
10
8
6
4
2
0
Slew Rate [V/µs]
Load Capacitance [pF]
0500 1000 1500 2000 2500 3000
+ Slew
- Slew
80
70
60
50
40
30
20
10
0
Supply Current [mA]
Load Capacitance [pF]
0500 1000 1500 2000 2500
118KHz
60KHz
10KHz
3000
Rev. 6/30/03 SP3223 +3.0V to +5.5V RS-232 Transceivers © Copyright 2003 Sipex Corporation
6
Table 1. Device Pin Description
EMANNOITCNUF REBMUNNIP
3223PS3423PS
NE HGIHcigolylppA.noitarepolamronrofWOLcigolylppA.elbanErevieceR .)etatsZ-hgih(stuptuoreviecerehtelbasidot 1-
+1C .roticapacpmup-egrahcrelbuodegatlovehtfolanimretevitisoP 282
+V.pmupegrahcehtybdetarenegtuptuoV5.5+detalugeR 372
-1C .roticapacpmup-egrahcrelbuodegatlovehtfolanimretevitageN 442
+2C.roticapacpmup-egrahcgnitrevniehtfolanimretevitisoP 51
-2C.roticapacpmup-egrahcgnitrevniehtfolanimretevitageN 62
-V.pmupegrahcehtybdetarenegtuptuoV5.5-detalugeR 73
R
1
NI.tupnireviecer232-SR 614
R
2
NI.tupnireviecer232-SR 95
R
3
NI.tupnireviecer232-SR -6
R
4
NI.tupnireviecer232-SR -7
R
5
NI.tupnireviecer232-SR -8
R
1
TUO.tuptuoreviecerSOMC/LTT 5191
R
2
TUO.tuptuoreviecerSOMC/LTT 0181
R
2
TUO.nwodtuhsnievitca,tuptuo2-reviecergnitrevni-noN -02
R
3
TUO.tuptuoreviecerSOMC/LTT -71
R
4
TUO.tuptuoreviecerSOMC/LTT -61
R
5
TUO.tuptuoreviecerSOMC/LTT -51
SUTATS.sutatsnwodtuhsdnaenilnognitacidnituptuOSOMC/LTT 1112
T
1
NI.tupnirevirdSOMC/LTT 3141
T
2
NI.tupnirevirdSOMC/LTT 2131
T
3
NI.tupnirevirdSOMC/LTT -21
ENILNO edirrevootHGIHcigolylppA
ENIL-NOOTUA
srevirdgnipeekyrtiucric .)2elbaTotrefer,HGIHcigoleboslatsumNWODTUHS(evitca 4132
T
1
TUO.tuptuorevird232-SR 719
T
2
TUO.tuptuorevird232-SR 801
T
3
TUO.tuptuorevird232-SR -11
DNG.dnuorG 8152
V
CC
.egatlovylppusV5.5+otV0.3+ 9162
NWODTUHS llasedirrevosihT.pmupegrahcdnasrevirdnwodtuhsotWOLcigolylppA ENIL-NOOTUA
®
.)2elbaTotrefer(ENILNOdnayrtiucric 0222
7
Rev. 6/30/03 SP3223 +3.0V to +5.5V RS-232 Transceivers © Copyright 2003 Sipex Corporation
Figure 8. SP3243 Pinout Configuration
Figure 7. SP3223 Pinout Configuration
V-
1
2
3
417
18
19
20
5
6
7
16
15
14
SHUTDOWN
C1+
V+
C1-
C2+
C2-
ONLINE
EN
R
1
IN
GND
V
CC
T
1
OUT
STATUS
8
9
10 11
12
13
R
2
IN
R
2
OUT
SP3223
T
2
OUT T
1
IN
T
2
IN
R
1
OUT
R4IN
1
2
3
425
26
27
28
5
6
7
24
23
22 SHUTDOWN
C2-
V-
R1IN
R2IN
R3IN ONLINE
C2+
C1-
GND
VCC
V+
STATUS
T1IN
8
9
10
11 18
19
20
21
12
13
14
17
16
15 R5OUT
T1OUT
T2OUT
T3OUT
T3IN
T2IN R4OUT
R5IN
R3OUT
R2OUT
R1OUT
R2OUT
SP3243
C1+
Rev. 6/30/03 SP3223 +3.0V to +5.5V RS-232 Transceivers © Copyright 2003 Sipex Corporation
8
Figure 9. SP3223 Typical Operating Circuit
SP3223
2
4
6
5
3
7
19
GND
T
1
IN
T
2
IN
C1+
C1-
C2+
C2-
V+
V-
V
CC
13
12
0.1µF
0.1µF
0.1µF
+
C2
C5
C1
+
+C3
C4
+
+
0.1µF
0.1µF
17
8RS-232
OUTPUTS
RS-232
INPUTS
TTL/CMOS
INPUTS
+3V to +5V
18
SHUTDOWN
20
5KΩ
R
1
OUT
15 16
5KΩ
R
2
IN
R
2
OUT
10 9
TTL/CMOS
OUTPUTS
EN
1
ONLINE
14
R
1
IN
T
2
OUT
T
1
OUT
11 STATUS
V
CC
To µP Supervisor
Circuit
9
Rev. 6/30/03 SP3223 +3.0V to +5.5V RS-232 Transceivers © Copyright 2003 Sipex Corporation
Figure 10. SP3243 Typical Operating Circuit
SP3243
28
24
2
1
27
3
26
5KΩ
5KΩ
5KΩ
5KΩ
5KΩ
GND
C1+
C1-
C2+
C2-
V+
V-
V
CC
14
13
12
20
19
18
17
16
15
0.1µF
0.1µF
0.1µF
+
C2
C5
C1
+
+C3
C4
+
+
0.1µF
0.1µF
9
10
11
4
5
6
7
8
RS-232
OUTPUTS
RS-232
INPUTS
TTL/CMOS
INPUTS
TTL/CMOS
OUTPUTS
To µP Supervisor
Circuit
23
22
21
V
CC
V
CC
25
T
1
IN
R
1
OUT R
1
IN
T
2
OUT
R
2
OUT
T
2
IN
T
3
IN T
3
OUT
T
1
OUT
R
2
IN
R
3
IN
R
4
IN
R
5
IN
R
2
OUT
R
3
OUT
R
4
OUT
R
5
OUT
ONLINE
SHUTDOWN
STATUS
Rev. 6/30/03 SP3223 +3.0V to +5.5V RS-232 Transceivers © Copyright 2003 Sipex Corporation
10
DESCRIPTION
The SP3223 and SP3243 transceivers meet the
EIA/TIA-232 and ITU-T V.28/V.24 communica-
tion protocols and can be implemented in bat-
tery-powered, portable, or hand-held applica-
tions such as notebook or palmtop computers.
The SP3223 and SP3243 devices feature Sipex's
proprietary and patented (U.S.-- 5,306,954) on-
board charge pump circuitry that generates
±5.5V RS-232 voltage levels from a single +3.0V
to +5.5V power supply. The SP3223 and SP3243
devices can operate at
a typical data rate of 235kbps fully loaded.
The SP3223 is a 2-driver/2-receiver device, and
the SP3243 is a 3-driver/5-receiver device
ideal for portable or hand-held applications.
The SP3243 includes one complementary
always-active receiver that can monitor an
external device (such as a modem) in shutdown.
This aids in protecting the UART or serial
controller IC by preventing forward biasing
of the protection diodes where VCC may be
disconnected.
The SP3223 and SP3243 series is an ideal choice
for power sensitive designs. The SP3223 and
SP3243 devices feature AUTO ON-LINE®
circuitry which reduces the power supply drain
to a 1µA supply current. In many portable or
hand-held applications, an RS-232 cable can be
disconnected or a connected peripheral can be
turned off. Under these conditions, the internal
charge pump and the drivers will be shut down.
Otherwise, the system automatically comes
online. This feature allows design engineers to
address power saving concerns without major
design changes.
THEORY OF OPERATION
The SP3223 and SP3243 series is made up
of four basic circuit blocks:
1. Drivers, 2. Receivers, 3. the Sipex proprietary
charge pump, and 4. AUTO ON-LINE® cir-
cuitry.
Drivers
The drivers are inverting level transmitters that
convert TTL or CMOS logic levels to 5.0V EIA/
TIA-232 levels with an inverted sense relative to
the input logic levels. Typically, the RS-232
output voltage swing is +5.4V with no load and
+5V minimum fully loaded. The driver outputs
are protected against infinite short-circuits to
ground without degradation in reliability. These
drivers comply with the EIA-TIA-232F and all
previous RS-232 versions. Unused driver inputs
should be connected to GND or VCC.
The drivers can guarantee a data rate of 120Kbps
fully loaded with 3KΩ in parallel with 1000pF,
ensuring compatibility with PC-to-PC commu-
nication software.
The slew rate of the driver output is internally
limited to a maximum of 30V/µs in order to
meet the EIA standards (EIA RS-232D 2.1.7,
Paragraph 5). The transition of the loaded
output from HIGH to LOW also meets the
monotonicity requirements of the standard.
Figure 11. Interface Circuitry Controlled by Micropro-
cessor Supervisory Circuit
SP3243
28
24
2
1
27
3
26
5KΩ
5KΩ
5KΩ
5KΩ
5KΩ
GND
C1+
C1-
C2+
C2-
V+
V-
VCC
14
13
12
20
19
18
17
16
15
0.1µF
0.1µF
0.1µF
+
C2
C5
C1
+
+C3
C4
+
+
0.1µF
0.1µF
9
10
11
4
5
6
7
8
RS-232
OUTPUTS
RS-232
INPUTS
23
22
21
VCC
25
T
1
IN
R
1
OUT R
1
IN
T
2
OUT
R
2
OUT
T
2
IN
T
3
IN T
3
OUT
T
1
OUT
R
2
IN
R
3
IN
R
4
IN
R
5
IN
R
2
OUT
R
3
OUT
R
4
OUT
R
5
OUT
ONLINE
SHUTDOWN
STATUS
UART
or
Serial µC
µP
Supervisor
IC
TxD
RTS
DTR
RxD
CTS
DSR
DCD
RI
VCC
VIN
RESET
11
Rev. 6/30/03 SP3223 +3.0V to +5.5V RS-232 Transceivers © Copyright 2003 Sipex Corporation
Figure 12 shows a loopback test circuit used to
test the RS-232 Drivers. Figure 13 shows the test
results of the loopback circuit with all three
drivers active (SP3243) at 120Kbps with typical
RS-232 loads in parallel with 1000pF capacitors.
Figure 14 shows the test results where one driver
was active at 235Kbps and all three drivers
loaded with an RS-232 receiver in parallel with
a 1000pF capacitor. A solid RS-232 data trans-
Table 2. SHUTDOWN and EN Truth Tables
Note: In AUTO ON-LINE® Mode where ONLINE =
GND and SHUTDOWN = VCC, the device will shut down
if there is no activity present at the Receiver inputs.
Figure 12. Loopback Test Circuit for RS-232 Driver
Data Transmission Rates
mission rate of 120Kbps provides compatibility
with many designs in personal computer periph-
erals and LAN applications.
Receivers
The receivers convert ±5.0V EIA/TIA-232
levels to TTL or CMOS logic output levels.
Receivers have an inverting output that can be
disabled by using the EN pin.
Figure 13. Loopback Test Circuit Result at 120Kbps
(All Drivers Fully Loaded) Figure 14. Loopback Test Circuit result at 235Kbps
(All Drivers Fully Loaded)
SP3223
SP3243
2
4
6
5
3
7
19
GND
T1IN
TXIN
C1+
C1-
C2+
C2-
V+
V-
V
CC
0.1µF
0.1µF
0.1µF
+
C2
C5
C1
+
+C3
C4
+
+
0.1µF
0.1µF
TTL/CMOS
INPUTS
+3V to +5V
18
SHUTDOWN
20
5KΩ
R1OUT
5KΩ
RXIN
RXOUT
TTL/CMOS
OUTPUTS
EN
1
ONLINE
14
R1IN
TXOUT
T1OUT
11 STATUS
V
CC
To µP Supervisor
Circuit
1000pF 1000pF
3223PS:ECIVED
NWODTUHSNET
X
TUOR
X
TUO
00 ZhgiHevitcA
01 ZhgiHZhgiH
10 evitcAevitcA
11 evitcAZhgiH
3423PS:ECIVED
NWODTUHST
X
TUOR
X
TUOR
2
TUO
0ZhgiHZhgiHevitcA
1evitcAevitcAevitcA
T1 IN
T1 OUT
R1 OUT
T1 IN
T1 OUT
R1 OUT
Rev. 6/30/03 SP3223 +3.0V to +5.5V RS-232 Transceivers © Copyright 2003 Sipex Corporation
12
Receivers are active when the AUTO ON-LINE®
circuitry is enabled or when in shutdown.
During the shutdown, the receivers will continue
to be active. If there is no activity present at the
receivers for a period longer than 100µs or when
SHUTDOWN is enabled, the device goes into a
standby mode where the circuit draws 1µA.
Driving EN to a logic HIGH forces the outputs of
the receivers into high-impedance. The truth
table logic of the SP3223 and SP3243 driver and
receiver outputs can be found in Table 2.
The SP3243 includes an additional non-invert-
ing receiver with an output R2OUT. R2OUT is an
extra output that remains active and monitors
activity while the other receiver outputs are
forced into high impedance. This allows Ring
Indicator (RI) from a peripheral to be monitored
without forward biasing the TTL/CMOS inputs
of the other devices connected to the receiver
outputs.
Since receiver input is usually from a transmis-
sion line where long cable lengths and system
interference can degrade the signal, the inputs
have a typical hysteresis margin of 300mV. This
ensures that the receiver is virtually immune to
noisy transmission lines. Should an input be left
unconnected, an internal 5KΩ pulldown resistor
to ground will commit the output of the receiver
to a HIGH state.
Charge Pump
The charge pump is a Sipex–patented design
(U.S. 5,306,954) and uses a unique approach
compared to older less–efficient designs. The
charge pump still requires four external
capacitors, but uses a four–phase voltage
shifting technique to attain symmetrical 5.5V
power supplies. The internal power supply
consists of a regulated dual charge pump that
provides output voltages 5.5V regardless of the
input voltage (VCC) over the +3.0V to +5.5V
range. This is important to maintain compliant
RS-232 levels regardless of power supply
fluctuations.
The charge pump operates in a discontinuous
mode using an internal oscillator. If the output
voltages are less than a magnitude of 5.5V, the
charge pump is enabled. If the output voltages
exceed a magnitude of 5.5V, the charge pump is
disabled. This oscillator controls the four phases
of the voltage shifting. A description of each
phase follows.
Phase 1
— VSS charge storage — During this phase of
the clock cycle, the positive side of capacitors
C1 and C2 are initially charged to VCC. Cl+ is
then switched to GND and the charge in C1– is
transferred to C2–. Since C2+ is connected to
VCC, the voltage potential across capacitor C2 is
now 2 times VCC.
Phase 2
— VSS transfer — Phase two of the clock
connects the negative terminal of C2 to the VSS
storage capacitor and the positive terminal of C2
to GND. This transfers a negative generated
voltage to C3. This generated voltage is
regulated to a minimum voltage of -5.5V.
Simultaneous with the transfer of the voltage to
C3, the positive side of capacitor C1 is switched
to VCC and the negative side is connected to
GND.
Phase 3
— VDD charge storage — The third phase of the
clock is identical to the first phase — the charge
transferred in C1 produces –VCC in the negative
terminal of C1, which is applied to the negative
side of capacitor C2. Since C2+ is at VCC, the
voltage potential across C2 is 2 times VCC.
Phase 4
— VDD transfer — The fourth phase of the clock
connects the negative terminal of C2 to GND,
and transfers this positive generated voltage
across C2 to C4, the VDD storage capacitor. This
voltage is regulated to +5.5V. At this voltage,
the internal oscillator is disabled. Simultaneous
with the transfer of the voltage to C4, the
positive side of capacitor C1 is switched to VCC
and the negative side is connected to GND,
allowing the charge pump cycle to begin again.
The charge pump cycle will continue as long as
the operational conditions for the internal
oscillator are present.
13
Rev. 6/30/03 SP3223 +3.0V to +5.5V RS-232 Transceivers © Copyright 2003 Sipex Corporation
Since both V+ and V– are separately generated
from VCC, in a no–load condition V+ and V– will
be symmetrical. Older charge pump approaches
that generate V– from V+ will show a decrease in
the magnitude of V– compared to V+ due to the
inherent inefficiencies in the design.
Figure 15. AUTO ON-LINE® Timing Waveforms
RECEIVER
RS-232 INPUT
VOLTAGES
STATUS
+5V
0V
-5V
t
STSL
t
STSH
t
ONLINE
V
CC
0V
DRIVER
RS-232 OUTPUT
VOLTAGES
0V
+2.7V
-2.7V
S
H
U
T
D
O
W
N
The clock rate for the charge pump typically
operates at 250kHz. The external capacitors can
be as low as 0.1µF with a 16V breakdown
voltage rating.
Rev. 6/30/03 SP3223 +3.0V to +5.5V RS-232 Transceivers © Copyright 2003 Sipex Corporation
14
Figure 17. Charge Pump — Phase 2
Figure 18. Charge Pump Waveforms
V
CC
= +5V
–10V
V
SS
Storage Capacitor
V
DD
Storage Capacitor
C
1
C
2
C
3
C
4
+
+
++
–
–
––
Figure 19. Charge Pump — Phase 3
V
CC
= +5V
–5V
+5V
–5V
V
SS
Storage Capacitor
V
DD
Storage Capacitor
C
1
C
2
C
3
C
4
+
+
++
–
–
––
Figure 20. Charge Pump — Phase 4
V
CC
= +5V
+10V
V
SS
Storage Capacitor
V
DD
Storage Capacitor
C
1
C
2
C
3
C
4
+
+
++
–
–
––
VCC = +5V
–5V –5V
+5V
VSS Storage Capacitor
VDD Storage Capacitor
C1C2
C3
C4
+
+
++
–
–
––
Figure 16. Charge Pump — Phase 1
Ch1 2.00V Ch2 2.00V M 1.00µs Ch1 1.96V
2
1T
T[]
T
2
+6V
a) C2+
b) C2-
-6V
0V
0V
15
Rev. 6/30/03 SP3223 +3.0V to +5.5V RS-232 Transceivers © Copyright 2003 Sipex Corporation
Figure 21. SP3243 Driver Output Voltages vs. Load
Current per Transmitter
Figure 22. Circuit for the connectivity of the SP3243 with a DB-9 connector
6
4
2
0
-2
-4
-6
Transmitter Output Voltage [V]
Load Current Per Transmitter [mA]
Vout+
Vout-
0.62
0.869
0.939
1.02
1.12
1.23
1.38
1.57
1.82
2.67
3.46
4.93
8.6
6
7
8
9
1
2
3
4
5
DB-9
Connector
6. DCE Ready
7. Request to Send
8. Clear to Send
9. Ring Indicator
DB-9 Connector Pins:
1. Received Line Signal Detector
2. Received Data
3. Transmitted Data
4. Data Terminal Ready
5. Signal Ground (Common)
SP3243
28
24
2
1
27
3
26
5KΩ
5KΩ
5KΩ
5KΩ
5KΩ
GND
C1+
C1-
C2+
C2-
V+
V-
V
CC
14
13
12
20
19
18
17
16
15
0.1µF
0.1µF
0.1µF
+
C2
C5
C1
+
+C3
C4
+
+
0.1µF
0.1µF
9
10
11
4
5
6
7
8
To µP Supervisor
Circuit
23
22
21
V
CC
V
CC
25
T
1
IN
R
1
OUT R
1
IN
T
2
OUT
R
2
OUT
T
2
IN
T
3
IN T
3
OUT
T
1
OUT
R
2
IN
R
3
IN
R
4
IN
R
5
IN
R
2
OUT
R
3
OUT
R
4
OUT
R
5
OUT
ONLINE
SHUTDOWN
STATUS
Rev. 6/30/03 SP3223 +3.0V to +5.5V RS-232 Transceivers © Copyright 2003 Sipex Corporation
16
Table 3. AUTO ON-LINE® Logic
Figure 23. Stage I of AUTO ON-LINE® Circuitry
Figure 24. Stage II of AUTO ON-LINE® Circuitry
LANGIS232-SR REVIECERTA TUPNI
NWODTUHS TUPNI TUPNIENILNOTUPTUOSUTATS REVIECSNART SUTATS
SEYHGIHWOLHGIH
noitarepOlamroN ENIL-NOOTUA(
®
)
ONHGIHHGIHWOL
noitarepOlamroN
ONHGIHWOLWOL
nwodtuhS ENIL-NOOTUA(
®
)
SEYWOLWOL/HGIHHGIH
nwodtuhS
ONWOLWOL/HGIHWOL
nwodtuhS
RS-232
Receiver Block
RXINACT
Inactive Detection Block
RXIN RXOUT
R
1
INACT R
2
INACT R
3
INACT R
4
INACT R
5
INACT
Delay
Stage Delay
Stage Delay
Stage Delay
Stage Delay
Stage
SHUTDOWN
STATUS
17
Rev. 6/30/03 SP3223 +3.0V to +5.5V RS-232 Transceivers © Copyright 2003 Sipex Corporation
AUTO ON-LINE® Circuitry
The SP3223 and SP3243 devices have a patent
pending AUTO ON-LINE® circuitry on board
that saves power in applications such as laptop
computers, palmtop (PDA) computers, and other
portable systems.
The SP3223 and SP3243 devices incorporate an
AUTO ON-LINE® circuit that automatically
enables itself when the external transmitters are
enabled and the cable is connected. Conversely,
the AUTO ON-LINE® circuit also disables
most of the internal circuitry when the device is
not being used and goes into a standby mode
where the device typically draws 1µA. This
function can also be externally controlled by the
ONLINE pin. When this pin is tied to a logic
LOW, the AUTO ON-LINE® function is active.
Once active, the device is enabled until there is
no activity on the receiver inputs. The receiver
input typically sees at least ±3V, which are
generated from the transmitters at the other end
of the cable with a ±5V minimum. When the
external transmitters are disabled or the cable is
disconnected, the receiver inputs will be pulled
down by their internal 5kΩ resistors to ground.
When this occurs over a period of time, the
internal transmitters will be disabled and the
device goes into a shutdown or standy mode.
When ONLINE is HIGH, the AUTO ON-LINE®
mode is disabled.
The AUTO ON-LINE® circuit has two stages:
1) Inactive Detection
2) Accumulated Delay
The first stage, shown in Figure 23, detects an
inactive input. A logic HIGH is asserted on
RXINACT if the cable is disconnected or the
external transmitters are disabled. Otherwise,
RXINACT will be at a logic LOW. This circuit
is duplicated for each of the other receivers.
The second stage of the AUTO ON-LINE®
circuitry, shown in Figure 24, processes all the
receiver's RXINACT signals with an accumu-
lated delay that disables the device to a 1µA
supply current.
The STATUS pin goes to a logic LOW when the
cable is disconnected, the external transmitters
are disabled, or the SHUTDOWN pin is
invoked. The typical accumulated delay is
around 20µs.
When the SP3223 and SP3243 drivers or inter-
nal charge pump are disabled, the supply current
is reduced to 1µA. This can commonly occur in
hand-held or portable applications where the
RS-232 cable is disconnected or the RS-232
drivers of the connected peripheral are turned off.
The AUTO ON-LINE ® mode can be disabled
by the SHUTDOWN pin. If this pin is a logic
LOW,the AUTO ON-LINE® function will not
operate regardless of the logic state of the
ONLINE pin. Table 3 summarizes the logic of the
AUTO ON-LINE® operating modes. The truth
table logic of the SP3223 and SP3243 driver and
receiver outputs can be found in Table 2.
The STATUS pin outputs a logic LOW signal
if the device is shutdown. This pin goes to a
logic HIGH when the external transmitters are
enabled and the cable is connected.
When the SP3223 and SP3243 devices
are shut down, the charge pumps are turned off.
V+ charge pump output decays to VCC, the
V- output decays to GND. The decay time will
depend on the size of capacitors used for the
charge pump. Once in shutdown, the time
required to exit the shut down state and have
valid V+ and V- levels is typically 200µs.
For easy programming, the STATUS can be
used to indicate DTR or a Ring Indicator signal.
Tying ONLINE and SHUTDOWN together
will bypass the AUTO ON-LINE® circuitry so
this connection acts like a shutdown input pin.
Rev. 6/30/03 SP3223 +3.0V to +5.5V RS-232 Transceivers © Copyright 2003 Sipex Corporation
18
ESD TOLERANCE
The SP3223/3243 series incorporates
ruggedized ESD cells on all driver output and
receiver input pins. The ESD structure is
improved over our previous family for more
rugged applications and environments sensitive
to electro-static discharges and associated
transients.
The Human Body Model has been the generally
accepted ESD testing method for semiconductors.
This method is also specified in MIL-STD-883,
Method 3015.7 for ESD testing. The premise of
this ESD test is to simulate the human body’s
potential to store electro-static energy and
discharge it to an integrated circuit. The
simulation is performed by using a test model as
shown in Figure 25. This method will test the
IC’s capability to withstand an ESD transient
during normal handling such as in manufacturing
areas where the ICs tend to be handled frequently.
For the Human Body Model, the current limiting
resistor (RS) and the source capacitor (CS) are
1.5kΩ and 100pF, respectively.
R
C
C
S
R
S
SW1 SW2
R
C
Device
Under
Test
DC Power
Source
C
S
R
S
SW1 SW2
Figure 25. ESD Test Circuit for Human Body Model
19
Rev. 6/30/03 SP3223 +3.0V to +5.5V RS-232 Transceivers © Copyright 2003 Sipex Corporation
D
ALTERNATE
END PINS
(BOTH ENDS)
D1 = 0.005" min.
(0.127 min.)
E
PACKAGE: PLASTIC
DUAL–IN–LINE
(NARROW)
DIMENSIONS (Inches)
Minimum/Maximum
(mm)
A = 0.210" max.
(5.334 max).
E1
C
Ø
LA2
A1 = 0.015" min.
(0.381min.)
B
B1
e = 0.100 BSC
(2.540 BSC) eA = 0.300 BSC
(7.620 BSC)
A2
B
B1
C
D
E
E1
L
Ø
16–PIN
0.115/0.195
(2.921/4.953)
0.014/0.022
(0.356/0.559)
0.045/0.070
(1.143/1.778)
0.008/0.014
(0.203/0.356)
0.780/0.800
(19.812/20.320)
0.300/0.325
(7.620/8.255)
0.240/0.280
(6.096/7.112)
0.115/0.150
(2.921/3.810)
0°/ 15°
(0°/15°)
20–PIN
0.115/0.195
(2.921/4.953)
0.014/0.022
(0.356/0.559)
0.045/0.070
(1.143/1.778)
0.008/0.014
(0.203/0.356)
0.980/1.060
(24.892/26.924)
0.300/0.325
(7.620/8.255)
0.240/0.280
(6.096/7.112)
0.115/0.150
(2.921/3.810)
0°/ 15°
(0°/15°)
28–PIN
0.068/0.078
(1.73/1.99)
0.002/0.008
(0.05/0.21)
0.010/0.015
(0.25/0.38)
0.397/0.407
(10.07/10.33)
0.205/0.212
(5.20/5.38)
0.0256 BSC
(0.65 BSC)
0.301/0.311
(7.65/7.90)
0.022/0.037
(0.55/0.95)
0°/8°
(0°/8°)
Rev. 6/30/03 SP3223 +3.0V to +5.5V RS-232 Transceivers © Copyright 2003 Sipex Corporation
20
D
EH
PACKAGE: PLASTIC SHRINK
SMALL OUTLINE
(SSOP)
DIMENSIONS (Inches)
Minimum/Maximum
(mm) 20–PIN
A
A1
Ø
L
Be
A
A1
B
D
E
e
H
L
Ø
0.068/0.078
(1.73/1.99)
0.002/0.008
(0.05/0.21)
0.010/0.015
(0.25/0.38)
0.278/0.289
(7.07/7.33)
0.205/0.212
(5.20/5.38)
0.0256 BSC
(0.65 BSC)
0.301/0.311
(7.65/7.90)
0.022/0.037
(0.55/0.95)
0°/8°
(0°/8°)
24–PIN
0.068/0.078
(1.73/1.99)
0.002/0.008
(0.05/0.21)
0.010/0.015
(0.25/0.38)
0.317/0.328
(8.07/8.33)
0.205/0.212
(5.20/5.38)
0.0256 BSC
(0.65 BSC)
0.301/0.311
(7.65/7.90)
0.022/0.037
(0.55/0.95)
0°/8°
(0°/8°)
28–PIN
0.068/0.078
(1.73/1.99)
0.002/0.008
(0.05/0.21)
0.010/0.015
(0.25/0.38)
0.397/0.407
(10.07/10.33)
0.205/0.212
(5.20/5.38)
0.0256 BSC
(0.65 BSC)
0.301/0.311
(7.65/7.90)
0.022/0.037
(0.55/0.95)
0°/8°
(0°/8°)
16–PIN
0.068/0.078
(1.73/1.99)
0.002/0.008
(0.05/0.21)
0.010/0.015
(0.25/0.38)
0.239/0.249
(6.07/6.33)
0.205/0.212
(5.20/5.38)
0.0256 BSC
(0.65 BSC)
0.301/0.311
(7.65/7.90)
0.022/0.037
(0.55/0.95)
0°/8°
(0°/8°)
21
Rev. 6/30/03 SP3223 +3.0V to +5.5V RS-232 Transceivers © Copyright 2003 Sipex Corporation
D
EH
PACKAGE: PLASTIC
SMALL OUTLINE (SOIC)
(WIDE)
DIMENSIONS (Inches)
Minimum/Maximum
(mm)
A
A1
Ø
L
Be
A
A1
B
D
E
e
H
L
Ø
28–PIN
0.093/0.104
(2.352/2.649)
0.004/0.012
(0.102/0.300)
0.013/0.020
(0.330/0.508)
0.697/0.713
(17.70/18.09)
0.291/0.299
(7.402/7.600)
0.050 BSC
(1.270 BSC)
0.394/0.419
(10.00/10.64)
0.016/0.050
(0.406/1.270)
0°/8°
(0°/8°)
Rev. 6/30/03 SP3223 +3.0V to +5.5V RS-232 Transceivers © Copyright 2003 Sipex Corporation
22
PACKAGE: PLASTIC THIN SMALL
OUTLINE
(TSSOP)
DIMENSIONS
in inches (mm)
Minimum/Maximum
A
A1
Ø
L
Be
A
A1
B
D
E
e
E2
L
Ø
E2
D
- /0.043
(- /1.10)
0.002/0.006
(0.05/0.15)
0.007/0.012
(0.19/0.30)
0.252/0.260
(6.40/6.60)
0.169/0.177
(4.30/4.50)
0.026 BSC
(0.65 BSC)
0.126 BSC
(3.20 BSC)
0.020/0.030
(0.50/0.75)
0°/8°
20–PIN
E
23
Rev. 6/30/03 SP3223 +3.0V to +5.5V RS-232 Transceivers © Copyright 2003 Sipex Corporation
Model Temperature Range Package Types
SP3223CP 0°C to +70°C20-pin PDIP
SP3223CA 0°C to +70°C20-pin SSOP
SP3223CY 0ºC to +70ºC 20-pin TSSOP
SP3223EP -40°C to +85°C20-pin PDIP
SP3223EA -40°C to +85°C20-pin SSOP
SP3223EY -40°C to +85°C20-pin TSSOP
SP3243CT 0°C to +70°C28-pin Wide SOIC
SP3243CA 0°C to +70°C28-pin SSOP
SP3243ET -40°C to +85°C28-pin Wide SOIC
SP3243EA -40°C to +85°C28-pin SSOP
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ORDERING INFORMATION
Corporation
ANALOG EXCELLENCE
Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the
application or use of any product or circuit described hereing; neither does it convey any license under its patent rights nor the rights of others.
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Please consult the factory for pricing and availability on a Tape-On-Reel option.
Sipex Corporation
Headquarters and
Sales Office
233 South Hillview Drive
Milpitas, CA 95035
TEL: (408) 934-7500
FAX: (408) 935-7600
Sales Office
22 Linnell Circle
Billerica, MA 01821
TEL: (978) 667-8700
FAX: (978) 670-9001
e-mail: sales@sipex.com