LMZ10501 LMZ10501 1A SIMPLE SWITCHER(R) Nano Module with 5.5V Maximum Input Voltage Literature Number: SNVS677B LMZ10501 1A SIMPLE SWITCHER(R) Nano Module with 5.5V Maximum Input Voltage 8 Pin LLP-Footprint Package System Performance (Quick Overview Links: VOUT = 1.2V, 1.8V, 2.5V, 3.3V) Typical Efficiency at VIN = 3.6V 100 90 SE08A 8 Pin Package 3.0 x 2.5 x 1.2 mm (0.118 x 0.098 x 0.047 in) RoHS Compliant Electrical Specifications EFFICIENCY (%) 30124731 Up to 1A output current Input voltage range 2.7V to 5.5V Output voltage range 0.6V to 3.6V Efficiency up to 95% 80 70 60 50 30 20 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 LOAD CURRENT (A) Key Features 30124730 Integrated inductor Miniature form factor (3.0 mm x 2.5 mm x 1.2 mm) 8-pin LLP footprint -40C to 125C junction temperature range Adjustable output voltage 2.0MHz fixed PWM switching frequency Integrated compensation Soft start function Current limit protection Thermal shutdown protection Input voltage UVLO for power-up, power-down, and brown-out conditions Only 5 external components -- resistor divider and 3 ceramic capacitors Output Voltage Ripple VIN = 5.0V, VOUT = 1.8V, IOUT = 1A 30124733 Applications Performance Benefits Small solution size Low output voltage ripple Easy component selection and simple PCB layout High efficiency reduces system heat generation Radiated EMI (CISPR22) VIN = 5.0V, VOUT = 1.8V, IOUT = 1A 80 RADIATED EMISSIONS (dBV/m) Point of load conversions from 3.3V and 5V rails Space constrained applications Low output noise applications VOUT = 1.2V VOUT = 1.8V VOUT = 2.5V VOUT = 3.3V 40 Emissions (Evaluation Board) EN 55022 Class B Limit EN 55022 Class A Limit 70 60 50 40 30 20 10 0 0 200 400 600 800 FREQUENCY (MHz) 1000 30124732 (c) 2011 National Semiconductor Corporation 301247 www.national.com 1A SIMPLE SWITCHER(R) Nano Module with 5.5V Maximum Input Voltage October 5, 2011 LMZ10501 Connection Diagram 30124720 NS Package Number SE08A Order Information Order Number Package Marking (Note) Supplied As LMZ10501SEE XVS SP 250 units, Tape-and-Reel LMZ10501SE XVS SP 1000 units, Tape-and-Reel LMZ10501SEX XVS SP 3000 units, Tape-and-Reel Note: The actual physical placement of the package marking will vary from part to part. The package marking "X" designates the date code. "V" is a NSC internal code for die traceability. Both will vary in production. "S" designates device type as switcher and "SP" identifies the device (part number). Pin Descriptions Pin # Name 1 EN Enable Input. Set this digital input higher than 1.2V for normal operation. For shutdown, set low. Pin is internally pulled up to VIN and can be left floating for always-on operation. Description 2 VCON Output voltage control pin. Connect to analog voltage from resisitve divider or DAC/controller to set the VOUT voltage. VOUT = 2.5 x VCON. Connect a small (470pF) capacitor from this pin to SGND to provide noise filtering. 3 FB 4 SGND Ground for analog and control circuitry. Connect to PGND at a single point. 5 VOUT Output Voltage. Connected to one terminal of the integrated inductor. Connect output filter capacitor between VOUT and PGND. 6 PGND Power ground for the power MOSFETs and gate-drive circuitry. 7 VIN 8 VREF PAD www.national.com Feedback of the error amplifier. Connect directly to output capacitor to sense VOUT. Voltage supply input. Connect ceramic capacitor between VIN and PGND as close as possible to these two pins. Typical capacitor values are between 4.7F and 22F. 2.35V voltage reference output. Typically connected to VCON pin through a resistive divider to set the output voltage. The 3 pads underneath the module are not internally connected to any node. These pads should be connected to the ground plane for improved thermal performance. 2 Operating Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Input Voltage Range Recommended Load Current Junction Temperature (TJ) Range VIN, VREF to SGND PGND to SGND EN, FB, VCON VOUT Junction Temperature (TJ-MAX) Storage Temperature Range Maximum Lead Temperature ESD Susceptibility(Note 2) -0.2V to +6.0V -0.2V to +0.2V (SGND -0.2V) to (VIN +0.2V) w/6.0V max (PGND -0.2V) to (VIN +0.2V) w/6.0V max +150C -65C to +150C +260C 2kV (Note 1) 2.7V to 5.5V 0 mA to 1000 mA -40C to +125C Thermal Properties Junction-to-Ambient Thermal 120C/W Resistance (JA), SE08A Package (Note 3) Electrical Characteristics (Note 4) Specifications with standard typeface are for TJ = 25C only; Limits in bold face type apply over the operating junction temperature range TJ of -40C to 125C. Minimum and maximum limits are guaranteed through test, design, or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25C, and are provided for reference purposes only. Unless otherwise stated the following conditions apply: VIN = 3.6V, VEN = 1.2V. Symbol Parameter Conditions Min Typ (Note 4) (Note 5) Max (Note 4) Units SYSTEM PARAMETERS VREF x GAIN Reference voltage x VCON to VIN = VEN = 5.5V, VCON = 1.44V FB Gain 5.7575 5.875 5.9925 V GAIN VCON to FB Gain 2.4375 2.5 2.5750 V/V VINUVLO VIN rising threshold 2.4 V VINUVLO VIN falling theshold 2.25 V ISHDN Shutdown supply current VIN = 3.6V, VEN = 0.5V (Note 6) 11 18 A Iq DC bias current into VIN VIN = 5.5V, VCON = 1.6V, IOUT = 0A 6.5 8.5 mA RDROPOUT VIN to VOUTresistance IOUT = 200 mA 285 425 m I LIM DC Output Current Limit VCON = 0.24V (Note 7) FOSC VIH,ENABLE VIL,ENABLE Enable logic LOW voltage TSD Thermal shutdown TSD-HYST DMAX VIN = 5.5V, VCON = 1.44V 1125 1350 Internal oscillator frequency 1.75 2.0 Enable logic HIGH voltage 1.2 mA 2.25 V 0.5 Rising Threshold MHz V 150 C Thermal shutdown hysteresis 20 C Maximum duty cycle 100 % TON-MIN Minimum on-time 50 ns JA Package Thermal Resistance 20mm x 20mm board 2 layers, 2 oz copper, 0.5W, no airlow 118 15mm x 15mm board 2 layers, 2 oz copper, 0.5W, no airlow 132 10mm x 10mm board 2 layers, 2 oz copper, 0.5W, no airlow 157 3 C/W www.national.com LMZ10501 Absolute Maximum Ratings (Note 1) LMZ10501 System Characteristics The following specifications are guaranteed by design providing the component values in the Typical Application Circuit are used (CIN = COUT = 10 F, 6.3V, 0603, TDK C1608X5R0J106K). These parameters are not guaranteed by production testing. Unless otherwise stated the following conditions apply: TA = 25C. Symbol Parameter Conditions VOUT/VOUT Output Voltage Regulation Over VOUT = 0.6V Line Voltage and Load Current VIN =2.7V to 4.2V Min Typ Max Units 1.75 % 0.92 % 0.38 % EN = Low to High, VIN = 4.2V VOUT = 2.7V, IOUT = 1A 10 s VIN = 5.0V, VOUT = 3.3V IOUT = 200 mA 95 VIN = 5.0V, VOUT = 3.6V IOUT = 1000 mA 91 VIN = 5.0V, VOUT = 1.8V IOUT = 1000 mA (Note 8) 10 mV pk-pk Line transient response VIN = 2.7V to 5.5V, TR = TF= 10 s, VOUT = 1.8V, IOUT = 1000mA 30 mV pk-pk Load transient response VIN = 5.0V TR = TF = 40 s, VOUT = 1.8V IOUT = 100mA to 1000 mA 30 mV pk-pk IOUT = 0A to 1A VOUT/VOUT Output Voltage Regulation Over VOUT = 1.5V Line Voltage and Load Current VIN = 2.7V to 5.5V IOUT = 0A to 1A VOUT/VOUT Output Voltage Regulation Over VOUT = 3.6V Line Voltage and Load Current VIN = 4.0V to 5.5V IOUT = 0A to 1A VREF TRISE Rise time of reference voltage Peak Efficiency Full Load Efficiency VOUT Ripple Output voltage ripple Line Transient Load Transient www.national.com 4 % Note 2: The human body model is a 100pF capacitor discharged through a 1.5 k resistor into each pin. Test method is per JESD-22-114. Note 3: Junction-to-ambient thermal resistance (JA) is based on 4 layer board thermal measurements, performed under the conditions and guidelines set forth in the JEDEC standards JESD51-1 to JESD51-11. JA varies with PCB copper area, power dissipation, and airflow. Note 4: Min and Max limits are 100% production tested at 25C. Limits over the operating temperature range are guaranteed through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate National's Average Outgoing Quality Level (AOQL). Note 5: Typical numbers are at 25C and represent the most likely parametric norm. Note 6: Shutdown current includes leakage current of the high side PFET. Note 7: Current limit is built-in, fixed, and not adjustable. Note 8: Ripple voltage should be measured across COUT on a well-designed PC board using the suggested capacitors. 5 www.national.com LMZ10501 Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device is intended to be functional. For guaranteed specifications and test conditions, see the Electrical Characteristics. Unless otherwise specified the following conditions apply: VIN = 3.6V, TA = 25C Thermal Derating VOUT = 1.2V, JA = 120C/W Dropout Voltage vs Load Current and Input Voltage 0.30 0.25 1.2 VIN = 2.7V VIN = 3.3V VIN = 3.6V VIN = 4.0V OUTPUT CURRENT (A) DROPOUT VOLTAGE (V) 0.35 0.20 0.15 0.10 0.05 0.00 0.0 VIN = 3.3V VIN = 3.6V VIN = 5.0V VIN = 5.5V 1.0 0.8 0.6 0.4 0.2 0.0 0.2 0.4 0.6 0.8 LOAD CURRENT (A) 1.0 60 70 80 90 100 110 120 130 AMBIENT TEMPERATURE (C) 30124749 30124744 Thermal Derating VOUT = 1.8V, JA = 120C/W 1.2 Thermal Derating VOUT = 2.5V, JA = 120C/W 1.2 VIN = 3.3V VIN = 3.6V VIN = 5.0V VIN = 5.5V 1.0 OUTPUT CURRENT (A) OUTPUT CURRENT (A) LMZ10501 Typical Performance Characteristics 0.8 0.6 0.4 0.2 0.0 0.8 0.6 0.4 0.2 0.0 60 70 80 90 100 110 120 130 AMBIENT TEMPERATURE (C) 60 30124743 www.national.com VIN = 3.3V VIN = 3.6V VIN = 5.0V VIN = 5.5V 1.0 70 80 90 100 110 120 130 AMBIENT TEMPERATURE (C) 30124742 6 Radiated EMI (CISPR22) VIN = 5.0V, VOUT = 1.8V, IOUT = 1A Default evaluation board BOM VIN = 4.0V VIN = 4.5V VIN = 5.0V VIN = 5.5V 1.0 80 RADIATED EMISSIONS (dBV/m) OUTPUT CURRENT (A) 1.2 0.8 0.6 0.4 0.2 0.0 60 LMZ10501 Thermal Derating VOUT = 3.3V, JA = 120C/W 70 80 90 100 110 120 130 AMBIENT TEMPERATURE (C) Emissions (Evaluation Board) EN 55022 Class B Limit EN 55022 Class A Limit 70 60 50 40 30 20 10 0 0 30124741 200 400 600 800 FREQUENCY (MHz) 1000 30124732 Conducted EMI VIN = 5.0V, VOUT = 1.8V, IOUT = 1A Default evaluation board BOM with additional 1H 1F LC input filter CONDUCTED EMISSIONS (dBV) 80 70 Startup Conducted Emissions CISPR 22 Quasi Peak CISPR 22 Average 60 50 40 30 20 10 30124734 0 100m 1 10 FREQUENCY (MHz) 100 30124750 7 www.national.com Schematic VOUT = 1.2V Efficiency VOUT = 1.2V 100 EFFICIENCY (%) 90 80 70 60 50 VIN = 2.7V VIN = 3.3V VIN = 3.6V VIN = 5.0V VIN = 5.5V 40 30 20 30124722 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 LOAD CURRENT (A) 30124727 Output Ripple VOUT = 1.2V Load Transient VOUT = 1.2V 30124755 30124757 Line and Load Regulation VOUT = 1.2V DC Current Limit VOUT = 1.2V 1.5 DC CURRENT LIMIT (A) 1.24 OUTPUT VOLTAGE (V) LMZ10501 1.2V 1.23 1.22 1.21 1.20 VIN = 2.7V VIN = 3.3V VIN = 3.6V VIN = 5.0V VIN = 5.5V 30124737 www.national.com 1.3 1.2 1.1 1.0 2.5 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 LOAD CURRENT (A) TA = 85C 1.4 3.0 3.5 4.0 4.5 5.0 INPUT VOLTAGE (V) 5.5 30124751 8 LMZ10501 1.8V Schematic VOUT = 1.8V Efficiency VOUT = 1.8V 100 EFFICIENCY (%) 90 80 70 60 50 VIN = 2.7V VIN = 3.3V VIN = 3.6V VIN = 5.0V VIN = 5.5V 40 30 20 30124723 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 LOAD CURRENT (A) 30124726 Output Ripple VOUT = 1.8V Load Transient VOUT = 1.8V 30124758 30124733 Line and Load Regulation VOUT = 1.8V DC Current Limit VOUT = 1.8V 1.5 DC CURRENT LIMIT (A) OUTPUT VOLTAGE (V) 1.81 1.80 1.79 1.78 1.77 VIN = 2.7V VIN = 3.3V VIN = 3.6V VIN = 5.0V VIN = 5.5V 1.3 1.2 1.1 1.0 2.5 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 LOAD CURRENT (A) 30124738 TA = 85C 1.4 3.0 3.5 4.0 4.5 5.0 INPUT VOLTAGE (V) 5.5 30124752 9 www.national.com Schematic VOUT = 2.5V Efficiency VOUT = 2.5V 100 EFFICIENCY (%) 90 80 70 60 50 VIN = 3.3V VIN = 3.6V VIN = 5.0V VIN = 5.5V 40 30 20 30124724 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 LOAD CURRENT (A) 30124728 Output Ripple VOUT = 2.5V Load Transient VOUT = 2.5V 30124747 30124746 Line and Load Regulation VOUT = 2.5V DC Current Limit VOUT = 2.5V 1.5 DC CURRENT LIMIT (A) 2.53 OUTPUT VOLTAGE (V) LMZ10501 2.5V 2.52 2.51 2.50 2.50 VIN = 3.3V VIN = 3.6V VIN = 5.0V VIN = 5.5V 30124739 www.national.com 1.3 1.2 1.1 1.0 2.5 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 LOAD CURRENT (A) TA = 85C 1.4 3.0 3.5 4.0 4.5 5.0 INPUT VOLTAGE (V) 5.5 30124753 10 LMZ10501 3.3V Schematic VOUT = 3.3V Efficiency VOUT = 3.3V 100 EFFICIENCY (%) 90 80 70 60 50 VIN = 3.6V VIN = 4.0V VIN = 4.5V VIN = 5.0V VIN = 5.5V 40 30 20 30124725 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 LOAD CURRENT (A) 30124729 Output Ripple VOUT = 3.3V Load Transient VOUT = 3.3V 30124759 30124756 Line and Load Regulation VOUT = 3.3V DC Current Limit VOUT = 3.3V 1.5 DC CURRENT LIMIT (A) OUTPUT VOLTAGE (V) 3.30 3.28 3.26 3.24 VIN = 3.6V VIN = 4.0V VIN = 4.5V VIN = 5.0V VIN = 5.5V 3.22 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 LOAD CURRENT (A) 1.3 1.2 1.1 1.0 2.5 30124740 TA = 85C 1.4 3.0 3.5 4.0 4.5 5.0 INPUT VOLTAGE (V) 5.5 30124754 Block Diagram 11 www.national.com LMZ10501 30124704 FIGURE 1. Functional Block Diagram PFET on-time, which controls the peak inductor current. In current mode control architecture, the inductor current is compared with the slope compensated output of the error amplifier. At the rising edge of the clock, the PFET is turned ON, ramping up the inductor current with a slope of (VIN - VOUT)/ L. The PFET is ON until the current signal equals the error signal. Then the PFET is turned OFF and NFET is turned ON, ramping down the inductor current with a slope of VOUT /L. At the next rising edge of the clock, the cycle repeats. An increase of load pulls the output voltage down, resulting in an increase of the error signal. As the error signal goes up, the peak inductor current is increased, elevating the average inductor current and responding to the heavier load. To ensure stability, a slope compensation ramp is subtracted from the error signal and internal loop compensation is provided. Overview The LMZ10501 SIMPLE SWITCHER(R) nano module is an easy-to-use step-down DC-DC solution capable of driving up to 1A load in space-constrained applications. Only an input capacitor, an output capacitor, a small VCON filter capacitor, and two resistors are required for basic operation. The nano module comes in 8-pin LLP footprint package with an integrated inductor. The LMZ10501 operates in fixed 2.0MHz PWM (Pulse Width Modulation) mode, and is designed to deliver power at maximum efficiency. The output voltage is typically set by using a resistive divider between the built-in reference voltage VREF and the control pin VCON. The VCON pin is the positive input to the error amplifier. The output voltage of the LMZ10501 can also be dynamically adjusted between 0.6V and 3.6V by driving the VCON pin externally. Internal current limit based softstart function, current overload protection, and thermal shutdown are also provided. INPUT UNDER VOLTAGE DETECTION The LMZ10501 implements an under voltage lock out (UVLO) circuit to ensure proper operation during startup, shutdown and input supply brownout conditions. The circuit monitors the voltage at the VIN pin to ensure that sufficient voltage is present to bias the regulator. If the under voltage threshold is not met, all functions of the controller are disabled and the controller remains in a low power standby state. CIRCUIT OPERATION The LMZ10501 is a synchronous Buck power module using a PFET for the high side switch and an NFET for the synchronous rectifier switch. The output voltage is regulated by modulating the PFET switch on-time. The circuit generates a duty-cycle modulated rectangular signal. The rectangular signal is averaged using a low pass filter formed by the integrated inductor and an output capacitor. The output voltage is equal to the average of the duty-cycle modulated rectangular signal. In PWM mode, the switching frequency is constant. The energy per cycle to the load is controlled by modulating the www.national.com SHUTDOWN MODE To shutdown the LMZ10501, pull the EN pin low (<0.5V). In the shutdown mode all internal circuits are turned OFF. 12 LMZ10501 EN PIN OPERATION The EN pin is internally pulled up to VIN through a 790k (typ.) resistor. This allows the nano module to be enabled by default when the EN pin is left floating. In such cases VIN will set EN high when VIN reaches 1.2V. As the input voltage continues to rise, operation will start once VIN exceeds the undervoltage lockout (UVLO) threshold. To set EN high externally, pull it up to 1.2V or higher. Note that the voltage on EN must remain at less than VIN+ 0.2V due to absolute maximum ratings of the device. INTERNAL SYNCHRONOUS RECTIFICATION The LMZ10501 uses an internal NFET as a synchronous rectifier to minimize the switch voltage drop and increase efficiency. The NFET is designed to conduct through its intrinsic body diode during the built-in dead time between the PFET on-time and the NFET on-time. This eliminates the need for an external diode. The dead time between the PFET and NFET connection prevents shoot through current from VIN to PGND during the switching transitions. 30124734 FIGURE 2. Startup behavior of current limit based softstart. The soft start rate is also limited by the VCON ramp up rate. The VCON pin is discharged internally through a pull down device before startup occurs. This is done to deplete any residual charge on the VCON filter capacitor and allow the VCON voltage to ramp up from 0V when the part is started. The events that cause VCON discharge are thermal shutdown, UVLO, EN low, or output short circuit detection. The minimum recommended capacitance on VCON is 220pF and the maximum is 1nF. The duration of startup current limiting sequence takes approximately 75s. After the sequence is completed, the feedback voltage is monitored for output short circuit events. CURRENT LIMIT The LMZ10501 current limit feature protects the module during an overload condition. The circuit employs positive peak current limit in the PFET and negative peak current limit in the NFET switch. The positive peak current through the PFET is limited to 1.7A (typ.). When the current reaches this limit threshold the PFET switch is immediately turned off until the next switching cycle. This behavior continues on a cycle-bycycle basis until the overload condition is removed from the output. The typical negative peak current limit through the NFET switch is -0.6A (typ.). The ripple of the inductor current depends on the input and output voltages. This means that the DC level of the output current when the peak current limiting occurs will also vary over the line voltage and the output voltage level. Refer to the DC Output Current Limit plots in the Typical Performance Characteristics section for more information. OUTPUT SHORT CIRCUIT PROTECTION In addition to cycle by cycle current limit, the LMZ10501 features a second level of short circuit protection. If the load pulls the output voltage down and the feedback voltage falls to 0.375V, the output short circuit protection will engage. In this mode the internal PFET switch is turned OFF after the current limit comparator trips and the beginning of the next cycle is inhibited for approximately 230s. This forces the inductor current to ramp down and limits excessive current draw from the input supply when the output of the regulator is shorted. The synchronous rectifier is always OFF in this mode. After 230s of non-switching a new startup sequence is initiated. During this new startup sequence the current limit is gradually stepped up to the nominal value as illustrated in the STARTUP BEHAVIOR AND SOFTSTART section. After the startup sequence is completed again, the feedback voltage is monitored for output short circuit. If the short circuit is still persistent after the new startup sequence, switching will be stopped again and there will be another 230s off period. A persistent output short condition results in a hiccup behavior where the LMZ10501 goes through the normal startup sequence, then detects the output short at the end of startup, terminates switching for 230s, and repeats this cycle until the output short is released. This behavior is illustrated in the following figure. STARTUP BEHAVIOR AND SOFTSTART The LMZ10501 features a current limit based soft start circuit in order to prevent large in-rush current and output overshoot as VOUT is ramping up. This is achieved by gradually increasing the PFET current limit threshold to the final operating value as the output voltage ramps during startup. The maximum allowed current in the inductor is stepped up in a staircase profile for a fixed number of switching periods in each step. Additionally, the switching frequency in the first step is set at 450kHz and is then increased for each of the following steps until it reaches 2MHz at the final step of current limiting. This current limiting behavior is illustrated in the following figure and allows for a smooth VOUT ramp up. 13 www.national.com LMZ10501 regulation. If VIN is lowered even more, the off-time of the PFET will reach the 35ns mark again. The LMZ10501 will then reduce the frequency again, achieving less than 100% duty cycle operation and maintaining regulation. As VIN is lowered even more, the LMZ10501 will continue to scale down the frequency, aiming to maintain at least 35ns off time. Eventually, as the input voltage decreases further, 100% duty cycle is reached. This behavior of extending the VIN regulation range is illustrated in the following plot. 30124745 FIGURE 3. Hiccup behavior with persistent output short circuit. Since the output current is limited during normal startup by the softstart function, the current charging the output capacitor is also limited. This results in a smooth VOUT ramp up to nominal voltage. However, using excessively large output capacitance or VCON capacitance under normal conditions can prevent the output voltage from reaching 0.375V at the end of the startup sequence. In such cases the module will maintain the described above hiccup mode and the output voltage will not ramp up to final value. To cause this condition, one would have to use unnecessarily large output capacitance for 1A load applications. See the INPUT AND OUTPUT CAPACITOR SELECTION section for guidance on maximum capacitances for different output voltage settings. 30124760 FIGURE 4. High duty cycle operation and switching frequency reduction. THERMAL OVERLOAD PROTECTION The junction temperature of the LMZ10501 should not be allowed to exceed its maximum operating rating of 125C. Thermal protection is implemented by an internal thermal shutdown circuit which activates at 150C (typ). When this temperature is reached, the device enters a low power standby state. In this state switching remains off causing the output voltage to fall. Also, the VCON capacitor is discharged to SGND. When the junction temperature falls back below 130 C (typ) normal startup occurs and VOUT rises smoothly from 0V. Applications requiring maximum output current may require derating at elevated ambient temperature. See the Typical Performance Characteristics section for thermal derating plots for various output voltages. HIGH DUTY CYCLE OPERATION The LMZ10501 features a transition mode designed to extend the output regulation range to the minimum possible input voltage. As the input voltage decreases closer and closer to VOUT, the off-time of the PFET gets smaller and smaller and the duty cycle eventually needs to reach 100% to support the output voltage. The input voltage at which the duty cycle reaches 100% is the edge of regulation. When the LMZ10501 input voltage is lowered, such that the off-time of the PFET reduces to less than 35ns, the LMZ10501 doubles the switching period to extend the off-time for that VIN and maintain www.national.com 14 LMZ10501 Application Information 30124736 FIGURE 5. Typical Application Circuit SETTING THE OUTPUT VOLTAGE The LMZ10501 provides a fixed 2.35V VREF voltage output. As shown in Figure 5 above, a resistive divider formed by RT and RB sets the VCON pin voltage level. The VOUT voltage tracks VCON and is governed by the following relationship: by design is 5.875V. Each nano module's VREF voltage is trimmed so that this product is as close to the ideal 5.875V value as possible, achieving high VOUT accuracy. See the Electrical Specifications section for the VREF x GAIN product tolerance limits. (1) DYNAMIC OUTPUT VOLTAGE SCALING The VCON pin on the LMZ10501 can be driven externally by a DAC to scale the output voltage dynamically. The output voltage VOUT = 2.5V/V x VCON. When driving VCON with a source different than VREF place a 1.5k resistor in series with the VCON pin. Current limiting the external VCON helps to protect this pin and allows the VCON capacitor to be fully discharged to 0V after fault conditions. VOUT = GAIN x VCON where GAIN is 2.5V/V from VCON to VFB. This equation is valid for output voltages between 0.6V and 3.6V and corresponds to VCON voltage between 0.24V and 1.44V, respectively. RT and RB Selection for Fixed VOUT The parameters affecting the output voltage setting are the RT, RB, and the product of the VREF voltage x GAIN. The VREF voltage is typically 2.35V. Since VCON is derived from VREF via RT and RB, VCON = VREF x RB/ (RB + RT) INTEGRATED INDUCTOR The LMZ10501 uses a Low Temperature Co-fired Ceramic (LTCC) type 2.6 H inductor with over 1.2A DC current rating and soft saturation profile for up to 2A. This inductor allows for the 1.2mm overall package height providing an easy to use, compact solution with reduced EMI. (2) After substitution, VOUT = VREF x GAIN x RB/ (RB + RT) (3) RT = ( GAIN x VREF / VOUT - 1 ) x RB (4) INPUT AND OUTPUT CAPACITOR SELECTION The LMZ10501 is designed for use with low ESR multi-layer ceramic capacitors (MLCC) for its input and output filters. Using a 10 F 0603 or 0805 with 6.3V or 10V rating ceramic input capacitor typically provides sufficient VIN bypass. Use of multiple 4.7 F or 2.2F capacitors can also be considered. Ceramic capacitors with X5R and X7R temperature characteristics are recommended for both input and output filters. These provide an optimal balance between small size, cost, reliability, and performance for space sensitive applications. The DC voltage bias characteristics of the capacitors must be considered when selecting the DC voltage rating and case size of these components. The effective capacitance of an MLCC is typically reduced by the DC voltage bias applied across its terminals. For example, a typical 0805 case size X5R 6.3V 10 F ceramic capacitor may only have 4.8 F left in it when a 5.0V DC bias is applied. Similarly, a typical 0603 case size X5R 6.3V 10 F ceramic capacitor may only have 2.4 F at the same 5.0V DC. Smaller case size capacitors may have even larger percentage drop in value with DC bias. The ideal product of GAIN x VREF = 5.875V. Choose RT to be between 80k and 300k. Then, RB can be calculated using equation (5) below. RB = ( VOUT / (5.875V - VOUT) ) x RT (5) Note that the resistance of RT should be 80k. This ensures that the VREF output current loading is not exceeded and the reference voltage is maintained. The current loading on VREF should not be greater than 30 A. OUTPUT VOLTAGE ACCURACY OPTIMIZATION Each nano module is optimized to achieve high VOUT accuracy. Equation (1) shows that, by design, the output voltage is a function of the VCON voltage and the gain from VCON to VFB. The voltage at VCON is derived from VREF. Therefore, as shown in equation (3), the accuracy of the output voltage is a function of the VREF x GAIN product as well as the tolerance of the RT and RB resistors. The typical VREF x GAIN product 15 www.national.com LMZ10501 The optimum output capacitance value is application dependent. Too small output capacitance can lead to instability due to lower loop phase margin. On the other hand, if the output capacitor is too large, it may prevent the output voltage from reaching the 0.375V required voltage level at the end of the startup sequence. In such cases, the output short circuit protection can be engaged and the nano module will enter a hiccup mode as described in the OUTPUT SHORT CIRCUIT PROTECTION section. The table below sets the minimum output capacitance for stability and maximum output capacitance for proper startup for various output voltage settings. Note that the maximum COUT value in Table 1 assumes that the filter capacitance on VCON is the maximum recommended value of 1nF and the RT resistor value is less than 300k. Lower VCON capacitance can extend the maximum COUT range. There is no great performance benefit in using excessive COUT values. Use of multiple 4.7 F or 2.2F output capacitors can be considered for reduced effective ESR and smaller output voltage ripple. In addition to the main output capacitor, small 0.1F - 0.01F parallel capacitors can be used to reduce high frequency noise. PACKAGE CONSIDERATIONS The nano module package includes an LTCC inductor on the bottom and a micro SMD die mounted on top. The die has exposed edges and can be sensitive to ambient light. For applications with direct high intensity ambient red, infrared, LED, or natural light it is recommended to have the device shielded from the light source to avoid abnormal behavior. TABLE 1. Output Capacitance Range Output Voltage Minimum COUT Suggested COUT Maximum COUT 0.6V 4.7F 10F 47F 1.0V 3.3F 10F 47F 1.2V 3.3F 10F 47F 1.8V 3.3F 10F 68F 2.5V 3.3F 10F 100F 3.3V 3.3F 10F 100F www.national.com 16 LMZ10501 Board Layout Considerations 30124748 FIGURE 6. Example Top Layer Board Layout The board layout of any DC-DC switching converter is critical for the optimal performance of the design. Bad PCB layout design can disrupt the operation of an otherwise good schematic design. Even if the regulator still converts the voltage properly, the board layout can mean the difference between passing or failing EMI regulations. In a Buck converter, the most critical board layout path is between the input capacitor ground terminal and the synchronous rectifier ground. The loop formed by the input capacitor and the power FETs is a path for the high di/dt switching current during each switching period. This loop should always be kept as short as possible when laying out a board for any Buck converter. The LMZ10501 integrates the inductor and simplifies the DCDC converter board layout. Refer to the example layout in Figure 6. There are a few basic requirements to achieve a good LMZ10501 layout. 1. Place the input capacitor CIN as close as possible to the VIN and PGND terminals. VIN (pin 7) and PGND (pin 6) on the LMZ10501 are next to each other which makes the input capacitor placement simple. 2. Place the VCON filter capacitor CVC and the RB RT resistive divider as close as possible to the VCON and SGND terminals.The CVC capacitor (not RB) should be the component closer to the VCON pin, as shown in Figure 6. This allows for better bypass of the control voltage set at VCON. 3. Run the feedback trace (from VOUT to FB) away from noise sources. 4. Connect SGND to a quiet GND plane. 5. Provide enough PCB area for proper heatsinking. Refer to the Electrical Characteristics table for example JA values for different board areas. Also, refer to AN-2020 for additional thermal design hints. Refer to the evaluation board application note (AN-2166) for a complete board layout example. 17 www.national.com LMZ10501 Physical Dimensions inches (millimeters) unless otherwise noted NS Package Number SE08A www.national.com 18 LMZ10501 Notes 19 www.national.com 1A SIMPLE SWITCHER(R) Nano Module with 5.5V Maximum Input Voltage Notes For more National Semiconductor product information and proven design tools, visit the following Web sites at: www.national.com Products Design Support Amplifiers www.national.com/amplifiers WEBENCH(R) Tools www.national.com/webench Audio www.national.com/audio App Notes www.national.com/appnotes Clock and Timing www.national.com/timing Reference Designs www.national.com/refdesigns Data Converters www.national.com/adc Samples www.national.com/samples Interface www.national.com/interface Eval Boards www.national.com/evalboards LVDS www.national.com/lvds Packaging www.national.com/packaging Power Management www.national.com/power Green Compliance www.national.com/quality/green Switching Regulators www.national.com/switchers Distributors www.national.com/contacts LDOs www.national.com/ldo Quality and Reliability www.national.com/quality LED Lighting www.national.com/led Feedback/Support www.national.com/feedback Voltage References www.national.com/vref Design Made Easy www.national.com/easy www.national.com/powerwise Applications & Markets www.national.com/solutions Mil/Aero www.national.com/milaero PowerWise(R) Solutions Serial Digital Interface (SDI) www.national.com/sdi Temperature Sensors www.national.com/tempsensors SolarMagicTM www.national.com/solarmagic PLL/VCO www.national.com/wireless www.national.com/training PowerWise(R) Design University THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION ("NATIONAL") PRODUCTS. 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