___. General Description The MAX7231 /32/33/34 family of integrated circuits is a complete line of triplexed liquid crystal display (LCD) drivers. These devices interface microproces- sors (or digital systems) to multiplexed numeric and alphanumeric displays. The MAX7231 drives 8 digits and accepts data in a parallel format. The MAX7232 drives 10 digits and accepts data in a serial format. Both devices feature two independent annunciators per digit. The MAX7233 drives 4 alphanumeric 18 segment characters. The MAX7234 drives 5 alpha- numeric 18 segment characters. Each device includes an input buffer, digit address decoding circuitry and mask-programmed ROM allowing six bits of input data to be decoded into 64 independent combinations of the output seg- ments of each digit. This offloads the microprocessor system, reducing the ROM space and CPU time needed to service a display. _ Applications These low-power LCD drivers are ideal for micro- processor-based portable applications where power consumption is a primary concern. Many applica- tions also take advantage of the annunciator drive capability, which allows unlimited variations of display layout. Portable instrumentation Industrial equipment Telecommunications Medical equipment Panel Meters Machine control ee Typical Operating C Circuit (RRR) eo MAX?7233 MAX7233 | Cs2 CS1 Ay Ao DeDs CS2 CS1 A, Ag DoDs ry] | LY | Two MAX7233's driving 8 character display { Detailed Circuit Diagram Figure 21) INPUT SA AALSVI Triplexed LCD Decoder/Drivers _ Features @ MAX7231 drives 8 digits/7 segments; parallel input format; 2 annunciators per digit @ MAX7232 drives 10 digits/7 segments; serial input format; 2 annunciators per digit @ MAX7233 drives 4 alphanumeric characters/ 18 segments; parallel input format @ MAX7234 drives 5 alphanumeric characters/ 18 segments; serial input format @ On-chip oscillator od Direct interface to microprocessors @ Monolithic, Low Power CMOS Design Ordering Information | PART MAX7231AFIPL_- TEMP. RANGE -20C to +85C PACKAGE _i| 40 Lead Plastic DIP MAX7231BFIPL MAX7232AF IPL MAX7232BFIPL | MAX7232CFIPL MAX7283AF PL MAX7233BFIPL MAX7231CFIPL -20C to +85C -20C to ~85C -20C to -85C -20C to +85C -20C to +85C "=20C to +85C -20S to +85C 40 Lead Plastic DIP 40 Lead Plastic DIP 40 Lead Plastic DIP "40 Lead Plastic DIP 40 Lead Plastic DIP | 40 Lead Plastic DIP 40 Lead Plastic. DIP MAX7234BFIPL ee -20C to +85C 20C to 85 Co 40 Lead Plastic. DIP 40 Lead Plastic C DIP | Ordering information continued on next page _____ Pin Configuration Top View 40 Lead DIP 285 A2 995 Hat oo u F 0 Le} 14] @Nno zr F eos we] oap 602 xB 3f18D1 2z fo] pe a Gi AN2 we Te Be 8 bw 2 Dx 3X [16 ny az G7] D 7z le} f9} ] 6x 3 Li] 6Y [) 6z 44 Lead PCC / MAKIN Maxim Integrated Products Call toll free 1-800-998-8800 for free samples or literature. PE/EE/CE/LECLXVINMAX7231/32/33/34 Triplexed LCD Decoder/Drivers OPTION TABLE DEVICE OUTPUT CODE ANNUNCIATOR LOCATIONS INPUT OUTPUT MAX7231 AF Hexdecimal Both Annunicators Parallel Entry 8 Digits MAX7231 BF Code B on COM3 4 bit Data plus MAX7231CF Code B 1 Annunciator COM1 2 bit Annunciators 16 Annunciators | 1 Annunciator COM3 3 bit Address MAX7232AF Hexadecimal Both Annunciators Serial Entry 10 Digits MAX7232BF Code B on COM3 4 bit Data plus 2 Bit Annunciators 20 Annunciators MAX7232CF Code B 1 Annunciator COM1 4 bit Address 1 Annunciator COM3 MAX7233AF 64 Character (ASCII) No independent Parallel Entry 6 bit (ASCII) | Four 18 Segment Annunciators Data Characters (Half width numbers} 2 bit Address MAX7233BF 64 Character (ASCII) No Independent Parallel Entry 6 bit (ASCH) | Four 18 Segment Annunciators Data Characters , (Full width numbers) 2 bit Address MAX7234AF 64 Character (ASCII) No Independent Serial Entry 6 bit (ASCII) Five 18 Segment Annunciators Data Characters (Half width numbers) 3 bit Address MAX7234BF 64 Character (ASCII) No Independent Serial Entry 6 bit (ASCII) Five 18 Segment Annunciators Data Characters (Full width numbers) 3 bit Address __..._____... Ordering Information (Continued from front page) _.. CR Cornfiguration PART TEMP. RANGE PACKAGE Top View 44 Lead PCC MAX7231AFIQ -20C to+85C 44 Lead Plastic Chip Carrier DATA ACCEPTED MAX7231BFIQ -20C ta+85C 44 Lead Plastic Chip Carrier MAX7231CFIQ -20C to+85C 44 Lead Plastic Chip Carrier f=]coma [=] cOM1 3 | WRITE INPUT S ] DATA INPUT 1Z mH MAX7232AFIQ -20C to+85C 44 Lead Plastic Chip Carrier vo MAX7232BFIQ -20C to+85C 44 Lead Plastic Chip Carrier oe MAX7232 MAX7232CFIQ -20C to+85C 44 Lead Plastic Chip Carrier we = AF MAX7233AFIQ -20C to+85C 44 Lead Plastic Chip Carrier a 32 [14 MAX7233BFIQ -20C to+85C 44 Lead Plastic Chip Carrier ay [5] 3X [16 MAX7234AFIQ -20C to +85C = 44 Lead Plastic Chip Carrier az MAX7234BFIQ -20C to+85C 44 Lead Plastic Chip Carrier 40 Lead DIP 40 Lead DIP DATA CLOCK _ DATA CLOCK pen peg tNPUT [J1 ao pve tsiqjt 400 vt INPUT [J1 40D v~ Voise (2 a9 [0 WRITE INPUT Voise 2 39] Cs2 Voise ( 2 a9 [0 WRITE INPUT comi(}3 38 1D DATA INPUT comi]3 3D a1 com1(]3 38 [ DATA INPUT com2 (]4 37 [1 DATA ACCEPTED com2 (]4 37 Dao com2 (]4 a7 [1 DATA ACCEPTED coms 1] 5 36 Fan OUTPUT coms C15 36 [GND coms {5 as Hy ano OUTPUT zs 35H 10x 1z6 35 1 ps izO6 a5 0 5u wy 34D 107 wr 34.0 D4 wO7 347 sv xO 8 yaxro92" r} 10Z 41x] 8 a ax7299 33D D3 x 8 axzoad sw azo arp 2 [) 9x iwi AE a2 p2 wo ar 42 [J 5x 2yvQw ge apo wo pp 3fiD1 Wt pee psy ax CF soplez wn 30 1 bo wun 30 7 5z 3z 1] 12 29 77 8x 2z 0] 12 290 4u 2z 12 29 au ay 13 28 [1 ay ayy zpDav av 13 23 av 3x (14 27 1 az 2x (14 27 Daw ax O14 27 0 aw 4z 15 26 7 7x aw 15 26 0 4x ow 15 26 2 4x ay 16 27 ao 2say a6 250 ay 4x 17 240 7z 2u( 17 2a az wow 242 4z sz] 18 23 1 6x 3z 18 231 3u oz) 18 230 au sy O19 220 6Y 3y C19 20w sy 19 22D av 5X (J 20 21f7 62 3x [J 20 aD 3w 3x J 20 210 3w Continued on last page of data sheet Qe. a ce oe _MAXAILSVIABSOLUTE MAXIMUM RATINGS Power Dissipation (Note 1) ............. 0.5 W @ 85C Supply Voltage (V7)... cc eee e cece eee eee eens 6.5V Input Voltage (Note 2) .............. -0.3V < Vin < 6.5V Display Voltage (Note 2) ............ -0.3V to Vt + 0.3V Operating Temperature Range ......... -20C to +85C Triplexed LCD Decoder/Drivers Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not limited. Exposure to abso- lute maximum rating conditions for extended periods may affect device reliability. Storage Temperature Range Soldering Temperature (10 seconds) . ELECTRICAL CHARACTERISTICS (v+ = +5v +10%, Ta = -20C to +85C unless noted) PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN TYP MAX UNITS Power Supply Voltage vt 45 5.5 Vv Data Retention + : Supply Voltage Vv Guaranteed Retention at 2V 2 1.6 Vv : + Current from V* to Ground Logic Supply Current l excluding Display, Voisp = 2V 30 100 pA Shutdown Total Current Is Voisp Pin 2 Open, Ty = +25C 1 10 BA Display Voltage Range Voise | Ground < Voge = Vt QO vr Vv Display Voltage Voisp = (V* - 3V), Current from V* to Setup Current lnISP_ | Verse On-Chip (Note 3), Ta = +25C 15 25 BA Display Voltage Setup One of Three Identical Resistors Resistor Value RoisP | in String (Note 3), Ta = +25C 40 5 ko DC Component of _ on (yee Display Signals Sample Test only, Voisp = OV 1/4 1 % (V+-VpIsP) Display Frame Rate foise See Figure 2, Ta = +25C 60 90 120 Hz Input Low Level (Note 3) VIL MAX7231, MAX7233] MAX7232, MAX7234 0.8 Vv Input High Level (Note 3) VIH Pins 1, 30-35, 37-39] Pins 1, 38, 39 2.0 Vv Input Leakage lik MAX7231, MAX7233 | MAX7232, MAX7234 0.1 1 BA Input Capacitance CIN Pins 1, 30-35, 37-39 | Pins 1, 38, 39 5 pF Output Low Level VoL Pin 37, MAX7232, MAX7234, lo. = 1mA, 04 Vv Output High Level Vou Vt = 4.5V, lon = -500uA 41 Vv AC CHARACTERISTICS V* = 5V, Ta = 25C, 0-3V INPUT SWINGS PARALLEL INPUT (MAX7231, MAX7233) See Figure 5 PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN TYP MAX UNITS Chip Select Pulse Width tes 500 350 ns Address/Data Setup Time tds 350 ns Address/Data Hold Time tah 0 -20 ns Inter-Chip Select Time tics 3.5 us AC CHARACTERISTICS 0-3V INPUT SWINGS SERIAL INPUT (MAX7232, MAX7234) See Figures 6, 7, 8 PARAMETER SYMBOL CONDITIONS/DESCRIPTION MIN TYP MAX UNITS Data Clock Low Time tel 350 ns Data Clock Period tel 1 us Data Setup Time tds 350. ns Data Hold Time tdh 0 -20 ns Write Pulse Width twp 500 350 ns Write Pulse to Clack at Initialization wll 40 Hs Data Accepted Low Output Delay toa 1 HS Data Accepted High Output Delay todh 15 3 us Write Delay After Last Clock tews 350 ns Note 1: This limit refers to that of the package and will not be obtained during normal operation. Note 2: Due to the SCR structure inherent in these devices, connecting any display terminal or the display voltage terminal to a voltage outside the power supply to the chip may cause destructive device latchup. The digital inputs should never be connected to a voltage less than -0.3 voits below ground, but may be connected to voltages above V+ but not more than 6.5 volts above GND. Note 3: Vt = 5V, Ta = +25C. MAAIM. PE/EE/CE/LECLXVNMAX 7231/32/33/34 Triplexed LCD Decoder/Drivers TERMINAL DEFINITIONS MAX7231 PARALLEL INPUT NUMERIC DISPLAY (Note 3) TERMINAL PIN NO. DESCRIPTION FUNCTION ANI 30 Annunciator 1 Control Bit High = ON AN2 _ 3 Annunciator 2 Control Bit Low = OFF See Table 1 | BDO 32 Least Significant Input BDI 33 4 Bit Binary Data BD2 34 Data Inputs BD3 35 Most Significant (See Table 2) HIGH Logical One (1) AO 37 Least Significant 3 Bit Digi Input LOW = Logical Zero (0) it Digit Al 38 Address Inputs Address A2 39 Most Significant p (See Table 4) cs 1 Data Input Strobe/Chip Select Trailing (Positive going) edge latches data, causes data input to be decoded and sent out to addressed digit MAX7233 PARALLEL INPUT ALPHA DISPLAY Note 3: CS has a special mid-level sense circuit that establishes a test mode if it is held near 3V for several msec. Inadvertent triggering of this mode can be avoided by pulling it high when inactive, and driving it with fast rise and fall times. TERMINAL PIN NO. DESCRIPTION FUNCTION DO 30 Least Significant D1 31 Il t be 32 6 Bit (ASCII) Data D3 33 Data Inputs (See Table 3) HIGH = Logical One (1) D4 34 LOW = Logical Zero (0) DS 35 Most Significant AO 37 Least Significant Input Add. Ai 3 Most Significant | Aress Inputs (See Table 5) cs1 39 Chip Select Inputs Both Inputs LOW, load data into input latches. CS2 1 (Note 3) Rising edge of either input causes data to be latched, decoded and sent out to addressed character. MAX7232 and MAX7234 SERIAL DATA AND ADDRESS INPUT | TERMINAL PIN NO. DESCRIPTION FUNCTION | Data Input 38 Data + Address Shift Register Input HIGH Logical One (1) _ LOW = Logical Zero (0) : _ WRITE Input 39 Decode, Output, and Reset Strobe When DATA ACCEPTED Output is LOW, positive going edge of WRITE causes data in shift register to be decoded and sent to addressed digit, then shift register and control logic is reset. When DATA ACCEPTED Output is HIGH, positive going _ edge of WRITE triggers reset only. : Data Clock 1 Data Shift Register and Control Positive going edge advances data in shift Input Logic Clock register. MAX7232: Eleventh edge resets shift register and control logic. MAX7234: Tenth edge resets shift register ae and control logic. | DATA 37 Handshake Output Output LOW when correct number of bits ACCEPTED entered into shift register; MAX7232: 8, 9 or Output 10 bits. MAX7234: 9 bits. ALL DEVICES TERMINAL | PINNO. | | DESCRIPTION, =| ;~~sSCC:CCW FUNCTION is Display \ 2 | Negative end of on-chip resistor string Display voltage control. When open (or less Voltage Vbisp used to generate intermediate voltage than 1V from V*) chip is shutdown; oscillator ee levels for display. Shutdown Input. stops, all display pins to Vt. Common Line . : Driver Outputs 3,45 Drive display commons, or rows. Segment Line 6-29 {On MAX7231/33) Drive disol ments. or columns Driver Outputs 6-35 (On MAX7232/34) & alsplay Segments, oF columns. vt 40 Positive Supply - GND 36 Ground _MAXI/VITriplexed LCD Decoder/Drivers DB D7? DE DS De D3 D2 Di LINE ORIVERS 3 WIDE Vu ON CHIP DISPLAY VOLTAGE LEVEL Vu GENERATOR OUTPUT LATCHES 9 WIDE Voise PIN 2 (INPUT) DIGIT ADORESS EN DECODER DISPLAY TIMING GENERATOR DATA com1 DECODER LINE DRIVER cOM2 cOM3 DATA INPUT LATCHES EN AO Al A2 ~~ eee DATA INPUTS ADDRESS INPUTS ] Figure 1. Block Diagram of MAX7231. SEGMENT D10 be Ds o7 D6 DS Da D3 D2 DI XYZ xZ XYZ KY Z XYZ KY Z XYZ XYZ XYZ KY Z Vy ON CHIP DISPLAY VOLTAGE LEVEL ourpuT _ GENERATOR 9 WIDE DIGIT EN DISPLAY DATA ADDRESS TIMING com1 DECODER DECODER GENERATOR SERIAL INPUT CONTROL LOGIC LINE DRIVERS cOM2 cLOcK AO) A11A2 143] DaTA t COM3 AN, BD\80/8D 2 1 Oltir2y;3 SHIFT REGISTER DATA DATA DATA SHIFTS RIGHT TO LEFT INPUT CLOCK INPUT ACCEPTED ON RISING EDGE OF DATA CLOCK INPUT OUTPUT Figure 2. Block Diagram of MAX7232 MMA XAILSVI . PIN 2 (INPUT) PE/EE/SE/LECLXVNMAX 7231/32/33/34 Triplexed LCD Decoder/Drivers CHAR 4 CHAR 3 CHAR 2 CHAR 1 UVWXYZ UVWXYZ UVWXYZ UVWXYZ SEGMENT [ r LINE . DRIVERS f v 6 WIDE = | OUTPUT Vu ON CHIP LATCHES DISPLAY 18 WIDE VOLTAGE LEVEL 18 i" {* {" V_L GENERATOR | L_ Voise PIN 2 (INPUT) 18 DISPLAY TIMING RACTER GENERATOR CHA ae ADDRESS EN IL + comi DECODER CODER OE COMMON ONE LINE com2 H DRIVER SHOT -. coms ADDRESS DATA INPUT EN INPUT EN LATCHES LATCHES DO D1 02 D3 D4 DS AO Al i SS at Csi CS2 aa at = CHIP SELECT INPUTS Figure 3. Block Diagram of MAX7233 : CHAR 5 CHAR 4 CHAR 3 CHAR 2 CHAR 1 UVWXYZ rey Witt UVWXYZ Wt SEGMENT - LINE ORIVER th Tr vw 6 WIDE \ -f I -4 Ss 2 > OUTPUT vy ON CHIP uarewes $t bisa IDE > 18 WI | | | > LeveL v_ GENERATOR 18 18 18 18 18 3 s YpisP ; PIN 2 {INPUT) fis [ DATA Cnopacse EN DISPLAY LF com1 DECODER DECOnER TIMING COMMON GENERATOR uNE | _come SERIAL INPUT DRIVERS | [ CONTROL LOGIC coma T CLOCK torr tt ( Do ,01102/ 03104 (05 AOL AT (a2 toto oy tod i | DATA 1 1 i 1 4. y SHIFT REGISTER SHIFTS RIGHT TO LEFT ON RISING EDGE OF DATA CLOCK DATA DATA WRITE DATA INPUT CLOCK INPUT ACCEPTED (PUT OUTPUT Figure 4. Block Diagram of MAX7234 MAATriplexed LCD Decoder/Drivers cs2 \ INPUT (MAX72330NLY) csi: INPUT | ties | DATA = Y ADDRESS a ee ADDRESS x Seri ocesnaeetnetes ADDRESS : AND DATA oe fone AND DATA RSENS INPUT 7 '\\inputs VALIO/T\ woes oo INPUTS VALID J Qe eee, t | 1 | l vi tan! | etgsel > DO NOT CARE PARALLEL INPUT TIMING MAX7233 AND MAX7231 a Figure . Parallel Input Timing Detailed Description on the subsequent data clock inputs. The MAX7232's Parallel Input Interface The MAX7231 and MAX7233 have a parallel interface allowing direct parallel connection to microproces- sors. The address and data bits are latched on the positive going edge of the Chip Select. The positive going edge of Chip Select also triggers an internal monostable that enables the address decoder and latches the decoded data into the digit/character output latches. Figure 5 shows the timing requirements for the parallel input devices (7231 and 7233). To ensure that the new data does not appear at the decoder inputs before the previous decoded data is written to the outputs, there is a minimum time required between CHIP SELECT pulses. Serial Input Interface A WRITE pulse while Data Accepted Output is high will reset the serial input control logic, but will not latch any data. A WRITE pulse while Data Accepted Output is low will cause the MAX7232 and MAX7234 to decode the data, latch the data into the output latches and then reset the serial input control logic. This assures that each data bit will be entered into the correct position in the shift register, depending MAAIA __ Data Accepted Output goes low after 8 Data Clock pulses, whereas the MAX7234s Data Accepted Out- put goes low after 9 Data Clock Inpulses. Further Data Clock pulses occuring before a WRITE pulse will cause the Data Accepted Output to go high after 11 Data Clock pulses in the MAX7232 and the 10 Data Clock pulses in the MAX7234. In both cases, the serial input control logic is also reset when Data Accepted goes high. The serial input timing diagram shown in Figure 6 illustrates the recommended procedure for enter- ing data. Note that the eleventh clock resets the shift register and control logic for the MAX7232, but the Data Accepted Output goes low after the eighth clock. As Figure 7 illustrates, this allows the user to reduce the data to eight bits. The MAX7232 then writes to the 7 segment display, but leaves the annunciators off. Nine Bits are clocked in if only AN2 is turned on. The control logic of the MAX7234 is similar to the MAX7232, but nine bits are always required. As illu- strated in Figure 8, the data bits are only latched if the WATTE input occurs after the ninth data bit has been entered and Data Accepted Output is low. PE/EE/CE/LESCZXVANMAX 7231/32/33/34 Triplexed LCD Decoder/Drivers DATA ELEVENTH CLOCK WITH NO WRITE PULSE RESETS SR + LOGIC >| todi ke 1 ol \ clock INPUT (PER BIT OF DATA) DATA (INPUT DATA ACCEPTED OUTPUT _ | WRITE INPUT i ; RESETS SHIFT REGISTER AND INPUT CONTROL LOGIC WHEN DATA ACCEPTED HIGH LL | DECODES AND STORES OATA, RESETS SHIFT REGISTER AND LOGIC WHEN DATA ACCEPTED Is Low DO NOT CARE i Figure 6. One Digit Timing Diagram for the MAX7232, Writing Both Annunciators. AN1 | AN2 | Boo | BD1] BD2 | BD3 | Ap | Ar | Ac | Aa ENTER ENTER FIRST LAST j MAX7232 WRITE ORDER fe tela fa tel DATA | | ! INPUT j DATA ; INPUT BD1 BD2 DATA DATA VALID VALID DATA 1 ACCEPTED | OUTPUT | | I ( | WRITE | INPUT RESETS SHIFT REGISTER DECODES AND STORES ! ( AND CONTROL LOGIC { DATA, RESETS SHIFT I | WHEN DATA ACCEPTED IS HIGH REGISTER AND LOGIC WHEN DATA ACCEPTED Is LOW DO NOT CARE Figure 7. Input Timing Diagram of the MAX7232. Both Annunciators OFF. MMA KLTriplexed LCD Decoder/Drivers r TENTH CLOCK WITH NO WRITE ' ' PULSE RESETS i aoe a SR AND LOGIC DATA cABex Los Ve INPUT t | Soot | | ( DATA | INPUT DATA VALID | VALID tod! Ht tod! DATA ACCEPTED I | OUTPUT ( bee tet I | twp be | | WRITE INPUT RESETS SHIFT REGISTER { AND CONTROL LOGIC IF | DATA ACCEPTED IS HIGH Do Oy | Dz | Dz | Dg | Ds | Ao | Ar A WRITE ORDER | WRITE WRITE FIRST LAST Figure 8. One Character Input Timing Diagram of the MAX7234. Temperature Compensation Temperature Effects Temperature affects the performance of liquid crystal displays (LCD's) in two ways. As the display tem- perature drops, the response time of the display becomes longer. At very low temperatures, some displays may take several seconds to change to a new character. However, high-speed liquid crystal materials are available for low temperature environ- ments. Temperature has a significant effect on the variation of liquid crystal threshold voltage. The peak voltage (Vp) required to turn on the display has a temperature coefficient of -7 to -14 mV/C for typical liquid crystal materials used in multiplexed LCDs. This means that as the temperature increases, the threshold voltage . PEAK VOLTAGE e PEAK VOLTAGE FOR 10% CONTRAST o -10 \ \VR OECODES AND STORES I REGISTER ANO LOGIC coe D0 NOT CARE WHEN DATA ACCEPTED IS LOW decreases. Figure 9 illustrates the dependence of peak voltage (Vp) on temperature for the same liquid crystal material described in Figure 10. Assuming a fixed value for Vp, OFF segments begin to be visible when the threshold voltage drops below Vp/3. To avoid this problem at high temperature, Vp may be set at a fixed voltage chosen to make the RMS OFF voltage, Vp/3, just below the threshold voltage at the highest temperature expected. This is appropriate where display temperatures do not vary widely. I 100 30 PEAK VOLTAGE 80 FOR 90% CONTRAST 70 (ON) = ee ~ 60 < = 50 a a0 9 30 (OFF) 20 10 0 0 10 20 30 40 50 o 1 2 3 4 AMBIENT TEMPERATURE (C) APPLIED VOLTAGE (Vams) Lu Figure 9. Temperature Dependence of Liquid Crystal Threshold. MAXI/VI_ Figure 10. Applied RMS Voltage vs. Contrast. PE/EE/SE/LECZXVINMAX7231/32/33/34 Triplexed LCD Decoder/Drivers Display Voltage An internal resistor string of three equal value resistors is used to generate the display drive voltages. One end of the string is available at Pin 2 (Vpisp) and the other end is connected to V* on the chip. Pin 2, the users input, allows the display voltage to be optimized for a particular liquid crystal material. Note that Vp should be three times the threshold voltage for the tiquid crystal material used (Vp = Vt ~ Voisp). To avoid device latchup and possible destruction of the chip, never drive Pin 2 below Ground or above V+. Figure 11 illustrates a simple method of generating a display voltage suitable for a particular display. A potentiometer with a maximum value of 200k{2 connected from Pin 2 to Ground gives sufficient range adjustment to suit most displays. Due to the positive temperature coefficient of the resistors on-chip, this method for generating display voltage should be used only in applications where the tem- perature variation of the chip and display will not vary more than +5C (15F). The power supply voltage also effects the display voltage. The chip may be operated at the display voltage with Vpoise connected to Ground in battery powered applications where the display voltage is the same as the battery voltage (typically 3 to 4.5 volts). The inputs of the chip are designed such that they may be driven above Vt without damage. This allows the chip and display to operate at a regulated 3V while its inputs are driven by a microprocessor that is operating at aless well controlled 5V supply. Under no circumstances should the inputs be driven more than 6.5V above Ground. Independent adjustment of both voltage and temperature compensation is illustrated in Figure 12. Temperature compensation is performed by the !CL7663. Another method of setting up a display voltage is ilustrated in Figure 13. The five diodes (1N914 or equivalent), each have a forward drop of approxi- mately 0.65V, with 20 (A) at room temperature. This configuration is suitable for the 3V display using the material properties as shown in Figures 9 and 10. More diodes may be added for higher voltage dis- plays. Each diode has a negative temperature | OPEN 200k.) 2 Voisp 40 +5 ob MAX7231 MAX7234 Figure 11. Simple Display Voltage Adjustment. 10 oe coefficient of -2mV/C (5 in series gives -10mV/C). Consequently, this circuit will provide reasonable temperature compensation. l +5V J veiw Yours rT t vt Loic Vourz z SYSTEM, > PROCESSOR, tame 4 etc. VseT 300K: Vie Hn MAX7233 > > GND 27MO z j Tt t L Vpisp | = MIAXI/VI GND | ICL7663 DATA BUS Figure 12. Flexible Temperature Compensation. +NS14 2 Ypise 40 | +sv DIODES 38 MAX7231 ~ MAX7234 40k) Figure 13. Diode String VDISP Generator. Triplexing The connection diagram for a typical 7-segment display font with 2 annunciators is illustrated in Figure 15. The MAX7231 and MAX7232 (A and B suffix versions) numeric display drivers use this configuration. The voltage waveforms of the com- mon lines and one segment line are illustrated in Figure 14. The Y segment line has been chosen as an example. This line intersects with COM1 to form the A segment, COM2 to form the G segment, and COMS to form the D segment. Four different ON/OFF combinations of the A, G" and D segments and their corresponding waveforms of the Y segment line are illustrated in Figure 14. The schematic diagram in Figure 16 shows that each intersection acts as a capacitance from segment line to common line. Figure 17 illustrates the voltage across the G segment for the same four combina- tions of ON/OFF segments shown in Figure 14. The RMS voltage across the segment determines the degree of polarization for the liquid crystal material and thus the contrast of the segment. The __ MMAXLMRMS OFF voltage is always Vp/3, whereas the RMS ON voltage is always 1.92 Ve/3. This is illustrated in Figure 17. The ratio of RMS ON to OFF voltage is fixed at 1.92 for a triplexed liquid crystal display. Contrast vs. applied RMS voltage is shown in Figure 10. With a Vp of 3.1V, the RMS ON voltage is 2.4V and the RMS OFF voltage is 1.1V. The OFF seg- ment will have a contrast of less than 5%, while the ON segments will have greater than 85% contrast. i | oy | 2 | 3 | oy | bz ft os | | COMMON LINE WAVEFORMS ON CHIP RESISTOR STRING ve ~ 75K ~ 75KLL ~ 7aKQ) Voisp # PIN2 INPUT TYPICAL SEGMENT LINE WAVEFORMS (SEGMENT LINE Y") NOTE: 4, a. 63 COMMON HIGH WITH RESPECT TO SEGMENT. $1,7.3 COMMON LOW WITH RESPECT TO SEGMENT. COM 1 ACTIVE DURING 1 AND 44, COM 2 ACTIVE DURING $2 AND do: | COM 3 ACTIVE DURING 3 AND 3 Figure 14. Display Voltage Waveforms. SEGMENT LINE CONNECTION COMMON LINE CONNECTION Figure 15. Connection Diagrams for Typical 7-Segment Displays. MAALVI_.. Triplexed LCD Decoder/Drivers SEGMENT LINES - a com1 cOM2 NS COM3 r a ols Dt DP, | | Figure 16. Schematic of Display. Vg = Va - Vcom 2 (DIFFERENCE BETWEEN SEGMENT LINE b AND COM 2 VOLTAGES) | or | o2 | os | or | be | oa: | Vp > * - Voise +p COMMON AND SEGMENT PEAK TO. PEAK VOLTAGE ALL OFF Q Vrms - % - Vrms OFF aON v g,d OFF - +t VAMS OFF ag ON WV S OFF 0 Vrms - a ap: Yams on AL Vp VRMs =~ - Yams ON vo 3 Vams ON VOLTAGE CONTRAST RATIO = a Vas Orr /3 *92 NOTE: 0). 9, 63 COMMON HIGH WITH RESPECT TO SEGMENT. by ba @3 GOMMON LOW WITH RESPECT TO SEGMENT. COM 1 ACTIVE DURING &1 AND dy COM 2 ACTIVE DURING 62 AND 02 COM 3 ACTIVE DURING 3 AND 3: Figure 17. Voltage Waveforms on Segment g (Vg). PE/EE/ZE/LESCLXVINMAX 7231/32/33/34 Triplexed LCD Decoder/Drivers ___ Output Codes and Display Fonts The MAX7231 and MAX7232 numeric display drivers are programmed to drive 7-segment displays plus 2 annunciators per digit. Refer to Table 1 for annun- ciator input controls. The display connections for one digit are shown in Figure 18. Both annunciators are placed on COM3 on the A and "B suffix devices. The A devices offer a hexadecimal 7-segment output, while the B devices offer Code B outputs. This is illustrated in Table 2. Figure 19 illustrates the C device configuration. The Left Table 1: Annunciator Decoding | CODE | INPUT DISPLAY OUTPUT [an | AN MAX7231 A/B MAX7231C 2 1 MAX7232 A/B MAX7232C BOTH LH ANNUNCIATORS | ANNUNCIATOR ON COM 3 CoM 1 RH ANNUNCIATOR COM 3 0 0 a a 0 1 o Gg, 1 0 a g 1 1 6. 4 Table 2: Binary Data Decoding (MAX7231/MAX7232) CODE DISPLAY INPUT OUTPUT BD BD BD BD CODE 3 2 1 0 HEX B 0 0 0 0 { o 0 0 0 1 ] i 0 0 1 0 e 2 0 0 1 1 3 3 0 1 0 0 Y uy 0 1 0 1 S 5 ) 1 1 0 & & 0 1 1 1 7 7 | 1 0 0 0 a 8 4 0 0 1 9 q 1 0 1 0 A = 1 9) 1 1 b E 1 1 0) 0 H 1 1 0 1 d L 1 1 1 0 E Pp 1 1 1 1 - BLANK hand annunciator is placed on COM1 (AN2) and the right hand annunciator (usually a decimal point) is placed on COM3 (AN1). Only a Code B output is offered for the C devices. Both the MAX7233 and MAX7234 are supplied in A and B versions, decoding an ASCII 6-bit subset to an 18-segment display, with 16 flag segments and 2 dots. Figure 20 illustrates the layout for a single character. The A devices have numbers which are half-width and the B devices have full-width num- bers. Refer to Table 3 for output decoding. Table 3: Data Decoding 18 Segment (MAX7233/MAX7234) DISPLAY OUTPUT D5 D4 0,0 0,1 1,0 1,1 CODE INPUT D3 | D2 | D1 Qg So afajafoafejoafjalalasjaso;olo]o;/o);o 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 alalolo;s/Aalajajof-=|/-;ojos/a;/Aa;/o/o a=/O/A}/O/=;/0};]}/O0/]=/0/+-/O];/=;0;+; cee MAASTable 4: Address Decoding (MAX7231/7232) Triplexed LCD Decoder/Drivers DISPLAY x Y z CODE INPUT OUTPUT Max | a7 | 7232 com1 ONLY DIGIT <i> | A3 A2 Al AO SELECTED | come - o | 0 0 0 Dt AN an | 1 1 2 0 0 0 1 D2 coms | 0 | 0 1 0 D3 SEGMENT LINE CONNECTIONS COMMON LINE CONNECTIONS 0 0 1 1 D4 BOTH ANNUNCIATORS ON COMMON #3 0 1 0 0 DS (AT BOTTOM OF CHARACTER) {LH (A" AND B SUFFIX VERSIONS) Oo | 3 fs) 1 D6 i | L 0 | 1 | Q ob? Figure 18. Display Fonts for MAX7231 and 7232. QO | 1 1 1 Dg {Suffix Versions A and "B). 1 | 0 0 0 Dg 1 0 0 1 D10 1 0 1 0 NONE x Y 1 0 1 1 NONE 1 + 1 0 0 NONE _ 1 | 4 o | 4 NONE 1 1 1 0 NONE | 1 1 1 | 14] NONE Table 5: Address Decoding (MAX7233/7234) | CODE DIGIT | | INPUT | SELECTED | MAX | | 7234 __ONLY A2 Al AO 0 | 0 0.) D1 o | o 1 D2 | 0 1 0 D3 | 0 1 1 D4 1 0 o. | D5 1 0 1 NONE 7 Fi 0 NONE | 1) 4 1 NONE MIAAKI/VE SEGMENT LINE CONNECTIONS COMMON LINE CONNECTIONS LH ANNUNCIATOR ON COMMON #1 (TOP) (AN 2) RAH ANNUNCIATOR ON COMMON #3 (BOTTOM) (AN 1) "C SUFFIX DEVICES * ANNUNCIATORS CAN BE: [STOP] [GO], AA 4 -anROWws THAT POINT TO INFORMATION PRINTED AROUND THE DISPLAY IN THE LIQUID CRYSTAL DISPLAY. OPENING, ETC., WHATEVER THE DESIGNER CHOOSES TO INCORPORATE Figure 19. Display Fonts for MAX7231 and 7232. (Suffix Version C"'). u vVwx Zz com1 | | aN | SEGMENT LINE CONNECTIONS COMMON LINE CONNECTIONS Figure 20. Display Fonts for MAX7233 and 7234. (18-Segment Alphanumeric). ee ee ee ND PE/EE/EE/LESCLXVNMAX 7231/32/33/34 Triplexed LCD Decoder/Drivers NZENENVENY NI] SK YN ZN UN AN VN AN ZN MAX7233 MAX7233 CS$2 csi Ar Ae Do-Ds cs2 cs1 Ai Ao Do-Ds, F +5V > n. > > TO Gg ON S 750K! 2 i 22 i 4 ea EPROM 9 2 7 8 4 ve MC 140498 4k0. +e OR cp404g) RC 2 : hy. 8 > OAF > 4 K,. - | maxim <r 1CM7240 8 - 16 hy. +5Y TRIG 32 RESET 64 Ul GND 128 As Ag As Az Ar Ap Qe-O5 Ag Ay 2708 Os As C1 TBO RC 1 MAXIM , 1CM7240 4 4 +5V -J TRIG Il RESET ' GND | Figure 21. EPROM-Coded Message System. This circuit cycles through a message coded in the EPROM, pausing at the end of each line, or whenever coded on Og. 14 | MAXIM!Triplexed LCD Decoder/Drivers i t 1 Mc6802 , =7 MICROPROCESSOR mMowIce te ru oe WITH RAM UNRIeEOO 1 CTR oa v ra TEMPERATURE Lt J 4e COMPENSATION - 27 27 27 27 ve 1218 Ves Veo MAX7233B 2N2222 Voisp aMHz t t tT ADJ. ve 39EXTAL Vcc 35f- V* 200K! } o se | vwefaove 3290 2 4 4 RE 36 - vr DISPLAY V TL __I ae ra GND Fasano Bet MAx72998 | Maxz2998 | 4 Maxzea3B | DATA ADD C52 40 RESET 30:35 373839. 40K.) ~~ > nALT tera +1 6+2 44 bet24+4 6 b2}1 ve 2 HALT para ho Ao oc. Ao Ao | a. = | TI 3MA 8 DeDs ay | Az Do-Ds ao [As Ds a, [Aa [Dos a, [As = = 10k) ol ga 26-33 [7 | TO OTHER ADD 9-20 -{ PARTS OF SYSTEM | 478A gus 22-25] 16 2-5, 16, 30-33, 38-40 74L $00 E37 - rN, AWA we | v, = MO ag ace 1 P7 DISPLAY STORAGE ENABLE | ADDRESS 7 21-28 Ly Z OTHER 1/0 TRO. RAW MA 845 on , 4 34 5 ara | 2 | Daa [DATA Cp24q[@ | CONTROL CTO 19 }>| 6CSO ETC 18 }< } COUNTER/TIMER __Jraw CTE 17 36_Vss | ina] 1 mcesss | > ROM-I/0-TIMER | Figure 22. MC6802 Microprocessor with 16 Character 16 Segment ASCII Liquid Crystal Display. PIN (1) 045, PIN (1) (DENT 050 001 B.C 045, + + 127.025 - 035 AAD 0.090 __..____ 2.070. oe (1.943) r / Vee 1431 688} 0.070 (2.286) (52.578) ' . ' a : (7a) RAD poon ponooooo. : : 0,600 - 0.620 MN 5 0.550 20.005 a 045 L I (15.240 - 15.748) 5) MAXI (13.97020.127) (1443) (1.43) I 0.030 [! 1 (6.762) COT ererererer eres ~ 250, ko 00s Le 9 1.270 } 620 0051575 127) 0.10020.010 0.15020.005 Ll | Gsapso7sa) 7] f (3.81010.127) 1 TYP (16.51 127) 2 BC. OF BEND RADII rit \ \ \ \ + 0.025 0.625 9015 ! 15.8757 0-639 \ (0.009 -0.015 | oraso.a0s . . (0.45720.076) (3.175) (0.508) | 0.07520,015 tT (1.90520.381) 86 94 TYP TP (0.229 -0.381) 40 Lead Plastic (PL) @jn ~ 100C/W, yc = 45C/W mt 0.125 0.020 Q10 MAX (660) (254) PARTING MIN MIN 1 LINE . , 4 "a _ _ Y 10 MAK = = 021 (553) 25a) 890 - 005 e102 (2.59) * 17526 - 327 - - - 170 (4.318) 44 Lead Plastic Chip Carrier (Quad Pack) (Q) MAMALSVI_... 15 PE/EE/SE/LESCLXVNMAX 7231/32/33/34 Triplexed LCD Decoder/Drivers a t$U_C#i in Configuration | g Top View rok g 254 S 289 a = 225 225 ao w 225 22 2 3839 bese 66 0 #422 3 IF 485 1z[7 [39] bs 1277] 139] 5U ty[a] [38] D4 (8) aa] sv 1x[9] 137] D3 1x fe] 5w 1w [0] 36] D2 iw [10] [36] 5x qv [11] 135] D1 Wi] 135] SY NC AF 34) Nic ne G2] 34] NC 1u [3] 133] po qu fia [3a] 5z 2z [14] 132] 4U 22 [14] [32] 4u ay [15] st]av 2y [15] 31] av 2x [6] 30] aw 2x [6] 730] aw aw [7] 29] 4x 2w [7] [29] 4x RRSES $ BRARS __Chip Topography - | MAX?7232 | Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 16 Maxim Integrated Products, 120 San Gabrief Drive, Sunnyvale, CA 94086 (408) 737-7600 1995 Maxim Integrated Products Printed USA MAXUM is a registered tradernark of Maxim Integrated Products