74AC573SC - Fairchild Semiconductor

November 1988

Revised October 1999

74AC573 • 74ACT573 Octal Latch with 3-STATE Outputs

74AC573 • 74ACT573

Octal Latch with 3-STATE Outputs

General Descript ion

The 74AC5 73 and 74A CT 57 3 ar e hi g h-s pee d octal latch es

with buffered common Latch Enable (LE) and buffered

common Output Enable (OE) inputs.

The 74AC573 and 74ACT573 are functionally identical to

the 74AC373 and 74ACT373 but with inputs and outputs

on opposite sides.

Features

■ICC and IOZ reduced by 50%

■Inputs and outputs on op posite sides of package allow-

ing easy interface with microprocessors

■Useful as input or output port for microprocessors

■Functionally identical to 74AC373 and 74ACT373

■3-STATE outputs for bus interfacing

■Outputs source/sink 24 mA

■74ACT573 has TTL-compatible inputs

Ordering Code:

Device a ls o av ailable in Tape and R eel. Spec ify by appending s uffix let te r “X” to the or dering co de.

Logic Symbols

IEEE/IEC

Connection Diagram

Pin Descriptions

FACT is a tradem ark of F airchild Semicon ductor C orporation.

Order Number Package Number Package Description

74AC573SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS--013, 0.300” Wide Body

74AC573SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74AC573MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

74AC573PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

74ACT573SC M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS--013, 0.300” Wide Body

74ACT573SJ M20D 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74ACT573MTC MTC20 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

74ACT573PC N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Pin Names Description

D0–D7Data Inputs

LE Latch Enable Input

OE 3-STATE Output Enable Input

O0–O73-STATE Latch Outputs

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74AC573 • 74ACT573

Functional Description

The 74 AC573 and 74ACT 573 co ntain e ight D -type latches

with 3- STATE output bu ffers. When the Latch Enable (LE)

input is HI GH, data on th e Dn inputs enters the latch es. In

this c ondition the latches are t ransparent, i.e., a latch out-

put will change state each time its D-type input changes.

When LE is LOW the latches store the information that was

present on the D-type inputs a setup time preceding the

HIGH-to-LOW transition of LE. The 3-STATE buffers are

controlled by the Output Enable (OE) input. When OE is

LOW, the buffers are ena bled. When OE is HIGH the buff-

ers are in the high impedance mode but this does not inter-

fere with entering new data into the latches.

Truth Table

H = HIGH Voltage

L = LOW Voltage

Z = High Impedance

X = Immateri al

O0 = Previo us O0 bef ore HIGH -to-LOW t ransition of Latch Enable

Logic Diagram

Pleas e note that this diagram is provided only for t he underst anding o f lo gic operat ions and sh ould not be us ed to estim ate propa gation delays.

Inputs Outputs

OE LE D On

LHH H

LHL L

LLX O

HXX Z

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74AC573 • 74ACT573

Absolute Maximum Ratings(Note 1) Recommended Operating

Conditions

Note 1: Absolute maximum ratings are those values beyond which damage

to the device may occur. The databook specifications should be met, with-

out exception, to ensure that the system design is reliable over its power

supply, tempera ture, and output /input lo ading variabl es. Fair child do es not

recomm end operation of FACT circ uit s outside da t abook specificat ions.

DC Electrical Characteristics for AC

Note 2: All outpu ts loaded; t hreshol ds on input as s oc iated with outpu t un der test.

Note 3: IIN and ICC @ 3.0V are guarant eed to be les s t han or equal to the re s pective lim it @ 5. 5V VCC.

Note 4: Maximum test duration 2.0 ms, one output loaded at a time.

Supply Voltage (VCC)−0.5 V to +7.0V

DC Input Diode Current (IIK)

VI = −0.5V −20 mA

VI = VCC + 0.5V +20 mA

DC Input Voltage (VI)−0.5V to VCC + 0.5V

DC Output Diode Current (IOK)

VO = −0.5V −20 mA

VO = VCC + 0.5V +20 mA

DC Output Voltage (VO)−0.5V to VCC + 0.5V

DC Output Source

or Sink Current (IO)±50 mA

DC VCC or Ground Current

per Output Pin (ICC or IGND)±50 mA

Storage Temperature (TSTG)−65°C to +150°C

Junction Temperature (TJ)

(PDIP) 140°C

Supply Voltage (VCC)

AC 2.0V to 6.0V

ACT 4.5V to 5.5V

Input Voltage (VI)0V to V

Output Voltage (VO)0V to V

Operating Temperature (TA)−40°C to +85°C

Minimum Input Edge Rate (∆V/∆t)

AC Devices

VIN from 30% to 70% of VCC

VCC @ 3.0V, 4.5V, 5.5V 125 mV/ns

ACT Devices

VIN from 0.8V to 2.0V

VCC @ 4.5V, 5.5V 125 mV/ns

Symbol Parameter VCC TA = +25°CT

A = −40°C to +85°CUnits Conditions

(V) Typ Guaranteed Limits

VIH Minimum HIGH Level 3.0 1.5 2.1 2.1 VVOUT = 0.1V

Input Voltage 4.5 2.25 3.15 3.15 or VCC − 0.1V

5.5 2.75 3.85 3.85

VIL Maximum LOW Level 3.0 1.5 0.9 0.9 VVOUT = 0.1V

Input Voltage 4.5 2.25 1.35 1.35 or VCC − 0.1V

5.5 2.75 1.65 1.65

VOH Minimum HIGH Level 3.0 2.99 2.9 2.9 VIOUT = −50 µA

Output Voltage 4.5 4.49 4.4 4.4

5.5 5.49 5.4 5.4

VIN = VIL or VIH

3.0 2.56 2.46 IOH = −12 mA

4.5 3.86 3.76 IOH = −24 mA

5.5 4.86 4.76 IOH = −24 mA (Note 2)

VOL Maximum LOW Level 3.0 0.002 0.1 0.1 VI

OUT = 50 µAOutput Voltage 4.5 0.001 0.1 0.1

5.5 0.001 0.1 0.1

VIN = VIL or VIH

3.0 0.36 0.44 IOL = 12 mA

4.5 0.36 0.44 IOL = 24 mA

5.5 0.36 0.44 IOL = 24 mA (Note 2)

IIN (Note 3) Maximum Input Leakage Current 5.5 ±0.1 ±1.0 µAV

I = VCC, GND

IOLD Minimum Dynamic 5.5 75 mA VOLD = 1.65V Max

IOHD Output Current (Note 4) 5.5 −75 mA VOHD = 3.85V Min

ICC Maximum Quiescent 5.5 4.0 40.0 µAV

IN = VCC or GND

(Note 3) Supply Current

IOZ Maxim um 3-STATE 5.5 ±0.25 ±2.5 µAVI (OE) = VIL, VIH

Leakage Current VI = VCC, GND

VO = VCC, GND

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74AC573 • 74ACT573

AC Electrical Characteristics for AC

Note 5: Voltage Range 5.0 is 5.0V ± 0.5V

Voltage Range 3. 3 is 3. 3V ± 0.3V

AC Operating Requirements for AC

Note 6: Voltage Range 5. 0 is 5. 0V ± 0.5V

Voltage Range 3. 3 is 3. 3V ± 0.3V

VCC TA = +25°CT

A = −40°C to +85°C

Symbol Parameter (V) CL = 50 pF CL = 50 pF Units

(Note 5) Min Typ Max Min Max

tPHL Propagation Delay 3.3 0.5 8.5 10.5 2.5 11.0 ns

tPLH Dn to On5.0 1.5 5.5 7.0 1.5 7.5

tPLH Propagation Delay 3.3 2.5 8.5 12.0 2.5 12.5 ns

tPHL LE to On5.0 2.0 6.0 8.0 2.0 8.5

tPZL Output Enable Time 3.3 2.5 8.5 13.0 2.5 13.5 ns

tPZH 5.0 1.5 6.0 8.5 1.5 9.0

tPHZ Output Disable Time 3.3 1.0 9.0 14.5 1.0 15.0 ns

tPLZ 5.0 1.0 6.0 9.5 1.0 10.0

VCC TA = +25°CT

A = −40°C to +85°C

Symbol Parameter (V) CL = 50 pF CL = 50 pF Units

(Note 6) Typ Guaranteed Minimum

tSSetup Time, HIGH or LOW 3.3 0 3.0 3.0 ns

Dn to LE 5.0 0 3.0 3.0

tHHold Time, HIGH or LOW 3.3 0 1.5 1.5 ns

Dn to LE 5.0 0 1.5 1.5

tWLE Pulse Width, HIGH 3.3 2.0 4.0 4.0 ns

5.0 2.0 4.0 4.0

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74AC573 • 74ACT573

DC Electrical Characteristics for ACT

Note 7: All outpu ts loaded; t hreshol ds on input as s oc iated with outpu t un der test.

Note 8: Maximum test duration 2.0 ms, one output loaded at a time.

AC Electrical Characteristics for ACT

Note 9: Voltage Range 5. 0 is 5. 0V ± 0.5 V

Symbol Parameter VCC TA = +25°CT

A = −40°C to +85°CUnits Conditions

(V) Typ Guaranteed Limits

VIH Minimum HIGH Level 4.5 1.5 2.0 2.0 VVOUT = 0.1V

Input Voltage 5.5 1.5 2.0 2.0 or VCC − 0.1V

VIL Maximum LOW Level 4.5 1.5 0.8 0.8 VVOUT = 0.1V

Input Voltage 5.5 1.5 0.8 or VCC − 0.1V

VOH Minimum HIGH Level 4.5 4.49 4.4 4.4 VI

OUT = −50 µA

Output Voltage 5.5 5.49 5.4 5.4 VIN = VIL or VIH

4.5 3.86 3.76 V IOH = −24 mA

5.5 4.86 4.76 IOH = −24 mA (Note 7)

VOL Maximum LOW Level 4.5 0.001 0.1 0.1 VI

OUT = 50 µA

Output Voltage 5.5 0.001 0.1 0.1 VIN = VIL or VIH

4.5 0.36 0.44 V IOL = 24 mA

5.5 0.36 0.44 IOL = 24 mA (Note 7)

IIN Maximum Input 5.5 ±0.1 ±1.0 µAV

I = VCC, GND

Leakage Current

IOZ Maximum 3-STATE 5.5 ±0.25 ±2.5 µAVI = VIL, VIH

Leakage Current VO = VCC, GND

ICCT Maximum 5.5 0.6 1.5 mA VI = VCC − 2.1V

ICC/Input

IOLD Minimum Dynamic 5.5 75 mA VOLD = 1.65V Max

IOHD Output Current (Note 8) 5.5 −75 mA VOHD = 3.85V Min

ICC Maximum Quiescent 5.5 4.0 40.0 µAV

IN = VCC or GND

Supply Curre nt

VCC TA = +25°CT

A = −40°C to +85°C

Symbol Parameter (V) CL = 50 pF CL = 50 pF Units

(Note 9) Min Typ Max Min Max

tPLH Propagation Delay 5.0 2.5 6.0 10.5 2.0 12.0 ns

tPHL Dn to On

tPLH Propagation Delay 5.0 3.0 6.0 10.5 2.5 12.0 ns

LE to On

tPHL Propagation Delay 5.0 2.5 5.5 9.5 2.0 10.5 ns

LE to On

tPZH Output Enable Time 5.0 2.0 5.5 10.0 1.5 11.0 ns

tPZL Output Enable Time 5.0 1.5 5.5 9.5 1.5 10.5 ns

tPHZ Output Disable Time 5.0 2.5 6.5 11.0 1.5 12.5 ns

tPLZ Output Disable Time 5.0 1.5 5.0 8.5 1.0 9.5 ns

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74AC573 • 74ACT573

AC Operating Requirements for ACT

Note 10: Voltage Range 5.0 is 5.0V ± 0.5V

Capacitance

VCC TA = +25°CT

A = −40°C to +85°C

Symbol Parameter (V) CL = 50 pF CL = 50 pF Units

(Note 10) Typ Guaranteed Minimum

tSSetup Time, HIGH or LOW 5.0 1.5 3.0 3.5 ns

Dn to LE

tHHold Time, HIGH or LOW 5.0 −1.5 0 0 ns

Dn to LE

tWLE Pulse Width, HIGH 5.0 2.0 3.5 4.0 ns

Symbol Parameter Typ Units Conditions

CIN Input Capacitance 5.0 pF VCC = OPEN

CPD Power Dissipation Capacitance for AC 25.0 pF VCC = 5.0V

for ACT 42.0

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74AC573 • 74ACT573

Physical Dimensions inches (millimeters) unless otherwise noted

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body

Package Number M20B

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74AC573 • 74ACT573

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Sma ll Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M20D

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74AC573 • 74ACT573

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Packag e Num be r MTC 20

www.fairchildsemi.com 10

74AC573 • 74ACT573 Octal Latch with 3-STATE Outputs

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide

Package Number N20A

Fairchild does no t assume any responsibility for use of any circuitry de scribed, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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