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FEATURES
APPLICATIONS
DESCRIPTION/ORDERING INFORMATION
DAC5675-EP
SGLS381A – OCTOBER 2006 – REVISED OCTOBER 2006
14-Bit 400-MSPS Digital-to-Analog Converter
•Power Dissipation: 660 mW atf
CLK
= 400 MSPS, f
OUT
= 20 MHz•400-MSPS Update Rate
•Package: 48-Pin PowerPAD™•Controlled Baseline
Thermally-Enhanced Thin Quad Flat Pack– One Assembly
(HTQFP) T
JA
= 29.1 °C/W– One Test Site– One Fabrication Site•Extended Temperature Performance of –55 °C
•Cellular Base Transceiver Station Transmitto 125 °C
Channel:
– CDMA: WCDMA, CDMA2000, IS-95•Enhanced Diminishing ManufacturingSources (DMS) Support
– TDMA: GSM, IS-136, EDGE/GPRS– Supports Single-Carrier and Multicarrier•Enhanced Product-Change Notification
Applications•LVDS-Compatible Input Interface
•Test and Measurement: Arbitrary Waveform•Spurious-Free Dynamic Range (SFDR) to
GenerationNyquist
•Military Communications– 69 dBc at 70 MHz IF, 400 MSPS•W-CDMA Adjacent Channel Power Ratio(ACPR)
– 73 dBc at 30.72-MHz IF, 122.88 MSPS– 71 dBc at 61.44-MHz IF, 245.76 MSPS•Differential Scalable Current Outputs: 2 mAto 20 mA•On-Chip 1.2-V Reference•Single 3.3-V Supply Operation
The DAC5675 is a 14-bit resolution high-speed digital-to-analog converter (DAC). The DAC5675 is designed forhigh-speed digital data transmission in wired and wireless communication systems, high-frequency direct-digitalsynthesis (DDS), and waveform reconstruction in test and measurement applications. The DAC5675 hasexcellent spurious-free dynamic range (SFDR) at high intermediate frequencies, which makes it well-suited formulticarrier transmission in TDMA- and CDMA-based cellular base transceiver stations (BTSs).
The DAC5675 operates from a single-supply voltage of 3.3 V. Power dissipation is 660 mW atf
CLK
= 400 MSPS, f
OUT
= 70 MHz. The DAC5675 provides a nominal full-scale differential current output of 20mA, supporting both single-ended and differential applications. The output current can be directly fed to the loadwith no additional external output buffer required. The output is referred to the analog supply voltage AV
DD
.
The DAC5675 comprises a low-voltage differential signaling (LVDS) interface for high-speed digital data input.LVDS features a low differential voltage swing with a low constant power consumption across frequency,allowing for high-speed data transmission with low noise levels; that is, with low electromagnetic interference(EMI). LVDS is typically implemented in low-voltage digital CMOS processes, making it the ideal technology forhigh-speed interfacing between the DAC5675 and high-speed low-voltage CMOS ASICs or FPGAs. TheDAC5675 current-source-array architecture supports update rates of up to 400 MSPS. On-chip edge-triggeredinput latches provide for minimum setup and hold times, thereby relaxing interface timing.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of TexasInstruments semiconductor products and disclaimers thereto appears at the end of this data sheet.PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright © 2006, Texas Instruments IncorporatedProducts conform to specifications per the terms of the TexasInstruments standard warranty. Production processing does notnecessarily include testing of all parameters.
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DAC5675-EP
SGLS381A – OCTOBER 2006 – REVISED OCTOBER 2006
The DAC5675 has been specifically designed for a differential transformer-coupled output with a 50- Ωdoubly-terminated load. With the 20-mA full-scale output current, both a 4:1 impedance ratio (resulting in anoutput power of 4 dBm) and 1:1 impedance ratio transformer (–2 dBm) is supported. The last configuration ispreferred for optimum performance at high output frequencies and update rates. The outputs are terminated toAVDD and have voltage compliance ranges from AV
DD
– 1 to AV
DD
+ 0.3 V.
An accurate on-chip 1.2-V temperature-compensated bandgap reference and control amplifier allows the user toadjust this output current from 20 mA down to 2 mA. This provides 20-dB gain range control capabilities.Alternatively, an external reference voltage may be applied. The DAC5675 features a SLEEP mode, whichreduces the standby power to approximately 18 mW.
The DAC5675 is available in a 48-pin PowerPAD™ thermally-enhanced thin quad flat pack (HTQFP). Thispackage increases thermal efficiency in a standard size IC package. The device is specified for operation overthe military temperature range of –55 °C to 125 °C.This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled withappropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may bemore susceptible to damage because very small parametric changes could cause the device not to meet its publishedspecifications.
ORDERING INFORMATION
(1)
PACKAGE PACKAGE PACKAGE ORDERING TRANSPORTPRODUCT
LEAD DESIGNATOR MARKING NUMBER MEDIA, QUANTITY
DAC5675MPHPREP Tape and reel, 1000DAC5675-EP 48 HTQFP PHP DAC5675-EP
DAC5675MPHPEP Tray, 250
(1) For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet.
TQFP-48 PACKAGE THERMAL CHARACTERISTICS
SAME PACKAGE PowerPADPARAMETER FORM WITHOUT CONNECTED TOPowerPAD PCB THERMAL PLANE
(1)
R
θJA
Thermal resistance, junction to ambient
(1) (2)
108.71 °C/W 29.11 °C/WR
θJC
Thermal resistance, junction to case
(1) (2)
18.18 °C/W 1.14 °C/W
(1) Airflow is at 0 LFM (no airflow).(2) Specified with the PowerPAD bond pad on the backside of the package soldered to a 2-oz CU plate PCB thermal plane
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Bandgap
Reference
1.2V
Control Amp
Current
Source
Array
Output
Current
Switches
DAC
Latch
+
Drivers
Decoder
Input
Latches
LVDS
Input
Interface
Clock Distribution
SLEEP
EXTIO
BIASJ
D[13:0]A
D[13:0]B
CLK
CLKC
AVDD(4x) AGND(4x) DVDD(2x) DGND(2x)
14
14
DAC5675-EP
DAC5675-EP
SGLS381A – OCTOBER 2006 – REVISED OCTOBER 2006
FUNCTIONAL BLOCK DIAGRAM
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Absolute Maximum Ratings
DAC5675-EP
SGLS381A – OCTOBER 2006 – REVISED OCTOBER 2006
over operating free-air temperature range (unless otherwise noted)
(1)
DAC5675-EP UNIT
AV
DD
(2)
–0.3 to 3.6Supply voltage range DV
DD
(3)
–0.3 to 3.6 VAV
DD
to DV
DD
–3.6 to 3.6Voltage between AGND and DGND –0.3 to 0.5 VCLK, CLKC
(2)
–0.3 to AV
DD
+ 0.3 VDigital input D[13:0]A, D[13:0]B
(3)
, SLEEP, DLLOFF –0.3 to DV
DD
+ 0.3 VIOUT1, IOUT2
(2)
–1 to AV
DD
+ 0.3 VEXTIO, BIASJ
(2)
–1 to AV
DD
+ 0.3 VPeak input current (any input) 20 mAPeak total input current (all inputs) –30 mAOperating free-air temperature range, T
A
–55 to 125 °CStorage temperature range –65 to 150 °CLead temperature 1,6 mm (1/16 in) from the case for 10 s 260 °C
(1) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolutemaximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of thedevice at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure toabsolute-maximum-rated conditions for extended periods may affect device reliability.(2) Measured with respect to AGND(3) Measured with respect to DGND
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DC Electrical Characteristics
DAC5675-EP
SGLS381A – OCTOBER 2006 – REVISED OCTOBER 2006
over operating free-air temperature range, typical values at 25 °C, AV
DD
= 3.3 V, DV
DD
= 3.3 V, I
O(FS)
= 20 mA (unlessotherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Resolution 14 Bit
DC Accuracy
(1)
INL Integral nonlinearity –4 ±1.5 4.6 LSBT
MIN
to T
MAXDNL Differential nonlinearity –2 ±0.6 2.2 LSBMonotonicity Monotonic 12b Level
Analog Output
I
O(FS)
Full-scale output current 2 20 mAAV
DD
= 3.15 V to 3.45 V,Output compliance range AV
DD
– 1 AV
DD
+ 0.3 VI
O(FS)
= 20 mAOffset error 0.01 %FSRWithout internal reference –10 5 10Gain error %FSRWith internal reference –10 2.5 10Output resistance 300 k ΩOutput capacitance 5 pF
Reference Output
V
(EXTIO)
Reference voltage 1.17 1.23 1.29 VReference output current
(2)
100 nA
Reference Input
V
(EXTIO)
Input reference voltage 0.6 1.2 1.25 VInput resistance 1 M ΩSmall-signal bandwidth 1.4 MHzInput capacitance 100 pF
Temperature Coefficients
Offset drift 12 ppm of FSR/ °C∆V
(EXTIO)
Reference voltage drift ±50 ppm/ °C
Power Supply
AV
DD
Analog supply voltage 3.15 3.3 3.6 VDV
DD
Digital supply voltage 3.15 3.3 3.6 VI
(AVDD)
Analog supply current
(3)
115 mAI
(DVDD)
Digital supply current
(3)
85 mASleep mode 18P
D
Power dissipation mWAV
DD
= 3.3 V, DV
DD
= 3.3 V 660 900APSRR –0.9 ±0.1 0.9Analog and digital
AV
DD
= 3.15 V to 3.45 V %FSR/Vpower-supply rejection ratioDPSRR –0.9 ±0.1 0.9
(1) Measured differential at I
OUT1
and I
OUT2
: 25 Ωto AV
DD(2) Use an external buffer amplifier with high impedance input to drive any external load.(3) Measured at f
CLK
= 400 MSPS and f
OUT
= 70 MHz
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AC Electrical Characteristics
DAC5675-EP
SGLS381A – OCTOBER 2006 – REVISED OCTOBER 2006
over operating free-air temperature range, typical values at 25 °C, AV
DD
= 3.3 V, DV
DD
= 3.3 V, I
O(FS)
= 20 mA, differentialtransformer-coupled output, 50- Ωdoubly-terminated load (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Analog Output
f
CLK
Output update rate 400 MSPSt
s(DAC)
Output setting time to 0.1% Transition: code x2000 to x23
FF
12 nst
PD
Output propagation delay 1 nst
r(IOUT)
Output rise time, 10% to 90% 2 nst
f(IOUT)
Output fall time, 90% to 10% 2 nsIOUT
FS
= 20 mA 55Output noise pA/ √HzIOUT
FS
= 2 mA 30
AC Linearity
f
CLK
= 100 MSPS, f
OUT
= 19.9 MHz 73f
CLK
= 160 MSPS, f
OUT
= 41 MHz 72f
CLK
= 200 MSPS, f
OUT
= 70 MHz 68THD Total harmonic distortion dBcf
OUT
= 20.1 MHz 72f
CLK
= 400 MSPS f
OUT
= 70 MHz 71f
OUT
= 140 MHz 58f
CLK
= 100 MSPS, f
OUT
= 19.9 MHz 73f
CLK
= 160 MSPS, f
OUT
= 41 MHz 73f
CLK
= 200 MSPS, f
OUT
= 70 MHz 70Spurious-free dynamic rangeSFDR dBcto Nyquist
f
OUT
= 20.1 MHz 73f
CLK
= 400 MSPS f
OUT
= 70 MHz 74f
OUT
= 140 MHz 60f
CLK
= 100 MSPS, f
OUT
= 19.9 MHz 88f
CLK
= 160 MSPS, f
OUT
= 41 MHz 87f
CLK
= 200 MSPS, f
OUT
= 70 MHz 82Spurious-free dynamic rangeSFDR dBcwithin a window, 5-MHz span
f
OUT
= 20.1 MHz 87f
CLK
= 400 MSPS f
OUT
= 70 MHz 82f
OUT
= 140 MHz 75f
CLK
= 122.88 MSPS, IF = 30.72 MHz, See Figure 9 73Adjacent channel power ratioACPR WCDM A with 3.84 MHz BW, f
CLK
= 245.76 MSPS, IF = 61.44 MHz, See Figure 10 71 dB5-MHz channel spacing
f
CLK
= 399.32 MSPS, IF = 153.36 MHz, See Figure 12 65Two-tone intermodulation f
CLK
= 400 MSPS, f
OUT1
= 70 MHz, f
OUT2
= 71 MHz 73to Nyquist (each tone at
f
CLK
= 400 MSPS, f
OUT1
= 140 MHz, f
OUT2
= 141 MHz 62–6 dBfs)IMD dBcFour-tone intermodulation, f
CLK
= 156 MSPS, f
OUT
= 15.6, 15.8, 16.2, 16.4 MHz 8215-MHz span, missing center
f
CLK
= 400 MSPS, f
OUT
= 68.1, 69.3, 71.2, 72 MHz 74tone (each tone at –16 dBfs)
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Digital Specifications
DAC5675-EP
SGLS381A – OCTOBER 2006 – REVISED OCTOBER 2006
over operating free-air temperature range, typical values at 25 °C, AV
DD
= 3.3 V, DV
DD
= 3.3 V (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
LVDS Interface: Nodes D[13:0]A, D[13:0]B
Positive-going differential inputV
ITH+
100 mVvoltage threshold
See LVDS Min/Max ThresholdVoltages tableNegative-going differential inputV
ITH–
–100 mVvoltage thresholdZ
T
Internal termination impedance 90 110 132 ΩC
I
Input capacitance 2 pF
CMOS Interface (SLEEP)
V
IH
High-level input voltage 2 3.3 VV
IL
Low-level input voltage 0 0.8 VI
IH
High-level input current –100 100 µAI
IL
Low-level input current –10 10 µAInput capacitance 2 pF
Clock Interface (CLK, CLKC)
|CLK-CLKC| Clock differential input voltage 0.4 0.8 V
PP
t
w(H)
Clock pulse width high 1.25 nst
w(L)
Clock pulse width low 1.25 nsClock duty cycle 40% 60%V
CM
Common-mode voltage range 2 ±20% VInput resistance Node CLK, CLKC 670 ΩInput capacitance Node CLK, CLKC 2 pFInput resistance Differential 1.3 k ΩInput capacitance Differential 1 pF
Timing
t
SU
Input setup time 1.5 nst
H
Input hold time 0.25 nst
LPH
Input latch pulse high time 2 nst
DD
Digital delay time DLL disabled, DLLOFF = 1 3 clk
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50% 50%
Valid Data
D[13:0]A
D[13:0]B
CLK
CLKC
DAC Output
IOUT1/IOUT2
tW (LPH)
tSU
tH
tPD
tS(DAC)
tr(IOUT)
tDD
0.1%
0.1%
50%
10%
90%
Electrical Characteristics
(1)
VA+ VB
2
VCOM =
VA
VB
VA, B
VA, B
VB
VA
DVDD
DGND
Logical Bit
Equivalent
1.4 V
1 V
0.4 V
−0.4 V
1
0
0 V
DAC5675-EP
DAC5675-EP
SGLS381A – OCTOBER 2006 – REVISED OCTOBER 2006
Timing Information
Figure 1. Timing Diagram
over operating free-air temperature range, AV
DD
= 3.3 V, DV
DD
= 3.3 V, I
O(FS)
= 20 mA (unless otherwise noted)
RESULTING RESULTING LOGICAL BITAPPLIED
DIFFERENTIAL COMMON-MODE BINARY COMMENTVOLTAGES
INPUT VOLTAGE INPUT VOLTAGE EQUIVALENT
V
A
(V) V
B
(V) V
A,B
(mV) V
COM
(V)
1.25 1.15 100 1.2 11.15 1.25 –100 1.2 0
Operation with minimum differential voltage2.4 2.3 100 2.35 1
(±100 mV) applied to the complementary inputs2.3 2.4 –100 2.35 0
versus common-mode range0.1 0 100 0.05 10 0.1 –100 0.05 01.5 0.9 600 1.2 10.9 1.5 –600 1.2 0
Operation with maximum differential voltage2.4 1.8 600 2.1 1
(±600 mV) applied to the complementary inputs1.8 2.4 –600 2.1 0
versus common-mode range0.6 0 600 0.3 10 0.6 –600 0.3 0
(1) Specifications subject to change.
Figure 2. LVDS Timing Test Circuit and Input Test Levels
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DEVICE INFORMATION
PHP PACKAGE
(TOP VIEW)
DAC5675
DAC5675-EP
SGLS381A – OCTOBER 2006 – REVISED OCTOBER 2006
A. Thermal pad size: 4,5mm ×4,5mm (min), 5,5mm ×5,5mm (max)
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DAC5675-EP
SGLS381A – OCTOBER 2006 – REVISED OCTOBER 2006
DEVICE INFORMATION (continued)TERMINAL FUNCTIONS
TERMINAL
I/O DESCRIPTIONNAME NO.
AGND 19, 41, 46, 47 I Analog negative supply voltage (ground). Pin 47 is internally connected to the heat slug.AV
DD
20, 42, 45, 48 I Analog positive supply voltageBIASJ 39 O Full-scale output current biasCLK 22 I External clock inputCLKC 21 I Complementary external clock1, 3, 5, 7, 9,
LVDS positive input, data bits 13–0.11, 13, 23, 25,D[13:0]A I D13A is the most significant data bit (MSB).27, 29, 31, 33,
D0A is the least significant data bit (LSB).352, 4, 6, 8, 10,
LVDS negative input, data bits 13–0..12, 14, 24, 26,D[13:0]B I D13B is the most significant data bit (MSB).28, 30, 32, 34,
D0B is the least significant data bit (LSB).36DGND 16, 18 I Digital negative supply voltage (ground)DV
DD
15, 17 I Digital positive supply voltageInternal reference output or external reference input. Requires a 0.1- µF decoupling capacitor toEXTIO 40 I/O
AGND when used as reference output.DAC current output. Full-scale when all input bits are set 1. Connect the reference side of theIOUT1 43 O
DAC load resistors to AV
DD
.DAC complementary current output. Full-scale when all input bits are 0. Connect the referenceIOUT2 44 O
side of the DAC load resistors to AV
DD
.NC 38 Not connected in chip. Can be high or low.SLEEP 37 I Asynchronous hardware power-down input. Active high. Internal pulldown.
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TYPICAL CHARACTERISTICS
InputCode
DNL(LSB)
0 2000
1.0
0.8
0.6
0.4
0.2
0
−
0.2
−
0.4
−
0.6
−
0.8
−
1.0
4000 6000 8000 10000 12000 14000 16000
Input Code
INL (LSB)
0 2000
1.5
1.0
0.5
0
−0.5
−1.0
−1.5
4000 6000 8000 10000 12000 14000 16000
Frequency (MHz)
Power (dBFS)
65
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
−100
67 69 71 73 75
f1=69.5MHz, −6dBFS
f2=70.5MHz, −6dBFS
IMD3=77.41dBc
VCC =VAA=3.3V
fCLK =200MHz
Frequency (MHz)
Power (dBFS)
0 4020
0
−10
−20
−30
−40
−50
−60
−70
−80
−90
80 10060 120 140 160 180 200
VCC = VAA = 3.3 V
fCLK = 400 MHz
fOUT = 20.1 MHz, 0 dBFS
SFDR = 74.75 dBc
20.1 MHz
40.06 MHz
60.25 MHz
Output Frequency (MHz)
SFDR (dBFS)
90
86
82
78
74
70
66
62
58
54
50
10 3020 50 6040 8070 90 100 110 120
VCC = VAA = 3.3 V
fCLK = 400 MHz
0 dBFS
−3 dBFS
−6 dBFS
DAC5675-EP
SGLS381A – OCTOBER 2006 – REVISED OCTOBER 2006
DIFFERENTIAL NONLINEARITY (DNL) vs INPUT CODE INTEGRAL NONLINEARITY (INL) vs INPUT CODE
Figure 3. Figure 4.
TWO-TONE IMD (POWER) vs FREQUENCY TWO-TONE IMD3 vs FREQUENCY
Figure 5. Figure 6.
SINGLE-TONE SPECTRUMPOWER vs FREQUENCY SPURIOUS-FREE DYNAMIC RANGE vs FREQUENCY
Figure 7. Figure 8.
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Output Frequency (MHz)
SFDR (dBFS)
90
86
82
78
74
70
66
62
58
54
50
10 3020 50 6040 8070 90 100 110 120
VCC = VAA = 3.3 V
fCLK = 200 MHz
0 dBFS
−3 dBFS
−6 dBFS
Frequency
Power (dBm/30kHz)
18
−25
−35
−45
−55
−65
−75
−85
−95
−105
−115
23 28 33 38 43
VCC = VAA = 3.3 V
fCLK = 122.88 MHz
fCENTER = 30.72 MHz
ACLR = 72.29 dB
Frequency
Power (dBm/30kHz)
82.2
−30
−40
−50
−60
−70
−80
−90
−100
−110
87.2 92.2 97.2 10.2
VCC = VAA = 3.3 V fCLK = 3 68.64 MHz
fCENTER =
92.16 MHz
ACLR = 65 dBc
Output Frequency (MHz)
ACLR (dBc)
80
78
76
74
72
70
68
66
64
62
60
10 30 50 70 90 110 130 150
VCC = VAA = 3.3 V
fCLK = 399.36 MHz
Single Channel
DAC5675-EP
SGLS381A – OCTOBER 2006 – REVISED OCTOBER 2006
TYPICAL CHARACTERISTICS (continued)
W-CDMA TM1 SINGLE CARRIERSPURIOUS-FREE DYNAMIC RANGE vs FREQUENCY POWER vs FREQUENCY
Figure 9. Figure 10.
W-CDMA TM1 DUAL CARRIER W-CDMA TM1 SINGLE CARRIERPOWER vs FREQUENCY ACLR vs OUTPUT FREQUENCY
Figure 11. Figure 12.
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APPLICATION INFORMATION
Detailed Description
Bandgap
Reference
1.2 V
Control Amp
Current
Source
Array
Output
Current
Switches
DAC
Latch
+
Drivers
Decoder
Input
Latches
LVDS
Input
Interface
Clock Distribution
SLEEP
EXTIO
BIASJ
D[13:0]A
D[13:0]B
CLK
CLKC
DVDD(2x) DGND(2x)
14
14
AVDD(4x) AGND(4x)
CEXT
0.1 Fm
RBIAS
1 kΩ
1:4
Clock
Input
RT
200 Ω
3.3V
(AVDD)
3.3V
(AVDD)
3.3V
(AVDD)
100 Ω
50 Ω
50 Ω
IOUT
IOUT
1:1 Output
RLOAD
50 Ω
DAC5675-EP
DAC5675-EP
SGLS381A – OCTOBER 2006 – REVISED OCTOBER 2006
Figure 13 shows a simplified block diagram of the current steering DAC5675. The DAC5675 consists of asegmented array of NPN-transistor current sources, capable of delivering a full-scale output current up to20 mA. Differential current switches direct the current of each current source to either one of the complementaryoutput nodes IOUT1 or IOUT2. The complementary current output enables differential operation, canceling outcommon-mode noise sources (digital feedthrough, on-chip, and PCB noise), dc offsets, and even-orderdistortion components, and doubling signal output power.
The full-scale output current is set using an external resistor (R
BIAS
) in combination with an on-chip bandgapvoltage reference source (1.2 V) and control amplifier. The current (I
BIAS
) through resistor R
BIAS
is mirroredinternally to provide a full-scale output current equal to 16 times I
BIAS
. The full-scale current is adjustable from20 mA down to 2 mA by using the appropriate bias resistor value.
Figure 13. Application Schematic
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Digital Inputs
Internal
DigitalIn
110-Ω
Termination
Resistor
Internal
Digital In
D[13:0]A
D[13..0]A
D[13..0]B
D[13:0]B
DGND
DVDD
DAC5675-EPDAC5675-EP
Internal
Digital In
DVDD
DGND
Digital Input
DAC5675-EP
Clock Input
DAC5675-EP
SGLS381A – OCTOBER 2006 – REVISED OCTOBER 2006
APPLICATION INFORMATION (continued)
The DAC5675 uses a low-voltage differential signaling (LVDS) bus input interface. The LVDS features a lowdifferential voltage swing with low constant power consumption (4 mA per complementary data input) acrossfrequency. The differential characteristic of LVDS allows for high-speed data transmission with lowelectromagnetic interference (EMI) levels. The LVDS input minimum and maximum input threshold table lists theLVDS input levels. Figure 14 shows the equivalent complementary digital input interface for the DAC5675, validfor pins D[13:0]A and D[13:0]B. Note that the LVDS interface features internal 110- Ωresistors for propertermination. Figure 2 shows the LVDS input timing measurement circuit and waveforms. A common-mode levelof 1.2 V and a differential input swing of 0.8 V
PP
is applied to the inputs.
Figure 15 shows a schematic of the equivalent CMOS/TTL-compatible digital inputs of the DAC5675, valid forthe SLEEP pin.
Figure 14. LVDS Digital Equivalent Input
Figure 15. CMOS/TTL Digital Equivalent Input
The DAC5675 features differential LVPECL-compatible clock inputs (CLK, CLKC). Figure 16 shows theequivalent schematic of the clock input buffer. The internal biasing resistors set the input common-mode voltageto approximately 2 V, while the input resistance is typically 670 Ω. A variety of clock sources can be ac-coupledto the device, including a sine-wave source (see Figure 17 ).
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Internal
Clock
CLKC
AGND
AVDD
CLK
R1
1kΩ
R1
1kΩ
R2
2kΩ
R2
2kΩ
DAC5675-EP
CLK
CLKC
Optional, may be
bypassedforsine-
waveinput
RT
200 Ω
Swing Limitation
Termination
Resistor
1:4
CAC
0.1 mF
DAC5675-EP
CLK
CLKC
Single-Ended
ECL
or
(LV)PECL
Source
ECL/PECL
Gate
CAC
RT
50 Ω
RT
50 Ω
VTT
CAC
0.01 mF
0.01 mF
DAC5675-EP
DAC5675-EP
SGLS381A – OCTOBER 2006 – REVISED OCTOBER 2006
APPLICATION INFORMATION (continued)
Figure 16. Clock Equivalent Input
Figure 17. Driving the DAC5675 With a Single-Ended Clock Source Using a Transformer
To obtain best ac performance, the DAC5675 clock input should be driven with a differential LVPECL orsine-wave source as shown in Figure 18 and Figure 19 . Here, the potential of V
TT
should be set to thetermination voltage required by the driver along with the proper termination resistors (R
T
). The DAC5675 clockinput can also be driven single ended; this is shown in Figure 20 .
Figure 18. Driving the DAC5675 With a Single-Ended ECL/PECL Clock Source
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CLK
CLKC
CAC
RT
50 Ω
RT
50 Ω
VTT
CAC
0.01 mF
0.01 mF
Differential
ECL
or
(LV)PECL
Source
+
−
DAC5675-EP
CLK
CLKC
0.01mF
ROPT
22 Ω
TTL/CMOS
Source
Node CLKC
Internally Biased to
AVDD/2
DAC5675-EP
Supply Inputs
DAC Transfer Function
IOUT1 +IO(FS)*IOUT2
(1)
IOUT1 +IO(FS) CODE
16384
(2)
IOUT2 +IO(FS) (16383*CODE)
16384
(3)
DAC5675-EP
SGLS381A – OCTOBER 2006 – REVISED OCTOBER 2006
APPLICATION INFORMATION (continued)
Figure 19. Driving the DAC5675 With a Differential ECL/PECL Clock Source
Figure 20. Driving the DAC5675 With a Single-Ended TTL/CMOS Clock Source
The DAC5675 comprises separate analog and digital supplies, that is AV
DD
and DV
DD
, respectively. Thesesupply inputs can be set independently from 3.6 V down to 3.15 V.
The DAC5675 delivers complementary output currents IOUT1 and IOUT2. The DAC supports straight binarycoding, with D13 being the MSB and D0 the LSB. (For ease of notation, we denote D13–D0 as the logical bitequivalent of the complementary LVDS inputs D[13:0]A and D[13:0]B). Output current IOUT1 equals theapproximate full-scale output current when all input bits are set high, when the binary input word has the decimalrepresentation 16383. Full-scale output current flows through terminal IOUT2 when all input bits are set low(mode 0, straight binary input). The relation between IOUT1 and IOUT2 can thus be expressed as:
where IO
(FS)
is the full-scale output current. The output currents can be expressed as:
where CODE is the decimal representation of the DAC data input word. Output currents IOUT1 and IOUT2 drivea load R
L
. R
L
is the combined impedance for the termination resistance and/or transformer load resistance,R
LOAD
(see Figure 22 and Figure 23 ). This would translate into single-ended voltages VOUT1 and VOUT2 atterminal IOUT1 and IOUT2, respectively, of Equation 4 and Equation 5 :
16
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VOUT1 +IOUT1 RL+ǒCODE IO(FS) RLǓ
16384
(4)
VOUT2 +IOUT2 RL+(16383*CODE) IO(FS) RL
16384
(5)
VOUT(DIFF)+VOUT1*VOUT2 +(2CODE *16383) IO(FS) RL
16384
(6)
Reference Operation
IO(FS)+16 IBIAS +16 VEXTIO
RBIAS
(7)
Analog Current Outputs
DAC5675-EP
SGLS381A – OCTOBER 2006 – REVISED OCTOBER 2006
APPLICATION INFORMATION (continued)
Thus, the differential output voltage VOUT
(DIFF)
can be expressed as:
Equation 6 shows that applying the differential output results in doubling the signal power delivered to the load.Since the output currents IOUT1 and IOUT2 are complementary, they become additive when processeddifferentially. Care should be taken not to exceed the compliance voltages at nodes IOUT1 and IOUT2, whichleads to increased signal distortion.
The DAC5675 has a bandgap reference and control amplifier for biasing the full-scale output current. Thefull-scale output current is set by applying an external resistor R
BIAS
. The bias current I
BIAS
through resistor R
BIASis defined by the on-chip bandgap reference voltage and control amplifier. The full-scale output current equals16 times this bias current. The full-scale output current IO
(FS)
is thus expressed as Equation 7 :
where V
EXTIO
is the voltage at terminal EXTIO. The bandgap reference voltage delivers a stable voltage of 1.2 V.This reference can be overridden by applying an external voltage to terminal EXTIO. The bandgap referencecan additionally be used for external reference operation. In such a case, an external buffer amplifier with highimpedance input should be selected in order to limit the bandgap load current to less than 100 nA. The capacitorC
EXT
may be omitted. Terminal EXTIO serves as either an input or output node. The full-scale output current isadjustable from 20 mA down to 2 mA by varying resistor R
BIAS
.
Figure 21 shows a simplified schematic of the current source array output with corresponding switches.Differential NPN switches direct the current of each individual NPN current source to either the positive outputnode IOUT1 or its complementary negative output node IOUT2. The output impedance is determined by thestack of the current sources and differential switches and is >300 k Ωin parallel with an output capacitanceof 5 pF.
The external output resistors are referred to the positive supply AV
DD
.
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S(1) S(1)C S(2)C S(N)CS(2) S(N)
Current Sink Array
IOUT1 IOUT2
RLOAD
RLOAD
3.3V
AVDD
AGND
DAC5675-EP
IOUT1
IOUT2
3.3V
AVDD
3.3V
AVDD
50 Ω
50 Ω
100 Ω
1:1
RLOAD
50 Ω
DAC5675-EP
DAC5675-EP
SGLS381A – OCTOBER 2006 – REVISED OCTOBER 2006
APPLICATION INFORMATION (continued)
Figure 21. Equivalent Analog Current Output
The DAC5675 can easily be configured to drive a doubly-terminated 50- Ωcable using a properly selectedtransformer. Figure 22 and Figure 23 show the 1:1 and 4:1 impedance ratio configuration, respectively. Theseconfigurations provide maximum rejection of common-mode noise sources and even-order distortioncomponents, thereby doubling the power of the DAC to the output. The center tap on the primary side of thetransformer is terminated to AV
DD
, enabling a dc-current flow for both IOUT1 and IOUT2. Note that the acperformance of the DAC5675 is optimum and specified using a 1:1 differential transformer-coupled output.
Figure 22. Driving a Doubly-Terminated 50- ΩCable Using a 1:1 Impedance Ratio Transformer
18
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IOUT1
IOUT2
3.3V
AVDD
3.3V
AVDD
100 Ω
100 Ω
4:1
RLOAD
50 Ω
15 Ω
DAC5675-EP
(a)
VOUT
3.3V
AVDD
3.3V
AVDD
25 Ω
25 Ω
VOUT1
VOUT2
Optional, for single-
ended output
referred to AVDD
IOUT1
IOUT2
CFB
IOUT1
IOUT2
3.3V
AVDD
200 Ω(RFB)
(b)
DAC5675-EP
DAC5675-EP
Sleep Mode
DAC5675-EP
SGLS381A – OCTOBER 2006 – REVISED OCTOBER 2006
APPLICATION INFORMATION (continued)
Figure 23. Driving a Doubly-Terminated 50- ΩCable Using a 4:1 Impedance Ratio Transformer
Figure 24 (a) shows the typical differential output configuration with two external matched resistor loads. Thenominal resistor load of 25 Ωgives a differential output swing of 1 V
PP
(0.5 V
PP
single ended) when applying a20-mA full-scale output current. The output impedance of the DAC5675 slightly depends on the output voltage atnodes IOUT1 and IOUT2. Consequently, for optimum dc-integral nonlinearity, the configuration of Figure 24 (b)should be chosen. In this current/voltage (I-V) configuration, terminal IOUT1 is kept at AV
DD
by the invertingoperational amplifier. The complementary output should be connected to AV
DD
to provide a dc-current path forthe current sources switched to IOUT1. The amplifier maximum output swing and the full-scale output current ofthe DAC determine the value of the feedback resistor R
FB
. The capacitor C
FB
filters the steep edges of theDAC5675 current output, thereby reducing the operational amplifier slew-rate requirements. In this configuration,the operational amplifier should operate at a supply voltage higher than the resistor output reference voltageAV
DD
as a result of its positive and negative output swing around AV
DD
. Node IOUT1 should be selected if asingle-ended unipolar output is desired.
Figure 24. Output Configurations
The DAC5675 features a power-down mode that turns off the output current and reduces the supply current toapproximately 6 mA. The power-down mode is activated by applying a logic level one to the SLEEP pin, pulleddown internally.
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DEFINITIONS
Definitions of Specifications and Terminology
DAC5675-EP
SGLS381A – OCTOBER 2006 – REVISED OCTOBER 2006
Gain error is defined as the percentage error in the ratio between the measured full-scale output current andthe value of 16 ×V
(EXTIO)
/R
BIAS
. A V
(EXTIO)
of 1.25 V is used to measure the gain error with an external referencevoltage applied. With an internal reference, this error includes the deviation of V
(EXTIO)
(internal bandgapreference voltage) from the typical value of 1.25 V.
Offset error is defined as the percentage error in the ratio of the differential output current (IOUT1-IOUT2) andthe half of the full-scale output current for input code 8192.
THD is the ratio of the rms sum of the first six harmonic components to the rms value of the fundamental outputsignal.
SNR is the ratio of the rms value of the fundamental output signal to the rms sum of all other spectralcomponents below the Nyquist frequency, including noise, but excluding the first six harmonics and dc.
SINAD is the ratio of the rms value of the fundamental output signal to the rms sum of all other spectralcomponents below the Nyquist frequency, including noise and harmonics, but excluding dc.
ACPR or adjacent channel power ratio is defined for a 3.84-Mcps 3GPP W-CDMA input signal measured in a3.84-MHz bandwidth at a 5-MHz offset from the carrier with a 12-dB peak-to-average ratio.
APSSR or analog power supply ratio is the percentage variation of full-scale output current versus a 5%variation of the analog power supply AV
DD
from the nominal. This is a dc measurement.
DPSSR or digital power supply ratio is the percentage variation of full-scale output current versus a 5% variationof the digital power supply DV
DD
from the nominal. This is a dc measurement.
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PACKAGING INFORMATION
Orderable Device Status (1) Package
Type Package
Drawing Pins Package
Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
DAC5675MPHPEP ACTIVE HTQFP PHP 48 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
DAC5675MPHPREP ACTIVE HTQFP PHP 48 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
V62/05619-01XE ACTIVE HTQFP PHP 48 1000 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
V62/05619-02XE ACTIVE HTQFP PHP 48 250 Green (RoHS &
no Sb/Br) CU NIPDAU Level-3-260C-168 HR
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF DAC5675-EP :
•Catalog: DAC5675
NOTE: Qualified Version Definitions:
•Catalog - TI's standard catalog product
PACKAGE OPTION ADDENDUM
www.ti.com 18-Sep-2008
Addendum-Page 1
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0 (mm) B0 (mm) K0 (mm) P1
(mm) W
(mm) Pin1
Quadrant
DAC5675MPHPREP HTQFP PHP 48 1000 330.0 16.4 9.6 9.6 1.5 12.0 16.0 Q2
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Jul-2008
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DAC5675MPHPREP HTQFP PHP 48 1000 346.0 346.0 33.0
PACKAGE MATERIALS INFORMATION
www.ti.com 11-Jul-2008
Pack Materials-Page 2
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