8-Channel DAS with 16-Bit, 800 kSPS
Bipolar Input, Simultaneous Sampling ADC
Data Sheet
AD7606B
Rev. 0 Document Feedback
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FEATURES
16-bit ADC with 800 kSPS on all channels
Input buffer with 5 MΩ analog input impedance
Pin to pin compatible with the AD7606
−40°C to +125°C operating temperature range
Single 5 V analog supply and 1.71 V to 3.6 V VDRIVE supply
±21 V input clamp protection with 8 kV ESD
Extra modes available in software mode
Per channel selectable analog input ranges
Single-ended, bipolar: ±10 V, ±5 V, and ±2.5 V
Per channel system phase, offset, and gain calibration
Analog input open circuit detection feature
<20 LSB open circuit code error (RPD = 10 kΩ)
Self diagnostics and monitoring features
CRC error checking on read/write data and registers
APPLICATIONS
Power line monitoring
Protective relays
Multiphase motor control
Instrumentation and control systems
Data acquisition systems
FUNCTIONAL BLOCK DIAGRAM
V8 5MΩ
CLAMP
V8GND 5MΩ
CLAMP PGA LPF SAR
V7 5MΩ
CLAMP
V7GND 5MΩ
CLAMP PGA LPF SAR
V6 5MΩ
CLAMP
V6GND 5MΩ
CLAMP PGA LPF SAR
V5 5MΩ
CLAMP
V5GND 5MΩ
CLAMP PGA LPF SAR
V4 5MΩ
CLAMP
V4GND 5MΩ
CLAMP PGA LPF SAR
V3 5MΩ
CLAMP
V3GND 5MΩ
CLAMP PGA LPF SAR
V2 5MΩ
CLAMP
V2GND 5MΩ
CLAMP PGA LPF SAR
CLK OSC
CONTROL
INPUTS
V1 5MΩ
CLAMP
V1GND 5MΩ
CLAMP PGA LPF SAR
PROGRAMMABLE
DIGITAL FILTER
SW /HW M ODE
CONTROL
ADC, PGA, AND
CHANNEL
CONTROL
AND
CONFIGURATION
PARALLEL/
SERIAL
INTERFACE
SERIAL
SDI
BUSY
FRSTDATA
SCLK
CS
RD
DB0 TO DB15
D
OUT
A TO D
OUT
D
WR
CONVST
RESET
RANGE
OS0 TO OS2
SYSTEM GAIN,
OFFSETAND
PHASE
CALIBRATION
DIAGNOSTICS
AND
ANALOG INPUT
OPEN DETECT
CONFIGURATION
2.5V
REF
REFGND
PARALLEL
PAR/SER SEL
REF SELECT
REFCAPA
REFCAPB
AV
CC
REGCAP
ALDO
AV
CC
REGCAP
DLDO
V
DRIVE
AGND
REFIN/REFOUT
AD7606B
15137-001
Figure 1.
AD7606B Data Sheet
Rev. 0 | Page 2 of 69
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
General Description ......................................................................... 3
Specifications ..................................................................................... 4
Timing Specifications .................................................................. 6
Absolute Maximum Ratings .......................................................... 10
Thermal Resistance .................................................................... 10
ESD Caution ................................................................................ 10
Pin Configuration and Function Descriptions ........................... 11
Typical Performance Characteristics ........................................... 14
Terminology .................................................................................... 20
Theory of Operation ...................................................................... 22
Analog Front End ....................................................................... 22
SAR ADC ..................................................................................... 23
Reference ..................................................................................... 23
Operation Modes ........................................................................ 24
Digital Filter .................................................................................... 27
Padding Oversampling .............................................................. 28
External Oversampling Clock ................................................... 28
System Calibration Features .......................................................... 29
System Phase Calibration .......................................................... 29
System Gain Calibration............................................................ 29
System Offset Calibration ......................................................... 29
Analog Input Open Circuit Detection .................................... 30
Digital Interface .............................................................................. 32
Hardware Mode .......................................................................... 32
Software Mode ............................................................................ 32
Parallel Interface ......................................................................... 33
Serial Interface ............................................................................ 35
Diagnostics ...................................................................................... 39
Reset Detection ........................................................................... 39
Overvoltage and Undervoltage Events .................................... 39
Digital Error ................................................................................ 39
Diagnostics Multiplexer ............................................................ 42
Typical Connection Diagram ....................................................... 44
Applications Information .............................................................. 46
Layout Guidelines....................................................................... 46
Register Summary .......................................................................... 48
Register Details ............................................................................... 50
Outline Dimensions ....................................................................... 69
Ordering Guide .......................................................................... 69
REVISION HISTORY
6/2019—Revision 0: Initial Version
Data Sheet AD7606B
Rev. 0 | Page 3 of 69
GENERAL DESCRIPTION
The AD7606B is a 16-bit, simultaneous sampling, analog-to-
digital data acquisition system (DAS) with eight channels,
each channel containing analog input clamp protection, a
programmable gain amplifier (PGA), a low-pass filter, and a
16-bit successive approximation register (SAR), analog-to-digital
converter (ADC). The AD7606B also contains a flexible digital
filter, low drift, 2.5 V precision reference and reference buffer to
drive the ADC and flexible parallel and serial interfaces.
The AD7606B operates from a single 5 V supply and accommo-
dates ±10 V, ±5 V, and ±2.5 V true bipolar input ranges when
sampling at throughput rates of 800 kSPS for all channels. The
input clamp protection tolerates voltages up to ±21 V. The
AD7606B has a 5 MΩ analog input impedance, resulting in less
than 20 LSB bipolar zero code when the input signal is discon-
nected and pulled to ground through a 10 kΩ external resistor.
The single supply operation, on-chip filtering, and high input
impedance eliminates the need for external driver op amps, which
require bipolar supplies. For applications with lower throughput
rates, the AD7606B flexible digital filter can be used to improve
noise performance.
In hardware mode, the AD7606B is fully compatible with the
AD7606. In software mode, the following advanced features are
available:
Additional ±2.5 V analog input range.
A n a l o g i n p u t r a n g e ( ± 1 0 V, ± 5 V, a n d ± 2 . 5 V ) , s e l e c t a b l e
per channel.
Additional oversampling (OS) options, up to OS × 256.
System gain, system offset, and system phase calibration
per channel.
Analog input open circuit detector.
Diagnostic multiplexer.
Monitoring functions (serial peripheral interface (SPI)
invalid read/write, cyclic redundancy check (CRC),
overvoltage and undervoltage events, busy stuck monitor,
and reset detection).
Note that throughout this data sheet, multifunction pins, such
as the RD/SCLK pin, are referred to either by the entire pin
name or by a single function of the pin, for example, the SCLK pin,
when only that function is relevant.
Table 1. Pin to Pin Compatible Devices
Resolution
(Bits)
Single-Ended
Bipolar Inputs
True Differential
Bipolar Inputs
18 AD7608 AD7609
16 AD7606
AD7606B
14 AD7607
AD7606B Data Sheet
Rev. 0 | Page 4 of 69
SPECIFICATIONS
Voltage reference (VREF) = 2.5 V external and internal, analog supply voltage (AVCC) = 4.75 V to 5.25 V, logic supply voltage (VDRIVE) =
1.71 V to 3.6 V, sample frequency (fSAMPLE) = 800 kSPS, with no oversampling, TA = −40°C to +125°C, single-ended input, and all input
voltage ranges, unless otherwise noted.
Table 2.
Parameter Test Conditions/Comments Min Typ Max Unit
DYNAMIC PERFORMANCE Input frequency (fIN) = 1 kHz sine wave, unless
otherwise noted
Signal-to-Noise Ratio (SNR)1 No oversampling (OS), ±10 V range 87.5 89.5 dB
No OS, ±5 V range 86.5 88.5 dB
No OS, ±2.5 V range 83.5 86 dB
Oversampling ratio (OSR) = 16×, ±10 V range 92 93.5 dB
OSR = 16×, ±5 V range 90.5 92 dB
OSR = 16×, ±2.5 V range 87.5 89 dB
Total Harmonic Distortion (THD) All input ranges
f
SAMPLE
= 200 kSPS
−105
−94
dB
fSAMPLE = 800 kSPS −100 −90 dB
Signal-to-Noise-and-Distortion No OS, ±10 V range 86.5 88.5 dB
No OS, ±5 V range 85.5 87.7 dB
No OS, ±2.5 V range 83 85.5 dB
OSR = 16×, ±10 V range 89 92 dB
OSR = 16×, ±5 V range 89 91.3 dB
OSR = 16×, ±2.5 V range 86.5 88.7 dB
Spurious-Free Dynamic Range
(SFDR)
−104 dB
Channel to Channel Isolation fIN on unselected channels up to 160 kHz −110 dB
Full Scale Step Settling Time 0.01% of full scale
±10 V range 70 μs
±5 V range 110 μs
±2.5V range 130 μs
ANALOG INPUT FILTER
Full Power Bandwidth −3 dB, ±10 V range 22.5 kHz
−3 dB, ±5 V range 13.5 kHz
−3 dB, ±2.5 V range 11.5 kHz
−0.1 dB, ±10 V range 3 kHz
−0.1 dB, ±5 V range 2 kHz
−0.1 dB, ±2.5 V range 2 kHz
Phase Delay ±10 V range 8 µs
±5 V range 9 µs
±2.5 V range 11 µs
Phase Delay Matching
±10 V range 240 ns
±5 V range 365 ns
±2.5 V range 445 ns
DC ACCURACY
Resolution No missing codes 16 Bits
Differential Nonlinearity (DNL) ±0.5 ±0.99 LSB2
Integral Nonlinearity (INL) fSAMPLE = 200 kSPS ±2 LSB2
fSAMPLE = 800 kSPS ±1.16 ±2.5 LSB2
Total Unadjusted Error (TUE) Internal reference ±3 ±47 LSB
Positive and Negative Full-
Scale (FS) Error3
External reference ±2 ±30 LSB
Internal reference ±2 ±45 LSB
Data Sheet AD7606B
Rev. 0 | Page 5 of 69
Parameter Test Conditions/Comments Min Typ Max Unit
R
FILTER4 = 20 kΩ, system gain calibration disabled 126 LSB
R
FILTER4 = 0 kΩ to 65 kΩ, system gain calibration enabled 4 LSB
Positive and Negative FS Error Drift External reference ±1 ±5 ppm/°C
Internal reference ±4 ±15 ppm/°C
Positive and Negative FS Error
Matching
3 20 LSB
Bipolar Zero Code Error ±1 ±20 LSB2
T
A = −40°C to +85°C ±1 ±14 LSB
Bipolar Zero Code Error Drift ±0.2 ±2 ppm/°C
Bipolar Zero Code Error Matching 1.5 23 LSB2
T
A = −40°C to +85°C 1.4 14 LSB
Open Circuit Code Error Pull-down resistor (RPD)5 = 10 kΩ, ±10 V range ±12 ±30 LSB
R
PD = 10 kΩ, ±10 V range, TA = −40°C to +85°C ±12 ±20 LSB
R
PD = 10 kΩ, ±5 V range ±17 ±35 LSB
R
PD = 10 kΩ, ±5 V range, TA = −40°C to +85°C ±17 ±25 LSB
R
PD = 10 kΩ, ±2.5 V range ±22 ±40 LSB
R
PD = 10 kΩ, ±2.5 V range, TA = −40°C to +85°C ±22 ±30 LSB
ANALOG INPUT
Input Voltage Ranges Vx − VxGND
±10 V range −10 +10 V
±5 V range −5 +5 V
±2.5 V range −2.5 +2.5 V
Input Voltage Ranges VxGND − AGND
±10 V range −0.7 +1.9 V
±5 V range −0.1 +2.7 V
±2.5 V range −0.1 +3.1 V
Analog Input Current See the Typical Performance Characteristics section (VIN − 2)/RIN μA
Input Capacitance (CIN)6 5 pF
Input Impedance (RIN)7 5 MΩ
Input Impedance Drift ±1 ±25 ppm/°C
REFERENCE INPUT/OUTPUT
Reference Input Voltage REF SELECT = 0, external reference 2.495 2.5 2.505 V
DC Leakage Current ±0.12 μA
Input Capacitance6 7.5 pF
Reference Output Voltage REF SELSECT = 1, internal reference, TA = 25°C 2.497 2.5 2.503 V
Reference Temperature Coefficient ±3 ±15 ppm/°C
Reference Voltage to the ADC REFCAPA (Pin 44) and REFCAPB (Pin 45) 4.39 4.41 V
LOGIC INPUTS
Input High Voltage (VINH) 0.7 × VDRIVE V
Input Low Voltage (VINL) 0.3 × VDRIVE V
Input Current (IIN) ±1 μA
Input Capacitance6 5 pF
LOGIC OUTPUTS
Output High Voltage (VOH) Current source (ISOURCE) = 100 μA VDRIVE − 0.2 V
Output Low Voltage (VOL) Current sink (ISINK) = 100 μA 0.2 V
Floating State Leakage Current ±1 ±20 μA
Output Capacitance6 5 pF
Output Coding Twos complement N/A8
CONVERSION RATE
Conversion Time See Table 3 0.75 μs
Acquisition Time 0.5 μs
Throughput Rate Per channel 800 kSPS
AD7606B Data Sheet
Rev. 0 | Page 6 of 69
Parameter Test Conditions/Comments Min Typ Max Unit
POWER REQUIREMENTS
AVCC 4.75 5 5.25 V
VDRIVE 1.71 3.6 V
REGCAP 1.875 1.93 V
AVCC Current (IAVCC)
Normal Mode (Static) 7.5 9.5 mA
Normal Mode (Operational) fSAMPLE = 800 kSPS 43 47.5 mA
fSAMPLE = 10 kSPS 8 10 mA
Standby 3.5 4.5 mA
Shutdown Mode 0.5 5 µA
VDRIVE Current (IDRIVE)
Normal Mode (Static) 1.8 3.5 µA
Normal Mode (Operational) fSAMPLE = 800 kSPS 1.1 1.5 mA
fSAMPLE = 10 kSPS 30 75 µA
Standby 1.6 3 µA
Shutdown Mode 0.8 2 µA
Power Dissipation
Normal Mode (Static) 40 50 mW
Normal Mode (Operational) fSAMPLE = 800 kSPS 230 255 mW
fSAMPLE = 10 kSPS 42 50 mW
Standby 18 24 mW
Shutdown Mode 2.5 25 µW
1 No OS means no oversampling is applied.
2 LSB means least significant bit. With a ±2.5 V input range, 1 LSB = 76.293 µV. With a ±5 V input range, 1 LSB = 152.58 µV. With a ±10 V input range, 1 LSB = 305.175 µV.
3 These specifications include the full temperature range variation and contribution from the internal reference and reference buffer.
4 RFILTER is a resistor placed in a series to the analog input front-end. See Figure 57.
5 See Figure 59.
6 Not production tested. Sample tested during initial release to ensure compliance.
7 Input impedance variation is factory trimmed and accounted for in the System Gain Calibration section.
8 N/A means not applicable.
TIMING SPECIFICATIONS
Universal Timing Specifications
AVCC = 4.75 V to 5.25 V, VDRIVE = 1.71 V to 3.6 V, VREF = 2.5 V external reference and internal reference, and TA = −40°C to +125°C, unless
otherwise noted. Interface timing tested using a load capacitance of 20 pF, dependent on VDRIVE and load capacitance for serial interface.
Table 3.
Parameter Min Typ Max Unit Description
tCYCLE 1.25
µs Minimum time between consecutive CONVST rising edges (excluding
oversampling modes)1
t
LP_CNV
10
ns CONVST low pulse width
t
HP_CNV
10
ns CONVST high pulse width
t
D_CNV_BSY
CONVST high to BUSY high delay time
20 ns VDRIVE > 2.7 V
25 ns VDRIVE < 2.7 V
t
S_BSY
0
ns Minimum time from BUSY falling edge to RD falling edge setup time
(in parallel interface) or to MSB being available on DOUTx line (in serial interface)
t
D_BSY
25 ns Maximum time between last RD falling edge (in parallel interface) or
last LSB being clocked out (serial interface) and the following BUSY falling
edge; read during conversion
tCONV 0.65
0.85 μs Conversion time; no oversampling
2.2 2.3 μs Oversampling by 2
4.65 4.8 μs Oversampling by 4
9.6 9.9 μs Oversampling by 8
19.4 20 μs Oversampling by 16
Data Sheet AD7606B
Rev. 0 | Page 7 of 69
Parameter Min Typ Max Unit Description
39.2 40.2 μs Oversampling by 32
78.7 80.8 μs Oversampling by 64
157.6 161.9 μs Oversampling by 128
315.6 324 μs Oversampling by 256
tRESET
Partial Reset 55 2000 ns Partial RESET high pulse width
Full Reset 3000 ns Full RESET high pulse width
tDEVICE_SETUP µs Time between RESET falling edge and first CONVST rising edge
Partial Reset 50 ns
Full Reset 253 µs
tWAKE-UP Wake-up time after standby/shutdown mode
Standby 1 µs
Shutdown 10 ms
tPOWER-UP 10 ms Time between stable VCC/VDRIVE and assert of RESET
1 Applies to serial mode when all four DOUTx lines are selected.
READ AF TER
CONVERSION
tS_BSY
tD_BSY
tCONV
tCYCLE
tD_CNV_BSY
tDEVICE_SETUP
tRESET
tPOWER-UP
READ DURING
CONVERSION
AVCC
VDRIVE
RESET
CONVST
BUSY
CS
tHP_CNV tLP_CNV
15137-002
Figure 2. Universal Timing Diagram
Parallel Mode Timing Specifications
Table 4.
Parameter Min Typ Max Unit Description
tS_CS_RD 0 ns CS falling edge to RD falling edge setup time
tH_RD_CS 0 ns RD rising edge to CS rising edge hold time
tHP_RD 10 ns RD high pulse width
tLP_RD 10 ns RD low pulse width
tHP_CS 10 ns CS high pulse width
tD_CS_DB 35 ns Delay from CS until DBx three-state disabled
tH_CS_DB 0 ns CS to DBx hold time
tD_RD_DB Data access time after falling edge of RD
27 ns VDRIVE > 2.7 V
37 ns VDRIVE < 2.7 V
tH_RD_DB 12 ns Data hold time after falling edge of RD
tDHZ_CS_DB 40 ns CS rising edge to DBx high impedance
tCYC_RD RD falling edge to next RD falling edge
30 ns VDRIVE > 2.7 V
40 ns VDRIVE < 2.7 V
tD_CS_FD 26 ns Delay from CS falling edge until FRSTDATA three-state disabled
AD7606B Data Sheet
Rev. 0 | Page 8 of 69
Parameter Min Typ Max Unit Description
tD_RD_FDH 30 ns Delay from RD falling edge until FRSTDATA high
tD_RD_FDL 30 ns Delay from RD falling edge until FRSTDATA low
tDHZ_FD 28 ns Delay from CS rising edge until FRSTDATA three-state enabled
tS_CS_WR 0 ns CS to WR setup time
tHP_WR 213 ns WR high pulse width
tLP_WR WR low pulse width
88 ns VDRIVE > 2.7 V
213 ns VDRIVE < 2.7 V
tH_WR_CS 0 ns WR hold time
tS_DB_WR 5 ns Configuration data to WR setup time
tH_WR_DB 5 ns Configuration data to WR hold time
tCYC_WR 230 ns Configuration data settle time, WR rising edge to next WR rising edge
tDHZ_FD
tD_RD_FDL
tD_RD_FDH
tD_CS_FD
tD_CS_DB tD_RD_DB tCYC_RD
tH_RD_DB
tH_CS_DB
tDHZ_CS_DB
tH_RD_CS
tLP_RD
tHP_RD
tS_CS_RD
VIN8
CS
DB0 TO DB15
FRSTDATA
RD
VIN7
VIN6
VIN5
VIN4
VIN3
VIN2VIN1x
15137-003
Figure 3. Parallel Mode Read Timing Diagram, Separate CS and RD Pulses
t
DHZ_FD
t
DHZ_CS_DB
t
H_CS_DB
t
D_RD_FDL
t
D_CS_FD
t
D_RD_DB
t
HP_CS
t
CYC_RD
t
LP_RD
VIN8
CS AND RD
DB0 TO DB15
FRSTDATA
VIN7
VIN6
VIN5
VIN4
VIN3
VIN2VIN1
15137-004
Figure 4. Parallel Mode Read Timing Diagram, Linked CS and
RD
tH_WR_DB
tH_WR_CS
tS_DB_WR
tS_CS_WR tHP_WR
tLP_WR
tCYC_WR
WR
CS
DB0 TO DB15
15137-005
Figure 5. Parallel Mode Write Operation Timing Diagram
Data Sheet AD7606B
Rev. 0 | Page 9 of 69
Serial Mode Timing Specifications
Table 5.
Parameter Min Typ Max Unit Description
fSCLK SCLK frequency; fSCLK = 1/tSCLK
60 MHz VDRIVE > 2.7 V
40 MHz VDRIVE < 2.7 V
tSCLK 1/fSCLK μs Minimum SCLK period
tS_CS_SCK 2 ns CS to SCLK falling edge setup time
tH_SCK_CS 2 ns SCLK to CS rising edge hold time
tLP_SCK 0.4 × tSCLK ns SCLK low pulse width
tHP_SCK 0.4 × tSCLK ns SCLK high pulse width
tD_CS_DO Delay from CS until DOUTx three-state disabled
9 ns VDRIVE > 2.7 V
18 ns VDRIVE < 2.7 V
tD_SCK_DO Data out access time after SCLK rising edge
15 ns VDRIVE > 2.7 V
25 ns VDRIVE < 2.7 V
tH_SCK_DO 8 ns Data out hold time after SCLK rising edge
tS_SDI_SCK 8 ns Data in setup time before SCLK falling edge
tH_SCK_SDI 0 ns Data in hold time after SCLK falling edge
tDHZ_CS_DO CS rising edge to DOUTx high impedance
7 ns VDRIVE > 2.7 V
22
ns
V
DRIVE
< 2.7 V
tWR 25 ns
Time between writing and reading the same register or between two writes;
if fSCLK >50 MHz
tD_CS_FD 26 ns Delay from CS until DOUTx three-state disabled/delay from CS until MSB valid
tD_SCK_FDL 18 ns 16th SCLK falling edge to FRSTDATA low
tDHZ_FD 28 ns CS rising edge until FRSTDATA three-state enabled
t
D_CS_FD
t
D_CS_DO
t
S_CS_SCK
t
D_SCK_DO
t
H_SCK_DO
t
HP_SCK
t
H_SCK_CS
t
LP_SCK
t
SCLK
t
D_SCK_FDL
t
DHZ_FD
t
DHZ_CS_DO
CS
FRSTDATA
D
OUT
x
SCLK
DB
15
116151432
DB
14
DB
13
DB
2
DB
1
DB
0
15137-006
Figure 6. Serial Timing Diagram, ADC Read Mode (Channel 1)
t
S_SDI_SCK
t
H_SCK_SDI
t
D_CS_DO
t
D_SCK_DO
t
S_CS_SCK
t
HP_SCK
t
H_SCK_CS
t
LP_SCK
t
SCLK
CS
WEN R/W ADD5 ADD0 DIN
7
DIN
0
SDI
D
OUT
x
SCLK 11682 93
D
OUT
7 D
OUT
0
15137-007
t
WR
Figure 7. Serial Interface Timing Diagram, Register Map Read/Write Operations
AD7606B Data Sheet
Rev. 0 | Page 10 of 69
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 6.
Parameter Rating
AVCC to AGND −0.3 V to +7 V
VDRIVE to AGND −0.3 V to AVCC + 0.3 V
Analog Input Voltage to AGND1 ±21 V
Digital Input Voltage to AGND −0.3 V to VDRIVE + 0.3 V
Digital Output Voltage to AGND −0.3 V to VDRIVE + 0.3 V
REFIN to AGND −0.3 V to AVCC + 0.3 V
Input Current to Any Pin Except Supplies1 ±10 mA
Operating Temperature Range −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Junction Temperature 150°C
Pb/Sn Temperature, Soldering
Reflow (10 sec to 30 sec) 240 (+0)°C
Pb-Free Temperature, Soldering Reflow 260 (+0)°C
Electrostatic Discharge (ESD)
All Pins Except Analog Inputs 3.5 kV
Analog Input Pins Only 8 kV
1 Transient currents of up to 100 mA do not cause silicon controlled
rectifier (SCR) latch-up.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit
board (PCB) design and operating environment. Close
attention to PCB thermal design is required.
θJA is the natural convection junction to ambient thermal
resistance measured in a one cubic foot sealed enclosure. θJC is
the junction to case thermal resistance.
Table 7. Thermal Resistance
Package Type θJA1 θJC Unit
ST-64-2 40 7 °C/W
1 Simulated data based on JEDEC 2s2p thermal test PCB in a JEDEC natural
convention environment.
ESD CAUTION
Data Sheet AD7606B
Rev. 0 | Page 11 of 69
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
64
V8GND
63
V8
62
V7GND
61
V7
60
V6GND
59
V6
58
V5GND
57
V5
56
V4GND
55
V4
54
V3GND
53
V3
52
V2GND
51
V2
50
V1GND
49
V1
47
AGND
46
REFGND
45
REFCAPB
42
REFIN/REFOUT
43
REFGND
44
REFCAPA
48
AV
CC
41
AGND
40
AGND
39
REGCAP
37
AV
CC
36
REGCAP
35
AGND
34
REF SELECT
33
DB15
38
AV
CC
2
AGND
3
OS0
4
OS1
7
STBY
6
PAR/S E R S EL
5
OS2
1
AV
CC
8
RANGE
9
CONVST
10
WR
12
RD/SCLK
13
CS
14
BUSY
15
FRSTDATA
16
DB0
11
RESET
17
DB1
18
DB2
19
DB3
20
DB4
21
DB5
22
DB6
23
V
DRIVE
24
DB7/D
OUT
A
25
DB8/D
OUT
B
26
AGND
27
DB9/D
OUT
C
28
DB10/D
OUT
D
29
DB11/SDI
30
DB12
31
DB13
32
DB14
AD7606B
(No t t o Scale)
TOP VI EW
ANALOG INPUT
DECOUP LI NG CA PACITOR PIN
POWER SUPPLY
GRO UND P IN
DATA OUTPUT
DIGITAL OUTPUT
DIGITAL INP UT
REF ERE NCE INPUT/ OUT P UT
15137-008
Figure 8. Pin Configuration
Table 8. Pin Function Description
Pin No. Type 1 Mnemonic Description
1, 37, 38, 48 P AVCC Analog Supply Voltage, 4.75 V to 5.25 V. This supply voltage is applied to the internal front-end
amplifiers and to the ADC core. Decouple these supply pins to AGND.
2, 26, 35, 40,
41, 47
P AGND Analog Ground. These pins are the ground reference points for all analog circuitry on the
AD7606B. All analog input signals and external reference signals must be referred to these pins. All
six of the AGND pins must connect to the AGND plane of a system.
3 to 5 DI OS0 to OS2 Oversampling Mode Pins. These inputs select the oversampling ratio or enable software mode
(see Table 12 for oversampling pin decoding). See the Digital Filter section for more details about
the oversampling mode of operation.
6 DI PAR/SER SEL Parallel/Serial Interface Selection Input. If this pin is tied to a logic low, the parallel interface is
selected. If this pin is tied to a logic high, the serial interface is selected. See the Digital Interface
section for more information on each interface available.
7 DI STBY Standby Mode Input. In hardware mode, this pin, in combination with the RANGE pin, places the
AD7606B in one of two power-down modes: standby mode or shutdown mode. In software mode,
this pin is ignored. Therefore, it is recommended to connect this pin to logic high. See the Power-
Down Modes section for more information on both hardware mode and software mode.
8 DI RANGE Analog Input Range Selection Input. In hardware mode, this pin determines the input range of the
analog input channels (see Table 9). If the STBY pin is at logic low, this pin determines the power-
down mode (see Table 14). In software mode, the RANGE pin is ignored. However, this pin must be
tied high or low.
9 DI CONVST Conversion Start Input. When the CONVST pin transitions from low to high, the analog input is
sampled on all eight SAR ADCs. In software mode, this pin can be configured as external
oversampling clock. Providing a low jitter external clock improves the SNR performance for large
oversampling ratios. See the External Oversampling Clock section for further details.
10 DI WR Digital Input. In hardware mode, this pin has no function. Therefore, it can be tied high, tied low,
or shorted to CONVST. In software mode, this pin is an active low write pin for writing registers
using the parallel interface. See the Parallel Interface section for more information.
AD7606B Data Sheet
Rev. 0 | Page 12 of 69
Pin No. Type 1 Mnemonic Description
11 DI RESET Reset Input, Active High. Full and partial reset options are available on the AD7606B. The type of
reset is determined by the length of the reset pulse. It is recommended that the device receives a
full reset pulse after power-up. See the Reset Functionality section for further details.
12 DI RD/SCLK Parallel Data Read Control Input when the Parallel Interface is Selected (RD).
Serial Clock Input when the Serial Interface is Selected (SCLK). See the Digital Interface section for
more details.
13 DI CS Chip Select. This pin is the active low chip select input for ADC data read or register data read and
write, in both serial and parallel interface. See the Digital Interface section for more details.
14 DO BUSY Busy Output. This pin transitions to a logic high along with the CONVST rising edge. The BUSY
output remains high until the conversion process for all channels is complete.
15 DO FRSTDATA First Data Output. The FRSTDATA output signal indicates when the first channel, V1, is being read
back on the parallel interface (see Figure 3) or the serial interface (see Figure 6). See the Digital
Interface section for more details.
16 to 22 DO/DI DB0 to DB6 Parallel Output/Input Data Bits. When using parallel interface, these pins act as three-state parallel
digital input and output pins (see the Parallel Interface section). When using serial interface, tie
these pins to AGND.
23 P VDRIVE Logic Power Supply Input. The voltage (1.71 V to 3.6 V) supplied at this pin determines the
operating voltage of the interface. This pin is nominally at the same supply as the supply of the
host interface, that is, data signal processing (DSP) and field programmable gate array (FPGA).
24 DO/DI DB7/DOUTA Parallel Output/Input Data Bit 7 (DB7)/Serial Interface Data Output Pin (DOUTA). When using the
parallel interface, this pin acts as a three-state parallel digital input/output pin. When using the
serial interface, this pin functions as DOUTA. See Table 21 and Table 22 for more details on each
data interface and operation mode.
25 DO/DI DB8/DOUTB Parallel Output/Input Data Bit 8 (DB8)/Serial Interface Data Output Pin (DOUTB). When using the
parallel interface, this pin acts as a three-state parallel digital input and output pin. When using
the serial interface, this pin functions as DOUTB. See Table 21 and Table 22 for more details on each
data interface and operation mode.
27 DO/DI DB9/DOUTC Parallel Output/Input Data Bit 9 (DB9)/Serial Interface Data Output Pin (DOUTC). When using the
parallel interface, this pin acts as a three-state parallel digital input and output pin. When using
the serial interface, this pin functions as DOUTC if in software mode and using four data output lines
option. See Table 21 and Table 22 for more details on each data interface and operation mode.
28 DO/DI DB10/DOUTD Parallel Output/Input Data Bit 10 (DB10)/Serial Interface Data Output Pin (DOUTD). When using the
parallel interface, this pin acts as a three-state parallel digital input/output pin. When using the
serial interface, this pin functions as DOUTD if in software mode and using the four data output lines
option. See Table 21 and Table 22 for more details on each data interface and operation mode.
29 DO/DI DB11/SDI Parallel Output/Input Data Bit DB11/Serial Data Input. When using the parallel interface, this pin
acts as a three-state parallel digital input and output pin. When using the serial interface in
software mode, this pin functions as serial data input. See Table 21 and Table 22 for more details
on each data interface and operation mode.
30 to 33 DO/DI DB12 to
DB15
Parallel Output/Input Data Bits, DB15 to DB12. When using the parallel interface, these pins act as
three-state parallel digital input and output pins (see the Parallel Interface section). When using
the serial interface, tie these pins to AGND.
34 DI REF SELECT Internal/External Reference Selection Logic Input. If this pin is set to logic high, the internal
reference is selected and enabled. If this pin is set to logic low, the internal reference is disabled
and an external reference voltage must be applied to the REFIN/REFOUT pin.
36, 39 P REGCAP Decoupling Capacitor Pins for Voltage Output from 1.9 V Internal Regulator, Analog Low
Dropout (ALDO) and Digital Low Dropout (DLDO). These output pins must be decoupled
separately to AGND using a 1 μF capacitor.
42 REF REFIN/
REFOUT
Reference Input (REFIN)/Reference Output (REFOUT). The internal 2.5 V reference is available on
the REFOUT pin for external use while the REF SELECT pin is set to logic high. Alternatively, by
setting the REF SELECT pin to logic low, the internal reference is disabled and an external
reference of 2.5 V must be applied to this input (REFIN). A 100 nF capacitor must be applied from
the REFIN pin to ground, close to the REFGND pins, for both internal and external reference
options. See the Reference section for more details.
43, 46 REF REFGND Reference Ground Pins. These pins must be connected to AGND.
44, 45 REF REFCAPA,
REFCAPB
Reference Buffer Output Force/Sense Pins. These pins must be connected together and decoupled
to AGND using a low effective series resistance (ESR), 10 μF ceramic capacitor. The voltage on
these pins is typically 4.4 V.
49 AI V1 Channel 1 Positive Analog Input Pin.
50 AI GND V1GND Channel 1 Negative Analog Input Pin.
Data Sheet AD7606B
Rev. 0 | Page 13 of 69
Pin No. Type 1 Mnemonic Description
51 AI V2 Channel 2 Positive Analog Input Pin.
52 AI GND V2GND Channel 2 Negative Analog Input Pin.
53 AI V3 Channel 3 Positive Analog Input Pin.
54 AI GND V3GND Channel 3 Negative Analog Input Pin.
55 AI V4 Channel 4 Positive Analog Input Pin.
56 AI GND V4GND Channel 4 Negative Analog Input Pin.
57 AI V5 Channel 5 Positive Analog Input Pin.
58 AI GND V5GND Channel 5 Negative Analog Input Pin.
59 AI V6 Channel 6 Positive Analog Input Pin.
60 AI GND V6GND Channel 6 Negative Analog Input Pin.
61 AI V7 Channel 7 Positive Analog Input Pin.
62 AI GND V7GND Channel 7 Negative Analog Input Pin.
63 AI V8 Channel 8 Positive Analog Input Pin.
64 AI GND V8GND Channel 8 Negative Analog Input Pin.
1 P is power supply, DI is digital input, DO is digital output, REF is reference input/output, AI is analog input, and GND is ground.
AD7606B Data Sheet
Rev. 0 | Page 14 of 69
TYPICAL PERFORMANCE CHARACTERISTICS
–180
–160
–140
–120
–100
–80
–60
–40
–20
0
0.1 110 100
AMPLITUDE ( dB)
INPUT F RE QUENC Y (kHz )
15137-009
AVCC = 5V, VDRIVE = 3.3V
INTERNAL REFE RE NCE
±10V RANG E
fSAMPLE = 800kSPS
fIN = 1kHz
32768 POINT FF T
SNR = 89. 2dB
THD = –108.3d B
Figure 9. Fast Fourier Transform (FFT), ±10 V Range
0.1 110 100
INPUT F RE QUENC Y (kHz )
–180
–160
–140
–120
–100
–80
–60
–40
–20
0
AMPLITUDE ( dB)
15137-010
AV
CC
= 5V, V
DRIVE
= 3.3V
INTERNAL REFE RE NCE
±2.5V RANGE
fSAMPLE
= 800kSPS
fIN
= 1kHz
32768 POINT FF T
SNR = 86d B
THD = –98.5d B
Figure 10. FFT, ±2.5 V Range
ADC CODE
010000 20000 30000 40000 50000 60000
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
INL (L SB)
AVCC = 5V, VDRIVE = 3.3V
INTERNAL REFE RE NCE
fSAMPLE = 800kSPS
T = 25°C
15137-311
Figure 11. Typical INL, ±10 V Range
0.1 110 100
INPUT F RE QUENC Y (kHz )
–180
–160
–140
–120
–100
–80
–60
–40
–20
0
AMPLITUDE ( dB)
15137-012
AVCC = 5V, VDRIVE = 3.3V
INTERNAL REFE RE NCE
±5V RANG E
fSAMPLE = 800kSPS
fIN = 1kHz
32768 POINT FF T
SNR = 88. 3dB
THD = –103dB
Figure 12. FFT, ±5 V Range
010515 20 25
INPUT F RE QUENC Y (kHz )
AVCC = 5V, VDRIVE = 3.3V
INTERNAL REFE RE NCE
±10V RANG E
fSAMPLE = 800kSPS
fIN = 146Hz
8192 POINT FF T
SNR = 93. 6dB
THD = – 110dB
–200
–180
–160
–140
–120
–100
–80
–60
–40
–20
0
AMPLITUDE ( dB)
15137-013
Figure 13. FFT Oversampling by 16, ±10 V Range
ADC CODE
010000 20000 30000 40000 50000 60000
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
DNL (LSB)
AV
CC
= 5V, V
DRIVE
= 3.3V
INTERNAL REFE RE NCE
f
SAMPLE
= 800kSPS
T = 25°C
15137-316
Figure 14. Typical DNL
Data Sheet AD7606B
Rev. 0 | Page 15 of 69
80
82
84
86
88
90
92
94
96
98
100
0.01 0.1 110 100
SNR (dB)
INPUT F RE QUENC Y (kHz )
AV
CC
= 5V, V
DRIVE
= 3.3V
f
SAMPLE
= 800kSPS /O S R
INTERNAL REFE RE NCE
T = 25°C
±10V RANG E
NO OS
OS BY 2
OS BY 4
OS BY 8
OS BY 16
OS BY 32
OS BY 64
OS BY 128
OS BY 256
15137-415
Figure 15. SNR vs. Input Frequency for Different OSR Values, ±10 V Range,
Internal OS Clock
80
82
84
86
88
90
92
94
96
98
100
0.01 0.1 110 100
SNR (dB)
INPUT F RE QUENC Y (kHz )
AVCC = 5V, VDRIVE = 3.3V
fSAMPLE = 800kSPS /O S R
INTERNAL REFE RE NCE
T = 25°C
±5V RANG E
NO OS
OS BY 2
OS BY 4
OS BY 8
OS BY 16
OS BY 32
OS BY 64
OS BY 128
OS BY 256
15137-031
Figure 16. SNR vs. Input Frequency for Different OSR Values, ±5 V Range,
Internal OS Clock
80
82
84
86
88
90
92
94
96
98
100
0.01 0.1 110 100
SNR (dB)
INPUT F RE QUENC Y (kHz )
AV
CC
= 5V, V
DRIVE
= 3.3V
f
SAMPLE
= 800kSPS /O S R
INTERNAL REFE RE NCE
T = 25°C
±2.5V RANGE
NO OS
OS BY 2
OS BY 4
OS BY 8
OS BY 16
OS BY 32
OS BY 64
OS BY 128
OS BY 256
15137-035
Figure 17. SNR vs. Input Frequency for Different OSR Values, ±2.5 V Range,
Internal OS Clock
INPUT F RE QUENC Y (kHz )
80
82
84
86
88
90
92
94
96
98
100
0.01 0.1 110 100
SNR (dB)
AV
CC
= 5V, V
DRIVE
= 3.3V
f
SAMPLE
= 800KSPS /O S R
INTERNAL REFE RE NCE
T = 25°C
±10V RANG E
NO OS
OS BY 2
OS BY 4
OS BY 8
OS BY 16
OS BY 32
OS BY 64
OS BY 128
OS BY 256
15137-034
Figure 18. SNR vs. Input Frequency for Different OSR Values, ±10 V Range,
External OS Clock
80
82
84
86
88
90
92
94
96
98
100
0.01 0.1 110 100
SNR (dB)
INPUT F RE QUENC Y (kHz )
AV
CC
= 5V, V
DRIVE
= 3.3V
f
SAMPLE
= 800kSPS /O S R
INTERNAL REFE RE NCE
T = 25°C
±5V RANG E
NO OS
OS BY 2
OS BY 4
OS BY 8
OS BY 16
OS BY 32
OS BY 64
OS BY 128
OS BY 256
15137-032
Figure 19. SNR vs. Input Frequency for Different OSR Values, ±5 V Range,
External OS Clock
80
85
90
95
100
0.01 0.1 110 100
SNR (dB)
INPUT F RE QUENC Y (kHz )
AVCC = 5V, VDRIVE = 3.3V
fSAMPLE = 800kSPS /O S R
INTERNAL REFE RE NCE
T = 25°C
±2.5V RANGE
NO OS
OS BY 2
OS BY 4
OS BY 8
OS BY 16
OS BY 32
OS BY 64
OS BY 128
OS BY 256
15137-036
Figure 20. SNR vs. Input Frequency for Different OSR Values, ±2.5 V Range,
External OS Clock
AD7606B Data Sheet
Rev. 0 | Page 16 of 69
84
85
86
87
88
89
90
91
–40 –20 020 40 60 80
100 120
SNR (dB)
TEMPERATURE ( °C)
±2.5V
±5V
±10V
AV
CC
= 5V V
DRIVE
= 3.3V
f
SAMPLE
= 800kSPS
15137-333
Figure 21. SNR vs. Temperature
2.495
2.496
2.497
2.498
2.499
2.500
2.501
2.502
2.503
2.504
2.505
–40 –20 020 40
60 80 100 120
REFERENCE VOLTAGE (V)
TEMPERATURE ( °C)
15137-343
AV
CC
= 5V, V
DRIVE
= 3.3V
f
SAMPLE
= 800kSPS
T = 25°C
Figure 22. Reference Drift
–10 –5 0 5 10
REF ERE NCE DRIF T (pp m/°C)
0
5
10
15
20
25
NUMBER O F HI TS
15137-423
Figure 23. Reference Drift Histogram
–120
–110
–100
–90
–80
–70
–60
0.01
0.1 110 100
THD ( dB)
INPUT F RE QUENCY (kHz)
0Ω
1.2kΩ
5kΩ
10kΩ
23.7kΩ
48.7kΩ
105kΩ
±10V RANG E
f
SAMPLE
= 800kSPS
R
SOURCE
MATCHED ON Vx AND VxGND
15137-326
Figure 24. THD vs. Input Frequency for Various Source Impedances,
±10 V Range
–120
–
110
–100
–90
–80
–70
–60
0.01 0.1 110 100
THD ( dB)
INPUT F RE QUENC Y (kHz )
±5V RANG E
fSAMPLE
= 800kSPS
R
SOURCE
MATCHED ON Vx AND VxGND
0Ω
1.2kΩ
5kΩ
10kΩ
23.7kΩ
48.7kΩ
105kΩ
15137-327
Figure 25. THD vs. Input Frequency for Various Source Impedances,
±5 V Range
–120
–
110
–100
–90
–80
–70
–60
0.01 0.1 110 100
THD ( dB)
INPUT F RE QUENC Y (kHz )
±2.5V RANGE
f
SAMPLE
= 800kSPS
R
SOURCE
MATCHED ON Vx AND VxGND
0Ω
1.2kΩ
5kΩ
10kΩ
23.7kΩ
48.7kΩ
105kΩ
15137-330
Figure 26. THD vs. Input Frequency for Various Source Impedances,
±2.5 V Range
Data Sheet AD7606B
Rev. 0 | Page 17 of 69
–30
–20
–10
0
10
20
30
–40 –20 020 40 60 80 100 120
PFS/NFS ERROR (LSB)
TEMPERATURE ( °C)
NFS CH1
NFS CH3
NFS CH5
NFS CH7
PF S CH1
PF S CH3
PF S CH5
PF S CH7
NFS CH2
NFS CH4
NFS CH6
NFS CH8
PF S CH2
PF S CH4
PF S CH6
PF S CH8
15137-320
Figure 27. Positive Full-Scale(PFS)/Negative Full-Scale (NFS) Error vs.
Temperature, ±10 V Range
–25
–20
–15
–10
–5
0
5
10
15
20
25
–40 –20
020 40
60 80 100 120
PFS/NFS ERROR (LSB)
TEMPERATURE ( °C)
NFS CH1
NFS CH3
NFS CH5
NFS CH7
PF S CH1
PF S CH3
PF S CH5
PF S CH7
NFS CH2
NFS CH4
NFS CH6
NFS CH8
PF S CH2
PF S CH4
PF S CH6
PF S CH8
15137-321
Figure 28. PFS/NFS Error vs. Temperature, ±5 V Range
–25
–20
–15
–10
–5
0
5
10
15
20
–40 –20 020 40 60 80 100 120
PFS/NFS ERROR (LSB)
TEMPERATURE ( °C)
NFS CH1
NFS CH3
NFS CH5
NFS CH7
PF S CH1
PF S CH3
PF S CH5
PF S CH7
NFS CH2
NFS CH4
NFS CH6
NFS CH8
PF S CH2
PF S CH4
PF S CH6
PF S CH8
15137-324
Figure 29. PFS/NFS Error vs. Temperature, ±2.5 V Range
15137-430
–10 –5 5
010
NFS DRIFT (ppm/°C)
0
5
10
15
20
25
30
35
40
45
NUMBER OF HIT S
Figure 30. PFS/NFS Drift Histogram, External Reference
15137-431
–10 –5 5
010
NFS DRIFT (ppm/°C)
0
5
10
15
20
25
30
35
40
45
NUMBER OF HIT S
Figure 31. PFS/NFS Drift Histogram, Internal Reference
–100
–90
–80
–70
–60
–50
–40
0.1 110 100
AC PSRR ( dB)
AV
CC
NOI S E FREQUENCY (kHz)
AV
CC
= 5V, V
DRIVE
= 3.3V
INTERNAL REFE RE NCE
RECOMMENDE D DE COUPLI NG USE D
f
SAMPLE
= 800kSPS
T = 25°C
±10V RANG E
±5V RANG E
±2.5V RANGE
15137-042
Figure 32. AC PSRR
AD7606B Data Sheet
Rev. 0 | Page 18 of 69
–6.0
–4.8
–3.6
–2.4
–1.2
0
1.2
2.4
3.6
4.8
6.0
–40 –20 020 40 60 80 100 120
BIPOL AR ZERO CO DE E RROR (LSB)
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
AV
CC
= 5V, V
DRIVE
= 3.3V
INTERNALREFERENCE
fSAMPLE
= 800kSPS
TEMPERATURE ( °C)
15137-022
Figure 33. Bipolar Zero Code Error vs. Temperature, ±10 V Range
–12.0
–9.6
–7.2
–4.8
–2.4
0
2.4
4.8
7.2
9.6
12.0
–40 –20 020 40 60 80 100 120
BIPOL AR ZERO CO DE E RROR (LSB)
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
AV
CC
= 5V, V
DRIVE
= 3.3V
INTERNAL REFE RE NCE
f
SAMPLE
= 800kSPS
TEMPERATURE ( °C)
15137-023
Figure 34. Bipolar Zero Code Error vs. Temperature, ±5 V Range
–24.0
–19.2
–14.4
–9.6
–4.8
0
4.8
9.6
14.4
19.2
24.0
–40 –20 020 40 60 80 100 120
BIPOL AR ZERO CO DE E RROR (LSB)
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
AV
CC
= 5V, V
DRIVE
= 3.3V
INTERNAL REFE RE NCE
f
SAMPLE
= 800kSPS
TEMPERATURE ( °C)
15137-024
Figure 35. Bipolar Zero Code Error vs. Temperature, ±2.5 V Range
Vx AND VxGND
SHORTED TOGETHER
T = 25°C
4096 SAMP LES
MEAN = 32767.8
SIGMA = 1.2
91
458
1163
1303
782
246
0
200
400
600
800
1000
1200
1400
32765 32766 32767 32768 32769 32770 32771 32772
NUMBER O F HI TS
ADC CODE
15137-039
Figure 36. Histogram of Codes, ±10 V Range
6
878
119
0
200
400
600
800
1000
1200
1400
1600
1800
2000
32765 32766 32767 32768 32769 32770 32771 32772
NUMBER O F HI TS
ADC CODE
Vx AND VxGND
SHORTED TOGETHER
T = 25°C
4096 SAMP LES
MEAN = 32767.8
SIGMA = 0.92
1182
177
1727
15137-037
Figure 37. Histogram of Codes, ±5 V Range
8
281
1667 1702
415
23
0
200
400
600
800
1000
1200
1400
1600
1800
32765 32766 32767 32768 32769 32770 32771 32772
NUMBER O F HI TS
ADC CODE
Vx AND VxGND
SHORTED TOGETHER
T = 25°C
4096 SAMP LES
MEAN = 32767.5
SIGMA = 0.8
15137-038
Figure 38. Histogram of Codes, ±2.5 V Range
Data Sheet AD7606B
Rev. 0 | Page 19 of 69
–6
–4
–2
0
2
4
6
–10 –8 –6 –4 –2
0 2 46 8 10
ANALOG INPUT CURRENT (μA)
INPUT VOLTAGE (V)
±10V
±5V
±2.5V
AV
CC
= 5V, V
DRIVE
= 3.3V
fSAMPLE
= 800kSPS
T = 25°C
15137-341
Figure 39. Analog Input Current vs. Input Voltage
0
5
10
15
20
25
30
35
40
45
50
0100 200 300 400 500 600 700 800
AVCC SUPPLY CURRE NT (mA)
THRO UGHPUT RATE (kSPS)
T = –40°C
T = + 25°C
T = + 125°C
AVCC = 5V, VDRIVE = 3.3V
INTERNAL REFE RE NCE
T = 25°C
15137-440
Figure 40. AVCC Supply Current vs. Throughput Rate
0
5
10
15
20
25
30
35
40
45
50
0200 400 600 800 1000
AV
CC
SUPPLY CURRE NT (mA)
THROUGHP UT R AT E (kSPS)
NORMAL MO DE
AUTOSTANDBY MODE
AV
CC
= 5V, V
DRIVE
= 3.3V
INTERNAL REFE RE NCE
T = 25°C
15137-441
Figure 41. AVCC Supply Current vs. Throughput Rate
–140
–130
–120
–110
–100
–90
–80
–70
–60
–50
020 40 60 80 100 120 140 160
CHANNELTO CHANNE L ISOLATION (dB)
NOI S E FREQUENCY (kHz )
AVCC = 5V,VDRIVE = 3.3V
INTERNAL REFE RE NCE
f
SAMPLE = 800kSPS
T = 25°C
INTERF E RE R IN ALL
UNSEL E CTED CHANNE LS
±10V RANG E
±5V RANG E
±2.5V RANGE
15137-043
Figure 42. Channel to Channel Isolation vs. Noise Frequency
AD7606B Data Sheet
Rev. 0 | Page 20 of 69
TERMINOLOGY
Integral Nonlinearity (INL)
INL is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The
endpoints of the transfer function are zero scale at ½ LSB below
the first code transition and full scale at ½ LSB above the last code
transition.
Differential Nonlinearity (DNL)
DNL is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Bipolar Zero Code Error
Bipolar zero code error is the deviation of the midscale
transition (all 1s to all 0s) from the ideal, which is 0 V − ½ LSB.
Bipolar Zero Code Error Match
Bipolar zero code error match is the absolute difference in
bipolar zero code error between any two input channels.
Open Circuit Code Error
Open circuit code error is the ADC output code when there is an
open circuit on the analog input, and a pull-down resistor (RPD)
connected between the analog input pair of pins. See Figure 59
for more details.
Positive Full-Scale (PFS) Error
PFS error is the deviation of the actual last code transition from
the ideal last code transition (10 V − 1½ LSB (9.99954), 5 V −
1½ LSB (4.99977), and 2.5 V − 1½ LSB (2.49988)) after the
bipolar zero code error is adjusted out. The positive full-scale
error includes the contribution from the internal reference and
reference buffer.
Positive Full-Scale Error Match
PFS error match is the absolute difference in positive full-scale
error between any two input channels.
Negative Full-Scale (NFS) Error
NFS error is the deviation of the first code transition from the
ideal first code transition (−10 V + ½ LSB (−9.99984), −5 V + ½
LSB (−4.99992), and −2.5 V + ½ LSB (−2.49996)) after the
bipolar zero code error is adjusted out. The negative full-scale
error includes the contribution from the internal reference and
reference buffer.
Negative Full-Scale Error Match
NFS error match is the absolute difference in negative full-scale
error between any two input channels.
Total Unadjusted Error (TUE)
TUE is the maximum deviation of the output code from the
ideal. TUE includes INL errors, bipolar zero code and positive
and negative full-scale errors, and reference errors.
Signal-to-Noise-and-Distortion Ratio (SINAD)
SINAD ratio is the measured ratio of signal-to-noise-and-
distortion at the output of the ADC. The signal is the rms
amplitude of the fundamental. Noise is the sum of all
nonfundamental signals up to half the sampling frequency (fS/2,
excluding dc).
The ratio depends on the number of quantization levels in
the digitization process: the more levels, the smaller the
quantization noise.
The theoretical SINAD for an ideal N-bit converter with a sine
wave input is given by
SINAD = (6.02 N + 1.76) (dB)
Thus, for a 16-bit converter, the SINAD is 98 dB.
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the harmonics to the
fundamental. For the AD7606B, THD is defined as
THD (dB) =
20log
22222222
23456789
1
VVVVVVVV
V
+++++++
where:
V1 is the rms amplitude of the fundamental.
V2 to V9 are the rms amplitudes of the second through ninth
harmonics.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is the ratio of the rms value of the
next largest component in the ADC output spectrum (up to fS/2,
excluding dc) to the rms value of the fundamental. Normally, the
value of this specification is determined by the largest harmonic
in the spectrum, but for ADCs where the harmonics are buried
in the noise floor, the value is determined by a noise peak.
Power Supply Rejection Ratio (PSRR)
Variations in power supply affect the full-scale transition but
not the linearity of the converter. The power supply rejection (PSR)
is the maximum change in full-scale transition point due to a
change in power supply voltage from the nominal value. The
PSRR is defined as the ratio of the 100 mV p-p sinewave applied
to the AVCC supplies of the ADC frequency, fS, to the power of
the ADC output at that frequency, fS.
PSRR (dB) = 20 log (0.1/PfS)
where:
PfS is equal to the power at frequency, fS, coupled on the AVCC
supply.
Channel to Channel Isolation
Channel to channel isolation is a measure of the level of
crosstalk between all input channels. It is measured by applying
a full-scale sine wave signal, up to 160 kHz, to all unselected
input channels and then determining the degree to which the
signal attenuates in the selected channel with a 1 kHz sine wave
signal applied (see Figure 42).
Data Sheet AD7606B
Rev. 0 | Page 21 of 69
Phase Delay
Phase delay is a measure of the absolute time delay between
when an input is sampled by the converter and when the result
associated with that sample is available to be read back from the
ADC, including delay induced by the analog front end of the
device.
Phase Delay Drift
Phase delay drift is the change in phase delay per unit temperature
across the entire operating temperature of the device.
Phase Delay Matching
Phase delay matching is the maximum phase delay seen between
any simultaneously sampled pair.
AD7606B Data Sheet
Rev. 0 | Page 22 of 69
THEORY OF OPERATION
ANALOG FRONT END
The AD7606B is a 16-bit, simultaneous sampling, analog-to-
digital DAS with eight channels. Each channel contains analog
input clamp protection, a PGA, a low-pass filter, and a 16-bit
SAR ADC.
Analog Input Ranges
The AD7606B can handle true bipolar, single-ended input
voltages. In hardware mode, the logic level on the RANGE pin
determines either ±10 V or ±5 V as the analog input range of all
analog input channels, as shown in Table 9.
A logic change on the RANGE pin has an immediate effect on
the analog input range. However, there is typically a settling
time of approximately 80 µs in addition to the normal acquisition
time requirement. Changing the RANGE pin during a conversion
is not recommended for fast throughput rate applications.
In software mode, it is possible to configure an individual
analog input range per channel using Address 0x03 through
Address 0x06. The logic level on the RANGE pin is ignored in
software mode.
Table 9. Analog Input Range Selection
Range (V) Hardware Mode1 Software Mode2
±10 RANGE pin high
Address 0x03 through
Address 0x06
±5 RANGE pin low Address 0x03 through
Address 0x06
±2.5 Not applicable Address 0x03 through
Address 0x06
1 The same analog input range, ±10 V or ±5 V, applies to all eight channels.
2 The analog input range (±10 V, ±5 V, or ±2.5 V) is selected on a per channel
basis using the memory map.
Analog Input Impedance
The analog input impedance of the AD7606B is typically 5 MΩ.
This is a fixed input impedance that does not vary with the
AD7606B sampling frequency. This high analog input
impedance eliminates the need for a driver amplifier in front of
the AD7606B, allowing direct connection to the source or
sensor. Therefore, bipolar supplies can be removed from the
signal chain.
Analog Input Clamp Protection
Figure 43 shows the analog input circuitry of the AD7606B.
Each analog input of the AD7606B contains clamp protection
circuitry. Despite single, 5 V supply operation, this analog input
clamp protection allows an input overvoltage of up to ±21 V.
CLAMP 5MΩ
CLAMP 5MΩ
Vx
VxGND LPF
16-BIT
SAR ADC
15137-047
Figure 43. Analog Input Circuitry for Each Channel
Figure 44 shows the input clamp current vs. the source voltage
characteristic of the clamp circuit. For input voltages of up to
±21 V, no current flows in the clamp circuit. For input voltages
that are above ±21 V, the AD7606B clamp circuitry turns on.
–15
–10
–5
0
5
10
15
–30 –20 –10 010 20 30
INPUT CL AMP CURRENT ( mA)
SOURCE V OLTAGE (V)
TA = –40° C
TA = +25°C
TA = +125°C
15137-248
Figure 44. Input Protection Clamp Profile
It is recommended to place a series resistor on the analog input
channels to limit the current to ±10 mA for input voltages
greater than ±21 V. In an application where there is a series
resistance (R) on an analog input channel, Vx, it is recommended
to match the resistance (R) with the resistance on VxGND to
eliminate any offset introduced to the system, as shown in
Figure 45. However, in software mode, there is a per channel
system offset calibration that removes the offset of the full
system (see the System Offset Calibration section).
During normal operation, it is not recommended to leave the
AD7606B in a condition where the analog input is greater than
the input range for extended periods of time because this can
degrade the bipolar zero code error performance. In shutdown
or standby mode, there is no such concern.
CLAMP 5MΩ
CLAMP
VxGND
R
RC
Vx
5MΩ
AD7606B
15137-049
Figure 45. Input Resistance Matching on the Analog Input of the AD7606B
PGA
A PGA is provided at each input channel. The gain is configured
depending on the analog input range selected (see Tabl e 9) to
scale the single-ended analog input signal to the ADC fully
differential input range.
Input impedance on each input of the PGA is accurately trimmed
to maintain the overall gain error. This trimmed value is then
used when the gain calibration is enabled to compensate for the
gain error introduced by an external series resistor. See the
System Gain Calibration section for more information on the
PGA feature.
Data Sheet AD7606B
Rev. 0 | Page 23 of 69
Analog Input Antialiasing Filter
An analog antialiasing filter is provided on the AD7606B.
Figure 46 and Figure 47 show the frequency response and phase
response, respectively, of the analog antialiasing filter. In the
±10 V range, the −3 dB frequency is typically 22.5 kHz.
100 1k 10k 100k
A
TTENU
A
TION (dB)
INPUT FREQUENCY (Hz)
±10V RANGE
±5V RANGE
±2.5V RANGE
15137-050
Figure 46. Analog Antialiasing Filter Frequency Response
0
2
4
6
8
10
12
14
16
100 1k 10k 100k
PHASE DEL
A
Y (μs)
INPUT FREQUENCY (Hz)
AV
CC
= 5V, V
DRIVE
= 3.3V
f
SAMPLE
= 800kSPS
T = 25°C
±10V
±5V
±2.5V
15137-051
Figure 47. Analog Antialiasing Filter Phase Response
SAR ADC
The AD7606B allows the ADC to accurately acquire an input
signal of full-scale amplitude to 16-bit resolution. All eight SAR
ADCs sample the respective inputs simultaneously on the rising
edge of the CONVST signal.
The BUSY signal indicates when conversions are in progress.
Therefore, when the rising edge of the CONVST signal is applied,
the BUSY pin goes logic high and transitions low at the end of
the entire conversion process. The end of the conversion process
across all eight channels is indicated by the falling edge of the
BUSY signal. When the BUSY signal edge falls, the acquisition
time for the next set of conversions begins. The rising edge of the
CONVST signal has no effect while the BUSY signal is high.
New data can be read from the output register via the parallel or
serial interface after the BUSY output goes low. Alternatively,
data from the previous conversion can be read while the BUSY pin
is high, as explained in the Reading During Conversion section.
The AD7606B contains an on-chip oscillator that performs the
conversions. The conversion time for all ADC channels is tCONV
(see Table 3). In software mode, there is an option to apply an
external clock through the CONVST pin. Providing a low jitter
external clock improves SNR performance for large oversampling
ratios. See the Digital Filter section and Figure 15 to Figure 20
for further information.
Connect all unused analog input channels to AGND. The
results for any unused channels are still included in the data
read because all channels are always converted.
ADC Transfer Function
The output coding of the AD7606B is twos complement. The
designed code transitions occur midway between successive
integer LSB values, that is, 1/2 LSB and 3/2 LSB. The LSB size is
FSR/65,536 for the AD7606B. The ideal transfer characteristics for
the AD7606B are shown in Figure 48. The LSB size is dependent on
the analog input range selected, as shown in Table 10.
011...111
LSB =
NFS + 1/2LSB PFS – 3/2LSB0v – 1/2LSB
ANALOG INPUT
PFS – (NFS)
2N*
±10V CODE = × 32,768
V
x
10V
±5V CODE = × 32,768
Vx
5V
±2.5V CODE = × 32,768
Vx
2.5V
ADC CODE
100...000
100...001
100...010
111...111
000...001
000...000
011...110
15137-052
Figure 48. Ideal Transfer Characteristics
Table 10. Input Voltage Ranges
Range (V) PFS (V) Midscale (V) NFS (V) LSB (μV)
±10 +10 0 −10 305
±5 +5 0 −5 152
±2.5 +2.5 0 −2.5 76
REFERENCE
The AD7606B contains an on-chip, 2.5 V, band gap reference.
The REFIN/REFOUT pin allows either
Access to the internal 2.5 V reference, if the
REF SELECT pin is tied to logic high.
Application of an external reference of 2.5 V, if the REF
SELECT pin is tied to logic low.
Table 11. Reference Configuration
REF SELECT Pin Reference Selected
Logic High Internal reference enabled
Logic Low Internal reference disabled; an external 2.5 V
reference voltage must be applied to the
REFIN/REFOUT pin
AD7606B Data Sheet
Rev. 0 | Page 24 of 69
The AD7606B contains a reference buffer configured to gain the
reference voltage up to approximately 4.4 V, as shown in Figure 49.
The 4.4 V buffered reference is the reference used by the SAR
ADC, as shown in Figure 49. After a reset, the AD7606B operates
in the reference mode selected by the REF SELECT pin. The
REFCAPA and REFCAPB pins must be shorted together
externally, and a ceramic capacitor of 10 μF must be applied to
the REFGND pin to ensure that the reference buffer is in closed-
loop operation. A 10 µF ceramic capacitor is required on the
REFIN/REFOUT pin.
When the AD7606B is configured in external reference mode,
the REFIN/REFOUT pin is a high input impedance pin.
2.5V
REF
REFIN/REFOUT
REFCAPA
10µF
REFCAPB
SAR
BUF
15137-053
Figure 49. Reference Circuitry
Using Multiple AD7606B Devices
For applications using multiple AD7606B devices, the following
configurations are recommended, depending on the application
requirements.
External Reference Mode
One external reference can drive the REFIN/REFOUT pins of
all AD7606B devices (see Figure 50). In this configuration,
decouple each REFIN/REFOUT pin of the AD7606B with at
least a 100 nF decoupling capacitor.
REF
REF SELECT
REFIN/REFOUT
100nF
1µF
AD7606B
REF SELECT
REFIN/REFOUT
100nF
AD7606B
REF SELECT
REFIN/REFOUT
100nF
AD7606B
15137-054
Figure 50. Single External Reference Driving Multiple AD7606B
REFIN/REFOUT Pins
Internal Reference Mode
One AD7606B device, configured to operate in internal
reference mode, can drive the remaining AD7606B devices,
which are configured to operate in external reference mode (see
Figure 51). Decouple the REFIN/REFOUT pin of the AD7606B,
configured in internal reference mode, using a 10 µF ceramic
decoupling capacitor. The other AD7606B devices, configured in
external reference mode, must use at least a 100 nF decoupling
capacitor on their REFIN/REFOUT pins.
REF SELECT
REFIN/REFOUT
10µF
V
DRIVE
AD7606B
REF SELECT
REFIN/REFOUT
100nF
AD7606B
REF SELECT
REFIN/REFOUT
100nF
AD7606B
+
15137-055
Figure 51. Internal Reference Driving Multiple AD7606B REFIN/REFOUT Pins
OPERATION MODES
The AD7606B can be operated in hardware or software mode
by controlling the OSx pins (Pin 3, Pin 4, and Pin 5), described
in Tabl e 12.
In hardware mode, the AD7606B is configured depending on
the logic level on the RANGE, OSx, or STBY pins.
In software mode, that is, when all three OSx pins are connected
to logic high level, the AD7606B is configured by the
corresponding registers accessed via the serial or parallel interface.
Additional features are available, as described in Table 13.
The reference and the data interface is selected using the
REF SELECT and PAR/SER SEL pins, in both hardware and
software modes.
Table 12. Oversampling Pin Decoding
OSx Pins AD7606B
000 No OS
001 2
010 4
011 8
100 16
101 32
110 64
111 Enters software mode
Data Sheet AD7606B
Rev. 0 | Page 25 of 69
Table 13. Functionality Matrix
Parameter Hardware Mode Software Mode
Analog Input Range1 ±10 V or ±5 V2 ±10 V, ±5 V, or ±2.5 V3
System Gain, Phase, and Offset Calibration Not accessible Available3
OSR From no OS to OSR = 64 From no OS to OSR = 256
Analog Input Open Circuit Detection Not accessible Available3
Serial Data Output Lines 2 Selectable: 1, 2, or 4
Diagnostics Not accessible Available
Power-Down Modes Standby and shutdown Standby, shutdown, and autostandby
1 See Table 9 for the analog input range selection.
2 Same input range configured in all input channels.
3 On a per channel basis.
AD7606B Data Sheet
Rev. 0 | Page 26 of 69
Reset Functionality
The AD7606B has two reset modes: full or partial. The reset
mode selected is dependent on the length of the reset high
pulse. A partial reset requires the RESET pin to be held high
between 55 ns and 2 μs. After 50 ns from the release of the
RESET pin (tDEVICE_SETUP, partial reset), the device is fully functional
and a conversion can be initiated. A full reset requires the
RESET pin to be held high for a minimum of 3 µs. After 253 μs
(tDEVICE_SETUP, full reset) from the release of the RESET pin, the
device is completely reconfigured and a conversion can be
initiated.
A partial reset reinitializes the following modules:
• Digital filter.
• SPI and parallel, resetting to ADC mode.
• SAR ADCs.
• CRC logic.
After the partial reset, the RESET_DETECT bit of the status
register asserts (Address 0x01, Bit 7).The current conversion
result is discarded after the completion of a partial reset. The
partial reset does not affect the register values programmed in
software mode or the latches that store the user configuration in
both hardware and software modes.
A full reset returns the device to the default power-on state, the
RESET_DETECT bit of the status register asserts (Address 0x01,
Bit 7), and the current conversion result is discarded. The
following features, in addition to those listed previously, are
configured when the AD7606B is released from full reset:
• Hardware mode or software mode.
• Interface type (serial or parallel).
Power-Down Modes
In hardware mode, two power-down modes are available on the
AD7606B: standby mode and shutdown mode. The STBY pin
controls whether the AD7606B is in normal mode or in one of the
two power-down modes, as shown in Table 14. If the STBY pin
is low, the power-down mode is selected by the state of the
RANGE pin.
Table 14. Power-Down Mode Selection, Hardware Mode
Power Mode STBY Pin RANGE Pin
Normal Mode 1 X1
Standby 0 1
Shutdown 0 0
1 X = don’t care.
In software mode, the power-down mode is selected through
the OPERATION_MODE bits on the CONFIG register
(Address 0x02, Bits[1:0]) within the memory map. There is an
extra power-down mode available in software mode called
autostandby mode.
Table 15. Power-Down Mode Selection, Software Mode,
Through CONFIG Register (Address 0x02)
Operation Mode Address 0x02, Bit 1 Address 0x02, Bit 0
Normal 0 0
Standby 0 1
Autostandby 1 0
Shutdown 1 1
When the AD7606B is placed in shutdown mode, all circuitry is
powered down and the current consumption reduces to 5 µA,
maximum. The power-up time is approximately 10 ms. When
the AD7606B is powered up from shutdown mode, a full reset
must be applied to the AD7606B after the required power-up
time elapses.
When the AD7606B is placed in standby mode, all the PGAs
and all the SAR ADCs enter a low power mode, such that the
overall current consumption reduces to 4.5 mA, maximum. No
reset is required after exiting standby mode.
When the AD7606B is placed in autostandby mode, available
only in software mode the device automatically enters standby
mode on the BUSY signal falling edge. The AD7606B exits
standby mode automatically on the CONVST signal rising edge.
Therefore, the CONVST signal low pulse time is longer than
tWA K E _ U P (standby mode) = 1 μs.
CONVST
BUSY
POWER MODE STANDBY NORMAL
t
WAKE_UP
STANDBY
15137-056
Figure 52. Autostandby Mode Operation
Data Sheet AD7606B
Rev. 0 | Page 27 of 69
DIGITAL FILTER
The AD7606B contains an optional digital averaging filter that
can be enabled in slower throughput rate applications that require
higher SNR or dynamic range.
In hardware mode, the oversampling ratio of the digital filter is
controlled using the oversampling pins, OSx, as shown in Table 12.
The OSx pins are latched on the falling edge of the BUSY signal.
In software mode, that is, if all OSx pins are tied to logic high,
the oversampling ratio is selected through the oversampling
register (Address 0x08). Two additional oversampling ratios
(OS × 128 and OS × 256) are available in software mode.
In oversampling mode, the ADC takes the first sample for each
channel on the rising edge of the CONVST signal. After
converting the first sample, the subsequent samples are taken by
the internally generated sampling signal, as shown in Figure 53.
Alternatively, this sampling signal can be applied externally as
described in the External Oversampling Clock section.
For example, if oversampling by eight is configured, eight
samples are taken, averaged, and the result is provided on the
output. A CONVST signal rising edge triggers the first sample,
and the remaining seven samples are taken with an internally
generated sampling signal. Consequently, turning on the
averaging of multiple samples leads to an improvement in SNR
performance, at the expense of reducing the maximum throughput
rate. When the oversampling function is turned on, the BUSY
signal high time (tCONV) extends, as shown in Table 3. Table 16
shows the trade-off in SNR vs. bandwidth and throughput for
the ±10 V, ±5 V, and ±2.5 V ranges.
t
CYCLE
t
CONV
CONVST
OS CLOCK
BUSY
DATA:
DB0 TO DB15
CS
RD
15137-057
Figure 53. Oversampling by 8 Example, Read After Conversion, Parallel
Interface, OS Clock Internally Generated Sampling Signal
Figure 53 shows that the conversion time (tCONV) extends when
oversampling is turned on. The throughput rate (1/tCYCLE) must be
reduced to accommodate the longer conversion time and to allow
the read operation to occur. To achieve the fastest throughput rate
possible when oversampling is turned on, the read can be
performed during the BUSY signal high time as explained in the
Reading During Conversion section.
Table 16. Oversampling Performance
OS
Ratio
Input
Frequency (Hz)
±10 V Range ±5 V Range ±2.5 V Range
Maximum Throughput
(kSPS)
SNR (dB)
3 dB
BW (kHz) SNR (dB)
3 dB
BW (kHz) SNR (dB)
3 dB
BW (kHz)
No OS 1000 89.5 23.0 88.5 13.9 86 11.6 800
2 1000 91 22.7 89.9 13.8 87.2 11.5 400
4 1000 92.2 22.0 90.8 13.6 88 11.4 200
8 1000 93 20.0 91.5 13.0 88.4 11.1 100
16 1000 93.5 15.4 92 11.4 89 10.0 50
32 130 95.4 9.7 93.7 8.4 90.4 7.7 25
64 130 96.3 5.3 95 5.0 91.8 4.9 12.5
1281 50 97.1 2.7 95.9 2.7 93.3 2.7 6.25
2561 50 97.6 1.4 96.8 1.4 94.7 1.4 3.125
1 Only available in software mode.
AD7606B Data Sheet
Rev. 0 | Page 28 of 69
PADDING OVERSAMPLING
As shown in Figure 53, an internally generated clock triggers
the samples to be averaged, and then the ADC remains idle
until the following CONVST signal rising edge. In software
mode, through the oversampling register (Address 0x08), the
internal clock (OS clock) frequency can be changed such that idle
time is minimized, that is sampling instants are equally spaced, as
shown in Figure 54.
t
CYCLE
t
CONV
CONVST
OS CLOCK
BUSY
15137-158
Figure 54. Oversampling by 8 Example, Oversampling Padding Enabled
Table 17. OS_PAD Bit Decoding
OS_PAD (Address 0x08, Bits[7:5]) OS Clock Frequency (kHz)
0000 800
0001 753
0010 711
0011 673.5
0100 640
0101 609.5
0110 582
0111 556.5
1000 533
1001 512
1010 492.5
1011 474
1100 457
1101 441.5
1110 426.5
1111 413
EXTERNAL OVERSAMPLING CLOCK
In software mode, there is an option to apply an external clock
through the CONVST pin when oversampling mode is enabled.
Providing a low jitter external clock improves SNR performance
for large oversampling ratios. By applying an external clock, the
input is sampled at regular time intervals, which is optimum for
antialiasing performance.
To enable the external oversampling clock, Bit 5 in the CONFIG
register (Address 0x02, Bit 5) must be set. Then, the throughput
rate is
1
=×
CNVST
Throughput t OSR
That is, the sampling signal is provided externally through the
CONVST pin, and every OSR number of clocks, an output is
averaged and provided, as shown in Figure 55. This feature is
available using either the parallel interface or the serial interface.
CONVST
BUSY
DB0 TO DB15
CS
RD
t
CNVST
15137-159
Figure 55. External Oversampling Clock Applied on the CONVST Pin (OSR = 4); Parallel Interface
Data Sheet AD7606B
Rev. 0 | Page 29 of 69
SYSTEM CALIBRATION FEATURES
The following system calibration features are available in
software mode by writing to corresponding registers in the
memory map:
• Phase calibration.
• Gain calibration.
• Offset calibration.
• Analog Input open circuit detection.
SYSTEM PHASE CALIBRATION
When using an external filter, as shown in Figure 57, any
mismatch on the discrete components, or in the sensor used,
can cause phase mismatch between channels. This phase mismatch
can be compensated for in software mode, on a per channel
basis, by delaying the sampling instant on individual channels.
The sampling instant on any particular channel can be delayed
with regard to the CONVST signal rising edge, with a resolution of
1.25 μs, and up to 318.75 μs, by writing to the corresponding
CHx_PHASE register (Address 0x19 through Address 0x20).
For example, if the CH4_PHASE register (Address 0x1C) is
written with 10d, Channel 4 is effectively sampled 12.5 μs
(tPHASE_REG) after the CONVST signal rising edge, as shown in
Figure 56.
t
PHASE_REG
t
CONV
CONVST
INPUT V1
INPUT V4
V1 CODE
V4 CODE
INTERNAL
CONVS T CH1
INTERNAL
CONVS T CH4
BUSY
15137-160
Figure 56. System Phase Calibration Functionality
The BUSY signal high time equals tCONV plus tPHASE_REG, as shown in
Figure 56. In the previously explained example and Figure 56, if
only CH4_PHASE_REGISTER is programmed, tCONV increases
by 12.5 μs. Therefore, this scenario must be taken into account
when running at higher throughput rates.
SYSTEM GAIN CALIBRATION
Using an external RFILTER, as shown in Figure 57, generates a
system gain error. This gain error can be compensated for in
software mode, on a per channel basis, by writing the series
resistor value used on the corresponding register, Address 0x09
through Address 0x10. These registers can compensate up to
65 kΩ series resistors, with a resolution of 1024 Ω.
5MΩ
ANALOG
INPUT
SIGNAL VxGND
R
FILTER
R
FILTER
C
Vx
5MΩ
AD7606B
15137-060
Figure 57. System Gain Error
For example, if a 27 kΩ resistor is placed in series to the analog
input of Channel 5, the resistor generates −170 LSB positive
full-scale error on the system (at ±10 V range), as shown in
Figure 58. In software mode, this error is eliminated by writing
27d to the CH5_GAIN register (Address 0x0D).
010 20 30
RFILTER (kΩ)
PFS (LSB)
40 50 60
–500
–400
–300
–200
–100
0
SYSTEM GAIN CALIBRATION OFF
SYSTEM GAIN CALIBRATION ON
15137-162
Figure 58. System Gain Calibration with and Without Calibration
SYSTEM OFFSET CALIBRATION
A potential offset on the sensor, or any offset caused by a
mismatch between the RFILTER pair placed on a particular
channel (as described in the Analog Front End section), can be
compensated in software mode, on a per channel basis. The
CHx_OFFSET registers (Address 0x11 through Address 0x18)
allow the ability to add or subtract up to 128 LSB from the ADC
code automatically, with a resolution of 1 LSB, as shown in
Tabl e 18.
For example, if the signal connected to Channel 3 has a 9 mV
offset, and the analog input range is set to the ±10 V range
(where LSB size = 305 μV) to compensate for this offset,
program −30 LSB to the corresponding register. Writing 128d −
30d = 0x80 − 0x1E = 0x62 to the CH3_OFFSET register
(Address 0x13) removes such offset.
Table 18. CHx_OFFSET Register Bit Decoding
CHx_OFFSET Register Offset Calibration (LSB)
0x00 −128
0x45 −59
0x80 (Default) 0
0x83 +3
0xFF +127
AD7606B Data Sheet
Rev. 0 | Page 30 of 69
ANALOG INPUT OPEN CIRCUIT DETECTION
The AD7606B has an analog input open circuit detection
feature available in software mode. To use this feature, RPD must
be placed as shown in Figure 59. If the analog input is
disconnected, for example, if a switch opens in Figure 59, the
source impedance changes from RS to RPD, as long as RS < RPD. It
is recommended to use RPD = 50 kΩ so that the AD7606B can
detect changes in the source impedance by internally switching
the PGA common-mode voltage. Analog input open circuit
detection operates in manual mode or in automatic mode.
5MΩ
Vx–
R
FILTER
R
FILTER
R
PD
C
Vx+
AD7606B
SAR
ADC
15137-061
5MΩ
R
SFILTER
Figure 59. Analog Front End with RPD
Manual Mode
In manual mode, enabled by writing 0x01 to OPEN_DETECT_
QUEUE (Address 0x2C), each PGA common-mode voltage is
controlled by the corresponding CHx_OPEN_DETECT_EN bit
on the OPEN_DETECT_ENABLE register (Address 0x23).
Setting this bit high shifts up the PGA common-mode voltage.
If there is an open circuit on the analog input, the ADC output
changes proportionally to the RPD resistor, as shown in Figure 60. If
there is not an open circuit, any change on the PGA common-
mode voltage has no effect on the ADC output.
100
ADC CODE INCREM E NT (LSB)
120
R
PD
(kΩ)
80
60
40
20
100
806040
20
00
10V
5V
2.5V
15137-460
Figure 60. Open Circuit Code Error Increment, Dependent of RPD
Automatic Mode
Automatic mode is enabled by writing any value greater than
0x01 to the OPEN_DETECT_QUEUE register (Address 0x2C), as
shown in Tabl e 19. If the AD7606B detects that the ADC reported a
number (specified in the OPEN_DETECT_QUEUE register) of
consecutive unchanged conversions, the analog input open circuit
detection algorithm is performed internally and automatically.
The analog input open circuit detection algorithm automatically
changes the PGA common-mode voltage, checks the ADC
output, and returns to the initial common-mode voltage, as
shown in Figure 61. If the ADC code changes in any channel
with the PGA common-mode change, this implies that there is
no input signal connected to that analog input, and the
corresponding flag asserts within the OPEN_DETECTED
register (Address 0x24). Each channel can be individually
enabled or disabled through the OPEN_DETECT_
ENABLE register (Address 0x23).
START
CONVERSION
0 < ADC CO DE < 350 LSB i = 0
YES
YES
ERROR FL AG
YES; SET
COMMON MODE HIGH
N = NUMBER OF
CONSECUTIVE REPEATED
(W IT HIN 10 L SB)
ADC OUTPUT CODE
YES; SET
COMMON MODE LOW
NO
i = i + 1 i = N?
NO
i = 0
NO
i = 0
NO
ΔADC CODE > 20 LSB
ADC CODE BACK
TO ORIGINAL?
15137-165
Figure 61. Automatic Analog Input Open Circuit Detect Flowchart
If no oversampling is used, the recommended minimum
number of conversions to be programmed for the AD7606B to
automatically detect an open circuit on the analog input is
( )
__
10 2
=
× +× ×
SAMPLE PD FILTER FILTER
OPEN DETECT QUEUE
fR R C
However, when oversampling mode is enabled, the
recommended minimum number of conversions to use is
( )
( )
__
1 22
=
+ × +× × ×
SAMPLE PD FILTER FILTER
OPEN DETECT QUEUE
f R R C OSR
Data Sheet AD7606B
Rev. 0 | Page 31 of 69
Table 19. Analog Input Open Circuit Detect Mode Selection and Register Functionality
OPEN_DETECT_QUEUE
(Address 0x2C) Open Detect Mode OPEN_DETECT_ENABLE (Address 0x23)
0x00 (Default) Disabled Not applicable
0x01 Manual mode Sets common-mode voltage high or low, on a
per channel basis
0x02 to 0xFF Automatic; OPEN_DETECT_QUEUE is the number of
consecutive conversions before asserting any CHx_OPENED flag
Enables or disables automatic analog input
open circuit detection on a per channel basis
AD7606B Data Sheet
Rev. 0 | Page 32 of 69
DIGITAL INTERFACE
The AD7606B provides two interface options: a parallel interface
and a high speed serial interface. The required interface mode is
selected via the PAR/SER SEL pin.
Table 20. Interface Mode Selection
PAR/SER SEL Interface Mode
0 Parallel interface mode
1 Serial interface mode
Operation of the interface modes is discussed in the following
sections.
HARDWARE MODE
In hardware mode, only ADC mode is available. ADC data can
be read from the AD7606B via the parallel data bus with standard
CS and RD signals or via the serial interface with standard CS,
SCLK, and two DOUTx signals.
See the Reading Conversion Results (Parallel ADC Mode) section
and the Reading Conversion Results (Serial ADC Mode) section
for more details on how ADC read mode operates.
SOFTWARE MODE
In software mode, which is active only when all three
oversampling pins are tied high, both ADC read mode and
register mode are available. ADC data can be read from the
AD7606B, and registers can also be read from and written to
the AD7606B via the parallel data bus with standard CS, RD,
and WR signals or via the serial interface with standard CS,
SCLK, SDI, and DOUTA lines.
See the Parallel Register Mode (Writing Register Data) section
and the Parallel Register Mode (Reading Register Data) section
for more details on how register mode operates.
Pin functions differ depending on the interface selected
(parallel or serial) and the operation mode (hardware or
software), as shown in Tabl e 21 and Table 22.
Table 21. Data Interface Pin Function per Mode of Operation (Parallel Interface)
Pin Name Pin No. Hardware Mode
Software Mode
ADC Mode Register Mode
DB0 to DB6 16 to 22 DB0 to DB6 Register data
DB7/DOUTA 24 DB7 Register data (MSB)
DB8/DOUTB 25 DB8 ADD0
DB9/DOUTC 27 DB9 ADD1
DB10/DOUTD 28 DB10 ADD2
DB11/SDI 29 DB11 ADD3
DB12 to DB14 30 to 32 DB12 to DB14 ADD4 to ADD6
DB15 33 DB15
R/W
Table 22. Data Interface Pin Function per Mode of Operation (Serial Interface)
Pin Name Pin No. Hardware Mode
Software Mode
ADC Mode Register Mode
DB0 to DB6 16 to 22 N/A1 N/A
DB7/DOUTA 24 DOUTA DOUTA DOUTA
DB8/DOUTB 25 DOUTB DOUTB2 Unused
DB9/DOUTC 27 N/A DOUTC3 Unused
DB10/DOUTD 28 DOUTD3 Unused
DB11/SDI 29 Unused SDI
DB12 to DB14 30 to 32 N/A
DB15 33
1 N/A means not applicable. Tie all N/A pins to AGND.
2 Only used if 2SDO or 4SDO mode is selected on the CONFIG register, otherwise leave unconnected.
3 Only used if 4SDO mode is selected on the CONFIG register, otherwise leave unconnected.
Data Sheet AD7606B
Rev. 0 | Page 33 of 69
PARALLEL INTERFACE
To read ADC data or to read/write the register content over the
parallel interface, tie the PAR/SER SEL pin low.
DIGITAL
HOST
INTERRUPT
BUSY
14
13
12
10
DB[33:24]
DB[22:16]
CS
RD/SCLK
WR
DB[15:0]
AD7606B
15137-166
Figure 62. AD7606B Interface Diagram—One AD7606B Using the Parallel
Bus, with CS and RD Shorted Together
The rising edge of the CS input signal three-states the bus, and
the falling edge of the CS input signal takes the bus out of the
high impedance state. CS is the control signal that enables the
data lines and it is the function that allows multiple AD7606B
devices to share the same parallel data bus.
Reading Conversion Results (Parallel ADC Mode)
The falling edge of the RD pin reads data from the output
conversion results register. Applying a sequence of RD pulses to
the RD pin clocks the conversion results out from each channel
to the parallel bus, [DB15:DB0], in ascending order, from V1 to
V8, as shown in Figure 63.
The CS signal can be permanently tied low, and the RD signal
can access the conversion results, as shown in Figure 3. A read
operation of new data can take place after the BUSY signal goes
low (see Figure 2). Alternatively, a read operation of data from
the previous conversion process can take place while the
BUSY pin is high.
When there is only one AD7606B in a system and it does not
share the parallel bus, data can be read using one control signal
from the digital host. The CS and RD signals can be tied
together, as shown in Figure 4. In this case, the falling edge of
the CS and RD signals bring the data bus out of three-state and
clocks out the data.
The FRSTDATA output signal indicates when the first channel,
V1, is being read back, as shown in Figure 4. When the CS input
is high, the FRSTDATA output pin is in three-state. The falling
edge of CS takes the FRSTDATA pin out of three-state. The
falling edge of the RD signal corresponding to the result of V1 sets
the FRSTDATA pin high, indicating that the result from V1 is
available on the output data bus. The FRSTDATA pin returns to a
logic low following the next falling edge of RD.
Reading During Conversion
Data can be read from the AD7606B while the BUSY pin is high
and the conversions are in progress. This operation has little
effect on the performance of the converter, and it allows a faster
throughput rate to be achieved. Data can be read from the
AD7606B at any time other than on the falling edge of the
BUSY signal because this is when the output data registers are
updated with the new conversion data. Any data read while the
BUSY signal is high must be completed before the falling edge
of the BUSY signal.
Parallel ADC Mode with CRC Enabled
In software mode, the parallel interface supports reading the
ADC data with the CRC appended, when enabled through the
INT_CRC_ERR_EN bit (Address 0x21, Bit 2). The CRC is
16 bits, and it is clocked out after reading all eight channel
conversions, as shown in Figure 65. The CRC calculation includes
all data on the DBx pins: data, status (when appended), and zeros.
See the Diagnostics section for more details on the CRC.
Parallel ADC Mode with Status Enabled
In software mode, the 8-bit status header is enabled (see Table 24)
by setting Bit 6 in the CONFIG register (Address 0x02, Bit 6),
and each channel then takes two frames of data:
The first frame clocks the ADC data out normally through
DBx.
The second frame clocks out the status header of the
channel on DB15 to DB8, DB15 being the MSB and DB8
the LSB, while the DB7 to DB0 pins clock out zeros.
This sequence is shown in Figure 64. Table 24 explains the
status header content and describes each bit.
Table 23. CH.ID Bits Decoding in Status Header
CH.ID2 CH.ID1 CH.ID0 Channel Number
0 0 0 Channel 1 (V1)
0 0 1 Channel 2 (V2)
0 1 0 Channel 3 (V3)
0 1 1 Channel 4 (V4)
1 0 0 Channel 5 (V5)
1 0 1 Channel 6 (V6)
1 1 0 Channel 7 (V7)
1 1 1 Channel 8 (V8)
Table 24. Status Header, Parallel Interface
Bit Details Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)
Bit Name RESET_DETECT DIGITAL_ERROR OPEN_DETECTED AIN_OV_DIAG_ERR AIN_UV_DIAG_ERR CH.ID 2 CH.ID 1 CH.ID 0
Bit Description1 Reset detected Error flag on
Address 0x22
The analog input
of this channel is
open
Overvoltage
detected on this
channel
Undervoltage
detected on this
channel
Channel ID (see Table 23)
1 See the Diagnostics section for more information.
AD7606B Data Sheet
Rev. 0 | Page 34 of 69
V1 V2 V3 V4 V5 V6 V7 V8
CONVST
BUSY
DB0 TO DB15
FRSTDATA
CS
RD
15137-167
Figure 63. Parallel Interface, ADC Read Mode
V1[15:8] STATUS_CH1 V2[15:8] STATUS_CH2 V7[15:8] STATUS_CH7 V8[15:8]
V1[7:0] V2[7:0] V7[7:0] V8[7:0]
STATUS_CH8
CONVST
BUSY
DB0 TO
DB15
DB0 TO
DB7
CS
RD
15137-168
Figure 64. Parallel Interface, ADC Read Mode with Status Header Enabled
V1 V2 V3 V4 V5 V6 V7 V8
CONVST
BUSY
DB0 TO
DB15
CS
RD
CRC
15137-169
Figure 65. Parallel Interface, ADC Read Mode with CRC Enabled
Parallel Register Mode (Reading Register Data)
In software mode, all the registers in Table 31 can be read over
the parallel interface. [DB15:DB0] leave a high impedance state
when both the CS signal and RD signal are logic low for reading
register content, or when both the CS signal and WR signal are
logic low for writing register address and/or register content.
A register read is performed through two frames: first, a read
command is sent to the AD7606B and second, the AD7606B
clocks out the register content. The format for a register read
command is shown in Figure 66. On the first frame,
Bit DB15 must be set to 1 to select a read command. The
read command places the AD7606B in register mode.
Bits DB[14:8] must contain the register address.
The subsequent eight bits, DB[7:0], are ignored.
The register address is latched on the AD7606B on the rising
edge of the WR signal. The register content can then be read
from the latched register by bringing the RD line low on the
following frame, as follows:
Bit DB15 is pulled to 0 by the AD7606B.
Bits DB[14:8] provide the register address being read.
The subsequent eight bits, DB[7:0], provide the register
content.
To revert to ADC read mode, write to Address 0x00, as shown
in the Parallel Register Mode (Writing Register Data) section.
No ADC data can be read while the device is in register mode.
Parallel Register Mode (Writing Register Data)
In software mode, all the R/W registers in Table 31 can be written
to over the parallel interface. To write a sequence of registers,
exit ADC read mode (default mode) by reading any register on the
memory map. A register write command is performed by a single
frame, via the parallel bus (DB[15:0]), CS signal, and WR signal.
The format for a write command is shown in Figure 66. The
format of a write command, as shown in Figure 66, is structured as
follows:
Bit DB15 must be set to 0 to select a write command.
Bits DB[14:8] contain the register address.
The subsequent eight bits, DB[7:0], contain the data to be
written to the selected register.
Data is latched onto the device on the rising edge of the WR pin. To
revert to ADC read mode, write to Address 0x00. No ADC data
can be read while the device is in register mode.
Data Sheet AD7606B
Rev. 0 | Page 35 of 69
REG. ADDRESS
DON’ T CARE
REG. ADDRESS
REGISTER DATA
REG. ADDRESS
REGISTER DATA
ADDRESS = 0x00
R/W = 1 R/W = 0 R/W = 0 R/W = 0
DON’ T CARE
DB8 TO
DB14
DB15
DB0 TO
DB7
MODE
CS
RD
WR
ADC READ MO DE ADC READ MO DE
REGISTER MODE
15137-170
Figure 66. Parallel Interface Register Read Operation, Followed by a Write Operation
V1 V2 V3 V4 V5 V6 V7 V8
D
OUT
A
D
OUT
B
D
OUT
C
D
OUT
D
FRSTDATA
SCLK
CS
15137-171
Figure 67. Serial Interface ADC Reading, One DOUTx Line
SERIAL INTERFACE
To read ADC data or to read/write the registers content over the
serial interface, tie the PAR/SER SEL pin high.
DIGITAL
HOST
INTERRUPT
BUSY14
13
12
29
CS
RD/SCLK
DB11/SDI
DB7/DOUTA
DB8/DOUTB
DB9/DOUTC
DB10/DOUTD
AD7606B
24
25
27
28
15137-172
Figure 68. AD7606B Interface Diagram—One AD7606B Using the Serial
Interface with Four DOUTx Lines
Reading Conversion Results (Serial ADC Mode)
The AD7606B has four serial data output pins: DOUTA, DOUTB,
DOUTC, and DOUTD. In software mode, data can be read back
from the AD7606B using either one (see Figure 68), two (see
Figure 69), or four DOUTx lines (see Figure 70), depending on the
configuration set in the CONFIG register.
Table 25. DOUTx Format Selection, Using the CONFIG
Register (Address 0x02)
DOUTx Format Address 0x02, Bit 4 Address 0x02, Bit 3
1 DOUTx 0 0
2 DOUTx 0 1
4 DOUTx 1 0
1 DOUTx 1 1
In hardware mode, only the 2 DOUTx lines option is available.
However, all channels can be read from DOUTA by providing
eight 16-bit SPI frames between two CONVST pulses.
V1 V2 V3 V4
V5 V6 V7 V8
DOUTA
DOUTB
DOUTC
DOUTD
CNVST
SCLK
CS
15137-173
Figure 69. Serial Interface ADC Reading, Two DOUTx Lines
V1 V2
V3 V4
V5 V6
V7 V8
D
OUT
A
D
OUT
B
D
OUT
C
D
OUT
D
SCLK
CS
15137-174
Figure 70. Serial Interface ADC Reading, Four DOUTx Lines
The CS falling edge takes the data output lines, DOUTA to DOUTD,
out of three-state and clocks out the MSB of the conversion result.
In 3-wire mode (CS tied low), instead of CS clocking out the MSB,
the falling edge of the BUSY signal clocks out the MSB. The rising
edge of the SCLK signal clocks all the subsequent data bits on the
serial data outputs, DOUTA to DOUTD, as shown in Figure 6. The CS
input can be held low for the entire serial read operation, or it can
be pulsed to frame each channel read of 16 SCLK cycles (see
AD7606B Data Sheet
Rev. 0 | Page 36 of 69
Figure 69). However, if CS is pulsed during a channel
conversion result transmission, the channel that was interrupted
retransmits on the next frame, completely starting from the
MSB.
Data can also be clocked out using only the DOUTA pin, as
shown in Figure 67. For the AD7606B to access all eight
conversion results on one DOUTx line, a total of 128 SCLK cycles
is required. In hardware mode, these 128 SCLK cycles must be
framed on groups of 16 SCLK cycles by the CS signal. The
disadvantage of using just one DOUTx line is that the throughput
rate is reduced if reading occurs after conversion. Leave the
unused DOUTx lines unconnected in serial mode.
Figure 70 shows a read of eight simultaneous conversion results
using four DOUTx lines on the AD7606B, available in software
mode. In this case, a 32 SCLK transfer accesses data from the
AD7606B, and CS is either held low to frame the entire 32 SCLK
cycles or is pulsed between two 16-bit frames. This mode is only
available in software mode, and it is configured using the
CONFIG register (Address 0x02).
Figure 6 shows the timing diagram for reading one channel of
data, framed by the CS signal, from the AD7606B in serial
mode. The SCLK input signal provides the clock source for the
serial read operation. The CS signal goes low to access the data
from the AD7606B.
The FRSTDATA output signal indicates when the first channel,
V1, is being read back. When the CS input is high, the FRSTDATA
output pin is in three-state. In serial mode, the falling edge of the
CS signal takes the FRSTDATA pin out of three-state and sets
the FRSTDATA pin high if the BUSY line is already deasserted,
indicating that the result from V1 is available on the DOUTA
output data line. The FRSTDATA output returns to a logic low
following the 16th SCLK falling edge. If the CS pin is tied
permanently low (3-wire mode), the falling edge of the BUSY
line sets the FRSTDATA pin high when the result from V1 is
available on DOUTA.
If SDI is tied low or high, nothing is clocked to the AD7606B.
Therefore, the device remains clocking out conversion results.
When using the AD7606B in 3-wire mode, keep the SDI at a
high level. While in ADC read mode, single-write operations
can be performed, as shown in Figure 71. For writing a
sequence of registers, switch to register mode, as described in
the Serial Register Mode (Writing Register Data) section.
Reading During Conversion
Data can be read from the AD7606B while the BUSY signal is
high and the conversions are in progress. This operation has
little effect on the performance of the converter, and it allows a
faster throughput rate to be achieved. Data can be read from the
AD7606B at any time other than on the falling edge of the
BUSY signal because this is when the output data registers are
updated with the new conversion data. Any data read while the
BUSY signal is high must be completed before falling edge of
the BUSY signal.
Serial ADC Mode, with CRC Enabled
In software mode, the CRC can be enabled by writing to the
register map. In this case, the CRC is appended on each DOUTx
line after the last channel is clocked out as shown in Figure 78.
See the Interface CRC Checksum section for more information
on how the CRC is calculated.
Serial ADC Mode, with Status Enabled
In software mode, the 8-bit status header can be turned on
when using the serial interface, so that it is appended after each
16-bit data conversion, extending the frame size to 24 bits per
channel, as shown in Figure 71.
123456789
ADC DATA
D
OUT
x
SCLK
CS
STATUS HEADER
16 24
15137-175
Figure 71. Serial Interface, ADC Mode, Status On
REGISTER MODE ADC MODEADC MODE
ADC DATA
READ COMMAND R/W COMMAND R/W COMMAND WRITE COMMAND
ADDRESS
0x00
REGISTER
N + 1
REGISTER
N + 2
REGISTER
N
ADC DATAD
OUT
A
MODE
SDI
SCLK
CS
ADC DATA
ADC DATAADC DATA
D
OUT
BTO
D
OUT
DADC DATA
15137-176
REGISTER
N + 2
REGISTER
N + 1
REGISTER
N
Figure 72. AD7606B Register Mode
Data Sheet AD7606B
Rev. 0 | Page 37 of 69
Table 26. Status Header, Serial Interface
Bit Details Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (LSB)
Bit Name RESET_DETECT DIGITAL_ERROR OPEN_DETECTED AIN_OV_DIAG_ERR AIN_UV_DIAG_ERR CH.ID 2 CH.ID 1 CH.ID 0
Bit Description1 Reset detected Error flag on
Address 0x22
At least one analog
input is open
on a channel
Overvoltage
detected on a
channel
Undervoltage
detected on a
channel
Channel ID (see Table 23)
1 See the Diagnostics section for more information.
Serial Register Mode (Reading Register Data)
All the registers in Table 31 can be read over the serial interface.
The format for a read command is shown in Figure 73. It consists
of two 16-bit frames. On the first frame,
• The first bit in SDI must be set to 0 to enable writing the
address.
• The second bit must be set to 1 to select a read command.
• Bits[3:8] in SDI contain the register address to be clocked out
on DOUTA on the following frame.
• The subsequent eight bits, Bits[9:16], in SDI are ignored.
If the AD7606B is in ADC mode, the SDO keeps clocking ADC
data on Bits[9:16], and then the AD7606B switches to register
mode.
If the AD7606B is in register mode, the SDO reads back the
content from the previous addressed register, no matter if the
previous frame was a read or a write command. To exit register
mode, a write to Address 0x00 is required, as shown in Figure 72.
Serial Register Mode (Writing Register Data)
In software mode, all the read/write registers in Table 31 can be
written to over the serial interface. To write a sequence of
registers, exit ADC read mode (default mode) by reading any
register on the memory map. A register write command is
performed by a single 16-bit SPI access. The format for a write
command is shown in Figure 74.
The format for a write command, as shown in Figure 74, is
structured as follows:
• The first bit in SDI must be set to 0 to enable a write
command.
• The second bit, the R/W bit, must be cleared to 0.
• Bits[ADD5:ADD0] contain the register address to be
written.
• The subsequent eight bits (Bits[DIN7:DIN0]) contain the
data to be written to the selected register. Data is clocked in
from SDI on the falling edge of SCLK, while data is clocked
out on DOUTA on the rising edge of SCLK.
When writing continuously to the device, the data that appears
on DOUTA is from the register address that was written to on the
previous frame, as shown in Figure 74. The DOUTB, DOUTC, and
DOUTD pins are kept low during the transmission.
While in register mode, no ADC data is clocked out because the
DOUTx lines are used to clock out register content. When finished
writing all needed registers, a write to Address 0x00 returns the
AD7606B to ADC read mode, where the ADC data is again
clocked out on the DOUTx lines, as shown in Figure 72.
In software mode, when the CRC is turned on, eight additional
bits are clocked in and out on each frame. Therefore, 24-bit
frames are needed.
AD7606B Data Sheet
Rev. 0 | Page 38 of 69
816
1
ADD0
ADC DATA (8 L SB) O R PREV IO US
REGISTE R READ/W RITTEN
ADC DATA (8 L SB) O R XX
READ OR WRI TE COM MAND
REGISTE R [ ADD5 :ADD0] CO NT ENT
ADD1
ADD2ADD3
ADD4ADD5
R/WWEN
CS
SCLK
DOUTA
SDI
15137-073
Figure 73. Serial Interface Read Command; First Frame Points the Address; Second Frame Provides the Register Content
8 9 16
1
DIN0
1
DIN1
1
DIN2
1
DIN3
1
DIN4
1
DIN5
1
DIN6
1
DIN7
1
ADD0ADD1ADD2
ADD3ADD4
ADD5
WE N R/ W
DATA O UT
2
CS
SCLK
D
OUT
A
1
DATA I N DINx I S WRI TT E N INT O REGI S TER ADDRE S S [ ADD5: ADD0]
2
DATA OUT IS THE REGISTER CONTENT OF PREVIOUS REGISTER WRITTEN
SDI
15137-074
Figure 74. Serial Interface, Single-Write Command; SDI Clocks in the Address [ADD5:ADD0] and the Register Content [DINx] During the Same Frame, DOUTA Provides
Register Content Requested on the Previous Frame
8 9 16 241
ADD5 ADD0
MSB LSB 8-BI T CRC
ADD4 ADD3 ADD2 ADD1
WEN R/W
15137-179
CS
SCLK
D
OUT
A
SDI
Figure 75. Reading Registers Through the SPI Interface with CRC Enabled
8 9 16 241
ADD5 ADD0 MSB LSB 8-BI T CRCADD4 ADD3 ADD2 ADD1
WEN R/W
15137-180
CS
SCLK
SDI
Figure 76. Writing Registers Through the SPI Interface with CRC Enabled
Serial Register Mode with CRC
Registers can be written to and read from the AD7606B with
CRC enabled, in software mode, by asserting the INT_CRC_
ERR_EN bit (Address 0x21, Bit 2).
When reading a register, the AD7606B provides eight additional
bits on the DOUTA pin with the CRC resultant of the data shifted
out previously on the same frame. The controller can then
check whether the data received is correct by applying the
following polynomial:
x8 + x2 + x + 1
With the CRC enabled, the SPI frames extend to 24 bits in
length, as shown in Figure 75.
When writing a register, the controller must clock the data
(register address plus register content) in the AD7606B followed by
an 8-bit CRC word, calculated from the previous 16 bits using
the previously described polynomial. The AD7606B reads the
register address and the register content, calculates the
corresponding 8-bit CRC word, and asserts the INT_CRC_ERR bit
(Address 0x22, Bit 2) if the calculated CRC word does not match
the CRC word received between the 17th and 24th bit through
SDI, as shown in Figure 76.
Data Sheet AD7606B
Rev. 0 | Page 39 of 69
DIAGNOSTICS
Diagnostic features are available in software mode to verify
correct operation of the AD7606B. The list of diagnostic
monitors includes reset detection, overvoltage detection,
undervoltage detection, analog input open circuit detection,
and digital error detection.
If an error is detected, a flag asserts on the status header, if
enabled, as described in the Digital Interface section. This flag
points to the registers on which the error is located, as explained
in the following sections.
In addition, a diagnostic multiplexer can dedicate any channel
to verify a series of internal nodes, as explained in the
Diagnostics Multiplexer section.
RESET DETECTION
The RESET_DETECT bit on the status register (Address 0x01,
Bit 7) asserts if either a partial reset or full reset pulse is applied
to the AD7606B. On power-up, a full reset is required. This
reset asserts the RESET_DETECT bit, indicating that the
power-on reset (POR) initialized correctly on the device.
The POR monitors the REGCAP voltage and issues a full reset
if the voltage drops under a certain threshold.
The RESET_DETECT bit can be used to detect an unexpected
device reset or a large glitch on the RESET pin, or a voltage
drop on the supplies.
The RESET_DETECT bit is only cleared by reading the status
register.
OVERVOLTAGE AND UNDERVOLTAGE EVENTS
The AD7606B includes on-chip overvoltage and undervoltage
circuitry on each analog input pin. These comparators can be
enabled or disabled using the AIN_OV_UV_DIAG_
ENABLE register (Address 0x25).
After this register is enabled, when the voltage on any analog
input pin goes above the overvoltage threshold shown in Table 27,
the AIN_OV_DIAG_ERROR register (Address 0x26) shows
which channel or channels have an overvoltage event. When a
bit within the AIN_OV_DIAG_ERROR register asserts, it stays
at a high state even after the overvoltage event disappears. To
clear the error bit, the error bit must be overwritten to 1 or the
error checker must be disabled.
Vx
OVERVOLTAGE
THRESHOLD
UNDERVOLTAGE
THRESHOLD
CHx_OV_ERR
SETS IF Vx > OV
AD7606B
CHx_UV_ERR
SETS IF Vx < UV
15137-075
Figure 77. Overvoltage and Undervoltage Circuitry on Each Analog Input
When the voltage on any analog input pin goes below the
undervoltage threshold shown in Table 27, the AIN_UV_
DIAG_ERROR register (Address 0x27) shows which channel or
channels have an undervoltage event. When a bit within the
AIN_UV_DIAG_ERROR register asserts, it stays at high state
after the undervoltage event disappears. To clear the error bit, the
error bit must be overwritten to 1 or the error checker must be
disabled.
Table 27. Overvoltage and Undervoltage Thresholds
Analog Input
Range (V)
Overvoltage
Threshold (V)
Undervoltage
Threshold (V)
±2.5 +6.5 −3
±5 +8 −5.5
±10 +12 −11
DIGITAL ERROR
Both the status register and status header contain a
DIGITAL_ERROR bit. This bit asserts when any of the
following monitors trigger:
• Memory map CRC, read only memory (ROM) CRC, and
digital interface CRC.
• SPI invalid read or write.
• BUSY stuck high.
To find out which monitor triggered the DIGITAL_ERROR bit,
the DIGITAL_DIAG_ERR address (Address 0x22) has a bit
dedicated for each monitor, as explained in the following sections.
ROM CRC
The ROM stores the factory trimming settings for the
AD7606B. After power-up, the ROM content is loaded to
registers during device initialization. After the load, a CRC is
calculated on the loaded data and verified if the result matches
the CRC stored in the ROM. If an error is found, the ROM_
CRC_ERR (Address 0x22, Bit 0) asserts. When ROM_CRC_
ERR asserts after power-up, it is recommended to issue a full
reset to reload all factory settings.
This ROM CRC monitoring feature is enabled by default, but
can be disabled by clearing the ROM_CRC_ERR_EN bit
(Address 0x21, Bit 0).
Memory Map CRC
The memory map CRC is disabled by default. After the
AD7606B is configured in software mode through writing the
required registers, the memory map CRC can be enabled
through the MM_CRC_ERR_EN bit (Address 0x21, Bit 1).
When enabled, the CRC calculation is performed on the entire
memory map and stored. Every 4 μs, the CRC on the memory
map is recalculated and compared to the stored CRC value. If
the calculated and the stored CRC values do not match, the
memory map is corrupted and the MM_CRC_ERR bit asserts.
Every time the memory map is written, the CRC is recalculated
and the new value stored.
AD7606B Data Sheet
Rev. 0 | Page 40 of 69
If the MM_CRC_ERR bit asserts, it is recommended to write to
the memory map to recalculate the CRC. If the error persists, it
is recommended to issue a full reset to restore the default
contents of the memory map.
Interface CRC Checksum
The AD7606B has a CRC checksum mode to improve interface
robustness by detecting errors in data transmission. The CRC
feature is available in both ADC modes (serial and parallel) and
register mode (serial only).
The AD7606B uses the following 8-bit CRC polynomial to
calculate the CRC checksum value:
x16 + x14 + x13 + x12 + x10 + x8 +x6 + x4 + x3 + x + 1
To replicate the polynomial division in hardware, the data shifts
left by 16 bits to create a number ending in 16 Logic 0s. The
polynomial is aligned so that the MSB is adjacent to the
leftmost Logic 1 of the data. An exclusive OR (XOR) function is
applied to the data to produce a new, shorter number. The
polynomial is again aligned so that the MSB is adjacent to the
leftmost Logic 1 of the new result, and the procedure repeats.
This process repeats until the original data is reduced to a value
less than the polynomial, the 16-bit checksum.
An example of the CRC calculation for the 16-bit data is shown
in Table 28. The CRC corresponding to the data 0x064E, using
the previously described polynomial, is 0x2137.
The serial interface supports the CRC when enabled via the
INT_CRC_ERR_EN bit (Address 0x21, Bit 2). The CRC is a 16-
bit word that is appended to the end of each DOUTx in use, after
reading all the channels. An example using four DOUTx lines is
shown in Figure 78.
V1 V2 CRC(V1,V2)
V3 V4 CRC(V3,V4)
V5 V6 CRC(V5,V6)
V7 V8 CRC(V7,V8)
CS
CNVST
SCLK
DOUTA
DOUTB
DOUTC
DOUTD
15137-076
Figure 78. Serial Interface ADC Reading with CRC On, Four DOUTx Lines
If using two DOUTx lines (DOUTA and DOUTB), each 16-bit CRC
word is calculated using data from four channels, that is 64 bits,
as shown in Figure 79. If using only one DOUTx line, all eight
channels are clocked out through DOUTA, followed by the 16-bit
CRC word calculated using data from the eight channels, that is,
128 bits.
V1 V2
V5 V6
V3
V7
V4
V8
CRC(V1,V4)
CRC(V5,V8)
CS
CNVST
SCLK
D
OUT
A
D
OUT
B
D
OUT
C
D
OUT
D
15137-077
Figure 79. Serial Interface ADC Reading with CRC On, Two DOUTx Lines
Data Sheet AD7606B
Rev. 0 | Page 41 of 69
When the AD7606B is in register mode, that is, when registers
are being read or written, the CRC polynomial used is x8 + x2 +
x + 1. When reading a register, and CRC is enabled, each SPI
frame is 24 bits long and the CRC 8-bit word is clocked out
from the 17th to 24th SCLK cycle. Similarly, when writing a
register, a CRC word can be appended on the SDI line, as shown
in Figure 80 and the AD7606B checks and triggers an error,
INT_CRC_ERR (Address 0x22, Bit 2), if the CRC given and the
internally calculated do not match.
The parallel interface also supports CRC in ADC mode only,
and it is clocked out through DB15 to DB0 after Channel 8, as
shown in Figure 65. The 16-bit CRC word calculated using data
from the eight channels, that is, 128 bits.
2417154321 16
CRC0
CRC7
DB0DB1DB12DB13DB14DB15
CS
SCLK
D
OUT
A TO D
OUT
D
SDI CRC0
CRC7
DIN0DIN1ADD4ADD5R/WWEN
15137-078
Figure 80. Register Write with CRC On
AD7606B Data Sheet
Rev. 0 | Page 42 of 69
Table 28. Example CRC Calculation for 16-Bit Data1
Data2 0 0 0 0 0 1 1 0 0 1 0 0 1 1 1 0 x x x x x x x x x x x x x x x x
Process
Data
0 0 0 0 0 1 1 0 0 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Polynomial 1 0 1 1 1 0 1 0 1 0 1 0 1 1 0 1 1
0 1 1 1 0 0 1 1 0 1 1 0 1 1 0 1 1 0
1 0 1 1 1 0 1 0 1 0 1 0 1 1 0 1 1
0 1 0 1 1 1 0 0 0 1 1 1 0 1 1 0 1 0
1 0 1 1 1 0 1 0 1 0 1 0 1 1 0 1 1
0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0
1 0 1 1 1 0 1 0 1 0 1 0 1 1 0 1 1
0 0 1 0 1 0 1 0 1 0 0 0 1 1 0 1 1 0 0
1 0 1 1 1 0 1 0 1 0 1 0 1 1 0 1 1
CRC 0 0 1 0 0 0 0 1 0 0 1 1 0 1 1 1
1 This table represents the division of the data. Blank cells are for formatting purposes.
2 X = don’t care.
Interface Check
The integrity of the digital interface can be checked by setting
the INTERFACE_CHECK_EN bit (Address 0x21, Bit 7).
Selecting the interface check forces the conversion result
registers to a known value, as shown in Table 29.
Verifying that the controller receives the data shown in Table 29
ensures that the interface between the AD7606B and the
controller operates properly. If the interface CRC is enabled
because the data transmitted is known, this mode verifies that
the controller performs the CRC calculation properly.
Table 29. Interface Check Conversion Results
Channel Number Conversion Result Forced (Hex.)
V1 0xACCA
V2 0x5CC5
V3 0xA33A
V4 0x5335
V5 0xCAAC
V6 0xC55C
V7 0x3AA3
V8 0x3553
SPI Invalid Read/Write
When attempting to read back an invalid register address, the
SPI_READ_ERR bit (Address 0x22, Bit 4) is set. The invalid
readback address detection can be enabled by setting the
SPI_READ_ERR_EN bit (Address 0x21, Bit 4). If an SPI read
error is triggered, it is cleared by overwriting that bit or disabling
the checker.
When attempting to write to an invalid register address or a
read only register, the SPI_WRITE_ERR bit (Address 0x22, Bit 3) is
set. The invalid write address detection can be enabled by
setting the SPI_WRITE _ERR bit (Address 0x21, Bit 3). If an SPI
write error is triggered, it is cleared by overwriting that bit or
disabling the checker.
BUSY Stuck High
BUSY stuck high monitoring is enabled by setting the
BUSY_STUCK_HIGH_ERR_EN bit (Address 0x21, Bit 5).
After this bit is enabled, the conversion time (tCONV in Table 3) is
monitored internally with an independent clock. If tCONV exceeds
4 μs, the AD7606B automatically issues a partial reset and asserts
the BUSY_STUCK_HIGH_ERR bit (Address 0x22, Bit 5). To
clear this error flag, the BUSY_STUCK_HIGH_ERR bit must be
overwritten with a 1.
When oversampling mode is enabled, the individual conversion
time for each internal conversion is monitored.
DIAGNOSTICS MULTIPLEXER
All eight input channels contain a diagnostics multiplexer in
front of the PGA that allows monitoring of the internal nodes
described in Table 30 to ensure the correct operation of the
AD7606B. Table 30 shows the bit decoding for the diagnostic mux
register on Channel 1, as an example. When an internal node is
selected, the input voltage at input pins are deselected from the
PGA, as shown in Figure 81.
Each diagnostic multiplexer configuration is accessed, in
software mode through the corresponding register (Address 0x28
to Address 0x2B). To use the multiplexer on one channel, the
±10 V range must be selected on that channel.
Table 30. Diagnostic Mux Register Bit Decoding of Channel 1
Address 0x18
Bit 2 Bit 1 Bit 0 Signal on Channel 1
0 0 0 V1
0 0 1 Temperature sensor
0 1 0 VREF
0 1 1 4 × ALDO
1 0 0 4 × DLDO
1 0 1 VDRIVE
1 1 0 AGND
1 1 1 AVCC
Data Sheet AD7606B
Rev. 0 | Page 43 of 69
AV
CC
AGND
V
DRIVE
4×DLDO
4×ALDO
V
REF
TEMPERATURE
SENSOR
V1
V1GND
MUX
5MΩ
5MΩ R
FB
R
FB
AD7606B
15137-079
Figure 81. Diagnostic Multiplexer (Channel 1 Shown as an Example)
Temperature Sensor
The temperature sensor can be selected through the diagnostic
multiplexer and converted with the ADC, as shown in Figure 81.
The temperature sensor voltage is measured and is proportional to
the die temperature, as per the following equation:
( ) ( ) ( )
( ) ( )
0.69068 25
0.019328 /
°−
= °
°+
OUT
CC
ADC V V
TV C
emperature
with an accuracy of ±2°C.
Reference Voltage
The reference voltage can be selected through the diagnostic
multiplexer and converted with the ADC, as shown in Figure 82.
The internal or external reference is selected as input to the
diagnostic multiplexer based on REF SELECT pin. Ideally, the
ADC output follows the voltage reference level ratio metrically.
Therefore, if the ADC output goes beyond the expected 2.5 V,
either the reference buffer or the PGA is malfunctioning.
2.5V
INT RE F
AD7606B
4.4V
EXT REF
Vx
VxGND
MUX
ADC
R
FB
R
FB
5MΩ
5MΩ
15137-080
R
FB
Figure 82. Reference Voltage Signal Path Through the Diagnostic Multiplexer
Internal LDOs
The analog and digital LDO (REGCAP pins) can be selected
through the diagnostic multiplexer and converted with the
ADC, as shown in Figure 81. The ADC output is four times the
voltage on the REGCAPA and REGCAPD pins, respectively.
This measurement verifies that each LDO is at the correct
operating voltage so that the internal circuitry is biased correctly.
Supply Voltages
AVCC, VDRIVE, and AGND can be selected through the diagnostic
multiplexer and converted with the ADC, as shown in Figure 81.
This setup ensures the voltage and grounds are correctly applied to
the device to ensure correct operation.
AD7606B Data Sheet
Rev. 0 | Page 44 of 69
TYPICAL CONNECTION DIAGRAM
There are four AVCC supply pins on the device. It is recommended
that each of the four pins are decoupled using a 100 nF capacitor at
each supply pin and a 10 µF capacitor at the supply source. The
AD7606B can operate with the internal reference or an externally
applied reference. When using a single AD7606B device on the
board, decouple the REFIN/REFOUT pin with a 100 nF capacitor.
Refer to the Reference section when using an application with
multiple AD7606B devices. The REFCAPA and REFCAPB pins
are shorted together and decoupled with a 10 µF ceramic capacitor.
The VDRIVE supply is connected to the same supply as the
processor. The VDRIVE voltage controls the voltage value of the
output logic signals. For more information on layout, decoupling,
and grounding, see the Layout Guidelines section.
After supplies are applied to the AD7606B, apply a reset to the
AD7606B to ensure that it is configured for the correct mode of
operation.
In Figure 83, the AD7606B is configured in hardware mode and is
operating with the internal reference because the REF SELECT pin
is set to logic high. In this example, the device also uses the
parallel interface because the PAR/SER pin is tied to AGND.
The analog input range for all eight channels is ±10 V, provided
the RANGE pin is tied to a high level and the oversampling
ratio is controlled through the OS pins by the controller.
In Figure 84, the AD7606B is configured in software mode,
because all three OS2, OS1, and OS0 pins are at logic level high.
The oversampling ratio, as well as each channel range, are
configured through accessing the memory map. In this example,
the PAR/SER pin is at logic level high. Therefore, the serial
interface is used for both reading the ADC data and reading
and writing the memory map. The REF SELECT pin is tied to
AGND. Therefore, the internal reference is disabled and an
external reference is connected externally to the REFIN/REFOUT
pin and decoupled through a 100 nF capacitor.
Figure 83 and Figure 84 are examples of typical connection
diagrams. Other combinations of reference, data interface, and
operation mode are also possible, depending on the logic levels
applied to each configuration pin.
V8GND
1DECOUP LI NG SHOW N ON T HE AVCC PI N AP P LI E S TO E ACH AVCC P IN (P IN 1, P I N 37, PIN 38, P IN 48).
DECOUP LI NG CAPACIT OR CAN BE S HARE D BE TW E E N AVCC P IN 37 AND PIN 38.
2DECOUP LI NG SHOW N ON T HE RE GCAP P IN APP LI E S TO E ACH RE GCAP P IN (P IN 36, P IN 39).
V8
V7GND
V7
V6GND
V6
V5GND
V5
V4GND
V4
V3GND
EIGHT ANALOG
INPUTS V1 TO V8
V3
V2GND
V2
V1GND
V1
REFGND
10µF
DB0 TO DB15 PARALLEL
INTERFACE
OVERSAMPLING
MICROPROCESSOR/
MICROCONVERTER/
DSP
STBY
RANGE
AGND
PAR/SER SEL
REF SELECT VDRIVE
VDRIVE
OS0
OS1
OS2
RESET
BUSY
RD
CS
CONVST
REFCAPB
REFCAPA
REFIN/REFOUT REGCAP2AVCC VDRIVE
+
100nF +1µF 100nF
ANALOG S UP P LY
VOLTAGE 5V1DIGITAL SUPPLY
VOLTAGE +1.71V TO +3.6V
100nF
AD7606B
15137-081
Figure 83. AD7606B Typical Connection Diagram, Hardware Mode
Data Sheet AD7606B
Rev. 0 | Page 45 of 69
V8GND
1
DECOUP LI NG SHOW N ON T HE AV
CC
PIN APPLIES TO EACHAV
CC
PIN (PI N 1, PIN 37, P IN 38, P IN 48).
DECOUP LI NG CAPACIT OR CAN BE S HARE D BE TW E E N AV
CC
PIN 37 AND P IN 38.
2
DECOUP LI NG SHOW N ON T HE RE GCAP P IN APP LI E S TO E ACH RE GCAP P IN (P IN 36, P IN 39).
V8
V7GND
V7
V6GND
V6
V5GND
V5
V4GND
V4
V3GND
EIGHT ANALOG
INPUTS V1 TO V8
V3
V2GND
V2
V1GND
V1
REFGND
10µF
DB0 TO DB15
OVERSAMPLING =
111b
MICROPROCESSOR/
MICROCONVERTER/
DSP
STBY
RANGE
AGND
PAR/SER SEL
REF SELECT
V
DRIVE
OS0
OS1
OS2
RESET
D
OUT
x
SDI
CS
CONVST
REFCAPB
REFCAPA
REF
+
100nF +1µF
SCLK
100nF
ANALOG S UP P LY
VOLTAGE 5V
1
DIGITAL SUPPLY
VOLTAGE +1.71V TO +3.6V
100nF
AD7606B
15137-082
REFIN/REFOUT REGCAP
2
AV
CC
V
DRIVE
Figure 84. Typical Connection Diagram, Software Mode
AD7606B Data Sheet
Rev. 0 | Page 46 of 69
APPLICATIONS INFORMATION
LAYOUT GUIDELINES
The following layout guidelines are recommended to be
followed when designing the PCB that houses the AD7606B:
• The analog and digital sections are separated and confined
to different areas of the board.
• Use at least one ground plane. This plane can be common
or split between the digital and analog sections. In the case
of a split plane, join the digital and analog ground planes in
only one place, preferably as close as possible to the
AD7606B.
• If the AD7606B is in a system where multiple devices
require analog-to-digital ground connections, make the
connection at only one point: a star ground point that is
established as close as possible to the AD7606B.
• Make stable connections to the ground plane. Avoid
sharing one connection for multiple ground pins. Use
individual vias or multiple vias to the ground plane for
each ground pin.
• Avoid running digital lines under the device because doing
so couples noise on the die. Allow the analog ground plane
to run under the AD7606B to avoid noise coupling.
• Shield fast switching signals like CONVST, or clocks with
digital ground to avoid radiating noise to other sections of
the board and ensure that they never run near analog
signal paths.
• Avoid crossover of digital and analog signals.
• Traces on layers in close proximity on the board run at
right angles to each other to reduce the effect of
feedthrough through the board.
• Power supply lines to t he AVCC and VDRIVE pins on the
AD7606B use as large a trace as possible to provide low
impedance paths and reduce the effect of glitches on the
power supply lines. Where possible, use supply planes and
make stable connections between the AD7606B supply
pins and the power tracks on the board. Use a single via or
multiple vias for each supply pin.
• Place the decoupling capacitors close to (ideally, directly
against) the supply pins and their corresponding ground
pins. Place the decoupling capacitors for the REFIN/
REFOUT pin and the REFCAPA pin and REFCAPB pin as
close as possible to their respective AD7606B pins. Where
possible, place the pins on the same side of the board as the
AD7606B device.
Figure 85 shows the recommended decoupling on the top layer
of the AD7606B board. Figure 86 shows bottom layer decoupling,
which is used for the four AVCC pins and the VDRIVE pin decoupling.
Where the ceramic 100 nF caps for the AVCC pins are placed
close to their respective device pins, a single 100 nF capacitor
can be shared between Pin 37 and Pin 38.
15137-083
Figure 85. Top Layer Decoupling REFIN/REFOUT,
REFCAPA, REFCAPB, and REGCAP Pins
15137-084
Figure 86. Bottom Layer Decoupling
Data Sheet AD7606B
Rev. 0 | Page 47 of 69
To ensure stable device to device performance matching in a
system that contains multiple AD7606B devices, a symmetrical
layout between the AD7606B devices is important.
Figure 87 shows a layout with two AD7606B devices. The AVCC
supply plane runs to the right of both devices, and the VDRIVE
supply track runs to the left of the two devices. The reference
chip is positioned between the two devices, and the reference
voltage track runs north to Pin 42 of U1 and south to Pin 42 of
U2. A solid ground plane is used.
These symmetrical layout principles can also be applied to a
system that contains more than two AD7606B devices. The
AD7606B devices can be placed in a north/south direction, with
the reference voltage located midway between the devices and
the reference track running in the north/south direction,
similar to Figure 87.
AVCC
U2
U1
AVCC
U2
U1
15137-085
Figure 87. Layout for Multiple AD7606B Devices—Top Layer and
Supply Plane Layer
AD7606B Data Sheet
Rev. 0 | Page 48 of 69
REGISTER SUMMARY
Table 31. Register Summary
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW
0x01 STATUS RESET_
DETECT
DIGITAL_
ERROR
RESERVED 0x00 R
0x02 CONFIG RESERVED STATUS_
HEADER
EXT_OS_CLOCK DOUT_FORMAT RESERVED OPERATION_MODE 0x08 R/W
0x03 RANGE_CH1_
CH2
CH2_RANGE CH1_RANGE 0x33 R/W
0x04 RANGE_CH3_
CH4
CH4_RANGE CH3_RANGE 0x33 R/W
0x05 RANGE_CH5_
CH6
CH6_RANGE CH5_RANGE 0x33 R/W
0x06 RANGE_CH7_
CH8
CH8_RANGE CH7_RANGE 0x33 R/W
0x08 OVERSAMPLING OS_PAD OS_RATIO 0x00 R/W
0x09 CH1_GAIN RESERVED CH1_GAIN 0x00 R/W
0x0A CH2_GAIN RESERVED CH2_GAIN 0x00 R/W
0x0B CH3_GAIN RESERVED CH3_GAIN 0x00 R/W
0x0C CH4_GAIN RESERVED CH4_GAIN 0x00 R/W
0x0D CH5_GAIN RESERVED CH5_GAIN 0x00 R/W
0x0E CH6_GAIN RESERVED CH6_GAIN 0x00 R/W
0x0F CH7_GAIN RESERVED CH7_GAIN 0x00 R/W
0x10 CH8_GAIN RESERVED CH8_GAIN 0x00 R/W
0x11 CH1_OFFSET CH1_OFFSET 0x80 R/W
0x12 CH2_OFFSET CH2_OFFSET 0x80 R/W
0x13 CH3_OFFSET CH3_OFFSET 0x80 R/W
0x14 CH4_OFFSET CH4_OFFSET 0x80 R/W
0x15 CH5_OFFSET CH5_OFFSET 0x80 R/W
0x16 CH6_OFFSET CH6_OFFSET 0x80 R/W
0x17 CH7_OFFSET CH7_OFFSET 0x80 R/W
0x18 CH8_OFFSET CH8_OFFSET 0x80 R/W
0x19 CH1_PHASE CH1_PHASE_OFFSET 0x00 R/W
0x1A CH2_PHASE CH2_PHASE_OFFSET 0x00 R/W
0x1B CH3_PHASE CH3_PHASE_OFFSET 0x00 R/W
0x1C CH4_PHASE CH4_PHASE_OFFSET 0x00 R/W
0x1D CH5_PHASE CH5_PHASE_OFFSET 0x00 R/W
0x1E CH6_PHASE CH6_PHASE_OFFSET 0x00 R/W
0x1F CH7_PHASE CH7_PHASE_OFFSET 0x00 R/W
0x20 CH8_PHASE CH8_PHASE_OFFSET 0x00 R/W
0x21 DIGITAL_
DIAG_ENABLE
INTERFACE_
CHECK_EN
CLK_FS_OS_
COUNTER_EN
BUSY_STUCK_
HIGH_ERR_EN
SPI_READ_
ERR_EN
SPI_WRITE_
ERR_EN
INT_CRC_
ERR_EN
MM_CRC_
ERR_EN
ROM_
CRC_
ERR_EN
0x01 R/W
0x22 DIGITAL_
DIAG_ERR
RESERVED BUSY_STUCK_
HIGH_ERR
SPI_READ_
ERR
SPI_WRITE_
ERR
INT_CRC_ERR MM_CRC_
ERR
ROM_
CRC_
ERR
0x00 R/W
0x23 OPEN_
DETECT_
ENABLE
CH8_OPEN_
DETECT_EN
CH7_OPEN_
DETECT_EN
CH6_OPEN_
DETECT_EN
CH5_OPEN_
DETECT_EN
CH4_OPEN_
DETECT_EN
CH3_OPEN_
DETECT_EN
CH2_OPEN_
DETECT_EN
CH1_
OPEN_
DETECT_
EN
0x00 R/W
0x24 OPEN_
DETECTED
CH8_OPEN CH7_OPEN CH6_OPEN CH5_OPEN CH4_OPEN CH3_OPEN CH2_OPEN CH1_
OPEN
0x00 R/W
0x25 AIN_OV_UV_
DIAG_ENABLE
CH8_OV_
UV_EN
CH7_OV_UV_EN CH6_OV_UV_EN CH5_OV_
UV_EN
CH4_OV_
UV_EN
CH3_OV_
UV_EN
CH2_OV_
UV_EN
CH1_
OV_UV_
EN
0x00 R/W
0x26 AIN_OV_DIAG_
ERROR
CH8_OV_ERR CH7_OV_ERR CH6_OV_ERR CH5_OV_ERR CH4_OV_ERR CH3_OV_ERR CH2_OV_ERR CH1_
OV_ERR
0x00 R/W
0x27 AIN_UV_DIAG_
ERROR
CH8_UV_ERR CH7_UV_ERR CH6_UV_ERR CH5_UV_ERR CH4_UV_ERR CH3_UV_ERR CH2_UV_ERR CH1_
UV_ERR
0x00 R/W
0x28 DIAGNOSTIC_
MUX_CH1_2
RESERVED CH2_DIAG_MUX_CTRL CH1_DIAG_MUX_CTRL 0x00 R/W
0x29 DIAGNOSTIC_
MUX_CH3_4
RESERVED CH4_DIAG_MUX_CTRL CH3_DIAG_MUX_CTRL 0x00 R/W
Data Sheet AD7606B
Rev. 0 | Page 49 of 69
Addr Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW
0x2A DIAGNOSTIC_
MUX_CH5_6
RESERVED CH6_DIAG_MUX_CTRL CH5_DIAG_MUX_CTRL 0x00 R/W
0x2B DIAGNOSTIC_
MUX_CH7_8
RESERVED CH8_DIAG_MUX_CTRL CH7_DIAG_MUX_CTRL 0x00 R/W
0x2C OPEN_
DETECT_
QUEUE
OPEN_DETECT_QUEUE 0x00 R/W
0x2D FS_CLK_
COUNTER
CLK_FS_COUNTER 0x00 R
0x2E OS_CLK_
COUNTER
CLK_OS_COUNTER 0x00 R
0x2F ID DEVICE_ID SILICON_REVISION 0x14 R
AD7606B Data Sheet
Rev. 0 | Page 50 of 69
REGISTER DETAILS
Address: 0x01, Reset: 0x00, Name: STATUS
A reset has been det ec ted, either
full or partial r eset
Error present in DIGIT AL_DI AG _E RROR
register
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7] RESET_DETECT (R) [5:0] RESERVED
[6] DIG ITAL_ERROR (R)
Table 32. Bit Descriptions for STATUS
Bits Bit Name Description Reset Access
7 RESET_DETECT A reset has been detected, either full or partial reset. 0x0 R
6 DIGITAL_ERROR Error present in DIGITAL_DIAG_ERROR register. 0x0 R
[5:0] RESERVED Reserved. 0x0 R
Address: 0x02, Reset: 0x08, Name: CONFIG
O peration mode
11: shut down mode.
10: autost andby mode.
01: st andby mode.
00: normal mode.
Enable ST AT US header to be appended
to ADC dat a i n both serial and parallel
interface
In oversampling mode, enable ext ernal
oversampling clock. Over sampling
conversions are trigger ed through
a cl oc k signal applied to CONVST
pin, instead of managed by t he i nternal
oversampling clock
Number of DOUT lines used in seri al
mode when readi ng conversions
11: x.
OUT
D1
10: x.
OUT
D4
01: x.
OUT
D2
00: x.
OUT
D1
0
0
1
0
2
0
3
1
4
0
5
0
6
0
7
0
[7] RESERVED [1: 0] OPERATION_MODE (R/W)
[6] STATUS_HEADE R (R/W)
[2] RESERVED
[5] EXT_OS_CLOCK (R/W)
[4: 3] DOUT_F ORMAT (R/W)
Table 33. Bit Descriptions for CONFIG
Bits Bit Name Description Reset Access
7 RESERVED Reserved. 0x0 R
6 STATUS_HEADER Enable STATUS header to be appended to ADC data in both serial and parallel interface. 0x0 R/W
5 EXT_OS_CLOCK In oversampling mode, enable external oversampling clock. Oversampling conversions are
triggered through a clock signal applied to CONVST pin, instead of managed by the
internal oversampling clock.
0x0 R/W
[4:3] DOUT_FORMAT Number of DOUTx lines used in serial mode when reading conversions. 0x1 R/W
00: 1 DOUTx.
01: 2 DOUTx.
10: 4 DOUTx.
11: 1 DOUTx.
2 RESERVED Reserved. 0x0 R
[1:0] OPERATION_MODE Operation mode. 0x0 R/W
00: normal mode.
01: standby mode.
10: autostandby mode.
11: shutdown mode.
Data Sheet AD7606B
Rev. 0 | Page 51 of 69
Address: 0x03, Reset: 0x33, Name: RANGE_CH1_CH2
Range options f or Channel 2
1111: reserved.
1110: reserved.
1101: reserved.
...
0010: ±10V single-ended range.
0001: ±5V single-ended range.
0000: ±2.5V single-ended range. Range options f or Channel 1
1111: reserved.
1110: reserved.
1101: reserved.
...
0010: ±10V single-ended range.
0001: ±5V single-ended range.
0000: ±2.5V single-ended range.
0
1
1
1
2
0
3
0
4
1
5
1
6
0
7
0
[7: 4] CH2_RANGE (R/W) [3: 0] CH1_RANGE (R/W)
Table 34. Bit Descriptions for RANGE_CH1_CH2
Bits Bit Name Description Reset Access
[7:4] CH2_RANGE Range options for Channel 2. 0x3 R/W
0000: ±2.5 V single-ended range.
0001: ±5 V single-ended range.
0010: ±10 V single-ended range.
0011: ±10 V single-ended range.
0100: ±10 V single-ended range.
0101: ±10 V single-ended range.
0110: ±10 V single-ended range.
0111: ±10 V single-ended range.
1000: ±10 V single-ended range.
1001: ±10 V single-ended range.
1010: ±10 V single-ended range.
1011: ±10 V single-ended range.
1100: reserved.
1101: reserved.
1110: reserved.
1111: reserved.
[3:0] CH1_RANGE Range options for Channel 1. 0x3 R/W
0000: ±2.5 V single-ended range.
0001: ±5 V single-ended range.
0010: ±10 V single-ended range.
0011: ±10 V single-ended range.
0100: ±10 V single-ended range.
0101: ±10 V single-ended range.
0110: ±10 V single-ended range.
0111: ±10 V single-ended range.
1000: ±10 V single-ended range.
1001: ±10 V single-ended range.
1010: ±10 V single-ended range.
1011: ±10 V single-ended range.
1100: reserved.
1101: reserved.
1110: reserved.
1111: reserved.
AD7606B Data Sheet
Rev. 0 | Page 52 of 69
Address: 0x04, Reset: 0x33, Name: RANGE_CH3_CH4
Range options f or Channel 4
1111: reserved.
1110: reserved.
1101: reserved.
...
0010: ±10V single-ended range.
0001: ±5V single-ended range.
0000: ±2.5V single-ended range. Range options f or Channel 3
1111: reserved.
1110: reserved.
1101: reserved.
...
0010: ±10V single-ended range.
0001: ±5V single-ended range.
0000: ±2.5V single-ended range.
0
1
1
1
2
0
3
0
4
1
5
1
6
0
7
0
[7: 4] CH4_RANGE (R/W) [3: 0] CH3_RANGE (R/W)
Table 35. Bit Descriptions for RANGE_CH3_CH4
Bits Bit Name Description Reset Access
[7:4] CH4_RANGE Range options for Channel 4. 0x3 R/W
0000: ±2.5 V single-ended range.
0001: ±5 V single-ended range.
0010: ±10 V single-ended range.
0011: ±10 V single-ended range.
0100: ±10 V single-ended range.
0101: ±10 V single-ended range.
0110: ±10 V single-ended range.
0111: ±10 V single-ended range.
1000: ±10 V single-ended range.
1001: ±10 V single-ended range.
1010: ±10 V single-ended range.
1011: ±10 V single-ended range.
1100: reserved.
1101: reserved.
1110: reserved.
1111: reserved.
[3:0] CH3_RANGE Range options for Channel 3. 0x3 R/W
0000: ±2.5 V single-ended range.
0001: ±5 V single-ended range.
0010: ±10 V single-ended range.
0011: ±10 V single-ended range.
0100: ±10 V single-ended range.
0101: ±10 V single-ended range.
0110: ±10 V single-ended range.
0111: ±10 V single-ended range.
1000: ±10 V single-ended range.
1001: ±10 V single-ended range.
1010: ±10 V single-ended range.
1011: ±10 V single-ended range.
1100: reserved.
1101: reserved.
1110: reserved.
1111: reserved.
Data Sheet AD7606B
Rev. 0 | Page 53 of 69
Address: 0x05, Reset: 0x33, Name: RANGE_CH5_CH6
Range options f or Channel 6
1111: reserved.
1110: reserved.
1101: reserved.
...
0010: ±10V single-ended range.
0001: ±5V single-ended range.
0000: ±2.5V single-ended range. Range options f or Channel 5
1111: reserved.
1110: reserved.
1101: reserved.
...
0010: ±10V single-ended range.
0001: ±5V single-ended range.
0000: ±2.5V single-ended range.
0
1
1
1
2
0
3
0
4
1
5
1
6
0
7
0
[7: 4] CH6_RANGE (R/W) [3: 0] CH5_RANGE (R/W)
Table 36. Bit Descriptions for RANGE_CH5_CH6
Bits Bit Name Description Reset Access
[7:4] CH6_RANGE Range options for Channel 6. 0x3 R/W
0000: ±2.5 V single-ended range.
0001: ±5 V single-ended range.
0010: ±10 V single-ended range.
0011: ±10 V single-ended range.
0100: ±10 V single-ended range.
0101: ±10 V single-ended range.
0110: ±10 V single-ended range.
0111: ±10 V single-ended range.
1000: ±10 V single-ended range.
1001: ±10 V single-ended range.
1010: ±10 V single-ended range.
1011: ±10 V single-ended range.
1100: reserved.
1101: reserved.
1110: reserved.
1111: reserved.
[3:0] CH5_RANGE Range options for Channel 5. 0x3 R/W
0000: ±2.5 V single-ended range.
0001: ±5 V single-ended range.
0010: ±10 V single-ended range.
0011: ±10 V single-ended range.
0100: ±10 V single-ended range.
0101: ±10 V single-ended range.
0110: ±10 V single-ended range.
0111: ±10 V single-ended range.
1000: ±10 V single-ended range.
1001: ±10 V single-ended range.
1010: ±10 V single-ended range.
1011: ±10 V single-ended range.
1100: reserved.
1101: reserved.
1110: reserved.
1111: reserved.
AD7606B Data Sheet
Rev. 0 | Page 54 of 69
Address: 0x06, Reset: 0x33, Name: RANGE_CH7_CH8
Range options f or Channel 8
1111: reserved.
1110: reserved.
1101: reserved.
...
0010: ±10V single-ended range.
0001: ±5V single-ended range.
0000: ±2.5V single-ended range. Range options f or Channel 7
1111: reserved.
1110: reserved.
1101: reserved.
...
0010: ±10V single-ended range.
0001: ±5V single-ended range.
0000: ±2.5V single-ended range.
0
1
1
1
2
0
3
0
4
1
5
1
6
0
7
0
[7: 4] CH8_RANGE (R/W) [3: 0] CH7_RANGE (R/W)
Table 37. Bit Descriptions for RANGE_CH7_CH8
Bits Bit Name Description Reset Access
[7:4] CH8_RANGE Range options for Channel 8. 0x3 R/W
0000: ±2.5 V single-ended range.
0001: ±5 V single-ended range.
0010: ±10 V single-ended range.
0011: ±10 V single-ended range.
0100: ±10 V single-ended range.
0101: ±10 V single-ended range.
0110: ±10 V single-ended range.
0111: ±10 V single-ended range.
1000: ±10 V single-ended range.
1001: ±10 V single-ended range.
1010: ±10 V single-ended range.
1011: ±10 V single-ended range.
1100: reserved.
1101: reserved.
1110: reserved.
1111: reserved.
[3:0] CH7_RANGE Range options for Channel 7. 0x3 R/W
0000: ±2.5 V single-ended range.
0001: ±5 V single-ended range.
0010: ±10 V single-ended range.
0011: ±10 V single-ended range.
0100: ±10 V single-ended range.
0101: ±10 V single-ended range.
0110: ±10 V single-ended range.
0111: ±10 V single-ended range.
1000: ±10 V single-ended range.
1001: ±10 V single-ended range.
1010: ±10 V single-ended range.
1011: ±10 V single-ended range.
1100: reserved.
1101: reserved.
1110: reserved.
1111: reserved.
Data Sheet AD7606B
Rev. 0 | Page 55 of 69
Address: 0x08, Reset: 0x00, Name: OVERSAMPLING
O versampling padding, extend the
internal oversampling per i od all owing
evenly spaced sampling between
CO NVST rising edges.
O versampling rat i o
1111: oversampling off .
1110: oversampling off .
1101: oversampling off .
...
10: oversampling by 4.
1: oversampling by 2.
0: no oversampling.
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7: 4] OS_PAD (R/W) [3: 0] OS_RATIO (R/W)
Table 38. Bit Descriptions for OVERSAMPLING
Bits Bit Name Description Reset Access
[7:4] OS_PAD Oversampling padding, extend the internal oversampling period allowing evenly spaced sampling
between CONVST rising edges.
0x0 R/W
[3:0] OS_RATIO Oversampling ratio. 0x0 R/W
0: no oversampling.
1: oversampling by 2.
10: oversampling by 4.
11: oversampling by 8.
100: oversampling by 16.
101: oversampling by 32.
110: oversampling by 64.
111: oversampling by 128.
1000: oversampling by 256.
1001: oversampling off.
1010: oversampling off.
1011: oversampling off.
1100: oversampling off.
1101: oversampling off.
1110: oversampling off.
1111: oversampling off.
Address: 0x09, Reset: 0x00, Name: CH1_GAIN
R
FILTER
cal ibrati on regist er. Resolut i on:
1024 Ω. Range: 0 Ω to 65, 536 Ω
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:6] RESERVED [5:0] CH1_G AIN (R/W)
Table 39. Bit Descriptions for CH1_GAIN
Bits Bit Name Description Reset Access
[7:6] RESERVED Reserved. 0x0 R
[5:0] CH1_GAIN RFI LTER calibration register. Resolution: 1024 Ω. Range: 0 Ω to 65,536 Ω. 0x0 R/W
Address: 0x0A, Reset: 0x00, Name: CH2_GAIN
R
FILTER
cal ibrati on regist er. Resolut i on:
1024 Ω. Range: 0 Ω t o 65,536 Ω
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:6] RESERVED [5:0] CH2_G AIN (R/W)
Table 40. Bit Descriptions for CH2_GAIN
Bits Bit Name Description Reset Access
[7:6] RESERVED Reserved. 0x0 R
[5:0] CH2_GAIN RFI LTER calibration register. Resolution: 1024 Ω. Range: 0 Ω to 65,536 Ω. 0x0 R/W
AD7606B Data Sheet
Rev. 0 | Page 56 of 69
Address: 0x0B, Reset: 0x00, Name: CH3_GAIN
R
FILTER
calibration regis ter. Res olution
:
1024 Ω. Range: 0 Ω to 65,536 Ω
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:6] RESERVED [5:0] CH3_GAIN (R/W )
Table 41. Bit Descriptions for CH3_GAIN
Bits Bit Name Description Reset Access
[7:6] RESERVED Reserved. 0x0 R
[5:0] CH3_GAIN RFILTER calibration register. Resolution: 1024 Ω. Range: 0 Ω to 65,536 Ω. 0x0 R/W
Address: 0x0C, Reset: 0x00, Name: CH4_GAIN
R
FILTER
calibration regis ter. Res olution
:
1024 Ω. Range: 0 Ω to 65,536 Ω
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:6] RESERVED [5:0] CH4_GAIN (R/W )
Table 42. Bit Descriptions for CH4_GAIN
Bits Bit Name Description Reset Access
[7:6] RESERVED Reserved. 0x0 R
[5:0] CH4_GAIN RFILTER calibration register. Resolution: 1024 Ω. Range: 0 Ω to 65,536 Ω. 0x0 R/W
Address: 0x0D, Reset: 0x00, Name: CH5_GAIN
R
FILTER
calibration regis ter. Res olution
:
1024 Ω. Range: 0 Ω to 65,536 Ω
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:6] RESERVED [5:0] CH5_GAIN (R/W )
Table 43. Bit Descriptions for CH5_GAIN
Bits Bit Name Description Reset Access
[7:6] RESERVED Reserved. 0x0 R
[5:0] CH5_GAIN RFILTER calibration register. Resolution: 1024 Ω. Range: 0 Ω to 65,536 Ω. 0x0 R/W
Address: 0x0E, Reset: 0x00, Name: CH6_GAIN
R
FILTER
calibration regis ter. Res olution
:
1024 Ω. Range: 0 Ω to 65,536 Ω
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:6] RESERVED [5:0] CH5_GAIN (R/W )
Table 44. Bit Descriptions for CH6_GAIN
Bits Bit Name Description Reset Access
[7:6] RESERVED Reserved. 0x0 R
[5:0] CH6_GAIN RFILTER calibration register. Resolution: 1024 Ω. Range: 0 Ω to 65,536 Ω. 0x0 R/W
Data Sheet AD7606B
Rev. 0 | Page 57 of 69
Address: 0x0F, Reset: 0x00, Name: CH7_GAIN
R
FILTER
cal ibrati on regist er. Resolut i on:
1024 Ω. Range: 0 Ω to 65, 536 Ω
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:6] RESERVED [5:0] CH7_G AIN (R/W)
Table 45. Bit Descriptions for CH7_GAIN
Bits Bit Name Description Reset Access
[7:6] RESERVED Reserved. 0x0 R
[5:0] CH7_GAIN RFI LTER calibration register. Resolution: 1024 Ω. Range: 0 Ω to 65,536 Ω. 0x0 R/W
Address: 0x10, Reset: 0x00, Name: CH8_GAIN
R
FILTER
cal ibrati on regist er. Resolut i on:
1024 Ω. Range: 0 Ω to 65, 536 Ω
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:6] RESERVED [5:0] CH8_G AIN (R/W)
Table 46. Bit Descriptions for CH8_GAIN
Bits Bit Name Description Reset Access
[7:6] RESERVED Reserved. 0x0 R
[5:0] CH8_GAIN RFI LTER calibration register. Resolution: 1024 Ω. Range: 0 Ω to 65,536 Ω. 0x0 R/W
Address: 0x11, Reset: 0x80, Name: CH1_OFFSET
O ff set register. Range f rom –128
LSB to +127 LS B .
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
1
[7:0] CH 1_OFFSET (R/W)
Table 47. Bit Descriptions for CH1_OFFSET
Bits Bit Name Description Reset Access
[7:0] CH1_OFFSET Offset register. Range from −128 LSB to +127 LSB. 0x00 = −128 LSB offset; 0x80 = no offset;
0xFF = +127 LSB offset.
0x80 R/W
Address: 0x12, Reset: 0x80, Name: CH2_OFFSET
O ff set register. Range f rom –128
LSB to +127 LS B .
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
1
[7:0] CH 2_OFFSET (R/W)
Table 48. Bit Descriptions for CH2_OFFSET
Bits Bit Name Description Reset Access
[7:0] CH2_OFFSET Offset register. Range from −128 LSB to +127 LSB. 0x00 = −128 LSB offset; 0x80 = no offset;
0xFF = +127 LSB offset.
0x80 R/W
AD7606B Data Sheet
Rev. 0 | Page 58 of 69
Address: 0x13, Reset: 0x80, Name: CH3_OFFSET
O ff set register. Range f rom –128
LSB to +127 LS B .
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
1
[7:0] CH 3_OFFSET (R/W)
Table 49. Bit Descriptions for CH3_OFFSET
Bits Bit Name Description Reset Access
[7:0] CH3_OFFSET Offset register. Range from −128 LSB to +127 LSB. 0x00 = −128 LSB offset; 0x80 = no offset;
0xFF = +127 LSB offset.
0x80 R/W
Address: 0x14, Reset: 0x80, Name: CH4_OFFSET
O ff set register. Range f rom –128
LSB to +127 LS B .
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
1
[7:0] CH 4_OFFSET (R/W)
Table 50. Bit Descriptions for CH4_OFFSET
Bits Bit Name Description Reset Access
[7:0] CH4_OFFSET Offset register. Range from −128 LSB to +127 LSB. 0x00 = −128 LSB offset; 0x80 = no offset;
0xFF = +127 LSB offset.
0x80 R/W
Address: 0x15, Reset: 0x80, Name: CH5_OFFSET
O ff set register. Range f rom –128
LSB to +127 LS B .
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
1
[7:0] CH 5_OFFSET (R/W)
Table 51. Bit Descriptions for CH5_OFFSET
Bits Bit Name Description Reset Access
[7:0] CH5_OFFSET Offset register. Range from −128 LSB to +127 LSB. 0x00 = −128 LSB offset; 0x80 = no offset;
0xFF = +127 LSB offset.
0x80 R/W
Address: 0x16, Reset: 0x80, Name: CH6_OFFSET
O ff set register. Range f rom –128
LSB to +127 LS B .
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
1
[7:0] CH 6_OFFSET (R/W)
Table 52. Bit Descriptions for CH6_OFFSET
Bits Bit Name Description Reset Access
[7:0] CH6_OFFSET Offset register. Range from −128 LSB to +127 LSB. 0x00 = −128 LSB offset; 0x80 = no offset;
0xFF = +127 LSB offset.
0x80 R/W
Data Sheet AD7606B
Rev. 0 | Page 59 of 69
Address: 0x17, Reset: 0x80, Name: CH7_OFFSET
O ff set register. Range f rom –128
LSB to +127 LS B .
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
1
[7:0] CH 7_OFFSET (R/W)
Table 53. Bit Descriptions for CH7_OFFSET
Bits Bit Name Description Reset Access
[7:0] CH7_OFFSET Offset register. Range from −128 LSB to +127 LSB. 0x00 = −128 LSB offset; 0x80 = no offset;
0xFF = +127 LSB offset.
0x80 R/W
Address: 0x18, Reset: 0x80, Name: CH8_OFFSET
O ff set register. Range f rom –128
LSB to +127 LS B .
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
1
[7:0] CH 8_OFFSET (R/W)
Table 54. Bit Descriptions for CH8_OFFSET
Bits Bit Name Description Reset Access
[7:0] CH8_OFFSET Offset register. Range from −128 LSB to +127 LSB. 0x00 = −128 LSB offset; 0x80 = no offset;
0xFF = +127 LSB offset.
0x80 R/W
Address: 0x19, Reset: 0x00, Name: CH1_PHASE
Phase delay f rom 0 µs t o 318.75
µs in steps of 1.25 µs
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7: 0] CH1_PHASE_OFFSET (R/W)
Table 55. Bit Descriptions for CH1_PHASE
Bits Bit Name Description Reset Access
[7:0] CH1_PHASE_OFFSET Phase delay from 0 to 318.75 μs in steps of 1.25 μs. 0x0 R/W
Address: 0x1A, Reset: 0x00, Name: CH2_PHASE
Phase delay f rom 0 µs t o 318.75
µs in steps of 1.25 µs
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7: 0] CH2_PHASE_OF FSET (R/W)
Table 56. Bit Descriptions for CH2_PHASE
Bits Bit Name Description Reset Access
[7:0] CH2_PHASE_OFFSET Phase delay from 0 to 318.75 μs in steps of 1.25 μs. 0x0 R/W
Address: 0x1B, Reset: 0x00, Name: CH3_PHASE
Phase delay f rom 0 µs t o 318.75
µs in steps of 1.25 µs
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7: 0] CH3_PHASE_OFFSET (R/W)
Table 57. Bit Descriptions for CH3_PHASE
Bits Bit Name Description Reset Access
[7:0] CH3_PHASE_OFFSET Phase delay from 0 to 318.75 μs in steps of 1.25 μs. 0x0 R/W
AD7606B Data Sheet
Rev. 0 | Page 60 of 69
Address: 0x1C, Reset: 0x00, Name: CH4_PHASE
Phase delay f rom 0 µs t o 318.75
µs in steps of 1.25 µs
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7: 0] CH4_PHASE_OF FSET (R/W)
Table 58. Bit Descriptions for CH4_PHASE
Bits Bit Name Description Reset Access
[7:0] CH4_PHASE_OFFSET Phase delay from 0 to 318.75 μs in steps of 1.25 μs. 0x0 R/W
Address: 0x1D, Reset: 0x00, Name: CH5_PHASE
Phase delay f rom 0 µs t o 318.75
µs in steps of 1.25 µs
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7: 0] CH5_PHASE_OFFSET (R/W)
Table 59. Bit Descriptions for CH5_PHASE
Bits Bit Name Description Reset Access
[7:0] CH5_PHASE_OFFSET Phase delay from 0 to 318.75 μs in steps of 1.25 μs. 0x0 R/W
Address: 0x1E, Reset: 0x00, Name: CH6_PHASE
Phase delay f rom 0 µs t o 318.75
µs in steps of 1.25 µs
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7: 0] CH6_PHASE_OF FSET (R/W)
Table 60. Bit Descriptions for CH6_PHASE
Bits Bit Name Description Reset Access
[7:0] CH6_PHASE_OFFSET Phase delay from 0 to 318.75 μs in steps of 1.25 μs. 0x0 R/W
Address: 0x1F, Reset: 0x00, Name: CH7_PHASE
Phase delay f rom 0 µs t o 318.75
µs in steps of 1.25 µs
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7: 0] CH7_PHASE_OFFSET (R/W)
Table 61. Bit Descriptions for CH7_PHASE
Bits Bit Name Description Reset Access
[7:0] CH7_PHASE_OFFSET Phase delay from 0 to 318.75 μs in steps of 1.25 μs. 0x0 R/W
Address: 0x20, Reset: 0x00, Name: CH8_PHASE
Phase delay f rom 0 µs t o 318.75
µs in steps of 1.25 µs
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7: 0] CH8_PHASE_OF FSET (R/W)
Table 62. Bit Descriptions for CH8_PHASE
Bits Bit Name Description Reset Access
[7:0] CH8_PHASE_OFFSET Phase delay from 0 to 318.75 μs in steps of 1.25 μs. 0x0 R/W
Data Sheet AD7606B
Rev. 0 | Page 61 of 69
Address: 0x21, Reset: 0x01, Name: DIGITAL_DIAG_ENABLE
Enable i nterface c heck. Provides
a fixed dat a on each channel when
readi ng ADC dat a
Enable ROM CRC chec k
Enable FS and O S clock c ounter
Enable memory map CRC chec k
Enable busy st uc k high check
Enable i nterface CRC chec k
Enable checking if attempting t o read
from an invalid addr ess
Enable checking if attempting t o write
to an invalid address
0
1
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7] INTERFACE_CHECK_EN (R/W) [0] ROM_CRC_ERR_EN (R/W)
[6] CLK_F S_OS_COUNTER_E N (R/W)
[1] MM_CRC_ERR_EN (R/W)
[5] BUSY_STUCK_HIG H_ERR_EN (R/W)
[2] INT_CRC_ERR_EN (R/W)
[4] SPI_READ_ERR_E N (R/W)
[3] SPI_WRITE_ERR_EN (R/W)
Table 63. Bit Descriptions for DIGITAL_DIAG_ENABLE
Bits Bit Name Description Reset Access
7 INTERFACE_CHECK_EN Enable interface check. Provides a fixed data on each channel when reading ADC
data.
0x0 R/W
6 CLK_FS_OS_COUNTER_EN Enable FS and OS clock counter. 0x0 R/W
5 BUSY_STUCK_HIGH_ERR_EN Enable busy stuck high check. 0x0 R/W
4 SPI_READ_ERR_EN Enable checking if attempting to read from an invalid address. 0x0 R/W
3 SPI_WRITE_ERR_EN Enable checking if attempting to write to an invalid address. 0x0 R/W
2 INT_CRC_ERR_EN Enable interface CRC check. 0x0 R/W
1 MM_CRC_ERR_EN Enable memory map CRC check. 0x0 R/W
0 ROM_CRC_ERR_EN Enable ROM CRC check. 0x1 R/W
Address: 0x22, Reset: 0x00, Name: DIGITAL_DIAG_ERR
RO M CRC er ror
Busy stuck high error. Busy line has
been at high logic level f or longer
than 4us Memory map CRC error
SP I invalid read address I nterface CRC err or
SP I invalid write address
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:6] RESERVED [0] ROM_CRC_ERR (R/W1C)
[5] BUSY_STUCK_HIG H_ERR (R/W1C) [1] MM_CRC_ERR (R/W1C)
[4] SPI_READ_ERR (R/W1C) [2] INT_CRC_ERR (R/W1C)
[3] SPI_WRITE_ERR (R/W1C)
Table 64. Bit Descriptions for DIGITAL_DIAG_ERR
Bits Bit Name Description Reset Access
[7:6] RESERVED Reserved. 0x0 R
5 BUSY_STUCK_HIGH_ERR Busy stuck high error. Busy line has been at high logic level for longer than 4 μs. 0x0 R/W1C
4 SPI_READ_ERR SPI invalid read address. 0x0 R/W1C
3 SPI_WRITE_ERR SPI invalid write address. 0x0 R/W1C
2 INT_CRC_ERR Interface CRC error. 0x0 R/W1C
1 MM_CRC_ERR Memory map CRC error. 0x0 R/W1C
0 ROM_CRC_ERR ROM CRC error. 0x0 R/W1C
AD7606B Data Sheet
Rev. 0 | Page 62 of 69
Address: 0x23, Reset: 0x00, Name: OPEN_DETECT_ENABLE
In automatic mode, enabl e analog
input open det ec tion for Channel
8. In manual mode, set s the PGA
common mode t o hi gh
In automatic mode, enabl e analog
input open det ec tion for Channel
1. In manual mode, set s the PGA
common mode t o hi gh
In automatic mode, enabl e analog
input open det ec tion for Channel
7. In manual mode, set s the PGA
common mode t o hi gh
In automatic mode, enabl e analog
input open det ec tion for Channel
2. In manual mode, set s the PGA
common mode t o hi gh
In automatic mode, enabl e analog
input open det ec tion for Channel
6. In manual mode, set s the PGA
common mode t o hi gh
In automatic mode, enabl e analog
input open det ec tion for Channel
3. In manual mode, set s the PGA
common mode t o hi gh
In automatic mode, enabl e analog
input open det ec tion for Channel
5. In manual mode, set s the PGA
common mode t o hi gh
In automatic mode, enabl e analog
input open det ec tion for Channel
4. In manual mode, set s the PGA
common mode t o hi gh
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7] CH8_OPEN_DETECT_EN (R/W) [0] CH1_OPEN_DETECT_EN (R/W)
[6] CH7_OPEN_DETECT_EN (R/W) [1] CH2_OPEN_DETECT_EN (R/W)
[5] CH6_OPEN_DETECT_EN (R/W) [2] CH3_OPEN_DETECT_EN (R/W)
[4] CH5_OPEN_DETECT_EN (R/W) [3] CH4_OPEN_DETECT_EN (R/W)
Table 65. Bit Descriptions for OPEN_DETECT_ENABLE
Bits Bit Name Description Reset Access
7 CH8_OPEN_DETECT_EN
In automatic mode, enables analog input open detection for Channel 8. In manual
mode, sets the PGA common mode to high.
0x0 R/W
6 CH7_OPEN_DETECT_EN In automatic mode, enables analog input open detection for Channel 7. In manual
mode, sets the PGA common mode to high.
0x0 R/W
5 CH6_OPEN_DETECT_EN In automatic mode, enables analog input open detection for Channel 6. In manual
mode, sets the PGA common mode to high.
0x0 R/W
4 CH5_OPEN_DETECT_EN In automatic mode, enables analog input open detection for Channel 5. In manual
mode, sets the PGA common mode to high.
0x0 R/W
3 CH4_OPEN_DETECT_EN In automatic mode, enables analog input open detection for Channel 4. In manual
mode, sets the PGA common mode to high.
0x0 R/W
2 CH3_OPEN_DETECT_EN In automatic mode, enables analog input open detection for Channel 3. In manual
mode, sets the PGA common mode to high.
0x0 R/W
1 CH2_OPEN_DETECT_EN In automatic mode, enables analog input open detection for Channel 2. In manual
mode, sets the PGA common mode to high.
0x0 R/W
0 CH1_OPEN_DETECT_EN In automatic mode, enables analog input open detection for Channel 1. In manual
mode, sets the PGA common mode to high.
0x0 R/W
Address: 0x24, Reset: 0x00, Name: OPEN_DETECTED
Analog Input 8 open detected Analog I nput 1 open detected
Analog Input 7 open detected Analog I nput 2 open detected
Analog Input 6 open detected Analog I nput 3 open detected
Analog Input 5 open detected Analog I nput 4 open detected
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7] CH8_OPEN (R/W1C) [0] CH1_OPEN (R/W1C)
[6] CH7_OPEN (R/W1C) [1] CH2_OPEN (R/W1C)
[5] CH6_OPEN (R/W1C) [2] CH3_OPEN (R/W1C)
[4] CH5_OPEN (R/W1C) [3] CH4_OPEN (R/W1C)
Table 66. Bit Descriptions for OPEN_DETECTED
Bits Bit Name Description Reset Access
7 CH8_OPEN Analog Input 8 open detected. 0x0 R/W1C
6 CH7_OPEN Analog Input 7 open detected. 0x0 R/W1C
5 CH6_OPEN Analog Input 6 open detected. 0x0 R/W1C
4 CH5_OPEN Analog Input 5 open detected. 0x0 R/W1C
3 CH4_OPEN Analog Input 4 open detected. 0x0 R/W1C
Data Sheet AD7606B
Rev. 0 | Page 63 of 69
Bits Bit Name Description Reset Access
2 CH3_OPEN Analog Input 3 open detected. 0x0 R/W1C
1 CH2_OPEN Analog Input 2 open detected. 0x0 R/W1C
0 CH1_OPEN Analog Input 1 open detected. 0x0 R/W1C
Address: 0x25, Reset: 0x00, Name: AIN_OV_UV_DIAG_ENABLE
Enable over voltage/undervolt age
error check on Channel 8 Enable over voltage/undervolt age
error check on Channel 1
Enable over voltage/undervolt age
error check on Channel 7 Enable over voltage/undervolt age
error check on Channel 2
Enable over voltage/undervolt age
error check on Channel 6 Enable over voltage/undervolt age
error check on Channel 3
Enable over voltage/undervolt age
error check on Channel 5 Enable over voltage/undervolt age
error check on Channel 4
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7] CH8_OV_UV_EN (R/W) [0] CH1_OV_UV_EN (R/W)
[6] CH7_OV_UV_EN (R/W) [1] CH2_OV_UV_EN (R/W)
[5] CH6_OV_UV_EN (R/W) [2] CH3_OV_UV_EN (R/W)
[4] CH5_OV_UV_EN (R/W) [3] CH4_OV_UV_EN (R/W)
Table 67. Bit Descriptions for AIN_OV_UV_DIAG_ENABLE
Bits Bit Name Description Reset Access
7 CH8_OV_UV_EN Enable overvoltage/undervoltage error check on Channel 8. 0x0 R/W
6 CH7_OV_UV_EN Enable overvoltage/undervoltage error check on Channel 7. 0x0 R/W
5 CH6_OV_UV_EN Enable overvoltage/undervoltage error check on Channel 6. 0x0 R/W
4 CH5_OV_UV_EN Enable overvoltage/undervoltage error check on Channel 5. 0x0 R/W
3 CH4_OV_UV_EN Enable overvoltage/undervoltage error check on Channel 4. 0x0 R/W
2 CH3_OV_UV_EN Enable overvoltage/undervoltage error check on Channel 3. 0x0 R/W
1 CH2_OV_UV_EN Enable overvoltage/undervoltage error check on Channel 2. 0x0 R/W
0 CH1_OV_UV_EN Enable overvoltage/undervoltage error check on Channel 1. 0x0 R/W
Address: 0x26, Reset: 0x00, Name: AIN_OV_DIAG_ERROR
O vervoltage err or on Channel 8 Overvoltage err or on Channel 1
O vervoltage err or on Channel 7 Overvoltage err or on Channel 2
O vervoltage err or on Channel 6 Overvoltage err or on Channel 3
O vervoltage err or on Channel 5 Overvoltage err or on Channel 4
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7] CH8_OV_ERR (R/W1C) [0] CH1_OV_E RR (R/W1C)
[6] CH7_OV_ERR (R/W1C) [1] CH2_OV_E RR (R/W1C)
[5] CH6_OV_ERR (R/W1C) [2] CH3_OV_E RR (R/W1C)
[4] CH5_OV_ERR (R/W1C) [3] CH4_OV_E RR (R/W1C)
Table 68. Bit Descriptions for AIN_OV_DIAG_ERROR
Bits Bit Name Description Reset Access
7 CH8_OV_ERR Overvoltage error on Channel 8. 0x0 R/W1C
6 CH7_OV_ERR Overvoltage error on Channel 7. 0x0 R/W1C
5 CH6_OV_ERR Overvoltage error on Channel 6. 0x0 R/W1C
4 CH5_OV_ERR Overvoltage error on Channel 5. 0x0 R/W1C
3 CH4_OV_ERR Overvoltage error on Channel 4. 0x0 R/W1C
2 CH3_OV_ERR Overvoltage error on Channel 3. 0x0 R/W1C
1 CH2_OV_ERR Overvoltage error on Channel 2. 0x0 R/W1C
0 CH1_OV_ERR Overvoltage error on Channel 1. 0x0 R/W1C
AD7606B Data Sheet
Rev. 0 | Page 64 of 69
Address: 0x27, Reset: 0x00, Name: AIN_UV_DIAG_ERROR
Undervoltage err or on Channel 8 Undervoltage err or on Channel 1
Undervoltage err or on Channel 7 Undervoltage err or on Channel 2
Undervoltage err or on Channel 6 Undervoltage err or on Channel 3
Undervoltage err or on Channel 5 Undervoltage err or on Channel 4
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7] CH8_UV_ERR (R/W1C) [0] CH1_UV_ERR (R/W1C)
[6] CH7_UV_ERR (R/W1C) [1] CH2_UV_ERR (R/W1C)
[5] CH6_UV_ERR (R/W1C) [2] CH3_UV_ERR (R/W1C)
[4] CH5_UV_ERR (R/W1C) [3] CH4_UV_ERR (R/W1C)
Table 69. Bit Descriptions for AIN_UV_DIAG_ERROR
Bits Bit Name Description Reset Access
7 CH8_UV_ERR Undervoltage error on Channel 8. 0x0 R/W1C
6 CH7_UV_ERR Undervoltage error on Channel 7. 0x0 R/W1C
5 CH6_UV_ERR Undervoltage error on Channel 6. 0x0 R/W1C
4 CH5_UV_ERR Undervoltage error on Channel 5. 0x0 R/W1C
3 CH4_UV_ERR Undervoltage error on Channel 4. 0x0 R/W1C
2 CH3_UV_ERR Undervoltage error on Channel 3. 0x0 R/W1C
1 CH2_UV_ERR Undervoltage error on Channel 2. 0x0 R/W1C
0 CH1_UV_ERR Undervoltage error on Channel 1. 0x0 R/W1C
Address: 0x28, Reset: 0x00, Name: DIAGNOSTIC_MUX_CH1_2
Channel 1 diagnostic mux control.
Select ±10V range.
111: .
CC
AVselect
110: select AGND.
101: .
DRIVE
Vselect
100: select DLDO 1.8V x 4.
011: select ALDO 1.8V x 4.
010: select 2. 5V.
001:
+ 25° C.
= (output voltage - 0.17267)/0.0004832
select t emperature sensor . Die temper ature
000: select analog input pin.
Channel 2 diagnostic mux control.
Select ±10V range.
111: .
CC
AVselect
110: select AGND.
101: .
DRIVE
Vselect
100: select ALDO 1.8V x 4.
011: select ALDO 1.8V x 4.
010: select 2. 5V.
001:
+ 25° C.
= (output voltage - 0.17267)/0.0004832
select t emperature sensor . Die temper ature
000: select analog input pin.
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:6] RESERVED [2: 0] CH1_DIAG _MUX_CTRL (R/W)
[5: 3] CH2_DIAG _MUX_CTRL (R/W)
Table 70. Bit Descriptions for DIAGNOSTIC_MUX_CH1_2
Bits Bit Name Description Reset Access
[7:6] RESERVED Reserved. 0x0 R
[5:3] CH2_DIAG_MUX_CTRL Channel 2 diagnostic mux control. Select ±10 V range. 0x0 R/W
000: select analog input pin.
001: select temperature sensor. Die temperature = (output voltage −
0.17267)/0.0004832 + 25°C.
010: select 2.5 V.
011: select ALDO 1.8 V × 4.
100: select ALDO 1.8 V × 4.
101: select VDRIVE.
110: select AGND.
111: select AVCC.
[2:0] CH1_DIAG_MUX_CTRL Channel 1 diagnostic mux control. Select ±10 V range. 0x0 R/W
000: select analog input pin.
001: select temperature sensor. Die temperature = (output voltage −
0.17267)/0.0004832 + 25°C.
010: select 2.5 V.
011: select ALDO 1.8 V × 4.
100: select DLDO 1.8 V × 4.
Data Sheet AD7606B
Rev. 0 | Page 65 of 69
Bits Bit Name Description Reset Access
101: select VDRIVE.
110: select AGND.
111: select AVCC.
Address: 0x29, Reset: 0x00, Name: DIAGNOSTIC_MUX_CH3_4
Channel 3 diagnostic mux control.
Select ±10V range.
111: .
CC
AVselect
110: select AGND.
101: .
DRIVE
Vselect
100: select ALDO 1.8V x 4.
011: select ALDO 1.8V x 4.
010: select 2. 5V.
001:
+ 25° C.
= (output voltage - 0.17267)/0.0004832
select t emperature sensor . Die temper ature
000: select analog input pin.
Channel 4 diagnostic mux control.
Select ±10V range.
111: .
CC
AVselect
110: select AGND.
101: .
DRIVE
V
select
100: select ALDO 1.8V x 4.
011: select ALDO 1.8V x 4.
010: select 2. 5V.
001:
+ 25° C.
= (output voltage - 0.17267)/0.0004832
select t emperature sensor . Die temper ature
000: select analog input pin.
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:6] RESERVED [2: 0] CH3_DIAG _MUX_CTRL (R/W)
[5: 3] CH4_DIAG _MUX_CTRL (R/W)
Table 71. Bit Descriptions for DIAGNOSTIC_MUX_CH3_4
Bits Bit Name Description Reset Access
[7:6] RESERVED Reserved. 0x0 R
[5:3]
CH4_DIAG_MUX_CTRL
Channel 4 diagnostic mux control. Select ±10 V range.
0x0
R/W
000: select analog input pin.
001: select temperature sensor. Die temperature = (output voltage −
0.17267)/0.0004832 + 25°C.
010: select 2.5 V.
011: select ALDO 1.8 V × 4.
100: select ALDO 1.8 V × 4.
101: select VDRIVE.
110: select AGND.
111: select AVCC.
[2:0] CH3_DIAG_MUX_CTRL Channel 3 diagnostic mux control. Select ±10 V range. 0x0 R/W
000: select analog input pin.
001: select temperature sensor. Die temperature = (output voltage −
0.17267)/0.0004832 + 25°C.
010: select 2.5 V.
011: select ALDO 1.8 V × 4.
100: select ALDO 1.8 V × 4.
101: select VDRIVE.
110: select AGND.
111: select AVCC.
AD7606B Data Sheet
Rev. 0 | Page 66 of 69
Address: 0x2A, Reset: 0x00, Name: DIAGNOSTIC_MUX_CH5_6
Channel 5 diagnostic mux control.
Select ±10V range.
111: .
CC
AVselect
110: select AGND.
101: .
DRIVE
Vselect
100: select ALDO 1.8V x 4.
011: select ALDO 1.8V x 4.
010: select 2. 5V.
001:
+ 25° C.
= (output voltage - 0.17267)/0.0004832
select t emperature sensor . Die temper ature
000: select analog input pin.
Channel 6 diagnostic mux control.
Select ±10V range.
111: .
CC
AVselect
110: select AGND.
101: .
DRIVE
Vselect
100: select ALDO 1.8V x 4.
011: select ALDO 1.8V x 4.
010: select 2. 5V.
001:
+ 25° C.
= (output voltage - 0.17267)/0.0004832
select t emperature sensor . Die temper ature
000: select analog input pin.
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:6] RESERVED [2: 0] CH5_DIAG _MUX_CTRL (R/W)
[5: 3] CH6_DIAG _MUX_CTRL (R/W)
Table 72. Bit Descriptions for DIAGNOSTIC_MUX_CH5_6
Bits Bit Name Description Reset Access
[7:6] RESERVED Reserved. 0x0 R
[5:3] CH6_DIAG_MUX_CTRL Channel 6 diagnostic mux control. Select ±10 V range. 0x0 R/W
000: select analog input pin.
001: select temperature sensor. Die temperature = (output voltage −
0.17267)/0.0004832 + 25°C.
010: select 2.5 V.
011: select ALDO 1.8 V × 4.
100: select ALDO 1.8 V × 4.
101: select VDRIVE.
110: select AGND.
111: select AVCC.
[2:0] CH5_DIAG_MUX_CTRL Channel 5 diagnostic mux control. Select ±10 V range. 0x0 R/W
000: select analog input pin.
001: select temperature sensor. Die temperature = (output voltage −
0.17267)/0.0004832 + 25°C.
010: select 2.5 V.
011: select ALDO 1.8 V × 4.
100: select ALDO 1.8 V × 4.
101: select VDRIVE.
110: select AGND.
111: select AVCC.
Data Sheet AD7606B
Rev. 0 | Page 67 of 69
Address: 0x2B, Reset: 0x00, Name: DIAGNOSTIC_MUX_CH7_8
Channel 7 diagnostic mux control.
Select ±10V range.
111: .
CC
AVselect
110: select AGND.
101: .
DRIVE
Vselect
100: select ALDO 1.8V x 4.
011: select ALDO 1.8V x 4.
010: select 2. 5V.
001:
+ 25° C.
= (output voltage - 0.17267)/0.0004832
select t emperature sensor . Die temper ature
000: select analog input pin.
Channel 8 diagnostic mux control.
Select ±10V range.
111: .
CC
AVselect
110: select AGND.
101: .
DRIVE
Vselect
100: select ALDO 1.8V x 4.
011: select ALDO 1.8V x 4.
010: select 2. 5V.
001:
+ 25° C.
= (output voltage - 0.17267)/0.0004832
select t emperature sensor . Die temper ature
000: select analog input pin.
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7:6] RESERVED [2: 0] CH7_DIAG _MUX_CTRL (R/W)
[5: 3] CH8_DIAG _MUX_CTRL (R/W)
Table 73. Bit Descriptions for DIAGNOSTIC_MUX_CH7_8
Bits Bit Name Description Reset Access
[7:6] RESERVED Reserved. 0x0 R
[5:3] CH8_DIAG_MUX_CTRL Channel 8 diagnostic mux control. Select ±10 V range. 0x0 R/W
000: select analog input pin.
001: select temperature sensor. Die temperature = (output voltage −
0.17267)/0.0004832 + 25°C.
010: select 2.5 V.
011: select ALDO 1.8 V × 4.
100: select ALDO 1.8 V × 4.
101: select VDRIVE.
110: select AGND.
111: select AVCC.
[2:0] CH7_DIAG_MUX_CTRL Channel 7 diagnostic mux control. Select ±10 V range. 0x0 R/W
000: select analog input pin.
001: select temperature sensor. Die temperature = (output voltage −
0.17267)/0.0004832 + 25°C.
010: select 2.5 V.
011: select ALDO 1.8 V × 4.
100: select ALDO 1.8 V × 4.
101: select VDRIVE.
110: select AGND.
111: select AVCC.
Address: 0x2C, Reset: 0x00, Name: OPEN_DETECT_QUEUE
Number of conversions for no change
on output codes before enabling
open detect f unction. Range = 2 to
256. Q ueue = 1 enabl es manual
mode
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7: 0] OPEN_DETECT_QUEUE (R/W)
Table 74. Bit Descriptions for OPEN_DETECT_QUEUE
Bits Bit Name Description Reset Access
[7:0] OPEN_DETECT_QUEUE Number of conversions for no change on output codes before enabling open detect
function. Range = 2 to 256. Queue = 1 enables manual mode.
0x0 R/W
AD7606B Data Sheet
Rev. 0 | Page 68 of 69
Address: 0x2D, Reset: 0x00, Name: FS_CLK_COUNTER
Determine the frequency of the F S
cl oc k oscill ator. Count er is incremented
at 16 M/64.
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7: 0] CLK_FS_COUNTER (R)
Table 75. Bit Descriptions for FS_CLK_COUNTER
Bits Bit Name Description Reset Access
[7:0] CLK_FS_COUNTER Determine the frequency of the FS clock oscillator. Counter is incremented at 16 M/64. 0x0 R
Address: 0x2E, Reset: 0x00, Name: OS_CLK_COUNTER
Determine the frequency of the OS
cl oc k oscill ator. Count er resolut i on
= 200 kHz.
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7: 0] CLK_OS_COUNTER (R)
Table 76. Bit Descriptions for OS_CLK_COUNTER
Bits Bit Name Description Reset Access
[7:0] CLK_OS_COUNTER Determine the frequency of the OS clock oscillator. Counter resolution = 200 kHz. 0x0 R
Address: 0x2F, Reset: 0x14, Name: ID
Generic
0001: AD7606B Generi c .
0000: reserved. Silicon revision
0
0
1
0
2
0
3
0
4
0
5
0
6
0
7
0
[7: 4] DEVICE_ID (R) [3: 0] SILICON_REVISION (R)
Table 77. Bit Descriptions for ID
Bits Bit Name Description Reset Access
[7:4] DEVICE_ID Generic. 0x1 R
0000: reserved.
0001: AD7606B generic.
[3:0] SILICON_REVISION Silicon revision. 0x4 R
Data Sheet AD7606B
Rev. 0 | Page 69 of 69
OUTLINE DIMENSIONS
COMPLIANT TO JE DE C S TANDARDS MS-026-BCD
051706-A
TOP VIEW
(PINS DOW N)
1
16
17 33
32
48
4964
0.27
0.22
0.17
0.50
BSC
LE AD PIT CH
12.20
12.00 SQ
11.80
PIN 1
1.60
MAX
0.75
0.60
0.45
10.20
10.00 SQ
9.80
VIEW A
0.20
0.09
1.45
1.40
1.35
0.08
COPLANARITY
VIEW A
ROTAT E D 90° CCW
SEATING
PLANE
0.15
0.05
7°
3.5°
0°
Figure 88. 64-Lead Low Profile Quad Flat Package [LQFP]
(ST-64-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
AD7606BBSTZ −40°C to +125°C 64-Lead Low Profile Quad Flat Package [LQFP] ST-64-2
AD7606BBSTZ-RL −40°C to +125°C 64-Lead Low Profile Quad Flat Package [LQFP] ST-64-2
EVAL-AD7606BFMCZ Evaluation Board for the AD7606B
EVAL-SDP-CH1Z Evaluation Controller Board
1 Z = RoHS Compliant Part.
©2019 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D15137-0-6/19(0)
