8-Channel DAS with 16-Bit, 800 kSPS Bipolar Input, Simultaneous Sampling ADC AD7606B Data Sheet FEATURES APPLICATIONS 16-bit ADC with 800 kSPS on all channels Input buffer with 5 M analog input impedance Pin to pin compatible with the AD7606 -40C to +125C operating temperature range Single 5 V analog supply and 1.71 V to 3.6 V VDRIVE supply 21 V input clamp protection with 8 kV ESD Extra modes available in software mode Per channel selectable analog input ranges Single-ended, bipolar: 10 V, 5 V, and 2.5 V Per channel system phase, offset, and gain calibration Analog input open circuit detection feature <20 LSB open circuit code error (RPD = 10 k) Self diagnostics and monitoring features CRC error checking on read/write data and registers Power line monitoring Protective relays Multiphase motor control Instrumentation and control systems Data acquisition systems FUNCTIONAL BLOCK DIAGRAM AVCC AD7606B ALDO V1 CLAMP V1GND CLAMP V2 CLAMP V2GND CLAMP AVCC REGCAP REGCAP VDRIVE DLDO 5M 5M PGA SAR CLK OSC LPF 5M 5M PGA CONVST RESET RANGE CONTROL INPUTS SAR LPF OS0 TO OS2 V3 CLAMP V3GND CLAMP V4 CLAMP V4GND CLAMP V5 CLAMP V5GND CLAMP V6 CLAMP V6GND CLAMP 5M 5M PGA SAR LPF PROGRAMMABLE DIGITAL FILTER SW/HW MODE CONTROL BUSY FRSTDATA SERIAL 5M 5M PGA SAR LPF 5M 5M PGA PARALLEL/ SERIAL INTERFACE PGA SDI SCLK CS PARALLEL DB0 TO DB15 RD WR SAR SYSTEM GAIN, OFFSET AND PHASE CALIBRATION LPF 5M 5M ADC, PGA, AND CHANNEL CONTROL AND CONFIGURATION DOUTA TO DOUTD PAR/SER SEL SAR LPF REFCAPA CLAMP V7GND CLAMP V8 CLAMP V8GND CLAMP 5M 5M PGA SAR LPF DIAGNOSTICS AND ANALOG INPUT OPEN DETECT CONFIGURATION REFCAPB REFIN/REFOUT 5M 5M PGA 2.5V REF SAR LPF REF SELECT REFGND AGND 15137-001 V7 Figure 1. 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Technical Support www.analog.com AD7606B Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 System Phase Calibration .......................................................... 29 Applications ....................................................................................... 1 System Gain Calibration............................................................ 29 Functional Block Diagram .............................................................. 1 System Offset Calibration ......................................................... 29 Revision History ............................................................................... 2 Analog Input Open Circuit Detection .................................... 30 General Description ......................................................................... 3 Digital Interface .............................................................................. 32 Specifications..................................................................................... 4 Hardware Mode .......................................................................... 32 Timing Specifications .................................................................. 6 Software Mode ............................................................................ 32 Absolute Maximum Ratings.......................................................... 10 Parallel Interface ......................................................................... 33 Thermal Resistance .................................................................... 10 Serial Interface ............................................................................ 35 ESD Caution ................................................................................ 10 Diagnostics ...................................................................................... 39 Pin Configuration and Function Descriptions ........................... 11 Reset Detection ........................................................................... 39 Typical Performance Characteristics ........................................... 14 Overvoltage and Undervoltage Events .................................... 39 Terminology .................................................................................... 20 Digital Error ................................................................................ 39 Theory of Operation ...................................................................... 22 Diagnostics Multiplexer ............................................................ 42 Analog Front End ....................................................................... 22 Typical Connection Diagram ....................................................... 44 SAR ADC..................................................................................... 23 Applications Information .............................................................. 46 Reference ..................................................................................... 23 Layout Guidelines....................................................................... 46 Operation Modes ........................................................................ 24 Register Summary .......................................................................... 48 Digital Filter .................................................................................... 27 Register Details ............................................................................... 50 Padding Oversampling .............................................................. 28 Outline Dimensions ....................................................................... 69 External Oversampling Clock................................................... 28 Ordering Guide .......................................................................... 69 System Calibration Features .......................................................... 29 REVISION HISTORY 6/2019--Revision 0: Initial Version Rev. 0 | Page 2 of 69 Data Sheet AD7606B GENERAL DESCRIPTION The AD7606B is a 16-bit, simultaneous sampling, analog-todigital data acquisition system (DAS) with eight channels, each channel containing analog input clamp protection, a programmable gain amplifier (PGA), a low-pass filter, and a 16-bit successive approximation register (SAR), analog-to-digital converter (ADC). The AD7606B also contains a flexible digital filter, low drift, 2.5 V precision reference and reference buffer to drive the ADC and flexible parallel and serial interfaces. The AD7606B operates from a single 5 V supply and accommodates 10 V, 5 V, and 2.5 V true bipolar input ranges when sampling at throughput rates of 800 kSPS for all channels. The input clamp protection tolerates voltages up to 21 V. The AD7606B has a 5 M analog input impedance, resulting in less than 20 LSB bipolar zero code when the input signal is disconnected and pulled to ground through a 10 k external resistor. The single supply operation, on-chip filtering, and high input impedance eliminates the need for external driver op amps, which require bipolar supplies. For applications with lower throughput rates, the AD7606B flexible digital filter can be used to improve noise performance. In hardware mode, the AD7606B is fully compatible with the AD7606. In software mode, the following advanced features are available: Additional 2.5 V analog input range. Analog input range (10 V, 5 V, and 2.5 V), selectable per channel. Additional oversampling (OS) options, up to OS x 256. System gain, system offset, and system phase calibration per channel. Analog input open circuit detector. Diagnostic multiplexer. Monitoring functions (serial peripheral interface (SPI) invalid read/write, cyclic redundancy check (CRC), overvoltage and undervoltage events, busy stuck monitor, and reset detection). Note that throughout this data sheet, multifunction pins, such as the RD/SCLK pin, are referred to either by the entire pin name or by a single function of the pin, for example, the SCLK pin, when only that function is relevant. Table 1. Pin to Pin Compatible Devices Resolution (Bits) 18 16 14 Rev. 0 | Page 3 of 69 Single-Ended Bipolar Inputs AD7608 AD7606 AD7606B AD7607 True Differential Bipolar Inputs AD7609 AD7606B Data Sheet SPECIFICATIONS Voltage reference (VREF) = 2.5 V external and internal, analog supply voltage (AVCC) = 4.75 V to 5.25 V, logic supply voltage (VDRIVE) = 1.71 V to 3.6 V, sample frequency (fSAMPLE) = 800 kSPS, with no oversampling, TA = -40C to +125C, single-ended input, and all input voltage ranges, unless otherwise noted. Table 2. Parameter DYNAMIC PERFORMANCE Signal-to-Noise Ratio (SNR) 1 Total Harmonic Distortion (THD) Signal-to-Noise-and-Distortion Spurious-Free Dynamic Range (SFDR) Channel to Channel Isolation Full Scale Step Settling Time ANALOG INPUT FILTER Full Power Bandwidth Phase Delay Test Conditions/Comments Input frequency (fIN) = 1 kHz sine wave, unless otherwise noted No oversampling (OS), 10 V range No OS, 5 V range No OS, 2.5 V range Oversampling ratio (OSR) = 16x, 10 V range OSR = 16x, 5 V range OSR = 16x, 2.5 V range All input ranges fSAMPLE = 200 kSPS fSAMPLE = 800 kSPS No OS, 10 V range No OS, 5 V range No OS, 2.5 V range OSR = 16x, 10 V range OSR = 16x, 5 V range OSR = 16x, 2.5 V range Min Typ 87.5 86.5 83.5 92 90.5 87.5 89.5 88.5 86 93.5 92 89 86.5 85.5 83 89 89 86.5 -105 -100 88.5 87.7 85.5 92 91.3 88.7 -104 Max Unit dB dB dB dB dB dB -94 -90 dB dB dB dB dB dB dB dB dB fIN on unselected channels up to 160 kHz 0.01% of full scale 10 V range 5 V range 2.5V range -110 dB 70 110 130 s s s -3 dB, 10 V range -3 dB, 5 V range -3 dB, 2.5 V range -0.1 dB, 10 V range -0.1 dB, 5 V range -0.1 dB, 2.5 V range 10 V range 5 V range 2.5 V range 22.5 13.5 11.5 3 2 2 8 9 11 kHz kHz kHz kHz kHz kHz s s s Phase Delay Matching 10 V range 5 V range 2.5 V range DC ACCURACY Resolution Differential Nonlinearity (DNL) Integral Nonlinearity (INL) Total Unadjusted Error (TUE) Positive and Negative FullScale (FS) Error 3 No missing codes 240 365 445 ns ns ns Bits LSB 2 LSB2 LSB2 LSB LSB LSB 16 0.5 fSAMPLE = 200 kSPS fSAMPLE = 800 kSPS Internal reference External reference 1.16 3 2 0.99 2 2.5 47 30 Internal reference 2 45 Rev. 0 | Page 4 of 69 Data Sheet Parameter Positive and Negative FS Error Drift AD7606B Test Conditions/Comments RFILTER4 = 20 k, system gain calibration disabled RFILTER4 = 0 k to 65 k, system gain calibration enabled External reference Internal reference Min Typ 126 4 1 4 3 5 15 20 Unit LSB LSB ppm/C ppm/C LSB 1 1 0.2 1.5 1.4 12 12 17 17 22 22 20 14 2 23 14 30 20 35 25 40 30 LSB2 LSB ppm/C LSB2 LSB LSB LSB LSB LSB LSB LSB -10 -5 -2.5 +10 +5 +2.5 V V V -0.7 -0.1 -0.1 +1.9 +2.7 +3.1 V V V A pF M ppm/C Positive and Negative FS Error Matching Bipolar Zero Code Error TA = -40C to +85C Bipolar Zero Code Error Drift Bipolar Zero Code Error Matching Open Circuit Code Error ANALOG INPUT Input Voltage Ranges Input Voltage Ranges Analog Input Current Input Capacitance (CIN)6 Input Impedance (RIN)7 Input Impedance Drift REFERENCE INPUT/OUTPUT Reference Input Voltage DC Leakage Current Input Capacitance6 Reference Output Voltage Reference Temperature Coefficient Reference Voltage to the ADC LOGIC INPUTS Input High Voltage (VINH) Input Low Voltage (VINL) Input Current (IIN) Input Capacitance6 LOGIC OUTPUTS Output High Voltage (VOH) Output Low Voltage (VOL) Floating State Leakage Current Output Capacitance6 Output Coding CONVERSION RATE Conversion Time Acquisition Time Throughput Rate TA = -40C to +85C Pull-down resistor (RPD)5 = 10 k, 10 V range RPD = 10 k, 10 V range, TA = -40C to +85C RPD = 10 k, 5 V range RPD = 10 k, 5 V range, TA = -40C to +85C RPD = 10 k, 2.5 V range RPD = 10 k, 2.5 V range, TA = -40C to +85C Vx - VxGND 10 V range 5 V range 2.5 V range VxGND - AGND 10 V range 5 V range 2.5 V range See the Typical Performance Characteristics section Max (VIN - 2)/RIN 5 5 1 25 REF SELECT = 0, external reference 2.495 2.5 REF SELSECT = 1, internal reference, TA = 25C 2.497 7.5 2.5 3 REFCAPA (Pin 44) and REFCAPB (Pin 45) 4.39 2.505 0.12 2.503 15 4.41 0.7 x VDRIVE 0.3 x VDRIVE 1 5 Current source (ISOURCE) = 100 A Current sink (ISINK) = 100 A VDRIVE - 0.2 1 5 0.2 20 Twos complement See Table 3 0.75 0.5 Per channel 800 Rev. 0 | Page 5 of 69 V A pF V ppm/C V V V A pF V V A pF N/A8 s s kSPS AD7606B Data Sheet Parameter POWER REQUIREMENTS AVCC VDRIVE REGCAP AVCC Current (IAVCC) Normal Mode (Static) Normal Mode (Operational) Test Conditions/Comments fSAMPLE = 800 kSPS fSAMPLE = 10 kSPS Standby Shutdown Mode VDRIVE Current (IDRIVE) Normal Mode (Static) Normal Mode (Operational) fSAMPLE = 800 kSPS fSAMPLE = 10 kSPS Standby Shutdown Mode Power Dissipation Normal Mode (Static) Normal Mode (Operational) fSAMPLE = 800 kSPS fSAMPLE = 10 kSPS Standby Shutdown Mode Min Typ Max Unit 4.75 1.71 1.875 5 5.25 3.6 1.93 V V V 7.5 43 8 3.5 0.5 9.5 47.5 10 4.5 5 mA mA mA mA A 1.8 1.1 30 1.6 0.8 3.5 1.5 75 3 2 A mA A A A 40 230 42 18 2.5 50 255 50 24 25 mW mW mW mW W No OS means no oversampling is applied. LSB means least significant bit. With a 2.5 V input range, 1 LSB = 76.293 V. With a 5 V input range, 1 LSB = 152.58 V. With a 10 V input range, 1 LSB = 305.175 V. 3 These specifications include the full temperature range variation and contribution from the internal reference and reference buffer. 4 RFILTER is a resistor placed in a series to the analog input front-end. See Figure 57. 5 See Figure 59. 6 Not production tested. Sample tested during initial release to ensure compliance. 7 Input impedance variation is factory trimmed and accounted for in the System Gain Calibration section. 8 N/A means not applicable. 1 2 TIMING SPECIFICATIONS Universal Timing Specifications AVCC = 4.75 V to 5.25 V, VDRIVE = 1.71 V to 3.6 V, VREF = 2.5 V external reference and internal reference, and TA = -40C to +125C, unless otherwise noted. Interface timing tested using a load capacitance of 20 pF, dependent on VDRIVE and load capacitance for serial interface. Table 3. Parameter tCYCLE Min 1.25 tLP_CNV tHP_CNV tD_CNV_BSY 10 10 tS_BSY Max 0.65 2.2 4.65 9.6 19.4 Unit s ns ns 20 25 ns ns ns 25 ns 0.85 2.3 4.8 9.9 20 s s s s s 0 tD_BSY tCONV Typ Description Minimum time between consecutive CONVST rising edges (excluding oversampling modes) 1 CONVST low pulse width CONVST high pulse width CONVST high to BUSY high delay time VDRIVE > 2.7 V VDRIVE < 2.7 V Minimum time from BUSY falling edge to RD falling edge setup time (in parallel interface) or to MSB being available on DOUTx line (in serial interface) Maximum time between last RD falling edge (in parallel interface) or last LSB being clocked out (serial interface) and the following BUSY falling edge; read during conversion Conversion time; no oversampling Oversampling by 2 Oversampling by 4 Oversampling by 8 Oversampling by 16 Rev. 0 | Page 6 of 69 Data Sheet Parameter tRESET Partial Reset Full Reset tDEVICE_SETUP Partial Reset Full Reset tWAKE-UP Standby Shutdown tPOWER-UP 1 AD7606B Min 39.2 78.7 157.6 315.6 Typ Max 40.2 80.8 161.9 324 Unit s s s s Description Oversampling by 32 Oversampling by 64 Oversampling by 128 Oversampling by 256 2000 Partial RESET high pulse width Full RESET high pulse width Time between RESET falling edge and first CONVST rising edge 50 253 ns ns s ns s 1 10 10 s ms ms 55 3000 Wake-up time after standby/shutdown mode Time between stable VCC/VDRIVE and assert of RESET Applies to serial mode when all four DOUTx lines are selected. AVCC VDRIVE tPOWER-UP tRESET RESET tCYCLE tDEVICE_SETUP tHP_CNV tLP_CNV CONVST tCONV tD_CNV_BSY BUSY tD_BSY READ DURING CONVERSION READ AFTER CONVERSION 15137-002 tS_BSY CS Figure 2. Universal Timing Diagram Parallel Mode Timing Specifications Table 4. Parameter tS_CS_RD Min 0 tH_RD_CS tHP_RD tLP_RD tHP_CS Unit ns Description CS falling edge to RD falling edge setup time 0 ns RD rising edge to CS rising edge hold time 10 10 10 ns ns ns RD high pulse width RD low pulse width CS high pulse width ns Delay from CS until DBx three-state disabled ns CS to DBx hold time ns ns ns ns Data access time after falling edge of RD VDRIVE > 2.7 V VDRIVE < 2.7 V Data hold time after falling edge of RD CS rising edge to DBx high impedance ns ns ns RD falling edge to next RD falling edge VDRIVE > 2.7 V VDRIVE < 2.7 V Delay from CS falling edge until FRSTDATA three-state disabled tD_CS_DB tH_CS_DB Typ Max 35 0 tD_RD_DB 27 37 tH_RD_DB tDHZ_CS_DB 12 40 tCYC_RD 30 40 tD_CS_FD 26 Rev. 0 | Page 7 of 69 AD7606B Data Sheet Parameter tD_RD_FDH tD_RD_FDL tDHZ_FD tS_CS_WR Min tHP_WR tLP_WR Typ Max 30 30 28 0 Unit ns ns ns ns Description Delay from RD falling edge until FRSTDATA high Delay from RD falling edge until FRSTDATA low Delay from CS rising edge until FRSTDATA three-state enabled CS to WR setup time 213 ns tH_WR_CS 88 213 0 ns ns ns WR high pulse width WR low pulse width VDRIVE > 2.7 V VDRIVE < 2.7 V WR hold time tS_DB_WR tH_WR_DB tCYC_WR 5 5 230 ns ns ns Configuration data to WR setup time Configuration data to WR hold time Configuration data settle time, WR rising edge to next WR rising edge CS tHP_RD tS_CS_RD tH_RD_CS tLP_RD RD tD_RD_DB tD_CS_DB tH_CS_DB tDHZ_CS_DB tH_RD_DB x VIN1 VIN2 tD_CS_FD VIN4 VIN3 VIN5 VIN7 VIN6 VIN8 tD_RD_FDL tD_RD_FDH tDHZ_FD 15137-003 DB0 TO DB15 tCYC_RD FRSTDATA Figure 3. Parallel Mode Read Timing Diagram, Separate CS and RD Pulses tCYC_RD tHP_CS CS AND RD tLP_RD DB0 TO DB15 VIN1 tD_CS_FD VIN3 VIN2 tH_CS_DB tDHZ_CS_DB VIN5 VIN4 VIN6 VIN8 VIN7 tDHZ_FD tD_RD_FDL FRSTDATA 15137-004 tD_RD_DB Figure 4. Parallel Mode Read Timing Diagram, Linked CS and RD CS tHP_WR tS_CS_WR tH_WR_CS tCYC_WR WR tLP_WR tH_WR_DB DB0 TO DB15 Figure 5. Parallel Mode Write Operation Timing Diagram Rev. 0 | Page 8 of 69 15137-005 tS_DB_WR Data Sheet AD7606B Serial Mode Timing Specifications Table 5. Parameter fSCLK Min Typ Max Unit 60 40 MHz MHz s ns Description SCLK frequency; fSCLK = 1/tSCLK VDRIVE > 2.7 V VDRIVE < 2.7 V Minimum SCLK period CS to SCLK falling edge setup time tSCLK tS_CS_SCK 1/fSCLK 2 tH_SCK_CS 2 ns SCLK to CS rising edge hold time tLP_SCK tHP_SCK tD_CS_DO 0.4 x tSCLK 0.4 x tSCLK ns ns SCLK low pulse width SCLK high pulse width Delay from CS until DOUTx three-state disabled 9 18 ns ns 15 25 ns ns ns ns ns VDRIVE > 2.7 V VDRIVE < 2.7 V Data out access time after SCLK rising edge VDRIVE > 2.7 V VDRIVE < 2.7 V Data out hold time after SCLK rising edge Data in setup time before SCLK falling edge Data in hold time after SCLK falling edge CS rising edge to DOUTx high impedance 7 22 ns ns ns tD_CS_FD 26 ns VDRIVE > 2.7 V VDRIVE < 2.7 V Time between writing and reading the same register or between two writes; if fSCLK >50 MHz Delay from CS until DOUTx three-state disabled/delay from CS until MSB valid tD_SCK_FDL tDHZ_FD 18 28 ns ns 16th SCLK falling edge to FRSTDATA low CS rising edge until FRSTDATA three-state enabled tD_SCK_DO 25 CS tHP_SCK tS_CS_SCK SCLK tH_SCK_CS tSCLK 1 2 3 14 15 16 tLP_SCK tD_CS_DO DOUTx tD_SCK_DO DB15 DB14 tDHZ_CS_DO tH_SCK_DO DB13 DB2 DB1 DB0 tD_SCK_FDL tD_CS_FD tDHZ_FD 15137-006 tWR 8 8 0 FRSTDATA Figure 6. Serial Timing Diagram, ADC Read Mode (Channel 1) CS tSCLK tS_CS_SCK 1 SCLK 2 tHP_SCK 3 tH_SCK_CS 8 9 16 tLP_SCK tH_SCK_SDI tS_SDI_SCK tWR SDI WEN tD_CS_DO R/W ADD5 ADD0 DIN7 DIN0 tD_SCK_DO DOUTx DOUT7 DOUT0 Figure 7. Serial Interface Timing Diagram, Register Map Read/Write Operations Rev. 0 | Page 9 of 69 15137-007 tH_SCK_DO tS_SDI_SCK tH_SCK_SDI tDHZ_CS_DO AD7606B Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25C, unless otherwise noted. Table 6. Parameter AVCC to AGND VDRIVE to AGND Analog Input Voltage to AGND1 Digital Input Voltage to AGND Digital Output Voltage to AGND REFIN to AGND Input Current to Any Pin Except Supplies1 Operating Temperature Range Storage Temperature Range Junction Temperature Pb/Sn Temperature, Soldering Reflow (10 sec to 30 sec) Pb-Free Temperature, Soldering Reflow Electrostatic Discharge (ESD) All Pins Except Analog Inputs Analog Input Pins Only 1 Rating -0.3 V to +7 V -0.3 V to AVCC + 0.3 V 21 V -0.3 V to VDRIVE + 0.3 V -0.3 V to VDRIVE + 0.3 V -0.3 V to AVCC + 0.3 V 10 mA -40C to +125C -65C to +150C 150C 240 (+0)C 260 (+0)C 3.5 kV 8 kV Transient currents of up to 100 mA do not cause silicon controlled rectifier (SCR) latch-up. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. THERMAL RESISTANCE Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Close attention to PCB thermal design is required. JA is the natural convection junction to ambient thermal resistance measured in a one cubic foot sealed enclosure. JC is the junction to case thermal resistance. Table 7. Thermal Resistance Package Type ST-64-2 1 JA1 40 JC 7 Unit C/W Simulated data based on JEDEC 2s2p thermal test PCB in a JEDEC natural convention environment. ESD CAUTION Rev. 0 | Page 10 of 69 Data Sheet AD7606B V1GND V1 V2GND V2 V3GND V3 V4GND V4 V5GND V5 V6GND V6 V7GND V7 V8GND V8 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 AVCC 1 48 AGND 2 47 AGND OS0 3 46 REFGND AVCC OS1 4 45 REFCAPB OS2 5 44 REFCAPA PAR/SER SEL 6 43 REFGND STBY 7 RANGE 8 CONVST AD7606B TOP VIEW (Not to Scale) 42 REFIN/REFOUT 41 AGND AGND 9 40 WR 10 39 REGCAP RESET 11 38 AVCC RD/SCLK 12 37 AVCC CS 13 36 REGCAP BUSY 14 35 AGND FRSTDATA 15 34 REF SELECT DB0 16 33 DB15 DB14 DB13 DB12 DB11/SDI DB9/DOUTC DB10/D OUTD AGND DB8/DOUTB VDRIVE DB7/DOUTA DB6 DATA OUTPUT DIGITAL OUTPUT DIGITAL INPUT REFERENCE INPUT/OUTPUT 15137-008 ANALOG INPUT DECOUPLING CAPACITOR PIN POWER SUPPLY GROUND PIN DB5 DB4 DB3 DB2 DB1 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Figure 8. Pin Configuration Table 8. Pin Function Description Pin No. 1, 37, 38, 48 Type 1 P Mnemonic AVCC 2, 26, 35, 40, 41, 47 P AGND 3 to 5 DI OS0 to OS2 6 DI PAR/SER SEL 7 DI STBY 8 DI RANGE 9 DI CONVST 10 DI WR Description Analog Supply Voltage, 4.75 V to 5.25 V. This supply voltage is applied to the internal front-end amplifiers and to the ADC core. Decouple these supply pins to AGND. Analog Ground. These pins are the ground reference points for all analog circuitry on the AD7606B. All analog input signals and external reference signals must be referred to these pins. All six of the AGND pins must connect to the AGND plane of a system. Oversampling Mode Pins. These inputs select the oversampling ratio or enable software mode (see Table 12 for oversampling pin decoding). See the Digital Filter section for more details about the oversampling mode of operation. Parallel/Serial Interface Selection Input. If this pin is tied to a logic low, the parallel interface is selected. If this pin is tied to a logic high, the serial interface is selected. See the Digital Interface section for more information on each interface available. Standby Mode Input. In hardware mode, this pin, in combination with the RANGE pin, places the AD7606B in one of two power-down modes: standby mode or shutdown mode. In software mode, this pin is ignored. Therefore, it is recommended to connect this pin to logic high. See the PowerDown Modes section for more information on both hardware mode and software mode. Analog Input Range Selection Input. In hardware mode, this pin determines the input range of the analog input channels (see Table 9). If the STBY pin is at logic low, this pin determines the powerdown mode (see Table 14). In software mode, the RANGE pin is ignored. However, this pin must be tied high or low. Conversion Start Input. When the CONVST pin transitions from low to high, the analog input is sampled on all eight SAR ADCs. In software mode, this pin can be configured as external oversampling clock. Providing a low jitter external clock improves the SNR performance for large oversampling ratios. See the External Oversampling Clock section for further details. Digital Input. In hardware mode, this pin has no function. Therefore, it can be tied high, tied low, or shorted to CONVST. In software mode, this pin is an active low write pin for writing registers using the parallel interface. See the Parallel Interface section for more information. Rev. 0 | Page 11 of 69 AD7606B Data Sheet Pin No. 11 Type 1 DI Mnemonic RESET 12 DI RD/SCLK 13 DI CS 14 DO BUSY 15 DO FRSTDATA 16 to 22 DO/DI DB0 to DB6 23 P VDRIVE 24 DO/DI DB7/DOUTA 25 DO/DI DB8/DOUTB 27 DO/DI DB9/DOUTC 28 DO/DI DB10/DOUTD 29 DO/DI DB11/SDI 30 to 33 DO/DI DB12 to DB15 34 DI REF SELECT 36, 39 P REGCAP 42 REF REFIN/ REFOUT 43, 46 44, 45 REF REF REFGND REFCAPA, REFCAPB 49 50 AI AI GND V1 V1GND Description Reset Input, Active High. Full and partial reset options are available on the AD7606B. The type of reset is determined by the length of the reset pulse. It is recommended that the device receives a full reset pulse after power-up. See the Reset Functionality section for further details. Parallel Data Read Control Input when the Parallel Interface is Selected (RD). Serial Clock Input when the Serial Interface is Selected (SCLK). See the Digital Interface section for more details. Chip Select. This pin is the active low chip select input for ADC data read or register data read and write, in both serial and parallel interface. See the Digital Interface section for more details. Busy Output. This pin transitions to a logic high along with the CONVST rising edge. The BUSY output remains high until the conversion process for all channels is complete. First Data Output. The FRSTDATA output signal indicates when the first channel, V1, is being read back on the parallel interface (see Figure 3) or the serial interface (see Figure 6). See the Digital Interface section for more details. Parallel Output/Input Data Bits. When using parallel interface, these pins act as three-state parallel digital input and output pins (see the Parallel Interface section). When using serial interface, tie these pins to AGND. Logic Power Supply Input. The voltage (1.71 V to 3.6 V) supplied at this pin determines the operating voltage of the interface. This pin is nominally at the same supply as the supply of the host interface, that is, data signal processing (DSP) and field programmable gate array (FPGA). Parallel Output/Input Data Bit 7 (DB7)/Serial Interface Data Output Pin (DOUTA). When using the parallel interface, this pin acts as a three-state parallel digital input/output pin. When using the serial interface, this pin functions as DOUTA. See Table 21 and Table 22 for more details on each data interface and operation mode. Parallel Output/Input Data Bit 8 (DB8)/Serial Interface Data Output Pin (DOUTB). When using the parallel interface, this pin acts as a three-state parallel digital input and output pin. When using the serial interface, this pin functions as DOUTB. See Table 21 and Table 22 for more details on each data interface and operation mode. Parallel Output/Input Data Bit 9 (DB9)/Serial Interface Data Output Pin (DOUTC). When using the parallel interface, this pin acts as a three-state parallel digital input and output pin. When using the serial interface, this pin functions as DOUTC if in software mode and using four data output lines option. See Table 21 and Table 22 for more details on each data interface and operation mode. Parallel Output/Input Data Bit 10 (DB10)/Serial Interface Data Output Pin (DOUTD). When using the parallel interface, this pin acts as a three-state parallel digital input/output pin. When using the serial interface, this pin functions as DOUTD if in software mode and using the four data output lines option. See Table 21 and Table 22 for more details on each data interface and operation mode. Parallel Output/Input Data Bit DB11/Serial Data Input. When using the parallel interface, this pin acts as a three-state parallel digital input and output pin. When using the serial interface in software mode, this pin functions as serial data input. See Table 21 and Table 22 for more details on each data interface and operation mode. Parallel Output/Input Data Bits, DB15 to DB12. When using the parallel interface, these pins act as three-state parallel digital input and output pins (see the Parallel Interface section). When using the serial interface, tie these pins to AGND. Internal/External Reference Selection Logic Input. If this pin is set to logic high, the internal reference is selected and enabled. If this pin is set to logic low, the internal reference is disabled and an external reference voltage must be applied to the REFIN/REFOUT pin. Decoupling Capacitor Pins for Voltage Output from 1.9 V Internal Regulator, Analog Low Dropout (ALDO) and Digital Low Dropout (DLDO). These output pins must be decoupled separately to AGND using a 1 F capacitor. Reference Input (REFIN)/Reference Output (REFOUT). The internal 2.5 V reference is available on the REFOUT pin for external use while the REF SELECT pin is set to logic high. Alternatively, by setting the REF SELECT pin to logic low, the internal reference is disabled and an external reference of 2.5 V must be applied to this input (REFIN). A 100 nF capacitor must be applied from the REFIN pin to ground, close to the REFGND pins, for both internal and external reference options. See the Reference section for more details. Reference Ground Pins. These pins must be connected to AGND. Reference Buffer Output Force/Sense Pins. These pins must be connected together and decoupled to AGND using a low effective series resistance (ESR), 10 F ceramic capacitor. The voltage on these pins is typically 4.4 V. Channel 1 Positive Analog Input Pin. Channel 1 Negative Analog Input Pin. Rev. 0 | Page 12 of 69 Data Sheet Pin No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 Type 1 AI AI GND AI AI GND AI AI GND AI AI GND AI AI GND AI AI GND AI AI GND AD7606B Mnemonic V2 V2GND V3 V3GND V4 V4GND V5 V5GND V6 V6GND V7 V7GND V8 V8GND Description Channel 2 Positive Analog Input Pin. Channel 2 Negative Analog Input Pin. Channel 3 Positive Analog Input Pin. Channel 3 Negative Analog Input Pin. Channel 4 Positive Analog Input Pin. Channel 4 Negative Analog Input Pin. Channel 5 Positive Analog Input Pin. Channel 5 Negative Analog Input Pin. Channel 6 Positive Analog Input Pin. Channel 6 Negative Analog Input Pin. Channel 7 Positive Analog Input Pin. Channel 7 Negative Analog Input Pin. Channel 8 Positive Analog Input Pin. Channel 8 Negative Analog Input Pin. P is power supply, DI is digital input, DO is digital output, REF is reference input/output, AI is analog input, and GND is ground. Rev. 0 | Page 13 of 69 AD7606B Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS -40 -60 -40 -80 -100 -120 -60 -80 -100 -120 -140 -140 -160 -160 0.1 1 10 100 INPUT FREQUENCY (kHz) -180 0.1 15137-009 -180 AVCC = 5V, VDRIVE = 3.3V INTERNAL REFERENCE 5V RANGE fSAMPLE = 800kSPS fIN = 1kHz 32768 POINT FFT SNR = 88.3dB THD = -103dB -20 AMPLITUDE (dB) -20 Figure 12. FFT, 5 V Range 0 0 AVCC = 5V, VDRIVE = 3.3V INTERNAL REFERENCE 2.5V RANGE fSAMPLE = 800kSPS fIN = 1kHz 32768 POINT FFT SNR = 86dB THD = -98.5dB -60 -40 -60 -80 -100 -120 -80 -100 -120 -140 -140 -160 -160 -180 1 10 100 INPUT FREQUENCY (kHz) -200 15137-010 -180 0.1 0 0.5 0.5 DNL (LSB) 1.0 0 -0.5 -1.0 -1.0 -1.5 -1.5 20000 30000 40000 50000 ADC CODE 25 0 -0.5 10000 20 AVCC = 5V, VDRIVE = 3.3V INTERNAL REFERENCE fSAMPLE = 800kSPS T = 25C 1.5 60000 -2.0 15137-311 INL (LSB) 2.0 1.0 0 15 Figure 13. FFT Oversampling by 16, 10 V Range AVCC = 5V, VDRIVE = 3.3V INTERNAL REFERENCE fSAMPLE = 800kSPS T = 25C 1.5 10 INPUT FREQUENCY (kHz) Figure 10. FFT, 2.5 V Range 2.0 5 15137-013 AMPLITUDE (dB) -40 AVCC = 5V, VDRIVE = 3.3V INTERNAL REFERENCE 10V RANGE fSAMPLE = 800kSPS fIN = 146Hz 8192 POINT FFT SNR = 93.6dB THD = -110dB -20 AMPLITUDE (dB) -20 100 INPUT FREQUENCY (kHz) Figure 9. Fast Fourier Transform (FFT), 10 V Range -2.0 10 1 0 10000 20000 30000 40000 ADC CODE Figure 11. Typical INL, 10 V Range Figure 14. Typical DNL Rev. 0 | Page 14 of 69 50000 60000 15137-316 AMPLITUDE (dB) 0 AVCC = 5V, VDRIVE = 3.3V INTERNAL REFERENCE 10V RANGE fSAMPLE = 800kSPS fIN = 1kHz 32768 POINT FFT SNR = 89.2dB THD = -108.3dB 15137-012 0 Data Sheet AD7606B 94 96 94 SNR (dB) 92 98 90 88 84 INTERNAL REFERENCE T = 25C 10V RANGE 82 80 0.01 1 0.1 10 100 INPUT FREQUENCY (kHz) Figure 15. SNR vs. Input Frequency for Different OSR Values, 10 V Range, Internal OS Clock 100 96 92 1 10 100 98 96 94 90 88 92 90 88 NO OS OS BY 2 OS BY 4 OS BY 8 OS BY 16 OS BY 32 OS BY 64 OS BY 128 OS BY 256 86 AVCC = 5V, VDRIVE = 3.3V fSAMPLE = 800kSPS/OSR INTERNAL REFERENCE T = 25C 5V RANGE 84 82 1 0.1 10 100 INPUT FREQUENCY (kHz) Figure 16. SNR vs. Input Frequency for Different OSR Values, 5 V Range, Internal OS Clock 100 96 94 INTERNAL REFERENCE T = 25C 5V RANGE 0.1 1 10 Figure 19. SNR vs. Input Frequency for Different OSR Values, 5 V Range, External OS Clock 100 95 SNR (dB) 92 90 88 90 NO OS OS BY 2 OS BY 4 OS BY 8 OS BY 16 OS BY 32 OS BY 64 OS BY 128 OS BY 256 86 82 85 AVCC = 5V, VDRIVE = 3.3V fSAMPLE = 800kSPS/OSR INTERNAL REFERENCE T = 25C 2.5V RANGE 80 0.01 0.1 1 INPUT FREQUENCY (kHz) 10 100 Figure 17. SNR vs. Input Frequency for Different OSR Values, 2.5 V Range, Internal OS Clock AVCC = 5V, VDRIVE = 3.3V fSAMPLE = 800kSPS/OSR INTERNAL REFERENCE T = 25C 2.5V RANGE 80 0.01 15137-035 84 100 INPUT FREQUENCY (kHz) NO OS OS BY 2 OS BY 4 OS BY 8 OS BY 16 OS BY 32 OS BY 64 OS BY 128 OS BY 256 98 AVCC = 5V, VDRIVE = 3.3V fSAMPLE = 800kSPS/OSR 80 0.01 15137-031 80 0.01 100 Figure 18. SNR vs. Input Frequency for Different OSR Values, 10 V Range, External OS Clock 86 SNR (dB) 0.1 INPUT FREQUENCY (kHz) SNR (dB) SNR (dB) 94 82 NO OS OS BY 2 OS BY 4 OS BY 8 OS BY 16 OS BY 32 OS BY 64 OS BY 128 OS BY 256 AVCC = 5V, VDRIVE = 3.3V fSAMPLE = 800KSPS/OSR INTERNAL REFERENCE T = 25C 10V RANGE 80 0.01 NO OS OS BY 2 OS BY 4 OS BY 8 OS BY 16 OS BY 32 OS BY 64 OS BY 128 OS BY 256 98 84 88 AVCC = 5V, VDRIVE = 3.3V fSAMPLE = 800kSPS/OSR 15137-415 82 90 86 86 84 92 15137-034 96 15137-032 98 SNR (dB) 100 NO OS OS BY 2 OS BY 4 OS BY 8 OS BY 16 OS BY 32 OS BY 64 OS BY 128 OS BY 256 0.1 1 INPUT FREQUENCY (kHz) 10 100 15137-036 100 Figure 20. SNR vs. Input Frequency for Different OSR Values, 2.5 V Range, External OS Clock Rev. 0 | Page 15 of 69 AD7606B Data Sheet 91 -60 AVCC = 5V VDRIVE = 3.3V fSAMPLE = 800kSPS 90 -70 10V RANGE fSAMPLE = 800kSPS RSOURCE MATCHED ON Vx AND VxGND 89 THD (dB) 88 87 -90 -100 0 1.2k 5k 10k 23.7k 48.7k 105k 86 84 -40 -110 2.5V 5V 10V -20 20 0 40 60 80 100 120 TEMPERATURE (C) -120 0.01 15137-333 85 1 10 100 INPUT FREQUENCY (kHz) Figure 21. SNR vs. Temperature Figure 24. THD vs. Input Frequency for Various Source Impedances, 10 V Range 2.505 -60 AVCC = 5V, VDRIVE = 3.3V f = 800kSPS 2.504 SAMPLE T = 25C -70 2.503 2.502 0 1.2k 5k 10k 23.7k 48.7k 105k 5V RANGE fSAMPLE = 800kSPS RSOURCE MATCHED ON Vx AND VxGND -80 2.501 THD (dB) REFERENCE VOLTAGE (V) 0.1 15137-326 SNR (dB) -80 2.500 2.499 -90 -100 2.498 2.497 -110 -20 0 20 40 60 80 100 120 TEMPERATURE (C) -120 0.01 15137-343 2.495 -40 1 10 100 INPUT FREQUENCY (kHz) Figure 22. Reference Drift Figure 25. THD vs. Input Frequency for Various Source Impedances, 5 V Range 25 -60 -70 20 0 1.2k 5k 10k 23.7k 48.7k 105k 2.5V RANGE fSAMPLE = 800kSPS RSOURCE MATCHED ON Vx AND VxGND -80 THD (dB) 15 10 -90 -100 5 -5 0 5 REFERENCE DRIFT (ppm/C) 10 Figure 23. Reference Drift Histogram -120 0.01 0.1 1 INPUT FREQUENCY (kHz) 10 100 15137-330 0 -10 -110 15137-423 NUMBER OF HITS 0.1 15137-327 2.496 Figure 26. THD vs. Input Frequency for Various Source Impedances, 2.5 V Range Rev. 0 | Page 16 of 69 Data Sheet NFS CH1 NFS CH3 NFS CH5 NFS CH7 PFS CH1 PFS CH3 PFS CH5 PFS CH7 PFS/NFS ERROR (LSB) 20 10 45 NFS CH2 NFS CH4 NFS CH6 NFS CH8 PFS CH2 PFS CH4 PFS CH6 PFS CH8 40 35 NUMBER OF HITS 30 AD7606B 0 -10 30 25 20 15 10 -20 0 20 40 60 80 100 120 TEMPERATURE (C) 0 -10 Figure 27. Positive Full-Scale(PFS)/Negative Full-Scale (NFS) Error vs. Temperature, 10 V Range NFS CH1 NFS CH3 NFS CH5 NFS CH7 PFS CH1 PFS CH3 PFS CH5 PFS CH7 20 10 40 35 5 0 -5 -10 30 25 20 15 -15 10 -20 5 -25 -40 -20 0 20 40 10 45 NFS CH2 NFS CH4 NFS CH6 NFS CH8 PFS CH2 PFS CH4 PFS CH6 PFS CH8 60 80 120 100 TEMPERATURE (C) 15137-321 PFS/NFS ERROR (LSB) 15 5 Figure 30. PFS/NFS Drift Histogram, External Reference NUMBER OF HITS 25 0 NFS DRIFT (ppm/C) -5 15137-430 -20 0 -10 Figure 28. PFS/NFS Error vs. Temperature, 5 V Range 0 NFS DRIFT (ppm/C) -5 5 10 15137-431 -30 -40 15137-320 5 Figure 31. PFS/NFS Drift Histogram, Internal Reference 20 -40 10V RANGE 5V RANGE 2.5V RANGE 15 -50 5 AC PSRR (dB) -60 0 -5 -15 -20 -25 -40 -20 NFS CH1 NFS CH2 NFS CH3 NFS CH4 NFS CH5 NFS CH6 NFS CH7 NFS CH8 PFS CH2 PFS CH1 PFS CH4 PFS CH3 PFS CH6 PFS CH5 PFS CH8 PFS CH7 0 20 40 -70 -80 -90 60 80 100 120 TEMPERATURE (C) AVCC = 5V, VDRIVE = 3.3V INTERNAL REFERENCE RECOMMENDED DECOUPLING USED fSAMPLE = 800kSPS T = 25C -100 0.1 1 10 AVCC NOISE FREQUENCY (kHz) Figure 29. PFS/NFS Error vs. Temperature, 2.5 V Range Figure 32. AC PSRR Rev. 0 | Page 17 of 69 100 15137-042 -10 15137-324 PFS/NFS ERROR (LSB) 10 AD7606B 1000 1.2 0 -1.2 -2.4 782 800 600 458 400 246 -3.6 -20 0 20 40 60 80 100 120 TEMPERATURE (C) 91 0 32765 32766 4.8 2000 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 1800 2.4 0 -2.4 1400 878 800 400 AVCC = 5V, VDRIVE = 3.3V INTERNAL REFERENCE fSAMPLE = 800kSPS -20 0 20 40 60 80 100 120 TEMPERATURE (C) 177 200 0 32765 32767 32766 32768 32769 1800 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 1600 1400 4.8 0 -4.8 Vx AND VxGND SHORTED TOGETHER T = 25C 4096 SAMPLES MEAN = 32767.5 SIGMA = 0.8 1667 32771 32772 1702 1200 1000 800 600 -9.6 415 400 -14.4 281 AVCC = 5V, VDRIVE = 3.3V INTERNAL REFERENCE fSAMPLE = 800kSPS -20 0 20 40 60 80 100 120 TEMPERATURE (C) 200 23 8 15137-024 -19.2 -24.0 -40 32770 Figure 37. Histogram of Codes, 5 V Range NUMBER OF HITS 9.6 119 6 ADC CODE Figure 34. Bipolar Zero Code Error vs. Temperature, 5 V Range 14.4 Vx AND VxGND SHORTED TOGETHER T = 25C 4096 SAMPLES MEAN = 32767.8 SIGMA = 0.92 600 -9.6 19.2 32771 32772 1000 -7.2 24.0 32770 1182 1200 -4.8 -12.0 -40 1727 1600 NUMBER OF HITS 7.2 32769 Figure 36. Histogram of Codes, 10 V Range 15137-023 BIPOLAR ZERO CODE ERROR (LSB) 9.6 32768 ADC CODE Figure 33. Bipolar Zero Code Error vs. Temperature, 10 V Range 12.0 32767 15137-039 -6.0 -40 200 AVCC = 5V, VDRIVE = 3.3V INTERNALREFERENCE fSAMPLE = 800kSPS -4.8 BIPOLAR ZERO CODE ERROR (LSB) 1303 1163 15137-037 2.4 Vx AND VxGND SHORTED TOGETHER T = 25C 4096 SAMPLES MEAN = 32767.8 SIGMA = 1.2 0 32765 32766 32767 32768 32769 32770 32771 ADC CODE Figure 38. Histogram of Codes, 2.5 V Range Figure 35. Bipolar Zero Code Error vs. Temperature, 2.5 V Range Rev. 0 | Page 18 of 69 32772 15137-038 3.6 1200 15137-022 BIPOLAR ZERO CODE ERROR (LSB) 4.8 1400 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8 NUMBER OF HITS 6.0 Data Sheet Data Sheet 50 4 2 0 -2 -4 10V 5V 2.5V -6 -4 -2 0 2 4 6 8 35 30 25 20 15 10 AVCC = 5V, VDRIVE = 3.3V INTERNAL REFERENCE T = 25C 10 INPUT VOLTAGE (V) 0 0 -50 35 30 25 20 15 10 AVCC = 5V, VDRIVE = 3.3V INTERNAL REFERENCE T = 25C 0 100 200 300 400 500 600 700 THROUGHPUT RATE (kSPS) 800 15137-440 AVCC SUPPLY CURRENT (mA) CHANNEL TO CHANNEL ISOLATION (dB) T = -40C T = +25C T = +125C 40 0 1000 800 Figure 41. AVCC Supply Current vs. Throughput Rate 50 5 600 THROUGHPUT RATE (kSPS) Figure 39. Analog Input Current vs. Input Voltage 45 400 200 AVCC = 5V,VDRIVE = 3.3V INTERNAL REFERENCE fSAMPLE = 800kSPS T = 25C INTERFERER IN ALL UNSELECTED CHANNELS 10V RANGE 5V RANGE 2.5V RANGE -60 -70 -80 -90 -100 -110 -120 -130 -140 0 20 40 60 80 100 120 140 160 NOISE FREQUENCY (kHz) Figure 42. Channel to Channel Isolation vs. Noise Frequency Figure 40. AVCC Supply Current vs. Throughput Rate Rev. 0 | Page 19 of 69 15137-043 -8 40 5 15137-341 -6 -10 NORMAL MODE AUTOSTANDBY MODE 45 15137-441 AVCC = 5V, VDRIVE = 3.3V fSAMPLE = 800kSPS T = 25C AVCC SUPPLY CURRENT (mA) ANALOG INPUT CURRENT (A) 6 AD7606B AD7606B Data Sheet TERMINOLOGY Integral Nonlinearity (INL) INL is the maximum deviation from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale at 1/2 LSB below the first code transition and full scale at 1/2 LSB above the last code transition. Differential Nonlinearity (DNL) DNL is the difference between the measured and the ideal 1 LSB change between any two adjacent codes in the ADC. Bipolar Zero Code Error Bipolar zero code error is the deviation of the midscale transition (all 1s to all 0s) from the ideal, which is 0 V - 1/2 LSB. The ratio depends on the number of quantization levels in the digitization process: the more levels, the smaller the quantization noise. The theoretical SINAD for an ideal N-bit converter with a sine wave input is given by SINAD = (6.02 N + 1.76) (dB) Thus, for a 16-bit converter, the SINAD is 98 dB. Total Harmonic Distortion (THD) THD is the ratio of the rms sum of the harmonics to the fundamental. For the AD7606B, THD is defined as THD (dB) = Bipolar Zero Code Error Match Bipolar zero code error match is the absolute difference in bipolar zero code error between any two input channels. 20log Open Circuit Code Error Open circuit code error is the ADC output code when there is an open circuit on the analog input, and a pull-down resistor (RPD) connected between the analog input pair of pins. See Figure 59 for more details. Positive Full-Scale (PFS) Error PFS error is the deviation of the actual last code transition from the ideal last code transition (10 V - 11/2 LSB (9.99954), 5 V - 11/2 LSB (4.99977), and 2.5 V - 11/2 LSB (2.49988)) after the bipolar zero code error is adjusted out. The positive full-scale error includes the contribution from the internal reference and reference buffer. Positive Full-Scale Error Match PFS error match is the absolute difference in positive full-scale error between any two input channels. Negative Full-Scale (NFS) Error NFS error is the deviation of the first code transition from the ideal first code transition (-10 V + 1/2 LSB (-9.99984), -5 V + 1/2 LSB (-4.99992), and -2.5 V + 1/2 LSB (-2.49996)) after the bipolar zero code error is adjusted out. The negative full-scale error includes the contribution from the internal reference and reference buffer. Negative Full-Scale Error Match NFS error match is the absolute difference in negative full-scale error between any two input channels. Total Unadjusted Error (TUE) TUE is the maximum deviation of the output code from the ideal. TUE includes INL errors, bipolar zero code and positive and negative full-scale errors, and reference errors. Signal-to-Noise-and-Distortion Ratio (SINAD) SINAD ratio is the measured ratio of signal-to-noise-anddistortion at the output of the ADC. The signal is the rms amplitude of the fundamental. Noise is the sum of all nonfundamental signals up to half the sampling frequency (fS/2, excluding dc). V22 + V32 + V4 2 + V52 + V62 + V7 2 + V82 + V92 V1 where: V1 is the rms amplitude of the fundamental. V2 to V9 are the rms amplitudes of the second through ninth harmonics. Peak Harmonic or Spurious Noise Peak harmonic or spurious noise is the ratio of the rms value of the next largest component in the ADC output spectrum (up to fS/2, excluding dc) to the rms value of the fundamental. Normally, the value of this specification is determined by the largest harmonic in the spectrum, but for ADCs where the harmonics are buried in the noise floor, the value is determined by a noise peak. Power Supply Rejection Ratio (PSRR) Variations in power supply affect the full-scale transition but not the linearity of the converter. The power supply rejection (PSR) is the maximum change in full-scale transition point due to a change in power supply voltage from the nominal value. The PSRR is defined as the ratio of the 100 mV p-p sinewave applied to the AVCC supplies of the ADC frequency, fS, to the power of the ADC output at that frequency, fS. PSRR (dB) = 20 log (0.1/PfS) where: PfS is equal to the power at frequency, fS, coupled on the AVCC supply. Channel to Channel Isolation Channel to channel isolation is a measure of the level of crosstalk between all input channels. It is measured by applying a full-scale sine wave signal, up to 160 kHz, to all unselected input channels and then determining the degree to which the signal attenuates in the selected channel with a 1 kHz sine wave signal applied (see Figure 42). Rev. 0 | Page 20 of 69 Data Sheet AD7606B Phase Delay Phase delay is a measure of the absolute time delay between when an input is sampled by the converter and when the result associated with that sample is available to be read back from the ADC, including delay induced by the analog front end of the device. Phase Delay Drift Phase delay drift is the change in phase delay per unit temperature across the entire operating temperature of the device. Phase Delay Matching Phase delay matching is the maximum phase delay seen between any simultaneously sampled pair. Rev. 0 | Page 21 of 69 AD7606B Data Sheet THEORY OF OPERATION ANALOG FRONT END 21 V, no current flows in the clamp circuit. For input voltages that are above 21 V, the AD7606B clamp circuitry turns on. 15 Analog Input Ranges A logic change on the RANGE pin has an immediate effect on the analog input range. However, there is typically a settling time of approximately 80 s in addition to the normal acquisition time requirement. Changing the RANGE pin during a conversion is not recommended for fast throughput rate applications. In software mode, it is possible to configure an individual analog input range per channel using Address 0x03 through Address 0x06. The logic level on the RANGE pin is ignored in software mode. RANGE pin low 2.5 Not applicable Software Mode2 Address 0x03 through Address 0x06 Address 0x03 through Address 0x06 Address 0x03 through Address 0x06 Analog Input Impedance The analog input impedance of the AD7606B is typically 5 M. This is a fixed input impedance that does not vary with the AD7606B sampling frequency. This high analog input impedance eliminates the need for a driver amplifier in front of the AD7606B, allowing direct connection to the source or sensor. Therefore, bipolar supplies can be removed from the signal chain. Analog Input Clamp Protection Figure 43 shows the analog input circuitry of the AD7606B. Each analog input of the AD7606B contains clamp protection circuitry. Despite single, 5 V supply operation, this analog input clamp protection allows an input overvoltage of up to 21 V. CLAMP 5M 16-BIT SAR ADC 5M 15137-047 CLAMP LPF Figure 43. Analog Input Circuitry for Each Channel -10 -15 -30 -10 -20 0 10 20 30 It is recommended to place a series resistor on the analog input channels to limit the current to 10 mA for input voltages greater than 21 V. In an application where there is a series resistance (R) on an analog input channel, Vx, it is recommended to match the resistance (R) with the resistance on VxGND to eliminate any offset introduced to the system, as shown in Figure 45. However, in software mode, there is a per channel system offset calibration that removes the offset of the full system (see the System Offset Calibration section). The same analog input range, 10 V or 5 V, applies to all eight channels. 2 The analog input range (10 V, 5 V, or 2.5 V) is selected on a per channel basis using the memory map. VxGND -5 Figure 44. Input Protection Clamp Profile 1 Vx 0 During normal operation, it is not recommended to leave the AD7606B in a condition where the analog input is greater than the input range for extended periods of time because this can degrade the bipolar zero code error performance. In shutdown or standby mode, there is no such concern. AD7606B R R C Vx VxGND CLAMP CLAMP 5M 5M 15137-049 5 5 SOURCE VOLTAGE (V) Table 9. Analog Input Range Selection Hardware Mode1 RANGE pin high INPUT CLAMP CURRENT (mA) 10 The AD7606B can handle true bipolar, single-ended input voltages. In hardware mode, the logic level on the RANGE pin determines either 10 V or 5 V as the analog input range of all analog input channels, as shown in Table 9. Range (V) 10 TA = -40C TA = +25C TA = +125C 15137-248 The AD7606B is a 16-bit, simultaneous sampling, analog-todigital DAS with eight channels. Each channel contains analog input clamp protection, a PGA, a low-pass filter, and a 16-bit SAR ADC. Figure 45. Input Resistance Matching on the Analog Input of the AD7606B PGA A PGA is provided at each input channel. The gain is configured depending on the analog input range selected (see Table 9) to scale the single-ended analog input signal to the ADC fully differential input range. Input impedance on each input of the PGA is accurately trimmed to maintain the overall gain error. This trimmed value is then used when the gain calibration is enabled to compensate for the gain error introduced by an external series resistor. See the System Gain Calibration section for more information on the PGA feature. Figure 44 shows the input clamp current vs. the source voltage characteristic of the clamp circuit. For input voltages of up to Rev. 0 | Page 22 of 69 Data Sheet AD7606B Analog Input Antialiasing Filter An analog antialiasing filter is provided on the AD7606B. Figure 46 and Figure 47 show the frequency response and phase response, respectively, of the analog antialiasing filter. In the 10 V range, the -3 dB frequency is typically 22.5 kHz. The AD7606B contains an on-chip oscillator that performs the conversions. The conversion time for all ADC channels is tCONV (see Table 3). In software mode, there is an option to apply an external clock through the CONVST pin. Providing a low jitter external clock improves SNR performance for large oversampling ratios. See the Digital Filter section and Figure 15 to Figure 20 for further information. ATTENUATION (dB) Connect all unused analog input channels to AGND. The results for any unused channels are still included in the data read because all channels are always converted. ADC Transfer Function 100 1k 10k 100k INPUT FREQUENCY (Hz) 15137-050 10V RANGE 5V RANGE 2.5V RANGE The output coding of the AD7606B is twos complement. The designed code transitions occur midway between successive integer LSB values, that is, 1/2 LSB and 3/2 LSB. The LSB size is FSR/65,536 for the AD7606B. The ideal transfer characteristics for the AD7606B are shown in Figure 48. The LSB size is dependent on the analog input range selected, as shown in Table 10. 10V CODE = Figure 46. Analog Antialiasing Filter Frequency Response 16 5V CODE = 10V 5V 2.5V 14 2.5V CODE = Vx x 32,768 5V Vx 2.5V x 32,768 10 8 6 000...001 000...000 111...111 LSB = PFS - (NFS) 2N* 100...010 100...001 100...000 NFS + 1/2LSB 0v - 1/2LSB PFS - 3/2LSB 4 AVCC = 5V, VDRIVE = 3.3V fSAMPLE = 800kSPS T = 25C 1k Figure 48. Ideal Transfer Characteristics 10k 100k INPUT FREQUENCY (Hz) 15137-051 0 100 ANALOG INPUT 15137-052 ADC CODE PHASE DELAY (s) x 32,768 011...111 011...110 12 2 Vx 10V Table 10. Input Voltage Ranges Figure 47. Analog Antialiasing Filter Phase Response SAR ADC The AD7606B allows the ADC to accurately acquire an input signal of full-scale amplitude to 16-bit resolution. All eight SAR ADCs sample the respective inputs simultaneously on the rising edge of the CONVST signal. The BUSY signal indicates when conversions are in progress. Therefore, when the rising edge of the CONVST signal is applied, the BUSY pin goes logic high and transitions low at the end of the entire conversion process. The end of the conversion process across all eight channels is indicated by the falling edge of the BUSY signal. When the BUSY signal edge falls, the acquisition time for the next set of conversions begins. The rising edge of the CONVST signal has no effect while the BUSY signal is high. New data can be read from the output register via the parallel or serial interface after the BUSY output goes low. Alternatively, data from the previous conversion can be read while the BUSY pin is high, as explained in the Reading During Conversion section. Range (V) 10 5 2.5 PFS (V) +10 +5 +2.5 Midscale (V) 0 0 0 NFS (V) -10 -5 -2.5 LSB (V) 305 152 76 REFERENCE The AD7606B contains an on-chip, 2.5 V, band gap reference. The REFIN/REFOUT pin allows either Access to the internal 2.5 V reference, if the REF SELECT pin is tied to logic high. Application of an external reference of 2.5 V, if the REF SELECT pin is tied to logic low. Table 11. Reference Configuration REF SELECT Pin Logic High Logic Low Rev. 0 | Page 23 of 69 Reference Selected Internal reference enabled Internal reference disabled; an external 2.5 V reference voltage must be applied to the REFIN/REFOUT pin AD7606B Data Sheet When the AD7606B is configured in external reference mode, the REFIN/REFOUT pin is a high input impedance pin. REFIN/REFOUT REFCAPA REFCAPB Using Multiple AD7606B Devices For applications using multiple AD7606B devices, the following configurations are recommended, depending on the application requirements. External Reference Mode One external reference can drive the REFIN/REFOUT pins of all AD7606B devices (see Figure 50). In this configuration, decouple each REFIN/REFOUT pin of the AD7606B with at least a 100 nF decoupling capacitor. AD7606B REF SELECT REFIN/REFOUT REFIN/REFOUT 100nF 100nF REF SELECT REFIN/REFOUT REFIN/REFOUT REFIN/REFOUT + 10F 100nF 100nF Figure 51. Internal Reference Driving Multiple AD7606B REFIN/REFOUT Pins OPERATION MODES The AD7606B can be operated in hardware or software mode by controlling the OSx pins (Pin 3, Pin 4, and Pin 5), described in Table 12. REF SELECT Table 12. Oversampling Pin Decoding OSx Pins 000 001 010 011 100 101 110 111 REFIN/REFOUT 100nF REF 1F 15137-054 AD7606B REF SELECT AD7606B REF SELECT The reference and the data interface is selected using the REF SELECT and PAR/SER SEL pins, in both hardware and software modes. Figure 49. Reference Circuitry AD7606B AD7606B REF SELECT In software mode, that is, when all three OSx pins are connected to logic high level, the AD7606B is configured by the corresponding registers accessed via the serial or parallel interface. Additional features are available, as described in Table 13. 10F 15137-053 2.5V REF AD7606B In hardware mode, the AD7606B is configured depending on the logic level on the RANGE, OSx, or STBY pins. SAR BUF VDRIVE 15137-055 The AD7606B contains a reference buffer configured to gain the reference voltage up to approximately 4.4 V, as shown in Figure 49. The 4.4 V buffered reference is the reference used by the SAR ADC, as shown in Figure 49. After a reset, the AD7606B operates in the reference mode selected by the REF SELECT pin. The REFCAPA and REFCAPB pins must be shorted together externally, and a ceramic capacitor of 10 F must be applied to the REFGND pin to ensure that the reference buffer is in closedloop operation. A 10 F ceramic capacitor is required on the REFIN/REFOUT pin. Figure 50. Single External Reference Driving Multiple AD7606B REFIN/REFOUT Pins Internal Reference Mode One AD7606B device, configured to operate in internal reference mode, can drive the remaining AD7606B devices, which are configured to operate in external reference mode (see Figure 51). Decouple the REFIN/REFOUT pin of the AD7606B, configured in internal reference mode, using a 10 F ceramic decoupling capacitor. The other AD7606B devices, configured in external reference mode, must use at least a 100 nF decoupling capacitor on their REFIN/REFOUT pins. Rev. 0 | Page 24 of 69 AD7606B No OS 2 4 8 16 32 64 Enters software mode Data Sheet AD7606B Table 13. Functionality Matrix Parameter Analog Input Range 1 System Gain, Phase, and Offset Calibration OSR Analog Input Open Circuit Detection Serial Data Output Lines Diagnostics Power-Down Modes 1 2 3 Hardware Mode 10 V or 5 V 2 Not accessible From no OS to OSR = 64 Not accessible 2 Not accessible Standby and shutdown See Table 9 for the analog input range selection. Same input range configured in all input channels. On a per channel basis. Rev. 0 | Page 25 of 69 Software Mode 10 V, 5 V, or 2.5 V 3 Available3 From no OS to OSR = 256 Available3 Selectable: 1, 2, or 4 Available Standby, shutdown, and autostandby AD7606B Data Sheet Reset Functionality Table 14. Power-Down Mode Selection, Hardware Mode The AD7606B has two reset modes: full or partial. The reset mode selected is dependent on the length of the reset high pulse. A partial reset requires the RESET pin to be held high between 55 ns and 2 s. After 50 ns from the release of the RESET pin (tDEVICE_SETUP, partial reset), the device is fully functional and a conversion can be initiated. A full reset requires the RESET pin to be held high for a minimum of 3 s. After 253 s (tDEVICE_SETUP, full reset) from the release of the RESET pin, the device is completely reconfigured and a conversion can be initiated. Power Mode Normal Mode Standby Shutdown A partial reset reinitializes the following modules: X = don't care. In software mode, the power-down mode is selected through the OPERATION_MODE bits on the CONFIG register (Address 0x02, Bits[1:0]) within the memory map. There is an extra power-down mode available in software mode called autostandby mode. Table 15. Power-Down Mode Selection, Software Mode, Through CONFIG Register (Address 0x02) Digital filter. SPI and parallel, resetting to ADC mode. SAR ADCs. CRC logic. After the partial reset, the RESET_DETECT bit of the status register asserts (Address 0x01, Bit 7).The current conversion result is discarded after the completion of a partial reset. The partial reset does not affect the register values programmed in software mode or the latches that store the user configuration in both hardware and software modes. A full reset returns the device to the default power-on state, the RESET_DETECT bit of the status register asserts (Address 0x01, Bit 7), and the current conversion result is discarded. The following features, in addition to those listed previously, are configured when the AD7606B is released from full reset: * * RANGE Pin X1 1 0 Hardware mode or software mode. Interface type (serial or parallel). Power-Down Modes In hardware mode, two power-down modes are available on the AD7606B: standby mode and shutdown mode. The STBY pin controls whether the AD7606B is in normal mode or in one of the two power-down modes, as shown in Table 14. If the STBY pin is low, the power-down mode is selected by the state of the RANGE pin. Operation Mode Normal Standby Autostandby Shutdown Address 0x02, Bit 1 0 0 1 1 Address 0x02, Bit 0 0 1 0 1 When the AD7606B is placed in shutdown mode, all circuitry is powered down and the current consumption reduces to 5 A, maximum. The power-up time is approximately 10 ms. When the AD7606B is powered up from shutdown mode, a full reset must be applied to the AD7606B after the required power-up time elapses. When the AD7606B is placed in standby mode, all the PGAs and all the SAR ADCs enter a low power mode, such that the overall current consumption reduces to 4.5 mA, maximum. No reset is required after exiting standby mode. When the AD7606B is placed in autostandby mode, available only in software mode the device automatically enters standby mode on the BUSY signal falling edge. The AD7606B exits standby mode automatically on the CONVST signal rising edge. Therefore, the CONVST signal low pulse time is longer than tWAKE_UP (standby mode) = 1 s. CONVST BUSY POWER MODE STANDBY NORMAL STANDBY tWAKE_UP Figure 52. Autostandby Mode Operation Rev. 0 | Page 26 of 69 15137-056 * * * * 1 STBY Pin 1 0 0 Data Sheet AD7606B The AD7606B contains an optional digital averaging filter that can be enabled in slower throughput rate applications that require higher SNR or dynamic range. In hardware mode, the oversampling ratio of the digital filter is controlled using the oversampling pins, OSx, as shown in Table 12. The OSx pins are latched on the falling edge of the BUSY signal. In software mode, that is, if all OSx pins are tied to logic high, the oversampling ratio is selected through the oversampling register (Address 0x08). Two additional oversampling ratios (OS x 128 and OS x 256) are available in software mode. In oversampling mode, the ADC takes the first sample for each channel on the rising edge of the CONVST signal. After converting the first sample, the subsequent samples are taken by the internally generated sampling signal, as shown in Figure 53. Alternatively, this sampling signal can be applied externally as described in the External Oversampling Clock section. For example, if oversampling by eight is configured, eight samples are taken, averaged, and the result is provided on the output. A CONVST signal rising edge triggers the first sample, and the remaining seven samples are taken with an internally generated sampling signal. Consequently, turning on the averaging of multiple samples leads to an improvement in SNR performance, at the expense of reducing the maximum throughput rate. When the oversampling function is turned on, the BUSY signal high time (tCONV) extends, as shown in Table 3. Table 16 shows the trade-off in SNR vs. bandwidth and throughput for the 10 V, 5 V, and 2.5 V ranges. tCYCLE CONVST OS CLOCK BUSY tCONV CS RD DATA: DB0 TO DB15 15137-057 DIGITAL FILTER Figure 53. Oversampling by 8 Example, Read After Conversion, Parallel Interface, OS Clock Internally Generated Sampling Signal Figure 53 shows that the conversion time (tCONV) extends when oversampling is turned on. The throughput rate (1/tCYCLE) must be reduced to accommodate the longer conversion time and to allow the read operation to occur. To achieve the fastest throughput rate possible when oversampling is turned on, the read can be performed during the BUSY signal high time as explained in the Reading During Conversion section. Table 16. Oversampling Performance OS Ratio No OS 2 4 8 16 32 64 1281 2561 1 Input Frequency (Hz) 1000 1000 1000 1000 1000 130 130 50 50 10 V Range 3 dB SNR (dB) BW (kHz) 89.5 23.0 91 22.7 92.2 22.0 93 20.0 93.5 15.4 95.4 9.7 96.3 5.3 97.1 2.7 97.6 1.4 5 V Range 3 dB SNR (dB) BW (kHz) 88.5 13.9 89.9 13.8 90.8 13.6 91.5 13.0 92 11.4 93.7 8.4 95 5.0 95.9 2.7 96.8 1.4 Only available in software mode. Rev. 0 | Page 27 of 69 2.5 V Range 3 dB SNR (dB) BW (kHz) 86 11.6 87.2 11.5 88 11.4 88.4 11.1 89 10.0 90.4 7.7 91.8 4.9 93.3 2.7 94.7 1.4 Maximum Throughput (kSPS) 800 400 200 100 50 25 12.5 6.25 3.125 AD7606B Data Sheet PADDING OVERSAMPLING EXTERNAL OVERSAMPLING CLOCK As shown in Figure 53, an internally generated clock triggers the samples to be averaged, and then the ADC remains idle until the following CONVST signal rising edge. In software mode, through the oversampling register (Address 0x08), the internal clock (OS clock) frequency can be changed such that idle time is minimized, that is sampling instants are equally spaced, as shown in Figure 54. In software mode, there is an option to apply an external clock through the CONVST pin when oversampling mode is enabled. Providing a low jitter external clock improves SNR performance for large oversampling ratios. By applying an external clock, the input is sampled at regular time intervals, which is optimum for antialiasing performance. tCYCLE CONVST To enable the external oversampling clock, Bit 5 in the CONFIG register (Address 0x02, Bit 5) must be set. Then, the throughput rate is BUSY tCONV 15137-158 OS CLOCK Figure 54. Oversampling by 8 Example, Oversampling Padding Enabled Table 17. OS_PAD Bit Decoding OS_PAD (Address 0x08, Bits[7:5]) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 OS Clock Frequency (kHz) 800 753 711 673.5 640 609.5 582 556.5 533 512 492.5 474 457 441.5 426.5 413 Throughput = 1 tCNVST x OSR That is, the sampling signal is provided externally through the CONVST pin, and every OSR number of clocks, an output is averaged and provided, as shown in Figure 55. This feature is available using either the parallel interface or the serial interface. tCNVST CONVST BUSY CS 15137-159 RD DB0 TO DB15 Figure 55. External Oversampling Clock Applied on the CONVST Pin (OSR = 4); Parallel Interface Rev. 0 | Page 28 of 69 Data Sheet AD7606B SYSTEM CALIBRATION FEATURES The following system calibration features are available in software mode by writing to corresponding registers in the memory map: Phase calibration. Gain calibration. Offset calibration. Analog Input open circuit detection. Vx 5M VxGND 5M RFILTER C 15137-060 RFILTER Figure 57. System Gain Error When using an external filter, as shown in Figure 57, any mismatch on the discrete components, or in the sensor used, can cause phase mismatch between channels. This phase mismatch can be compensated for in software mode, on a per channel basis, by delaying the sampling instant on individual channels. The sampling instant on any particular channel can be delayed with regard to the CONVST signal rising edge, with a resolution of 1.25 s, and up to 318.75 s, by writing to the corresponding CHx_PHASE register (Address 0x19 through Address 0x20). 0 -100 -200 -300 For example, if the CH4_PHASE register (Address 0x1C) is written with 10d, Channel 4 is effectively sampled 12.5 s (tPHASE_REG) after the CONVST signal rising edge, as shown in Figure 56. -400 SYSTEM GAIN CALIBRATION OFF SYSTEM GAIN CALIBRATION ON -500 0 INPUT V1 INPUT V4 INTERNAL CONVST CH4 20 40 30 RFILTER (k) 50 60 Figure 58. System Gain Calibration with and Without Calibration SYSTEM OFFSET CALIBRATION CONVST INTERNAL CONVST CH1 10 15137-162 SYSTEM PHASE CALIBRATION For example, if a 27 k resistor is placed in series to the analog input of Channel 5, the resistor generates -170 LSB positive full-scale error on the system (at 10 V range), as shown in Figure 58. In software mode, this error is eliminated by writing 27d to the CH5_GAIN register (Address 0x0D). PFS (LSB) * * * * AD7606B ANALOG INPUT SIGNAL tPHASE_REG tCONV V1 CODE V4 CODE 15137-160 BUSY Figure 56. System Phase Calibration Functionality The BUSY signal high time equals tCONV plus tPHASE_REG, as shown in Figure 56. In the previously explained example and Figure 56, if only CH4_PHASE_REGISTER is programmed, tCONV increases by 12.5 s. Therefore, this scenario must be taken into account when running at higher throughput rates. SYSTEM GAIN CALIBRATION Using an external RFILTER, as shown in Figure 57, generates a system gain error. This gain error can be compensated for in software mode, on a per channel basis, by writing the series resistor value used on the corresponding register, Address 0x09 through Address 0x10. These registers can compensate up to 65 k series resistors, with a resolution of 1024 . A potential offset on the sensor, or any offset caused by a mismatch between the RFILTER pair placed on a particular channel (as described in the Analog Front End section), can be compensated in software mode, on a per channel basis. The CHx_OFFSET registers (Address 0x11 through Address 0x18) allow the ability to add or subtract up to 128 LSB from the ADC code automatically, with a resolution of 1 LSB, as shown in Table 18. For example, if the signal connected to Channel 3 has a 9 mV offset, and the analog input range is set to the 10 V range (where LSB size = 305 V) to compensate for this offset, program -30 LSB to the corresponding register. Writing 128d - 30d = 0x80 - 0x1E = 0x62 to the CH3_OFFSET register (Address 0x13) removes such offset. Table 18. CHx_OFFSET Register Bit Decoding CHx_OFFSET Register 0x00 0x45 0x80 (Default) 0x83 0xFF Rev. 0 | Page 29 of 69 Offset Calibration (LSB) -128 -59 0 +3 +127 AD7606B Data Sheet ANALOG INPUT OPEN CIRCUIT DETECTION The AD7606B has an analog input open circuit detection feature available in software mode. To use this feature, RPD must be placed as shown in Figure 59. If the analog input is disconnected, for example, if a switch opens in Figure 59, the source impedance changes from RS to RPD, as long as RS < RPD. It is recommended to use RPD = 50 k so that the AD7606B can detect changes in the source impedance by internally switching the PGA common-mode voltage. Analog input open circuit detection operates in manual mode or in automatic mode. changes the PGA common-mode voltage, checks the ADC output, and returns to the initial common-mode voltage, as shown in Figure 61. If the ADC code changes in any channel with the PGA common-mode change, this implies that there is no input signal connected to that analog input, and the corresponding flag asserts within the OPEN_DETECTED register (Address 0x24). Each channel can be individually enabled or disabled through the OPEN_DETECT_ ENABLE register (Address 0x23). START CONVERSION AD7606B RFILTER CFILTER RPD SAR ADC 0 < ADC CODE < 350 LSB Vx- 15137-061 5M RFILTER NO i=0 YES Figure 59. Analog Front End with RPD NO i = N? i=i+1 Manual Mode N = NUMBER OF CONSECUTIVE REPEATED (WITHIN 10 LSB) ADC OUTPUT CODE YES; SET COMMON MODE HIGH In manual mode, enabled by writing 0x01 to OPEN_DETECT_ QUEUE (Address 0x2C), each PGA common-mode voltage is controlled by the corresponding CHx_OPEN_DETECT_EN bit on the OPEN_DETECT_ENABLE register (Address 0x23). Setting this bit high shifts up the PGA common-mode voltage. If there is an open circuit on the analog input, the ADC output changes proportionally to the RPD resistor, as shown in Figure 60. If there is not an open circuit, any change on the PGA commonmode voltage has no effect on the ADC output. NO i=0 ADC CODE > 20 LSB YES; SET COMMON MODE LOW NO i=0 120 ADC CODE BACK TO ORIGINAL? YES 10V 5V 2.5V 15137-165 RS 5M Vx+ ADC CODE INCREMENT (LSB) 100 ERROR FLAG Figure 61. Automatic Analog Input Open Circuit Detect Flowchart 80 If no oversampling is used, the recommended minimum number of conversions to be programmed for the AD7606B to automatically detect an open circuit on the analog input is 60 40 OPEN _ DETECT _ QUEUE = 10 x f SAMPLE ( RPD + 2 x RFILTER ) x CFILTER 20 0 20 40 RPD (k) 60 80 100 However, when oversampling mode is enabled, the recommended minimum number of conversions to use is 15137-460 0 OPEN _ DETECT _ QUEUE = Figure 60. Open Circuit Code Error Increment, Dependent of RPD ( 1 + f SAMPLE x 2 ( RPD + 2 x RFILTER ) x CFILTER x OSR Automatic Mode Automatic mode is enabled by writing any value greater than 0x01 to the OPEN_DETECT_QUEUE register (Address 0x2C), as shown in Table 19. If the AD7606B detects that the ADC reported a number (specified in the OPEN_DETECT_QUEUE register) of consecutive unchanged conversions, the analog input open circuit detection algorithm is performed internally and automatically. The analog input open circuit detection algorithm automatically Rev. 0 | Page 30 of 69 ) Data Sheet AD7606B Table 19. Analog Input Open Circuit Detect Mode Selection and Register Functionality OPEN_DETECT_QUEUE (Address 0x2C) 0x00 (Default) 0x01 0x02 to 0xFF Open Detect Mode Disabled Manual mode Automatic; OPEN_DETECT_QUEUE is the number of consecutive conversions before asserting any CHx_OPENED flag Rev. 0 | Page 31 of 69 OPEN_DETECT_ENABLE (Address 0x23) Not applicable Sets common-mode voltage high or low, on a per channel basis Enables or disables automatic analog input open circuit detection on a per channel basis AD7606B Data Sheet DIGITAL INTERFACE The AD7606B provides two interface options: a parallel interface and a high speed serial interface. The required interface mode is selected via the PAR/SER SEL pin. Table 20. Interface Mode Selection PAR/SER SEL 0 1 Interface Mode Parallel interface mode Serial interface mode Operation of the interface modes is discussed in the following sections. HARDWARE MODE In hardware mode, only ADC mode is available. ADC data can be read from the AD7606B via the parallel data bus with standard CS and RD signals or via the serial interface with standard CS, SCLK, and two DOUTx signals. SOFTWARE MODE In software mode, which is active only when all three oversampling pins are tied high, both ADC read mode and register mode are available. ADC data can be read from the AD7606B, and registers can also be read from and written to the AD7606B via the parallel data bus with standard CS, RD, and WR signals or via the serial interface with standard CS, SCLK, SDI, and DOUTA lines. See the Parallel Register Mode (Writing Register Data) section and the Parallel Register Mode (Reading Register Data) section for more details on how register mode operates. Pin functions differ depending on the interface selected (parallel or serial) and the operation mode (hardware or software), as shown in Table 21 and Table 22. See the Reading Conversion Results (Parallel ADC Mode) section and the Reading Conversion Results (Serial ADC Mode) section for more details on how ADC read mode operates. Table 21. Data Interface Pin Function per Mode of Operation (Parallel Interface) Pin Name DB0 to DB6 DB7/DOUTA DB8/DOUTB DB9/DOUTC DB10/DOUTD DB11/SDI DB12 to DB14 DB15 Pin No. 16 to 22 24 25 27 28 29 30 to 32 33 Hardware Mode DB0 to DB6 DB7 DB8 DB9 DB10 DB11 DB12 to DB14 DB15 ADC Mode Software Mode Register Mode Register data Register data (MSB) ADD0 ADD1 ADD2 ADD3 ADD4 to ADD6 R/W Table 22. Data Interface Pin Function per Mode of Operation (Serial Interface) Pin Name DB0 to DB6 DB7/DOUTA DB8/DOUTB DB9/DOUTC DB10/DOUTD DB11/SDI DB12 to DB14 DB15 Pin No. 16 to 22 24 25 27 28 29 30 to 32 33 Hardware Mode N/A 1 DOUTA DOUTB N/A N/A means not applicable. Tie all N/A pins to AGND. Only used if 2SDO or 4SDO mode is selected on the CONFIG register, otherwise leave unconnected. 3 Only used if 4SDO mode is selected on the CONFIG register, otherwise leave unconnected. 1 2 Rev. 0 | Page 32 of 69 ADC Mode DOUTA DOUTB 2 DOUTC 3 DOUTD3 Unused Software Mode Register Mode N/A DOUTA Unused Unused Unused SDI N/A Data Sheet AD7606B PARALLEL INTERFACE To read ADC data or to read/write the register content over the parallel interface, tie the PAR/SER SEL pin low. AD7606B INTERRUPT BUSY 14 CS 13 RD/SCLK 12 DIGITAL HOST WR 10 DB[33:24] DB[22:16] 15137-166 DB[15:0] Figure 62. AD7606B Interface Diagram--One AD7606B Using the Parallel Bus, with CS and RD Shorted Together The rising edge of the CS input signal three-states the bus, and the falling edge of the CS input signal takes the bus out of the high impedance state. CS is the control signal that enables the data lines and it is the function that allows multiple AD7606B devices to share the same parallel data bus. Reading Conversion Results (Parallel ADC Mode) The falling edge of the RD pin reads data from the output conversion results register. Applying a sequence of RD pulses to the RD pin clocks the conversion results out from each channel to the parallel bus, [DB15:DB0], in ascending order, from V1 to V8, as shown in Figure 63. The CS signal can be permanently tied low, and the RD signal can access the conversion results, as shown in Figure 3. A read operation of new data can take place after the BUSY signal goes low (see Figure 2). Alternatively, a read operation of data from the previous conversion process can take place while the BUSY pin is high. When there is only one AD7606B in a system and it does not share the parallel bus, data can be read using one control signal from the digital host. The CS and RD signals can be tied together, as shown in Figure 4. In this case, the falling edge of the CS and RD signals bring the data bus out of three-state and clocks out the data. The FRSTDATA output signal indicates when the first channel, V1, is being read back, as shown in Figure 4. When the CS input is high, the FRSTDATA output pin is in three-state. The falling edge of CS takes the FRSTDATA pin out of three-state. The falling edge of the RD signal corresponding to the result of V1 sets the FRSTDATA pin high, indicating that the result from V1 is available on the output data bus. The FRSTDATA pin returns to a logic low following the next falling edge of RD. Reading During Conversion Data can be read from the AD7606B while the BUSY pin is high and the conversions are in progress. This operation has little effect on the performance of the converter, and it allows a faster throughput rate to be achieved. Data can be read from the AD7606B at any time other than on the falling edge of the BUSY signal because this is when the output data registers are updated with the new conversion data. Any data read while the BUSY signal is high must be completed before the falling edge of the BUSY signal. Parallel ADC Mode with CRC Enabled In software mode, the parallel interface supports reading the ADC data with the CRC appended, when enabled through the INT_CRC_ERR_EN bit (Address 0x21, Bit 2). The CRC is 16 bits, and it is clocked out after reading all eight channel conversions, as shown in Figure 65. The CRC calculation includes all data on the DBx pins: data, status (when appended), and zeros. See the Diagnostics section for more details on the CRC. Parallel ADC Mode with Status Enabled In software mode, the 8-bit status header is enabled (see Table 24) by setting Bit 6 in the CONFIG register (Address 0x02, Bit 6), and each channel then takes two frames of data: The first frame clocks the ADC data out normally through DBx. The second frame clocks out the status header of the channel on DB15 to DB8, DB15 being the MSB and DB8 the LSB, while the DB7 to DB0 pins clock out zeros. This sequence is shown in Figure 64. Table 24 explains the status header content and describes each bit. Table 23. CH.ID Bits Decoding in Status Header CH.ID2 0 0 0 0 1 1 1 1 CH.ID1 0 0 1 1 0 0 1 1 CH.ID0 0 1 0 1 0 1 0 1 Channel Number Channel 1 (V1) Channel 2 (V2) Channel 3 (V3) Channel 4 (V4) Channel 5 (V5) Channel 6 (V6) Channel 7 (V7) Channel 8 (V8) Table 24. Status Header, Parallel Interface Bit Details Bit Name Bit Description1 1 Bit 7 (MSB) RESET_DETECT Reset detected Bit 6 DIGITAL_ERROR Error flag on Address 0x22 Bit 5 OPEN_DETECTED The analog input of this channel is open Bit 4 AIN_OV_DIAG_ERR Overvoltage detected on this channel See the Diagnostics section for more information. Rev. 0 | Page 33 of 69 Bit 3 AIN_UV_DIAG_ERR Undervoltage detected on this channel Bit 2 Bit 1 Bit 0 (LSB) CH.ID 2 CH.ID 1 CH.ID 0 Channel ID (see Table 23) AD7606B Data Sheet CONVST BUSY CS DB0 TO DB15 V1 V2 V3 V4 V5 V6 V7 15137-167 RD V8 FRSTDATA Figure 63. Parallel Interface, ADC Read Mode CONVST BUSY CS DB0 TO DB15 DB0 TO DB7 V1[15:8] STATUS_CH1 V2[15:8] V1[7:0] STATUS_CH2 V7[15:8] V2[7:0] STATUS_CH7 V7[7:0] V8[15:8] STATUS_CH8 V8[7:0] 15137-168 RD Figure 64. Parallel Interface, ADC Read Mode with Status Header Enabled CONVST BUSY DB0 TO DB15 V1 V2 V3 V4 V5 V6 V7 V8 CRC 15137-169 CS RD Figure 65. Parallel Interface, ADC Read Mode with CRC Enabled Parallel Register Mode (Reading Register Data) In software mode, all the registers in Table 31 can be read over the parallel interface. [DB15:DB0] leave a high impedance state when both the CS signal and RD signal are logic low for reading register content, or when both the CS signal and WR signal are logic low for writing register address and/or register content. A register read is performed through two frames: first, a read command is sent to the AD7606B and second, the AD7606B clocks out the register content. The format for a register read command is shown in Figure 66. On the first frame, Bit DB15 must be set to 1 to select a read command. The read command places the AD7606B in register mode. Bits DB[14:8] must contain the register address. The subsequent eight bits, DB[7:0], are ignored. The register address is latched on the AD7606B on the rising edge of the WR signal. The register content can then be read from the latched register by bringing the RD line low on the following frame, as follows: Bit DB15 is pulled to 0 by the AD7606B. Bits DB[14:8] provide the register address being read. The subsequent eight bits, DB[7:0], provide the register content. To revert to ADC read mode, write to Address 0x00, as shown in the Parallel Register Mode (Writing Register Data) section. No ADC data can be read while the device is in register mode. Parallel Register Mode (Writing Register Data) In software mode, all the R/W registers in Table 31 can be written to over the parallel interface. To write a sequence of registers, exit ADC read mode (default mode) by reading any register on the memory map. A register write command is performed by a single frame, via the parallel bus (DB[15:0]), CS signal, and WR signal. The format for a write command is shown in Figure 66. The format of a write command, as shown in Figure 66, is structured as follows: Bit DB15 must be set to 0 to select a write command. Bits DB[14:8] contain the register address. The subsequent eight bits, DB[7:0], contain the data to be written to the selected register. Data is latched onto the device on the rising edge of the WR pin. To revert to ADC read mode, write to Address 0x00. No ADC data can be read while the device is in register mode. Rev. 0 | Page 34 of 69 Data Sheet AD7606B CS RD R/W = 1 R/W = 0 R/W = 0 R/W = 0 DB8 TO DB14 REG. ADDRESS REG. ADDRESS REG. ADDRESS ADDRESS = 0x00 DB0 TO DB7 DON'T CARE REGISTER DATA REGISTER DATA DON'T CARE DB15 MODE ADC READ MODE 15137-170 WR ADC READ MODE REGISTER MODE Figure 66. Parallel Interface Register Read Operation, Followed by a Write Operation CS FRSTDATA SCLK DOUTA V1 V2 V3 V4 V5 V6 V7 V8 DOUTB 15137-171 DOUTC DOUTD Figure 67. Serial Interface ADC Reading, One DOUTx Line SERIAL INTERFACE To read ADC data or to read/write the registers content over the serial interface, tie the PAR/SER SEL pin high. In hardware mode, only the 2 DOUTx lines option is available. However, all channels can be read from DOUTA by providing eight 16-bit SPI frames between two CONVST pulses. CNVST AD7606B INTERRUPT BUSY 14 CS CS 13 SCLK RD/SCLK 12 DOUTA V1 V2 V3 V4 DOUTB V5 V6 V7 V8 DB11/SDI 29 DIGITAL HOST DOUTD DB9/DOUTC 27 Figure 69. Serial Interface ADC Reading, Two DOUTx Lines 15137-172 DB10/D OUTD 28 CS Figure 68. AD7606B Interface Diagram--One AD7606B Using the Serial Interface with Four DOUTx Lines SCLK Reading Conversion Results (Serial ADC Mode) The AD7606B has four serial data output pins: DOUTA, DOUTB, DOUTC, and DOUTD. In software mode, data can be read back from the AD7606B using either one (see Figure 68), two (see Figure 69), or four DOUTx lines (see Figure 70), depending on the configuration set in the CONFIG register. Table 25. DOUTx Format Selection, Using the CONFIG Register (Address 0x02) DOUTx Format 1 DOUTx 2 DOUTx 4 DOUTx 1 DOUTx Address 0x02, Bit 4 0 0 1 1 15137-173 DOUTC DB8/DOUTB 25 Address 0x02, Bit 3 0 1 0 1 DOUTA V1 V2 DOUTB V3 V4 DOUTC V5 V6 DOUTD V7 V8 15137-174 DB7/DOUTA 24 Figure 70. Serial Interface ADC Reading, Four DOUTx Lines The CS falling edge takes the data output lines, DOUTA to DOUTD, out of three-state and clocks out the MSB of the conversion result. In 3-wire mode (CS tied low), instead of CS clocking out the MSB, the falling edge of the BUSY signal clocks out the MSB. The rising edge of the SCLK signal clocks all the subsequent data bits on the serial data outputs, DOUTA to DOUTD, as shown in Figure 6. The CS input can be held low for the entire serial read operation, or it can be pulsed to frame each channel read of 16 SCLK cycles (see Rev. 0 | Page 35 of 69 AD7606B Data Sheet Figure 69). However, if CS is pulsed during a channel conversion result transmission, the channel that was interrupted retransmits on the next frame, completely starting from the MSB. Data can also be clocked out using only the DOUTA pin, as shown in Figure 67. For the AD7606B to access all eight conversion results on one DOUTx line, a total of 128 SCLK cycles is required. In hardware mode, these 128 SCLK cycles must be framed on groups of 16 SCLK cycles by the CS signal. The disadvantage of using just one DOUTx line is that the throughput rate is reduced if reading occurs after conversion. Leave the unused DOUTx lines unconnected in serial mode. line sets the FRSTDATA pin high when the result from V1 is available on DOUTA. If SDI is tied low or high, nothing is clocked to the AD7606B. Therefore, the device remains clocking out conversion results. When using the AD7606B in 3-wire mode, keep the SDI at a high level. While in ADC read mode, single-write operations can be performed, as shown in Figure 71. For writing a sequence of registers, switch to register mode, as described in the Serial Register Mode (Writing Register Data) section. Reading During Conversion Figure 70 shows a read of eight simultaneous conversion results using four DOUTx lines on the AD7606B, available in software mode. In this case, a 32 SCLK transfer accesses data from the AD7606B, and CS is either held low to frame the entire 32 SCLK cycles or is pulsed between two 16-bit frames. This mode is only available in software mode, and it is configured using the CONFIG register (Address 0x02). Figure 6 shows the timing diagram for reading one channel of data, framed by the CS signal, from the AD7606B in serial mode. The SCLK input signal provides the clock source for the serial read operation. The CS signal goes low to access the data from the AD7606B. The FRSTDATA output signal indicates when the first channel, V1, is being read back. When the CS input is high, the FRSTDATA output pin is in three-state. In serial mode, the falling edge of the CS signal takes the FRSTDATA pin out of three-state and sets the FRSTDATA pin high if the BUSY line is already deasserted, indicating that the result from V1 is available on the DOUTA output data line. The FRSTDATA output returns to a logic low following the 16th SCLK falling edge. If the CS pin is tied permanently low (3-wire mode), the falling edge of the BUSY Data can be read from the AD7606B while the BUSY signal is high and the conversions are in progress. This operation has little effect on the performance of the converter, and it allows a faster throughput rate to be achieved. Data can be read from the AD7606B at any time other than on the falling edge of the BUSY signal because this is when the output data registers are updated with the new conversion data. Any data read while the BUSY signal is high must be completed before falling edge of the BUSY signal. Serial ADC Mode, with CRC Enabled In software mode, the CRC can be enabled by writing to the register map. In this case, the CRC is appended on each DOUTx line after the last channel is clocked out as shown in Figure 78. See the Interface CRC Checksum section for more information on how the CRC is calculated. Serial ADC Mode, with Status Enabled In software mode, the 8-bit status header can be turned on when using the serial interface, so that it is appended after each 16-bit data conversion, extending the frame size to 24 bits per channel, as shown in Figure 71. CS 1 2 3 4 DOUTx 5 6 7 8 9 16 24 ADC DATA 15137-175 SCLK STATUS HEADER Figure 71. Serial Interface, ADC Mode, Status On CS SCLK SDI REGISTER N DOUTA ADC DATA ADC DATA DOUTB TO ADC DATA DOUTD ADC DATA MODE ADC MODE R/W COMMAND R/W COMMAND WRITE COMMAND REGISTER N+1 REGISTER N+2 ADDRESS 0x00 REGISTER N REGISTER N+1 REGISTER N+2 ADC DATA ADC DATA REGISTER MODE Figure 72. AD7606B Register Mode Rev. 0 | Page 36 of 69 ADC MODE 15137-176 READ COMMAND Data Sheet AD7606B Table 26. Status Header, Serial Interface Bit Details Bit Name Bit Description 1 1 Bit 7 (MSB) RESET_DETECT Reset detected Bit 6 DIGITAL_ERROR Error flag on Address 0x22 Bit 5 OPEN_DETECTED At least one analog input is open on a channel Bit 4 AIN_OV_DIAG_ERR Overvoltage detected on a channel Bit 3 AIN_UV_DIAG_ERR Undervoltage detected on a channel Bit 2 Bit 1 Bit 0 (LSB) CH.ID 2 CH.ID 1 CH.ID 0 Channel ID (see Table 23) See the Diagnostics section for more information. Serial Register Mode (Reading Register Data) All the registers in Table 31 can be read over the serial interface. The format for a read command is shown in Figure 73. It consists of two 16-bit frames. On the first frame, * * * * The first bit in SDI must be set to 0 to enable writing the address. The second bit must be set to 1 to select a read command. Bits[3:8] in SDI contain the register address to be clocked out on DOUTA on the following frame. The subsequent eight bits, Bits[9:16], in SDI are ignored. If the AD7606B is in ADC mode, the SDO keeps clocking ADC data on Bits[9:16], and then the AD7606B switches to register mode. If the AD7606B is in register mode, the SDO reads back the content from the previous addressed register, no matter if the previous frame was a read or a write command. To exit register mode, a write to Address 0x00 is required, as shown in Figure 72. Serial Register Mode (Writing Register Data) In software mode, all the read/write registers in Table 31 can be written to over the serial interface. To write a sequence of registers, exit ADC read mode (default mode) by reading any register on the memory map. A register write command is performed by a single 16-bit SPI access. The format for a write command is shown in Figure 74. The format for a write command, as shown in Figure 74, is structured as follows: * * * * The first bit in SDI must be set to 0 to enable a write command. The second bit, the R/W bit, must be cleared to 0. Bits[ADD5:ADD0] contain the register address to be written. The subsequent eight bits (Bits[DIN7:DIN0]) contain the data to be written to the selected register. Data is clocked in from SDI on the falling edge of SCLK, while data is clocked out on DOUTA on the rising edge of SCLK. When writing continuously to the device, the data that appears on DOUTA is from the register address that was written to on the previous frame, as shown in Figure 74. The DOUTB, DOUTC, and DOUTD pins are kept low during the transmission. While in register mode, no ADC data is clocked out because the DOUTx lines are used to clock out register content. When finished writing all needed registers, a write to Address 0x00 returns the AD7606B to ADC read mode, where the ADC data is again clocked out on the DOUTx lines, as shown in Figure 72. In software mode, when the CRC is turned on, eight additional bits are clocked in and out on each frame. Therefore, 24-bit frames are needed. Rev. 0 | Page 37 of 69 AD7606B Data Sheet CS SCLK 1 8 16 SDI ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 READ OR WRITE COMMAND ADC DATA (8LSB) OR PREVIOUS REGISTER READ/WRITTEN ADC DATA (8LSB) OR XX REGISTER [ADD5:ADD0] CONTENT 15137-073 WEN R/W DOUTA Figure 73. Serial Interface Read Command; First Frame Points the Address; Second Frame Provides the Register Content CS SCLK 8 1 WEN R/W SDI 9 16 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 DIN71 DIN61 DIN51 DIN41 DIN31 DIN21 DIN11 DIN01 DOUTA DATA OUT2 15137-074 1DATA 2DATA IN DINx IS WRITTEN INTO REGISTER ADDRESS [ADD5:ADD0] OUT IS THE REGISTER CONTENT OF PREVIOUS REGISTER WRITTEN Figure 74. Serial Interface, Single-Write Command; SDI Clocks in the Address [ADD5:ADD0] and the Register Content [DINx] During the Same Frame, DOUTA Provides Register Content Requested on the Previous Frame CS SDI 1 WEN R/W 8 9 16 24 ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 MSB DOUTA LSB 15137-179 SCLK 8-BIT CRC Figure 75. Reading Registers Through the SPI Interface with CRC Enabled CS 1 8 9 16 24 SDI WEN R/W ADD5 ADD4 ADD3 ADD2 ADD1 ADD0 MSB LSB 8-BIT CRC 15137-180 SCLK Figure 76. Writing Registers Through the SPI Interface with CRC Enabled Serial Register Mode with CRC Registers can be written to and read from the AD7606B with CRC enabled, in software mode, by asserting the INT_CRC_ ERR_EN bit (Address 0x21, Bit 2). When reading a register, the AD7606B provides eight additional bits on the DOUTA pin with the CRC resultant of the data shifted out previously on the same frame. The controller can then check whether the data received is correct by applying the following polynomial: x8 + x 2 + x + 1 With the CRC enabled, the SPI frames extend to 24 bits in length, as shown in Figure 75. When writing a register, the controller must clock the data (register address plus register content) in the AD7606B followed by an 8-bit CRC word, calculated from the previous 16 bits using the previously described polynomial. The AD7606B reads the register address and the register content, calculates the corresponding 8-bit CRC word, and asserts the INT_CRC_ERR bit (Address 0x22, Bit 2) if the calculated CRC word does not match the CRC word received between the 17th and 24th bit through SDI, as shown in Figure 76. Rev. 0 | Page 38 of 69 Data Sheet AD7606B DIAGNOSTICS Diagnostic features are available in software mode to verify correct operation of the AD7606B. The list of diagnostic monitors includes reset detection, overvoltage detection, undervoltage detection, analog input open circuit detection, and digital error detection. If an error is detected, a flag asserts on the status header, if enabled, as described in the Digital Interface section. This flag points to the registers on which the error is located, as explained in the following sections. In addition, a diagnostic multiplexer can dedicate any channel to verify a series of internal nodes, as explained in the Diagnostics Multiplexer section. RESET DETECTION The RESET_DETECT bit on the status register (Address 0x01, Bit 7) asserts if either a partial reset or full reset pulse is applied to the AD7606B. On power-up, a full reset is required. This reset asserts the RESET_DETECT bit, indicating that the power-on reset (POR) initialized correctly on the device. The POR monitors the REGCAP voltage and issues a full reset if the voltage drops under a certain threshold. The RESET_DETECT bit can be used to detect an unexpected device reset or a large glitch on the RESET pin, or a voltage drop on the supplies. When the voltage on any analog input pin goes below the undervoltage threshold shown in Table 27, the AIN_UV_ DIAG_ERROR register (Address 0x27) shows which channel or channels have an undervoltage event. When a bit within the AIN_UV_DIAG_ERROR register asserts, it stays at high state after the undervoltage event disappears. To clear the error bit, the error bit must be overwritten to 1 or the error checker must be disabled. Table 27. Overvoltage and Undervoltage Thresholds Analog Input Range (V) 2.5 5 10 Overvoltage Threshold (V) +6.5 +8 +12 Undervoltage Threshold (V) -3 -5.5 -11 DIGITAL ERROR Both the status register and status header contain a DIGITAL_ERROR bit. This bit asserts when any of the following monitors trigger: * * * Memory map CRC, read only memory (ROM) CRC, and digital interface CRC. SPI invalid read or write. BUSY stuck high. The RESET_DETECT bit is only cleared by reading the status register. To find out which monitor triggered the DIGITAL_ERROR bit, the DIGITAL_DIAG_ERR address (Address 0x22) has a bit dedicated for each monitor, as explained in the following sections. OVERVOLTAGE AND UNDERVOLTAGE EVENTS ROM CRC The AD7606B includes on-chip overvoltage and undervoltage circuitry on each analog input pin. These comparators can be enabled or disabled using the AIN_OV_UV_DIAG_ ENABLE register (Address 0x25). The ROM stores the factory trimming settings for the AD7606B. After power-up, the ROM content is loaded to registers during device initialization. After the load, a CRC is calculated on the loaded data and verified if the result matches the CRC stored in the ROM. If an error is found, the ROM_ CRC_ERR (Address 0x22, Bit 0) asserts. When ROM_CRC_ ERR asserts after power-up, it is recommended to issue a full reset to reload all factory settings. After this register is enabled, when the voltage on any analog input pin goes above the overvoltage threshold shown in Table 27, the AIN_OV_DIAG_ERROR register (Address 0x26) shows which channel or channels have an overvoltage event. When a bit within the AIN_OV_DIAG_ERROR register asserts, it stays at a high state even after the overvoltage event disappears. To clear the error bit, the error bit must be overwritten to 1 or the error checker must be disabled. OVERVOLTAGE THRESHOLD AD7606B CHx_OV_ERR SETS IF Vx > OV CHx_UV_ERR SETS IF Vx < UV UNDERVOLTAGE THRESHOLD 15137-075 Vx Figure 77. Overvoltage and Undervoltage Circuitry on Each Analog Input This ROM CRC monitoring feature is enabled by default, but can be disabled by clearing the ROM_CRC_ERR_EN bit (Address 0x21, Bit 0). Memory Map CRC The memory map CRC is disabled by default. After the AD7606B is configured in software mode through writing the required registers, the memory map CRC can be enabled through the MM_CRC_ERR_EN bit (Address 0x21, Bit 1). When enabled, the CRC calculation is performed on the entire memory map and stored. Every 4 s, the CRC on the memory map is recalculated and compared to the stored CRC value. If the calculated and the stored CRC values do not match, the memory map is corrupted and the MM_CRC_ERR bit asserts. Every time the memory map is written, the CRC is recalculated and the new value stored. Rev. 0 | Page 39 of 69 AD7606B Data Sheet The serial interface supports the CRC when enabled via the INT_CRC_ERR_EN bit (Address 0x21, Bit 2). The CRC is a 16bit word that is appended to the end of each DOUTx in use, after reading all the channels. An example using four DOUTx lines is shown in Figure 78. If the MM_CRC_ERR bit asserts, it is recommended to write to the memory map to recalculate the CRC. If the error persists, it is recommended to issue a full reset to restore the default contents of the memory map. Interface CRC Checksum The AD7606B has a CRC checksum mode to improve interface robustness by detecting errors in data transmission. The CRC feature is available in both ADC modes (serial and parallel) and register mode (serial only). CNVST The AD7606B uses the following 8-bit CRC polynomial to calculate the CRC checksum value: DOUTA V1 V2 CRC(V1,V2) DOUTB V3 V4 CRC(V3,V4) DOUTC V5 V6 CRC(V5,V6) DOUTD V7 V8 CRC(V7,V8) CS x16 + x14 + x13 + x12 + x10 + x8 +x6 + x4 + x3 + x + 1 To replicate the polynomial division in hardware, the data shifts left by 16 bits to create a number ending in 16 Logic 0s. The polynomial is aligned so that the MSB is adjacent to the leftmost Logic 1 of the data. An exclusive OR (XOR) function is applied to the data to produce a new, shorter number. The polynomial is again aligned so that the MSB is adjacent to the leftmost Logic 1 of the new result, and the procedure repeats. This process repeats until the original data is reduced to a value less than the polynomial, the 16-bit checksum. 15137-076 SCLK Figure 78. Serial Interface ADC Reading with CRC On, Four DOUTx Lines If using two DOUTx lines (DOUTA and DOUTB), each 16-bit CRC word is calculated using data from four channels, that is 64 bits, as shown in Figure 79. If using only one DOUTx line, all eight channels are clocked out through DOUTA, followed by the 16-bit CRC word calculated using data from the eight channels, that is, 128 bits. An example of the CRC calculation for the 16-bit data is shown in Table 28. The CRC corresponding to the data 0x064E, using the previously described polynomial, is 0x2137. CNVST CS SCLK DOUTA V1 V2 V3 V4 CRC(V1,V4) DOUTB V5 V6 V7 V8 CRC(V5,V8) 15137-077 DOUTC DOUTD Figure 79. Serial Interface ADC Reading with CRC On, Two DOUTx Lines Rev. 0 | Page 40 of 69 Data Sheet AD7606B INT_CRC_ERR (Address 0x22, Bit 2), if the CRC given and the internally calculated do not match. When the AD7606B is in register mode, that is, when registers are being read or written, the CRC polynomial used is x8 + x2 + x + 1. When reading a register, and CRC is enabled, each SPI frame is 24 bits long and the CRC 8-bit word is clocked out from the 17th to 24th SCLK cycle. Similarly, when writing a register, a CRC word can be appended on the SDI line, as shown in Figure 80 and the AD7606B checks and triggers an error, The parallel interface also supports CRC in ADC mode only, and it is clocked out through DB15 to DB0 after Channel 8, as shown in Figure 65. The 16-bit CRC word calculated using data from the eight channels, that is, 128 bits. CS DOUTA TO DOUTD SDI 1 2 3 4 DB15 DB14 DB13 DB12 WEN R/W ADD5 ADD4 15 16 17 DB1 DB0 CRC7 DIN1 DIN0 CRC7 Figure 80. Register Write with CRC On Rev. 0 | Page 41 of 69 24 CRC0 CRC0 15137-078 SCLK AD7606B Data Sheet Table 28. Example CRC Calculation for 16-Bit Data 1 Data 2 Process Data Polynomial 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 0 0 1 1 1 1 1 1 0 0 x 0 x 0 x 0 x 0 x 0 x 0 x 0 x 0 x 0 x 0 x 0 x 0 x 0 x 0 x 0 x 0 1 0 0 1 1 0 1 1 0 1 1 0 1 1 1 0 0 0 1 0 1 1 1 0 0 0 1 1 1 0 1 1 0 1 1 0 0 1 1 0 0 0 1 0 0 0 1 1 1 0 0 1 1 0 0 0 0 0 1 1 0 1 1 0 1 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 1 1 1 0 1 1 1 0 0 0 0 0 1 1 0 0 1 1 1 0 1 1 1 0 1 1 0 1 1 0 0 0 0 0 1 1 1 0 0 0 1 1 1 0 0 1 1 1 0 0 0 0 0 0 1 1 1 0 1 1 0 0 0 0 0 0 1 1 1 0 0 1 1 0 1 0 0 0 1 1 0 1 1 1 0 0 1 1 0 1 0 1 1 0 1 1 CRC 1 2 This table represents the division of the data. Blank cells are for formatting purposes. X = don't care. Interface Check BUSY Stuck High The integrity of the digital interface can be checked by setting the INTERFACE_CHECK_EN bit (Address 0x21, Bit 7). Selecting the interface check forces the conversion result registers to a known value, as shown in Table 29. BUSY stuck high monitoring is enabled by setting the BUSY_STUCK_HIGH_ERR_EN bit (Address 0x21, Bit 5). After this bit is enabled, the conversion time (tCONV in Table 3) is monitored internally with an independent clock. If tCONV exceeds 4 s, the AD7606B automatically issues a partial reset and asserts the BUSY_STUCK_HIGH_ERR bit (Address 0x22, Bit 5). To clear this error flag, the BUSY_STUCK_HIGH_ERR bit must be overwritten with a 1. Verifying that the controller receives the data shown in Table 29 ensures that the interface between the AD7606B and the controller operates properly. If the interface CRC is enabled because the data transmitted is known, this mode verifies that the controller performs the CRC calculation properly. Table 29. Interface Check Conversion Results Channel Number V1 V2 V3 V4 V5 V6 V7 V8 When oversampling mode is enabled, the individual conversion time for each internal conversion is monitored. DIAGNOSTICS MULTIPLEXER Conversion Result Forced (Hex.) 0xACCA 0x5CC5 0xA33A 0x5335 0xCAAC 0xC55C 0x3AA3 0x3553 All eight input channels contain a diagnostics multiplexer in front of the PGA that allows monitoring of the internal nodes described in Table 30 to ensure the correct operation of the AD7606B. Table 30 shows the bit decoding for the diagnostic mux register on Channel 1, as an example. When an internal node is selected, the input voltage at input pins are deselected from the PGA, as shown in Figure 81. SPI Invalid Read/Write When attempting to read back an invalid register address, the SPI_READ_ERR bit (Address 0x22, Bit 4) is set. The invalid readback address detection can be enabled by setting the SPI_READ_ERR_EN bit (Address 0x21, Bit 4). If an SPI read error is triggered, it is cleared by overwriting that bit or disabling the checker. When attempting to write to an invalid register address or a read only register, the SPI_WRITE_ERR bit (Address 0x22, Bit 3) is set. The invalid write address detection can be enabled by setting the SPI_WRITE _ERR bit (Address 0x21, Bit 3). If an SPI write error is triggered, it is cleared by overwriting that bit or disabling the checker. Each diagnostic multiplexer configuration is accessed, in software mode through the corresponding register (Address 0x28 to Address 0x2B). To use the multiplexer on one channel, the 10 V range must be selected on that channel. Table 30. Diagnostic Mux Register Bit Decoding of Channel 1 Bit 2 0 0 0 0 1 1 1 1 Rev. 0 | Page 42 of 69 Address 0x18 Bit 1 Bit 0 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 Signal on Channel 1 V1 Temperature sensor VREF 4 x ALDO 4 x DLDO VDRIVE AGND AVCC Data Sheet TEMPERATURE SENSOR VREF 4xALDO 4xDLDO VDRIVE AGND AVCC AD7606B Therefore, if the ADC output goes beyond the expected 2.5 V, either the reference buffer or the PGA is malfunctioning. AD7606B AD7606B MUX 5M RFB INT REF 4.4V V1 V1GND EXT REF RFB 2.5V 15137-079 MUX Figure 81. Diagnostic Multiplexer (Channel 1 Shown as an Example) RFB 5M Vx VxGND RFB 5M RFB Temperature Sensor The temperature sensor can be selected through the diagnostic multiplexer and converted with the ADC, as shown in Figure 81. The temperature sensor voltage is measured and is proportional to the die temperature, as per the following equation: ADC 15137-080 5M Figure 82. Reference Voltage Signal Path Through the Diagnostic Multiplexer Internal LDOs with an accuracy of 2C. The analog and digital LDO (REGCAP pins) can be selected through the diagnostic multiplexer and converted with the ADC, as shown in Figure 81. The ADC output is four times the voltage on the REGCAPA and REGCAPD pins, respectively. This measurement verifies that each LDO is at the correct operating voltage so that the internal circuitry is biased correctly. Reference Voltage Supply Voltages The reference voltage can be selected through the diagnostic multiplexer and converted with the ADC, as shown in Figure 82. The internal or external reference is selected as input to the diagnostic multiplexer based on REF SELECT pin. Ideally, the ADC output follows the voltage reference level ratio metrically. AVCC, VDRIVE, and AGND can be selected through the diagnostic multiplexer and converted with the ADC, as shown in Figure 81. This setup ensures the voltage and grounds are correctly applied to the device to ensure correct operation. Temperature ( C ) = ADCOUT (V ) - 0.69068 (V ) 0.019328 (V / C ) + 25 ( C ) Rev. 0 | Page 43 of 69 AD7606B Data Sheet TYPICAL CONNECTION DIAGRAM There are four AVCC supply pins on the device. It is recommended that each of the four pins are decoupled using a 100 nF capacitor at each supply pin and a 10 F capacitor at the supply source. The AD7606B can operate with the internal reference or an externally applied reference. When using a single AD7606B device on the board, decouple the REFIN/REFOUT pin with a 100 nF capacitor. Refer to the Reference section when using an application with multiple AD7606B devices. The REFCAPA and REFCAPB pins are shorted together and decoupled with a 10 F ceramic capacitor. parallel interface because the PAR/SER pin is tied to AGND. The analog input range for all eight channels is 10 V, provided the RANGE pin is tied to a high level and the oversampling ratio is controlled through the OS pins by the controller. In Figure 84, the AD7606B is configured in software mode, because all three OS2, OS1, and OS0 pins are at logic level high. The oversampling ratio, as well as each channel range, are configured through accessing the memory map. In this example, the PAR/SER pin is at logic level high. Therefore, the serial interface is used for both reading the ADC data and reading and writing the memory map. The REF SELECT pin is tied to AGND. Therefore, the internal reference is disabled and an external reference is connected externally to the REFIN/REFOUT pin and decoupled through a 100 nF capacitor. The VDRIVE supply is connected to the same supply as the processor. The VDRIVE voltage controls the voltage value of the output logic signals. For more information on layout, decoupling, and grounding, see the Layout Guidelines section. After supplies are applied to the AD7606B, apply a reset to the AD7606B to ensure that it is configured for the correct mode of operation. Figure 83 and Figure 84 are examples of typical connection diagrams. Other combinations of reference, data interface, and operation mode are also possible, depending on the logic levels applied to each configuration pin. ANALOG SUPPLY VOLTAGE 5V1 100nF + REFIN/REFOUT DIGITAL SUPPLY VOLTAGE +1.71V TO +3.6V 100nF 100nF 1F REGCAP2 AVCC VDRIVE REFCAPA DB0 TO DB15 10F + REFCAPB REFGND CONVST V1 CS V1GND RD V2 BUSY V2GND V3 V3GND AD7606B V4 EIGHT ANALOG INPUTS V1 TO V8 PARALLEL INTERFACE MICROPROCESSOR/ MICROCONVERTER/ DSP In Figure 83, the AD7606B is configured in hardware mode and is operating with the internal reference because the REF SELECT pin is set to logic high. In this example, the device also uses the RESET OS2 OS1 V4GND OVERSAMPLING OS0 V5 V5GND REF SELECT V6 VDRIVE PAR/SER SEL V6GND RANGE V7 V7GND STBY VDRIVE V8 AGND 1DECOUPLING SHOWN ON THE AV CC PIN APPLIES TO EACH AVCC PIN (PIN 1, PIN 37, PIN 38, PIN 48). DECOUPLING CAPACITOR CAN BE SHARED BETWEEN AV CC PIN 37 AND PIN 38. 2DECOUPLING SHOWN ON THE REGCAP PIN APPLIES TO EACH REGCAP PIN (PIN 36, PIN 39). Figure 83. AD7606B Typical Connection Diagram, Hardware Mode Rev. 0 | Page 44 of 69 15137-081 V8GND Data Sheet AD7606B ANALOG SUPPLY VOLTAGE 5V1 REF 100nF + REFIN/REFOUT DIGITAL SUPPLY VOLTAGE +1.71V TO +3.6V 100nF 100nF 1F REGCAP2 AVCC VDRIVE DB0 TO DB15 10F + REFCAPB REFGND CONVST V1 CS V1GND SDI V2 V2GND V3 V3GND AD7606B DOUTx SCLK RESET OS2 V4 EIGHT ANALOG INPUTS V1 TO V8 MICROPROCESSOR/ MICROCONVERTER/ DSP REFCAPA OS1 V4GND OVERSAMPLING = 111b OS0 V5 V5GND REF SELECT V6 V6GND PAR/SER SEL V7 RANGE V7GND VDRIVE STBY V8 AGND 1DECOUPLING SHOWN ON THE AVCC PIN APPLIES TO EACH AVCC PIN (PIN 1, PIN 37, PIN 38, PIN 48). DECOUPLING CAPACITOR CAN BE SHARED BETWEEN AVCC PIN 37 AND PIN 38. SHOWN ON THE REGCAP PIN APPLIES TO EACH REGCAP PIN (PIN 36, PIN 39). 2DECOUPLING Figure 84. Typical Connection Diagram, Software Mode Rev. 0 | Page 45 of 69 15137-082 V8GND AD7606B Data Sheet The following layout guidelines are recommended to be followed when designing the PCB that houses the AD7606B: * * * * * * * * * * The analog and digital sections are separated and confined to different areas of the board. Use at least one ground plane. This plane can be common or split between the digital and analog sections. In the case of a split plane, join the digital and analog ground planes in only one place, preferably as close as possible to the AD7606B. If the AD7606B is in a system where multiple devices require analog-to-digital ground connections, make the connection at only one point: a star ground point that is established as close as possible to the AD7606B. Make stable connections to the ground plane. Avoid sharing one connection for multiple ground pins. Use individual vias or multiple vias to the ground plane for each ground pin. Avoid running digital lines under the device because doing so couples noise on the die. Allow the analog ground plane to run under the AD7606B to avoid noise coupling. Shield fast switching signals like CONVST, or clocks with digital ground to avoid radiating noise to other sections of the board and ensure that they never run near analog signal paths. Avoid crossover of digital and analog signals. Traces on layers in close proximity on the board run at right angles to each other to reduce the effect of feedthrough through the board. Power supply lines to the AVCC and VDRIVE pins on the AD7606B use as large a trace as possible to provide low impedance paths and reduce the effect of glitches on the power supply lines. Where possible, use supply planes and make stable connections between the AD7606B supply pins and the power tracks on the board. Use a single via or multiple vias for each supply pin. Place the decoupling capacitors close to (ideally, directly against) the supply pins and their corresponding ground pins. Place the decoupling capacitors for the REFIN/ REFOUT pin and the REFCAPA pin and REFCAPB pin as close as possible to their respective AD7606B pins. Where possible, place the pins on the same side of the board as the AD7606B device. Figure 85 shows the recommended decoupling on the top layer of the AD7606B board. Figure 86 shows bottom layer decoupling, which is used for the four AVCC pins and the VDRIVE pin decoupling. Where the ceramic 100 nF caps for the AVCC pins are placed close to their respective device pins, a single 100 nF capacitor can be shared between Pin 37 and Pin 38. Rev. 0 | Page 46 of 69 15137-083 LAYOUT GUIDELINES Figure 85. Top Layer Decoupling REFIN/REFOUT, REFCAPA, REFCAPB, and REGCAP Pins 15137-084 APPLICATIONS INFORMATION Figure 86. Bottom Layer Decoupling Data Sheet AD7606B To ensure stable device to device performance matching in a system that contains multiple AD7606B devices, a symmetrical layout between the AD7606B devices is important. Figure 87 shows a layout with two AD7606B devices. The AVCC supply plane runs to the right of both devices, and the VDRIVE supply track runs to the left of the two devices. The reference chip is positioned between the two devices, and the reference voltage track runs north to Pin 42 of U1 and south to Pin 42 of U2. A solid ground plane is used. AVCC U2 These symmetrical layout principles can also be applied to a system that contains more than two AD7606B devices. The AD7606B devices can be placed in a north/south direction, with the reference voltage located midway between the devices and the reference track running in the north/south direction, similar to Figure 87. 15137-085 U1 Figure 87. Layout for Multiple AD7606B Devices--Top Layer and Supply Plane Layer Rev. 0 | Page 47 of 69 AD7606B Data Sheet REGISTER SUMMARY Table 31. Register Summary Addr Name 0x01 STATUS 0x02 CONFIG Bit 7 RESET_ DETECT RESERVED Bit 6 DIGITAL_ ERROR STATUS_ HEADER Bit 5 Bit 4 EXT_OS_CLOCK RANGE_CH1_ CH2_RANGE CH2 0x04 RANGE_CH3_ CH4_RANGE CH4 0x05 RANGE_CH5_ CH6_RANGE CH6 0x06 RANGE_CH7_ CH8_RANGE CH8 0x08 OVERSAMPLING OS_PAD 0x09 CH1_GAIN RESERVED 0x0A CH2_GAIN RESERVED 0x0B CH3_GAIN RESERVED 0x0C CH4_GAIN RESERVED 0x0D CH5_GAIN RESERVED 0x0E CH6_GAIN RESERVED 0x0F CH7_GAIN RESERVED 0x10 CH8_GAIN RESERVED 0x11 CH1_OFFSET 0x12 CH2_OFFSET 0x13 CH3_OFFSET 0x14 CH4_OFFSET 0x15 CH5_OFFSET 0x16 CH6_OFFSET 0x17 CH7_OFFSET 0x18 CH8_OFFSET 0x19 CH1_PHASE 0x1A CH2_PHASE 0x1B CH3_PHASE 0x1C CH4_PHASE 0x1D CH5_PHASE 0x1E CH6_PHASE 0x1F CH7_PHASE 0x20 CH8_PHASE 0x21 DIGITAL_ INTERFACE_ CLK_FS_OS_ BUSY_STUCK_ DIAG_ENABLE CHECK_EN COUNTER_EN HIGH_ERR_EN Bit 3 Bit 2 RESERVED DOUT_FORMAT R/W CH1_RANGE 0x33 R/W CH3_RANGE 0x33 R/W CH5_RANGE 0x33 R/W CH7_RANGE 0x33 R/W OS_RATIO 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x80 0x80 0x80 0x80 0x80 0x80 0x80 0x80 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x00 R/W 0x00 R/W CH1_GAIN CH2_GAIN CH3_GAIN CH4_GAIN CH5_GAIN CH6_GAIN CH7_GAIN CH8_GAIN CH1_OFFSET CH2_OFFSET CH3_OFFSET CH4_OFFSET CH5_OFFSET CH6_OFFSET CH7_OFFSET CH8_OFFSET CH1_PHASE_OFFSET CH2_PHASE_OFFSET CH3_PHASE_OFFSET CH4_PHASE_OFFSET CH5_PHASE_OFFSET CH6_PHASE_OFFSET CH7_PHASE_OFFSET CH8_PHASE_OFFSET SPI_READ_ SPI_WRITE_ ERR_EN ERR_EN RESERVED CH4_DIAG_MUX_CTRL CH3_DIAG_MUX_CTRL OPEN_ DETECT_ ENABLE CH8_OPEN_ DETECT_EN 0x24 OPEN_ DETECTED AIN_OV_UV_ DIAG_ENABLE AIN_OV_DIAG_ ERROR AIN_UV_DIAG_ ERROR DIAGNOSTIC_ MUX_CH1_2 DIAGNOSTIC_ MUX_CH3_4 0x29 0x08 OPERATION_MODE CH2_DIAG_MUX_CTRL 0x23 0x28 RW R RESERVED DIGITAL_ DIAG_ERR 0x27 Bit 0 ROM_ CRC_ ERR_EN INT_CRC_ERR MM_CRC_ ROM_ ERR CRC_ ERR CH3_OPEN_ CH2_OPEN_ CH1_ DETECT_EN DETECT_EN OPEN_ DETECT_ EN CH3_OPEN CH2_OPEN CH1_ OPEN CH3_OV_ CH2_OV_ CH1_ UV_EN UV_EN OV_UV_ EN CH3_OV_ERR CH2_OV_ERR CH1_ OV_ERR CH3_UV_ERR CH2_UV_ERR CH1_ UV_ERR CH1_DIAG_MUX_CTRL 0x22 0x26 Reset 0x00 RESERVED 0x03 0x25 Bit 1 RESERVED BUSY_STUCK_ HIGH_ERR SPI_READ_ ERR SPI_WRITE_ ERR CH7_OPEN_ DETECT_EN CH6_OPEN_ DETECT_EN CH5_OPEN_ DETECT_EN CH4_OPEN_ DETECT_EN CH8_OPEN CH7_OPEN CH6_OPEN CH5_OPEN CH4_OPEN CH8_OV_ UV_EN CH7_OV_UV_EN CH6_OV_UV_EN CH5_OV_ UV_EN CH4_OV_ UV_EN CH8_OV_ERR CH7_OV_ERR CH6_OV_ERR CH5_OV_ERR CH4_OV_ERR CH8_UV_ERR CH7_UV_ERR CH6_UV_ERR CH5_UV_ERR CH4_UV_ERR Rev. 0 | Page 48 of 69 INT_CRC_ ERR_EN MM_CRC_ ERR_EN Data Sheet Addr Name 0x2A DIAGNOSTIC_ MUX_CH5_6 0x2B DIAGNOSTIC_ MUX_CH7_8 0x2C OPEN_ DETECT_ QUEUE 0x2D FS_CLK_ COUNTER 0x2E OS_CLK_ COUNTER 0x2F ID AD7606B Bit 7 Bit 6 RESERVED Bit 5 RESERVED Bit 4 Bit 3 CH6_DIAG_MUX_CTRL Bit 1 Bit 0 CH5_DIAG_MUX_CTRL Reset 0x00 RW R/W CH7_DIAG_MUX_CTRL 0x00 R/W OPEN_DETECT_QUEUE 0x00 R/W CLK_FS_COUNTER 0x00 R CLK_OS_COUNTER 0x00 R 0x14 R CH8_DIAG_MUX_CTRL DEVICE_ID Bit 2 SILICON_REVISION Rev. 0 | Page 49 of 69 AD7606B Data Sheet REGISTER DETAILS Address: 0x01, Reset: 0x00, Name: STATUS 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7] RESET_DETECT (R) A reset has been detected, either full or partial reset [5:0] RESERVED [6] DIGITAL_ERROR (R) Error present in DIGITAL_DIAG_ERROR register Table 32. Bit Descriptions for STATUS Bits 7 6 [5:0] Bit Name RESET_DETECT DIGITAL_ERROR RESERVED Description A reset has been detected, either full or partial reset. Error present in DIGITAL_DIAG_ERROR register. Reserved. Reset 0x0 0x0 0x0 Access R R R Address: 0x02, Reset: 0x08, Name: CONFIG 7 6 5 4 3 2 1 0 0 0 0 0 1 0 0 0 [7] RESERVED [6] STATUS_HEADER (R/W) Enable STATUS header to be appended to ADC data in both serial and parallel interface [5] EXT_OS_CLOCK (R/W) In oversam pling m ode, enable external oversam pling clock. Oversam pling conversions are triggered through a clock signal applied to CONVST pin, instead of m anaged by the internal oversam pling clock [1:0] OPERATION_MODE (R/W) Operation m ode 00: norm al m ode. 01: standby m ode. 10: autostandby m ode. 11: shutdown m ode. [2] RESERVED [4:3] DOUT_FORMAT (R/W) Num ber of DOUT lines used in serial m ode when reading conversions 00: 1 D OUTx. 01: 2 D OUTx. 10: 4 D OUTx. 11: 1 D OUTx. Table 33. Bit Descriptions for CONFIG Bits 7 6 5 Bit Name RESERVED STATUS_HEADER EXT_OS_CLOCK [4:3] DOUT_FORMAT 2 [1:0] RESERVED OPERATION_MODE Description Reserved. Enable STATUS header to be appended to ADC data in both serial and parallel interface. In oversampling mode, enable external oversampling clock. Oversampling conversions are triggered through a clock signal applied to CONVST pin, instead of managed by the internal oversampling clock. Number of DOUTx lines used in serial mode when reading conversions. 00: 1 DOUTx. 01: 2 DOUTx. 10: 4 DOUTx. 11: 1 DOUTx. Reserved. Operation mode. 00: normal mode. 01: standby mode. 10: autostandby mode. 11: shutdown mode. Rev. 0 | Page 50 of 69 Reset 0x0 0x0 0x0 Access R R/W R/W 0x1 R/W 0x0 0x0 R R/W Data Sheet AD7606B Address: 0x03, Reset: 0x33, Name: RANGE_CH1_CH2 7 6 5 4 3 2 1 0 0 0 1 1 0 0 1 1 [7:4] CH2_RANGE (R/W) Range options for Channel 2 0000: 2.5V single-ended range. 0001: 5V single-ended range. 0010: 10V single-ended range. ... 1101: reserved. 1110: reserved. 1111: reserved. [3:0] CH1_RANGE (R/W) Range options for Channel 1 0000: 2.5V single-ended range. 0001: 5V single-ended range. 0010: 10V single-ended range. ... 1101: reserved. 1110: reserved. 1111: reserved. Table 34. Bit Descriptions for RANGE_CH1_CH2 Bits [7:4] Bit Name CH2_RANGE [3:0] CH1_RANGE Description Range options for Channel 2. 0000: 2.5 V single-ended range. 0001: 5 V single-ended range. 0010: 10 V single-ended range. 0011: 10 V single-ended range. 0100: 10 V single-ended range. 0101: 10 V single-ended range. 0110: 10 V single-ended range. 0111: 10 V single-ended range. 1000: 10 V single-ended range. 1001: 10 V single-ended range. 1010: 10 V single-ended range. 1011: 10 V single-ended range. 1100: reserved. 1101: reserved. 1110: reserved. 1111: reserved. Range options for Channel 1. 0000: 2.5 V single-ended range. 0001: 5 V single-ended range. 0010: 10 V single-ended range. 0011: 10 V single-ended range. 0100: 10 V single-ended range. 0101: 10 V single-ended range. 0110: 10 V single-ended range. 0111: 10 V single-ended range. 1000: 10 V single-ended range. 1001: 10 V single-ended range. 1010: 10 V single-ended range. 1011: 10 V single-ended range. 1100: reserved. 1101: reserved. 1110: reserved. 1111: reserved. Rev. 0 | Page 51 of 69 Reset 0x3 Access R/W 0x3 R/W AD7606B Data Sheet Address: 0x04, Reset: 0x33, Name: RANGE_CH3_CH4 7 6 5 4 3 2 1 0 0 0 1 1 0 0 1 1 [7:4] CH4_RANGE (R/W) Range options for Channel 4 0000: 2.5V single-ended range. 0001: 5V single-ended range. 0010: 10V single-ended range. ... 1101: reserved. 1110: reserved. 1111: reserved. [3:0] CH3_RANGE (R/W) Range options for Channel 3 0000: 2.5V single-ended range. 0001: 5V single-ended range. 0010: 10V single-ended range. ... 1101: reserved. 1110: reserved. 1111: reserved. Table 35. Bit Descriptions for RANGE_CH3_CH4 Bits [7:4] Bit Name CH4_RANGE [3:0] CH3_RANGE Description Range options for Channel 4. 0000: 2.5 V single-ended range. 0001: 5 V single-ended range. 0010: 10 V single-ended range. 0011: 10 V single-ended range. 0100: 10 V single-ended range. 0101: 10 V single-ended range. 0110: 10 V single-ended range. 0111: 10 V single-ended range. 1000: 10 V single-ended range. 1001: 10 V single-ended range. 1010: 10 V single-ended range. 1011: 10 V single-ended range. 1100: reserved. 1101: reserved. 1110: reserved. 1111: reserved. Range options for Channel 3. 0000: 2.5 V single-ended range. 0001: 5 V single-ended range. 0010: 10 V single-ended range. 0011: 10 V single-ended range. 0100: 10 V single-ended range. 0101: 10 V single-ended range. 0110: 10 V single-ended range. 0111: 10 V single-ended range. 1000: 10 V single-ended range. 1001: 10 V single-ended range. 1010: 10 V single-ended range. 1011: 10 V single-ended range. 1100: reserved. 1101: reserved. 1110: reserved. 1111: reserved. Rev. 0 | Page 52 of 69 Reset 0x3 Access R/W 0x3 R/W Data Sheet AD7606B Address: 0x05, Reset: 0x33, Name: RANGE_CH5_CH6 7 6 5 4 3 2 1 0 0 0 1 1 0 0 1 1 [7:4] CH6_RANGE (R/W) Range options for Channel 6 0000: 2.5V single-ended range. 0001: 5V single-ended range. 0010: 10V single-ended range. ... 1101: reserved. 1110: reserved. 1111: reserved. [3:0] CH5_RANGE (R/W) Range options for Channel 5 0000: 2.5V single-ended range. 0001: 5V single-ended range. 0010: 10V single-ended range. ... 1101: reserved. 1110: reserved. 1111: reserved. Table 36. Bit Descriptions for RANGE_CH5_CH6 Bits [7:4] Bit Name CH6_RANGE [3:0] CH5_RANGE Description Range options for Channel 6. 0000: 2.5 V single-ended range. 0001: 5 V single-ended range. 0010: 10 V single-ended range. 0011: 10 V single-ended range. 0100: 10 V single-ended range. 0101: 10 V single-ended range. 0110: 10 V single-ended range. 0111: 10 V single-ended range. 1000: 10 V single-ended range. 1001: 10 V single-ended range. 1010: 10 V single-ended range. 1011: 10 V single-ended range. 1100: reserved. 1101: reserved. 1110: reserved. 1111: reserved. Range options for Channel 5. 0000: 2.5 V single-ended range. 0001: 5 V single-ended range. 0010: 10 V single-ended range. 0011: 10 V single-ended range. 0100: 10 V single-ended range. 0101: 10 V single-ended range. 0110: 10 V single-ended range. 0111: 10 V single-ended range. 1000: 10 V single-ended range. 1001: 10 V single-ended range. 1010: 10 V single-ended range. 1011: 10 V single-ended range. 1100: reserved. 1101: reserved. 1110: reserved. 1111: reserved. Rev. 0 | Page 53 of 69 Reset 0x3 Access R/W 0x3 R/W AD7606B Data Sheet Address: 0x06, Reset: 0x33, Name: RANGE_CH7_CH8 7 6 5 4 3 2 1 0 0 0 1 1 0 0 1 1 [7:4] CH8_RANGE (R/W) Range options for Channel 8 0000: 2.5V single-ended range. 0001: 5V single-ended range. 0010: 10V single-ended range. ... 1101: reserved. 1110: reserved. 1111: reserved. [3:0] CH7_RANGE (R/W) Range options for Channel 7 0000: 2.5V single-ended range. 0001: 5V single-ended range. 0010: 10V single-ended range. ... 1101: reserved. 1110: reserved. 1111: reserved. Table 37. Bit Descriptions for RANGE_CH7_CH8 Bits [7:4] Bit Name CH8_RANGE [3:0] CH7_RANGE Description Range options for Channel 8. 0000: 2.5 V single-ended range. 0001: 5 V single-ended range. 0010: 10 V single-ended range. 0011: 10 V single-ended range. 0100: 10 V single-ended range. 0101: 10 V single-ended range. 0110: 10 V single-ended range. 0111: 10 V single-ended range. 1000: 10 V single-ended range. 1001: 10 V single-ended range. 1010: 10 V single-ended range. 1011: 10 V single-ended range. 1100: reserved. 1101: reserved. 1110: reserved. 1111: reserved. Range options for Channel 7. 0000: 2.5 V single-ended range. 0001: 5 V single-ended range. 0010: 10 V single-ended range. 0011: 10 V single-ended range. 0100: 10 V single-ended range. 0101: 10 V single-ended range. 0110: 10 V single-ended range. 0111: 10 V single-ended range. 1000: 10 V single-ended range. 1001: 10 V single-ended range. 1010: 10 V single-ended range. 1011: 10 V single-ended range. 1100: reserved. 1101: reserved. 1110: reserved. 1111: reserved. Rev. 0 | Page 54 of 69 Reset 0x3 Access R/W 0x3 R/W Data Sheet AD7606B Address: 0x08, Reset: 0x00, Name: OVERSAMPLING 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:4] OS_PAD (R/W) Oversam pling padding, extend the internal oversam pling period allowing evenly spaced sam pling between CONVST rising edges. [3:0] OS_RATIO (R/W) Oversam pling ratio 0: no oversam pling. 1: oversam pling by 2. 10: oversam pling by 4. ... 1101: oversam pling off. 1110: oversam pling off. 1111: oversam pling off. Table 38. Bit Descriptions for OVERSAMPLING Bits [7:4] Bit Name OS_PAD [3:0] OS_RATIO Description Oversampling padding, extend the internal oversampling period allowing evenly spaced sampling between CONVST rising edges. Oversampling ratio. 0: no oversampling. 1: oversampling by 2. 10: oversampling by 4. 11: oversampling by 8. 100: oversampling by 16. 101: oversampling by 32. 110: oversampling by 64. 111: oversampling by 128. 1000: oversampling by 256. 1001: oversampling off. 1010: oversampling off. 1011: oversampling off. 1100: oversampling off. 1101: oversampling off. 1110: oversampling off. 1111: oversampling off. Reset 0x0 Access R/W 0x0 R/W Address: 0x09, Reset: 0x00, Name: CH1_GAIN 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:6] RESERVED [5:0] CH1_GAIN (R/W) R FILTER calibration register. Resolution: 1024 . Range: 0 to 65,536 Table 39. Bit Descriptions for CH1_GAIN Bits [7:6] [5:0] Bit Name RESERVED CH1_GAIN Description Reserved. RFILTER calibration register. Resolution: 1024 . Range: 0 to 65,536 . Reset 0x0 0x0 Access R R/W Reset 0x0 0x0 Access R R/W Address: 0x0A, Reset: 0x00, Name: CH2_GAIN [7:6] RESERVED 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [5:0] CH2_GAIN (R/W) R FILTER calibration register. Resolution: 1024 . Range: 0 to 65,536 Table 40. Bit Descriptions for CH2_GAIN Bits [7:6] [5:0] Bit Name RESERVED CH2_GAIN Description Reserved. RFILTER calibration register. Resolution: 1024 . Range: 0 to 65,536 . Rev. 0 | Page 55 of 69 AD7606B Data Sheet Address: 0x0B, Reset: 0x00, Name: CH3_GAIN 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:6] RESERVED [5:0] CH3_GAIN (R/W) R FILTER calibration register. Resolution: 1024 . Range: 0 to 65,536 Table 41. Bit Descriptions for CH3_GAIN Bits [7:6] [5:0] Bit Name RESERVED CH3_GAIN Description Reserved. RFILTER calibration register. Resolution: 1024 . Range: 0 to 65,536 . Reset 0x0 0x0 Access R R/W Reset 0x0 0x0 Access R R/W Reset 0x0 0x0 Access R R/W Reset 0x0 0x0 Access R R/W Address: 0x0C, Reset: 0x00, Name: CH4_GAIN 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:6] RESERVED [5:0] CH4_GAIN (R/W) R FILTER calibration register. Resolution: 1024 . Range: 0 to 65,536 Table 42. Bit Descriptions for CH4_GAIN Bits [7:6] [5:0] Bit Name RESERVED CH4_GAIN Description Reserved. RFILTER calibration register. Resolution: 1024 . Range: 0 to 65,536 . Address: 0x0D, Reset: 0x00, Name: CH5_GAIN 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:6] RESERVED [5:0] CH5_GAIN (R/W) R FILTER calibration register. Resolution: 1024 . Range: 0 to 65,536 Table 43. Bit Descriptions for CH5_GAIN Bits [7:6] [5:0] Bit Name RESERVED CH5_GAIN Description Reserved. RFILTER calibration register. Resolution: 1024 . Range: 0 to 65,536 . Address: 0x0E, Reset: 0x00, Name: CH6_GAIN [7:6] RESERVED 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [5:0] CH5_GAIN (R/W) R FILTER calibration register. Resolution: 1024 . Range: 0 to 65,536 Table 44. Bit Descriptions for CH6_GAIN Bits [7:6] [5:0] Bit Name RESERVED CH6_GAIN Description Reserved. RFILTER calibration register. Resolution: 1024 . Range: 0 to 65,536 . Rev. 0 | Page 56 of 69 Data Sheet AD7606B Address: 0x0F, Reset: 0x00, Name: CH7_GAIN 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:6] RESERVED [5:0] CH7_GAIN (R/W) R FILTER calibration register. Resolution: 1024 . Range: 0 to 65,536 Table 45. Bit Descriptions for CH7_GAIN Bits [7:6] [5:0] Bit Name RESERVED CH7_GAIN Description Reserved. RFILTER calibration register. Resolution: 1024 . Range: 0 to 65,536 . Reset 0x0 0x0 Access R R/W Reset 0x0 0x0 Access R R/W Address: 0x10, Reset: 0x00, Name: CH8_GAIN 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:6] RESERVED [5:0] CH8_GAIN (R/W) R FILTER calibration register. Resolution: 1024 . Range: 0 to 65,536 Table 46. Bit Descriptions for CH8_GAIN Bits [7:6] [5:0] Bit Name RESERVED CH8_GAIN Description Reserved. RFILTER calibration register. Resolution: 1024 . Range: 0 to 65,536 . Address: 0x11, Reset: 0x80, Name: CH1_OFFSET 7 6 5 4 3 2 1 0 1 0 0 0 0 0 0 0 [7:0] CH1_OFFSET (R/W) Offset register. Range from -128 LSB to +127 LSB. Table 47. Bit Descriptions for CH1_OFFSET Bits [7:0] Bit Name CH1_OFFSET Description Offset register. Range from -128 LSB to +127 LSB. 0x00 = -128 LSB offset; 0x80 = no offset; 0xFF = +127 LSB offset. Reset 0x80 Access R/W Reset 0x80 Access R/W Address: 0x12, Reset: 0x80, Name: CH2_OFFSET 7 6 5 4 3 2 1 0 1 0 0 0 0 0 0 0 [7:0] CH2_OFFSET (R/W) Offset register. Range from -128 LSB to +127 LSB. Table 48. Bit Descriptions for CH2_OFFSET Bits [7:0] Bit Name CH2_OFFSET Description Offset register. Range from -128 LSB to +127 LSB. 0x00 = -128 LSB offset; 0x80 = no offset; 0xFF = +127 LSB offset. Rev. 0 | Page 57 of 69 AD7606B Data Sheet Address: 0x13, Reset: 0x80, Name: CH3_OFFSET 7 6 5 4 3 2 1 0 1 0 0 0 0 0 0 0 [7:0] CH3_OFFSET (R/W) Offset register. Range from -128 LSB to +127 LSB. Table 49. Bit Descriptions for CH3_OFFSET Bits [7:0] Bit Name CH3_OFFSET Description Offset register. Range from -128 LSB to +127 LSB. 0x00 = -128 LSB offset; 0x80 = no offset; 0xFF = +127 LSB offset. Reset 0x80 Access R/W Reset 0x80 Access R/W Reset 0x80 Access R/W Reset 0x80 Access R/W Address: 0x14, Reset: 0x80, Name: CH4_OFFSET 7 6 5 4 3 2 1 0 1 0 0 0 0 0 0 0 [7:0] CH4_OFFSET (R/W) Offset register. Range from -128 LSB to +127 LSB. Table 50. Bit Descriptions for CH4_OFFSET Bits [7:0] Bit Name CH4_OFFSET Description Offset register. Range from -128 LSB to +127 LSB. 0x00 = -128 LSB offset; 0x80 = no offset; 0xFF = +127 LSB offset. Address: 0x15, Reset: 0x80, Name: CH5_OFFSET 7 6 5 4 3 2 1 0 1 0 0 0 0 0 0 0 [7:0] CH5_OFFSET (R/W) Offset register. Range from -128 LSB to +127 LSB. Table 51. Bit Descriptions for CH5_OFFSET Bits [7:0] Bit Name CH5_OFFSET Description Offset register. Range from -128 LSB to +127 LSB. 0x00 = -128 LSB offset; 0x80 = no offset; 0xFF = +127 LSB offset. Address: 0x16, Reset: 0x80, Name: CH6_OFFSET 7 6 5 4 3 2 1 0 1 0 0 0 0 0 0 0 [7:0] CH6_OFFSET (R/W) Offset register. Range from -128 LSB to +127 LSB. Table 52. Bit Descriptions for CH6_OFFSET Bits [7:0] Bit Name CH6_OFFSET Description Offset register. Range from -128 LSB to +127 LSB. 0x00 = -128 LSB offset; 0x80 = no offset; 0xFF = +127 LSB offset. Rev. 0 | Page 58 of 69 Data Sheet AD7606B Address: 0x17, Reset: 0x80, Name: CH7_OFFSET 7 6 5 4 3 2 1 0 1 0 0 0 0 0 0 0 [7:0] CH7_OFFSET (R/W) Offset register. Range from -128 LSB to +127 LSB. Table 53. Bit Descriptions for CH7_OFFSET Bits [7:0] Bit Name CH7_OFFSET Description Offset register. Range from -128 LSB to +127 LSB. 0x00 = -128 LSB offset; 0x80 = no offset; 0xFF = +127 LSB offset. Reset 0x80 Access R/W Reset 0x80 Access R/W Address: 0x18, Reset: 0x80, Name: CH8_OFFSET 7 6 5 4 3 2 1 0 1 0 0 0 0 0 0 0 [7:0] CH8_OFFSET (R/W) Offset register. Range from -128 LSB to +127 LSB. Table 54. Bit Descriptions for CH8_OFFSET Bits [7:0] Bit Name CH8_OFFSET Description Offset register. Range from -128 LSB to +127 LSB. 0x00 = -128 LSB offset; 0x80 = no offset; 0xFF = +127 LSB offset. Address: 0x19, Reset: 0x00, Name: CH1_PHASE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH1_PHASE_OFFSET (R/W) Phase delay from 0 s to 318.75 s in steps of 1.25 s Table 55. Bit Descriptions for CH1_PHASE Bits [7:0] Bit Name CH1_PHASE_OFFSET Description Phase delay from 0 to 318.75 s in steps of 1.25 s. Reset 0x0 Access R/W Reset 0x0 Access R/W Reset 0x0 Access R/W Address: 0x1A, Reset: 0x00, Name: CH2_PHASE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH2_PHASE_OFFSET (R/W) Phase delay from 0 s to 318.75 s in steps of 1.25 s Table 56. Bit Descriptions for CH2_PHASE Bits [7:0] Bit Name CH2_PHASE_OFFSET Description Phase delay from 0 to 318.75 s in steps of 1.25 s. Address: 0x1B, Reset: 0x00, Name: CH3_PHASE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH3_PHASE_OFFSET (R/W) Phase delay from 0 s to 318.75 s in steps of 1.25 s Table 57. Bit Descriptions for CH3_PHASE Bits [7:0] Bit Name CH3_PHASE_OFFSET Description Phase delay from 0 to 318.75 s in steps of 1.25 s. Rev. 0 | Page 59 of 69 AD7606B Data Sheet Address: 0x1C, Reset: 0x00, Name: CH4_PHASE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH4_PHASE_OFFSET (R/W) Phase delay from 0 s to 318.75 s in steps of 1.25 s Table 58. Bit Descriptions for CH4_PHASE Bits [7:0] Bit Name CH4_PHASE_OFFSET Description Phase delay from 0 to 318.75 s in steps of 1.25 s. Reset 0x0 Access R/W Reset 0x0 Access R/W Reset 0x0 Access R/W Reset 0x0 Access R/W Reset 0x0 Access R/W Address: 0x1D, Reset: 0x00, Name: CH5_PHASE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH5_PHASE_OFFSET (R/W) Phase delay from 0 s to 318.75 s in steps of 1.25 s Table 59. Bit Descriptions for CH5_PHASE Bits [7:0] Bit Name CH5_PHASE_OFFSET Description Phase delay from 0 to 318.75 s in steps of 1.25 s. Address: 0x1E, Reset: 0x00, Name: CH6_PHASE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH6_PHASE_OFFSET (R/W) Phase delay from 0 s to 318.75 s in steps of 1.25 s Table 60. Bit Descriptions for CH6_PHASE Bits [7:0] Bit Name CH6_PHASE_OFFSET Description Phase delay from 0 to 318.75 s in steps of 1.25 s. Address: 0x1F, Reset: 0x00, Name: CH7_PHASE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH7_PHASE_OFFSET (R/W) Phase delay from 0 s to 318.75 s in steps of 1.25 s Table 61. Bit Descriptions for CH7_PHASE Bits [7:0] Bit Name CH7_PHASE_OFFSET Description Phase delay from 0 to 318.75 s in steps of 1.25 s. Address: 0x20, Reset: 0x00, Name: CH8_PHASE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CH8_PHASE_OFFSET (R/W) Phase delay from 0 s to 318.75 s in steps of 1.25 s Table 62. Bit Descriptions for CH8_PHASE Bits [7:0] Bit Name CH8_PHASE_OFFSET Description Phase delay from 0 to 318.75 s in steps of 1.25 s. Rev. 0 | Page 60 of 69 Data Sheet AD7606B Address: 0x21, Reset: 0x01, Name: DIGITAL_DIAG_ENABLE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 1 [7] INTERFACE_CHECK_EN (R/W) Enable interface check. Provides a fixed data on each channel when reading ADC data [0] ROM_CRC_ERR_EN (R/W) Enable ROM CRC check [1] MM_CRC_ERR_EN (R/W) Enable m em ory m ap CRC check [6] CLK_FS_OS_COUNTER_EN (R/W) Enable FS and OS clock counter [2] INT_CRC_ERR_EN (R/W) Enable interface CRC check [5] BUSY_STUCK_HIGH_ERR_EN (R/W) Enable busy stuck high check [3] SPI_WRITE_ERR_EN (R/W) Enable checking if attem pting to write to an invalid address [4] SPI_READ_ERR_EN (R/W) Enable checking if attem pting to read from an invalid address Table 63. Bit Descriptions for DIGITAL_DIAG_ENABLE Bits 7 Bit Name INTERFACE_CHECK_EN 6 5 4 3 2 1 0 CLK_FS_OS_COUNTER_EN BUSY_STUCK_HIGH_ERR_EN SPI_READ_ERR_EN SPI_WRITE_ERR_EN INT_CRC_ERR_EN MM_CRC_ERR_EN ROM_CRC_ERR_EN Description Enable interface check. Provides a fixed data on each channel when reading ADC data. Enable FS and OS clock counter. Enable busy stuck high check. Enable checking if attempting to read from an invalid address. Enable checking if attempting to write to an invalid address. Enable interface CRC check. Enable memory map CRC check. Enable ROM CRC check. Reset 0x0 Access R/W 0x0 0x0 0x0 0x0 0x0 0x0 0x1 R/W R/W R/W R/W R/W R/W R/W Address: 0x22, Reset: 0x00, Name: DIGITAL_DIAG_ERR 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:6] RESERVED [5] BUSY_STUCK_HIGH_ERR (R/W1C) Busy stuck high error. Busy line has been at high logic level for longer than 4us [4] SPI_READ_ERR (R/W1C) SPI invalid read address [0] ROM_CRC_ERR (R/W1C) ROM CRC error [1] MM_CRC_ERR (R/W1C) Mem ory m ap CRC error [2] INT_CRC_ERR (R/W1C) Interface CRC error [3] SPI_WRITE_ERR (R/W1C) SPI invalid write address Table 64. Bit Descriptions for DIGITAL_DIAG_ERR Bits [7:6] 5 4 3 2 1 0 Bit Name RESERVED BUSY_STUCK_HIGH_ERR SPI_READ_ERR SPI_WRITE_ERR INT_CRC_ERR MM_CRC_ERR ROM_CRC_ERR Description Reserved. Busy stuck high error. Busy line has been at high logic level for longer than 4 s. SPI invalid read address. SPI invalid write address. Interface CRC error. Memory map CRC error. ROM CRC error. Rev. 0 | Page 61 of 69 Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access R R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C AD7606B Data Sheet Address: 0x23, Reset: 0x00, Name: OPEN_DETECT_ENABLE 5 6 7 1 2 3 4 0 0 0 0 0 0 0 0 0 [7] CH8_OPEN_DETECT_EN (R/W) In autom atic m ode, enable analog input open detection for Channel 8. In m anual m ode, sets the PGA com m on m ode to high [0] CH1_OPEN_DETECT_EN (R/W) In autom atic m ode, enable analog input open detection for Channel 1. In m anual m ode, sets the PGA com m on m ode to high [6] CH7_OPEN_DETECT_EN (R/W) In autom atic m ode, enable analog input open detection for Channel 7. In m anual m ode, sets the PGA com m on m ode to high [1] CH2_OPEN_DETECT_EN (R/W) In autom atic m ode, enable analog input open detection for Channel 2. In m anual m ode, sets the PGA com m on m ode to high [5] CH6_OPEN_DETECT_EN (R/W) In autom atic m ode, enable analog input open detection for Channel 6. In m anual m ode, sets the PGA com m on m ode to high [2] CH3_OPEN_DETECT_EN (R/W) In autom atic m ode, enable analog input open detection for Channel 3. In m anual m ode, sets the PGA com m on m ode to high [4] CH5_OPEN_DETECT_EN (R/W) In autom atic m ode, enable analog input open detection for Channel 5. In m anual m ode, sets the PGA com m on m ode to high [3] CH4_OPEN_DETECT_EN (R/W) In autom atic m ode, enable analog input open detection for Channel 4. In m anual m ode, sets the PGA com m on m ode to high Table 65. Bit Descriptions for OPEN_DETECT_ENABLE Bits 7 Bit Name CH8_OPEN_DETECT_EN 6 CH7_OPEN_DETECT_EN 5 CH6_OPEN_DETECT_EN 4 CH5_OPEN_DETECT_EN 3 CH4_OPEN_DETECT_EN 2 CH3_OPEN_DETECT_EN 1 CH2_OPEN_DETECT_EN 0 CH1_OPEN_DETECT_EN Description In automatic mode, enables analog input open detection for Channel 8. In manual mode, sets the PGA common mode to high. In automatic mode, enables analog input open detection for Channel 7. In manual mode, sets the PGA common mode to high. In automatic mode, enables analog input open detection for Channel 6. In manual mode, sets the PGA common mode to high. In automatic mode, enables analog input open detection for Channel 5. In manual mode, sets the PGA common mode to high. In automatic mode, enables analog input open detection for Channel 4. In manual mode, sets the PGA common mode to high. In automatic mode, enables analog input open detection for Channel 3. In manual mode, sets the PGA common mode to high. In automatic mode, enables analog input open detection for Channel 2. In manual mode, sets the PGA common mode to high. In automatic mode, enables analog input open detection for Channel 1. In manual mode, sets the PGA common mode to high. Reset 0x0 Access R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W Address: 0x24, Reset: 0x00, Name: OPEN_DETECTED 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7] CH8_OPEN (R/W1C) Analog Input 8 open detected [0] CH1_OPEN (R/W1C) Analog Input 1 open detected [6] CH7_OPEN (R/W1C) Analog Input 7 open detected [1] CH2_OPEN (R/W1C) Analog Input 2 open detected [5] CH6_OPEN (R/W1C) Analog Input 6 open detected [2] CH3_OPEN (R/W1C) Analog Input 3 open detected [4] CH5_OPEN (R/W1C) Analog Input 5 open detected [3] CH4_OPEN (R/W1C) Analog Input 4 open detected Table 66. Bit Descriptions for OPEN_DETECTED Bits 7 6 5 4 3 Bit Name CH8_OPEN CH7_OPEN CH6_OPEN CH5_OPEN CH4_OPEN Description Analog Input 8 open detected. Analog Input 7 open detected. Analog Input 6 open detected. Analog Input 5 open detected. Analog Input 4 open detected. Rev. 0 | Page 62 of 69 Reset 0x0 0x0 0x0 0x0 0x0 Access R/W1C R/W1C R/W1C R/W1C R/W1C Data Sheet Bits 2 1 0 Bit Name CH3_OPEN CH2_OPEN CH1_OPEN AD7606B Description Analog Input 3 open detected. Analog Input 2 open detected. Analog Input 1 open detected. Reset 0x0 0x0 0x0 Access R/W1C R/W1C R/W1C Address: 0x25, Reset: 0x00, Name: AIN_OV_UV_DIAG_ENABLE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7] CH8_OV_UV_EN (R/W) Enable overvoltage/undervoltage error check on Channel 8 [0] CH1_OV_UV_EN (R/W) Enable overvoltage/undervoltage error check on Channel 1 [6] CH7_OV_UV_EN (R/W) Enable overvoltage/undervoltage error check on Channel 7 [1] CH2_OV_UV_EN (R/W) Enable overvoltage/undervoltage error check on Channel 2 [5] CH6_OV_UV_EN (R/W) Enable overvoltage/undervoltage error check on Channel 6 [2] CH3_OV_UV_EN (R/W) Enable overvoltage/undervoltage error check on Channel 3 [4] CH5_OV_UV_EN (R/W) Enable overvoltage/undervoltage error check on Channel 5 [3] CH4_OV_UV_EN (R/W) Enable overvoltage/undervoltage error check on Channel 4 Table 67. Bit Descriptions for AIN_OV_UV_DIAG_ENABLE Bits 7 6 5 4 3 2 1 0 Bit Name CH8_OV_UV_EN CH7_OV_UV_EN CH6_OV_UV_EN CH5_OV_UV_EN CH4_OV_UV_EN CH3_OV_UV_EN CH2_OV_UV_EN CH1_OV_UV_EN Description Enable overvoltage/undervoltage error check on Channel 8. Enable overvoltage/undervoltage error check on Channel 7. Enable overvoltage/undervoltage error check on Channel 6. Enable overvoltage/undervoltage error check on Channel 5. Enable overvoltage/undervoltage error check on Channel 4. Enable overvoltage/undervoltage error check on Channel 3. Enable overvoltage/undervoltage error check on Channel 2. Enable overvoltage/undervoltage error check on Channel 1. Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access R/W R/W R/W R/W R/W R/W R/W R/W Address: 0x26, Reset: 0x00, Name: AIN_OV_DIAG_ERROR 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7] CH8_OV_ERR (R/W1C) Overvoltage error on Channel 8 [0] CH1_OV_ERR (R/W1C) Overvoltage error on Channel 1 [6] CH7_OV_ERR (R/W1C) Overvoltage error on Channel 7 [1] CH2_OV_ERR (R/W1C) Overvoltage error on Channel 2 [5] CH6_OV_ERR (R/W1C) Overvoltage error on Channel 6 [2] CH3_OV_ERR (R/W1C) Overvoltage error on Channel 3 [4] CH5_OV_ERR (R/W1C) Overvoltage error on Channel 5 [3] CH4_OV_ERR (R/W1C) Overvoltage error on Channel 4 Table 68. Bit Descriptions for AIN_OV_DIAG_ERROR Bits 7 6 5 4 3 2 1 0 Bit Name CH8_OV_ERR CH7_OV_ERR CH6_OV_ERR CH5_OV_ERR CH4_OV_ERR CH3_OV_ERR CH2_OV_ERR CH1_OV_ERR Description Overvoltage error on Channel 8. Overvoltage error on Channel 7. Overvoltage error on Channel 6. Overvoltage error on Channel 5. Overvoltage error on Channel 4. Overvoltage error on Channel 3. Overvoltage error on Channel 2. Overvoltage error on Channel 1. Rev. 0 | Page 63 of 69 Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C AD7606B Data Sheet Address: 0x27, Reset: 0x00, Name: AIN_UV_DIAG_ERROR 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7] CH8_UV_ERR (R/W1C) Undervoltage error on Channel 8 [0] CH1_UV_ERR (R/W1C) Undervoltage error on Channel 1 [6] CH7_UV_ERR (R/W1C) Undervoltage error on Channel 7 [1] CH2_UV_ERR (R/W1C) Undervoltage error on Channel 2 [5] CH6_UV_ERR (R/W1C) Undervoltage error on Channel 6 [2] CH3_UV_ERR (R/W1C) Undervoltage error on Channel 3 [4] CH5_UV_ERR (R/W1C) Undervoltage error on Channel 5 [3] CH4_UV_ERR (R/W1C) Undervoltage error on Channel 4 Table 69. Bit Descriptions for AIN_UV_DIAG_ERROR Bits 7 6 5 4 3 2 1 0 Bit Name CH8_UV_ERR CH7_UV_ERR CH6_UV_ERR CH5_UV_ERR CH4_UV_ERR CH3_UV_ERR CH2_UV_ERR CH1_UV_ERR Description Undervoltage error on Channel 8. Undervoltage error on Channel 7. Undervoltage error on Channel 6. Undervoltage error on Channel 5. Undervoltage error on Channel 4. Undervoltage error on Channel 3. Undervoltage error on Channel 2. Undervoltage error on Channel 1. Reset 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 Access R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C R/W1C Address: 0x28, Reset: 0x00, Name: DIAGNOSTIC_MUX_CH1_2 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:6] RESERVED [5:3] CH2_DIAG_MUX_CTRL (R/W) Channel 2 diagnostic m ux control. Select 10V range. 000: select analog input pin. 001: select tem perature sensor. Die tem perature = (output voltage - 0.17267)/0.0004832 + 25C. 010: select 2.5V. 011: select ALDO 1.8V x 4. 100: select ALDO 1.8V x 4. 101: select VDRIVE. 110: select AGND. 111: select AVCC . [2:0] CH1_DIAG_MUX_CTRL (R/W) Channel 1 diagnostic m ux control. Select 10V range. 000: select analog input pin. 001: select tem perature sensor. Die tem perature = (output voltage - 0.17267)/0.0004832 + 25C. 010: select 2.5V. 011: select ALDO 1.8V x 4. 100: select DLDO 1.8V x 4. 101: select VDRIVE. 110: select AGND. 111: select AVCC . Table 70. Bit Descriptions for DIAGNOSTIC_MUX_CH1_2 Bits [7:6] [5:3] Bit Name RESERVED CH2_DIAG_MUX_CTRL [2:0] CH1_DIAG_MUX_CTRL Description Reserved. Channel 2 diagnostic mux control. Select 10 V range. 000: select analog input pin. 001: select temperature sensor. Die temperature = (output voltage - 0.17267)/0.0004832 + 25C. 010: select 2.5 V. 011: select ALDO 1.8 V x 4. 100: select ALDO 1.8 V x 4. 101: select VDRIVE. 110: select AGND. 111: select AVCC. Channel 1 diagnostic mux control. Select 10 V range. 000: select analog input pin. 001: select temperature sensor. Die temperature = (output voltage - 0.17267)/0.0004832 + 25C. 010: select 2.5 V. 011: select ALDO 1.8 V x 4. 100: select DLDO 1.8 V x 4. Rev. 0 | Page 64 of 69 Reset 0x0 0x0 Access R R/W 0x0 R/W Data Sheet Bits AD7606B Bit Name Description 101: select VDRIVE. 110: select AGND. 111: select AVCC. Reset Access Reset 0x0 0x0 Access R R/W 0x0 R/W Address: 0x29, Reset: 0x00, Name: DIAGNOSTIC_MUX_CH3_4 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:6] RESERVED [5:3] CH4_DIAG_MUX_CTRL (R/W) Channel 4 diagnostic m ux control. Select 10V range. 000: select analog input pin. 001: select tem perature sensor. Die tem perature = (output voltage - 0.17267)/0.0004832 + 25C. 010: select 2.5V. 011: select ALDO 1.8V x 4. 100: select ALDO 1.8V x 4. 101: select VDRIVE. 110: select AGND. 111: select AVCC . [2:0] CH3_DIAG_MUX_CTRL (R/W) Channel 3 diagnostic m ux control. Select 10V range. 000: select analog input pin. 001: select tem perature sensor. Die tem perature = (output voltage - 0.17267)/0.0004832 + 25C. 010: select 2.5V. 011: select ALDO 1.8V x 4. 100: select ALDO 1.8V x 4. 101: select VDRIVE. 110: select AGND. 111: select AVCC . Table 71. Bit Descriptions for DIAGNOSTIC_MUX_CH3_4 Bits [7:6] [5:3] Bit Name RESERVED CH4_DIAG_MUX_CTRL [2:0] CH3_DIAG_MUX_CTRL Description Reserved. Channel 4 diagnostic mux control. Select 10 V range. 000: select analog input pin. 001: select temperature sensor. Die temperature = (output voltage - 0.17267)/0.0004832 + 25C. 010: select 2.5 V. 011: select ALDO 1.8 V x 4. 100: select ALDO 1.8 V x 4. 101: select VDRIVE. 110: select AGND. 111: select AVCC. Channel 3 diagnostic mux control. Select 10 V range. 000: select analog input pin. 001: select temperature sensor. Die temperature = (output voltage - 0.17267)/0.0004832 + 25C. 010: select 2.5 V. 011: select ALDO 1.8 V x 4. 100: select ALDO 1.8 V x 4. 101: select VDRIVE. 110: select AGND. 111: select AVCC. Rev. 0 | Page 65 of 69 AD7606B Data Sheet Address: 0x2A, Reset: 0x00, Name: DIAGNOSTIC_MUX_CH5_6 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:6] RESERVED [5:3] CH6_DIAG_MUX_CTRL (R/W) Channel 6 diagnostic m ux control. Select 10V range. 000: select analog input pin. 001: select tem perature sensor. Die tem perature = (output voltage - 0.17267)/0.0004832 + 25C. 010: select 2.5V. 011: select ALDO 1.8V x 4. 100: select ALDO 1.8V x 4. 101: select VDRIVE. 110: select AGND. 111: select AVCC . [2:0] CH5_DIAG_MUX_CTRL (R/W) Channel 5 diagnostic m ux control. Select 10V range. 000: select analog input pin. 001: select tem perature sensor. Die tem perature = (output voltage - 0.17267)/0.0004832 + 25C. 010: select 2.5V. 011: select ALDO 1.8V x 4. 100: select ALDO 1.8V x 4. 101: select VDRIVE. 110: select AGND. 111: select AVCC . Table 72. Bit Descriptions for DIAGNOSTIC_MUX_CH5_6 Bits [7:6] [5:3] Bit Name RESERVED CH6_DIAG_MUX_CTRL [2:0] CH5_DIAG_MUX_CTRL Description Reserved. Channel 6 diagnostic mux control. Select 10 V range. 000: select analog input pin. 001: select temperature sensor. Die temperature = (output voltage - 0.17267)/0.0004832 + 25C. 010: select 2.5 V. 011: select ALDO 1.8 V x 4. 100: select ALDO 1.8 V x 4. 101: select VDRIVE. 110: select AGND. 111: select AVCC. Channel 5 diagnostic mux control. Select 10 V range. 000: select analog input pin. 001: select temperature sensor. Die temperature = (output voltage - 0.17267)/0.0004832 + 25C. 010: select 2.5 V. 011: select ALDO 1.8 V x 4. 100: select ALDO 1.8 V x 4. 101: select VDRIVE. 110: select AGND. 111: select AVCC. Rev. 0 | Page 66 of 69 Reset 0x0 0x0 Access R R/W 0x0 R/W Data Sheet AD7606B Address: 0x2B, Reset: 0x00, Name: DIAGNOSTIC_MUX_CH7_8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:6] RESERVED [2:0] CH7_DIAG_MUX_CTRL (R/W) Channel 7 diagnostic m ux control. Select 10V range. 000: select analog input pin. 001: select tem perature sensor. Die tem perature = (output voltage - 0.17267)/0.0004832 + 25C. 010: select 2.5V. 011: select ALDO 1.8V x 4. 100: select ALDO 1.8V x 4. 101: select VDRIVE. 110: select AGND. 111: select AVCC . [5:3] CH8_DIAG_MUX_CTRL (R/W) Channel 8 diagnostic m ux control. Select 10V range. 000: select analog input pin. 001: select tem perature sensor. Die tem perature = (output voltage - 0.17267)/0.0004832 + 25C. 010: select 2.5V. 011: select ALDO 1.8V x 4. 100: select ALDO 1.8V x 4. 101: select VDRIVE. 110: select AGND. 111: select AVCC . Table 73. Bit Descriptions for DIAGNOSTIC_MUX_CH7_8 Bits [7:6] [5:3] Bit Name RESERVED CH8_DIAG_MUX_CTRL [2:0] CH7_DIAG_MUX_CTRL Description Reserved. Channel 8 diagnostic mux control. Select 10 V range. 000: select analog input pin. 001: select temperature sensor. Die temperature = (output voltage - 0.17267)/0.0004832 + 25C. 010: select 2.5 V. 011: select ALDO 1.8 V x 4. 100: select ALDO 1.8 V x 4. 101: select VDRIVE. 110: select AGND. 111: select AVCC. Channel 7 diagnostic mux control. Select 10 V range. 000: select analog input pin. 001: select temperature sensor. Die temperature = (output voltage - 0.17267)/0.0004832 + 25C. 010: select 2.5 V. 011: select ALDO 1.8 V x 4. 100: select ALDO 1.8 V x 4. 101: select VDRIVE. 110: select AGND. 111: select AVCC. Reset 0x0 0x0 Access R R/W 0x0 R/W Reset 0x0 Access R/W Address: 0x2C, Reset: 0x00, Name: OPEN_DETECT_QUEUE 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] OPEN_DETECT_QUEUE (R/W) Num ber of conversions for no change on output codes before enabling open detect function. Range = 2 to 256. Queue = 1 enables m anual m ode Table 74. Bit Descriptions for OPEN_DETECT_QUEUE Bits [7:0] Bit Name OPEN_DETECT_QUEUE Description Number of conversions for no change on output codes before enabling open detect function. Range = 2 to 256. Queue = 1 enables manual mode. Rev. 0 | Page 67 of 69 AD7606B Data Sheet Address: 0x2D, Reset: 0x00, Name: FS_CLK_COUNTER 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CLK_FS_COUNTER (R) Determ ine the frequency of the FS clock oscillator. Counter is increm ented at 16 M/64. Table 75. Bit Descriptions for FS_CLK_COUNTER Bits [7:0] Bit Name CLK_FS_COUNTER Description Determine the frequency of the FS clock oscillator. Counter is incremented at 16 M/64. Reset 0x0 Access R Address: 0x2E, Reset: 0x00, Name: OS_CLK_COUNTER 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:0] CLK_OS_COUNTER (R) Determ ine the frequency of the OS clock oscillator. Counter resolution = 200 kHz. Table 76. Bit Descriptions for OS_CLK_COUNTER Bits [7:0] Bit Name CLK_OS_COUNTER Description Determine the frequency of the OS clock oscillator. Counter resolution = 200 kHz. Reset 0x0 Address: 0x2F, Reset: 0x14, Name: ID 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 [7:4] DEVICE_ID (R) Generic 0000: reserved. 0001: AD7606B Generic. [3:0] SILICON_REVISION (R) Silicon revision Table 77. Bit Descriptions for ID Bits [7:4] Bit Name DEVICE_ID [3:0] SILICON_REVISION Description Generic. 0000: reserved. 0001: AD7606B generic. Silicon revision. Rev. 0 | Page 68 of 69 Reset 0x1 Access R 0x4 R Access R Data Sheet AD7606B OUTLINE DIMENSIONS 0.75 0.60 0.45 12.20 12.00 SQ 11.80 1.60 MAX 64 49 1 48 PIN 1 10.20 10.00 SQ 9.80 TOP VIEW (PINS DOWN) 0.15 0.05 SEATING PLANE 0.20 0.09 7 3.5 0 0.08 COPLANARITY VIEW A 16 33 32 17 VIEW A 0.50 BSC LEAD PITCH 0.27 0.22 0.17 ROTATED 90 CCW COMPLIANT TO JEDEC STANDARDS MS-026-BCD 051706-A 1.45 1.40 1.35 Figure 88. 64-Lead Low Profile Quad Flat Package [LQFP] (ST-64-2) Dimensions shown in millimeters ORDERING GUIDE Model 1 AD7606BBSTZ AD7606BBSTZ-RL EVAL-AD7606BFMCZ EVAL-SDP-CH1Z 1 Temperature Range -40C to +125C -40C to +125C Package Description 64-Lead Low Profile Quad Flat Package [LQFP] 64-Lead Low Profile Quad Flat Package [LQFP] Evaluation Board for the AD7606B Evaluation Controller Board Z = RoHS Compliant Part. (c)2019 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D15137-0-6/19(0) Rev. 0 | Page 69 of 69 Package Option ST-64-2 ST-64-2