ES1021QI - Altera - Datasheet.Live

July 2014 Altera Corporation

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ES1021QI Datasheet

The Altera Enpirion ES1021QI is an integrated 4-channel

controlled-on/controlled-off power-supply sequencer

with supply monitoring, fault protection and a “sequence

completed” signal (RESET). ES1021QI uses a patented,

micropower 7x charge pump to drive four external low-

cost NFET switch gates above the supply rail by 5.3V.

These ICs can be biased from 5V down to 1.5V by any

supply.

ES1021QI has two groups of two channels, each with its

independent I/O. It is ideal for voltage sequencing into

redundant capability loads. All four inputs must be

satisfied before turn-on, but a single group fault is

ignored by the other group.

External resistors provide flexible voltage threshold

programming of monitored rail voltages. Delay and

sequencing are provided by external capacitors for

ramp-up and ramp-down.

Additional I/O is provided for indicating and driving

the RESET state in various configurations.

For volume applications, other programmable options

and features are available.

Features

• Enables Arbitrary Turn-on and Turn-off Sequencing of

Up to Four Power Supplies (0.7V to 5V)

• Operates From 1.5V to 5V Supply Voltage

• Supplies VDD +5.3V of Charge Pumped Gate Drive

• Adjustable Voltage Slew Rate for Each Rail

• Multiple Sequencers Can be Daisy-Chained to Sequence

an Infinite Number of Independent Supplies

• Glitch Immunity

• Undervoltage Lockout for Each Supply

• Active Low ENABLE Input

• Dual Channel Groupings

• QFN Package

• Pb-free (RoHS-compliant)

Applications

•Graphics Cards

• FPGA/ASIC/Microprocessor/PowerPC Supply

Sequencing

•Network Routers

• Telecommunications Systems

FIGURE 1. TYPICAL ES1021QI APPLICATION

V1OUT

V2OUT

V3OUT

V4OUT

UVLO_B

UVLO_A

UVLO_D

UVLO_C

DLY_ON_A

DLY_OFF_A

DLY_OFF_B

DLY_OFF_C

DLY_OFF_D

DLY_ON_B

DLY_ON_C

DLY_ON_D

GATE D

GATE C

GATE B

GATE A

V1

V2

V3

V4

ENABLE_1

ENABLE_2

GROUND

RESET

VDD

RESET_2

FIGURE 2. ES1021QI GROUP INDEPENDENT TURN-OFF AND DELAY

ADJUSTABLE PRE-PROGRAMMED TURN-ON

B_VOUT

C_VOUT

D_VOUT

A_VOUT

EN_2 5V/DIV

EN_1 5V/DIV

Enpirion® Power Datasheet

ES1021QI Power Sequencing Controller

10128 July 9, 2014 Rev A

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Enpirion Power Datasheet ES1021QI Power Sequencing Controller July 2014 Altera Corporation

Ordering Information

PART NUMBER

(Notes 1, 2) PART MARKING TEMP. RANGE (°C)

PACKAGE

(Pb-free) PKG. DWG. #

ES1021QI S1021 -40 to +85 24 Ld 4x4 QFN L24.4x4

NOTES:

1. Add “T” suffix for Tape and Reel. Please refer to Packing and Marking Information: www.altera.com/support/reliability/packing/rel-packing-

and-marking.html

2. These Altera Enpirion Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and

100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering

operations). Altera Enpirion Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free

requirements of IPC/JEDEC J STD-020.

10128 July 9, 2014 Rev A

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Enpirion Power Datasheet ES1021QI Power Sequencing ControllerJuly 2014 Altera Corporation

Block Diagram

FIGURE 3. ES1021QI BLOCK DIAGRAM

ENABLE_1

ENABLE_2

UVLOX

0.633V

RESET

DLY_ONX

1.26V

DLY_OFFX

1.26V

GATEX

LOGIC

1µA

BIAS

LOCK OUT

VDD

RISING DELAY

VDD+5V

Q-PUMP

1µA

1µA -1µA

30µs

FILTER

150ms

RISING DELAY

10ms

RESET_2

10128 July 9, 2014 Rev A

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Enpirion Power Datasheet ES1021QI Power Sequencing Controller July 2014 Altera Corporation

Pin Configurations

ES1021QI

(24 LD QFN)

TOP VIEW

1

2

3

4

5

6

18

17

16

15

14

13

24 23 22 21 20 19

7 8 9 10 11 12

EPAD

ENABLE_1

GATE_A

DLY_OFF_C

DLY_OFF_D

GATE_B

GATE_C

GATE_D

DLY_ON_B

RESET_2

GND

UVLO_B

DLY_OFF_B

UVLO_D

DLY_ON_D

DLY_ON_C

UVLO_C

DLY_OFF_A

NC

UVLO_A

DLY_ON_A

NC

VDD

RESET

(GND)

ENABLE_2

10128 July 9, 2014 Rev A

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Enpirion Power Datasheet ES1021QI Power Sequencing ControllerJuly 2014 Altera Corporation

Pin Descriptions

NAME

NUMBER DESCRIPTION

VDD 23 Chip Bias. Bias IC from nominal 1.5V to 5V.

GND 10 Bias Return. IC ground.

ENABLE_1 1 Input to start on/off sequencing. Input to initiate start of programmed sequencing of supplies on or off. Enable functionality disabled for 10ms

after UVLO is satisfied. ES1021QI has two ENABLE inputs; one for each 2-channel grouping. ENABLE_1 is for (A, B), and ENABLE_2 is for (C, D).

ENABLE_2 11

RESET 24 RESET Output. RESET provides low signal 150ms after all GATEs are fully enhanced. Delay is for stabilization of output voltages. RESET asserts

low upon UVLO not being satisfied or ENABLE being deasserted. RESET outputs are open-drain, N-channel FET and are guaranteed to be in correct

state for VDD down to 1V and are filtered to ignore fast transients on VDD and UVLO_X.

RESET_2 only exists for (C, D) group I/O.

RESET_2 9

UVLO_A 20 Undervoltage Lockout/Monitoring Input. Provides a programmable UV lockout referenced to an internal 0.633V reference. Filtered to ignore short

(<30µs) transients below programmed UVLO level.

UVLO_B 12

UVLO_C 17

UVLO_D 14

DLY_ON_A 21 Gate On Delay Timer Output. Allows programming of delay and sequence for VOUT turn-on using a capacitor to ground. Each capacitor charged

with 1µA 10ms after turn-on initiated by ENABLE/ENABLE. Internal current source provides delay to associated FET GATE turn-on.

DLY_ON_B 8

DLY_ON_C 16

DLY_ON_D 15

DLY_OFF_A 18 Gate Off Delay Timer Output. Allows programming of delay and sequence for VOUT turn-off through ENABLE/ENABLE via a capacitor to ground.

Each capacitor charged with 1µA internal current source to an internal reference voltage, causing corresponding gate to be pulled down, thus

turning off FET.

DLY_OFF_B 13

DLY_OFF_C 3

DLY_OFF_D 4

GATE_A 2 FET Gate Drive Output. Drives external FETs with 1µA current source to soft-start ramp into load.

GATE_B 5

GATE_C 6

GATE_D 7

GND EPAD Ground. Die Substrate. Can be left floating.

NC 19, 22 No Connect

ES1021QI Feature Matrix

PART

NAME EN/EN

CMOS/

TTL

GATE DRIVE

OR OPEN

DRAIN

OUTPUTS

REQUIRED

CONDITIONS

FOR INITIAL

START-UP

NUMBER OF

UVLO INPUTS

MONITORED BY

EACH RESET

NUMBER OF

CHANNELS THAT

TURN OFF WHEN

ONE UVLO

FAULTS

PRESET OR

ADJUSTABLE

SEQUENCE

NUMBER OF

UVLO AND

PAIRS OF I/O FEATURES

ES1021QI EN CMOS Gate Drive 4 UVLO

2 EN

2 UVLO 2 Gates Preset 2 Monitors

with 2 I/O

Dual Redundant

Operation

10128 July 9, 2014 Rev A

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Enpirion Power Datasheet ES1021QI Power Sequencing Controller July 2014 Altera Corporation

Absolute Maximum Ratings (Note 5) Thermal Information

VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.0V

GATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VDD+6V

UVLO, ENABLE. . . . . . . . . . . . . . . . . . . . . . .-0.3V to VDD + 0.3V

RESET, DLY_ON, DLYOFF. . . . . . . . . . . . . .-0.3V to VDD + 0.3V

Operating Conditions

VDD Supply Voltage Range . . . . . . . . . . . . . . . . . . +1.5V to +5.5V

Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . -40°C to +85°C

Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W)

24 Ld 4x4 QFN Package (Notes 3, 4) 46 8

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . +125°C

Maximum Storage Temperature Range . . . . . .-65°C to +150°C

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product

reliability and result in failures not covered by warranty.

NOTES:

3. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features.

4. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.

5. All voltages are relative to GND, unless otherwise specified.

Electrical Specifications VDD = 1.5V to +5V, TA = TJ = -40°C to +85°C, unless otherwise specified. Boldface limits apply over the operating

temperature range, -40°C to +85°C.

PARAMETER SYMBOL TEST CONDITIONS

MIN

(Note 6) TYP

MAX

(Note 6) UNIT

UVLO

Falling Undervoltage Lockout Threshold VUVLOvth TJ = +25°C 619 633 647 mV

Undervoltage Lockout Threshold Tempco TCUVLOvth 40 µV/°C

Undervoltage Lockout Hysteresis VUVLOhys 10 mV

Undervoltage Lockout Threshold Range RUVLOvth Max VUVLOvth- Min VUVLOvth 7mV

Undervoltage Lockout Delay TUVLOdel ENABLE satisfied 10 ms

Transient Filter Duration tFIL VDD, UVLO, ENABLE glitch filter 30 µs

DELAY ON/OFF

Delay Charging Current DLY_ichg VDLY = 0V 0.92 11.08 µA

Delay Charging Current Range DLY_ichg_r DLY_ichg(max) - DLY_ichg(min) 0.08 µA

Delay Charging Current Temperature Coefficient TC_DLY_ichg 0.2 nA/°C

Delay Threshold Voltage DLY_Vth 1.238 1.266 1.294 V

Delay Threshold Voltage Temperature Coefficient TC_DLY_Vth 0.2 mV/°C

ENABLE, RESET

ENABLE Threshold VENh 0.5 VDD V

ENABLE Hysteresis VENh -VENl Measured at VDD = 1.5V 0.2 V

ENABLE Lockout Delay tdelEN_LO UVLO satisfied 10 ms

ENABLE Input Capacitance Cin_en 5 pF

RESET Pull-up Voltage Vpu_rst VDD V

RESET Pull-Down Current IRSTpd1 VDD = 1.5V, RST = 0.1V 5mA

IRSTpd3 VDD = 3.3V, RST = 0.1V 13 mA

IRSTpd5 VDD = 5V, RST = 0.1V 17 mA

RESET Delay after GATE High TRSTdel GATE = VDD+5V 160 ms

10128 July 9, 2014 Rev A

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Enpirion Power Datasheet ES1021QI Power Sequencing ControllerJuly 2014 Altera Corporation

Descriptions and Operation

The ES1021QI sequencer is a 4-channel voltage sequencing controller, and is designed for use in multiple-voltage

systems requiring power sequencing of various supply voltages. Individual voltage rails are gated on and off by

external N-Channel MOSFETs, the gates of which are driven by an internal charge pump to VDD + 5.3V (VQP) in a

user-programmed sequence.

The ES1021QI is a 4-channel device that groups the four channels into two groups of two channels each. Each group

of A, B and C, D, has its own ENABLE and RESET I/O pins. All four UVLO and both ENABLEs must be satisfied for

sequencing to start. The A, B group turns on first, 10ms after the second ENABLE is pulled low, with A then B

turning on, followed by C then D.

Once the preceding GATE = VQP, the next DLY_ON pin starts to charge its capacitor; thus, all four GATEs turn on.

Approximately 160ms after D GATE = VQP, the RESET output is released to go high. Once any UVLO is unsatisfied, only

the related group’s RESET and two GATEs are pulled low. The related EN input must be cycled for the faulted group to

be turned on again.

Normal shutdown is invoked by signaling both ENABLE inputs high, which causes the two related GATEs to shut down

in reverse order from turn-on. DLY_X capacitors adjust the delay between GATES during turn-on and turn-off, but not

the order.

During bias up, the RESET output is guaranteed to be in the correct state, with VDD lower than 1V.

ES1021QI requires that the related ENABLE be cycled for restart of its associated group GATEs. If no capacitors are

connected between DLY_ON or DLY_OFF pins and ground, then all such related GATEs start to turn on immediately

after the 10ms (TUVLOdel) ENABLE stabilization timeout has expired. The GATEs start to turn off immediately when

ENABLE is asserted.

RESET Output Low VRSTlMeasured at VDD = 5V with 5k

pull-up resistors

0.1 V

RESET Output Capacitance COUT_RST 10 pF

GATE

GATE Turn-On Current IGATEon GATE = 0V 0.8 1.1 1.4 µA

GATE Turn-Off Current IGATEoff_l GATE = VDD, Disabled -1.4 -1.05 -0.8 µA

GATE Current Range IGATE_range Within IC IGATE max-min 0.35 µA

GATE Turn-On/Off Current Temperature Coefficient TC_IGATE 0.2 nA/°C

GATE Pull-Down High Current IGATEoff_h GATE = VDD, UVLO = 0V 88 mA

GATE High Voltage VGATEh VDD < 2V, TJ = +25°C VDD + 4.9V V

VGATEh VDD > 2V VDD + 5V VDD + 5.3V V

GATE Low Voltage VGATEl Gate Low Voltage, VDD = 1V 0 0.1 V

BIAS

IC Supply Current IVDD_5V VDD = 5V 0.20 0.5 mA

IVDD_3.3V VDD = 3.3V 0.14 mA

IVDD_1.5V VDD = 1.5V 0.10 mA

VDD Power-on Reset VDD_POR 1V

NOTE:

6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by

characterization and are not production tested.

Electrical Specifications VDD = 1.5V to +5V, TA = TJ = -40°C to +85°C, unless otherwise specified. Boldface limits apply over the operating

temperature range, -40°C to +85°C. (Continued)

PARAMETER SYMBOL TEST CONDITIONS

MIN

(Note 6) TYP

MAX

(Note 6) UNIT

10128 July 9, 2014 Rev A

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Enpirion Power Datasheet ES1021QI Power Sequencing Controller July 2014 Altera Corporation

If some of the rails are sequenced together to reduce cost and eliminate the effect of capacitor variance on the timing, a

common capacitor can be connected to two or more DLY_ON or DLY_OFF pins. In this case, multiply the capacitor value

by the number of common DLY_X pins to obtain the desired timing.

Table 1 shows the nominal time delay on the DLY_X pins for various capacitor values, from the start of charging to the

1.27V reference. This table does not include the 10ms of ENABLE lockout delay during a start-up sequence, but it does

represent the time from the end of the ENABLE lockout delay to the start of GATE transition. There is no ENABLE

lockout delay for a sequence-off, so this table illustrates the delay to GATE transition from a disable signal.

TABLE 1. NOMINAL DELAY TO SEQUENCING THRESHOLD

DLY PIN CAPACITANCE TIME(s)

Open 0.00006

100pF 0.00013

1000pF 0.0013

0.01µF 0.013

0.1µF 0.13

1µF 1.3

10µF 13

NOTE: Nom. TDEL_SEQ = Capacitor (µF)*1.3MW.

10128 July 9, 2014 Rev A

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Enpirion Power Datasheet ES1021QI Power Sequencing ControllerJuly 2014 Altera Corporation

l

Figure 6 demonstrates the independence of the ES1021QI, the redundant 2-rail sequencer. It shows that either one of

the two groups can be turned off, and the ABCD order of restart with capacitor programmable delay, once both EN

inputs are pulled low.

Typical Performance Waveforms

Typical Performance Curves

FIGURE 4. UVLO THRESHOLD VOLTAGE FIGURE 5. DLY CHARGE CURRENT

FIGURE 6. ES1021QI GROUP INDEPENDENT TURN-OFF AND DELAY

ADJUSTABLE PRE-PROGRAMMED TURN-ON

634

633

632

631

628

626

UV THRESHOLD (mV)

TEMPERATURE (°C)

627

-40 0 20 60-20 40 80 100

630

629

VDD = 5V

VDD = 1.5V

DLY CURRENT SOURCE (µA)

-40 0 20 60-20 40 80 100

TEMPERATURE (°C)

1.03

1.02

0.97

0.98

0.99

1.00

1.01

1.04

DLY_OFF/ON

VDD = +5V

VDD = 1.5V

B_VOUT

C_VOUT

D_VOUT

A_VOUT

EN_2 5V/DIV

EN_1 5V/DIV

10128 July 9, 2014 Rev A

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Enpirion Power Datasheet ES1021QI Power Sequencing Controller July 2014 Altera Corporation

1.5V

2.5V

3.3V

+5V

C1

1µF

C2

0.01µF

0.1µF

0.01µF

0.068µF

C4

C5

C3

C7

0.047µF

C8

0.01µF

C6

0.01µF

C9

0.1µF

NC

GND RESET1

RESET2

GATE_D

GATE_C

GATE_B

GATE_A

ISL6123IR

UVLO_A

DLY_OFF_BUVLO_C

UVLO_D

UVLO_B

DLY_OFF_C

DLY_OFF_D

DLY_ON_A

S1

DLY_ON_D

DLY_ON_C

DLY_ON_B

VDD

EN_2

EN_1

4.99k 1.47k

3.01k

R12 R5

EN1

EN2

R1 R2 R4 R6

7.68k 6.98k 8.45k

12

14

17

20

22

19 R9 DNP

R10

750

2

5

6

7

4

3

13

18

21

15

16

8

23

Q1

2

7

1

4Q1

5

78

R9 10 R10 10 R13 10 R14 10

4

2

1

6

8

3

6

Q2

DLY_OFF_A

R3 R11

10

1

11

9

24

2.26k

FIGURE 7. ES1021QI SCHEMATIC

5

3

Q2

4.99k

D1

D2 DNP

RST

RST2

EP

25

10128 July 9, 2014 Rev A

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Enpirion Power Datasheet ES1021QI Power Sequencing ControllerJuly 2014 Altera Corporation

Application Considerations

Timing Error Sources

In any system there are variance contributors. For ES1021QI, timing errors are mainly contributed by three sources.

Capacitor Timing Mismatch Error

Obviously, the absolute capacitor value is an error source; thus, lower-percentage tolerance capacitors help to reduce

this error source. Figure 8 illustrates a difference of 0.57ms between two DLY_X outputs ramping to DLY_X threshold

voltage. These 5% capacitors were from a common source. In applications where two or more GATEs or LOGIC

outputs must have concurrent transitions, it is recommended that a common GATE drive be used to eliminate this

timing error.

FIGURE 8. CAPACITOR TIMING MISMATCH

10128 July 9, 2014 Rev A

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Enpirion Power Datasheet ES1021QI Power Sequencing Controller July 2014 Altera Corporation

DLY_X Threshold Voltage and Charging Current Mismatch

The two other error sources come from the IC itself and are found across the four DLY_X outputs. These errors are the

DLY_X threshold voltage (DLY_Vth) variance when the GATE_X charging and discharging current latches are set, and

the DLY_X charging current (DLY_ichg) variances to determine the time to next sequencing event. Both of these

parameters are bounded by specification. Figure 9 shows that, with a common capacitor, the typical error contributed

by these factors is insignificant, since both DLY_X traces overlay each other.

FIGURE 9. DLY_VTH AND DLY_ICHG TIMING MISMATCH

10128 July 9, 2014 Rev A

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Enpirion Power Datasheet ES1021QI Power Sequencing ControllerJuly 2014 Altera Corporation

Revision History

The table lists the revision history for this document.

DATE REVISION CHANGE

July, 2014 1.0 Initial Release.

10128 July 9, 2014 Rev A

Page 14

Enpirion Power Datasheet ES1021QI Power Sequencing Controller July 2014 Altera Corporation

Package Outline Drawing

L24.4x4

24 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE

Rev 4, 10/06

0 . 90 ± 0 . 1

5

C0 . 2 REF

TYPICAL RECOMMENDED LAND PATTERN

0 . 05 MAX.

( 24X 0 . 6 )

DETAIL "X"

( 24X 0 . 25 )

0 . 00 MIN.

( 20X 0 . 5 )

( 2 . 10 )

SIDE VIEW

( 3 . 8 TYP )

BASE PLANE

4

TOP VIEW

BOTTOM VIEW

712

24X 0 . 4 ± 0 . 1

13

4.00

PIN 1

18

INDEX AREA

24

19

4.00

2.5

0.50

20X

4X

SEE DETAIL "X"

- 0 . 05

+ 0 . 07

24X 0 . 23

2 . 10 ± 0 . 15

PIN #1 CORNER

(C 0 . 25)

1

SEATING PLANE

0.08 C

0.10 C

C

0.10 M C A B

A

B

(4X) 0.15

located within the zone indicated. The pin #1 identifier may be

Unless otherwise specified, tolerance : Decimal ± 0.05

Tiebar shown (if present) is a non-functional feature.

The configuration of the pin #1 identifier is optional, but must be

between 0.15mm and 0.30mm from the terminal tip.

Dimension b applies to the metallized terminal and is measured

Dimensions in ( ) for Reference Only.

Dimensioning and tolerancing conform to AMSE Y14.5m-1994.

6.

either a mold or mark feature.

3.

5.

4.

2.

Dimensions are in millimeters.1.

NOTES:

10128 July 9, 2014 Rev A