1. General description
The 74LVT16374A; 74LVTH16374A a re high performance BiCMOS product s designed for
VCC operation at 3.3 V.
This device is a 16-bit edge-triggered D-type flip-flop featuring non-inverting 3-state
outputs. The device can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the
positive transition of the clock (nCP), the nQn outputs of the flip-flop take on the logic
levels set up at the nDn inputs.
2. Features and benefits
16-bit edge-tr igg er ed flip- flo p
3-state buffers
Output capability: +64 mA and 32 mA
TTL input and output switching levels
Input and output interface capability to systems at 5 V supply
Bus-hold data inputs eliminate the need for external pull-up resistors to hold unused
inputs
Live insertion an d ex tra ct i on perm i tte d
Power-up reset
Power-up 3-state
No bus current loading when output is tied to 5 V bus
Latch-up protection:
JESD78B Class II exceeds 500 mA
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
74LVT16374A; 74LVTH16374A
3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
Rev. 10 — 2 April 2012 Product data sheet
74LVT_LVTH16374A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 10 — 2 April 2012 2 of 19
NXP Semiconductors 74LVT16374A; 74LVTH16374A
3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
3. Ordering information
4. Functional diagram
Table 1. Ordering information
Type number Package
Temperature range Name Description Version
74LVT16374ADL 40 C to +85 C SSOP48 plastic shrink small outline package; 48 l e ad s;
body wid th 7.5 mm SOT370-1
74LVT16374ADGG 40 C to +85 C TSSOP48 plastic thin shrink small outline package;
48 leads; body width 6.1 mm SOT362-1
74LVTH16374ADGG
74LVT16374AEV 40 C to +85 C VFBGA56 plastic very thin fine-pitch ba ll grid array
package; 56 balls; body 4.5 7 0.65 mm SOT702-1
74LVTH16374ABX 40 Cto+125C HXQFN60 plastic compatible thermal enhanced extremely
thin quad flat package; no leads; 60 terminals;
body 4 6 0.5 mm
SOT1134-2
Pin numbers are shown for SSOP48 and TSSOP48
packages only. Pin numbers are shown for SSOP48 and TSSOP48
packages only.
Fig 1. Logic symbol Fig 2. IEC logic symbol
001aac369
1CP
1OE
48
47
1D0
46
1D1
44
1D2
43
1D3
41
1D4
40
1D5
38
1D6
37
2 3 5 6 8 9 11 12
1D7
1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7
1
2CP
2OE
25
36
2D0
35
2D1
33
2D2
32
2D3
30
2D4
29
2D5
27
2D6
26
13 14 16 17 19 20 22 23
2D7
2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7
24
23
001aaa254
37 12
11
9
8
6
5
47
46
44
43
41
40
38
1D7
1D0
1D1
1D2
1D3
1D4
1D5
1D6
2
3
1Q7
1Q6
1Q5
1Q4
1Q3
1Q2
1Q0
1Q1
26
22
20
19
17
16
36
35
33
32
30
29
27
2D5
2D0
2D1
2D2
2D3
2D4
13
14
2Q5
2Q4
2Q3
2Q2
2Q1
2Q0
24
25 EN2
1OE 1EN1
1CP
2OE
2CP
48 C3
C4
3D 1
4D
2D7
2D6
2Q7
2Q6
2
74LVT_LVTH16374A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 10 — 2 April 2012 3 of 19
NXP Semiconductors 74LVT16374A; 74LVTH16374A
3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
5. Pinning information
5.1 Pinning
Fig 3. Logic diagra m
001aac371
D
CP Q
nD0
nCP
nOE
nQ0
D
CP Q
nD1
nQ1
D
CP Q
nD2
nQ2
D
CP Q
nD3
nQ3
D
CP Q
nD4
nQ4
D
CP Q
nD5
nQ5
D
CP Q
nD6
nQ6
D
CP Q
nD7
nQ7
Fig 4. Pin configu ration for SOT370-1 (SSOP48) and
SOT362-1 (TSSOP48) Fig 5. Pi n configuration for SOT702-1 (VFBGA56)
74LVT16374A
74LVTH16374A
1OE 1CP
1Q0 1D0
1Q1 1D1
GND GND
1Q2 1D2
1Q3 1D3
VCC VCC
1Q4 1D4
1Q5 1D5
GND GND
1Q6 1D6
1Q7 1D7
2Q0 2D0
2Q1 2D1
GND GND
2Q2 2D2
2Q3 2D3
VCC VCC
2Q4 2D4
2Q5 2D5
GND GND
2Q6 2D6
2Q7 2D7
2OE 2CP
001aak263
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
001aak264
74LVT16374A
74LVTH16374A
Transparent top view
K
J
H
G
F
E
C
B
A
D
246135
ball A1
index area
74LVT_LVTH16374A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 10 — 2 April 2012 4 of 19
NXP Semiconductors 74LVT16374A; 74LVTH16374A
3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
(1) This is not a supply pin, the substrate is attached to this pad using conductive die attach material. There is no electrical or
mechanical requirement to solder this pad however if it is soldered the solder land should remain floating or be connected to
GND.
Fig 6. Pin configuration SOT1134-2 (HXQFN60)
D1
D3A16A15A14A13A12A11D2
B9
GND
(1)
B10 D7 A17
A18
B11
A19
B12
A20
B13
A21
B14
B8
A10 D6
A9
A8
B7
B6
A7
B5
A6
A22
B15
A23
B16
A24
B17
A25
A26
D8
D4A27
B18
A28A29
B19B20
A30A31A32
B4
A5
B3
B2
B1
D5
A4
A3
A2
A1
74LVT16374A
74LVTH16374A
001aak265
Transparent top view
terminal 1
index area
74LVT_LVTH16374A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 10 — 2 April 2012 5 of 19
NXP Semiconductors 74LVT16374A; 74LVTH16374A
3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
5.2 Pin description
6. Functional description
[1] H = HIGH voltage level;
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW clock transition;
L = LOW voltage level;
l = LOW voltage level one set-up time prior to the HIGH-to-LOW clock transition;
NC = no change;
X = don’t care;
Z = high-impedance OFF-state;
= LOW-to-HIGH clock transition.
Table 2. Pin description
Symbol Pin Description
SOT370-1 and
SOT362-1 SOT702-1 SOT1134-2
1OE, 2OE 1, 24 A1, K1 A30, A13 output enable input (active LOW)
1CP, 2CP 48, 25 A6, K6 A29, A14 clock input
1Q0 to 1Q7 2, 3, 5, 6, 8, 9, 11, 12 B2, B1, C2, C1, D2,
D1, E2, E1 B20, A31, D5, D1, A2,
B2, B3, A5 data output
2Q0 to 2Q7 13, 14, 16, 17, 19, 20,
22, 23 F1, F2, G1, G2, H1,
H2, J1, J2 A6, B5, B6, A9, D2,
D6, A12, B8 data output
GND 4, 10, 15, 21, 28, 34, 39,
45 B3, D3, G3, J3, J4,
G4, D4, B4 A32, A3, A8, A1 1, A16,
A19, A24, A27 groun d (0 V)
VCC 7, 18, 31, 42 C3, H3, H4, C4 A1, A10, A17, A26 supply voltage
1D0 to 1D7 47, 46, 44, 43, 41, 40,
38, 37 B5, B6, C5, C6, D5,
D6, E5, E6 B18, A28, D8, D4,
A25, B16, B15, A22 data input
2D0 to 2D7 36, 35, 33, 32, 30, 29,
27, 26 F6, F5, G6, G5, H6,
H5, J6, J5 A21, B13, B12, A18,
D3, D7, A15, B10 data input
n.c. - A2, A3, A4 , A5,
K2, K3, K4, K5 A4, A7, A20, A23, B1,
B4, B7, B9, B11, B14,
B17, B19
not connected
Table 3. Function table[1]
Operating mode Input Internal register Output
nOE nCP nDn nQ0 to nQ7
Load and read register L lL L
LhH H
Hold L NC X NC NC
Disable outputs H NC X NC Z
HnDn nDn Z
74LVT_LVTH16374A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 10 — 2 April 2012 6 of 19
NXP Semiconductors 74LVT16374A; 74LVTH16374A
3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
7. Limiting values
[1] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
[2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create j unction
temperatures which are detrimental to reliability.
[3] Above 60 C the value of Ptot derates linearly with 5.5 mW/K.
[4] Above 70 C the value of Ptot derates linearly with 1.8 mW/K.
8. Recommended operating conditions
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.5 +4.6 V
VIinput voltage [1] 0.5 +7.0 V
VOoutput voltage output in OFF-state or
HIGH-state [1] 0.5 +7.0 V
IIK input clamping current VI < 0 V 50 - mA
IOK output clamping current VO < 0 V 50 - mA
IOoutput current output in LOW-state - 128 mA
output in HIGH-state 64 - mA
Tstg storage temperature 65 +150 C
Tjjunction temperature [2] - 150 C
Ptot total power dissipation Tamb =40 C to +85 C
(T)SSOP48 pack age [3] - 500 mW
VFBGA56 and HXQFN60
package [4] - 1000 mW
Table 5. Recommended operating con ditions
Symbol Parameter Conditions Min Typ Max Unit
VCC supply voltage 2.7 - 3.6 V
VIinput voltage 0 - 5.5 V
VIH HIGH-level input voltage 2.0 - - V
VIL LOW-level input voltage - - 0.8 V
IOH HIGH-level output current 32 - - mA
IOL LOW-level output current none - - 32 mA
current duty cycle 50 %;
fi1kHz --64mA
Tamb ambient temperature in free-air 40 - +85 C
t/V input transition rise and fall rate outputs enabled - - 10 ns/V
74LVT_LVTH16374A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 10 — 2 April 2012 7 of 19
NXP Semiconductors 74LVT16374A; 74LVTH16374A
3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
9. Static characteristics
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ[1] Max Unit
Tamb = 40 C to +85 C
VIK input clamping voltage VCC = 2.7 V; IIK = 18 mA 1.2 0.85 - V
VOH HIGH-level output voltage IOH =100 A; VCC = 2.7 V to 3.6 V VCC 0.2 VCC -V
IOH = 8mA; V
CC = 2.7 V 2.4 2.5 - V
IOH = 32 mA; VCC = 3.0 V 2.0 2.3 - V
VOL LOW-level output voltage VCC = 2.7 V
IOL = 100 A - 0.07 0.2 V
IOL = 24 mA - 0.3 0.5 V
VCC = 3.0 V
IOL = 16 mA - 0.25 0.4 V
IOL = 32 mA - 0.3 0.5 V
IOL = 64 mA - 0.4 0.55 V
VOL(pu) power-up LOW-level
output voltage VCC = 3.6 V; IO = 1 mA; VI = VCC or GND [2] - 0.1 0.55 V
IIinput leakage current control pins
VCC = 3.6 V; VI = VCC or GND - 0.1 1A
VCC = 0 V or 3.6 V; VI = 5.5 V - 0.4 10 A
input da ta pins [3]
VCC = 0 V or 3.6 V; VI = 5.5 V - 0.4 10 A
VCC = 3.6 V; VI = VCC -0.11A
VCC = 3.6 V; VI = 0 V 50.4 - A
IOFF power-off leakage current VCC = 0 V; VI or VO = 0V to4.5V - 0.1 100 A
IBHL bus hold LOW curre nt VCC = 3 V; VI = 0.8 V 75 135 - A
IBHH bus hold HIGH curr ent VCC = 3 V; VI = 2.0 V - 135 75 A
IBHLO bus hold LOW
overdrive current input data pins;
VI=0Vto3.6V;V
CC =3.6V [4] 500 - - A
IBHHO bus hold HIGH
overdrive current input data pins;
VI=0Vto3.6V;V
CC =3.6V [4] --500 A
ILO output leakage current output in HIGH-state when VO>V
CC;
VO= 5.5 V; VCC =3.0V - 50 125 A
IO(pu/pd) power-up/power-down
output current VCC 1.2 V; VO= 0.5 V to VCC; VI= GND or
VCC; nOE = don’t care [5] -1100 A
IOZ OFF-st ate output cur r en t VCC = 3.6 V; VI = VIH or VIL
output HIGH: VO = 3.0 V - 0.5 5 A
output LOW: VO = 0.5 V 50.5-A
ICC supply current VCC = 3.6 V; VI = GND or VCC; IO=0A
outputs HIGH - 0.07 0.12 mA
outputs LOW - 4.0 6.0 mA
outputs disabled [6] - 0.07 0.12 mA
74LVT_LVTH16374A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 10 — 2 April 2012 8 of 19
NXP Semiconductors 74LVT16374A; 74LVTH16374A
3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
[1] Typical values are measured at VCC = 3.3 V and at Tamb = 25 C.
[2] For valid test results, data must not be loaded into the flips-flops (or latches) after applying power.
[3] Unused pins at VCC or GND.
[4] This is the bus hold overdrive current required to force the input to the opposite logic state.
[5] This parameter is valid for any VCC between 0 V and 1.2 V with a transition time of up to 10 ms. From VCC = 1.2 V to VCC = 3.3 V 0.3 V
a transition time of 100 s is permitted. This parameter is valid for Tamb = 25 C only.
[6] ICC is measured with outputs pulled to VCC or GND.
[7] This is the increase in supply current for each input at the specified voltage level other than VCC or GND.
10. Dynamic characteristics
ICC additional supply current per input pin; VCC = 3.0 V to 3.6 V; one input
at VCC 0.6 V, other inputs at VCC or GND [7] -0.10.2mA
CIinput capacitance input pins; VI = 0 V or 3.0 V - 3 - pF
COoutput capacitance output pins nQn; outputs disabled;
VO=0VorV
CC
-9-pF
Table 6. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Typ[1] Max Unit
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 10.
Symbol Parameter Conditions Min Typ[1] Max Unit
Tamb = 40 C to +85 C
fmax maximum frequency nCP; VCC = 3.3 V 0.3 V; see Figure 7 150 - - MHz
tPLH LOW to HIGH
propagation delay nCP to nQn; see Figure 7
VCC = 3.3 V 0.3 V 1.5 2.9 5.0 ns
VCC = 2.7 V - - 5.6 ns
tPHL HIGH to LOW
propagation delay nCP to nQn; see Figure 7
VCC = 3.3 V 0.3 V 1.5 3.0 5.0 ns
VCC = 2.7 V - - 5.6 ns
tPZH OFF-state to HIGH
propagation delay nOE to nQn; see Figure 8
VCC = 3.3 V 0.3 V 1.5 3.2 4.8 ns
VCC = 2.7 V - - 6.0 ns
tPZL OFF-state to LOW
propagation delay nOE to nQn; see Figure 8
VCC = 3.3 V 0.3 V 1.5 3.0 4.6 ns
VCC = 2.7 V - - 5.2 ns
tPHZ HIGH to OFF-state
propagation delay nOE to nQn; see Figure 8
VCC = 3.3 V 0.3 V 1.5 3.9 5.4 ns
VCC = 2.7 V - - 6.0 ns
tPLZ LOW to OFF-state
propagation delay nOE to nQn; see Figure 8
VCC = 3.3 V 0.3 V 1.5 3.4 4.6 ns
VCC = 2.7 V - - 5.0 ns
74LVT_LVTH16374A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 10 — 2 April 2012 9 of 19
NXP Semiconductors 74LVT16374A; 74LVTH16374A
3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
[1] All typical values are at VCC = 3.3 V and Tamb = 25 C.
[2] tsu is the same as tsu(H) and tsu(L).
[3] th is the same as th(H) and th(L).
[4] tW is the same as tW(H) and tW(L).
11. Waveforms
tsu set-up time nDn to nCP; HIGH or LOW; see Figure 9 [2]
VCC = 3.3 V 0.3 V 2.0 0.7 - ns
VCC = 2.7 V 2.0 - - ns
thhold time nDn to nCP; HIGH or LOW; see Figure 9 [3]
VCC = 3.3 V 0.3 V 0.8 0 - ns
VCC = 2.7 V 0.1 - - ns
tWpulse width nCP HIGH; see Figure 7 [4]
VCC = 3.3 V 0.3 V 1.5 0.6 - ns
VCC = 2.7 V 1.5 - - ns
nCP LOW; see Figure 7
VCC = 3.3 V 0.3 V 3.0 1.6 - ns
VCC = 2.7 V 3.0 - - ns
Table 7. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 10.
Symbol Parameter Conditions Min Typ[1] Max Unit
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 7. Pro pagation delay clock input to ou tput, clock pulse width and maximum clock frequency
001aaa256
nCP input
nQn output
t
PHL
t
PLH
t
W
V
OH
V
I
GND
V
OL
V
M
V
M
V
M
1/f
max
Table 8. Measurement points
Input Output
VMVMVXVY
1.5 V 1.5 V VOL + 0.3 V V OH 0.3 V
74LVT_LVTH16374A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 10 — 2 April 2012 10 of 19
NXP Semiconductors 74LVT16374A; 74LVTH16374A
3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
Measurements points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 8. Enable an d disable times
001aae464
tPZL
nYn output
nYn output
nOE input
VOL
VOH
3.0 V
VI
VM
GND
0 V
tPLZ
tPZH tPHZ
VX
VY
VM
VM
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Remark: The shaded areas indicate when the input is permitted to change for predictable output performance.
Fig 9. Dat a set-u p an d hold times
74LVT_LVTH16374A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 10 — 2 April 2012 11 of 19
NXP Semiconductors 74LVT16374A; 74LVTH16374A
3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
Test data is given in Table 9.
Definitions test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
VEXT = Test voltage for switching times.
Fig 10. Test circuit for measuring switching times
VEXT
VCC
VIVO
001aae235
DUT
CL
RT
RL
RL
PULSE
GENERATOR
VMVM
tW
tW
10 %
90 %
0 V
VI
VI
negative
pulse
positive
pulse
0 V
VMVM
90 %
10 %
tf
tr
tr
tf
Table 9. Test data
Input Load VEXT
VIfitWtr, tfCLRLtPHZ, tPZH tPLZ, tPZL tPLH, tPHL
2.7 V 10 MHz 500 ns 2.5 ns 50 pF 500 GND 6 V open
74LVT_LVTH16374A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 10 — 2 April 2012 12 of 19
NXP Semiconductors 74LVT16374A; 74LVTH16374A
3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
12. Package outline
Fig 11. Package outline SOT370-1 (SSOP48)
UNIT A1A2A3bpcD
(1) E(1) eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.4
0.2 2.35
2.20 0.25 0.3
0.2 0.22
0.13 16.00
15.75 7.6
7.4 0.635 1.4 0.25
10.4
10.1 1.0
0.6 1.2
1.0 0.85
0.40 8
0
o
o
0.18 0.1
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
SOT370-1 99-12-27
03-02-19
(1)
wM
bp
D
HE
E
Z
e
c
vMA
X
A
y
48 25
MO-118
24
1
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
pin 1 index
0 5 10 mm
scale
SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm SOT370-1
A
max.
2.8
74LVT_LVTH16374A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 10 — 2 April 2012 13 of 19
NXP Semiconductors 74LVT16374A; 74LVTH16374A
3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
Fig 12. Package outline SOT362-1 (TSSOP48)
UNIT A1A2A3bpcD
(1) E(2) eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.15
0.05 0.2
0.1 8
0
o
o
0.1
DIMENSIONS (mm are the original dimensions).
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
SOT362-1 99-12-27
03-02-19
wM
θ
A
A1
A2
D
Lp
Q
detail X
E
Z
e
c
L
X
(A )
3
0.25
124
48 25
y
pin 1 index
b
H
1.05
0.85 0.28
0.17 0.2
0.1 12.6
12.4 6.2
6.0 0.5 1 0.25
8.3
7.9 0.50
0.35 0.8
0.4
0.08
0.8
0.4
p
EvMA
A
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm SOT362-1
A
max.
1.2
0
2.5
5 mm
scale
MO-153
74LVT_LVTH16374A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 10 — 2 April 2012 14 of 19
NXP Semiconductors 74LVT16374A; 74LVTH16374A
3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
Fig 13. Package outline SOT702-1 (VFBGA56)
0.65
A1bA2
UNIT D ye
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
02-08-08
03-07-01
IEC JEDEC JEITA
mm 10.3
0.2 0.7
0.6 4.6
4.4
y1
7.1
6.9
0.45
0.35 0.08 0.1
e1
3.25
e2
5.85
DIMENSIONS (mm are the original dimensions)
SOT702-1 MO-225
E
0.15
v
0.08
w0 2.5 5 mm
scale
SOT702-1
VFBGA56: plastic very thin fine-pitch ball grid array package; 56 balls; body 4.5 x 7 x 0.65 mm
A
max.
AA2
A1
detail X
y
y1C
e
e
b
X
D
E
C
A
B
C
D
E
F
H
G
J
K
246135
ball A1
index area
BA
e2
e1
1/2 e
1/2 e
AC
CB
∅ vM
∅ wM
ball A1
index area
74LVT_LVTH16374A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 10 — 2 April 2012 15 of 19
NXP Semiconductors 74LVT16374A; 74LVTH16374A
3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
Fig 14. Package outline SOT1134-2 (HXQFN60)
References
Outline
version European
projection Issue date
IEC JEDEC JEITA
SOT1134-2 - - -
- - -
- - -
sot1134-2_po
11-08-15
Unit
mm max
nom
min
0.50 0.08
0.05
0.02
0.28
0.23
0.18
1.95
1.85
1.75
6.1
6.0
5.9
3.95
3.85
3.75 1.0 2.5 4.5 0.195
0.145
0.095 0.1
A
Dimensions
HXQFN60: plastic compatible thermal enhanced extremely thin quad flat package; no leads;
60 terminals; body 4 x 6 x 0.5 mm SOT1134-2
A1A2
0.42
0.40
0.38
bD
4.1
4.0
3.9
DhEE
h
0.08 0.1
yy
1
e
0.5
e1e2e3
3.0
e4eT
0.49
eR
0.5
K
0.25
0.20
0.15
L
0.28
0.23
0.18
L1v
0.05
w
0 5 mm
terminal 1
index area
BA
D
E
C
y
C
y1
X
detail X
A A2
A1
terminal 1
index area
e2
e1
eT
eR
eT
eR
e4
e3
e
e
1/2 e
1/2 e
AC B
vC
w
bAC B
vC
w
Dh
K
L
Eh
L1
B1
A1
B7
D5 D8
D6 D7
D1 D4
D2 D3
B20 B18 A27
A26
A17
B11
B17
A11 B8 B10 A16
A32
A10
eR
eT
eR
eT
74LVT_LVTH16374A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 10 — 2 April 2012 16 of 19
NXP Semiconductors 74LVT16374A; 74LVTH16374A
3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
13. Abbreviations
14. Revision history
Table 10. Abbreviations
Acronym Description
BiCMOS Bipolar Complementary Metal Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
TTL Tra nsistor-Transistor Logic
Table 11. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74LVT_LVTH16374A v.10 20120402 Product data sheet - 74LVT_LVTH16374A v.9
Modifications: •For type number 74LVTH16374ABX the sot code has changed to SOT1134-2.
74LVT_LVTH16374A v.9 20111122 Product data sheet - 74LVT_LVTH16374A v.8
Modifications: •Legal pages updated.
74LVT_LVTH16374A v.8 20110620 Product data sheet - 74LVT_LVTH16374A v.7
74LVT_LVTH16374A v.7 20100322 Product data sheet - 74LVT_LVTH16374A v.6
74LVT_LVTH16374A v.6 20100118 prod uct data sheet - 74LVT16374A v.5
74LVT16374A v.5 200409 16 product data sheet - 74LVT16374A v.4
74LVT16374A v.4 20021101 product specification - 74LVT16374A v.3
74LVT16374A v.3 199910 18 product specific ation - 74LVT16374A v.2
74LVT16374A v.2 19980219 product specification - -
74LVT_LVTH16374A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 10 — 2 April 2012 17 of 19
NXP Semiconductors 74LVT16374A; 74LVTH16374A
3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
15. Legal information
15.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and
full information. For detailed and full informatio n see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall pre vail.
Product specificat io n — The information and data provided in a Product
data sheet shall define the specification of the product as agr eed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond those described in the
Product data sheet.
15.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Se miconductors takes no
responsibility for the content in this document if provided by an inf ormation
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequ ential damages (including - wit hout limitatio n - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ ag gregate and cumulative l iability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors pro duct can reasonably be expected
to result in perso nal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconducto rs products in such equipment or
applications and ther efore such inclu sion and/or use is at the cu stomer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty tha t such application s will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for the custome r’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with t heir
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessa ry
testing for th e customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by cust omer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter ms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing i n this document may be interpreted or
construed as an of fer t o sell product s that is open for accept ance or t he grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property right s.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specification.
Product [short] dat a sheet Production This document contains the product specification.
74LVT_LVTH16374A All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 10 — 2 April 2012 18 of 19
NXP Semiconductors 74LVT16374A; 74LVTH16374A
3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for aut omo tive use. It i s neit her qua lif ied nor test ed
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applicati ons.
In the event that customer uses the product for design-in and use in
automotive applications to automot ive specifications and standard s, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting f rom customer design an d
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
15.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors 74LVT16374A; 74LVTH16374A
3.3 V 16-bit edge-triggered D-type flip-flop; 3-state
© NXP B.V. 2012. All rights reserved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 2 April 2012
Document identifier: 74LVT_LVTH16374A
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
17. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 2
4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
6 Functional description . . . . . . . . . . . . . . . . . . . 5
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6
8 Recommended operating conditions. . . . . . . . 6
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 7
10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 8
11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 12
13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 16
14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 16
15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 17
15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 17
15.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 17
15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 18
16 Contact information. . . . . . . . . . . . . . . . . . . . . 18
17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19