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FAN9673 Three-Channel Interleaved CCM PFC Controller Features Description Continuous Conduction Mode Control Programmable PFC Output Voltage The FAN9673 is an interleaved three-channel Continuous Conduction Mode (CCM) Power Factor Correction (PFC) controller IC intended for PFC preregulators. Incorporating circuits for the implementation of leading edge, average current, and "boost"-type power factor correction; the FAN9673 enables the design of a power supply that fully complies with the IEC1000-3-2 specification. Interleaved operation provides substantial reduction in the input and output ripple currents and the conducted EMI filtering becomes easier and cost effective. Sag Protection Three-Channel PFC Control (Maximum) Average Current-Mode Control PFC Slave Channel Management Function Programmable Operation Frequency Range: 18 kHz~40 kHz or 55 kHz~75 kHz Two Current Limit Functions An innovative channel management function allows the power level of the slave channels to be loaded and unloaded smoothly according to the setting voltage on the CM pin, improving the PFC converter's load transient response. TriFault DetectTM Protects Against Feedback Loop Failure Programmable Soft-Start The FAN9673 also incorporates a variety of protection functions, including: peak current limiting, input voltage brown out protection, and TriFault DetectTM function. Under-Voltage Lockout (UVLO) Differential Current Sensing Available in 32-Pin LQFP Package Applications High Power AC-DC Power Supply DC Motor Power Supply White Goods; e.g. Air Conditioner Power Supply Server and Telecom Power Supply UPS Industrial Welding and Power Supply Ordering Information Part Number FAN9673Q FAN9673QX Operating Temperature Range -40C to 105C (c) 2013 Fairchild Semiconductor Corporation FAN9673 * Rev. 1.4 Package 32LD, LQFP, JEDEC MS-026, Variation BBA, 7 mm Square Packing Method Tray Tape & Reel www.fairchildsemi.com 1 FAN9673 -- Three-Channel Interleaved CCM PFC Controller June 2016 * DBP RB1 VIN LPFC1 DPFC1 LPFC2 DPFC2 LPFC3 DPFC3 VPFC CB+ AC Line In RFB1 COUT EMI Filter RFB2 RB1 SPFC1 RA1 SPFC2 SPFC3 RF RSEN3 CFB3 Driver Circuit RA2 RSEN2 Driver Circuit RB2 Driver Circuit RSEN1 RFB3 CF1 CF2 RB3 OPFC1 CS1+ CS1- OPFC2 CS2+ CS2- OPFC3 CS3+ IAC CS3FBPFC CVC2 BIBO CB1 CB2 VEA CSS RB4 SS CILIMIT2 RILIMIT2 IEA1 ILIMIT2 FAN9673 MCU RDY MCU signal (DC) PVO IEA2 IEA3 CGC CVC1 CIC12 RIC1 CIC11 CVI22 RIC2 CIC21 CIC32 LS RLS RVC1 RIC3 CIC31 VDD GC RGC CVDD LPK CM1 CM2 CM3 GND RLPK RI ILIMIT VIR Standby Power RRI MCU CLPK RILIMIT RRLPK RLPK Channel Enable CRLPK CVIR RVIR CILIMIT * About DBP please reference System Design Precautions Figure 1. (c) 2013 Fairchild Semiconductor Corporation FAN9673 * Rev. 1.4 Typical Application Diagram for Three-Channel PFC Converter www.fairchildsemi.com 2 FAN9673 -- Three-Channel Interleaved CCM PFC Controller Typical Application PVO FBPFC ILIMIT ILIMIT2 VDD VIR SS 29 3 7 28 16 31 SS 2 10uA GMV VEA 30 1.2V / RRI 2.5V 1/4X B VDD 24V/23V VDD OVP 0.3V VVEA VEA LPD 20uA VVIR < 1.5V, FR VVIR > 3.5V, HV Brown Out, Protection 60uA VEA 0.5V LPK 8 Peak Detector C RLPK 6 IAC 32 IEA1 10 CS1+ 23 CS1- 22 VFBPFC RM A 2.75V/2.5V Imo Ratio VBIBO-UVP - VBIBO-UVP VBIBO VVEA > VSS PFC UVP PFC OVP AC UVP ILIMIT2 CS1 S R CM1 GMI1 S LPT1 R SET Q Q CLR SET 27 OPFC1 26 OPFC2 25 OPFC3 9 RDY Q Q CLR IEA_SAW1 Dead1 IEA2 11 CS2+ 21 CS2- 20 CM2 GMI2 S LPT2 R 19 CS3- 18 LS 17 GC 4 SET Q Q CLR SET Q Q CLR IEA_SAW2 12 CS3+ S R Dead2 IEA3 ILIMIT2 CS2 ILIMIT2 CS3 S R CM3 GMI3 S R LPT3 SET Q Q CLR SET Q Q CLR 5V IEA_SAW3 55uA 13 CM1 14 CM2 55uA UVLO VDD Dead3 Brown In /Out FR: 1.05V/1.9V HV: 1.05V/1.75V Oscillator VGMVFR: 2.4V/1.25V HV: 2.4/1.55V FAN9673 -- Three-Channel Interleaved CCM PFC Controller Block Diagram 55uA 15 5 1 24 CM3 RI BIBO GND * FR: Full Range AC Input, AC85V~264V HV: High Voltage Range AC Input, AC180~264V Figure 2. (c) 2013 Fairchild Semiconductor Corporation FAN9673 * Rev. 1.4 Functional Block Diagram www.fairchildsemi.com 3 16 LS 15 CS3- 14 CS3+ 13 CS2- CM2 CM1 FBPFC 12 CS2+ CM3 IEA3 VEA IEA2 SS IEA1 IAC RDY ZXYTT 4 5 GC RI 6 7 8 LPK 3 ILIMIT2 2 RLPK 1 ILIMIT FAN9673 TM PVO VDD BIBO OPFC1 27 OPFC2 28 OPFC3 26 VIR 11 CS1- 17 10 CS1+ 18 9 GND 19 25 20 29 21 30 22 31 23 32 24 Figure 3. F - Fairchild Logo Z - Plant Code X - 1-Digit Year Code Y - 1-Digit Week Code TT - 2-Digit Die Run Code T - Package Type (Q:LQFP) M - Manufacture Flow Code Pin Layout (Top View) Pin Definitions Pin # Name Description 1 BIBO Brown In /Out Level Setting. This pin is used for brown in /out setting. 2 PVO Programmable Output Voltage. DC voltage from a microcontroller (MCU) can be applied to this pin to program the output voltage level. The operation range is 3.5 V ~ 0.5 V. If VPVO < 0.5 V, the PVO function is disabled. 3 ILIMIT Current Command Clamp Setting. Average current mode is to control average value of inductor current by a current command. Connecting a resistor and a capacitor to this pin can determine a limit value of the current command. 4 GC Setting of Gain Modulator. A resistor, connected from this pin to ground, is used to adjust the output level of the gain modulator. A small capacitor connected from this pin to GND is recommended for noise filtering. 5 RI Oscillator Setting. There are two oscillator frequency ranges: 18 k~40 kHz and 50 k~75 kHz. A resistor connected from RI to ground determines the switching frequency. A resistor value between 10.6 k ~ 44.4 k is recommended. 6 RLPK 7 FAN9673 -- Three-Channel Interleaved CCM PFC Controller Pin Configuration / Marking Information Ratio of VLPK and VIN. Connect a resistor and a capacitor to this pin to adjust the ratio of VIN peak to VLPK. Typical value is 12.4 k (1:100 of VLPK and VIN peak). The accuracy of VLPK is primarily determined by the tolerance of RRLPK at this pin. Peak Current Limit Setting. Connect a resistor and a capacitor to this pin to set the over-current ILIMIT2 limit threshold and to protect power devices from damage due to inductor saturation. This pin sets the over-current threshold for cycle-by-cycle current limit. 8 LPK Peak of Line Voltage. This pin can be used to provide information about the peak amplitude of the line voltage to an MCU. 9 RDY Output Ready Signal. When the feedback voltage on FBPFC reaches 2.4 V, the RDY pin outputs a high VRDY signal to inform the MCU that the downstream power stage can start normal operation. If AC brownout is detected, the VRDY signal is LOW to signal to the MCU it is not ready. Continued on the following page... (c) 2013 Fairchild Semiconductor Corporation FAN9673 * Rev. 1.4 www.fairchildsemi.com 4 Pin # Name Description 10 IEA1 Output 1 of PFC Current Amplifier. The signal from this pin is compared with an internal sawtooth to determine the pulse width for PFC gate drive 1. 11 IEA2 Output 2 of PFC Current Amplifier. The signal from this pin is compared with an internal sawtooth to determine the pulse width for PFC gate drive 2. 12 IEA3 Output 3 of PFC Current Amplifier. The signal from this pin is compared with an internal sawtooth to determine the pulse width for PFC gate drive 3. 13 CM1 Channel 1 Management Setting. This pin is used to configure the characteristic of PFC enable / disable. "PFC Enabling" pull voltage on this pin is LOW (=0 V) to enable and HIGH (>4 V) to disable the whole PFC system. 14 CM2 Channel 2 Management Setting. There are two control methods for channel 2. The first uses an external signal to enable / disable channel 2 (VCM2 =0 V / VCM2 >4 V). The second is linear increase / decrease loading of channel 2 when power level, VVEA, triggers the setting level of VCM2. 15 CM3 Channel 3 Management Setting. There are two control methods for channel 3. The first uses an external signal to enable / disable channel 3 (VCM2 =0 V / VCM2 >4 V). The second is linear increase / decrease loading of channel 3 when power level, V VEA, triggers the setting level of VCM3. 16 VIR Input Voltage Range Setting. A capacitor and a resistor are connected in parallel from this pin to GND. When VVIR > 3.5 V, the PFC controller only works for the high-voltage input range (180 VAC ~ 264 VAC) and RIAC must be 12 M. When VVIR < 1.5 V, the PFC controller works for the full line voltage range (90 VAC ~ 264 VAC) and RIAC must be 6 M. Voltage 1.5 V to 3.5 V is not allowed. 17 LS Setting for Current Predict Function. A resistor, connected from this pin to ground, is used to adjust the compensation of the linear predict function (LPT). A small capacitor connected from this pin to GND is recommended for noise filtering. 18 CS3- Negative PFC Current Sense3 Input 19 CS3+ Positive PFC Current Sense3 Input 20 CS2- Negative PFC Current Sense2 Input 21 CS2+ Positive PFC Current Sense2 Input 22 CS1- Negative PFC Current Sense1 Input 23 CS1+ Positive PFC Current Sense1 Input 24 GND Ground 25 OPFC3 PFC Gate Drive 3. The totem-pole output drive for the PWM MOSFET or IGBT. This pin has an internal 15 V clamp to protect the external power switch. 26 OPFC2 PFC Gate Drive 2. The totem-pole output drive for the PWM MOSFET or IGBT. This pin has an internal 15 V clamp to protect the external power switch. 27 OPFC1 PFC Gate Drive 1. The totem-pole output drive for the PWM MOSFET or IGBT. This pin has an internal 15 V clamp to protect the external power switch. 28 VDD 29 FBPFC Voltage Feedback Input for PFC. Inverting input of the PFC error amplifier. This pin is connected to the PFC output through a resistor divider network. 30 VEA Output of PFC Voltage Amplifier. The error amplifier output for the PFC voltage feedback loop. A compensation network is connected between this pin and ground. 31 SS Soft-Start. Connect a capacitor to this pin to set the soft-start time. Pull this pin to ground to disable the gate drive outputs OPFC1, OPFC2, and OPFC3. 32 IAC Input AC Current. During normal operation, this input provides a current reference for the multiplier. The recommended maximum current on IAC, IAC, is 100 A. FAN9673 -- Three-Channel Interleaved CCM PFC Controller Pin Definitions (Continued) External Bias Supply for the IC. The typical turn-on and turn-off threshold voltages are 12.8 V and 10.8 V, respectively. (c) 2013 Fairchild Semiconductor Corporation FAN9673 * Rev. 1.4 www.fairchildsemi.com 5 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VDD VOPFC VL Parameter Min. DC Supply Voltage V VDD+0.3 V V Voltage on IAC, BIBO, LPK, RLPK, FBPFC, VEA, CS1+, CS2+, CS3+, CS1-, CS2-, CS3-, CM1, CM2, CM3, ILIMIT, ILIMIT2, RI, PVO, GC, LS, VIR Pins -0.3 7.0 V 0 8 V IIAC Input AC Current IPFC-OPFC Peak PFC OPFC Current, Source or Sink TJ 30 -0.3 Voltage on IEA1, IEA2, IEA3, SS Pins R j-a Unit Voltage on OPFC1, OPFC2, OPFC3 Pins VIEA PD Max. Power Dissipation, TA < 50C Thermal Resistance (Junction-to-Air) 1 mA 0.5 A 1640 mW 77 C/W Operating Junction Temperature -40 150 C TSTG Storage Temperature Range -55 150 C TL Lead temperature (Soldering) 260 C ESD Electrostatic Discharge Capability Human Body Model, ANSI/ESDA/JEDEC JS-001-2012 4 Charged Device Model, JESD22-C101 2 kV FAN9673 -- Three-Channel Interleaved CCM PFC Controller Absolute Maximum Ratings Recommended Operating Conditions The recommended operating conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to absolute maximum ratings. Symbol VDD-OP LMISMATCH Parameter Min. Operating Voltage Typ. Max. 15 Boost Inductor Mismatch -5 Unit V +5 % Notes: 1. All voltage values, except differential voltage, are given with respect to GND pin. 2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. (c) 2013 Fairchild Semiconductor Corporation FAN9673 * Rev. 1.4 www.fairchildsemi.com 6 Unless otherwise noted, VDD = 15 V and TJ = -40~105C. Symbol Parameter Condition Min. Typ. Max. Unit VDD Section IDD ST Startup Current VDD = VTH-ON - 0.1 V IDD-OP Operating Current VDD = 14 V; Output Not Switching, RRI = 25 k VTH-ON Turn-On Threshold Voltage VDD Rising VTH UVLO Hysteresis OPFC1~3 Disabled, IEA1~3 and SS Pull LOW VDD OVP Threshold VDD-OVP VDD OVP Hysteresis Oscillator VRI 80 A 6 7 mA 12.8 2 VDD-OVP tD-OVP 4 30 23 24 V 3 V 25 V 80 s 1 VDD OVP Debounce Time V (3) Voltage on RI RRI = 25 k 1.15 1.20 1.25 V fOSC1 PFC Frequency of RRI is 25 k RRI = 25 k 30 32 34 kHz fOSC2 PFC Frequency of RRI is 62 k RRI = 12.5 k 58 62 66 kHz fDV Voltage Stability 13 V VDD 22 V 2 % fDT Temperature Stability 2 % VIEA-SAW32 VIEA-SAW of PFC Frequency 32 kHz RRI = 25 k 5 VIEA-SAW64 VIEA-SAW of PFC Frequency 64 kHz RRI = 12.5 k DPFC-MAX Maximum Duty Cycle VIEA > 7 V DPFC-MIN Minimum Duty Cycle VIEA < 1 V fRANGE1 (3,6) Frequency Range 1 94 5.15 V 97 % 18 (3,6) fRANGE2 Frequency Range 2 tDEAD-MIN Minimum Dead Time RRI = 10.7 k VVIR-H Setting Level for High Voltage Input Range RVIR = 500 k (VVIR = 5 V) VVIR-L Setting Level for Low Voltage Input Range or Full Voltage Input Range VVIR = 0 V V 55 0 % 40 kHz 75 kHz 600 FAN9673 -- Three-Channel Interleaved CCM PFC Controller Electrical Characteristics ns VIR IVIR Source Current of VIR Pin 3.5 7 V 10 1.5 V 13 A PFC Soft-Start ISS Constant Current Output for SoftStart VSS Maximum Voltage on SS ISS- Discharge Discharge Current of SS Pin System Brown-in 22 6.8 A V Brownout, SAG, CM1>4 V, RRI Open / Short, OTP 60 A When VVEA-OFF < 0.3 V, VOPFC1~3 Turns Off & VIEA1~3 Pulls LOW 0.3 V Low-Power Detect Comparator VVEA-OFF VEA Voltage Off Continued on the following page... (c) 2013 Fairchild Semiconductor Corporation FAN9673 * Rev. 1.4 www.fairchildsemi.com 7 Unless otherwise noted, VDD = 15 V and TJ = -40~105C. Symbol Parameter Condition Min. Typ. Max. Unit PVO = GND, TJ = 25C 2.45 2.50 42 65 dB 100 mho Voltage Error Amplifier VREF AV GmV Reference Voltage (3) Open-Loop Gain Transconductance VNONINV - VINV = 0.5 V, TJ = 25C IFBPFC-L Maximum Source Current VFBPFC = 2 V, VVEA = 3 V IFBPFC-H Maximum Sink Current VFBPFC = 3 V, VVEA = 3 V IBS Input Bias Current Range 40 2.55 A 50 -50 -1 V -40 A 1 A IFBPFC-FL Pull HIGH Current for FBPFC FBPFC Floating VVEA-H Output High Voltage on VVEA VFBPFC = 2 V VVEA-L Output Low Voltage on VVEA VFBPFC = 3 V 0 IVEA-DIS Discharge Current Brownout, RRI Open /Short, OTP, SAG 10 A Transconductance VNONINV = VINV, VIEA = 4 V, VILIMIT >0.6V, TJ = 25C 88 mho VOFFSET Input Offset Voltage VVEA = 0.45 V, RIAC=12 M, VIAC = 311 V, VFBPFC = 2 V, VVIR = 5 V, TJ = 25C 0 mV VIEA-H Output High Voltage 7.0 V VIEA-L Output Low Voltage 5.7 500 nA 6.0 V 0.15 V Current Error Amplifier 1~3 Gmi 6.8 0 IL Source Current VNONINV - VINV, = +0.6 V, VIEA = 1 V, VILIMIT >0.6 V IH Sink Current VNONINV - VINV, = -0.6 V, VIEA = 6.5 V, VILIMIT >0.6 V AI Open-Loop Gain IIEA-LOW (3) 35 IEA Pin Pull LOW Capability Protection VIEA >= 5 V 500 1.00 V A 50 -50 40 0.4 FAN9673 -- Three-Channel Interleaved CCM PFC Controller Electrical Characteristics -35 50 A dB A Brown In /Out VBIBO-FL Low Threshold of BO at Full Range AC Input VVIR < 1.5 V, RIAC = 6 M VBIBO-F Hysteresis VBIBO > VBIBO-FL+VBIBO-F, System Brown-in, Start SS VBIBO-HL Low Threshold of BO at High Voltage Single Range AC Input VVIR > 3.5 V, RIAC = 12 M VBIBO-H Hysteresis VBIBO > VBIBO-HH +VBIBO-H, System Brown-in, Start SS tUVP 1.05 1.10 850 1.00 Under-Voltage Protection Delay 1.05 V mV 1.10 V 700 mV 450 ms TriFault DetectTM VPFC-UVP PFC Feedback Under-Voltage Protection 0.4 0.5 0.6 V VPFC-OVP Over-Voltage Protection 2.70 2.75 2.80 V PFC OVP Hysteresis 200 250 300 mV VPFC-OVP (3) tFBPFC-OPEN FBPFC Open Delay tFBPFC-UVP VFBPFC = VPFC-UVP to FBPFC Open, 470 pF from FBPFC to GND Under-Voltage Protection Debounce Time 2 ms 50 s Continued on the following page... (c) 2013 Fairchild Semiconductor Corporation FAN9673 * Rev. 1.4 www.fairchildsemi.com 8 Unless otherwise noted, VDD = 15 V and TJ = -40~105C. Symbol Parameter Condition Min. Typ. Max. Unit PFC ILIMIT2 (CS1 /CS2 /CS3) VILIMIT2-CS1 Peak Current Limit Voltage CS1> VILIMIT2, OPFC1 Disables Cycle by Cycle Limit, VIEA1~3 Pull LOW, RILIMIT2 = 30 k, RRI = 25 k 1.48 V VILIMIT2-CS2 Peak Current Limit Voltage CS2 > VILIMIT2, OPFC2 Disables Cycle by Cycle Limit, VIEA1~3 Pull LOW, RILIMIT2 = 30 k, RRI = 25 k 1.48 V VILIMIT2-CS3 Peak Current Limit Voltage CS3 > VILIMIT2, OPFC3 Disables Cycle by Cycle Limit, VIEA1~3 Pull LOW, RILIMIT2 = 30 k, RRI = 25 k 1.48 V IILIMIT2 Output Current for Peak Current Limit Setting RRI = 25 k, VRI /RRI, TJ = 25C 49.5 A tPFC-Bnk1 Leading-Edge Blanking Time of ILIMIT of Channel 1 VDD = 15 V, OPFC Drops to 9 V 250 ns tPFC-Bnk2 Leading-Edge Blanking Time of ILIMIT of Channel 2 VDD = 15 V, OPFC Drops to 9 V 250 ns tPFC-Bnk3 Leading-Edge Blanking Time of ILIMIT of Channel 3 VDD = 15 V, OPFC Drops to 9 V 250 ns tPD1 Propagation Delay to Output of Channel 1 200 400 ns tPD2 Propagation Delay to Output of Channel 2 200 400 ns tPD3 Propagation Delay to Output of Channel 3 200 400 ns 4.0 4.2 V 0.8 V VLIMIT-OPEN LIMIT Open Voltage OPFC1~3 Disabled and IEA1~3 Pull LOW 3.8 FAN9673 -- Three-Channel Interleaved CCM PFC Controller Electrical Characteristics ILIMIT (Command Limit) VILIMIT-R Input Range 0.2 VILIMIT Over-Power Limit Voltage RILIMIT = 42 K, RRI = 25 k, VILIMIT = RILIMIT * IILIMIT/4 IILIMIT Source Current of ILIMIT Pin RRI = 25 k, VRI /RRI 0.504 V 49 A 0.85 V 33 ms SAG Protection Section VSAG SAG Voltage of BIBO 1.VBIBO < VSAG & VRDY HIGH 33 ms, or 2.VBIBO < VSAG & VRDY Low, Brownout, tSAG-DT SAG Debounce Time VBIBO < VSAG & VRDY HIGH Gain Compensation Section IGC-L1 Mirror Current of IAC at Full Range VVIR = 0 V, VIAC = 127.28 V, AC Input RIAC = 6 M, 20.71 A IGC-L2 Mirror Current of IAC at Full Range VVIR = 0 V, VIAC = 311.13 V, AC Input RIAC = 6 M, 51.86 A IGC-HV Mirror Current of IAC at High Voltage Single AC Input 51.86 A 100 nA IGC-OPEN Pull HIGH Current for GC Open VGC-OPEN GC Open Voltage VVIR = 5 V, VIAC = 311.13 V, RIAC = 12 M. VGC > VGC-OPEN VIEA, OPFC1, 2, 3 Blanking 2.85 3.00 3.15 V Continued on the following page... (c) 2013 Fairchild Semiconductor Corporation FAN9673 * Rev. 1.4 www.fairchildsemi.com 9 Unless otherwise noted, VDD = 15 V and TJ = -40~105C. Symbol Parameter Condition Min. Typ. Max. Unit VLPK-H1 VLPK on High Voltage Input Range VIAC = 311 V, RIAC = 1 2M, VVIR > 3.5 V, RLPK = 12.4 k, TJ = 25C 3.168 V VLPK-H2 VLPK on High Voltage Input Range VIAC = 373 V, RIAC = 12 M, VVIR > 3.5 V, RLPK = 12.4 k, TJ = 25C 3.80 V VLPK-L1 VLPK on Full Range AC Input VIAC = 127 V, RIAC = 6 M, VVIR < 1.5 V, RLPK = 12.4 k, TJ = 25C 1.29 V VLPK-L2 VLPK on Full Range AC Input VIAC = 373 V, RIAC = 6 M, VVIR < 1.5 V, RLPK = 12.4 k, TJ = 25C 3.80 V VAC-OFF AC OFF Threshold Voltage RIAC = 12 M, VVIR > 3.5V, After tAC-OFF VIEA Pull LOW 32 V VAC-ON AC ON Threshold Voltage RIAC = 12 M, VVIR > 3.5 V VAC-OFF +26 V 100 nA (7) LPK RLPK IRLPK-OPEN Pull HIGH Current for RLPK Open VRLPK-OPEN RLPK Open Voltage RLPK Open 2.28 2.40 2.52 V 3.5 V PVO VPVO VPVO_DIS Input Range 0.3 PVO Disable Voltage VPVO-CLAMPH PVO Limit Voltage PVO< VPVO_DIS Disable 0.2 V FBPFC Connected to VEA, VPVO = 4 V 1.6 V VFBPFC1 FBPFC Voltage 1 FBPFC Connected to VEA, VPVO = 0.3 V 2.425 V VFBPFC2 FBPFC Voltage 2 FBPFC Connected to VEA, VPVO = 3.5 V 1.625 V 1 A 140 C 30 C 55 A IPVO-Discharge PVO Discharge Current PVO Open FAN9673 -- Three-Channel Interleaved CCM PFC Controller Electrical Characteristics OTP TOTP-ON TOTP Over-Temperature Protection Hysteresis (3) (3) CM1 Section ICM1 CM1 Output Current VCM1-disable PFC Disable Voltage OPFC1~3 Disabled and IEA1~3 Pull LOW and SS Pull LOW; ICM1 * RCM1 > 4 V 4 V 1 Phase of OPFC1 When ICM1 * RCM1 < 4 V or Short 0 2 Phase of OPFC2 When ICM1 * RCM1 < 4 V or Short 110 120 130 3 Phase of OPFC3 When ICM1 * RCM1 < 4 V or Short 230 240 250 CM2 Section ICM2 CM2 Output Current VCM2-disable Channel2 Disable Voltage VCM2-range OPFC2 Disables and IEA2 PulIs LOW; ICM2 * RCM2 > 4 V or CM2 Floating Set VEA Unload Voltage 55 A 4 V 0 1 Phase of OPFC1 ICM2 * RCM2 > 4 V or CM2 Floating 3 Phase of OPFC3 ICM2 * RCM2 > 4 V or CM2 Floating 3.8 0 170 180 V 190 Continued on the following page... (c) 2013 Fairchild Semiconductor Corporation FAN9673 * Rev. 1.4 www.fairchildsemi.com 10 Unless otherwise noted, VDD = 15 V and TJ = -40~105C. Symbol Parameter Condition Min. Typ. Max. Unit CM3 Section ICM3 CM3 Output Current VCM3-disable Channel3 Disable Voltage VCM3-range Set VEA Unload Voltage OPFC3 Disables and IEA3 PulIs LOW when ICM3 * RCM3 > 4 V or CM3 Floating 55 A 4 V 0 3.8 V 1 Phase of OPFC1 When ICM3 * RCM3 > 4 V or CM3 Floating 2 Phase of OPFC2 When ICM3 * RCM3 > 4 V or CM3 Floating 170 180 190 Level of VFBPFC to Pull RDY HIGH VPVO = 0 V, Brown-in, VFBPFC > VFB-RD 2.3 2.4 2.5 V VFB-RD-L Hysteresis VPVO = 0 V, VIR < 1.5 V 1.15 V VFB-RD-H Hysteresis VPVO = 0 V, VIR > 3.5 V 0.85 V Pull High Input Impedance TJ = 25C 100 k 5.0 V 0 RDY Section VFB-RD ZRDY VRDY-High HIGH Voltage of RDY V RDY-Low LOW Voltage of RDY 4.8 Pull High Current = 1 mA 0.5 V 17 V 1.5 V PFC Output Driver1~3 VGATE-CLAMP Gate Output Clamping Voltage VDD = 22 V 13 15 VGATE-L Gate Low Voltage VDD = 15 V; IO = 100 mA VGATE-H Gate High Voltage VDD = 13 V; IO = 100 mA tr Gate Rising Time VDD = 15 V; CL=4.7 nF; O/P = 2 V to 9 V 70 ns tf Gate Falling Time VDD = 15 V; CL=4.7 nF; O/P = 9 V to 2 V 60 ns 8 FAN9673 -- Three-Channel Interleaved CCM PFC Controller Electrical Characteristics V LPT Section RLS VLS-MIN Range of Inductance Setting 12 Voltage Difference between VFBPFC VFBPFC - VACD 0 V and VACD on LS Pin 87 50 k mV Gain Modulator IAC BW Input for AC Current Bandwidth (3,6) (3,6) Multiplier Linear Range IAC = 40 A 0 65 2 A kHz Continued on the following page... (c) 2013 Fairchild Semiconductor Corporation FAN9673 * Rev. 1.4 www.fairchildsemi.com 11 Unless otherwise noted, VDD = 15 V and TJ = -40~105C. Symbol VRM RM Parameter Voltage of RM (Output Current of Gain Modulator * RM) Condition Min. Typ. VIAC = 106.07 V, RIAC = 6 M, VFBPFC = 2.25 V, VBIBO = 2 V, VCM2, VCM3 > 4.5 V (VAC = 75 V), TJ = 25C 0.490 VIAC = 120.21 V, RIAC = 6 M, VFBPFC = 2.25 V, VBIBO = 2 V, VCM2, VCM3 > 4.5 V (VAC = 85 V), TJ = 25C 0.430 VIAC = 155.56 V, RIAC = 6 M, VFBPFC = 2.25 V, VBIBO = 2 V, VCM2, VCM3 > 4.5 V (VAC = 110 V), TJ = 25C 0.327 VIAC = 311.13 V, RIAC = 12 M, VFBPFC = 2.25 V, VBIBO = 2 V, VCM2, VCM3 > 4.5 V, VVIR > 3.5 V (VAC = 220 V), TJ = 25C 0.320 VIAC = 373.35 V, RIAC = 12 M, VFBPFC = 2.25 V, VBIBO = 2 V, VCM2, VCM3 > 4.5 V, VVIR > 3.5 V (VAC = 264 V), TJ = 25C 0.260 Resistor of Gain Modulator Output RM = VRM /IMO 7.5 Max. Unit V k Notes: 3. This parameter, although guaranteed by design, is not 100% production tested. 4. The setting range of resistance at the RI pin is between 53.3 k and 10.7 k. 5. The RLS and RGC setting suggestion follows the calculation result from Fairchild documents: AN-4164, AN-4165, FEBFAN9673_B01H1500A, FEBFAN9673_B01H2500A, and design tools. 6. Frequency of AC input should be <75 Hz. 7. LPK specification is guaranteed at state of PFC working. 8. Pull the CM pin low to ground to enable an individual channel for voltage of CM pin less than 0.2 V. (c) 2013 Fairchild Semiconductor Corporation FAN9673 * Rev. 1.4 FAN9673 -- Three-Channel Interleaved CCM PFC Controller Electrical Characteristics www.fairchildsemi.com 12 1. Continuous Conduction Mode (CCM) 2. Gain Modulator (IAC, LPK, VEA) The boost converter, shown in Figure 4, is the most popular topology for power factor correction in AC-DC power supplies. This popularity can be attributed to the continuous input current waveform provided by the boost inductor and the boost converter's input voltage range including 0 V. These fundamental properties make close-to-unity power factor easier to achieve. The FAN9673 employs two control loops for power factor correction: a current control loop and a voltage control loop. The current control loop shapes inductor current, as shown in Figure 6, through a current command, IMO, from the gain modulator. IL L IL Average of IL I MO RM RCS VGS Figure 6. CCM PFC Operation Waveforms The gain modulator is the block that provides the reference to control PFC output power. The current of the gain modulator, Imo, is a function of VVEA, IIAC, and LPK; as shown in the Figure 7. Figure 4. Basic PFC Boost Converter The boost converter can operate in Continuous Conduction Mode (CCM) or in Boundary Conduction Mode (BCM). These two descriptive names refer to the current flowing in the energy storage inductor of the boost power stage. These are the three inputs to the gain modulator: IIAC A current representing the instantaneous input voltage (amplitude and wave shape) to the PFC. The rectified AC input sine wave is converted to a proportional current via a resistor and is fed into the gain modulator on IAC. Sampling current IIAC minimizes ground noise, important in highpower, switching-power conversion environment. The gain modulator responds linearly to this current. VLPK Voltage proportional to the peak voltage of the bridge rectifier when the PFC is working. The signal is the output of peak-detect circuit and its input is from the IAC pin. This factor of the gain modulator is input-voltage feed-forward control. This voltage information is not valid when the PFC is not working. VVEA The output of the voltage error amplifier, VVEA. The gain modulator responds linearly to variations in this voltage. I 0A t Typical Inductor Current Waveform In Continuous Conduction Mode I 0A t FAN9673 -- Three-Channel Interleaved CCM PFC Controller Theory of Operation Typical Inductor Current Waveform In Boundary Conduction Mode Figure 5. CCM vs. BCM Control As the names indicate, the current in Continuous Conduction Mode (CCM) is continuous in the inductor. In Boundary Conduction Mode (BCM), the new switching period is initiated when the inductor current returns to zero. There are many fundamental differences in CCM and BCM operations and the respective designs of the boost converter. The FAN9673 is design for CCM control, as Figure 5 shows, this method reduces inductor current ripple because the start current of each cycle is not 0 A typically. The ripple is controlled by the operation frequency and inductance design. This characteristic can decrease the maximum peak current of the power semiconductor device. (c) 2013 Fairchild Semiconductor Corporation FAN9673 * Rev. 1.4 The output of the gain modulator is a current signal, IMO, calculated by Equation (1): I MO K I IAC VVEA 2 VLPK (1) The current signal, IMO, is in the form of a full-wave rectified sinusoid at twice the line frequency. The gain modulator forms the reference for the current error loop and ultimately controls the instantaneous current drawn from the power line. www.fairchildsemi.com 13 IL RFB1 CO RIAC IIAC VFBPFC RFB2 RCS A (IAC) IAC A Current Command (C. Comd.) C (VLPK) Peak Detector VLPK C IMO VIN B B (VEA) VO Gain Modulator AxB Current Command = K (C. Comd.) C2 VEA Gate2 Gate1 VCS1 2.5V VFBPFC PO VCS2 RCS1 RCS2 Differential Sense Filter Differential Sense Filter VO Close VVEA CS1- CS1+ C. Comd. CS2- CS2+ FAN9673 GND IL Figure 7. Filter Ground IC GND to Power ground Input of Gain Modulation Figure 9. FAN9673 -- Three-Channel Interleaved CCM PFC Controller High-power applications require the system current be large, so the distance of layout trace between the current sense resistors and the controller or power ground (negative of output capacitor) to IC ground is important, as Figure 9 shows. The longer trace and large current make the offset voltage and ground bounce differ significantly for different channels. Decreasing the deviation can balance the different channels. Follow the layout guidance of application notes AN-4164 and AN-4165. VPFC VIN Current Balance Factors 3. Current Balance 4. Interleaving Current matching of different channel is important topic of interleaved control. There have several main point is need to careful at FAN9673 of this topic. The FAN9673 controller is used to control three-channel boost converters connected in parallel. The controller operates in average-current mode and Continuous Conduction Mode (CCM). Each channel affords onethird the power when the system operates close to full load or when channel management is disabled. The current control of each channel is based on sense signal VCS to track the current command of the multiplier, as Figure 8 shows. Parallel power processing increases the number of power components, but the current rating of independent channels is reduced, allowing power semiconductors with lower current ratings to be applied. With interleaved control, the output current ripple is evenly distributed on channels and sequentially rippled on the output capacitor. Output current ripple is average share to difference sequence to output capacitor, which can extend the life of the capacitor. AVG IL, High Inductance/Frequency The switches of the three boost converters can operate at three-channel / 120 out-of-phase or two-channel / 180 out-of-phase (one channel disable at light load). The interleaving controller can reduce the total ripple current of input. The FAN9673 offers two types of channel management method selectable by the user. IL, Low Inductance/Frequency Figure 8. Average Current Mode Control The main factors to system balance are layout and device tolerance. The tolerance of the shunt resistor for the current sense is especially important. If the feedback signal, VCS, has large deviation due to the tolerance of the sense resistor; the current of the channels is unbalanced. A high precision resistor is necessary. (c) 2013 Fairchild Semiconductor Corporation FAN9673 * Rev. 1.4 www.fairchildsemi.com 14 IL1 The CM pin is used for channel management. The relationship of CM and the gain of the slave channel is shown in Figure 10. The level of CM determines the power level (VVEA) for reducing the output power for the slave PFC. The FAN9673 starts to reduce the current command (IMO*RM) for channel 2/3 by Gain2/3 when the VVEA level is lower than its CM level, as Figure 11 and Figure 12 show. The output power of the slave channel is reduced in response to the reduction in current command. Typical Gain2/3 is 1~0. Example: when CM2 is set at 3 V and VVEA is less than the CM2 voltage, the channel management block reduces the command for channel 2 as: Vgmi2 I MO RM Gain2 IL2 PO VVEA VCM Gain2=1 Gain to IL2 Channel Management Area, Gain2 < 1 Figure 12. VVEA and VCM Relationship in Channel Management Operation (2) VIN Table 1 explains the phase and gain change of each channel when the PFC operates at various loads. The loading decreases the gain to the slave until it is disabled. The phase of Channel Management (CM) mode doesn't change when channel 3 is disabled. The behavior is shown in Figure 13. VO Gate2 Gate1 ISENSE2 ISENSE1 Full load, all channel operation IL3 Command Generator Voltage Loop VO VVEA Current Command IL2 Current Loop 1 Gate1 IL1 Gain1 100% CM Block Current Loop 2 Gate2 Mid. load ~ light load, linear decrease gain of channel 2 & 3, final only left Channel 1 at light load Gain2 0~100% VCM Figure 10. Po Channel Management / Gain Slave Channel Relationship FAN9673 -- Three-Channel Interleaved CCM PFC Controller VAC 5. Channel Management 2/3: CM Control IL3 IL2 V (V) 6 IL1 VCM 0 Channel 120 Figure 13. Management 240 Phase and Gain Change of CM Control VVEA 100 Loading (%) 0 VAC IL1 VAC IL2 Gain2 = 0 Figure 11. Table 1. 0< Gain2 <1 Gain2 = 1 VVEA and Gain2 Relationship Phase and Gain Change of CM Control CM (Channel Management) Phase Channel 1 Channel 2 Channel 3 Heavy Load (All Channel 100% Works) 0 (Gain1=1) 120 (Gain2=1) 240 (0<Gain3<1) Mid. Load (Channel3 Disable) 0 (Gain1=1) 120 (0<Gain2<1) Disable (Gain3=0) Light Load (Only Channel1 Left ) 0 (Gain1=1) Disable (Gain2=0) Disable (Gain3=0) (c) 2013 Fairchild Semiconductor Corporation FAN9673 * Rev. 1.4 www.fairchildsemi.com 15 VAC To disable the Channel Management (CM) function and control the channels with an external signal from the MCU, the configuration is shown in Figure 14. If CM > 4 V, the channel is disabled. To enable the channel, make VCM = 0 V, as Figure 15 shows. IL1 IL2 PO VVEA VP2-OFF-H VP2-OFF-L The CM pin of the slave should be connected with a switch S2 to ground. When VVEA < VP2-OFF-L, the slave PFC turns off. If VVEA > VP2-OFF-H, the slave PFC turns on. One pin of MCU must read the VVEA signal to determine when to turn on / off the slave. (VP2-OFF-L and VP2-OFF-H are hysteresis levels required in MCU software.) When S2 turns on, CM disables and the slave works normally, as shown in Figure 16. MCU a S2 MCU Turn-Off Slaver Figure 16. CS+ CSSample & Hold The phase of each channel controlled by external signal control changes when the loading changes, as illustrated in Table 2 and Figure 17. When the MCU disables channel 3 at mid-load, the phase of channel 2 shifts to 180 from 120. The gain of each channel under this control mode must be 100% or 0%. CM mode makes the gain operation between 1~0. gmi CM CM 55uA S2 MCU Channel Management by External Signal from MCU OSC Gain Modulator Full load, all channel operation IL3 Figure 14. Channel Management by MCU IL2 IL1 V (V) 6 VCM-LIMIT (4V) VCM Mid. load, disable channel 3 by external signal FAN9673 -- Three-Channel Interleaved CCM PFC Controller 6. Channel Management 2: External Control IL3 VVEA IL2 120a 180 IL1 0 0 100 Loading (%) 120 240 Figure 17. VAC Phase Change under External Signal Control IL Figure 15. Table 2. Channel Management by MCU Phase Change of External Signal Control External Signal Control Phase (Disable Channel: VCM > 4 V, Enable Channel: VCM = 0 V) Channel 1 Channel 2 Channel 3 Heavy Load (All Channels Enabled) 0 120 240 Mid. Load (Channel3 Disabled) 0 180 Disable (VCM3 > 4 V) Light Load (Channel2/3 Disabled) 0 Disable (VCM2 > 4 V) Disable (VCM3 > 4 V) Disable All System (c) 2013 Fairchild Semiconductor Corporation FAN9673 * Rev. 1.4 VCM1 > 4 V, All Channels Disabled www.fairchildsemi.com 16 Internal Oscillator (RI) TriFault DetectTM Technology The internal oscillator frequency is determined by external resistor, RRI, on the RI pin. The frequency of the oscillator is given by: To improve power supply reliability, reduce system component count, and simplify compliance to UL 1950 safety standards; the FAN9673 includes TriFault DetectTM technology. This feature monitors FBPFC for certain PFC fault conditions. fOSC 8 108 RRI (3) Current-Control Loop of Boost Stage As shown in Figure 18, the two control loops for power factor correction are a current-control loop and a voltage-control loop. Based on the reference signal obtained at the IAC pin, the relationship of current loop is: I L RCS I MO RM GLU I IAC G GLU RM (4) The current sense, IL*RCS, is controlled by the current command from the multiplier; IMO*RM. IMO is the relationship of three input factors: IAC, VEA, and LPK. Gain2 is a gain between 0~1 from the channel management block for the slave channel. Voltage-Control Loop of Boost Stage The voltage-control loop regulates PFC output voltage by using the internal error amplifier, Gmv, such that the voltage on FBPFC is the same as the internal reference voltage of 2.5 V. This stabilizes PFC output voltage and decreases the 120 Hz ripple of PFC output voltage. PFC Over-Voltage Protection (OVP) protects the power circuit from damage from an excessive voltage at a sudden load change. When the voltage on FBPFC exceeds 2.75 V, the PFC output driver shuts down. VIN In the case of a feedback path failure, the output of the PFC can exceed operating limits. Should FBPFC go too low, too high, or open; TriFault Detect senses the error and terminates the PFC output drive. TriFault Detect is an entirely internal circuit. It requires no external components to perform its function. PFC Over-Voltage Protection (OVP) FAN9673 has an auto-restart OVP function. When the feedback level, VFBPFC, of the PFC reaches 2.75 V (reference level is 2.5 V), the PFC gate signal stops until the output voltage decreases and VFBPFC returns to 2.5 V, when the PFC restarts regulation. Linear Predict Function (GC & LC) The linear predict function is used to emulate the behavior of inductor current when the MOSFET is off. The resistors of the GC and LS pins (RGC and RLS) are used to adjust the DC gain and compensation, respectively. The resistors are determined by: RGC VPFC IL LPFC R RFB 2 RFB 3 1.5 10-9 RCS FB1 RFB 3 6 6 10 RFB1 RFB 2 RFB 3 RFB 3 RLS FAN9673 -- Three-Channel Interleaved CCM PFC Controller Functional Description (5) (6) PFC Brown In /Out (BIBO) An internal AC Under-Voltage Protection (UVP) comparator monitors the AC input information from VIN, as Figure 19 shows. The OPFC is disabled when the VBIBO is less than 1.05 V for 410 ms. If VBIBO is larger than 1.9 V / 1.75 V, VBIBO is over 1.9 V / 1.75 V, and the PFC stage is enabled. The VIR pin is used to set the AC input range according to Table 3. RCS CS- CS+ LS gmi LPT IEA GC CM CM RIAC RI1 RM CI2 IAC LPK CI1 IMO Drive Logic Peak Detecter VEA OPFC OSC RI RV1 RFB1+FB2 Table 3. BIBO Setting of Various AC Input Input Range Full-Range 85~ 264 HV-Single gmv CV2 CV1 2.5V RVIR RIAC BIBO Setting Setting Level (V) 10 k 6 M 180~264 470 k 12 M 85 / 75 170 / 160 1.9V/1.7V (PFC brown-in threshold) PVO FBPFC Figure 18. AC (V) RFB3 VIN VBIBO Gain Modulation Block 1.05V (brown-out protection trip point) PFC runs Figure 19. VBIBO According to the PFC Operation (c) 2013 Fairchild Semiconductor Corporation FAN9673 * Rev. 1.4 www.fairchildsemi.com 17 The FAN9673 has three groups of differential currentsensing pins. The CSn+ and CSn- sets of pins are the inputs of the internal differential amplifier. Switching noise problems in interleaved PFC control is more critical than on a single channel, especially for current sensing. The FAN9673 uses a differential amplifier to eliminate switching noise from other channels. This makes the PFC more stable in higher-power applications and eliminates switching noise from other channels. As Figure 20 shows, ground bounce can be decreased by a differential sense function. Differential Current Sense I RI 5 A 1/4 3 C I*RILIMIT 4 VRM B Gain Modulator Figure 22. Figure 20. Current Limit 2 (saturation state): Use 80%~90% of the maximum current of the switch device to serve as the saturation protection. This current protection is a cycle-by-cycle limit. VILIMIT2 = Saturation Protection VILIMIT2 VCS.PK Period Differential Current Sense PFC Gate Driver PFC Command Gmi+ For high-power applications, the switch device of the system requires high driver current. The totem-pole circuit shown in Figure 21 is recommended. VCS VILIMIT/4 Case1: Max. Power (Normal), VVEA-MAX"B"= 6V VDD OPFC Right design at abnormal test, command from Multiplier clamp by ILIMIT Figure 23. RCS Gate Drive Circuit Current-Limit Protection The FAN9673 includes three "cases" of current-limit protection to manage OCP and inductor saturation: VVEA, ILIMT, and ILIMIT2. The current-limit thresholds, VILIMIT1 and VILIMIT2, are controlled by the selection of the resistor for the application. Power (normal state): In the normal case, current / power should be controlled by command VM from the gain modulator. When VVEA rises to 6 V, the output power and current of the system are at peak. The power and current can't increase further. Wrong design at abnormal test, but protect by ILIMIT2 ILIMIT and ILIMIT2 Setting Programmable PFC Output Voltage (PVO) Decreasing the PFC output voltage can improve efficiency of the PFC stage. The PVO pin is used to modulate output voltage, as Figure 24 shows. This function is controlled by an external voltage signal on PVO pin from MCU or other source. VPVO should be over 0.5 V and the relationship for VPVO and VFBPFC is given by: V VFBPFC 2.5V PVO 4 (7) Example: If PVO input is 1 V; RFB1+RFB2 = 3.7 M, RFB3 = 23.7 k, VFBPFB = 2.25 V, and PFC VO = 354 V. VO Current Limit 1 (abnormal state): The current 2 command from the gain modulator is k*IAC*VVEA/VLPK . When in abnormal state (e.g. an AC cycle miss and return in a short period), the VLPK has a delay before returning to the original level. This delay significantly increases the current command. If the command is greater than the limit clamp level, VILIMIT, it works as shown in Figure 22 and Figure 23. The peak current of this state can be used as the maximum current designed for each channel such that inductor current is not saturated. VO IL 393V 354V RCS External Signal (MCU) RFB1 VFBPFC PVO gmv 2.5V RFB2 VFBPFC 2.5V Voltage Protection Figure 24. (c) 2013 Fairchild Semiconductor Corporation FAN9673 * Rev. 1.4 Case3: >Max. Power (Abnormal), AC cycle drop, as left case, but user uses wrong choke can not afford current at Max. command. Case2: >Max. Power (Abnormal), AC cycle drop VVEA = 6V, but"C"abnormal short time, clamp by VILIMIT Right design, max power limited by VVEA SPFC Figure 21. RILIMIT Current Command Limit by ILIMIT Non-Saturation Period ILIMIT FAN9673 -- Three-Channel Interleaved CCM PFC Controller 1.2V Differential Current Sensing (CS+, CS-) FBPFC RFB3 2.25V PVO 1V 0V Programmable PFC Output Voltage www.fairchildsemi.com 18 Soft-Start The ready (RDY) function is used to signal the MCU that the controller is ready and the power stage can start to operate. When the feedback voltage on FBPFC rises to 2.4 V, the VRDY signal pulls HIGH to indicate to the MCU that the next power stage can start, as shown in Figure 25. If the AC line is OFF (or AC signal drops for a long time), the FAN9673 enters brown out and VRDY pulls LOW to indicate to the MCU that the power stage should stop, as shown in Figure 26. When the AC signal drops for only a short time (i.e. 1~1.5 AC cycles) and the IC does not brown out, the FAN9673 recovers the VPFC (same as VFBFFC) when the AC signal is restored to normal, as shown in Figure 27. Soft-start is combined with RDY pin operation, as Figure 26 and Figure 27 show. During startup, the RDY pin remains LOW until the PFC output voltage reaches 96% of its nominal value. When the supply voltage of the downstream converter is controlled by the RDY pin, the PFC stage starts with no load because the downstream converter does not operate until the PFC output voltage reaches the required level for the design. AC "sag" means the AC drops to a low level, such as 110 V / 220 V a 40 V. AC "missing" means the AC drops to 0 V. If AC drops, the PFC attempts to transfer energy to VO before VO drops to the 50% level. If AC is 0 V, the PFC can't transfer energy. If the level reaches 50%; the PFC stops, resets, and waits for AC to return. VPFC IL Usually, the error amplifier output, VEA, is saturated to HIGH during startup because the actual output voltage is less than the target value. VEA remains saturated to HIGH until the PFC output voltage reaches its target value. Once the PFC output reaches its target value, the error amplifier comes out of saturation. However, it takes several line cycles for VEA to drop to its proper value for output regulation, which delivers more power to the load than required, causing output voltage overshoot. To prevent output voltage overshoot during startup caused by the saturation of error amplifier, the FAN9673 clamps the error amplifier output voltage (VEA) by the VSS value until PFC output reaches 96% of its nominal value. Input Voltage Peak Detection RFB1 + FB2 VREF RDY FBPFC MCU RFB3 FR: 2.4V/1.15V HV: 2.4V/1.55V Figure 25. RDY Function to MCU VAC IL AC OFF (AC Long Time Drop) VIN-OK = 2.4V VIN-OFF = 1.25V (FR) / 1.55V (HV) VFBPFC Brownout & RDY Pull-Low PFC Soft Start VSS VVEA VRDY a MCU Figure 26. Second Power Stage working AC Drops for Long Time PFC Soft Start The input AC peak voltage is sensed at the IAC pin. The RMS value of input voltage is used for feed-forward control in the gain modulator circuit and output to the LPK pin for MCU use. Since the RMS value of the AC input voltage is directly proportional to its peak, it is sufficient to find the peak instead of the morecomplicated and slower method of integrating the input voltage over a half line cycle. The internal circuit of the IAC pin works with peak detection of the input AC waveform, as shown in Figure 28. FAN9673 -- Three-Channel Interleaved CCM PFC Controller RDYF and AC Line Off / AC "Sag" One of the important benefits of this approach is that the peak indicates the correct RMS value even at no load. At no load, the HF filter capacitor at the input side of the boost converter is not discharged around the zero-crossing of the line waveform. Another notable benefit is that, during line transients when the peak exceeds the previously measured value, the inputvoltage feed-forward circuit can react immediately, without waiting for a valid integral value at the end of the half-line period. Lack of zero-crossing detection can lead to false integrator detection, while peak detection works properly during light-load operation. VAC tBLANK=5ms No update IL tBLANK=5ms No update VUP=+0.2V VIN-OK = 2.4V VLPK VIN-OFF = 1.25V (FR) / 1.55V (HV) AC Short Time Drop VB+/100 VFBPFC PFC Soft Start 95% tSH=3.5ms tSH=2.5ms IEA pull low VSS VVEA VRDY a MCU Figure 27. Figure 28. Second Power Stage working tSH=2.5ms IEA pull low VAC-OFF=30V VAC-ON=60V (RIAC=12M) (RIAC=12M) Waveform of LPK Function AC Drops Briefly (c) 2013 Fairchild Semiconductor Corporation FAN9673 * Rev. 1.4 www.fairchildsemi.com 19 VIN RIAC IAC As in the below design example, assume the maximum VIN.PK at 373 V (264 VAC), the relationship of VIN.PK / VLPK is 100, and VLPK = 3.73 V < 3.8 V. VLPK VIN .PK RRLPK 100 12.4k RLPK (8) VLPK Figure 29. (c) 2013 Fairchild Semiconductor Corporation FAN9673 * Rev. 1.4 Ratio RRLPK LPK Peak Detector Relationship of VIN.PK to VLPK FAN9673 -- Three-Channel Interleaved CCM PFC Controller The relationship of VIN.PK to VLPK is shown in Figure 29. The peak detection circuits recognizes the VIN information from IAC. RLPK sets the ratio of VIN to VLPK via a resistor RRLPK as described in Equation (8). The target value of VLPK is one percent (1%) of VIN_pk. The maximum VLPK cannot exceed 3.8 V when system operation is at maximum AC input. www.fairchildsemi.com 20 Typical characteristics are provided at TA = 25C and VDD = 15 V unless otherwise noted. Figure 30. Figure 32. IDD-OP vs. Temperature Figure 31. fOSC vs. Temperature Figure 33. VDD-OVP vs. Temperature VRI vs. Temperature Figure 34. VBIBO-FL vs. Temperature Figure 35. VBIBO-FH vs. Temperature Figure 36. VBIBO-HL vs. Temperature Figure 37. VBIBO-HH vs. Temperature (c) 2013 Fairchild Semiconductor Corporation FAN9673 * Rev. 1.4 FAN9673 -- Three-Channel Interleaved CCM PFC Controller Typical Performance Characteristics www.fairchildsemi.com 21 Typical characteristics are provided at TA = 25C and VDD = 15 V unless otherwise noted. Figure 38. VFBPFC-RD vs. Temperature Figure 39. GmV-MAX vs. Temperature Figure 40. VOFFSET vs. Temperature Figure 41. GmI vs. Temperature Figure 42. VPFC-OVP vs. Temperature Figure 43. VREF vs. Temperature Figure 44. IILIMIT vs. Temperature (c) 2013 Fairchild Semiconductor Corporation FAN9673 * Rev. 1.4 Figure 45. FAN9673 -- Three-Channel Interleaved CCM PFC Controller Typical Performance Characteristics VILIMIT vs. Temperature www.fairchildsemi.com 22 Typical characteristics are provided at TA = 25C and VDD = 15 V unless otherwise noted. Figure 46. IILIMIT2 vs. Temperature Figure 47. VILIMIT2-CS1 vs. Temperature Figure 48. tPFC-BNK vs. Temperature Figure 49. VRLPK-OPEN vs. Temperature Figure 50. VLPK-H1 vs. Temperature (c) 2013 Fairchild Semiconductor Corporation FAN9673 * Rev. 1.4 Figure 51. FAN9673 -- Three-Channel Interleaved CCM PFC Controller Typical Performance Characteristics VLPK-H2 vs. Temperature www.fairchildsemi.com 23 Application Output Power Input Voltage Output Voltage / Output Current Single-Stage, Three-Channel PFC 5000 W 180~264 VAC 393 V / 12.72 A Features 180 VAC ~264 V, Three-Channel PFC Using FAN9673 Switch-Charge Technique of Gain Modulator for Better PF and Lower THD 40 kHz Low Switching Frequency Operation with IGBT Protections: Over-Voltage Protection (OVP), Under-Voltage Protection (UVP), and Over-Current Protection (ILIMIT), Inductor Saturation Protection (ILIMIT2) * DBP1, 2 1N5406 RB1 CB 1F LPFC1 100H DPFC1 FFH30S60STU LPFC2 100H DPFC2 FFH30S60STU LPFC3 100H DPFC3 FFH30S60STU VPFC RFB1 2.2M SPFC1~3 FGH40N60SMDF RB1 1M RFB2 1.5M RA1 6M VDD RB2 1M COUT 2040F VDD VDD RA2 6M Rsen1 15m CFB 470pF Rsen3 15m Rsen2 15m FAN9673 -- Three-Channel Interleaved CCM PFC Controller Typical Application Circuit RFB3 23.7k RF1~2 470 CF1 2.2nF CF2 2.2nF RB3 200k OPFC1 CS1- CS1+ OPFC2 CS2- CS2+ OPFC3 CS3- CS3+ IAC FBPFC BIBO CB1 47nF CB2 0.47F CVC2 100nF RB4 16.2k VEA SS RVC1 75k CSS 0.47F RLPK IEA1 CRLPK 10nF CVC1 1F CIC12 100pF RIC11 17.4k CIC11 1nF RLPK 12.1k FAN9673 LS CLS 470pF IEA2 CIC122 100pF RIC21 17.4k CIC21 1nF RLS 43k IEA3 GC CGC 470pF CIC32 100pF RIC31 17.4k CIC31 1nF RGC 38.2k VDD ILIMIT2 CVDD 22F CILIMIT2 10nF RILIMIT2 10k LPK MCU CLPK 0.1F RLPK 4.7k Standby Power VIR CVIR 1nF RVIR 470k CM1 CM2 CM3 DC Setting Level PVO GND MCU signal (DC) RDY MCU/ Sec. Stage (PFC Ready) RI ILIMIT RRI CILIMIT RILIMIT 20k 10nF 30k Figure 52. Schematic of Design Example (c) 2013 Fairchild Semiconductor Corporation FAN9673 * Rev. 1.4 www.fairchildsemi.com 24 FAN9673 -- Three-Channel Interleaved CCM PFC Controller Specification VDD Maximum Rating: 20 V VDD OVP: 24 V VCC UVLO: 10.3 V / 12.8 V PVO: 0 V~1 V PFC Soft-Start: CSS = 0.47 F Brown-In/Out: 175 V / 165 V Switching Frequency: 40 kHz Gate Clamp: 2.4 V / 1.55 V (96% / 62%) RIAC: 12 M Inductor Schematic Diagram Core: QP2925H (3C94) Bobbin: 4 Pins Figure 53. Table 4. Inductor Schematic Diagram Winding Specification No. Winding Pin (S F) Wire Turns Winding Method 1 N1 14 0.1x40 *2 46 Solenoid Winding 2 Insulation: Polyester Tape t = 0.025 mm, 2-Layer 3 Copper-Foil 1.2T to PIN3 Table 5. MOSFET and Diode Reference Specification IGBTs Voltage Rating 600 V (IGBT) FGH40N60SMDF Boost Diodes 600 V (c) 2013 Fairchild Semiconductor Corporation FAN9673 * Rev. 1.4 FFH30S60STU www.fairchildsemi.com 25 Table 6. Efficiency 25% Load 50% Load 75% Load 100% Load 180 V / 50 Hz 96.5% 96.5% 96.5% 96.2% 220 V / 50 Hz 97.0% 97.1% 97.2% 97.1% 264 V / 50 Hz 97.6% 97.9% 97.7% 97.6% 25% Load 50% Load 75% Load 100% Load 180 V / 50 Hz 0.9912 0.9947 0.9971 0.9974 220 V / 50 Hz 0.9800 0.9868 0.9905 0.9924 264 V / 50 Hz 0.9365 0.9369 0.9526 0.9600 25% Load 50% Load 75% Load 100% Load 180 V / 50 Hz 10.55% 9.17% 6.62% 6.40% 220 V / 50 Hz 14.32% 14.36% 12.55% 11.26% 264 V / 50 Hz 25.85% 33.22% 29.59% 27.29% Table 7. Table 8. Power Factor Total Harmonic Distortion FAN9673 -- Three-Channel Interleaved CCM PFC Controller Typical Performance System Design Precautions Pay attention to the inrush current when AC input is first connected to the boost PFC convertor. It is recommended to use NTC and a parallel connected relay circuit to reduce inrush current. Add bypass diode to provide a path for inrush current when PFC start up. The PFC stage is normally used to provide power to a downstream DC-DC or inverter. It's recommend that downstream power stage is enabled to operate at full load once the PFC output voltage has reaches a level close to the specified steady-state value. The PVO function is used to change the output voltage of PFC, V PFC. The VPFC should be kept at least 25 V higher than VIN. (c) 2013 Fairchild Semiconductor Corporation FAN9673 * Rev. 1.4 www.fairchildsemi.com 26 9.0 7.0 24 D 17 1.80 25 16 A B 0.8 7.0 32 0.45 1 8 TOP VIEW A 9.0 9 PIN #1 IDENT 8.70 0.8 32X 1.45 1.35 0.20 C A-B D ALL LEAD TIPS 0.20 M C A-B D 0.45 0.30 32X SEATING PLANE 7.1 6.9 SIDE VIEW C 12 MAX TOP & BOTTOM R0.08 MIN 0.25 GAGE PLANE LAND PATTERN RECOMMENDATION NOTES: A. CONFORMS TO JEDEC MS-026 VARIATION BBA B. ALL DIMENSIONS ARE IN MILLIMETERS C. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-2009 D. DIMENSIONS EXCLUSIVE OF BURRS, MOLD FLASH, AND TIRE BAR PROTRUSIONS. E. LAND PATTERN STANDARD: QFP80P900X900X160-32BM F. DRAWING FILENAME: MKT-VBE32Arev3 1.60 MAX 0.20 0.09 0.10 C 0.75 0.45 R0.08-0.20 0.20 MIN 1.0 DETAIL A SCALE 3:1 0.15 0.05 8.70 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor's product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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