PE
ASIC / FPGA
CML
LVDS
LVPECL
ASIC / FPGA
LVDS
2
BR120
DS25BR120
www.ti.com
SNLS256E –MARCH 2007–REVISED APRIL 2013
DS25BR120 3.125 Gbps LVDS Buffer with Transmit Pre-Emphasis
Check for Samples: DS25BR120
1FEATURES DESCRIPTION
The DS25BR120 is a single channel 3.125 Gbps
2• DC - 3.125 Gbps Low Jitter, High Noise LVDS buffer optimized for high-speed signal
Immunity, Low Power Operation transmission over lossy FR-4 printed circuit board
• Four Levels of Transmit Pre-Emphasis Drive backplanes and balanced metallic cables. Fully
Lossy Backplanes and Cables differential signal paths ensure exceptional signal
integrity and noise immunity.
• On-Chip 100ΩInput and Output Termination
Minimizes Insertion and Return Losses, The DS25BR120 features four levels of pre-emphasis
Reduces Component Count, and Minimizes (PE) for use as an optimized driver device. Other
Board Space LVDS devices with similar IO characteristics include
the following products. The DS25BR110 features four
• 7 kV ESD on LVDS I/O pins Protects Adjoining levels of equalization for use as an optimized receiver
Components device, while the DS25BR100 features both pre-
• Small 3 mm x 3 mm 8-WSON Space Saving emphasis and equalization for use as an optimized
Package repeater device. The DS25BR150 is a buffer/repeater
with the lowest power consumption and does not
APPLICATIONS feature transmit pre-emphasis nor receive
equalization.
• Clock and Data Buffering
• Metallic Cable Driving Wide input common mode range allows the receiver
to accept signals with LVDS, CML and LVPECL
• FR-4 Driving levels; the output levels are LVDS. A very small
package footprint requires minimal space on the
board while the flow-through pinout allows easy board
layout. The differential inputs and outputs are
internally terminated with a 100Ωresistor to lower
device input and output return losses, reduce
component count and further minimize board space.
Typical Application
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2007–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
PE1
IN+
IN-
PE0
VCC
OUT+
OUT-
NC
1
2
3
4
8
6
5
7
GND
DAP
PE1
OUT+
OUT-
PE0
IN+
IN-
DS25BR120
SNLS256E –MARCH 2007–REVISED APRIL 2013
www.ti.com
Block Diagram
Pin Diagram
WSON Package
PIN DESCRIPTIONS
Pin Name Pin Name Pin Type Pin Description
PE1 1 Input Pre-emphasis select pin.
IN+ 2 Input Non-inverting LVDS input pin.
IN- 3 Input Inverting LVDS input pin.
PE0 4 Input Pre-emphasis select pin.
NC 5 NA "NO CONNECT" pin.
OUT- 6 Output Inverting LVDS output pin.
OUT+ 7 Output Non-inverting LVDS Output pin.
VCC 8 Power Power supply pin.
GND DAP Power Ground pad (DAP - die attach pad)
Pre-Emphasis Truth Table
PE1 PE0 Pre-emphasis Level
0 0 Off
0 1 Low (Approx. 3 dB at 1.56 GHz)
1 0 Medium (Approx. 6 dB at 1.56 GHz)
1 1 High (Approx. 9 dB at 1.56 GHz)
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
2Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: DS25BR120
DS25BR120
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SNLS256E –MARCH 2007–REVISED APRIL 2013
Absolute Maximum Ratings(1)(2)
Supply Voltage (VCC)−0.3V to +4V
LVCMOS Input Voltage (PE0, PE1) −0.3V to (VCC + 0.3V)
LVDS Input Voltage (IN+, IN−)−0.3V to +4V
Differential Input Voltage |VID| 1.0V
LVDS Output Voltage (OUT+, OUT−)−0.3V to (VCC + 0.3V)
LVDS Differential Output Voltage ((OUT+) - (OUT−)) 0V to 1.0V
LVDS Output Short Circuit Current Duration 5 ms
Junction Temperature +150°C
Storage Temperature Range −65°C to +150°C
Lead Temperature Range
Soldering (4 sec.) +260°C
Maximum Package Power Dissipation at 25°C
NGQ Package 2.08W
Derate NGQ Package 16.7 mW/°C above +25°C
Package Thermal Resistance
θJA +60.0°C/W
θJC +12.3°C/W
ESD Susceptibility
HBM(3) ≥7 kV
MM(4) ≥250V
CDM(5) ≥1250V
(1) “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of
device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or
other conditions beyond those indicated in the Recommended Operating Conditions is not implied. The Recommended Operating
Conditions indicate conditions at which the device is functional and the device should not be operated beyond such conditions.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
(3) Human Body Model, applicable std. JESD22-A114C
(4) Machine Model, applicable std. JESD22-A115-A
(5) Field Induced Charge Device Model, applicable std. JESD22-C101-C
Recommended Operating Conditions Min Typ Max Units
Supply Voltage (VCC) 3.0 3.3 3.6 V
Receiver Differential Input Voltage (VID) 0 1.0 V
Operating Free Air Temperature (TA)−40 +25 +85 °C
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.(1)(2)(3)
Symbol Parameter Conditions Min Typ Max Units
LVCMOS INPUT DC SPECIFICATIONS (PE0, PE1)
VIH High Level Input Voltage 2.0 VCC V
VIL Low Level Input Voltage GND 0.8 V
IIH High Level Input Current VIN = 3.6V 0 ±10 μA
VCC = 3.6V
IIL Low Level Input Current VIN = GND 0 ±10 μA
VCC = 3.6V
(1) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
(2) Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground
except VOD and ΔVOD.
(3) Typical values represent most likely parametric norms for VCC = +3.3V and TA= +25°C, and at the Recommended Operation Conditions
at the time of product characterization and are not ensured.
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SNLS256E –MARCH 2007–REVISED APRIL 2013
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Electrical Characteristics (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.(1)(2)(3)
Symbol Parameter Conditions Min Typ Max Units
VCL Input Clamp Voltage ICL =−18 mA, VCC = 0V -0.9 −1.5 V
LVDS OUTPUT DC SPECIFICATIONS (OUT+, OUT-)
VOD Differential Output Voltage 250 350 450 mV
RL= 100Ω
ΔVOD Change in Magnitude of VOD for Complimentary -35 35 mV
Output States
VOS Offset Voltage 1.05 1.2 1.375 V
RL= 100Ω
ΔVOS Change in Magnitude of VOS for Complimentary -35 35 mV
Output States
IOS Output Short Circuit Current(4) OUT to GND -35 -55 mA
PE0 = PE1 = 0
OUT to VCC 7 55 mA
PE0 = PE1 = 0
COUT Output Capacitance Any LVDS Output Pin to GND 1.2 pF
ROUT Output Termination Resistor Between OUT+ and OUT- 100 Ω
LVDS INPUT DC SPECIFICATIONS (IN+, IN-)
VID Input Differential Voltage 0 1 V
VTH Differential Input High Threshold VCM = +0.05V or VCC-0.05V 0 +100 mV
VTL Differential Input Low Threshold −100 0 mV
VCMR Common Mode Voltage Range VID = 100 mV 0.05 VCC - V
0.05
VIN = 3.6V or 0V ±1 ±10 μA
IIN Input Current VCC = 3.6V or 0V
CIN Input Capacitance Any LVDS Input Pin to GND 1.7 pF
RIN Input Termination Resistor Between IN+ and IN- 100 Ω
SUPPLY CURRENT
ICC Supply Current PE0 = 0, PE1 = 0 35 43 mA
(4) Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only.
AC Electrical Characteristics(1)
Over recommended operating supply and temperature ranges unless otherwise specified.(2)(3)
Symbol Parameter Conditions Min Typ Max Units
LVDS OUTPUT AC SPECIFICATIONS (OUT+, OUT-)
tPHLD Differential Propagation Delay High to Low 350 465 ps
RL= 100Ω
tPLHD Differential Propagation Delay Low to High 350 465 ps
tSKD1 Pulse Skew |tPLHD −tPHLD|(4) 45 100 ps
tSKD2 Part to Part Skew(5) 45 150 ps
tLHT Rise Time 80 150 ps
RL= 100Ω
tHLT Fall Time 80 150 ps
(1) Specification is ensured by characterization and is not tested in production.
(2) The Electrical Characteristics tables list ensured specifications under the listed Recommended Operating Conditions except as
otherwise modified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and
are not ensured.
(3) Typical values represent most likely parametric norms for VCC = +3.3V and TA= +25°C, and at the Recommended Operation Conditions
at the time of product characterization and are not ensured.
(4) tSKD1, |tPLHD −tPHLD|, is the magnitude difference in differential propagation delay time between the positive going edge and the negative
going edge of the same channel.
(5) tSKD2, Part to Part Skew, is defined as the difference between the minimum and maximum specified differential propagation delays. This
specification applies to devices at the same VCC and within 5°C of each other within the operating temperature range.
4Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: DS25BR120
DS25BR120
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SNLS256E –MARCH 2007–REVISED APRIL 2013
AC Electrical Characteristics(1) (continued)
Over recommended operating supply and temperature ranges unless otherwise specified.(2)(3)
Symbol Parameter Conditions Min Typ Max Units
JITTER PERFORMANCE WITH PE = OFF
tRJ1A VID = 350 mV 2.5 Gbps 0.5 1 ps
Random Jitter (RMS Value) VCM = 1.2V
tRJ2A No Test Channels Clock (RZ) 3.125 Gbps 0.5 1 ps
(6) PE0 = 0, PE1 = 0
tDJ1A VID = 350 mV 2.5 Gbps 9 31 ps
Deterministic Jitter (Peak to Peak) VCM = 1.2V
tDJ2A No Test Channels(7) K28.5 (NRZ) 3.125 Gbps 16 40 ps
PE0 = 0, PE1 = 0
tTJ1A VID = 350 mV 2.5 Gbps 0.05 0.13 UIP-P
Total Jitter (Peak to Peak) VCM = 1.2V
tTJ2A No Test Channels(8) PRBS-23 (NRZ) 3.125 Gbps 0.09 0.16 UIP-P
PE0 = 0, PE1 = 0
JITTER PERFORMANCE WITH PE = LOW (Figure 5 and Figure 6)
tRJ1B VID = 350 mV 2.5 Gbps 0.5 1.3 ps
Random Jitter (RMS Value) VCM = 1.2V
tRJ2B Test Channel A(6) Clock (RZ) 3.125 Gbps 0.5 1.3 ps
PE0 = 1, PE1 = 0
tDJ1B VID = 350 mV 2.5 Gbps 17 31 ps
Deterministic Jitter (Peak to Peak) VCM = 1.2V
tDJ2B Test Channel A(7) K28.5 (NRZ) 3.125 Gbps 18 40 ps
PE0 = 1, PE1 = 0
tTJ1B VID = 350 mV 2.5 Gbps 0.09 0.14 UIP-P
Total Jitter (Peak to Peak) VCM = 1.2V
tTJ2B Test Channel A(8) PRBS-23 (NRZ) 3.125 Gbps 0.12 0.19 UIP-P
PE0 = 1, PE1 = 0
JITTER PERFORMANCE WITH PE = MEDIUM (Figure 5 and Figure 6)
tRJ1C VID = 350 mV 2.5 Gbps 0.5 1.2 ps
Random Jitter (RMS Value) VCM = 1.2V
tRJ2C Test Channel B(6) Clock (RZ) 3.125 Gbps 0.5 1.2 ps
PE0 = 0, PE1 = 1
tDJ1C VID = 350 mV 2.5 Gbps 21 44 ps
Deterministic Jitter (Peak to Peak) VCM = 1.2V
tDJ2C Test Channel B(7) K28.5 (NRZ) 3.125 Gbps 27 48 ps
PE0 = 0, PE1 = 1
tTJ1C VID = 350 mV 2.5 Gbps 0.09 0.16 UIP-P
Total Jitter (Peak to Peak) VCM = 1.2V
tTJ2C Test Channel B(8) PRBS-23 (NRZ) 3.125 Gbps 0.13 0.23 UIP-P
PE0 = 0, PE1 = 1
JITTER PERFORMANCE WITH PE = HIGH (Figure 5 and Figure 6)
tRJ1D VID = 350 mV 2.5 Gbps 0.5 1.2 ps
Random Jitter (RMS Value) VCM = 1.2V
tRJ2D Test Channel C(6) Clock (RZ) 3.125 Gbps 0.5 1.2 ps
PE0 = 1, PE1 = 1
tDJ1D VID = 350 mV 2.5 Gbps 30 65 ps
Deterministic Jitter (Peak to Peak) VCM = 1.2V
tDJ2D Test Channel C(7) K28.5 (NRZ) 3.125 Gbps 30 58 ps
PE0 = 1, PE1 = 1
tTJ1D VID = 350 mV 2.5 Gbps 0.09 0.20 UIP-P
Total Jitter (Peak to Peak) VCM = 1.2V
tTJ2D Test Channel C(8) PRBS-23 (NRZ) 3.125 Gbps 0.13 0.22 UIP-P
PE0 = 1, PE1 = 1
(6) Measured on a clock edge with a histogram and an accumulation of 1500 histogram hits. Input stimulus jitter is subtracted geometrically.
(7) Tested with a combination of the 1100000101 (K28.5+ character) and 0011111010 (K28.5- character) patterns. Input stimulus jitter is
subtracted algebraically.
(8) Measured on an eye diagram with a histogram and an accumulation of 3500 histogram hits. Input stimulus jitter is subtracted.
Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback 5
Product Folder Links: DS25BR120
50: MS
50: MS
50: MS
50: MS
L=4"
L=4"
L=4"
L=4"
TEST
CHANNEL
CHARACTERIZATION
BOARD
DS25BR120
PATTERN
GENERATOR OSCILLOSCOPE
RL
OUT+
OUT-
IN+
IN-
Signal Generator R D
R D RL
VOL
OUT+
OUT-
IN+
IN-
Power Supply
Power Supply
VOH
DS25BR120
SNLS256E –MARCH 2007–REVISED APRIL 2013
www.ti.com
APPLICATION INFORMATION
DC TEST CIRCUITS
Figure 1. Differential Driver DC Test Circuit
AC TEST CIRCUITS AND TIMING DIAGRAMS
Figure 2. Differential Driver AC Test Circuit
Figure 3. Propagation Delay Timing Diagram
Figure 4. LVDS Output Transition Times
PRE-EMPHASIS TEST CIRCUITS
Figure 5. Pre-emphasis Performance Test Circuit
6Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: DS25BR120
OUT+
OUT-
DS25BR120
IN+
IN-
100: Differential T-Line
LVDS
50: MS
50: MS
50: MS
50: MS
L=1" L=1"
L=1"L=1"
L = A, B or C
100: Diff.
Stripline
DS25BR120
www.ti.com
SNLS256E –MARCH 2007–REVISED APRIL 2013
Figure 6. Test Channel Description
Test Channel Loss Characteristics
The test channel was fabricated with Polyclad PCL-FR-370-Laminate/PCL-FRP-370 Prepreg materials (Dielectric
constant of 3.7 and Loss Tangent of 0.02). The edge coupled differential striplines have the following geometries:
Trace Width (W) = 5 mils, Gap (S) = 5 mils, Height (B) = 16 mils.
Test Channel Length Insertion Loss (dB)
(inches) 500 MHz 750 MHz 1000 MHz 1250 MHz 1500 MHz 1560 MHz
A 10 -1.2 -1.7 -2.0 -2.4 -2.7 -2.8
B 20 -2.6 -3.5 -4.1 -4.8 -5.5 -5.6
C 30 -4.3 -5.7 -7.0 -8.2 -9.4 -9.7
D 15 -1.6 -2.2 -2.7 -3.2 -3.7 -3.8
E 30 -3.4 -4.5 -5.6 -6.6 -7.7 -7.9
F 60 -7.8 -10.3 -12.4 -14.5 -16.6 -17.0
Device Operation
INPUT INTERFACING
The DS25BR120 accepts differential signals and allows simple AC or DC coupling. With a wide common mode
range, the DS25BR120 can be DC-coupled with all common differential drivers (i.e. LVPECL, LVDS, CML). The
following three figures illustrate typical DC-coupled interface to common differential drivers. Note that the
DS25BR120 inputs are internally terminated with a 100Ωresistor.
Figure 7. Typical LVDS Driver DC-Coupled Interface to DS25BR120 Input
Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback 7
Product Folder Links: DS25BR120
OUT+
OUT-
CML or
LVPECL or
LVDS
IN+
IN-
100:
100: Differential T-Line
DS25BR120
OUT+
OUT-
150-250:
100: Differential T-Line LVDS
Receiver
IN+
IN-
100:
LVPECL
Driver
150-250:
OUT+
OUT-
DS25BR120
IN+
IN-
50:50:
VCC
CML3.3V or CML2.5V
100: Differential T-Line
DS25BR120
SNLS256E –MARCH 2007–REVISED APRIL 2013
www.ti.com
Figure 8. Typical CML Driver DC-Coupled Interface to DS25BR120 Input
Figure 9. Typical LVPECL Driver DC-Coupled Interface to DS25BR120 Input
OUTPUT INTERFACING
The DS25BR120 outputs signals compliant to the LVDS standard. It can be DC-coupled to most common
differential receivers. The following figure illustrates typical DC-coupled interface to common differential receivers
and assumes that the receivers have high impedance inputs. While most differential receivers have a common
mode input range that can accommodate LVDS compliant signals, it is recommended to check the respective
receiver's datasheet prior to implementing the suggested interface implementation.
Figure 10. Typical DS25BR120 Output DC-Coupled Interface to an LVDS, CML or LVPECL Receiver
8Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated
Product Folder Links: DS25BR120
4.50
3.75
3.00
2.25
1.50
0.75
00 6 12 18 24 30
VCC = 3.3V
TA =25°C
NRZ PRBS-7
TJ = 0.5 UI
Maximum Data Rate (Gbps)
CAT5e LENGTH (m)
w/ PE and/or EQ
w/o PE and EQ
50
45
40
35
30
25
20 0 0.4 0.8 1.2 1.6 2.0
VCC = 3.3V
TA = 25°C
SUPPLY CURRENT (mA)
FREQUENCY (GHz)
PE = Off
PE = Low
PE = Medium
PE = High
4.50
3.75
3.00
2.25
1.50
0.75
00 3 6 9 12 15
VCC = 3.3V
TA = 25°C
NRZ PRBS-7
TJ = 0.25 UI
MAXIMUM DATA RATE (Gbps)
CAT7 LENGTH (m)
w/o PE
w/ PE
4.50
3.75
3.00
2.25
1.50
0.75
00 6 12 18 24 30
VCC = 3.3V
TA = 25°C
NRZ PRBS-7
TJ = 0.25 UI
MAXIMUM DATA RATE (Gbps)
CAT5e LENGTH (m)
w/ PE and/or EQ
w/o PE and EQ
4.50
3.75
3.00
2.25
1.50
0.75
00 3 6 9 12 15
VCC = 3.3V
TA = 25°C
NRZ PRBS-7
TJ = 0.25 UI
MAXIMUM DATA RATE (Gbps)
CAT5e LENGTH (m)
w/o PE
w/ PE
DS25BR120
www.ti.com
SNLS256E –MARCH 2007–REVISED APRIL 2013
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 11. Maximum Data Rate as a Function of CAT5e Figure 12. Maximum Data Rate as a Function of CAT5e
(Belden 1700A) Length (Belden 1700A) Length
DS25BR120 Used as a Driver
DS25BR110 Used as a Receiver
Figure 13. Power Supply Current as a Function of Figure 14. Maximum Data Rate as a Function of CAT7
Frequency (Siemon Tera) Length
Figure 15. Maximum Data Rate as a Function of CAT5e
(Belden 1700A) Length
DS25BR120 Used as a Driver
DS25BR110 Used as a Receiver
Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback 9
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DS25BR120
SNLS256E –MARCH 2007–REVISED APRIL 2013
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TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Figure 16. A 2.5 Gbps NRZ PRBS-7 After 40" Figure 17. A 3.125 Gbps NRZ PRBS-7 After 40"
Differential FR-4 Stripline Differential FR-4 Stripline
V:125 mV / DIV, H:75 ps / DIV V:125 mV / DIV, H:50 ps / DIV
Figure 18. An Equalized (with PE) 2.5 Gbps NRZ PRBS-7 Figure 19. An Equalized (with PE) 3.125 Gbps NRZ PRBS-7
After 40" After 40"
Differential FR-4 Stripline Differential FR-4 Stripline
V:125 mV / DIV, H:75 ps / DIV V:125 mV / DIV, H:50 ps / DIV
10 Submit Documentation Feedback Copyright © 2007–2013, Texas Instruments Incorporated
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DS25BR120
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SNLS256E –MARCH 2007–REVISED APRIL 2013
REVISION HISTORY
Changes from Revision D (April 2013) to Revision E Page
• Changed layout of National Data Sheet to TI format .......................................................................................................... 10
Copyright © 2007–2013, Texas Instruments Incorporated Submit Documentation Feedback 11
Product Folder Links: DS25BR120
PACKAGE OPTION ADDENDUM
www.ti.com 10-Dec-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
DS25BR120TSD/NOPB ACTIVE WSON NGQ 8 1000 RoHS & Green SN Level-3-260C-168 HR -40 to 85 2R120
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
DS25BR120TSD/NOPB WSON NGQ 8 1000 178.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Sep-2016
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DS25BR120TSD/NOPB WSON NGQ 8 1000 210.0 185.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 20-Sep-2016
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
8X 0.3
0.2
2 0.1
8X 0.5
0.3
2X
1.5
1.6 0.1
6X 0.5
0.8
0.7
0.05
0.00
B3.1
2.9 A
3.1
2.9
(0.1) TYP
WSON - 0.8 mm max heightNGQ0008A
PLASTIC SMALL OUTLINE - NO LEAD
4214922/A 03/2018
PIN 1 INDEX AREA
SEATING PLANE
0.08 C
1
45
8
PIN 1 ID 0.1 C A B
0.05 C
THERMAL PAD
EXPOSED
9
SYMM
SYMM
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
SCALE 4.000
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EXAMPLE BOARD LAYOUT
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
(1.6)
6X (0.5)
(2.8)
8X (0.25)
8X (0.6)
(2)
(R0.05) TYP ( 0.2) VIA
TYP
(0.75)
WSON - 0.8 mm max heightNGQ0008A
PLASTIC SMALL OUTLINE - NO LEAD
4214922/A 03/2018
SYMM
1
45
8
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:20X
9
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
SOLDER MASK
OPENING
SOLDER MASK
METAL UNDER
SOLDER MASK
DEFINED
EXPOSED METAL
METAL
SOLDER MASK
OPENING
SOLDER MASK DETAILS
NON SOLDER MASK
DEFINED
(PREFERRED)
EXPOSED METAL
www.ti.com
EXAMPLE STENCIL DESIGN
8X (0.25)
8X (0.6)
6X (0.5)
(1.79)
(1.47)
(2.8)
(R0.05) TYP
WSON - 0.8 mm max heightNGQ0008A
PLASTIC SMALL OUTLINE - NO LEAD
4214922/A 03/2018
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
EXPOSED PAD 9:
82% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X
SYMM
1
45
8
SYMM
METAL
TYP
9
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