HM621100A Series 1048576-word x 1-bit High Speed CMOS Static RAM Rev. 0.0 Dec. 1, 1995 Description The Hitachi HM621100A is a high speed 1M Static RAM organized as 1048576-word x 1bit. It realizes high speed access time (20/25/35 ns) and low power consumption, employing CMOS process technology and high speed circuit designing technology. It is most advantageous for the field where high speed and high density memory is required, such as the cache memory for main frame or 32-bit MPU. The HM621100A, packaged in a 400-mil plastic SOJ is available for high density mounting. Features * Single 5 V supply and high density 28-pin package (DIP and SOJ) * High speed Access time: 20/25/35 ns (max) * Low power dissipation Active mode: 350 mW (typ) Standby mode: 100 W (typ) * Completely static memory required No clock or timing strobe required * Equal access and cycle time * DirectlyTTLcompatible All inputs and outputs Ordering Information Type No. Access HM621100AP-20 HM621100AP-25 HM621100AP-35 20 ns 25 ns 35 ns HM621100ALP-20 HM621100ALP-25 HM621100ALP-35 20 ns 25 ns 35 ns HM621100AJP-20 HM621100AJP-25 HM621100AJP-35 20 ns 25 ns 35 ns HM621100ALJP-20 20 ns HM621100ALJP-25 25 ns HM621100ALJP-35 35 ns Time Package 400-mil 28-pin plastic DIP (DP-28C) 400-mil 28-pin plastic SOJ (CP-28D) HM621100A Series Pin Arrangement A0 1 28 VCC A1 2 27 A19 A2 3 26 A18 A3 4 25 A17 A4 5 24 A16 A5 6 23 A15 NC 7 22 A14 A6 8 21 NC A7 9 20 A13 A8 10 19 A12 A9 11 18 A11 Q 12 17 A10 WE VSS 13 16 D 14 15 CS (Top view) Pin Description Pin Name Function A0 - A19 Address D Input Q Output CS Chip select WE Write enable VCC Power supply VSS Ground 2 HM621100A Block Diagram A1 A2 A3 A4 A5 A6 A7 A8 A9 VCC Row decoder Memory array 512 x 2048 VSS Din Column I/O Dout Column decoder CS WE A19 A18 A17 A16A15 A14 A13 A12 A11 A0 A10 3 Series HM621100A Series Function Table CS WE Mode VCC Current Output Pin Ref. Cycle H X Not selected ISB, ISB1 High-Z -- L H Read ICC Dout Read cycle L L Write ICC High-Z Write cycle Note: X : H or L Absolute Maximum Ratings Parameter Symbol Value Unit *1 Voltage on any pin relative to VSS Vin -0.5 to +7.0 V Power dissipation PT 1.0 W Operating temperature range Topr 0 to +70 C Storage temperature range Tstg -55 to +125 C Storage temperature range under bias Tbias -10 to +85 C Note: 1. Vin min = -2.0 V for pulse width 10 ns. Recommended DC Operating Conditions (Ta = 0 to +70C) Parameter Symbol Min Typ Max Unit Supply voltage VCC 4.5 5.0 5.5 V VSS 0 0 0 V VIH 2.2 -- 6.0 V -- 0.8 V Input high (logic 1) voltage Input low (logic 0) voltage Note: 4 VIL 1. VIL min = -2.0 V for pulse width 10 ns. -0.5 *1 HM621100A Series DC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, VSS = 0 V) HM621100A-20 HM621100A25/35 Parameter Symbol Min Typ*1 Max Min Typ*1 Max Unit Test Conditions Input leakage current |ILI| -- -- 2.0 -- -- 2.0 A VCC = max Vin = VSS to VCC Output leakage current |ILO| -- -- 2.0 -- -- 2.0 A CS = VIH VI/O = VSS to VCC Operating power supply current ICC -- -- 150 -- -- 120 mA CS = VIL, II/O = 0 mA, min cycle Standby power supply current ISB -- -- 60 -- -- 40 mA CS = VIH, min cycle *2 SB1 -- 0.02 2.0 -- 0.02 2.0 mA CS VCC -0.2 V 0 V Vin 0.2 V or Vin VCC -0.2 V ISB1*3 -- -- 100 -- -- 100 A Output low voltage VOL -- -- 0.4 -- -- 0.4 V IOL = 8 mA Output high voltage VOH 2.4 -- -- 2.4 -- -- V IOH = -4 mA Standby power supply current (1) I Notes: 1. Typical values are at VCC = 5.0 V, Ta = +25C and not guaranteed. 2. P and JP version 3. LP and LJP version Capacitance (Ta = 25C, f = 1 MHz) Parameter Symbol Min Max Unit Test Conditions Input capacitance Cin -- 5*2 pF Vin = 0 V pF Vout = 0 V 6 Output capacitance Cout -- 8 *3 Notes: 1. This parameter is sampled and not 100% tested. 2. SOJ package 3. DIP package AC Characteristics (Ta = 0 to +70C, VCC = 5 V 10%, unless otherwise noted.) Test Conditions _ Input pulse levels: 0 V to 3.0 V _ Input rise and fall time: 4 ns _ Input timing reference levels: 1.5 V _ Output timing reference levels: 1.5 V _ Output load: See figures 5 HM621100A Series +5V +5V 480 480 Dout Dout 255 255 30 pF *1 Output load (A) 5 pF *1 Output load (B) (For tHZ , tLZ, tWZ and tOW) Note: 1. Including scope and jig Read Cycle HM621100A20 HM621100A25 HM621100A35 Parameter Symbol Min Max Min Max Min Max Unit Read cycle time tRC 20 -- 25 -- 35 -- ns Address access time tAA -- 20 -- 25 -- 35 ns Chip select access time tACS Chip selection to output in low-Z -- 20 -- 25 -- 35 ns *1 5 -- 5 -- 5 -- ns *1 HZ tLZ Chip deselection to output in high-Z t 0 10 0 12 0 15 ns Output hold from address change tOH 5 -- 5 -- 5 -- ns Chip selection to power up time tPU 0 -- 0 -- 0 -- ns -- 12 -- 15 -- 25 ns Chip deselection to power down time tPD Note: 1. Transition is measured 200 mV from high impedance voltage with Load (B). This parameter is sampled and not 100% tested. Read Timing Waveform (1) (W E = VIH, CS = VIL) tRC Address tAA tOH tOH Dout 6 Valid Data HM621100A Series Read Timing Waveform (2) (W E = VIH) *1 tRC CS tHZ tACS tLZ Dout Valid Data High-Z High-Z tPD tPU VCCsupply Current 50% 50% ICC ISB Note: 1. Address valid prior to or coincident with CS transition low. Write Cycle HM621100A-20 HM621100A-25 HM621100A-35 Parameter Symbol Min Max Min Max Min Max Unit Write cycle time tWC 20 -- 25 -- 35 -- ns Chip selection to end of write tCW 15 -- 17 -- 25 -- ns Address valid to end of write tAW 16 -- 20 -- 30 -- ns Address setup time tAS 0 -- 0 -- 0 -- ns *2 15 -- 17 -- 25 -- ns Write recovery time tWR *3 0 -- 0 -- 0 -- ns Write to output in high-Z tWZ*1 0 12 0 15 0 15 ns Data to write time overlap tDW 12 -- 15 -- 20 -- ns Data hold from write time tDH Write pulse width tWP 0 -- 0 -- 0 -- ns Output active from end of write tOW *1 0 -- 0 -- 0 -- ns Output hold from address change tOH*4 5 -- 5 -- 5 -- ns Notes: 1. Transition is measured 200 mV from high impedance voltage with Load (B). This parameter is sampled and not 100% tested. 2. A write occurs during the overlap of a low CS and a low WE. 3. tWR is measured from the earlier of CS or WE going high to the end of write cycle. 4. Dout is the same phase of write data of this write cycle, if tWR is long enough. 7 HM621100A Series Write Timing Waveform (1) (W E Controlled) tWC Address tCW CS tAW tAS tWR tWP WE tDW Valid Data Din tWZ Dout 8 tDH tOW High-Z tOH HM621100A Series Write Timing Waveform (2) (CS Controlled) tWC Address tAW tWR tAS tCW CS tWP WE tDW Din tDH Valid Data High-Z *1 Dout Note: 1. If the CS low transition occurs simultaneously with the WE low transition or after the WE transition, the output buffers remain in a high impedance state. Low VCC Data Retention Characteristics (Ta = 0 to +70C) This characteristics is guaranteed only for L-version. Parameter Symbol Min Typ Max Unit Test VCC for data retention VDR 2.0 -- -- V CS VCC -0.2 V, Vin VCC -0.2 V or 0 V Vin 0.2 V Data retention current ICCDR -- 2 50*1 A Chip deselect to data retention time tCDR 0 -- -- ns Operation recovery time tR 5 -- -- ms Note: 1. VCC = 3.0 V 9 Conditions HM621100A Series Low VCC Data Retention Timing Waveform Data retention mode VCC 4.5 V tR tCDR 2.2 V VDR CS VCC-0.2 V 0V Low Level Input Voltage V IL (Normalized) CS 1.3 Ta=25C 1.2 1.1 1.0 0.9 0.8 0.7 4.5 4.75 5.0 5.25 5.5 Supply Voltage Vcc (V) High Level Input Voltage V IH (Normalized) Low Level Input Voltage vs. Supply Voltage 1.3 Ta=25C 1.2 1.1 1.0 0.9 0.8 0.7 4.5 4.75 5.0 5.25 5.5 Supply Voltage Vcc (V) High Level Input Voltage vs. Supply Voltage 10 High Level Output Current IOH (Normalized) HM621100A 1.6 Ta=25C Vcc=5V 1.4 1.2 1.0 0.8 0.6 0.4 1 2 3 4 5 High Level Output Voltage VOH (V) Low Level Output Current I OL (Normalized) High Level Output Current vs. High Level Output Voltage 1.6 Ta=25C Vcc=5V 1.4 1.2 1.0 0.8 0.6 0.4 0 0.2 0.4 0.6 0.8 Low Level Output Voltage VOL (V) Low Level Output Current vs. Low Level Output Voltage 10 -4 Standby Current ISB1 (A) Vcc=3V CS=2.8V 10 -5 10 -6 10 -7 0 20 40 60 80 Ambient Temperature Ta (C) Standby Current vs. Ambient Temperature 11 Series HM621100A Series Standby Current ISB1 (Normalized) 1.4 1.2 1.0 0.8 0.6 Ta=25C CS=Vcc-0.2V 0.4 0.2 2 3 4 6 5 Supply Voltage Vcc (V) Standby Current vs. Supply Voltage 1.6 Ta=25C Supply Current Icc (Normalized) 1.4 1.2 1.0 0.8 0.6 0.4 4.5 4.75 5.0 5.25 5.5 Supply Voltage Vcc (V) Supply Current vs. Supply Voltage 1.6 Vcc=5.0V Supply Current Icc (Normalized) 1.4 1.2 1.0 0.8 0.6 0.4 0 20 40 60 80 Ambient Temperature Ta (C) Supply Current vs. Ambient Temperature 12 HM621100A 1.3 Access Time t AA ,t ACS (Normalized) Ta=25C 1.2 1.1 1.0 0.9 0.8 0.7 4.5 4.75 5.0 5.25 5.5 Supply Voltage Vcc (V) Access Time vs. Supply Voltage Access Time t AA ,tACS (Normalized) 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0 50 100 150 200 Load Capacitance C L (pF) Access Time vs. Load Capacitance Access Time tAA ,tACS (Normalized) 1.3 Vcc=5.0V 1.2 1.1 1.0 0.9 0.8 0.7 0 20 40 60 80 Ambient Temperature Ta (C) Access Time vs. Ambient Temperature 13 Series HM621100A Series Supply Current Icc (Normalized) 1.4 100 50 33 25 T (ns) 20 10 20 30 40 50 1.2 1.0 0.8 0.6 0.4 0.2 0 Frequency f (MHz) Supply Current vs. Frequency 14 HM621100A Package Series Dimensions HM621100AP/ALP Series (DP-28C) Unit: mm 15 HM621100A Series HM621100AJP/ALJP Series (CP-28D) 16 Unit: mm