HM621100A Series
1048576-word × 1-bit High Speed CMOS Static RAM
Rev. 0.0
Dec. 1, 1995
Description
The Hitachi HM621100A is a high speed 1M Static RAM organized as 1048576-word × 1-
bit. It realizes high speed access time (20/25/35 ns) and low power consumption, employing
CMOS process technology and high speed circuit designing technology. It is most
advantageous for the field where high speed and high density memory is required, such as
the cache memory for main frame or 32-bit MPU. The HM621100A, packaged in a 400-mil
plastic SOJ is available for high density mounting.
Features
• Single 5 V supply and high density 28-pin package (DIP and SOJ)
• High speed
Access time: 20/25/35 ns (max)
• Low power dissipation
Active mode: 350 mW (typ)
Standby mode: 100 µW (typ)
• Completely static memory required
No clock or timing strobe required
• Equal access and cycle time
• Directly TTL compatible
All inputs and outputs
Ordering Information
Type No. Access Time Package
HM621100AP-20
HM621100AP-25
HM621100AP-35
20 ns
25 ns
35 ns
400-mil 28-pin plastic DIP (DP-28C)
HM621100ALP-20
HM621100ALP-25
HM621100ALP-35
20 ns
25 ns
35 ns
HM621100AJP-20
HM621100AJP-25
HM621100AJP-35
20 ns
25 ns
35 ns
400-mil 28-pin plastic SOJ (CP-28D)
HM621100ALJP-20
HM621100ALJP-25
HM621100ALJP-35
20 ns
25 ns
35 ns
HM621100A Series
2
Pin Arrangement
A19
Q
27
1A0
2A1
3A2
4A3
5A4
6A5
7NC
8A6
9A7
10A8
11A9
12
13
14
VSS
WE
VCC
28
A1826
A1725
A1624
A1523
A1422
NC21
A1320
A1219
A1118
A1017
D16
CS15
(Top view)
Pin Description
Pin Name Function
A0 – A19 Address
D Input
Q Output
CS Chip select
WE Write enable
VCC Power supply
VSS Ground
HM621100A Series
3
Block Diagram
A19 A18 A17 A16
VCC
VSS
Memory array
512 × 2048
Row
decoder
Column I/O
Column decoder
Din
CS
WE A0
Dout
A1
A2
A3
A4
A5
A6
A7
A8
A9
A15 A14 A13 A12 A11 A10
HM621100A Series
4
Function Table
CS WE Mode VCC Current Output Pin Ref. Cycle
H X Not selected ISB, ISB1 High-Z —
L H Read ICC Dout Read cycle
L L Write ICC High-Z Write cycle
Note: X : H or L
Absolute Maximum Ratings
Parameter Symbol Value Unit
Voltage on any pin relative to VSS Vin –0.5*1 to +7.0 V
Power dissipation PT1.0 W
Operating temperature range Topr 0 to +70 °C
Storage temperature range Tstg –55 to +125 °C
Storage temperature range under bias Tbias –10 to +85 °C
Note: 1. Vin min = –2.0 V for pulse width ≤ 10 ns.
Recommended DC Operating Conditions (Ta = 0 to +70°C)
Parameter Symbol Min Typ Max Unit
Supply voltage VCC 4.5 5.0 5.5 V
VSS 000V
Input high (logic 1) voltage VIH 2.2 — 6.0 V
Input low (logic 0) voltage VIL –0.5*1 — 0.8 V
Note: 1. VIL min = –2.0 V for pulse width ≤ 10 ns.
HM621100A Series
5
DC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, VSS = 0 V)
HM621100A-20 HM621100A-
25/35
Parameter Symbol Min Typ*1 Max Min Typ*1 Max Unit Test
Conditions
Input leakage current |ILI| — — 2.0 — — 2.0 µAV
CC = max
Vin = VSS to VCC
Output leakage current |ILO| — — 2.0 — — 2.0 µACS = VIH
VI/O = VSS to VCC
Operating power supply
current ICC — — 150 — — 120 mA CS = VIL, II/O = 0 mA,
min cycle
Standby power supply current ISB ——60—— 40mACS = VIH, min cycle
Standby power supply current
(1) ISB1*2 — 0.02 2.0 — 0.02 2.0 mA CS ≥ VCC –0.2 V
0 V ≤ Vin ≤ 0.2 V or
Vin ≥ VCC –0.2 V
ISB1*3 — — 100 — — 100 µA
Output low voltage VOL — — 0.4 — — 0.4 V IOL = 8 mA
Output high voltage VOH 2.4 — — 2.4 — — V IOH = –4 mA
Notes: 1. Typical values are at VCC = 5.0 V, Ta = +25°C and not guaranteed.
2. P and JP version
3. LP and LJP version
Capacitance (Ta = 25°C, f = 1 MHz)
Parameter Symbol Min Max Unit Test
Conditions
Input capacitance Cin — 5*2 pF Vin = 0 V
6*3
Output capacitance Cout — 8 pF Vout = 0 V
Notes: 1. This parameter is sampled and not 100% tested.
2. SOJ package
3. DIP package
AC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, unless otherwise noted.)
Test Conditions
_Input pulse levels: 0 V to 3.0 V
_Input rise and fall time: 4 ns
_Input timing reference levels: 1.5 V
_Output timing reference levels: 1.5 V
_Output load: See figures
HM621100A Series
6
Output load (A)
Output load (B)
(For tHZ , tLZ, tWZ and tOW)
Note: 1. Including scope and jig
+ 5 V
480 Ω
5 pF *1
255 Ω
Dout
+ 5 V
480 Ω
30 pF *1
255 Ω
Dout
Read Cycle HM621100A-
20 HM621100A-
25 HM621100A-
35
Parameter Symbol Min Max Min Max Min Max Unit
Read cycle time tRC 20 — 25 — 35 — ns
Address access time tAA — 20 — 25 — 35 ns
Chip select access time tACS — 20 — 25 — 35 ns
Chip selection to output in low-Z tLZ*1 5—5—5 —ns
Chip deselection to output in high-Z tHZ*1 0 10 0 12 0 15 ns
Output hold from address change tOH 5—5—5 —ns
Chip selection to power up time tPU 0—0—0 —ns
Chip deselection to power down time tPD — 12 — 15 — 25 ns
Note: 1. Transition is measured ±200 mV from high impedance voltage with Load (B). This parameter is
sampled and not 100% tested.
Read Timing Waveform (1) (WE = VIH, CS = VIL)
tRC
Address
tAA
tOH
Dout Valid Data
tOH
HM621100A Series
7
Read Timing Waveform (2)*1 (WE = VIH)
tRC
tACS
tLZ
tPU
High-Z
50%
Valid Data
tPD
50%
High-Z
tHZ
CS
Dout
VCCsupply
Current ICC
ISB
Note: 1. Address valid prior to or coincident with CS transition low.
Write Cycle HM621100A-20 HM621100A-25 HM621100A-35
Parameter Symbol Min Max Min Max Min Max Unit
Write cycle time tWC 20 — 25 — 35 — ns
Chip selection to end of write tCW 15 — 17 — 25 — ns
Address valid to end of write tAW 16 — 20 — 30 — ns
Address setup time tAS 0—0—0—ns
Write pulse width tWP*2 15 — 17 — 25 — ns
Write recovery time tWR*3 0—0—0—ns
Write to output in high-Z tWZ*1 012015015ns
Data to write time overlap tDW 12 — 15 — 20 — ns
Data hold from write time tDH 0—0—0—ns
Output active from end of write tOW*1 0—0—0—ns
Output hold from address
change tOH*4 5—5—5—ns
Notes: 1. Transition is measured ±200 mV from high impedance voltage with Load (B). This parameter is
sampled and not 100% tested.
2. A write occurs during the overlap of a low CS and a low WE.
3. tWR is measured from the earlier of CS or WE going high to the end of write cycle.
4. Dout is the same phase of write data of this write cycle, if tWR is long enough.
HM621100A Series
8
Write Timing Waveform (1) (WE Controlled)
Address
CS
WE
Dout
Din
tWC
tCW
tAW
tAS
tDW tDH
tWZ
High-Z tOW
tWR
tWP
tOH
Valid Data
HM621100A Series
9
Write Timing Waveform (2) (CS Controlled)
Address
CS
WE
Dout
Din
tWC
tAW
tAS tCW tWR
tWP
tDW tDH
Valid Data
High-Z *1
Note: 1. If the CS low transition occurs simultaneously with the WE low
transition or after the WE transition, the output buffers remain in a high
impedance state.
Low VCC Data Retention Characteristics (Ta = 0 to +70°C)
This characteristics is guaranteed only for L-version.
Parameter Symbol Min Typ Max Unit Test Conditions
VCC for data retention VDR 2.0 — — V CS ≥ VCC –0.2 V,
Vin ≥ VCC –0.2 V or
0 V ≤ Vin ≤ 0.2 V
Data retention current ICCDR —2 50
*1 µA
Chip deselect to data retention time tCDR 0——ns
Operation recovery time tR5——ms
Note: 1. VCC = 3.0 V
HM621100A Series
10
Low VCC Data Retention Timing Waveform
VCC
CS
4.5 V
2.2 V
VDR
0 V
tCDR
Data retention mode
tR
CS ≥ VCC–0.2 V
4.5 4.75 5.0 5.25 5.5
0.7
0.8
0.9
1.0
1.1
1.2
1.3
Low Level Input Voltage V (Normalized)
Supply Voltage Vcc (V)
IL
Ta=25°C
Low Level Input Voltage vs. Supply Voltage
4.5 4.75 5.0 5.25 5.5
0.7
0.8
0.9
1.0
1.1
1.2
1.3
High Level Input Voltage V (Normalized)
Supply Voltage Vcc (V)
IH
Ta=25°C
High Level Input Voltage vs. Supply Voltage
HM621100A Series
11
12345
0.4
0.6
0.8
1.0
1.2
1.4
1.6
High Level Output Current I (Normalized)
High Level Output Voltage V (V)
OH
OH
Ta=25°C
Vcc=5V
High Level Output Current vs. High Level Output Voltage
0.4
0.6
0.8
1.0
1.2
1.4
1.6
0 0.2 0.4 0.6 0.8
Low Level Output Current I (Normalized)
Low Level Output Voltage V (V)
OL
OL
Ta=25°C
Vcc=5V
Low Level Output Current vs. Low Level Output Voltage
10
10
10
10 020406080
-4
-5
-6
-7
Standby Current I (A)
Ambient Temperature Ta (°C)
SB1
Vcc=3V
CS=2.8V
Standby Current vs. Ambient Temperature
HM621100A Series
12
23456
0.2
0.4
0.6
0.8
1.0
1.2
1.4
Standby Current I (Normalized)
Supply Voltage Vcc (V)
SB1
Ta=25°C
CS=Vcc-0.2V
Standby Current vs. Supply Voltage
4.5 4.75 5.0 5.25 5.5
0.4
0.6
0.8
1.0
1.2
1.4
1.6
Supply Current Icc (Normalized)
Supply Voltage Vcc (V)
Ta=25°C
Supply Current vs. Supply Voltage
0 20406080
0.4
0.6
0.8
1.0
1.2
1.4
1.6
Supply Current Icc (Normalized)
Ambient Temperature Ta (°C)
Vcc=5.0V
Supply Current vs. Ambient Temperature
HM621100A Series
13
4.5 4.75 5.0 5.25 5.5
0.7
0.8
0.9
1.0
1.1
1.2
1.3
Access Time t ,t (Normalized)
Supply Voltage Vcc (V)
ACSAA
Ta=25°C
Access Time vs. Supply Voltage
0.6
0.8
1.0
1.2
1.4
1.6
1.8
0 50 100 150 200
Access Time t ,t (Normalized)
Load Capacitance C (pF)
L
AA ACS
Access Time vs. Load Capacitance
Access Time t ,t (Normalized)
Ambient Temperature Ta (°C)
AA ACS
0204060
80
0.7
0.8
0.9
1.0
1.1
1.2
1.3 Vcc=5.0V
Access Time vs. Ambient Temperature
HM621100A Series
14
010 3040
50
0.2
0.4
0.6
0.8
1.0
1.2
1.4
Supply Current Icc (Normalized)
Frequency f (MHz)
20
100 33 25 20
50 T (ns)
Supply Current vs. Frequency
HM621100A Series
15
Package Dimensions
HM621100AP/ALP Series (DP-28C) Unit: mm
HM621100A Series
16
HM621100AJP/ALJP Series (CP-28D) Unit: mm