© 2007-2012, 2014 Freescale Semiconductor, Inc. All rights reserved.
Freescale Semiconductor
Technical Data
Freescale reserves the right to change the detail specifications as may be required
to permit improvements in the design of its products.
1 Overview
This section provides a high-level overview of the device
features. The following figure shows the major functional
units within the device.
Although this document is written from the perspective of
the MPC8548E, most of the material applies to the other
family members, such as MPC8547E, MPC8545E, and
MPC8543E. When specific differences occur, such as pinout
differences and processor frequency ranges, they are
identified as such.
For specific PVR and SVR numbers, see the MPC8548E
PowerQUICC III Integrated Host Processor Reference
Manual.
Contents
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . 10
3. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 15
4. Input Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
5. RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 19
6. DDR and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . 20
7. DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
8. Enhanced Three-Speed Ethernet (eTSEC) . . . . . . . . 27
9. Ethernet Management Interface Electrical
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
10. Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
11. Programmable Interrupt Controller . . . . . . . . . . . . . 53
12. JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
13. I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
14. GPOUT/GPIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
15. PCI/PCI-X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
16. High-Speed Serial Interfaces (HSSI) . . . . . . . . . . . . 65
17. PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
18. Serial RapidIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
19. Package Description . . . . . . . . . . . . . . . . . . . . . . . . . 91
20. Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
21. Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
22. System Design Information . . . . . . . . . . . . . . . . . . 135
23. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 145
24. Document Revision History . . . . . . . . . . . . . . . . . . 148
MPC8548E PowerQUICC III
Integrated Processor
Hardware Specifications
Document Number: MPC8548EEC
Rev. 10, 06/2014
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 10
2Freescale Semiconductor
Overview
Figure 1. Device Block Diagram
1.1 Key Features
The following list provides an overview of the device feature set:
High-performance 32-bit core built on Power Architecture® technology.
32-Kbyte L1 instruction cache and 32-Kbyte L1 data cache with parity protection. Caches can
be locked entirely or on a per-line basis, with separate locking for instructions and data.
Signal-processing engine (SPE) APU (auxiliary processing unit). Provides an extensive
instruction set for vector (64-bit) integer and fractional operations. These instructions use both
the upper and lower words of the 64-bit GPRs as they are defined by the SPE APU.
Double-precision floating-point APU. Provides an instruction set for double-precision (64-bit)
floating-point instructions that use the 64-bit GPRs.
36-bit real addressing
Embedded vector and scalar single-precision floating-point APUs. Provide an instruction set
for single-precision (32-bit) floating-point instructions.
Memory management unit (MMU). Especially designed for embedded applications. Supports
4-Kbyte to 4-Gbyte page sizes.
Enhanced hardware and software debug support
Core Complex
x8 PCI Express
4x RapidIO
66 MHz
PCI 32-bit
10/100/1Gb
MII, GMII, TBI,
RTBI, RGMII,
Serial
IRQs
SDRAM
DDR
Flash
SDRAM
GPIO
Bus
I2CI2C
Controller
eTSEC
32-bit PCI Bus Interface
(If 64-bit not used)
e500
Coherency
Module
DDR/DDR2/
Memory Controller
Local Bus Controller
Programmable Interrupt
Controller (PIC)
DUART
e500 Core
512-Kbyte
L2 Cache/
SRAM
32-bit PCI/
64-bit PCI/PCI-X
Bus Interface
32-Kbyte L1
Instruction
Cache
32-Kbyte
L1 Data
Cache
OceaN
Switch
Fabric
Serial RapidIO
or
PCI Express
4-Channel DMA
Controller
133 MHz
PCI/PCI-X
I2CI2C
Controller
RMII
10/100/1Gb
MII, GMII, TBI,
RTBI, RGMII,
eTSEC
RMII
10/100/1Gb
MII, GMII, TBI,
RTBI, RGMII,
eTSEC
RMII
10/100/1Gb
RTBI, RGMII, eTSEC
Security
Engine
XOR
Engine
RMII
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 10
Freescale Semiconductor 3
Overview
Performance monitor facility that is similar to, but separate from, the device performance
monitor
The e500 defines features that are not implemented on this device. It also generally defines some features
that this device implements more specifically. An understanding of these differences can be critical to
ensure proper operations.
512-Kbyte L2 cache/SRAM
Flexible configuration.
Full ECC support on 64-bit boundary in both cache and SRAM modes
Cache mode supports instruction caching, data caching, or both.
External masters can force data to be allocated into the cache through programmed memory
ranges or special transaction types (stashing).
1, 2, or 4 ways can be configured for stashing only.
Eight-way set-associative cache organization (32-byte cache lines)
Supports locking entire cache or selected lines. Individual line locks are set and cleared through
Book E instructions or by externally mastered transactions.
Global locking and Flash clearing done through writes to L2 configuration registers
Instruction and data locks can be Flash cleared separately.
SRAM features include the following:
I/O devices access SRAM regions by marking transactions as snoopable (global).
Regions can reside at any aligned location in the memory map.
Byte-accessible ECC is protected using read-modify-write transaction accesses for
smaller-than-cache-line accesses.
Address translation and mapping unit (ATMU)
Eight local access windows define mapping within local 36-bit address space.
Inbound and outbound ATMUs map to larger external address spaces.
Three inbound windows plus a configuration window on PCI/PCI-X and PCI Express
Four inbound windows plus a default window on RapidIO™
Four outbound windows plus default translation for PCI/PCI-X and PCI Express
Eight outbound windows plus default translation for RapidIO with segmentation and
sub-segmentation support
DDR/DDR2 memory controller
Programmable timing supporting DDR and DDR2 SDRAM
64-bit data interface
Four banks of memory supported, each up to 4 Gbytes, to a maximum of 16 Gbytes
DRAM chip configurations from 64 Mbits to 4 Gbits with ×8/×16 data ports
Full ECC support
Page mode support
Up to 16 simultaneous open pages for DDR
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 10
4Freescale Semiconductor
Overview
Up to 32 simultaneous open pages for DDR2
Contiguous or discontiguous memory mapping
Read-modify-write support for RapidIO atomic increment, decrement, set, and clear
transactions
Sleep mode support for self-refresh SDRAM
On-die termination support when using DDR2
Supports auto refreshing
On-the-fly power management using CKE signal
Registered DIMM support
Fast memory access via JTAG port
2.5-V SSTL_2 compatible I/O (1.8-V SSTL_1.8 for DDR2)
Support for battery-backed main memory
Programmable interrupt controller (PIC)
Programming model is compliant with the OpenPIC architecture.
Supports 16 programmable interrupt and processor task priority levels
Supports 12 discrete external interrupts
Supports 4 message interrupts with 32-bit messages
Supports connection of an external interrupt controller such as the 8259 programmable
interrupt controller
Four global high-resolution timers/counters that can generate interrupts
Supports a variety of other internal interrupt sources
Supports fully nested interrupt delivery
Interrupts can be routed to external pin for external processing.
Interrupts can be routed to the e500 cores standard or critical interrupt inputs.
Interrupt summary registers allow fast identification of interrupt source.
Integrated security engine (SEC) optimized to process all the algorithms associated with IPSec,
IKE, WTLS/WAP, SSL/TLS, and 3GPP
Four crypto-channels, each supporting multi-command descriptor chains
Dynamic assignment of crypto-execution units via an integrated controller
Buffer size of 256 bytes for each execution unit, with flow control for large data sizes
PKEU—public key execution unit
RSA and Diffie-Hellman; programmable field size up to 2048 bits
Elliptic curve cryptography with F2m and F(p) modes and programmable field size up to
511 bits
DEU—Data Encryption Standard execution unit
DES, 3DES
Two key (K1, K2) or three key (K1, K2, K3)
ECB and CBC modes for both DES and 3DES
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 10
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Overview
AESU—Advanced Encryption Standard unit
Implements the Rijndael symmetric key cipher
ECB, CBC, CTR, and CCM modes
128-, 192-, and 256-bit key lengths
AFEU—ARC four execution unit
Implements a stream cipher compatible with the RC4 algorithm
40- to 128-bit programmable key
MDEU—message digest execution unit
SHA with 160- or 256-bit message digest
MD5 with 128-bit message digest
HMAC with either algorithm
KEU—Kasumi execution unit
Implements F8 algorithm for encryption and F9 algorithm for integrity checking
Also supports A5/3 and GEA-3 algorithms
RNG—random number generator
XOR engine for parity checking in RAID storage applications
Dual I2C controllers
Two-wire interface
Multiple master support
Master or slave I2C mode support
On-chip digital filtering rejects spikes on the bus
Boot sequencer
Optionally loads configuration data from serial ROM at reset via the I2C interface
Can be used to initialize configuration registers and/or memory
Supports extended I2C addressing mode
Data integrity checked with preamble signature and CRC
DUART
Two 4-wire interfaces (SIN, SOUT, RTS, CTS)
Programming model compatible with the original 16450 UART and the PC16550D
Local bus controller (LBC)
Multiplexed 32-bit address and data bus operating at up to 133 MHz
Eight chip selects support eight external slaves
Up to eight-beat burst transfers
The 32-, 16-, and 8-bit port sizes are controlled by an on-chip memory controller.
Three protocol engines available on a per chip select basis:
General-purpose chip select machine (GPCM)
Three user programmable machines (UPMs)
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 10
6Freescale Semiconductor
Overview
Dedicated single data rate SDRAM controller
Parity support
Default boot ROM chip select with configurable bus width (8, 16, or 32 bits)
Four enhanced three-speed Ethernet controllers (eTSECs)
Three-speed support (10/100/1000 Mbps)
Four controllers designed to comply with IEEE Std. 802.3®, 802.3u, 802.3x, 802.3z, 802.3ac,
and 802.3ab
Support for various Ethernet physical interfaces:
1000 Mbps full-duplex IEEE 802.3 GMII, IEEE 802.3z TBI, RTBI, and RGMII
10/100 Mbps full and half-duplex IEEE 802.3 MII, IEEE 802.3 RGMII, and RMII
Flexible configuration for multiple PHY interface configurations. See Section 8.1, “Enhanced
Three-Speed Ethernet Controller (eTSEC)
(10/100/1Gb Mbps)—GMII/MII/TBI/RGMII/RTBI/RMII Electrical Characteristics,” for
more information.
TCP/IP acceleration and QoS features available
IP v4 and IP v6 header recognition on receive
IP v4 header checksum verification and generation
TCP and UDP checksum verification and generation
Per-packet configurable acceleration
Recognition of VLAN, stacked (queue in queue) VLAN, IEEE Std 802.2™, PPPoE session,
MPLS stacks, and ESP/AH IP-security headers
Supported in all FIFO modes
Quality of service support:
Transmission from up to eight physical queues
Reception to up to eight physical queues
Full- and half-duplex Ethernet support (1000 Mbps supports only full duplex):
IEEE 802.3 full-duplex flow control (automatic PAUSE frame generation or
software-programmed PAUSE frame generation and recognition)
Programmable maximum frame length supports jumbo frames (up to 9.6 Kbytes) and
IEEE Std. 802.1™ virtual local area network (VLAN) tags and priority
VLAN insertion and deletion
Per-frame VLAN control word or default VLAN for each eTSEC
Extracted VLAN control word passed to software separately
Retransmission following a collision
CRC generation and verification of inbound/outbound frames
Programmable Ethernet preamble insertion and extraction of up to 7 bytes
MAC address recognition:
Exact match on primary and virtual 48-bit unicast addresses
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 10
Freescale Semiconductor 7
Overview
VRRP and HSRP support for seamless router fail-over
Up to 16 exact-match MAC addresses supported
Broadcast address (accept/reject)
Hash table match on up to 512 multicast addresses
Promiscuous mode
Buffer descriptors backward compatible with MPC8260 and MPC860T 10/100 Ethernet
programming models
RMON statistics support
10-Kbyte internal transmit and 2-Kbyte receive FIFOs
MII management interface for control and status
Ability to force allocation of header information and buffer descriptors into L2 cache
OCeaN switch fabric
Full crossbar packet switch
Reorders packets from a source based on priorities
Reorders packets to bypass blocked packets
Implements starvation avoidance algorithms
Supports packets with payloads of up to 256 bytes
Integrated DMA controller
Four-channel controller
All channels accessible by both the local and remote masters
Extended DMA functions (advanced chaining and striding capability)
Support for scatter and gather transfers
Misaligned transfer capability
Interrupt on completed segment, link, list, and error
Supports transfers to or from any local memory or I/O port
Selectable hardware-enforced coherency (snoop/no snoop)
Ability to start and flow control each DMA channel from external 3-pin interface
Ability to launch DMA from single write transaction
Two PCI/PCI-X controllers
PCI 2.2 and PCI-X 1.0 compatible
One 32-/64-bit PCI/PCI-X port with support for speeds of up to 133 MHz (maximum PCI-X
frequency in synchronous mode is 110 MHz)
One 32-bit PCI port with support for speeds from 16 to 66 MHz (available when the other port
is in 32-bit mode)
Host and agent mode support
64-bit dual address cycle (DAC) support
PCI-X supports multiple split transactions
Supports PCI-to-memory and memory-to-PCI streaming
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 10
8Freescale Semiconductor
Overview
Memory prefetching of PCI read accesses
Supports posting of processor-to-PCI and PCI-to-memory writes
PCI 3.3-V compatible
Selectable hardware-enforced coherency
Serial RapidIO™ interface unit
Supports RapidIO™ Interconnect Specification, Revision 1.2
Both 1× and 4× LP-serial link interfaces
Long- and short-haul electricals with selectable pre-compensation
Transmission rates of 1.25, 2.5, and 3.125 Gbaud (data rates of 1.0, 2.0, and 2.5 Gbps) per lane
Auto detection of 1- and 4-mode operation during port initialization
Link initialization and synchronization
Large and small size transport information field support selectable at initialization time
34-bit addressing
Up to 256 bytes data payload
All transaction flows and priorities
Atomic set/clr/inc/dec for read-modify-write operations
Generation of IO_READ_HOME and FLUSH with data for accessing cache-coherent data at
a remote memory system
Receiver-controlled flow control
Error detection, recovery, and time-out for packets and control symbols as required by the
RapidIO specification
Register and register bit extensions as described in part VIII (Error Management) of the
RapidIO specification
Hardware recovery only
Register support is not required for software-mediated error recovery.
Accept-all mode of operation for fail-over support
Support for RapidIO error injection
Internal LP-serial and application interface-level loopback modes
Memory and PHY BIST for at-speed production test
RapidIO-compatible message unit
4 Kbytes of payload per message
Up to sixteen 256-byte segments per message
Two inbound data message structures within the inbox
Capable of receiving three letters at any mailbox
Two outbound data message structures within the outbox
Capable of sending three letters simultaneously
Single segment multicast to up to 32 devIDs
Chaining and direct modes in the outbox
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 10
Freescale Semiconductor 9
Overview
Single inbound doorbell message structure
Facility to accept port-write messages
PCI Express interface
PCI Express 1.0a compatible
Supports x8,x4,x2, and x1 link widths
Auto-detection of number of connected lanes
Selectable operation as root complex or endpoint
Both 32- and 64-bit addressing
256-byte maximum payload size
Virtual channel 0 only
Traffic class 0 only
Full 64-bit decode with 32-bit wide windows
Pin multiplexing for the high-speed I/O interfaces supports one of the following configurations:
8 PCI Express
4 PCI Express and 4 serial RapidIO
Power management
Supports power saving modes: doze, nap, and sleep
Employs dynamic power management, which automatically minimizes power consumption of
blocks when they are idle
System performance monitor
Supports eight 32-bit counters that count the occurrence of selected events
Ability to count up to 512 counter-specific events
Supports 64 reference events that can be counted on any of the eight counters
Supports duration and quantity threshold counting
Burstiness feature that permits counting of burst events with a programmable time between
bursts
Triggering and chaining capability
Ability to generate an interrupt on overflow
System access port
Uses JTAG interface and a TAP controller to access entire system memory map
Supports 32-bit accesses to configuration registers
Supports cache-line burst accesses to main memory
Supports large block (4-Kbyte) uploads and downloads
Supports continuous bit streaming of entire block for fast upload and download
JTAG boundary scan, designed to comply with IEEE Std. 1149.1™
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 10
10 Freescale Semiconductor
Electrical Characteristics
2 Electrical Characteristics
This section provides the AC and DC electrical specifications and thermal characteristics for the device.
This device is currently targeted to these specifications. Some of these specifications are independent of
the I/O cell, but are included for a more complete reference. These are not purely I/O buffer design
specifications.
2.1 Overall DC Electrical Characteristics
This section covers the ratings, conditions, and other characteristics.
2.1.1 Absolute Maximum Ratings
The following table provides the absolute maximum ratings.
Table 1. Absolute Maximum Ratings 1
Characteristic Symbol Max Value Unit Notes
Core supply voltage VDD –0.3 to 1.21 V
PLL supply voltage AVDD –0.3 to 1.21 V
Core power supply for SerDes transceivers SVDD –0.3 to 1.21 V
Pad power supply for SerDes transceivers XVDD –0.3 to 1.21 V
DDR and DDR2 DRAM I/O voltage GVDD –0.3 to 2.75
–0.3 to 1.98
V2
Three-speed Ethernet I/O voltage LVDD (for eTSEC1
and eTSEC2)
–0.3 to 3.63
–0.3 to 2.75
V
TVDD (for eTSEC3
and eTSEC4)
–0.3 to 3.63
–0.3 to 2.75
3
PCI/PCI-X, DUART, system control and power management,
I2C, Ethernet MII management, and JTAG I/O voltage
OVDD –0.3 to 3.63 V
Local bus I/O voltage BVDD –0.3 to 3.63
–0.3 to 2.75
V—
Input voltage DDR/DDR2 DRAM signals MVIN –0.3 to (GVDD + 0.3) V 4
DDR/DDR2 DRAM reference MVREF –0.3 to
(GVDD/2 + 0.3)
V—
Three-speed Ethernet I/O signals LVIN
TVIN
–0.3 to (LVDD + 0.3)
–0.3 to (TVDD + 0.3)
V4
Local bus signals BVIN –0.3 to (BVDD + 0.3)
DUART, SYSCLK, system control and power
management, I2C, Ethernet MII management,
and JTAG signals
OVIN –0.3 to (OVDD + 0.3) V 4
PCI/PCI-X OVIN –0.3 to (OVDD + 0.3) V 4
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 10
Freescale Semiconductor 11
Electrical Characteristics
2.1.2 Recommended Operating Conditions
The following table provides the recommended operating conditions for this device. Note that the values
in this table are the recommended and tested operating conditions. Proper device operation outside these
conditions is not guaranteed.
Storage temperature range TSTG –55 to 150 °C—
Notes:
1. Functional and tested operating conditions are given in Ta bl e 2 . Absolute maximum ratings are stress ratings only, and
functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause
permanent damage to the device.
2. The –0.3 to 2.75 V range is for DDR and –0.3 to 1.98 V range is for DDR2.
3. The 3.63 V maximum is only supported when the port is configured in GMII, MII, RMII, or TBI modes; otherwise the 2.75 V
maximum applies. See Section 8.2, “FIFO, GMII, MII, TBI, RGMII, RMII, and RTBI AC Timing Specifications, for details on
the recommended operating conditions per protocol.
4. (M,L,O)VIN may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2.
Table 2. Recommended Operating Conditions
Characteristic Symbol Recommended
Value Unit Notes
Core supply voltage VDD 1.1 V ± 55 mV V
PLL supply voltage AVDD 1.1 V ± 55 mV V 1
Core power supply for SerDes transceivers SVDD 1.1 V ± 55 mV V
Pad power supply for SerDes transceivers XVDD 1.1 V ± 55 mV V
DDR and DDR2 DRAM I/O voltage GVDD 2.5 V ± 125 mV
1.8 V ± 90 mV
V—
Three-speed Ethernet I/O voltage LVDD 3.3 V ± 165 mV
2.5 V ± 125 mV
V4
TVDD 3.3 V ± 165 mV
2.5 V ± 125 mV
4
PCI/PCI-X, DUART, system control and power management, I2C,
Ethernet MII management, and JTAG I/O voltage
OVDD 3.3 V ± 165 mV V 3
Local bus I/O voltage BVDD 3.3 V ± 165 mV
2.5 V ± 125 mV
V—
Input voltage DDR and DDR2 DRAM signals MVIN GND to GVDD V2
DDR and DDR2 DRAM reference MVREF GND to GVDD/2 V 2
Three-speed Ethernet signals LVIN
TVIN
GND to LVDD
GND to TVDD
V4
Local bus signals BVIN GND to BVDD V—
PCI, DUART, SYSCLK, system control and power
management, I2C, Ethernet MII management, and
JTAG signals
OVIN GND to OVDD V3
Table 1. Absolute Maximum Ratings 1 (continued)
Characteristic Symbol Max Value Unit Notes
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 10
12 Freescale Semiconductor
Electrical Characteristics
The following figure shows the undershoot and overshoot voltages at the interfaces of this device.
Figure 2. Overshoot/Undershoot Voltage for GVDD/OVDD/LVDD/BVDD/TVDD
The core voltage must always be provided at nominal 1.1 V. Voltage to the processor interface I/Os are
provided through separate sets of supply pins and must be provided at the voltages shown in Table 2. The
input voltage threshold scales with respect to the associated I/O supply voltage. OVDD and LVDD based
receivers are simple CMOS I/O circuits and satisfy appropriate LVCMOS type specifications. The DDR
SDRAM interface uses a single-ended differential receiver referenced the externally supplied MVREF
signal (nominally set to GVDD/2) as is appropriate for the SSTL2 electrical signaling standard.
Junction temperature range Tj 0 to 105 °C—
Notes:
1. This voltage is the input to the filter discussed in Section 22.2, “PLL Power Supply Filtering, and not necessarily the voltage
at the AVDD pin, which may be reduced from VDD by the filter.
2. Caution: MVIN must not exceed GVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
3. Caution: OVIN must not exceed OVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
4. Caution: L/TVIN must not exceed L/TVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
Table 2. Recommended Operating Conditions (continued)
Characteristic Symbol Recommended
Value Unit Notes
GND
GND – 0.3 V
GND – 0.7 V Not to Exceed 10%
B/G/L/O/TVDD + 20%
B/G/L/O/TVDD
B/G/L/O/TVDD + 5%
of tCLOCK1
1. tCLOCK refers to the clock period associated with the respective interface:
VIH
VIL
Notes:
2. Note that with the PCI overshoot allowed (as specified above), the device
does not fully comply with the maximum AC ratings and device protection
guideline outlined in the PCI rev. 2.2 standard (section 4.2.2.3).
For I2C and JTAG, tCLOCK references SYSCLK.
For DDR, tCLOCK references MCLK.
For eTSEC, tCLOCK references EC_GTX_CLK125.
For LBIU, tCLOCK references LCLK.
For PCI, tCLOCK references PCIn_CLK or SYSCLK.
For SerDes, tCLOCK references SD_REF_CLK.
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 10
Freescale Semiconductor 13
Electrical Characteristics
2.1.3 Output Driver Characteristics
The following table provides information on the characteristics of the output driver strengths. The values
are preliminary estimates.
2.2 Power Sequencing
The device requires its power rails to be applied in a specific sequence in order to ensure proper device
operation. These requirements are as follows for power-up:
1. VDD, AVDD_n, BVDD, LVDD, OVDD, SVDD, TVDD, XVDD
2. GVDD
All supplies must be at their stable values within 50 ms.
NOTE
Items on the same line have no ordering requirement with respect to one
another. Items on separate lines must be ordered sequentially such that
voltage rails on a previous step must reach 90% of their value before the
voltage rails on the current step reach 10% of theirs.
NOTE
In order to guarantee MCKE low during power-up, the above sequencing for
GVDD is required. If there is no concern about any of the DDR signals being
in an indeterminate state during power-up, then the sequencing for GVDD is
not required.
Table 3. Output Drive Capability
Driver Type
Programmable
Output Impedance
(Ω)
Supply
Voltage Notes
Local bus interface utilities signals 25
25
BVDD = 3.3 V
BVDD = 2.5 V
1
45(default)
45(default)
BVDD = 3.3 V
BVDD = 2.5 V
PCI signals 25 OVDD = 3.3 V 2
45(default)
DDR signal 18
36 (half strength mode)
GVDD = 2.5 V 3
DDR2 signal 18
36 (half strength mode)
GVDD = 1.8 V 3
TSEC/10/100 signals 45 L/TVDD = 2.5/3.3 V
DUART, system control, JTAG 45 OVDD = 3.3 V
I2C 150 OVDD = 3.3 V
Notes:
1. The drive strength of the local bus interface is determined by the configuration of the appropriate bits in PORIMPSCR.
2. The drive strength of the PCI interface is determined by the setting of the PCI_GNT1 signal at reset.
3. The drive strength of the DDR interface in half-strength mode is at Tj = 105°C and at GVDD (min).
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 10
14 Freescale Semiconductor
Electrical Characteristics
NOTE
From a system standpoint, if any of the I/O power supplies ramp prior to the
VDD core supply, the I/Os associated with that I/O supply may drive a logic
one or zero during power-up, and extra current may be drawn by the device.
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 10
Freescale Semiconductor 15
Power Characteristics
3 Power Characteristics
The estimated typical power dissipation for the core complex bus (CCB) versus the core frequency for this
family of PowerQUICC III devices is shown in the following table.
Table 4. Device Power Dissipation
CCB Frequency1Core Frequency SLEEP2Typical-653Typical-1054Maximum5Unit
400 800 2.7 4.6 7.5 8.1 W
1000 2.7 5.0 7.9 8.5 W
1200 2.7 5.4 8.3 8.9
500 1500 11.5 13.6 16.5 18.6 W
533 1333 6.2 7.9 10.8 12.8 W
Notes:
1. CCB frequency is the SoC platform frequency, which corresponds to the DDR data rate.
2. SLEEP is based on VDD = 1.1 V, Tj = 65°C.
3. Typical-65 is based on VDD = 1.1 V, Tj = 65°C, running Dhrystone.
4. Typical-105 is based on VDD = 1.1 V, Tj = 105°C, running Dhrystone.
5. Maximum is based on VDD = 1.1 V, Tj = 105°C, running a smoke test.
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 10
16 Freescale Semiconductor
Input Clocks
4 Input Clocks
This section discusses the timing for the input clocks.
4.1 System Clock Timing
The following table provides the system clock (SYSCLK) AC timing specifications for the device.
4.2 Real Time Clock Timing
The RTC input is sampled by the platform clock (CCB clock). The output of the sampling latch is then
used as an input to the counters of the PIC and the TimeBase unit of the e500. There is no jitter
specification. The minimum pulse width of the RTC signal must be greater than 2x the period of the CCB
clock. That is, minimum clock high time is 2 × tCCB, and minimum clock low time is 2 × tCCB. There is
no minimum RTC frequency; RTC may be grounded if not needed.
Table 5. SYSCLK AC Timing Specifications
At recommended operating conditions (see Table 2) with OVDD = 3.3 V ± 165 mV.
Parameter/Condition Symbol Min Typ Max Unit Notes
SYSCLK frequency fSYSCLK 16 133 MHz 1, 6, 7, 8
SYSCLK cycle time tSYSCLK 7.5 60 ns 6, 7, 8
SYSCLK rise and fall time tKH, tKL 0.6 1.0 1.2 ns 2
SYSCLK duty cycle tKHK/tSYSCLK 40 60 % 3
SYSCLK jitter ±150 ps 4, 5
Notes:
1. Caution: The CCB clock to SYSCLK ratio and e500 core to CCB clock ratio settings must be chosen such that the resulting
SYSCLK frequency, e500 (core) frequency, and CCB clock frequency do not exceed their respective maximum or minimum
operating frequencies.See Section 20.2, “CCB/SYSCLK PLL Ratio, and Section 20.3, “e500 Core PLL Ratio, for ratio
settings.
2. Rise and fall times for SYSCLK are measured at 0.6 and 2.7 V.
3. Timing is guaranteed by design and characterization.
4. This represents the total input jitter—short term and long term—and is guaranteed by design.
5. The SYSCLK driver’s closed loop jitter bandwidth must be <500 kHz at –20 dB. The bandwidth must be set low to allow
cascade-connected PLL-based devices to track SYSCLK drivers with the specified jitter.
6. This parameter has been adjusted slower according to the workaround for device erratum GEN 13.
7. For spread spectrum clocking. Guidelines are + 0% to –1% down spread at modulation rate between 20 and 60 kHz on
SYSCLK.
8. System with operating core frequency less than 1200 MHz must limit SYSCLK frequency to 100 MHz maximum.
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 10
Freescale Semiconductor 17
Input Clocks
4.3 eTSEC Gigabit Reference Clock Timing
The following table provides the eTSEC gigabit reference clocks (EC_GTX_CLK125) AC timing
specifications for the device.
4.4 PCI/PCI-X Reference Clock Timing
When the PCI/PCI-X controller is configured for asynchronous operation, the reference clock for the
PCI/PCI-x controller is not the SYSCLK input, but instead the PCIn_CLK. The following table provides
the PCI/PCI-X reference clock AC timing specifications for the device.
Table 6. EC_GTX_CLK125 AC Timing Specifications
Parameter/Condition Symbol Min Typ Max Unit Notes
EC_GTX_CLK125 frequency fG125 —125—MHz
EC_GTX_CLK125 cycle time tG125 —8—ns
EC_GTX_CLK125 rise and fall time
L/TVDD = 2.5 V
L/TVDD = 3.3 V
tG125R, tG125F ——
0.75
1.0
ns 1
EC_GTX_CLK125 duty cycle
GMII, TBI
1000Base-T for RGMII, RTBI
tG125H/tG125
45
47
55
53
%2, 3
Notes:
1. Rise and fall times for EC_GTX_CLK125 are measured from 0.5 and 2.0 V for L/TVDD = 2.5 V, and from 0.6 and 2.7 V for
L/TVDD = 3.3 V.
2. Timing is guaranteed by design and characterization.
3. EC_GTX_CLK125 is used to generate the GTX clock TSECn_GTX_CLK for the eTSEC transmitter with 2% degradation.
EC_GTX_CLK125 duty cycle can be loosened from 47/53% as long as the PHY device can tolerate the duty cycle generated
by the TSECn_ GTX_CLK. See Section 8.2.6, “RGMII and RTBI AC Timing Specifications,” for duty cycle for 10Base-T and
100Base-T reference clock.
Table 7. PCIn_CLK AC Timing Specifications
At recommended operating conditions (see Table 2) with OVDD = 3.3 V ± 165 mV.
Parameter/Condition Symbol Min Typ Max Unit Notes
PCIn_CLK frequency fPCICLK 16 133 MHz
PCIn_CLK cycle time tPCICLK 7.5 60 ns
PCIn_CLK rise and fall time tPCIKH, tPCIKL 0.6 1.0 2.1 ns 1, 2
PCIn_CLK duty cycle tPCIKHKL/tPCICLK 40 60 % 2
Notes:
1. Rise and fall times for SYSCLK are measured at 0.6 and 2.7 V.
2. Timing is guaranteed by design and characterization.
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 10
18 Freescale Semiconductor
Input Clocks
4.5 Platform to FIFO Restrictions
Note the following FIFO maximum speed restrictions based on platform speed.
For FIFO GMII mode:
FIFO TX/RX clock frequency platform clock frequency/4.2
For example, if the platform frequency is 533 MHz, the FIFO TX/RX clock frequency must be no more
than 127 MHz.
For FIFO encoded mode:
FIFO TX/RX clock frequency platform clock frequency/4.2
For example, if the platform frequency is 533 MHz, the FIFO TX/RX clock frequency must be no more
than 167 MHz.
4.6 Platform Frequency Requirements for PCI-Express and Serial
RapidIO
The CCB clock frequency must be considered for proper operation of the high-speed PCI-Express and
Serial RapidIO interfaces as described below.
For proper PCI Express operation, the CCB clock frequency must be greater than:
527 MHz × (PCI-Express link width)
8
See MPC8548ERM, Rev. 2, PowerQUICC III Integrated Processor Family Reference Manual,
Section 18.1.3.2, “Link Width,” for PCI Express interface width details.
For proper serial RapidIO operation, the CCB clock frequency must be greater than:
2 × (0.80) × (Serial RapidIO interface frequency) × (Serial RapidIO link width)
64
See MPC8548ERM, Rev. 2, PowerQUICC III Integrated Processor Family Reference Manual,
Section 17.4, “1x/4x LP-Serial Signal Descriptions,” for serial RapidIO interface width and frequency
details.
4.7 Other Input Clocks
For information on the input clocks of other functional blocks of the platform see the specific section of
this document.
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 10
Freescale Semiconductor 19
RESET Initialization
5 RESET Initialization
This section describes the AC electrical specifications for the RESET initialization timing requirements of
the device. The following table provides the RESET initialization AC timing specifications for the DDR
SDRAM component(s).
The following table provides the PLL lock times.
5.1 Power-On Ramp Rate
This section describes the AC electrical specifications for the power-on ramp rate requirements.
Controlling the maximum power-on ramp rate is required to avoid falsely triggering the ESD circuitry. The
following table provides the power supply ramp rate specifications.
Table 8. RESET Initialization Timing Specifications
Parameter/Condition Min Max Unit Notes
Required assertion time of HRESET 100 μs—
Minimum assertion time for SRESET 3 SYSCLKs 1
PLL input setup time with stable SYSCLK before HRESET negation 100 μs—
Input setup time for POR configs (other than PLL config) with respect to
negation of HRESET
4 SYSCLKs 1
Input hold time for all POR configs (including PLL config) with respect to
negation of HRESET
2 SYSCLKs 1
Maximum valid-to-high impedance time for actively driven POR configs with
respect to negation of HRESET
5 SYSCLKs 1
Note:
1. SYSCLK is the primary clock input for the device.
Table 9. PLL Lock Times
Parameter/Condition Min Max Unit
Core and platform PLL lock times 100 μs
Local bus PLL lock time 50 μs
PCI/PCI-X bus PLL lock time 50 μs
Table 10. Power Supply Ramp Rate
Parameter Min Max Unit Notes
Required ramp rate for MVREF 3500 V/s 1
Required ramp rate for VDD 4000 V/s 1, 2
Note:
1. Maximum ramp rate from 200 to 500 mV is most critical as this range may falsely trigger the ESD circuitry.
2. VDD itself is not vulnerable to false ESD triggering; however, as per Section 22.2, “PLL Power Supply Filtering, the
recommended AVDD_CORE, AVDD_PLAT, AVDD_LBIU, AVDD_PCI1 and AVDD_PCI2 filters are all connected to VDD.
Their ramp rates must be equal to or less than the VDD ramp rate.
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 10
20 Freescale Semiconductor
DDR and DDR2 SDRAM
6 DDR and DDR2 SDRAM
This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the
device. Note that GVDD(typ) = 2.5 V for DDR SDRAM, and GVDD(typ) = 1.8 V for DDR2 SDRAM.
6.1 DDR SDRAM DC Electrical Characteristics
The following table provides the recommended operating conditions for the DDR2 SDRAM controller of
the device when GVDD(typ) = 1.8 V.
This table provides the DDR2 I/O capacitance when GVDD(typ) = 1.8 V.
Table 11. DDR2 SDRAM DC Electrical Characteristics for GVDD(typ) = 1.8 V
Parameter/Condition Symbol Min Max Unit Notes
I/O supply voltage GVDD 1.71 1.89 V 1
I/O reference voltage MVREF 0.49 ×GVDD 0.51 ×GVDD V2
I/O termination voltage VTT MVREF –0.04 MV
REF + 0.04 V 3
Input high voltage VIH MVREF +0.125 GV
DD +0.3 V
Input low voltage VIL –0.3 MVREF –0.125 V
Output leakage current IOZ –50 50 μA4
Output high current (VOUT = 1.420 V) IOH –13.4 mA
Output low current (VOUT = 0.280 V) IOL 13.4 mA
Notes:
1. GVDD is expected to be within 50 mV of the DRAM VDD at all times.
2. MVREF is expected to be equal to 0.5 × GVDD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak
noise on MVREF may not exceed ±2% of the DC value.
3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be
equal to MVREF. This rail must track variations in the DC level of MVREF.
4. Output leakage is measured with all outputs disabled, 0 V VOUT GVDD.
Table 12. DDR2 SDRAM Capacitance for GVDD(typ)=1.8 V
Parameter/Condition Symbol Min Max Unit Notes
Input/output capacitance: DQ, DQS, DQS CIO 68pF1
Delta input/output capacitance: DQ, DQS, DQS CDIO —0.5pF1
Note:
1. This parameter is sampled. GVDD = 1.8 V ± 0.090 V, f = 1 MHz, TA = 25°C, VOUT = GVDD/2, VOUT (peak-to-peak) = 0.2 V.
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 10
Freescale Semiconductor 21
DDR and DDR2 SDRAM
Table 13 provides the recommended operating conditions for the DDR SDRAM controller when
GVDD(typ) = 2.5 V.
Table 14 provides the DDR I/O capacitance when GVDD(typ) = 2.5 V.
This table provides the current draw characteristics for MVREF.
Table 13. DDR SDRAM DC Electrical Characteristics for GVDD(typ) = 2.5 V
Parameter/Condition Symbol Min Max Unit Notes
I/O supply voltage GVDD 2.375 2.625 V 1
I/O reference voltage MVREF 0.49 × GVDD 0.51 × GVDD V2
I/O termination voltage VTT MVREF – 0.04 MVREF + 0.04 V 3
Input high voltage VIH MVREF + 0.15 GVDD + 0.3 V
Input low voltage VIL –0.3 MVREF – 0.15 V
Output leakage current IOZ –50 50 μA4
Output high current (VOUT = 1.95 V) IOH –16.2 mA
Output low current (VOUT = 0.35 V) IOL 16.2 mA
Notes:
1. GVDD is expected to be within 50 mV of the DRAM VDD at all times.
2. MVREF is expected to be equal to 0.5 × GVDD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak
noise on MVREF may not exceed ±2% of the DC value.
3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be
equal to MVREF. This rail must track variations in the DC level of MVREF.
4. Output leakage is measured with all outputs disabled, 0 V VOUT GVDD.
Table 14. DDR SDRAM Capacitance for GVDD(typ) = 2.5 V
Parameter/Condition Symbol Min Max Unit Notes
Input/output capacitance: DQ, DQS CIO 68pF1
Delta input/output capacitance: DQ, DQS CDIO —0.5pF1
Note:
1. This parameter is sampled. GVDD = 2.5 V ± 0.125 V, f = 1 MHz, TA = 25°C, VOUT = GVDD/2, VOUT (peak-to-peak) = 0.2 V.
Table 15. Current Draw Characteristics for MVREF
Parameter/Condition Symbol Min Max Unit Notes
Current draw for MVREF IMVREF —500 μA1
Note:
1. The voltage regulator for MVREF must be able to supply up to 500 μA current.
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 10
22 Freescale Semiconductor
DDR and DDR2 SDRAM
6.2 DDR SDRAM AC Electrical Characteristics
This section provides the AC electrical characteristics for the DDR SDRAM interface. The DDR
controller supports both DDR1 and DDR2 memories. DDR1 is supported with the following AC timings
at data rates of 333 MHz. DDR2 is supported with the following AC timings at data rates down to
333 MHz.
6.2.1 DDR SDRAM Input AC Timing Specifications
This table provides the input AC timing specifications for the DDR SDRAM when GVDD(typ) = 1.8 V.
Table 17 provides the input AC timing specifications for the DDR SDRAM when GVDD(typ) = 2.5 V.
This table provides the input AC timing specifications for the DDR SDRAM interface.
Table 16. DDR2 SDRAM Input AC Timing Specifications for 1.8-V Interface
At recommended operating conditions
Parameter Symbol Min Max Unit
AC input low voltage VIL —MV
REF – 0.25 V
AC input high voltage VIH MVREF + 0.25 V
Table 17. DDR SDRAM Input AC Timing Specifications for 2.5-V Interface
At recommended operating conditions.
Parameter Symbol Min Max Unit
AC input low voltage VIL —MV
REF – 0.31 V
AC input high voltage VIH MVREF + 0.31 V
Table 18. DDR SDRAM Input AC Timing Specifications
At recommended operating conditions.
Parameter Symbol Min Max Unit Notes
Controller Skew for MDQS—MDQ/MECC
533 MHz
400 MHz
333 MHz
tCISKEW
–300
–365
–390
300
365
390
ps 1, 2
Notes:
1. tCISKEW represents the total amount of skew consumed by the controller between MDQS[n] and any corresponding bit that
is captured with MDQS[n]. This must be subtracted from the total timing budget.
2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW. This can be
determined by the following equation: tDISKEW = ± (T/4 – abs(tCISKEW)) where T is the clock period and abs(tCISKEW) is the
absolute value of tCISKEW.
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 10
Freescale Semiconductor 23
DDR and DDR2 SDRAM
6.2.2 DDR SDRAM Output AC Timing Specifications
Table 19. DDR SDRAM Output AC Timing Specifications
At recommended operating conditions.
Parameter Symbol1Min Max Unit Notes
MCK[n] cycle time, MCK[n]/MCK[n] crossing tMCK 3.75 6 ns 2
ADDR/CMD output setup with respect to MCK
533 MHz
400 MHz
333 MHz
tDDKHAS
1.48
1.95
2.40
ns 3
ADDR/CMD output hold with respect to MCK
533 MHz
400 MHz
333 MHz
tDDKHAX
1.48
1.95
2.40
ns 3
MCS[n] output setup with respect to MCK
533 MHz
400 MHz
333 MHz
tDDKHCS
1.48
1.95
2.40
ns 3
MCS[n] output hold with respect to MCK
533 MHz
400 MHz
333 MHz
tDDKHCX
1.48
1.95
2.40
ns 3
MCK to MDQS Skew tDDKHMH –0.6 0.6 ns 4
MDQ/MECC/MDM output setup with respect
to MDQS
533 MHz
400 MHz
333 MHz
tDDKHDS,
tDDKLDS
538
700
900
ps 5
MDQ/MECC/MDM output hold with respect to
MDQS
533 MHz
400 MHz
333 MHz
tDDKHDX,
tDDKLDX
538
700
900
ps 5
MDQS preamble start tDDKHMP –0.5 × tMCK – 0.6 –0.5 × tMCK + 0.6 ns 6
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 10
24 Freescale Semiconductor
DDR and DDR2 SDRAM
NOTE
For the ADDR/CMD setup and hold specifications in Table 19, it is
assumed that the clock control register is set to adjust the memory clocks by
1/2 applied cycle.
Figure 3 shows the DDR SDRAM output timing for the MCK to MDQS skew measurement (tDDKHMH).
Figure 3. Timing Diagram for tDDKHMH
MDQS epilogue end tDDKHME –0.6 0.6 ns 6
Notes:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing
(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,
tDDKHAS symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes from the high (H) state until outputs
(A) are setup (S) or output valid time. Also, tDDKLDX symbolizes DDR timing (DD) for the time tMCK memory clock reference
(K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.
2. All MCK/MCK referenced measurements are made from the crossing of the two signals ±0.1 V.
3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, and MDQ/MECC/MDM/MDQS.
4. Note that tDDKHMH follows the symbol conventions described in note 1. For example, tDDKHMH describes the DDR timing (DD)
from the rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). tDDKHMH can be modified through control
of the MDQS override bits (called WR_DATA_DELAY) in the TIMING_CFG_2 register. This is typically set to the same delay
as in DDR_SDRAM_CLK_CNTL[CLK_ADJUST]. The timing parameters listed in the table assume that these 2 parameters
have been set to the same adjustment value. See the MPC8548E PowerQUICC III Integrated Processor Reference Manual
for a description and understanding of the timing modifications enabled by use of these bits.
5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC
(MECC), or data mask (MDM). The data strobe must be centered inside of the data eye at the pins of the microprocessor.
6. All outputs are referenced to the rising edge of MCK[n] at the pins of the microprocessor. Note that tDDKHMP follows the
symbol conventions described in note 1.
Table 19. DDR SDRAM Output AC Timing Specifications (continued)
At recommended operating conditions.
Parameter Symbol1Min Max Unit Notes
tDDKHMHmax) = 0.6 ns
MDQS
MCK[n]
MCK[n]
tMCK
tDDKHMH(min) = –0.6 ns
MDQS
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 10
Freescale Semiconductor 25
DDR and DDR2 SDRAM
Figure 4 shows the DDR SDRAM output timing diagram.+
Figure 4. DDR SDRAM Output Timing Diagram
Figure 5 provides the AC test load for the DDR bus.
Figure 5. DDR AC Test Load
ADDR/CMD
t
DDKHAS
, t
DDKHCS
t
DDKLDS
t
DDKHDS
MDQ[x]
MDQS[
n]
MCK
[n]
MCK[
n]
t
MCK
t
DDKLDX
t
DDKHDX
D1D0
t
DDKHAX
, t
DDKHCX
Write A0 NOOP
t
DDKHME
t
DDKHMP
t
DDKHMH
Output Z0 = 50 ΩGVDD/2
RL = 50 Ω
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 10
26 Freescale Semiconductor
DUART
7 DUART
This section describes the DC and AC electrical specifications for the DUART interface of the device.
7.1 DUART DC Electrical Characteristics
This table provides the DC electrical characteristics for the DUART interface.
7.2 DUART AC Electrical Specifications
This table provides the AC timing parameters for the DUART interface.
Table 20. DUART DC Electrical Characteristics
Parameter Symbol Min Max Unit
High-level input voltage VIH 2OV
DD + 0.3 V
Low-level input voltage VIL –0.3 0.8 V
Input current (VIN1 = 0 V or VIN = VDD) IIN —±5 μA
High-level output voltage (OVDD = min, IOH = –2 mA) VOH 2.4 V
Low-level output voltage (OVDD = min, IOL = 2 mA) VOL —0.4V
Note:
1. Note that the symbol VIN, in this case, represents the OVIN symbol referenced in Table 1 and Table 2.
Table 21. DUART AC Timing Specifications
Parameter Value Unit Notes
Minimum baud rate fCCB/1,048,576 baud 1, 2
Maximum baud rate fCCB/16 baud 1, 2, 3
Oversample rate 16 1, 4
Notes:
1. Guaranteed by design.
2. fCCB refers to the internal platform clock.
3. Actual attainable baud rate is limited by the latency of interrupt processing.
4. The middle of a start bit is detected as the 8th sampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values are
sampled each 16th sample.
MPC8548E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 10
Freescale Semiconductor 27
Enhanced Three-Speed Ethernet (eTSEC)
8 Enhanced Three-Speed Ethernet (eTSEC)
This section provides the AC and DC electrical characteristics for the enhanced three-speed Ethernet
controller. The electrical characteristics for MDIO and MDC are specified in Section 9, “Ethernet
Management Interface Electrical Characteristics.”
8.1 Enhanced Three-Speed Ethernet Controller (eTSEC)
(10/100/1Gb Mbps)—GMII/MII/TBI/RGMII/RTBI/RMII Electrical
Characteristics
The electrical characteristics specified here apply to all gigabit media independent interface (GMII), media
independent interface (MII), ten-bit interface (TBI), reduced gigabit media independent interface
(RGMII), reduced ten-bit interface (RTBI), and reduced media independent interface (RMII) signals
except management data input/output (MDIO) and management data clock (MDC). The RGMII and RTBI
interfaces are defined for 2.5 V, while the GMII, MII, and TBI interfaces can be operated at 3.3 or 2.5 V.
The GMII, MII, or TBI interface timing is compliant with the IEEE 802.3. The RGMII and RTBI interfaces
follow the Reduced Gigabit Media-Independent Interface (RGMII) Specification Version 1.3
(12/10/2000). The RMII interface follows the RMII Consortium RMII Specification Version 1.2
(3/20/1998). The electrical characteristics for MDIO and MDC are specified in Section 9, “Ethernet
Management Interface Electrical Characteristics.”
8.1.1 eTSEC DC Electrical Characteristics
All GMII, MII, TBI, RGMII, RMII, and RTBI drivers and receivers comply with the DC parametric
attributes specified in Table 22 and Table 23. The RGMII and RTBI signals are based on a 2.5-V CMOS
interface voltage as defined by JEDEC EIA/JESD8-5.
Table 22. GMII, MII, RMII, and TBI DC Electrical Characteristics
Parameter Symbol Min Max Unit Notes
Supply voltage 3.3 V LVDD
TVDD
3.13 3.47 V1, 2
Output high voltage (LV DD/TVDD = min, IOH = 4.0 mA) VOH 2.40 LVDD/TVDD + 0.3 V—
Output low voltage (LVDD/TVDD = min, IOL = 4.0 mA) VOL GND 0.50 V—
Input high voltage VIH 2.0 LV DD/TVDD + 0.3 V—
Input low voltage VIL –0.3 0.90 V
Input high current (VIN = LVDD, VIN = TVDD)I
IH —40μA 1, 2, 3
Input low current (VIN = GND) IIL –600 μA—
Notes:
1. LVDD supports eTSECs 1 and 2.
2. TVDD supports eTSECs 3 and 4.
3. The symbol VIN, in this case, represents the LVIN and TVIN symbols referenced in Tab l e 1 and Ta b l e 2 .