For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
General Description
The MAX1385/MAX1386 set and control bias conditions
for dual RF LDMOS power devices found in cellular
base stations. Each device includes a high-side cur-
rent-sense amplifier with programmable gains of 2, 10,
and 25 to monitor LDMOS drain current over the 20mA
to 5A range. Two external diode-connected transistors
monitor LDMOS temperatures while an internal temper-
ature sensor measures the local die temperature of the
MAX1385/MAX1386. A 12-bit ADC converts the pro-
grammable-gain amplifier (PGA) outputs, external/inter-
nal temperature readings, and two auxiliary inputs.
The two gate-drive channels, each consisting of 8-bit
coarse and 10-bit fine DACs and a gate-drive amplifier,
generate a positive gate voltage to bias the LDMOS
devices. The MAX1385 includes a gate-drive amplifier
with a gain of 2 and the MAX1386 gate-drive amplifier
provides a gain of 4. The 8-bit coarse and 10-bit fine
DACs allow up to 18 bits of resolution. The MAX1385/
MAX1386 include autocalibration features to minimize
error over time, temperature, and supply voltage.
The MAX1385/MAX1386 feature an I2C/SPI™-compatible
serial interface. Both devices operate from a 4.75V to
5.25V analog supply (3.2mA supply current), a 2.7V to
5.25V digital supply (3.1mA supply current), and a 4.75V
to 11.0V gate-drive supply (4.5mA supply current). The
MAX1385/MAX1386 are available in a 48-pin thin QFN
package.
Applications
RF LDMOS Bias Control in Cellular Base Stations
Industrial Process Control
Features
♦Integrated High-Side Drain Current-Sense PGA
with Gain of 2, 10, or 25
♦±0.5% Accuracy for Sense Voltage Between 75mV
and 250mV
♦Full-Scale Sense Voltage of 100mV with Gain of 25
♦Full-Scale Sense Voltage of 250mV with Gain of 10
♦Common-Mode Range of 5V to 30V Drain Voltage
for LDMOS
♦Adjustable Low Noise 0 to 5V, 0 to 10V Output
Gate-Bias Voltage Ranges with ±10mA Gate Drive
♦Fast Clamp to 0V for LDMOS Protection
♦8-Bit DAC Control of Gate-Bias Voltage
♦10-Bit DAC Control of Gate-Bias Offset with
Temperature
♦Internal Die Temperature Measurement
♦External Temperature Measurement by Diode-
Connected Transistor (2N3904)
♦Internal 12-Bit ADC Measurement of Temperature,
Current, and Voltages
♦Selectable I2C-/SPI-Compatible Serial Interface
400kHz/1.7MHz/3.4MHz I2C-Compatible Control
for Settings and Data Measurement
16MHz SPI-Compatible Control for Settings
and Data Measurement
♦Internal 2.5V Reference
♦Three Address Inputs to Control Eight Devices in
I2C Mode
MAX1385/MAX1386
Dual RF LDMOS Bias Controllers
with I2C/SPI Interface
________________________________________________________________
Maxim Integrated Products
1
19-4456; Rev 0; 2/09
EVALUATION KIT
AVAILABLE
Ordering Information/Selector Guide
PART TEMP RANGE PIN-PACKAGE TEMP ERROR (°C) VGATE (V)
MAX1385AETM+** -40°C to +85°C 48 Thin QFN-EP* ±1 5
MAX1385BETM+ -40°C to +85°C 48 Thin QFN-EP* ±2 5
MAX1386AETM+** -40°C to +85°C 48 Thin QFN-EP* ±1 10
MAX1386BETM+** -40°C to +85°C 48 Thin QFN-EP* ±2 10
SPI is a trademark of Motorola, Inc.
*
EP = Exposed pad.
**
Future product—contact factory for availability.
+
Denotes a lead(Pb)-free/RoHS-compliant package.
Pin Configuration and Typical Operating Circuit (I2C Mode)
appear at end of data sheet.
MAX1385/MAX1386
Dual RF LDMOS Bias Controllers
with I2C/SPI Interface
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
AVDD to AGND .........................................................-0.3V to +6V
DVDD to DGND.........................................................-0.3V to +6V
AGND to DGND.....................................................-0.3V to +0.3V
CS1+, CS1-, CS2+, CS2- to GATEGND.................-0.3V to +32V
CS1- to CS1+, CS2- to CS2+ ...................................-6V to +0.3V
GATEVDD to GATEGND .........................................-0.3V to +12V
GATE1, GATE2 to GATEGND...........-0.3V to (GATEVDD + 0.3V)
SAFE1, SAFE2 to GATEGND....................................-0.3V to +6V
GATEGND to AGND..............................................-0.3V to +0.3V
All Other Analog Inputs
to AGND ............-0.3V to the lower of +6V and (AVDD + 0.3V)
Digital Inputs
to DGND ............-0.3V to the lower of +6V and (DVDD + 0.3V)
SDA/DIN, SCL to DGND...........................................-0.3V to +6V
Digital Outputs to DGND .........................-0.3V to (DVDD + 0.3V)
Maximum Continuous Current into Any Pin ........................50mA
Continuous Power Dissipation (TA= +70°C)
48-Pin, 7mm x 7mm, Thin QFN (derate 27.8 mW/°C
above +70°C).............................................................2222mW
Maximum Junction Temperature .....................................+150°C
Operating Temperature Range ...........................-40°C to +85°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
ELECTRICAL CHARACTERISTICS
(GATEVDD = +5.5V for the MAX1385, GATEVDD = +11V for the MAX1386, AVDD = DVDD = +5V, external VREFADC = +2.5V, external VREF-
DAC = +2.5V, CREF = 0.1µF, unless otherwise noted. TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
HIGH-SIDE CURRENT SENSE WITH PGA
Common-Mode Input Voltage
Range VCS+, VCS- 530V
Common-Mode Rejection Ratio CMRR 11V < VCS+ < 30V 90 dB
ICS+ VSENSE < 100mV over the common-mode
range 120 195
Input-Bias Current
ICS- 0.002 ±2
µA
PGA gain = 25 0 100
PGA gain = 10 0 250Full-Scale Sense Voltage Range
VSENSE =
VCS_+ -
VCS_- PGA gain = 2 0 1250
mV
PGA gain = 25 75 100
PGA gain = 10 75 250
Sense Voltage Range for
Accuracy of ±0.5% VSENSE PGA gain = 2 75 1250
mV
PGA gain = 25 20 100
PGA gain = 10 20 250
Sense Voltage Range for
Accuracy of ±2% VSENSE PGA gain = 2 20 1250
mV
Total PGAOUT Voltage Error VSENSE = 75mV ±0.1 ±0.5 %
PGAOUT Capacitive Load CPGAOUT 100 pF
PGAOUT Settling Time tHSCS Settles to within ±0.5% of final value, RS =
50Ω, CGATE = 15pF < 25 µs
Saturation Recovery Time Settles to within ±0.5% accuracy; from
VSENSE = 3 x full scale < 45 µs
AvPGA = 2 0.5
AvPGA = 10 2
Sense-Amplifier Slew Rate
AvPGA = 25 2
V/µs
MAX1385/MAX1386
Dual RF LDMOS Bias Controllers
with I2C/SPI Interface
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(GATEVDD = +5.5V for the MAX1385, GATEVDD = +11V for the MAX1386, AVDD = DVDD = +5V, external VREFADC = +2.5V, external VREF-
DAC = +2.5V, CREF = 0.1µF, unless otherwise noted. TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
AvPGA = 2 900
AvPGA = 10 720
Sense-Amplifier Bandwidth
AvPGA = 25 290
kHz
LDMOS GATE DRIVER (GAIN = 2 and 4)
IGATE = ±1mA 0.75 GATEVDD
- 0.75
Output Gate-Drive Voltage Range VGATE
IGATE = ±10mA 1 GATEVDD
- 1
V
Output Impedance RGATE Measured at DC 0.1 Ω
VGATE Settling Time tGATE Settles to within ±0.5% of final value;
RSERIES = 50Ω, CGATE = 15µF 10 ms
No series resistance, RSERIES = 0Ω010
Output Capacitive Load (Note 1) CGATE RSERIES = 50Ω0 25,000 nF
VGATE Noise RMS noise; 1kHz - 1MHz 250 nV/√Hz
Maximum Power-On Transient ±100 mV
Output Short-Circuit Current Limit ISC 1s, sinking or sourcing ±25 mA
MAX1385, LOCODE = 128, HICODE = 180 ±6 ±20
Total Unadjusted Error
No Autocalibration and Offset
Removal (Note 2)
TUE
MAX1386, LOCODE = 128, HICODE = 180 ±12 ±40
mV
MAX1385, LOCODE = 128, HICODE = 180 ±1 ±8
Total Adjusted Error
With Autocalibration and Offset
Removal
TUE
MAX1386, LOCODE = 128, HICODE = 180 ±2 ±16
mV
MAX1385, VGATE > 1V ±15
Drift MAX1386, VGATE > 1V ±30 µV/°C
Clamp to Zero Delay 1µs
Output Safe Switch On-
Resistance ROPSW GATE_ clamped to AGND (Note 3) 500 Ω
MAX1385 300
Amplifier Bandwidth MAX1386 150 kHz
Amplifier Slew Rate 0.375 V/µs
MONITOR ADC DC ACCURACY
Resolution NADC 12 Bits
Differential Nonlinearity DNLADC ±0.5 ±2 LSB
Integral Nonlinearity INLADC (Note 4) ±0.6 ±2 LSB
Offset Error ±2 ±4 LSB
Gain Error (Note 5) ±2 ±4 LSB
Gain Temperature Coefficient ±0.4 ppm/°C
Offset Temperature Coefficient ±0.4 ppm/°C
MAX1385/MAX1386
Dual RF LDMOS Bias Controllers
with I2C/SPI Interface
4 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(GATEVDD = +5.5V for the MAX1385, GATEVDD = +11V for the MAX1386, AVDD = DVDD = +5V, external VREFADC = +2.5V, external VREF-
DAC = +2.5V, CREF = 0.1µF, unless otherwise noted. TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Channel-to-Channel Offset
Matching ±0.1 LSB
Channel-to-Channel Gain
Matching ±0.1 LSB
MONITOR ADC DYNAMIC ACCURACY (1kHz sine-wave input, 2.5VP-P, up to 94.4ksps)
Signal-to-Noise Plus Distortion SINAD 70 dB
Total Harmonic Distortion THD Up to the 5th harmonic -82 dB
Spurious-Free Dynamic Range SFDR 86 dB
Intermodulation Distortion IMD fIN1 = 0.99kHz, fIN2 = 1.02kHz 76 dB
Full-Power Bandwidth -3dB point 10 MHz
Full-Linear Bandwidth S/(N + D) > 68dB 100 kHz
MONITOR ADC CONVERSION RATE
External reference 0.8
Power-Up Time tPU Internal reference 70 µs
Conversion Time tCONV Internally clocked 7.5 10 µs
MONITOR ADC ANALOG INPUT (ADCIN1, ADCIN2)
Input Range VADCIN Relative to AGND (Note 6) 0 VREF V
Input Leakage Current VIN = 0V and VIN = AVDD ±0.01 ±1 µA
Input Capacitance CADCIN 34 pF
TEMPERATURE MEASUREMENTS
MAX1385A/MAX1386A, TA = +25°C ±0.25
MAX1385A/MAX1386A, TA = TMIN to TMAX -1.0 ±0.25 +1.0
MAX1385B/MAX1386B, TA = +25°C ±0.25
Internal Sensor Measurement
Error (Note 1)
MAX1385B/MAX1386B, TA = TMIN to TMAX -2.0 ±0.35 +2.0
°C
TA = +25°C ±0.4
External Sensor Measurement
Error (Notes 1, 7) TA = TMIN to TMAX -3 ±0.75 +3 °C
Temperature Resolution 1/8 °C/LSB
External Diode Drive 2.8 85 µA
Drive Current Ratio (Note 8) 16.5
INTERNAL REFERENCE
VREFADC TA = +25°C 2.494 2.500 2.506
REFADC/REFDAC Output Voltage VREFDAC TA = +25°C 2.494 2.500 2.506 V
REFADC/REFDAC Output
Temperature Coefficient
TCREFADC,
TCREFDAC ±14 ppm/°C
REFADC/REFDAC Output
Impedance 6.5 kΩ
MAX1385/MAX1386
Dual RF LDMOS Bias Controllers
with I2C/SPI Interface
_______________________________________________________________________________________ 5
ELECTRICAL CHARACTERISTICS (continued)
(GATEVDD = +5.5V for the MAX1385, GATEVDD = +11V for the MAX1386, AVDD = DVDD = +5V, external VREFADC = +2.5V, external VREF-
DAC = +2.5V, CREF = 0.1µF, unless otherwise noted. TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Capacitive Bypass at REF 270 nF
Power-Supply Rejection Ratio PSRR AVDD = +5V ±5% 70 dB
EXTERNAL REFERENCE
REFADC Input Voltage Range VREFADC Limited code test 1.0 AVDD V
VREF = 2.5V, fSAMPLE = 174ksps 60 80
REFADC Input Current IREFADC Acquisition/between conversions ±0.01 ±1 µA
REFDAC Input Voltage Range VREFDAC (Note 9) 0.5 2.5 V
REFDAC Input Current Static current when no DAC calibration 0.1 µA
GATE-DRIVER COARSE-DAC DC ACCURACY
Resolution NCDAC 8 Bits
Integral Nonlinearity INLCDAC Measured at GATE; fine DAC set at full scale ±0.15 ±1 LSB
Differential Nonlinearity DNLCDAC Guaranteed monotonic ±0.05 ±0.5 LSB
GATE-DRIVER FINE-DAC DC ACCURACY
Resolution NFDAC 10 Bits
Integral Nonlinearity INLFDAC Measured at GATE; coarse DAC set at full
scale ±0.25 ±4 LSB
Differential Nonlinearity DNLFDAC Guaranteed monotonic ±0.1 ±1 LSB
POWER SUPPLIES (Note 10)
Analog Supply Voltage AVDD 4.75 5.25 V
Digital Supply Voltage DVDD 2.7 AVDD
+ 0.3 V
Gate-Drive Supply Voltage VGATEVDD 4.75 11.00 V
Analog Supply Current IAVDD AVDD = 5V 3.2 4 mA
Digital Supply Current IDVDD DVDD = 2.7V to 5.25V 3.1 4.3 mA
GATEVDD Supply Current IGATEVDD 3 4.5 7 mA
IAVDD 0.1 2
IDVDD 0.1 2Shutdown Current (Note 11) IPD
IVDDGATE 0.1 2
µA
MAX1385/MAX1386
Dual RF LDMOS Bias Controllers
with I2C/SPI Interface
6 _______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(GATEVDD = +5.5V for the MAX1385, GATEVDD = +11V for the MAX1386, AVDD = DVDD = +5V, external VREFADC = +2.5V, external VREF-
DAC = +2.5V, CREF = 0.1µF, unless otherwise noted. TA= -40°C to +85°C, unless otherwise noted. Typical values are at TA= +25°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
VIH AND VIL FOR SDA/DIN AND SCL IN I2C OPERATION ONLY
Input High Voltage VIH 0.7 x
DVDD V
Input Low Voltage VIL 0.3 x
DVDD V
Input Hysteresis VHYS 0.1 x
DVDD V
VIH AND VIL FOR OPSAFE1 AND OPSAFE2
Input High Voltage VIH 2.4 V
Input Low Voltage VIL 0.4 V
VIH AND VIL FOR ALL OTHER DIGITAL INPUTS
Input High Voltage VIH 2.2 V
Input Low Voltage VIL 0.7 V
VOH AND VOL FOR A1/DOUT (SPI), SDA/DIN, ALARM
Output Low Voltage VOL ISINK = 3mA 0.4 V
Output High Voltage VOH ISOURCE = 2mA DVDD
- 0.5 V
VOH AND VOL FOR SAFE1, SAFE2, BUSY
Output Low Voltage VOL ISINK = 0.5mA 0.4 V
Output High Voltage VOH ISOURCE = 0.5mA DVDD
- 0.5 V
MAX1385/MAX1386
Dual RF LDMOS Bias Controllers
with I2C/SPI Interface
_______________________________________________________________________________________ 7
I2C SLOW-/FAST-MODE TIMING CHARACTERISTICS (Note 12, see Figure 1)
(GATEVDD = +5.5V for MAX1385, GATEVDD = +11V for MAX1386, AVDD = +5V, DVDD = 2.7V to 5.25V, external VREFADC = +2.5V,
external VREFDAC = +2.5V, CREF = 0.1µF, TA= -40°C to +85°C, unless otherwise noted).
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Serial-Clock Frequency fSCL 0 400 kHz
Bus Free Time Between STOP
and START Condition tBUF 1.3 µs
Hold Time Repeated START
Condition tHD
;
STA After this period, the first clock pulse is
generated 0.6 µs
SCL Pulse-Width Low tLOW 1.3 µs
SCL Pulse-Width High tHIGH 0.6 µs
Setup Time Repeated START
Condition tSU;STA 0.6 µs
Data Hold Time tHD
;
DAT (Note 13) 0 0.9 µs
Data Setup Time tSU
;
DAT 100 ns
Rise Time of Both SDA and SCL
Signals, Receiving tR(Note 14) 0 300 ns
Fall Time of Both SDA and SCL
Signals, Receiving tF(Note 14) 0 300 ns
Fall Time of SDA Signal,
Transmitting tF(Notes 14, 15) 20 +
0.1Cb250 ns
Setup Time for STOP Condition tSU
;
STO 0.6 µs
Capacitive Load for Each Bus
Line Cb400 pF
Pulse Width of Spikes
Suppressed by the Input Filter tSP (Note 16) 0 50 ns
MAX1385/MAX1386
Dual RF LDMOS Bias Controllers
with I2C/SPI Interface
8 _______________________________________________________________________________________
I2C HIGH-SPEED-MODE TIMING CHARACTERISTICS (Note 12, see Figure 2)
(GATEVDD = +5.5V for MAX1385, GATEVDD = +11V for MAX1386, AVDD = +5V, DVDD = 2.7V to 5.25V, external VREFADC = +2.5V,
external VREFDAC = +2.5V, CREF = 0.1µF, TA= -40°C to +85°C, unless otherwise noted).
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Serial-Clock Frequency fSCL 0 3.4 MHz
Setup Time Repeated START
Condition tSU;STA 160 ns
Hold Time Repeated START
Condition tHD;STA 160 ns
SCL Pulse-Width Low tLOW 160 ns
SCL Pulse-Width High tHIGH 60 ns
Data Setup Time tSU;DAT 10 ns
Data Hold Time tHD;DAT (Note 17) 0 70 ns
Rise Time of SCL Signal,
Receiving tRCL 10 40 ns
Rise Time of SCL Signal After a
Repeated START Condition and
After an Acknowledge Bit,
Receiving
tRCL1 10 80 ns
Fall Time of SCL Signal,
Receiving tFCL 10 40 ns
Rise Time of SDA Signal,
Receiving tRDA 10 80 ns
Fall Time of SDA Signal,
Transmitting tFDA 10 80 ns
Setup Time for STOP Condition tSU;STO 160 ns
Capacitive Load for Each Bus
Line Cb(Note 18) 100 pF
Pulse Width of Spikes That are
Suppressed by the Input Filter tSP 010ns
MAX1385/MAX1386
Dual RF LDMOS Bias Controllers
with I2C/SPI Interface
_______________________________________________________________________________________ 9
Note 1: Guaranteed by design.
Note 2: Total unadjusted errors are for the entire gain drive channel including the 8- and 10-bit DACs and the gate driver. They are
all measured at the GATE1 and GATE2 outputs. Offset removal refers to presetting the drain current after a room tempera-
ture calibration by the user. This effectively removes the channel offset.
Note 3: During power-on reset, the output safe switch is closed. The output safe switch opens once both AVDD and DVDD supply
voltages are established.
Note 4: Integral nonlinearity is the deviation of the analog value at any code from its theoretical value after the gain and offset errors
have been removed.
Note 5: Offset nulled.
Note 6: Absolute range for analog inputs is from 0 to AVDD.
Note 7: The MAX1385/MAX1386 and external sensor are at the same temperature. External sensor measurement error is tested with
a diode-connected 2N3904.
Note 8: The drive current ratio is defined as the large drive current divided by the small drive current in a temperature measure-
ment. See the
Temperature Measurements
section for further details.
Note 9: Guaranteed monotonicity. Accuracy might be degraded at lower VREFDAC.
Note 10: Supply current limits are valid only when digital inputs are at DVDD or DGND. Timing specifications are only guaranteed
when inputs are driven rail-to-rail.
Note 11: Shutdown supply currents are typically 0.1µA. Maximum specification is limited by automated test equipment.
Note 12: All timing specifications referred to VIH or VIL levels.
Note 13: A master device must provide a hold time of at least 300ns for the SDA signal (referred to VIL of SCL) to bridge the unde-
fined region of SCL’s falling edge.
Note 14: Cb= total capacitance of one bus line in pF; tRand tFare measured between 0.3 x DVDD and 0.7 x DVDD.
Note 15: For a device operating in an I2C-compatible system.
Note 16: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
Note 17: A device must provide a data hold time to bridge the undefined part between VIH and VIL of the falling edge of the SCL signal.
An input circuit with a threshold as low as possible for the falling edge of the SCL signal minimizes this hold time.
Note 18: Cb = total capacitance of one bus line in pF. For bus loads between 100pF and 400pF, the timing parameters should be
linearly interpolated.
SPI TIMING CHARACTERISTICS (Note 12, See Figure 3)
(GATEVDD = +5.5V for the MAX1385, GATEVDD = +11V for the MAX1386, AVDD = +5V, DVDD = 2.7V to 5.25V, external VREFADC =
+2.5V, external VREFDAC = +2.5V, CREF = 0.1µF, TA= -40°C to +85°C, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SCL Clock Period tCP 62.5 ns
SCL High Time tCH 25 ns
SCL Low Time tCL 25 ns
DIN Setup Time tDS 10 ns
DIN Hold Time tDH 0ns
SCL Fall to DOUT Transition tDO CLOAD = 30pF 20 ns
CSB Fall to DOUT Enable tDV CLOAD = 30pF 40 ns
CSB Rise to DOUT Disable tTR CLOAD = 30pF (Note 12) 100 ns
CSB Rise or Fall to SCL Rise tCSS 25 ns
CSB Pulse-Width High tCSW 100 ns
Last Clock Rise to CSB Rise tCSH 50 ns
MAX1385/MAX1386
Dual RF LDMOS Bias Controllers
with I2C/SPI Interface
10 ______________________________________________________________________________________
SDA
SCL
tBUF
tSU;STO
tSP
tHD;STA
tSU;STA
tF
tHIGH
tSU;DAT
tHD;DAT
tLOW
tHD;STA
SSrPS
tR
tFtr
Figure 1. I
2
C Slow-/Fast-Mode Timing Diagram
tHD;DAT
SDA
SCL
tSU;STO
tRCL1
tRCL
tHIGH
tFDA
Sr
Sr
tLOW
tLOW
tHIGH
tFCL
tRDA P
tSU;STA tHD;STA
tSU;DAT
tRCL1
Figure 2. I
2
C High-Speed-Mode Timing Diagram
tCSH
tCP
tCH
tCSS
tDS
SCL
tCSW
tDH
CSB
D23
DIN D22 D1 D0
DOUT
tDV
tCL
tDO tTR
tCSS
D0D1
Figure 3. SPI Timing Diagram
MAX1385/MAX1386
Dual RF LDMOS Bias Controllers
with I2C/SPI Interface
______________________________________________________________________________________ 11
Typical Operating Characteristics
(GATEVDD = +5.5V for the MAX1385, GATEVDD = +11V for the MAX1386, AVDD = DVDD = +5V, external VREFADC = +2.5V, external
VREFDAC = +2.5V, CREF = 0.1µF, TA= +25°C, unless otherwise noted.)
3.0
3.3
3.2
3.1
3.4
3.5
3.6
3.7
3.8
3.9
4.0
4.7 4.94.8 5.0 5.1 5.2 5.3
AVDD SUPPLY CURRENT
vs. AVDD VOLTAGE
MAX1385/86 toc01
AVDD (V)
IAVDD (mA)
AvPGA = 2
CMV = 12V
VSENSE = 100mV
TA = +85°C
TA = +25°C
TA = -40°C
DVDD SUPPLY CURRENT vs. DVDD VOLTAGE
MAX1385/86 toc02
DVDD (V)
IDVDD (mA)
5.24.74.23.73.2
1.25
1.50
1.75
2.00
2.25
2.50
2.75
3.00
3.25
3.50
3.75
4.00
1.00
2.7
AvPGA = 2
CMV = 12V
VSENSE = 100mV TA = +25°C
TA = +85°C
TA = -40°C
GATEVDD SUPPLY CURRENT
vs. GATEVDD VOLTAGE
MAX1385/86 toc03
GATEVDD (V)
IGATEVDD (mA)
11108 96 75
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
5.0
4.0
412
AvPGA = 2
CMV = 12V
VSENSE = 100mV TA = +85°C
TA = +25°C
TA = -40°C
TOTAL PGAOUT_ ERROR
vs. TEMPERATURE
MAX1385/86 toc04
TEMPERATURE (°C)
PGAOUT_ ERROR (%)
806535 50-10 5 20-25
-0.125
-0.100
-0.075
-0.050
-0.025
0
0.025
0.050
0.075
0.100
0.125
0.150
-0.150
-40
AvPGA = 2
CMV = 12V
VSENSE = 100mV
ACQUISITION
TRACKING
TOTAL PGAOUT_ ERROR vs. VSENSE
MAX1385/86 toc05
VSENSE (mV)
PGAOUT_ ERROR (%)
1000750500250
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
0
0 1250
AvPGA = 2
CMV = 12V
TOTAL PGAOUT_ ERROR vs. VSENSE
MAX1385/86 toc06
VSENSE (mV)
PGAOUT_ ERROR (%)
80604020
-3.5
-3.0
-2.5
-2.0
-1.5
-1.0
-0.5
0
0.5
-4.0
0 100
AvPGA = 25
CMV = 12V
TOTAL PGAOUT_ ERROR
vs. COMMON-MODE VOLTAGE
MAX1385/86 toc07
COMMON-MODE VOLTAGE (V)
PGAOUT_ ERROR (%)
3025201510
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0.10
0
5
AvPGA = 2
VSENSE = 100mV
PGAOUT_ OFFSET VOLTAGE
vs. TEMPERATURE
MAX1385/86 toc08
TEMPERATURE (°C)
OFFSET VOLTAGE (μV)
806535 50-10 5 20-25
-350
-300
-250
-200
-150
-100
-50
0
50
100
150
200
-400
-40
AvPGA = 2
CMV = 12V
VSENSE = 100mV
ACQUISITION
TRACKING
VSENSE TRANSIENT RESPONSE
MAX1385/86 toc09
100mV/div
1V/div
PGAOUT_
VSENSE
10μs/div
MAX1385/MAX1386
Dual RF LDMOS Bias Controllers
with I2C/SPI Interface
12 ______________________________________________________________________________________
Typical Operating Characteristics (continued)
(GATEVDD = +5.5V for the MAX1385, GATEVDD = +11V for the MAX1386, AVDD = DVDD = +5V, external VREFADC = +2.5V, external
VREFDAC = +2.5V, CREF = 0.1µF, TA= +25°C, unless otherwise noted.)
PGAOUT_ 0mV TO 250mV
VSENSE TRANSIENT RESPONSE
MAX1385/86 toc10
VSENSE
PGAOUT_
10µs/div
100mV/div
1V/div
PGAOUT_ PEDESTAL ERROR
DURING CALIBRATION
MAX1385/86 toc11
BUSY
PGAOUT_
20µs/div
2V/div
10mV/div
GATE_ OFFSET COMPENSATED
ERROR vs. TEMPERATURE
MAX1385/86 toc12
TEMPERATURE (°C)
ERROR VOLTAGE (mV)
8065-25 -10 5 3520 50
-7
-6
-5
-4
-3
-2
-1
0
-8
-40
L_ERROR, AUTOCALIBRATION
H_ERROR, AUTOCALIBRATION
L_ERROR, NO AUTOCALIBRATION
H_ERROR, NO AUTOCALIBRATION
VGATE vs. POWER-ON TIME
MAX1385/86 toc13
VGATE_
400µs/div
50mV/div
CHARGE CURRENT vs. VGATE
MAX1385/86 toc15
VGATE_
1ms/div
IGATE_
2V/div
20mA/div
GATE_ SETTLING TIME
vs. LOAD CAPACITANCE
MAX1385/86 toc14
LOAD CAPACITANCE (µF)
SETTLING TIME (ms)
101
2
4
6
8
10
12
14
16
0
0.1 100
RSERIES = 50Ω
GATE_ VOLTAGE SWING
vs. LOAD RESISTANCE
MAX1385/86 toc16
LOAD RESISTANCE (Ω)
GATE_ VOLTAGE SWING (V)
10,0001000100
1
2
3
4
5
6
7
8
9
10
0
10 100,000
GLITCH ENERGY
MAX1385/86 toc17
1µs/div
10mV/div
MAX1385/MAX1386
Dual RF LDMOS Bias Controllers
with I2C/SPI Interface
______________________________________________________________________________________ 13
-1.0
-0.4
-0.6
-0.8
-0.2
0
0.2
0.4
0.6
0.8
1.0
0400200 600 800 1000
INTEGRAL NONLINEARITY vs. DIGITAL
INPUT CODE (10-BIT FINE DAC)
MAX1385/86 toc19
DIGITAL INPUT CODE
INL (LSB)
-1.0
-0.4
-0.6
-0.8
-0.2
0
0.2
0.4
0.6
0.8
1.0
DIFFERENTIAL NONLINEARITY
vs. DIGITAL INPUT CODE (8-BIT DAC)
MAX1385/86 toc20
DIGITAL INPUT CODE
DNL (LSB)
0 10050 150 200 250
-1.0
-0.4
-0.6
-0.8
-0.2
0
0.2
0.4
0.6
0.8
1.0
DIFFERENTIAL NONLINEARITY
vs. DIGITAL INPUT CODE (10-BIT FINE DAC)
MAX1385/86 toc21
DIGITAL INPUT CODE
DNL (LSB)
0 400200 600 800 1000 -1.0
-0.4
-0.6
-0.8
-0.2
0
0.2
0.4
0.6
0.8
1.0
0 20001000 3000 4000
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE (ADC)
MAX1385/86 toc22
DIGITAL OUTPUT CODE
INL (LSB)
-1.0
-0.4
-0.6
-0.8
-0.2
0
0.2
0.4
0.6
0.8
1.0
0 20001000 3000 4000
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE (ADC)
MAX1385/86 toc23
DIGITAL OUTPUT CODE
DNL (LSB)
-160
-140
-120
-100
-80
-60
-40
-20
0
0 5 10 15 20 25
FFT PLOT
MAX1385/86 toc24
FREQUENCY (kHz)
AMPLITUDE (dB)
fIN = 303Hz
fSAMPLE = 49.15kHz
Typical Operating Characteristics (continued)
(GATEVDD = +5.5V for the MAX1385, GATEVDD = +11V for the MAX1386, AVDD = DVDD = +5V, external VREFADC = +2.5V, external
VREFDAC = +2.5V, CREF = 0.1µF, TA= +25°C, unless otherwise noted.)
-1.0
-0.4
-0.6
-0.8
-0.2
0
0.2
0.4
0.6
0.8
1.0
0 10050 150 200 250
INTEGRAL NONLINEARITY vs. DIGITAL
INPUT CODE (8-BIT COARSE DAC)
MAX1385/86 toc18
DIGITAL INPUT CODE
INL (LSB)
MAX1385/MAX1386
Dual RF LDMOS Bias Controllers
with I2C/SPI Interface
14 ______________________________________________________________________________________
-0.05
-0.03
-0.04
-0.01
-0.02
0.01
0
0.02
0.04
0.03
0.05
-40 -10 5 20-25 35 50 65 80
ADC GAIN ERROR vs. TEMPERATURE
MAX1385/86 toc28
TEMPERATURE (°C)
GAIN ERROR (%)
AVDD = 5V
-1.4
-1.0
-1.2
-0.6
-0.8
-0.2
-0.4
0
-40 0 20-20 40 60 80
INTERNAL TEMPERATURE SENSOR
ERROR vs. TEMPERATURE
MAX1385/86 toc29
TEMPERATURE (°C)
ERROR (°C)
-1.0
-0.4
-0.6
-0.8
0
-0.2
0.8
0.6
0.4
0.2
1.0
MAX1385/86 toc30
ERROR (°C)
EXTERNAL TEMPERATURE SENSOR
ERROR vs. TEMPERATURE
-40 0 20-20 40 60 80
TEMPERATURE (°C)
-0.100
-0.075
-0.050
-0.025
0
0.025
0.050
0.075
0.100
4.75 4.85 4.95 5.05 5.15 5.25
ADC OFFSET ERROR vs. AVDD VOLTAGE
MAX1385/86 toc27
AVDD (V)
OFFSET ERROR (%)
Typical Operating Characteristics (continued)
(GATEVDD = +5.5V for the MAX1385, GATEVDD = +11V for the MAX1386, AVDD = DVDD = +5V, external VREFADC = +2.5V, external
VREFDAC = +2.5V, CREF = 0.1µF, TA= +25°C, unless otherwise noted.)
2.484
2.489
2.494
2.499
2.504
2.509
-40 -10-25 5 20 35 50 65 80
INTERNAL REFERENCE
vs. TEMPERATURE
MAX1385/86 toc25
TEMPERATURE (°C)
REFERENCE VOLTAGE (V)
AVDD = 5V
-0.100
-0.050
-0.075
0.025
0
-0.025
0.075
0.050
0.100
-40 5 20-25 -10 35 50 65 80
ADC OFFSET ERROR vs. TEMPERATURE
MAX1385/86 toc26
TEMPERATURE (°C)
OFFSET ERROR (%)
AVDD = 5V
MAX1385/MAX1386
Dual RF LDMOS Bias Controllers
with I2C/SPI Interface
______________________________________________________________________________________ 15
Pin Description
PIN NAME FUNCTION
1 DGND Digital Ground
2 SAFE1 Safe Status Channel 1 Output. Programmable active-high or active-low. SAFE1 asserts when
programmed channel 1 temperature threshold or current threshold has been reached.
3 A0/CSB I2C-Compatible Address 0/ SPI-Compatible Chip Select. See the Digital Serial Interface section. In
SPI mode, drive A0/CSB low to select the device.
4CNVST Active-Low Conversion-Start Input. Drive CNVST low to start a conversion (clock modes 01 and 11).
Connect CNVST to DVDD when initiating conversions through the serial interface (clock mode 00).
5 SEL Mode Select. Connect SEL to DGND to select I2C mode. Connect SEL to DVDD to select SPI mode.
6 ALARM
Alarm Output. Program ALARM for comparator or interrupt output modes (see the Alarm Modes
section). Program ALARM to assert on any combination of channel temperature or current
thresholds.
7 SAFE2 Safe Status Channel 2 Output. Programmable active-high or active-low. SAFE2 asserts when
programmed channel 2 temperature threshold or current threshold has been reached.
8, 19, 25, 28,
35–39, 42, 46 N.C. No Connection. Not internally connected.
9 REFDAC DAC Reference Input/Output
10 REFADC ADC Reference Input/Output
11 DXP1 Diode Positive Input 1. Connect to anode of temperature diode or the base and collector of an npn
transistor.
12 DXN1 Diode Negative Input 1. Connect to cathode of temperature diode or the emitter of an npn transistor.
13 DXP2 Diode Positive Input 2. Connect to anode of temperature diode or the base and collector of an npn
transistor.
14 DXN2 Diode Negative Input 2. Connect to cathode of temperature diode or the emitter of an npn transistor.
15 ADCIN1 ADC Input 1
16 ADCIN2 ADC Input 2
17 PGAOUT2 Programmable-Gain Amplifier Output 2
18 AVDD Analog Power-Supply Input
20, 21, 22 AGND Analog Ground
MAX1385/MAX1386
Dual RF LDMOS Bias Controllers
with I2C/SPI Interface
16 ______________________________________________________________________________________
Pin Description (continued)
PIN NAME FUNCTION
23 GATEGND Gate-Drive Amplifier Ground
24 GATEVDD Gate-Drive Amplifier Supply Input
26 OPSAFE2 Operating Safe Channel 2 Input. Drive OPSAFE2 high to clamp GATE2 to AGND.
27 CS2+ Current-Sense Positive Input 2. CS2+ is the external sense resistor connection to the LDMOS 2
supply.
29 CS2- Current-Sense Negative Input 2. CS2- is the external sense resistor connection to the LDMOS 2
drain.
30 GATE2 Channel 2 Gate-Drive Amplifier Output
31 GATE1 Channel 1 Gate-Drive Amplifier Output
32 CS1- Current-Sense Negative Input 1. CS1- is the external sense resistor connection to the LDMOS 1
drain.
33 CS1+ Current-Sense Positive Input 1. CS1+ is the external sense resistor connection to the LDMOS 1
supply.
34 OPSAFE1 Operating Safe Channel 1 Input. Drive OPSAFE1 high to clamp GATE1 to AGND.
40 PGAOUT1 Programmable-Gain Amplifier Output 1
I2C-Compatible Address 2. See the Digital Serial Interface section.
41 A2/N.C. No Connection. Leave unconnected in SPI mode.
43 SCL Digital Serial Clock Input
I2C-Compatible Serial Data Input/Output
44 SDA/DIN SPI-Compatible Serial Data Input
I2C-Compatible Address 1. See the Digital Serial Interface section.
45 A1/DOUT SPI-Compatible Serial Data Output
47 BUSY Device Busy Output. See the BUSY Output section
48 DVDD Digital Supply Input
— EP Exposed Pad. Connect to AGND. Internally connected to analog ground.
MAX1385/MAX1386
Dual RF LDMOS Bias Controllers
with I2C/SPI Interface
______________________________________________________________________________________ 17
V
REFDAC
V
REFDAC
SDA/DIN
SCL
PGA REGISTERS
10-BIT DAC
PGA1
PGAOUT1
DRV
PGAOUT2
CS1+
CS1-
GATE1
OPSAFE2
GATE2
CS2-
CS2+
OPSAFE1
12-BIT ADC
WITH T/H
TEMP
SENSOR
CONVERSION AND
SCAN OSCILLATOR
AND CONTROL
ADCIN0
ADCIN1
MUX
DXP1
DXN1
DXP2
DXN2
PGAOUT2
PGAOUT1
REGISTER
SECTION
DVDD
DGND
GATEVDD
GATEGND
AGND
PGA2
8-BIT HIGH CODE
EXTERNAL
TEMP
PROCESSING
DRV
CHANNEL 1 DAC
REGISTERS
SAFE1
SAFE2 ALARM
DIGITAL
CURRENT AND
TEMPERATURE
COMPARATORS
SERIAL
INTERFACE
8-BIT LOW CODE
10-BIT FINE
ADJUST CODE
CHANNEL 1 DAC
REGISTERS
8-BIT HIGH CODE
8-BIT LOW CODE
10-BIT FINE
ADJUST CODE
CNVST
V
REFADC
2.5V
REF
10-BIT DAC
REFDAC REFADC
V
REFDAC
FIFO
MEMORY
A0/CSB
A1/DOUT
A2/N.C.
AVDD
MAX1385
MAX1386
Functional Diagram
MAX1385/MAX1386
Dual RF LDMOS Bias Controllers
with I2C/SPI Interface
18 ______________________________________________________________________________________
Detailed Description
The MAX1385/MAX1386 set and control bias conditions
for dual RF LDMOS power devices found in cellular
base stations. Each device includes a high-side cur-
rent-sense amplifier with programmable gains of 2, 10,
and 25 to monitor the LDMOS drain current over the
20mA to 5A range. Two external diode-connected tran-
sistors monitor the LDMOS temperatures while an inter-
nal temperature sensor measures the local die
temperature of the MAX1385/MAX1386. A 12-bit ADC
converts the programmable-gain amplifier (PGA) out-
puts, external/internal temperature readings, and two
auxiliary inputs.
The two gate-drive channels, each consisting of 8-bit
coarse and 10-bit fine DACs and a gate-drive amplifier,
generate a positive gate voltage to bias the LDMOS
devices. The MAX1385 includes a gate-drive amplifier
with a gain of 2 and the MAX1386 gate-drive amplifier
provides a gain of 4. The 8-bit coarse and 10-bit fine
DACs allow up to 18 bits of resolution. The MAX1385/
MAX1386 include autocalibration modes to minimize
error over time, temperature, and supply voltage.
The MAX1385/MAX1386 feature an I2C-/SPI-compatible
serial interface. Both devices operate from a 4.75V to
5.25V analog supply (3.2mA supply current), a 2.7V to
5.25V digital supply (3.1mA supply current), and a 4.75V
to 11.0V gate-drive supply (4.5mA supply current).
Power-On Reset
On power-up, the MAX1385/MAX1386 are in full power-
down mode (see the
SSHUT (Write)
section). To change
to normal power mode, write two commands to the
Software Shutdown register. The first command sets
FULLPD to 0 (other bits in the Software Shutdown register
are ignored). A second command is needed to activate
any internal blocks. The recommended sequence of com-
mands to ensure reliable startup following the application
of power, is given in the
Appendix: Recommended
Power-Up Code Sequence
section.
ADC Description
The MAX1385/MAX1386 ADC uses a fully differential
successive approximation register (SAR) conversion
technique and on-chip track-and-hold (T/H) circuitry to
convert temperature and voltage signals into 12-bit dig-
ital results. The analog inputs accept single-ended
input signals. Single-ended signals are converted using
a unipolar transfer function. See the ADC transfer func-
tion of Figure 25 for more information.
The internal ADC block converts the results of the die
temperature, remote diode temperature readings,
PGAOUT1, PGAOUT2, ADCIN1, or ADCIN2 voltages
according to which bits are set in the ADC Conversion
register (see the
ADCCON (Write)
section). The results
of the conversions are written to FIFO memory. The
FIFO holds up to 15 words (each word is 16 bits) with
channel tags to indicate which channel the 12-bit data
comes from. The FIFO indicates an overflow condition
and an underflow condition (read of an empty FIFO) by
the Flag register (see the
RDFLAG (Read)
section) and
channel tags. The FIFO always stores the most recent
conversion results and allows the oldest data to be
overwritten. Read the latest result stored in the FIFO by
sending the appropriate read command byte (see the
FIFO (Read)
section).
Read the data stored in the FIFO through the FIFO
Read register. The
FIFO (Read)
section details which
channel is being read and whether the FIFO has over-
flowed.
Analog-to-Digital Conversion Scheduling
The MAX1385/MAX1386 ADC multiplexer scans select-
ed inputs in the order shown in Table 1. The ADC multi-
plexer skips over the items that are not selected in the
Analog-to-Digital Conversion register. When writing a
conversion command before a conversion is complete,
the pending conversion may be canceled. In addition,
using the serial interface while the ADC is converting
may degrade the performance of the ADC.
ADC Clock Modes
The MAX1385/MAX1386 offer three different conver-
sion/acquisition modes (known as clock modes) selec-
table through the Device Configuration register (see the
DCFIG (Read/Write)
section). Clock Mode 10 is
reserved and cannot be used. For conversion/acquisi-
tion examples and timing diagrams, see the
Applications Information
section.
If the analog-to-digital conversion requires the internal
reference (temperature measurement or voltage mea-
surement with internal reference selected) and the ref-
erence has not been previously forced on, the device
inserts a worst-case delay of 81µs, for the reference to
settle, before commencing the analog-to-digital conver-
sion. The reference remains powered up while there are
pending conversions. If the reference is not forced on,
it automatically powers down at the end of a scan or
when CONCONV in the Analog-to-Digital Conversion
register is set back to 0.
MAX1385/MAX1386
Dual RF LDMOS Bias Controllers
with I2C/SPI Interface
______________________________________________________________________________________ 19
Clock Mode 00
In clock mode 00, power-up, acquisition, conversion,
and power-down are all initiated by writing to the Analog-
to-Digital Conversion register and performed automati-
cally using the internal oscillator. This is the default clock
mode. The ADC sets the BUSY output high, powers up,
scans all requested channels, stores the results in the
FIFO, and then powers down. After the scan is complete,
BUSY is pulled low and the results for all the command-
ed channels are available in the FIFO.
Clock Mode 01
In clock mode 01, power-up, acquisition, conversion,
and power-down are all initiated by setting CNVST low
for at least 40ns. Conversions are performed automati-
cally using the internal oscillator. The ADC sets the
BUSY output high, powers up, scans all requested
channels, stores the results in the FIFO, and then pow-
ers down. After the scan is complete, BUSY is pulled
low and the results for all the commanded channels are
available in the FIFO.
Clock Mode 11
In clock mode 11, conversions are initiated one at a
time through CNVST in the order shown in Table 1 and
performed using the internal oscillator. In this mode, the
acquisition time is controlled by the time CNVST is
brought low. CNVST is resynchronized by the internal
oscillator, which means there is a one-clock-cycle
uncertainty (typically 320ns) in the exact sampling
instant. Different timing parameters apply depending
whether the conversion is temperature, voltage, using
the external reference, or using the internal reference.
For a temperature conversion, set CNVST low for at
least 40ns. The BUSY output goes high and the temper-
ature conversion results are available after an addition-
al 94µs (when BUSY goes low again). Thus, the
worst-case conversion time of the initial temperature
sensor scan (allowing the internal reference to settle) is
175µs. Subsequent temperature scans only take 85µs
worst case as the internal reference and temperature
sensor circuits are already powered.
For a voltage conversion while using an internal or
external reference, set CNVST low for at least 2µs but
less than 6.7µs. The BUSY output goes high and the
conversion results are available after an additional
7.5µs (typ) when BUSY goes low again.
Continuous conversion is not supported in this clock
mode (see the
ADCCON (Write)
section).
Changing Clock Modes During ADC Conversions
If a change is made to the clock mode in the Device
Configuration register while the ADC is already per-
forming a conversion (or series of conversions), the fol-
lowing descriptions show how the MAX1385/MAX1386
respond:
•CKSEL = 00 and is then changed to another value
The ADC completes the already triggered series of
conversions and then goes idle. The BUSY output
remains high until the conversions are completed.
The MAX1385/MAX1386 then respond in accor-
dance with the new CKSEL mode.
•CKSEL = 01 and is then changed to another value
If waiting for the initial external trigger, the
MAX1385/MAX1386 immediately exit clock mode
01, power down the ADC, and go idle. The BUSY
output stays low and waits for the external trigger. If
a conversion sequence has started, the ADC com-
pletes the requested conversions and then goes
idle. The BUSY output remains high until the conver-
sions are completed. The MAX1385/MAX1386 then
respond in accordance with the new CKSEL mode.
•CKSEL = 11 and is then changed to another value
If waiting for an external trigger, the MAX1385/
MAX1386 immediately exit clock mode 11, power
down the ADC, and go idle. The BUSY output stays
low and waits for the external trigger.
ORDER OF SCAN DESCRIPTION OF CONVERSION
1 Internal device temperature
2 External diode 1 temperature
3 PGAOUT1 for current sense
4 ADCIN1
5 External diode 2 temperature
6 PGAOUT2 for current sense
7 ADCIN2
Table 1. Order of ADC Conversion Scan
MAX1385/MAX1386
Dual RF LDMOS Bias Controllers
with I2C/SPI Interface
20 ______________________________________________________________________________________
CONTROL LOGIC
CAPACITIVE DAC
ADCIN_
AGND
CONTROL LOGIC
ADCIN_
AGND TRACK MODE
HOLD/CONVERSION MODE
CAPACITIVE DAC
Figure 4. Equivalent ADC Input Circuit
Analog Input Track and Hold
The equivalent circuit (Figure 4) shows the
MAX1385/MAX1386 ADC input architecture. In track
mode, a positive input capacitor is connected to
ADCIN_ and a negative input capacitor is connected to
AGND. After the T/H enters hold mode, the difference
between the sampled positive and negative input volt-
ages is converted. The input capacitance charging rate
determines the time required for the T/H to acquire an
input signal. If the input signal’s source impedance is
high, the required acquisition time lengthens.
Any source impedance below 300Ωdoes not signifi-
cantly affect the ADC’s AC performance. A high-imped-
ance source can be accommodated either by lengthen-
ing tACQ or by placing a 1µF capacitor between the
positive input and AGND. The combination of the ana-
log input source impedance and the capacitance at the
analog input creates an RC filter that limits the analog-
input bandwidth.
Analog-Input Bandwidth
The ADC’s input-tracking circuitry has a 10MHz band-
width to digitize high-speed transient events. Anti-alias
prefiltering of the input signals is necessary to avoid
high-frequency signals aliasing into the frequency band
of interest.
MAX1385/MAX1386
Dual RF LDMOS Bias Controllers
with I2C/SPI Interface
______________________________________________________________________________________ 21
Analog-Input Protection
Internal ESD protection diodes clamp all analog inputs
to AVDD and AGND, allowing the inputs to swing from
AGND - 0.3V to AVDD + 0.3V without damage. If an
analog input voltage exceeds the supplies, limit the
input current to 2mA.
DAC Description
The MAX1385/MAX1386 include two 8-bit and 10-bit
DAC blocks to independently control the voltage on
each LDMOS gate. Both 10-bit and 8-bit DACs can be
automatically calibrated to minimize output error over
time, temperature, and supply voltage. The 8-bit and
10-bit DACs have unipolar transfer functions and have
a relationship to the output voltage by the following
equation:
where LOCODE, HICODE, and FINECODE are the low
wiper (8 bits), high wiper (8 bits), and fine DAC (10 bits)
values written to the DAC by the user. LOCODE,
HICODE, and FINECODE represent the values in the
DAC input registers and may or may not be the actual
values in the DAC output registers depending whether
autocalibration is used or not (see the 8-Bit
Coarse-
DAC Adjustment
section). To find the actual voltage at
GATE_, multiply the VDACOUT result by 2 (MAX1385) or
4 (MAX1386). Due to the buffer amplifiers, the voltage
at GATE_ cannot be set below 100mV above AGND. It
is recommended that the LOCODE for DAC1 and DAC2
are set so that the minimum possible output at GATE_
is 200mV (MAX1385) and 400mV (MAX1386).
The DACs can be operated to produce an 18-bit
monotonic DAC with 12-bit (typ) INL. Write to either
HICODE or LOCODE in a leapfrog fashion, without
commanding autocalibration, to configure the 18-bit
monotonic DAC. When LOCODE > HICODE, invert the
value of FINECODE.
8-Bit Coarse-DAC Adjustment
Each DAC control block contains a resistor string with
wipers that serve as an 8-bit coarse DAC. Wipers are
set by writing to the appropriate DAC input registers
and/or using the Load DAC Control register (LDAC)
commands. The output of a coarse DAC is not updated
until the appropriate DAC output register(s) have been
set. See Figure 5 for the relationship between DAC
input registers, DAC output registers, and wipers.
DAC output registers are not directly accessible to the
user. Choose which input register to write to based on
whether automatic low or high calibration is desired, or
if updates to the output of the DAC need to be initiated
immediately. In the case of automatic low or high cali-
bration, a correction code is added to or subtracted
from the 10-bit fine-DAC input register. Transfers from
the DAC input registers to DAC output registers can
occur immediately after a write to the appropriate DAC
input register or on a software command through the
Software LDAC register. See the
Register Descriptions
section for bit-level descriptions of these registers.
10-Bit Fine-DAC Adjustment
Each DAC control block contains a 10-bit fine DAC that
operates between the high and low wiper positions
from the 8-bit coarse DAC. The 10-bit fine DAC also
has an optional automatic calibration mode and can be
updated immediately or on a software-issued command
in the Software LDAC register. Writing to the appropri-
ate fine-DAC input register determines whether auto-
matic calibration is used and/or when the DAC is
updated. See Figure 6 for the relationship between
DAC input registers, DAC output registers, and the
Software LDAC register.
The fine-DAC output registers are not directly accessi-
ble. Choose which DAC input register to write to based
on whether automatic fine calibration is desired, or
whether updates to the output of the DAC need to be ini-
tiated immediately. In the case of automatic fine calibra-
tion, a correction code is added to or subtracted from
the input register code and transferred to the appropriate
fine-DAC output register. Transfers from a fine-DAC input
register to a fine-DAC output register can occur immedi-
ately after a write to the appropriate DAC input register or
on a software command through the Software LDAC reg-
ister. See the
Register Descriptions
section for bit-level
detail of these registers.
VVLOCODE VHICODE LOCODE FINECODE
DACOUT REF REF
=× +× −×
22 2
88 10
[]
MAX1385/MAX1386
Dual RF LDMOS Bias Controllers
with I2C/SPI Interface
22 ______________________________________________________________________________________
FINETHRU_ REGISTER
FINECAL_ REGISTER
FINE_ REGISTER
FINECALTHRU_ REGISTER
LOAD DAC CONTROL REGISTER (LDAC)
TO GATE-DRIVE BLOCK
INPUT REGISTERS
FROM 8-BIT COARSE DAC
FROM 8-BIT COARSE DAC
FINE-CAL
FINE DAC_ OUTPUT REGISTER 10-BIT FINE
DAC
Figure 6. Fine-DAC Register Diagram
HIWIPE_ REGISTER
LOWIPE_ REGISTER COARSE DAC_ LOW WIPER OUTPUT REGISTER
THRUHI_ REGISTER
THRULO_ REGISTER
V
DACREF
HCAL
LCAL
LOW-CAL
LOAD DAC CONTROL REGISTER (LDAC)
TO 10-BIT FINE DAC
COARSE DAC_ HIGH WIPER OUTPUT REGISTER
HIGH-CAL
INPUT REGISTERS
Figure 5. Coarse-DAC Register Diagram
MAX1385/MAX1386
Dual RF LDMOS Bias Controllers
with I2C/SPI Interface
______________________________________________________________________________________ 23
ADC/DAC References
The MAX1385/MAX1386 provide an internal low-noise
2.5V reference for the ADCs, DACs, and temperature
sensor. See the
Device Configuration Register
section
for information on configuring the device for external or
internal reference. Connect a voltage source to
REFADC in the 1V to AVDD range when using an exter-
nal ADC reference. Connect a voltage source to REF-
DAC in the 0.5V to 2.5V range when using an external
DAC reference. When using an external voltage refer-
ence, bypass the reference pin with a 0.1µF capacitor
to AGND.
The internal reference has a lowpass filter to reduce
noise. The device allows 60µs (typ) and 81µs (typ) worst
case for the reference to settle before permitting an ana-
log-to-digital conversion. If reference mode 11 is select-
ed, the required settling time is longer. In this case, the
user should set at least one of DAC1PD, DAC2PD, or
FBGON in the Software Shutdown register, any of which
forces the reference to be permanently powered up.
Temperature Measurements
The MAX1385/MAX1386 measure the internal die tem-
perature and two external remote-diode temperature
sensors. Set up a temperature conversion by writing
to the Analog-to-Digital Conversion register (see the
ADCCON (Write)
section). Optionally program SAFE1
and SAFE2 outputs to depend on programmed temper-
ature thresholds.
The MAX1385/MAX1386 can perform temperature mea-
surements with an internal diode-connected transistor.
The diode bias current changes from 66µA to 4µA to
produce a temperature-dependent bias voltage differ-
ence. The second conversion result at 4µA is subtract-
ed from the first at 66µA to calculate a digital value that
is proportional to the absolute temperature. The stored
data result is the aforementioned digital code minus an
offset to adjust from Kelvin to Celsius.
The reference voltage for the temperature measure-
ments is always derived from the internal reference
source. Temperature results are in degrees Celsius
(two’s-complement form).
The temperature-sensing circuits power up for the first
temperature measurement in an analog-to-digital con-
version scan. The temperature-sensing circuits remain
powered until the end of the scan to avoid a possible
67µs delay of internal reference power-up time for each
individual temperature channel. If the continuous con-
vert bit CONCONV is set high and the current ADC
channel selection includes a temperature channel, the
temperature-sensor circuits remain powered up until
the CONCONV bit is set low.
The external temperature-sensor drive current ratio has
been optimized for a 2N3904 npn transistor with an ide-
ality factor of 1.0065. The nonideality offset is removed
internally by a preset digital coefficient. Use of a tran-
sistor with a different ideality factor produces a propor-
tionate difference in the absolute measured
temperature. More details on this topic and others relat-
ed to using an external temperature sensor can be
found in Maxim Application Note 1057:
Compensating
for Ideality and Series Resistance Differences Between
Thermal Sense Diodes
and Application Note 1944:
Temperature Monitoring Using the MAX1253/MAX1254
and MAX1153/MAX1154
.
High-Side Current-Sense PGAs
The MAX1385/MAX1386 provide two high-side current-
sense amplifiers with programmable gain. The current-
sense amplifiers are unidirectional and provide a 5V to
30V input common-mode range. Both CS1+ and CS2+
must be within the specified common-mode range for
proper operation of each amplifier.
The sense amplifiers measure the load current, ILOAD,
through an external sense resistor, RSENSE_, between
the CS_+ and CS_- inputs. The full-scale sense voltage
range (VSENSE_ = VCS_+ - VCS_-) depends on the pro-
grammed gain, AvPGA_ (see the
DCFIG (Read/Write)
section). The sense amplifiers provide a voltage output
at PGAOUT_ according to the following equation:
These outputs are also routed to the internal 12-bit ADC
so that a digital representation of the amplified voltages
can be read through the FIFO.
The PGA scales the sensed voltages to fit the input
range of the ADC. Program the PGA with gains of 2, 10,
and 25 by setting the PGSET_ bits (see the
DCFIG
(Read/Write)
section). The input stages have nominal
input offset voltages of 0mV that can be adjusted by a
trim DAC (not shown in the
Functional Diagram
) over the
-3mV to +3mV range in 25µV steps. Autocalibration can
be used to control the trim DAC to minimize the effective
channel input offset voltage (see the
PGACAL (Write)
section). The PGA feedback network is referenced to
AGND.
ALARM Output
The state of ALARM is logically equivalent to the inclu-
sive OR of SAFE1 and SAFE2. The exception to this
statement is when ALARM is configured for output inter-
rupt mode (see the
Alarm Modes
section). When in out-
put-interrupt mode, ALARM stays in its asserted state
until its associated flag is cleared by reading from the
VAvVV
PGAOUT PGA CS CS____
()=×+−−
MAX1385/MAX1386
Dual RF LDMOS Bias Controllers
with I2C/SPI Interface
24 ______________________________________________________________________________________
ALARM OUTPUT ASSERTED
WHEN MEASURED VALUE
RISES ABOVE THIS LEVEL
RANGE OF VALUES THAT DO NOT CAUSE AN ALARM
HIGHEST POSSIBLE THRESHOLD
VALUE (DEFAULT VALUE FOR HIGH
THRESHOLD REGISTER)
ALARM OUTPUT DEASSERTED
WHEN MEASURED VALUE FALLS
BELOW THIS LEVEL*
HIGH THRESHOLD
LOW THRESHOLD
LOWEST POSSIBLE THRESHOLD
VALUE (DEFAULT VALUE FOR HIGH
THRESHOLD REGISTER)
ALARM OUTPUT DEASSERTED
WHEN MEASURED VALUE RISES
ABOVE THIS LEVEL*
ALARM OUTPUT ASSERTED
WHEN MEASURED VALUE
FALLS BELOW THIS LEVEL
BUILT-IN 8 TO 64 LSBs
OF HYSTERESIS
BUILT-IN 8 TO 64 LSBs
OF HYSTERESIS
*ONLY WHEN ALARM IS CONFIGURED FOR OUTPUT-COMARATOR MODE.
WHEN IN OUTPUT-INTERRUPT MODE, FLAG REGISTER MUST BE READ
FOR ALARM TO BE DEASSERTED.
Figure 7. Window-Threshold-Mode Diagram
Flag register. Configure ALARM for open-drain/push-
pull and active-high/active-low by setting the respective
bits in the Hardware Alarm Configuration register.
SAFE1/SAFE2 Outputs
Set up the SAFE1 and SAFE2 outputs to allow Wired-
OR/AND-type logic functions or to create additional
interrupt-type signals to replace or supplement the
existing ALARM output. SAFE1 and SAFE2 do not have
any internal pullup/pulldown devices.
The SAFE1 and SAFE2 output buffers are CMOS-com-
patible, noninverting, output buffers capable of driving
to within 0.5V of either digital rail. The SAFE1 and
SAFE2 outputs power up as active-high CMOS outputs
with standard logic levels. Configure the SAFE1 and
SAFE2 outputs for open-drain or push-pull by setting
the appropriate bits in the Hardware Alarm
Configuration register. When configuring SAFE1 and
SAFE2 as open-drain outputs, an external pullup resis-
tor is required.
BUSY Output
The BUSY output is forced high to show that the
MAX1385/MAX1386 are busy for a variety of reasons:
• The ADC is in the middle of a user-commanded con-
version cycle (but not in continuous convert mode)
• The ADC is in the middle of an internally triggered
conversion cycle (for a self-calibration measurement)
• The device is in the middle of DAC calibra-
tion calculations
• The device is in the middle of power-up initialization
• One of the PGA channels is undergoing self-calibration
The serial interface remains active regardless of the
state of the BUSY output. Wait until BUSY goes low to
read the current conversion data from the FIFO. When
BUSY is high as a result of an ADC conversion, do not
enter a second conversion command until BUSY has
gone low to indicate the previous conversion is com-
plete. The rising edge of BUSY occurs on the next inter-
nal oscillator clock after the start of a new conversion
(either by CNVST or an interface command).
MAX1385/MAX1386
Dual RF LDMOS Bias Controllers
with I2C/SPI Interface
______________________________________________________________________________________ 25
In single-conversion mode (CKSEL = 11), the BUSY
signal remains high until the ADC has completed the
current conversion (not the entire scan, just the current
conversion), the data has been moved into the FIFO,
and the alarm limits for the channel have been checked
(if enabled). In multiple-conversion mode (CKSEL = 01
or CKSEL = 00), the BUSY signal remains high until all
channels have been scanned and the data from the
final channel has been moved into the FIFO and
checked for alarm limits (if enabled). In continuous-con-
version mode (CONCONV = 1), the BUSY signal does
not go high as a result of ADC conversions; however,
BUSY does go high when CONCONV is removed and
remains high until the current scan is complete and the
ADC sequence halts.
After commanding any of the DAC autocalibration compo-
nents, wait for BUSY to go low before setting OSCPD to 1.
Alarm Modes
The MAX1385/MAX1386 contain several programmable
modes for configuring outputs ALARM, SAFE1, and
SAFE2 behavior. Window-threshold mode allows SAFE_
to assert when the temperature/current is too high or
too low (outside the window). Hysteresis-threshold
mode allows SAFE_ to assert when the temperature/
current is too high, and then to deassert when the tem-
perature/current falls back to an appropriate level.
ALARM asserts when SAFE1 and/or SAFE2 asserts.
Program ALARM for output-comparator mode to stay
asserted after an alarm condition until temperature/cur-
rent levels are back below programmed thresholds.
Program ALARM for output-interrupt mode to stay
asserted after an alarm condition until the Flag register
is read.
Window-Threshold Mode
In window-threshold mode, ADC readings of
current/temperature are compared to the configured
current/temperature low/high thresholds that are pro-
grammed to cause an alarm condition. If an ADC read-
ing falls out of the configured window and ALARM is
configured for output-comparator mode, ALARM
asserts until the current/temperature reading falls back
into the window (past the built-in hysteresis). If an ADC
reading falls out of the configured window and ALARM
is configured for output-interrupt mode, ALARM asserts
until the Flag register is read. Set the amount of built-in
hysteresis from 8 LSBs to 64 LSBs (see the
ALMSCFG
(Read/Write)
section). See Figures 7 and 8.
MEASUREMENT VALUE
(TEMPERATURE OR CURRENT)
HIGH THRESHOLD
BUILT-IN HYSTERESIS
BUILT-IN HYSTERESIS
LOW THRESHOLD
ALARM OUTPUT
OUTPUT-
COMPARATOR MODE
(ACTIVE LOW)
OUTPUT-
INTERRUPT MODE
(ACTIVE LOW)
FLAG REGISTER
READ
FLAG REGISTER
READ
FLAG REGISTER
READ TIME
TIME
Figure 8. Window-Threshold-Mode Timing Diagram
MAX1385/MAX1386
Dual RF LDMOS Bias Controllers
with I2C/SPI Interface
26 ______________________________________________________________________________________
Hysteresis-Threshold Mode
In hysteresis-threshold mode, ADC readings of
current/temperature are compared to the configured
current/temperature low/high thresholds that are pro-
grammed to cause an alarm condition. If an ADC read-
ing exceeds its respective configured threshold and
ALARM is configured for output-comparator mode,
ALARM asserts until the current/temperature reading
falls back below its respective threshold. If an ADC
reading exceeds its respective configured threshold
and ALARM is configured for output-interrupt mode,
ALARM asserts until the Flag register is read. See
Figures 9 and 10.
Register Descriptions
Communicate with the MAX1385/MAX1386 through the
I2C/SPI-compatible serial interface. Complete read and
write operations consist of slave address bytes, com-
mand bytes, and data bytes. The following register
descriptions cover the contents of command bytes and
data bytes. See the
Digital Serial Interface
section for a
detailed description of how to construct full read and
write operations. All registers are volatile and are reset
to default states upon removal of power. These default
states are referred to as power-on reset (POR) states.
All accessible MAX1385/MAX1386 registers are shown
in Table 2.
TH1 and TH2 (Read/Write)
Write to Channel 1 and Channel 2 High Temperature
Threshold registers by sending the appropriate write
command byte followed by data bits D15–D0 (see Table
3). Bits D15–D12 are don’t care. Read channel 1 and
channel 2 high-temperature thresholds by sending the
appropriate read command byte. Channel 1 and
Channel 2 Temperature Threshold registers are com-
pared to temperature readings from the remote diode
connected transistors. Temperature data is in two’s-com-
plement format and the LSB corresponds to 1/8°C (see
Figure 26 for the Temperature Transfer Function).
TL1 and TL2 (Read/Write)
Write to Channel 1 and Channel 2 Low-Temperature-
Threshold registers by sending the appropriate write
command byte followed by data bits D15–D0 (see Table
4). Bits D15–D12 are don’t care. Read channel 1 and
channel 2 low-temperature thresholds by sending the
appropriate read command. Channel 1 and Channel 2
Temperature Threshold registers are compared to tem-
perature readings from the remote diode connected tran-
sistors. Temperature data is in two’s-complement format
and the LSB corresponds to 1/8°C (see Figure 26 for the
Temperature Transfer Function).
ALARM OUTPUT ASSERTED
WHEN MEASURED VALUE
RISES ABOVE THIS LEVEL
RANGE OF VALUES THAT DO NOT CAUSE AN ALARM
HIGHEST POSSIBLE THRESHOLD
VALUE (DEFAULT VALUE FOR HIGH
THRESHOLD REGISTER)
HIGH THRESHOLD
LOW THRESHOLD
LOWEST POSSIBLE THRESHOLD
VALUE (DEFAULT VALUE FOR LOW
THRESHOLD REGISTER)
ALARM OUTPUT ASSERTED
WHEN MEASURED VALUE
FALLS BELOW THIS LEVEL
*ONLY WHEN ALARM IS CONFIGURED FOR OUTPUT-COMARATOR MODE.
WHEN IN OUTPUT-INTERRUPT MODE, FLAG REGISTER MUST BE READ
FOR ALARM TO BE DEASSERTED.
Figure 9. Hysteresis-Threshold-Mode Diagram
MAX1385/MAX1386
Dual RF LDMOS Bias Controllers
with I2C/SPI Interface
______________________________________________________________________________________ 27
HEX COMMAND
REGISTER DESCRIPTION MNEMONIC WRITE READ
Analog-to-Digital Conversion ADCCON 62 —
Channel 1 High-Current Threshold IH1 24 A4
Channel 1 High-Temperature Threshold TH1 20 A0
Channel 1 Low-Current Threshold IL1 26 A6
Channel 1 Low-Temperature Threshold TL1 22 A2
Channel 2 High-Current Threshold IH2 2C AC
Channel 2 High-Temperature Threshold TH2 28 A8
Channel 2 Low-Current Threshold IL2 2E AE
Channel 2 Low-Temperature Threshold TL2 2A AA
Coarse DAC1 High Wiper Input HIWIPE1 34 B4
Coarse DAC1 Low Wiper Input LOWIPE1 36 B6
Coarse DAC1 Write-Through High Wiper Input THRUHI1 74 B4
Coarse DAC1 Write-Through Low Wiper Input THRULO1 76 B6
Coarse DAC2 High Wiper Input HIWIPE2 3A BA
Coarse DAC2 Low Wiper Input LOWIPE2 3C BC
Coarse DAC2 Write-Through High Wiper Input THRUHI2 7A BA
Coarse DAC2 Write-Through Low Wiper Input THRULO2 7C BC
Device Configuration DCFIG 30 B0
FIFO Memory FIFO — 80
Fine DAC1 Input Read RDFINE1 — B8
Fine DAC1 Input Register with Autocalibration FINECAL1 38 —
Fine DAC1 Input Without Autocalibration FINE1 50 —
Fine DAC1 Write-Through Input with Autocalibration FINECALTHRU1 78 —
Fine DAC1 Write-Through Input Without Autocalibration FINETHRU1 52 —
Fine DAC2 Input Read RDFINE2 — BE
Fine DAC2 Input Register with Autocalibration FINECAL2 3E —
Fine DAC2 Input Without Autocalibration FINE2 54 —
Fine DAC2 Write-Through Input with Autocalibration FINECALTHRU2 7E —
Fine DAC2 Write-Through Input Without Autocalibration FINETHRU2 56 —
Flag RDFLAG — EA
Hardware Alarm Configuration ALMHCFG 60 E0
PGA Calibration Control PGACAL 4E —
Software Clear SCLR 68 —
Software LDAC LDAC 66 —
Software Shutdown SSHUT 64 —
Software Alarm Configuration ALMSCFG 32 B2
Table 2. Register Listing (See
Appendix: Recommended Power-Up Code Sequence
section)
MAX1385/MAX1386
Dual RF LDMOS Bias Controllers
with I2C/SPI Interface
28 ______________________________________________________________________________________
IH1 and IH2 (Read/Write)
Write to Channel 1 and Channel 2 High-Current-
Threshold registers by sending the appropriate write
command byte followed by data bits D15–D0 (see
Table 5). Bits D15–D12 are don’t care. Read channel 1
and channel 2 high-current thresholds by sending the
appropriate read command byte. Channel 1 and
Channel 2 Current-Threshold registers are compared to
ADC readings at PGAOUT1 and PGAOUT2. Use the
following equation to find the required threshold code
for a specified threshold current:
where IDRAIN is the current threshold in amperes,
RSENSE is the sense resistor, AvPGA is the voltage gain
of the PGA, VREFADC is the ADC reference voltage, and
ITHRESH is the resulting threshold register value
in decimal.
IL1 and IL2 (Read/Write)
Write to Channel 1 and Channel 2 Low-Current-
Threshold registers by sending the appropriate write
command byte followed by data bits D15–D0 (see
Table 6). Bits D15–D12 are don’t care. Read channel 1
and channel 2 low-current thresholds by sending the
appropriate read command byte. Channel 1 and
Channel 2 Low-Current Threshold registers are com-
pared to ADC readings at PGAOUT1 and PGAOUT2.
IIRAv
V
THRESH DRAIN SENSE PGA REFADC
=× × ×
4096
FLAG REGISTER
READ
FLAG REGISTER
READ
TIME
TIME
MEASUREMENT VALUE
(TEMPERATURE OR CURRENT)
HIGH THRESHOLD
LOW THRESHOLD
ALARM OUTPUT
OUTPUT-
COMPARATOR MODE
(ACTIVE LOW)
OUTPUT-
INTERRUPT MODE
(ACTIVE LOW)
Figure 10. Hysteresis-Threshold-Mode Timing Diagram
D15 D14 D13 D12 D11
(MSB) D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
(LSB)
POR XXXX 0 111111111 1 1
Bit Value
(°C) X X X X -256 +128 +64 +32 +16 +8 +4 +2 +1 +0.5 +0.25 +0.125
Table 3. TH1 and TH2 (Read/Write)
X = Don’t care.
MAX1385/MAX1386
Dual RF LDMOS Bias Controllers
with I2C/SPI Interface
______________________________________________________________________________________ 29
Use the following equation to find the required thresh-
old code for a specified threshold current:
where IDRAIN is the current threshold in amperes,
RSENSE is the sense resistor, AvPGA is the voltage gain
of the PGA, VREFADC is the ADC reference voltage, and
ITHRESH is the resulting threshold register value
in decimal.
DCFIG (Read/Write)
Select PGA gain settings, clock modes, and DAC and
ADC reference modes by sending the appropriate write
command byte followed by data bits D15–D0 (see
Table 7). Bits D15–D10 are don’t care. Read the Device
Configuration register by sending the appropriate read
command byte. Program PG2SET1 and PG2SET0 to set
channel 2’s current-sense amplifier gain (see Table 7a).
Program PG1SET1 and PG1SET0 to set channel 1’s
current-sense amplifier gain (see Table 7a). Set
CKSEL1 and CKSEL0 to determine the conversion and
acquisition timing clock modes (see Table 7b). See the
ADC Clock Modes
section for a functional description
of each clock mode. Set REFADC1 and REFADC0 to
select external/internal reference for the ADC (see
Table 7c). Set REFDAC1 and REFDAC0 to select exter-
nal/internal reference for both DACs (see Table 7d).
When mode 11 is selected, the external capacitor that
is connected to the REFADC is charged by a resistor
with a typical value of 400kΩ. This time constant needs
to be allowed for powering up the reference. Avoid
leakage paths to REFADC.
ALMSCFG (Read/Write)
The Software Alarm Configuration register controls the
behavior of outputs SAFE1, SAFE2, and ALARM. Write
to the Software Alarm Configuration register by sending
the appropriate write command byte followed by data
bits D15–D0 (see Table 8). Bits D15–D12 are don’t
care. Read the Software Alarm Configuration register
by sending the appropriate command byte.
Set ALMSCLR to 1 to immediately set all temperature/
current threshold registers to their POR state. In addi-
tion, temperature-/current-related bits of the Flag regis-
ter are also reset to their POR state. The ALMSCLR
resets to 0 immediately after a write. Set ALARMCMP to
1 to enable output-comparator mode for ALARM and to
0 to enable output-interrupt mode for ALARM (see the
IIRAv
V
THRESH DRAIN SENSE PGA REFADC
=× × ×
4096
D15 D14 D13 D12 D11
(MSB) D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
(LSB)
POR XXXX1 000000000 0 0
Bit Value
(°C) X X X X -256 +128 +64 +32 +16 +8 +4 +2 +1 +0.5 +0.25 +0.125
Table 4. TL1 and TL2 (Read/Write)
X = Don’t care.
D15 D14 D13 D12 D11
(MSB) D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
(LSB)
POR XXXX 1 1111111111 1
Bit ValueXXXX — —————————— —
Table 5. IH1 and IH2 (Read/Write)
X = Don’t care.
D15 D14 D13 D12 D11
(MSB) D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
(LSB)
POR XXXX 0 0 0 0 0 0 0 0 0 0 0 0
Bit Value X X X X — — — — — — — — — — — —
Table 6. IL1 and IL2 (Read/Write)
X = Don’t care.
MAX1385/MAX1386
Dual RF LDMOS Bias Controllers
with I2C/SPI Interface
30 ______________________________________________________________________________________
Alarm Modes
section). Setting ALARMCMP does not
affect SAFE1 and SAFE2 outputs. Program
ALARMHYST1 and ALARMHYST0 to set the amount of
built-in hysteresis used in window-threshold mode.
See the
ALARM Output
and
SAFE1/SAFE2 Outputs
sections for a description of the relationship between
ALARM and SAFE1 and SAFE2. Set TALARM2 to 1 to
allow channel 2 temperature measurements to control
the state of SAFE2 and ALARM based on channel 2
temperature thresholds. Set TWIN2 to 0 to enable hys-
teresis-threshold mode and to 1 to enable window-
threshold mode for channel 2 temperature
measurements (see the
Alarm Modes
section). Set
IALARM2 to 1 to allow channel 2 current measurements
to control the state of SAFE2 and ALARM based on
channel 2 current thresholds. Set IWIN2 to 0 to enable
hysteresis-threshold mode and to 1 to enable window-
threshold mode for channel 2 current measurements.
Set TALARM1 to 1 to allow channel 1 temperature mea-
surements to control the state of SAFE1 and ALARM
based on channel 1 temperature thresholds. Set TWIN1
to 0 to enable hysteresis-threshold mode and to 1 to
enable window-threshold mode for channel 1 tempera-
ture measurements (see the
Alarm Modes
section). Set
IALARM1 to 1 to allow channel 1 current measurements
to control the state of SAFE1 and ALARM based on
channel 1 current thresholds. Set IWIN1 to 0 to enable
hysteresis-threshold mode and to 1 to enable window-
threshold mode for channel 1 current measurements.
HIWIPE1 and HIWIPE2 (Read/Write)
Write to the Coarse DAC1/DAC2 High Wiper Input reg-
ister by sending the appropriate write command byte
followed by data bits D15–D0 (see Table 9). Bits
D14–D8 are don’t care. Read the Coarse DAC1/DAC2
High Wiper Input register by sending the appropriate
read command byte. The DAC output is not updated
until an LDAC command is issued, at which point the
BIT NAME DATA BIT POR FUNCTION
X D15–D10 X Don’t care
PG2SET1 D9 0 PGA 2 gain-setting
PG2SET0 D8 0 PGA 2 gain-setting
PG1SET1 D7 0 PGA 1 gain-setting
PG1SET0 D6 0 PGA 1 gain-setting
CKSEL1 D5 0 Clock mode and CNVST
configuration
CKSEL0 D4 0 Clock mode and CNVST
configuration
REFADC1 D3 0 ADC reference select
REFADC0 D2 0 ADC reference select
REFDAC1 D1 0 DAC reference select
REFDAC0 D0 0 DAC reference select
Table 7. DCFIG (Read/Write)
PG_SET1 PG_SET0 FUNCTION
0 0 PGA_ gain of 2
0 1 PGA_ gain of 10
1 X PGA_ gain of 25
Table 7a. Gain-Setting Modes
X = Don’t care.
CKSEL1 CKSEL0 CONVERSION
CLOCK
ACQUISITION/
SAMPLING
0 0 Internal
Internally timed
acquisitions and
conversions.
Conversions started by
a write to the Analog-
to-Digital Conversion
register or setting the
CONCONV bit.
0 1 Internal
Internally timed
acquisitions and
conversions.
Conversions begin with
a high-to-low transition
at CNVST.
1 0 — Reserved. Do not use.
1 1 Internal
Externally timed
acquisitions by
CNVST. Conversions
internally timed.
Table 7b. Clock Modes
REFADC1 REFADC0 DESCRIPTION
0X
External. Bypass REFADC with a
0.1µF capacitor to AGND.
10
Internal. Leave REFADC
unconnected.
11
Internal. Connect a 0.1µF capacitor
to REFADC for better noise
performance.
Table 7c. ADC Reference Selection
X = Don’t care.
MAX1385/MAX1386
Dual RF LDMOS Bias Controllers
with I2C/SPI Interface
______________________________________________________________________________________ 31
DAC input register is transferred to the appropriate DAC
output register. Automatic calibration of the high wiper is
initiated if the HCAL bit in the DAC input register is set to
1 when the appropriate LDAC command is issued.
LOWIPE1 and LOWIPE2 (Read/Write)
Write to the Coarse DAC1/DAC2 Low Wiper Input regis-
ter by sending the appropriate command byte followed
by data bits D15–D0 (see Table 10). Bits D14–D8 are
don’t care. Read the Coarse DAC1/DAC2 Low Wiper
Input register by sending the appropriate read com-
mand byte. The DAC output is not updated until an
LDAC command is issued, at which point the DAC
input register is transferred to the appropriate DAC out-
put register. Automatic calibration of the low wiper is
initiated if the LCAL bit in the DAC input register is set
to 1 when the appropriate LDAC command is issued.
FINECAL1 and FINECAL2 (Write)
Write to the Fine DAC1/DAC2 Input register with auto-
calibration by sending the appropriate write command
byte followed by data bits D15–D0 (see Table 11). Bits
D15–D10 are don’t care. A write to these registers trig-
gers the autocalibration but does not automatically
update the output of the DAC. Write to the Software
LDAC register (LDAC) to transfer the Fine DAC Input
register contents to the Fine DAC Output register,
thereby updating the output of the DAC. POR contents
for these registers are all zeros. Read the DAC input
register values written to Fine DAC1 and DAC2 Input
registers through the Fine DAC1/DAC2 Input Read reg-
ister. These read registers contain the latest user-write
to any Fine DAC1 or Fine DAC2 Input Read register
and do not contain autocalibration-corrected values.
PGACAL (Write)
Write to the PGA Calibration Control register to calibrate
PGA1 and PGA2 internal amplifiers. Write to the PGA
Calibration Control register by sending the appropriate
write command byte followed by data bits D15–D0 (see
Table 12). Bits D15–D8 are reserved and must be set to
0. Bits D7–D3 are don’t care. Set FIRSTB to 1 to enable
tracking-calibration mode, and to 0 to enable acquisi-
tion-calibration mode.
During an offset calibration trial, for either mode, the
corresponding PGAOUT_ is put into hold, which pro-
duces a pedestal error for 67µs typically and BUSY is
set to 1. In acquisition mode, the calibration routine
operates continuously, first on channel 1 and then on
channel 2, until the channel-input offset voltage error
has been reduced to within 50µV. The time taken for
both channels to complete acquisition depends upon
the initial channel offset voltage error but should never
be longer than 112ms. In tracking mode, a pair of offset
calibration trials, first on channel 1 and then on channel
2, are made each time DOCAL is set to 1 or every 20ms
if the SELFTIME bit is set to 1. To reject noise, the offset
trim DAC code (not shown in the
Functional Diagram
)
only increments or decrements after the results of 16
calibration trials have been averaged.
Set FIRSTB to 0 and DOCAL to 1 to initiate an acquisi-
tion calibration. Acquisition must be done before track-
ing the first time a PGA calibration is commanded. Set
FIRSTB to 1, DOCAL to 1, and SELFTIME to 0 to trigger
an offset calibration trial on PGA1 and PGA2. At the
end of the routine, DOCAL returns to 0. Set FIRSTB to
1, DOCAL to 1 (optional to trigger calibration once
immediately before SELFTIME starts periodic calibra-
tions), and SELFTIME to 1, just once, to trigger periodic
offset-calibration trials (approximately every 20ms). Set
SELFTIME to 0 to halt the periodic calibration.
FINE1 and FINE2 (Write)
Write to the Fine DAC1/DAC2 Input register without auto-
calibration by sending the appropriate write command
byte followed by data bits D15–D0 (see Table 13). Bits
D15–D10 are don’t care. A write to these registers does
not trigger the autocalibration and does not automatically
update the output of the DAC. Write to the Software
LDAC register (LDAC) to transfer the DAC input register
contents to the Fine DAC Output register, thereby updat-
ing the output of the fine DAC. POR contents for these
registers are all zeros. Read the DAC input register val-
ues written to Fine DAC1 and DAC2 Input registers
through the Fine DAC1/DAC2 Input Read register. These
read registers contain the latest user-write to any Fine
DAC1 or Fine DAC2 Input Read register and do not con-
tain autocalibration corrected values.
FINETHRU1 and FINETHRU2 (Write)
Write to the Fine DAC1/DAC2 Write-Through Input reg-
ister without autocalibration by sending the appropriate
write command byte followed by data bits D15–D0 (see
REFDAC1 REFDAC0 DESCRIPTION
0X
External. Bypass REFDAC with a
0.1µF capacitor to AGND.
10
Internal. Leave REFDAC
unconnected.
11
Internal. Connect a 0.1µF capacitor
to REFDAC for extra decoupling
and better noise performance.
Table 7d. DAC Reference Selection
X = Don’t care.
MAX1385/MAX1386
Dual RF LDMOS Bias Controllers
with I2C/SPI Interface
32 ______________________________________________________________________________________
Table 14). Bits D15–D10 are don’t care. A write to these
registers does not trigger the autocalibration but imme-
diately updates the output of the DAC by transferring
the DAC input register to the DAC output register (writ-
ing through the input register). POR contents for these
registers are all zeros. Read the DAC input register val-
ues written to Fine DAC1 and DAC2 Input registers
through the Fine DAC1/DAC2 Input Read register.
These read registers contain the latest user write to any
Fine DAC1 or Fine DAC2 Input Read register and do
not contain autocalibration corrected values.
BIT NAME DATA BIT POR FUNCTION
X D15–D12 X Don’t care
ALMSCLR D11 0 1 = Temp/current thresholds set to POR state
0 = Temp/current thresholds unaffected
ALARMCMP D10 0 1 = ALARM in output-comparator mode
0 = ALARM in output-interrupt mode
ALARMHYST1 D9 0
ALARMHYST0 D8 0
Thresholds hysteresis (ALARMHYST1 is MSB)
00 = 8 LSBs of hysteresis
01 = 16 LSBs of hysteresis
10 = 32 LSBs of hysteresis
11 = 64 LSBs of hysteresis
TALARM2 D7 0 1 = SAFE2 and ALARM dependent on channel 2 temperature
0 = SAFE2 and ALARM not dependent on channel 2 temperature
TWIN2 D6 0 1 = Channel 2 temperature thresholds are in window-threshold mode
0 = Channel 2 temperature thresholds are in hysteresis-threshold mode
IALARM2 D5 0 1 = SAFE2 and ALARM dependent on channel 2 current
0 = SAFE2 and ALARM not dependent on channel 2 current
IWIN2 D4 0 1 = Channel 2 current thresholds are in window-threshold mode
0 = Channel 2 current thresholds are in hysteresis-threshold mode
TALARM1 D3 0 1 = SAFE1 and ALARM dependent on channel 1 temperature
0 = SAFE1 and ALARM not dependent on channel 1 temperature
TWIN1 D2 0 1 = Channel 1 temperature thresholds are in threshold-window mode
0 = Channel 1 temperature thresholds are in hysteresis-threshold mode
IALARM1 D1 0 1 = SAFE1 and ALARM dependent on channel 1 current
0 = SAFE1 and ALARM not dependent on channel 1 current
IWIN1 D0 0 1 = Channel 1 current thresholds are in window-threshold mode
0 = Channel 1 current thresholds are in hysteresis-threshold mode
Table 8. ALMSCFG (Read/Write)
X = Don’t care.
BIT NAME DATA BIT POR FUNCTION
HCAL D15 1 1 = High wiper autocalibration.
0 = No high wiper autocalibration.
— D14–D8 X Don’t care.
— D7–D0 0000 0000 8-bit coarse high wiper DAC input code. D7 is the MSB.
Table 9. HIWIPE1 and HIWIPE2 (Read/Write)
MAX1385/MAX1386
Dual RF LDMOS Bias Controllers
with I2C/SPI Interface
______________________________________________________________________________________ 33
ALMHCFG (Read/Write)
The Hardware Alarm Configuration register controls
SAFE1, SAFE2, and ALARM outputs. Write to the
Hardware Alarm Configuration register by sending the
appropriate write command byte followed by data bits
D15–D0 (see Table 15). Bits D15–D8 are don’t care.
Read the Hardware Alarm Configuration register by
sending the appropriate read command byte.
Set SETSAFE1 to 1 to immediately force SAFE1 active.
This is especially useful when SAFE1 is connected to
OPSAFE1, giving the user software control over shut-
ting down the LDMOS transistor. Set SETSAFE1 to 0 for
normal operation. SETSAFE2 has the same functionality
as SETSAFE1 but for channel 2.
Set ALARMPOL to 1 to configure ALARM active-low. Set
it to 0 to configure ALARM active-high. Set ALARMOPN
to 1 to configure ALARM open-drain. Set it to 0 to config-
ure ALARM push-pull. Set SAFE1POL to 1 to configure
SAFE1 for active-low, and to 0 for active-high. Set
SAFE2POL to 1 to configure SAFE2 for active-low, and to
0 for active-high. Set SAFE1OPN to 1 to configure SAFE1
for open-drain, and to 0 for push-pull. Set SAFE2OPN
to 1 to configure SAFE2 for open-drain, and to 0 for
push-pull.
When connecting SAFE1 and SAFE2 outputs to
OPSAFE1 and OPSAFE2 inputs, configure the device
as follows:
1) Set SAFE1POL and SAFE2POL to 0s.
2) Set SAFE1OPN and SAFE2OPN to 0s.
This ensures that when SAFE1 and SAFE2 are assert-
ed, and connected to OPSAFE1 and OPSAFE2, the
LDMOS transistors are shut off.
ADCCON (Write)
The Analog-to-Digital Conversion register selects which
inputs to the ADC are converted. Write to the Analog-to-
Digital Conversion register by sending the appropriate
write command byte followed by data bits D15–D0 (see
Table 16). Bits D15–D12 are don’t care. Bits D11–D8
are reserved bits and need to be set to 0. Read the
results of the conversions in the FIFO by sending the
appropriate read command byte. See the
ADC
Description
section for a complete description of the
ADC.
Set CONCONV to 1 to convert selected inputs to the
ADC continuously and to 0 to convert selected inputs to
the ADC only once. Set ADCSEL2 to 1 to select volt-
ages at ADCIN2 to be converted. Set IEXT2 to 1 to
select voltages at PGAOUT2 to be converted. Set
BIT NAME DATA BIT POR FUNCTION
LCAL D15 1 1 = Low wiper autocalibration.
0 = No low wiper autocalibration.
— D14–D8 X Don’t care.
— D7–D0 0000 0000 8-bit coarse low wiper DAC input code. D7 is the MSB.
Table 10. LOWIPE1 and LOWIPE2 (Read/Write)
BIT NAME DATA BIT RESET STATE FUNCTION
RESERVED D15–D8 0 Reserved. Set to 0.
X D7–D3 X Don’t care.
FIRSTB D2 0 1 = Tracking calibration mode.
0 = Acquisition calibration mode.
DOCAL D1 0 1 = Initiate the calibration defined by FIRSTB (one time).
0 = Do not initiate a calibration.
SELFTIME D0 0 1 = Initiate periodic calibrations defined by FIRSTB (every 15ms).
0 = Stop periodic calibrations.
Table 12. PGACAL (Write)
DATA BIT POR FUNCTION
D15–D10 X Don’t care.
D9–D0 00 0000 0000 10-bit fine DAC input code.
D9 is the MSB.
Table 11. FINECAL1 and FINECAL2 (Write)
MAX1385/MAX1386
Dual RF LDMOS Bias Controllers
with I2C/SPI Interface
34 ______________________________________________________________________________________
TEXT2 to 1 to select the temperature at external diode 2
to be converted. Set ADCSEL1 to 1 to select voltages at
ADCIN1 to be converted. Set IEXT1 to 1 to select volt-
ages at PGAOUT1 to be converted. Set TEXT1 to 1 to
select the temperature at external diode 1 to be con-
verted. Set TINT to 1 to select the internal temperature
of the MAX1385/MAX1386 to be converted.
During continuous conversions (CONCONV = 1),
the ADC does not trigger the BUSY signal. When
CONCONV is set to 0, the current scan (not just the
current conversion) is completed and the ADC waits for
the next command. During continuous conversions, the
FIFO overflows if the user does not read it quickly
enough. When the FIFO overflows, it contains a mixture
of old and new conversion results (see the
RDFLAG
(Read)
section). Continuous conversion mode is only
available in clock modes 00 and 01.
SSHUT (Write)
The Software Shutdown register shuts down all internal
blocks at once or the DAC, ADC, and PGA blocks indi-
vidually. Write to the Software Shutdown register by
sending the appropriate write command byte followed
by data bits D15–D0 (see Table 17). Bits D15–D8 and
D6, D5, and D4 are don’t care.
Set FULLPD to 1 to shut down all internal blocks and
reduce the AVDD supply current to 0.2µA. FULLPD is
set to 1 at power-up. To change to normal power mode,
write two commands to the Software Shutdown register.
The first command sets FULLPD to 0 (other bits in the
Software Shutdown register are ignored). A second
command is needed to activate any internal blocks.
FULLPD overrides all other shutdown bits; however, all
shutdown bits retain their data when FULLPD is set to
1. This means that if DAC1 and PGA1 are shut down
before FULLPD is set to 1, they remain shut down after
FULLPD is set to 0 again.
Set FBGON to 1 to force the internal bandgap refer-
ence to be powered at all times. Set FBGON to 0 to
transfer power-down control of the internal reference to
the ADC. In the event of DAC1PD or DAC2PD being set
to 0, the internal bandgap is forced on. Set OSCPD to 1
to shut down the internal oscillator. When the oscillator
is shut down, the ADC ceases conversions and internal
PGA calibration halts. Any interface command restarts
the oscillator and allows the system to resume from
where it left off. Set DAC2PD to 1 to shut down DAC2
and PGA2. Set DAC1PD to 1 to shut down DAC1 and
PGA1. DAC1PD and DAC2PD power down the individ-
ual blocks regardless of additional commands; howev-
er, writes are still permitted to the DACs and PGAs. For
maximum accuracy, do not command a DAC calibra-
tion while a DAC is powered down or powering up.
LDAC (Write)
The Software LDAC register controls the loading of the
DAC output registers with values from DAC input regis-
ters, allowing the user to update several changes to the
DAC all at once (see Table 18). Write to the Software
LDAC register by sending the appropriate write com-
mand byte followed by data bits D15–D0. Bits D15–D6
are don’t care. Any bit set to 1 in the Software LDAC
register is immediately set to 0 thereafter.
DATA BIT POR FUNCTION
D15–D10 X Don’t care.
D9–D0 00 0000 0000 10-bit fine DAC input code. D9
is the MSB.
Table 13. FINE1 and FINE2 (Write)
DATA BIT POR FUNCTION
D15–D10 X Don’t care.
D9–D0 00 0000 0000 10-bit fine DAC input code.
D9 is the MSB.
Table 14. FINETHRU1 and FINETHRU2
(Write)
BIT NAME DATA BIT POR FUNCTION
X D15–D8 X Don’t care
SETSAFE1 D7 0
1 = Force SAFE1 active
immediately
0 = Normal operation
SETSAFE2 D6 0
1 = Force SAFE2 active
immediately
0 = Normal operation
ALARMPOL D5 0 1 = ALARM is active-low
0 = ALARM is active-high
ALARMOPN D4 0 1 = ALARM is open-drain
0 = ALARM is push-pull
SAFE1POL D3 0 1 = SAFE1 is active-low
0 = SAFE1 is active-high
SAFE1OPN D2 0 1 = SAFE1 is open-drain
0 = SAFE1 is push-pull
SAFE2POL D1 0 1 = SAFE2 is active-low
0 = SAFE2 is active-high
SAFE2OPN D0 0 1 = SAFE2 is open-drain
0 = SAFE2 is push-pull
Table 15. ALMHCFG (Read/Write)
MAX1385/MAX1386
Dual RF LDMOS Bias Controllers
with I2C/SPI Interface
______________________________________________________________________________________ 35
Set FINECH2 to 1 to load the fine DAC2 output register
with the latest write to DAC2 input registers FINE2 or
FINECAL2. This means that if FINE2 is written to after
FINECAL2, FINE2 is sent to the fine DAC2 output regis-
ter (no calibration code) when FINECH2 is set to 1. Set
HIGHCH2 to 1 to load DAC input register HIWIPE2 into
the Coarse DAC2 High Wiper register. Autocalibration
of the DAC2 high wiper occurs if the HCAL bit in
HIWIPE2 is set to 1. Set LOWCH2 to 1 to load DAC
input register LOWIPE2 into the Coarse DAC2 Low
Wiper register. Autocalibration of the DAC2 low wiper
occurs if the LCAL bit in LOWIPE2 is set to 1.
Set FINECH1 to 1 to load the fine DAC1 output register
with the latest write to DAC input registers FINE1 or
FINECAL1. If FINECAL1 is written to after FINE1,
FINECAL1 is sent to the fine DAC1 output register (with
calibration code) when FINECH1 is set to 1. Set HIGH-
CH1 to 1 to load DAC input register HIWIPE1 into the
Coarse DAC1 output register. Autocalibration of the
DAC1 high wiper occurs if the HCAL bit in HIWIPE1 is
set to 1. Set LOWCH1 to 1 to load DAC input register
LOWIPE1 into the coarse DAC1 output register.
Autocalibration of the DAC1 low wiper occurs if the
LCAL bit in LOWIPE1 is set to 1.
SCLR (Write)
Write to the Software Clear register to reset the DACs
and FIFO to their POR states (see Table 19). Write to the
Software Clear register by sending the appropriate write
command byte followed by data bits D15–D0. Bits
D15–D10 are don’t care. A write to bits D5–D0 in the
Software Clear register immediately changes the appro-
priate DAC output to its power-on state (regardless of
LDAC). To reset all registers at once, set FULLRESET to
0 and ARMRESET to 1. Next set FULLRESET to 1 and
ARMRESET to 0. This 2-byte reset operation protects the
registers from being fully reset by inadvertent user
writes. After a full reset, the device is in shutdown mode
and the SSHUT register needs to be written to for full
operation.
Set CLFIFO to 1 to clear the entire 15-word FIFO and
FIFO-associated flag bits in the Flag register. Set
HIGHCL2 to 1 to reset the Coarse DAC2 High Wiper
Output and Input registers to their POR states. Set
LOWCL2 to 1 to reset the coarse DAC2 High Wiper
Output and Input registers to their POR states. Set
FINECL1 to 1 to reset Fine DAC1 Output and Input reg-
isters to their POR states. Set HIGHCL1 to 1 to reset
the Coarse DAC1 High Wiper Output and Input regis-
ters to their POR states. Set LOWCL1 to 1 to reset the
BIT NAME
DATA BIT POR
FUNCTION
X
D15–D12
X Don’t care
Reserved
D11–D8
0 Reserved; set these bits to 0
CONCONV
D7 0 1 = Continuous conversions (repeated scans)
0 = Noncontinuous conversions (one scan)
ADCSEL2
D6 0 1 = Select voltages at ADCIN2 to be converted
0 = Do not select voltages at ADCIN2 to be converted
IEXT2 D5 0 1 = Select voltages at PGAOUT2 to be converted
0 = Do not select voltages at PGAOUT2 to be converted
TEXT2 D4 0 1 = Select temperature at remote diode 2 to be converted
0 = Do not select temperature at remote diode 2 to be converted
ADCSEL1
D3 0 1 = Select voltages at ADCIN1 to be converted
0 = Do not select voltages at ADCIN1 to be converted
IEXT1 D2 0 1 = Select voltages at PGAOUT1 to be converted
0 = Do not select voltages at PGAOUT1 to be converted
TEXT1 D1 0 1 = Select temperature at remote diode 1 to be converted
0 = Do not select temperature at remote diode 1 to be converted
TINT D0 0 1 = Select internal temperature of device to be converted
0 = Do not select internal temperature of device to be converted
Table 16. ADCCON (Write)
MAX1385/MAX1386
Dual RF LDMOS Bias Controllers
with I2C/SPI Interface
36 ______________________________________________________________________________________
Coarse DAC1 Low Wiper Output and Input registers to
their POR states. Set FINECL2 to 1 to reset Fine DAC2
Output and Input registers to their POR states.
THRUHI1 and THRUHI2 (Read/Write)
Write to the Coarse DAC1/DAC2 Write-Through High
Wiper Input register by sending the appropriate write
command byte followed by data bits D15–D0 (see
Table 20). Bits D15–D8 are don’t care. Writing to one of
these registers automatically writes through to the
appropriate DAC output register, thereby updating the
DAC output immediately. Writing to one of these regis-
ters does not trigger automatic high wiper calibration.
Read the Coarse DAC1/DAC2 Write-Through High
Wiper Input register by sending the appropriate read
command byte.
THRULO1/THRULO2 (Read/Write)
Write to the Coarse DAC1/DAC2 Write-Through Low
Wiper Input register by sending the appropriate write
command byte followed by data bits D15–D0 (see
Table 21). Bits D15–D8 are don’t care. Writing to one of
these registers automatically writes through to the
appropriate DAC output register, thereby updating the
DAC output immediately. Writing to one of these regis-
ters does not trigger automatic low wiper calibration.
Read the Coarse DAC1/DAC2 Write-Through Low
BIT NAME DATA BIT POR FUNCTION
X D15–D8 X Don’t care
FULLPD D7 1 1 = Shut down all internal blocks
0 = Do not shut down all internal blocks
X D6, D5, D4 X Don’t care
FBGON D3 0 1 = Force internal bandgap reference to be powered always
0 = Let the ADC control power-down of the internal reference
OSCPD D2 0 1 = Shut down the internal oscillator
0 = Do not shut down the internal oscillator
DAC2PD D1 1 1 = Power down DAC2
0 = Do not power down DAC2
DAC1PD D0 1 1 = Power down DAC1
0 = Do not power down DAC1
Table 17. SSHUT (Write)
BIT NAME DATA BIT POR FUNCTION
X D15–D6 X Don’t care
FINECH2 D5 N/A 1 = Update fine DAC2 with FINE2 or FINECAL2
0 = Do not update DAC2
HIGHCH2 D4 N/A 1 = Update coarse DAC2 with HIWIPE2
0 = Do not update DAC2
LOWCH2 D3 N/A 1 = Update coarse DAC2 with LOWIPE2
0 = Do not update DAC2
FINECH1 D2 N/A 1 = Update fine DAC1 with FINE1 or FINECAL1
0 = Do not update DAC1
HIGHCH1 D1 N/A 1 = Update coarse DAC1 with HIWIPE1
0 = Do not update DAC1
LOWCH1 D0 N/A 1 = Update coarse DAC1 with LOWIPE1
0 = Do not update DAC1
Table 18. LDAC (Write)
MAX1385/MAX1386
Dual RF LDMOS Bias Controllers
with I2C/SPI Interface
______________________________________________________________________________________ 37
Wiper Input register by sending the appropriate read
command byte.
FINETHRUCAL1 and FINETHRUCAL2 (Write)
Write to the Fine DAC1/DAC2 Write-Through Input reg-
ister with autocalibration by sending the appropriate
write command byte followed by data bits D15–D0 (see
Table 22). Bits D15–D10 are don’t care. A write to these
registers not only triggers the autocalibration but imme-
diately updates the output of the DAC by transferring
the DAC input register with correction code to the Fine
DAC output register. POR contents for these registers
are all zeros. Read the DAC Input register values writ-
ten to Fine DAC1 and DAC2 Input registers through the
Fine DAC1/DAC2 Input Read register. These read reg-
isters contain the latest user-write to any Fine DAC1 or
Fine DAC2 Input register and do not contain autocali-
bration-corrected values.
FIFO (Read)
Read the oldest result in the FIFO by sending the
appropriate read command byte and reading out data
bits D15–D0 (see Table 23). Bits D15–D12 are channel
tag bits that indicate the source of the conversion. Bits
D11–D0 contain the conversion result. Reading from
the FIFO when the FIFO is empty results in the current
contents of the Flag read register to be sent.
RDFINE1 and RDFINE2 (Read)
Read the Fine DAC1/DAC2 Input Read register by
sending the appropriate read command byte and read-
ing out data bits D15–D0 (see Table 24). Data contains
the last write to any Fine DAC1/DAC2 Input registers
and does not contain autocalibration-corrected values.
RDFLAG (Read)
The Flag register contains important system information
regarding ADC/FIFO status and alarm conditions. Read
the Flag register by sending the appropriate read com-
mand byte and reading out data bits D15–D0 (see
Table 25). Bits D15–D12 are don’t care. ADCBUSY is
set to 1 when the ADC is busy, an ALARM value is
being checked, or the ADC results are being loaded
into the FIFO. ADCBUSY is set to 0 when the ADC has
completed all the conversions in the current scan.
ALUBUSY is set to 1 when the ALU is busy and set to 0
when it is not. ALUBUSY is set to 1 for 134µs at power-
up for initialization. FIFOEMP is set to 1 when the FIFO
is empty and set to 0 when the FIFO contains data.
Writing to the appropriate bit in the Software Clear reg-
ister empties the FIFO and sets the FIFOEMP bit to 1.
BIT NAME DATA BIT POR FUNCTION
X D15–D10 X Don’t care
FULLRESET D9 N/A
ARMRESET D8 0
Full reset of all DAC registers is a two write operation:
1) FULLRESET = 0, ARMRESET = 1
2) FULLRESET = 1, ARMRESET = 0
X D7 X Don’t care
CLFIFO D6 N/A 1 = Clear FIFO and FIFO flag bits
0 = Do not clear FIFO or FIFO flag bits
HIGHCL2 D5 N/A 1 = Reset coarse DAC2 high wiper to its POR state
0 = Do not reset coarse DAC2 high wiper to its POR state
LOWCL2 D4 N/A 1 = Reset coarse DAC2 low wiper to its POR state
0 = Do not reset coarse DAC2 low wiper to its POR state
FINECL1 D3 N/A 1 = Reset fine DAC1 to its POR state
0 = Do not reset fine DAC1 to its POR state
HIGHCL1 D2 N/A 1 = Reset coarse DAC1 high wiper to its POR state
0 = Do not reset coarse DAC1 high wiper to its POR state
LOWCL1 D1 N/A 1 = Reset coarse DAC1 high wiper to its POR state
0 = Do not reset coarse DAC1 high wiper to its POR state
FINECL2 D0 N/A 1 = Reset fine DAC2 to its POR state
0 = Do not reset fine DAC2 to its POR state
Table 19. SCLR (Write)
MAX1385/MAX1386
Dual RF LDMOS Bias Controllers
with I2C/SPI Interface
38 ______________________________________________________________________________________
FIFOOVER is set to 1 when the FIFO overflows.
FIFOOVER is set to 0 after reading the Flag register.
All threshold-related bits in the Flag register can be
cleared at once by writing to the ALMSCLR bit in the
Software Alarm Configuration register (see the
ALMSCFG
(Read/Write)
section). HIGHI2 is set to 1 when the chan-
nel 2 current exceeds its high threshold. HIGHI2 resets to
0 after reading the Flag register. LOWI2 is set to 1 when
the channel 2 current drops below its low threshold.
LOWI2 resets to 0 after reading the Flag register.
HIGHT2 is set to 1 when the channel 2 temperature
measurement exceeds its high threshold. HIGHT2
resets to 0 after reading the Flag register. The LOWT2
is set to 1 when the channel 2 temperature measure-
ment drops below its low threshold. LOWT2 resets to 0
after reading the Flag register.
HIGHI1 is set to 1 when the channel 1 current exceeds
its high threshold. HIGHI1 resets to 0 after reading the
Flag register. LOWI1 is set to 1 when the channel 1 cur-
rent drops below its low threshold. LOWI1 resets to 0
after reading the Flag register. HIGHT1 is set to 1 when
the channel 1 temperature measurement exceeds its
high threshold. HIGHT1 resets to 0 after reading the
Flag register. LOWT1 is set to 1 when the channel 1
temperature measurement drops below its low thresh-
old. LOWT1 resets to 0 after reading the Flag register.
Digital Serial Interface
The MAX1385/MAX1386 contain an I2C-/SPI-compati-
ble serial interface for configuration. Connect the mode-
select input, SEL, to DGND to select I2C mode. In I2C
mode, the MAX1385/MAX1386 provide address inputs
A0 to A2 to allow eight devices to be connected on the
same bus (see the
Slave Address Byte
section).
Connect SEL to DVDD to select SPI mode. In SPI mode,
drive A0/CSB low to select the device. The MAX1385/
MAX1386 support fast (400kHz) and high-speed
(1.7MHz or 3.4MHz) data-transfer modes. Data trans-
fers occur in 8-bit bytes with acknowledge (ACK) or
not-acknowledge (NACK) bits following each byte. The
MAX1385/ MAX1386 are permanent slaves and do not
generate their own clock signals. Figure 11 shows the
various read/write formats.
Write Format
Use the following sequence to write a single word (see
Figure 11):
1) After generating a START condition (S or Sr),
address the MAX1385/MAX1386 by sending the
appropriate slave address byte with its correspond-
ing R/Wbit set to zero (see the
Slave Address Byte
section). The MAX1385/MAX1386 answer with an
ACK bit (see the
Acknowledge Bits
section).
2) Send the appropriate write command byte (see the
Command Byte
section). The MAX1385/MAX1386
answer with an ACK bit.
3) Send the most significant 8-bit section of the 16-bit
data word, sending the MSBs first (see the
Data
Bytes
section). The MAX1385/MAX1386 answer with
an ACK bit.
4) Send the least significant 8-bit section of the 16-bit
data word, sending the MSBs first. The MAX1385/
MAX1386 answer with an ACK bit.
5) Generate a (repeated) START or STOP condition (Sr
or P).
To write to a block of registers, use the same steps as
above but repeat steps 2, 3, and 4 without any START,
STOP, or repeated START conditions (Sr). Finish the
block write by generating a STOP condition.
Read Format
All read operations can begin with a Sr as well as an S
condition. One type of read is a 5-byte operation, one is
a 3-byte operation, and the other is a continuous read
operation. The 5-byte operation reads from the register
address contained in one of the 5 bytes sent. The 3-
byte operation reads from the last register address
accessed. Use the following 5-byte sequence to read
DATA BIT POR FUNCTION
D15–D10 X Don’t care.
D9–D0 00 0000 0000 10-bit fine DAC input code. D9
is the MSB.
Table 22. FINETHRUCAL1 and
FINETHRUCAL2 (Write)
DATA BIT POR FUNCTION
D15–D8 X Don’t care.
D7–D0 0000 0000 8-bit coarse high wiper DAC
input code. D7 is the MSB.
Table 20. THRUHI1 and THRUHI2
(Read/Write)
DATA BIT POR FUNCTION
D15–D8 X Don’t care.
D7–D0 0000 0000 8-bit coarse high wiper DAC input
code. D7 is the MSB.
Table 21. THRULO1 and THRULO2
(Read/Write)
MAX1385/MAX1386
Dual RF LDMOS Bias Controllers
with I2C/SPI Interface
______________________________________________________________________________________ 39
16 bits of data from a MAX1385/MAX1386 register (see
Figure 11):
1) After generating a START condition (S or Sr),
address the MAX1385/MAX1386 by sending the
appropriate slave address byte and its correspond-
ing R/Wbit set to a 0 (see the
Slave Address Byte
section). The MAX1385/MAX1386 then answer with
an ACK bit (see the
Acknowledge Bits
section).
2) Send the appropriate read command byte (see the
Command Byte
section). The MAX1385/MAX1386
answer with an ACK bit.
3) After generating a repeated START condition (Sr),
address the MAX1385/MAX1386 once more by
sending the appropriate slave address byte and its
R/Wbit set to 1. The MAX1385/MAX1386 answer
with an ACK bit.
4) The MAX1385/MAX1386 transmit the most signifi-
cant 8-bit data byte of the 16-bit data word with the
MSB first. Afterwards, the master needs to send an
ACK bit.
5) The MAX1385/MAX1386 transmit the least signifi-
cant 8-bit byte of the 16-bit word with the MSB first.
6) The master issues a NACK bit and then generates a
repeated START or STOP condition (Sr or P).
Continue to poll the current register or read multiple
words (e.g., empty FIFO of several conversion results)
by omitting step 6 and keep issuing ACK bits after each
data byte. Use the following 3-byte sequence to read
16 bits of data from the last accessed MAX1385/
MAX1386 register:
1) After generating a START condition (S or Sr),
address the MAX1385/MAX1386 by sending the
appropriate 7-bit slave address byte and its corre-
sponding R/Wbit set to 1 (see the
Slave Address
Byte
section). The MAX1385/MAX1386 then answer
with an ACK bit (see the
Acknowledge Bits
section).
DATA BITS
D15 D14 D13 D12 D11 D0 CONVERSION ORIGIN
0 0 0 0 MSB LSB Internal temperature sensor
0 0 0 1 MSB LSB Channel 1 external temperature
0 0 1 0 MSB LSB Channel 1 drain current (PGAOUT1)
0 0 1 1 MSB LSB ADCIN1
0 1 0 0 MSB LSB Channel 2 external temperature
0 1 0 1 MSB LSB Channel 2 drain current (PGAOUT2)
0 1 1 0 MSB LSB ADCIN2
0 1 1 1 — — Reserved
1 0 0 0 — — Reserved
1 0 0 1 — — Reserved
1 0 1 0 — — Reserved
1 0 1 1 — — Reserved
1 1 0 0 — — Reserved
1 1 0 1 — — Reserved
1110MSB LSB
Conversion may be corrupted. This occurs only when
arriving data causes the FIFO to overflow at the same time
data is being read out.
1111MSB
BITS D11–D0 CONTAIN THE CONVERSION RESULT
LSB Empty FIFO. The current value of the Flag register is
provided in place of the FIFO data.
Table 23. FIFO (Read)
DATA BITS POR FUNCTION
D15–D10 X Don’t care.
D9–D0 00 0000 0000 10-bit fine DAC input code.
D9 is the MSB.
Table 24. RDFINE1 and RDFINE2 (Read)
MAX1385/MAX1386
Dual RF LDMOS Bias Controllers
with I2C/SPI Interface
40 ______________________________________________________________________________________
2) The MAX1385/MAX1386 then transmit the contents
of the last register accessed starting with the most
significant 8-bit byte of the 16-bit word. MSBs are
sent first. Afterwards, the master needs to send an
ACK bit.
3) The MAX1385/MAX1386 transmit the least signifi-
cant 8-bit byte of the 16-bit word. MSBs are sent
first.
4) The master issues a NACK bit and then generates a
repeated START or STOP condition (Sr or P).
Poll the current register by omitting step 4 and continu-
ing to issue ACK bits after each data byte.
Stringing Commands
The MAX1385/MAX1386 allow commands to be strung
together to minimize configuration time, which is espe-
cially useful in HS mode. Figure 12 shows an example
of stringing a write and read command together to form
a write/readback command.
Figure 13 shows another useful sequence for a read-
modify-write application.
Slave Address Byte
The MAX1385/MAX1386 include a 7-bit-long slave
address. The first 4 bits (MSBs) of the slave address
are factory programmed and always 0x4h. The logic
state of the address inputs (A2, A1, and A0) determine
the 3 LSBs of the device address (see Figure 14).
Connect A2, A1, and A0 to DVDD or DGND. A maxi-
mum of eight MAX1385/MAX1386 devices can be con-
nected on the same bus at one time using these
address inputs.
The 8th bit of the address byte is a R/Wbit. The
address byte R/Wbit is set to 0 to notify the device that
a command byte will be written to the device next. The
address byte R/Wbit is set to 1 to notify the device that
a control byte will not be sent and to immediately send
data from the last accessed register.
WRITE WORD FORMAT
ADDRESS R/WACK WRITE
COMMAND ACK DATA ACK Sr OR P
7 BITS 8 BITS 0
DATA
S OR Sr ADDRESS ACK Sr OR P
1
S OR Sr ADDRESS ACK ACK DATA ACK
0
DATA
ACK
Sr OR PACK
ADDRESS ACK READ
COMMAND ACK Sr ADDRESS ACK DATA ACK DATA NACK Sr OR P
10
DATA ACK DATA NACK
8 BITS (MSB) 8 BITS (LSB)
WRITE BLOCK FORMAT
7 BITS 8 BITS
R/WWRITE
COMMAND
8 BITS (MSB) 8 BITS (LSB)
N 3-BYTE SEQUENCES (S, Sr, AND P NOT NEEDED)
8 BITS (MSB) 8 BITS (LSB)
R/WR/W
7 BITS 8 BITS 7 BITS
5-BYTE READ
3-BYTE READ
R/W
7 BITS 8 BITS (MSB) 8 BITS (LSB)
S OR Sr
S OR Sr
Figure 11. Read/Write Formats
MAX1385/MAX1386
Dual RF LDMOS Bias Controllers
with I2C/SPI Interface
______________________________________________________________________________________ 41
Command Byte
The MAX1385/MAX1386 use read and write command
bytes (see Figure 15). The command byte consists of 8
bits and contains the address of the register. The com-
mand byte also communicates to the device whether a
read or write operation occurs. See the
Register
Description
section for details on how to access specif-
ic registers through the command byte.
Data Bytes
Data bytes are clocked in/out of the device with the
MSB first and the LSB last (see Figure 16). See the
Register Description
section for a description of data
bytes for each register.
Bit Transfer
One data bit is transferred during each SCL clock
cycle. The data on SDA must remain stable during the
high period of the SCL clock pulse. Changes in SDA
while SCL is high and stable are considered control
signals (see the
START and STOP Conditions
section).
Both SDA and SCL remain high when the bus is not
active. The interface can support fast (400kHz) and
high-speed (1.7MHz or 3.4MHz) data-transfer modes.
START and STOP Conditions
The master initiates a transmission with a START condi-
tion (S), which is a high-to-low transition on SDA while
SCL is high. The master terminates a transmission with
a STOP condition (P), which is a low-to-high transition
on SDA while SCL is high (Figure 17). A repeated
START condition (Sr) can be used in place of a STOP
condition to leave the bus active and the interface
transfer speed unchanged (see the
Fast/High-Speed
Modes
section).
BIT NAME DATA BIT POR FUNCTION
X D15– D12 X Don’t care
ADCBUSY D11 0 1 = ADC is busy
0 = ADC is not busy
ALUBUSY D10 1 1 = ALU is busy
0 = ALU is not busy
FIFOEMP D9 0 1 = FIFO is empty
0 = FIFO is not empty
FIFOOVER D8 0 1 = FIFO overflowed
0 = FIFO not overflowed
HIGHI2 D7 0 1 = Channel 2 high current threshold exceeded
0 = Channel 2 high current threshold not exceeded
LOWI2 D6 0 1 = Channel 2 low current threshold surpassed
0 = Channel 2 low current threshold not surpassed
HIGHT2 D5 0 1 = Channel 2 high temperature threshold exceeded
0 = Channel 2 high temperature threshold not exceeded
LOWT2 D4 0 1 = Channel 2 low temperature threshold surpassed
0 = Channel 2 low temperature threshold not surpassed
HIGHI1 D3 0 1 = Channel 1 high current threshold exceeded
0 = Channel 1 high current threshold not exceeded
LOWI1 D2 0 1 = Channel 1 low current threshold surpassed
0 = Channel 1 low current threshold not surpassed
HIGHT1 D1 0 1 = Channel 1 high temperature threshold exceeded
0 = Channel 1 high temperature threshold not exceeded
LOWT1 D0 0 1 = Channel 1 low temperature threshold surpassed
0 = Channel 1 low temperature threshold not surpassed
Table 25. RDFLAG (Read)
MAX1385/MAX1386
Dual RF LDMOS Bias Controllers
with I2C/SPI Interface
42 ______________________________________________________________________________________
Acknowledge Bits
Data transfers are acknowledged with an acknowledge
bit (ACK) or a not-acknowledge bit (NACK). Both the
master and the MAX1385/MAX1386 generate ACK bits.
To generate an ACK, SDA must be pulled low before
the rising edge of the ninth clock pulse and kept low
during the high period of the ninth clock pulse (see
Figure 20). To generate a NACK, SDA is pulled high
before the rising edge of the ninth clock pulse and is
left high for the duration of the ninth clock pulse.
Monitoring NACK bits allow for detection of unsuccess-
ful data transfers. NACK bits can also be used by the
master to interrupt the current data transfer to start
another data transfer. The MAX1385/MAX1386 do not
issue an ACK after the last byte of a full reset write to
the Software Clear register.
Fast/High-Speed Modes
At power-up, the bus timing is set for slow-/fast-speed
mode (FS mode), which allows bus speeds up to
400kHz. The MAX1385/MAX1386 are configurable for
S OR Sr ADDRESS ACK WRITE
COMMAND ACK DATA ACK
Sr
7 BITS 0
DATA ACK
ADDRESS DATA ACK DATA Sr OR P
NACK
ACK
R/W
8 BITS (MSB) 8 BITS (LSB)
8 BITS
7 BITS 18 BITS (MSB) 8 BITS (LSB)
R/W
Figure 12. Write/Readback Sequence
S OR Sr ADDRESS ACK READ
COMMAND ACK Sr
7 BITS
0
ADDRESS DATA ACK DATA
Sr OR P
NACK
ACK
R/W
8 BITS
7 BITS 8 BITS (MSB) 8 BITS (LSB)
R/W
1
7 BITS
ADDRESS ACK
R/WWRITE
COMMAND ACK DATA ACK DATA ACK
Sr
08 BITS 8 BITS (MSB) 8 BITS (LSB)
Figure 13. Read-Modify-Write Sequence
SDA
SCL
010 0A2A1A0 ACK
1234 56789
S
R/W
Figure 14. Slave Address Byte
MAX1385/MAX1386
Dual RF LDMOS Bias Controllers
with I2C/SPI Interface
______________________________________________________________________________________ 43
high-speed mode (HS mode), allowing bus speeds up
to 3.4MHz. Execute the following procedure to change
from FS mode to HS mode (see Figure 21).
1) Generate a START condition (S).
2) Send byte 00001XXX (X = don’t care). The MAX1385/
MAX1386 issue a NACK bit.
3) HS mode is entered on the 10th rising clock edge.
To remain in HS mode, use repeated START conditions
(Sr) in place of the normal STOP conditions (P) (see
Figure 22). All the same write and read formats sup-
ported in FS mode are supported in HS mode (with the
replacement of repeated START conditions for STOP
conditions). Generating a STOP condition (P) while in
HS mode changes the bus speed back to FS mode.
SPI Digital Serial Interface
The MAX1385/MAX1386 feature a 4-wire SPI-compati-
ble serial interface capable of supporting data rates up
to 16MHz. Full data transfers occur in 24-bit sections.
The first 8-bit byte is a command byte (C7–C0). The
next 16 bits are data bits (D15–D0). Clock signal SCL
may idle low or high but data is always clocked in on
the rising edge of SCL (CPOL = CPHA).
Write Format
Use the following sequence to write 16 bits of data to a
MAX1385/MAX1386 register (see Figure 18):
1) Pull CSB low to select the device.
2) Send the appropriate write command byte (see the
Command Byte
section). The command byte is
clocked in on the rising edge of SCL.
SDA
SCL 123
456789
C6
C7 C5 C4 C3 C2 C1 C0 ACK
Figure 15. Command Byte
SDA
SCL 123456789
D14
D15 D13 D12 D11 D10 D9 D8 ACK
10 11 12 13 14 15 16 17 18
D6
D7 D5 D4 D3 D2 D1 D0 NACK
OR ACK
Figure 16. Data Bytes
SCL
SDA
SSr P
Figure 17. START and STOP Conditions
MAX1385/MAX1386
Dual RF LDMOS Bias Controllers
with I2C/SPI Interface
44 ______________________________________________________________________________________
3) Send 16 bits of data (D15–D0) starting with the most
significant bit and ending with the least significant
bit. Data is clocked in on the rising edges of SCL.
4) Pull CSB high.
Read Format
Use the following sequence to read 16 bits of data from
a MAX1385/MAX1386 register (see Figure 19):
1) Pull CSB low to select the device.
2) Send the appropriate read command byte (see the
Command Byte
section). The command byte is
clocked in on the rising edges of SCL.
3) Receive 16 bits of data. Data is clocked out on the
falling edges of SCL.
4) Pull CSB high.
Command Byte
The MAX1385/MAX1386 use read and write command
bytes. The command byte consists of 8 bits and contains
the address of the register (C7–C0, see Figures 18 and
19). The command byte also communicates to the
device whether a read or write operation occurs. See the
Register Description
section for details on how to access
specific registers through the command byte.
Data Bytes
Data bytes are clocked in/out of the device with the
most significant bit first and the least significant bit last
(D15–D0, see Figures 18 and 19). See the
Register
Description
section for a description of data bytes for
each register.
SCL
SDA
S
1289
NOT ACKNOWLEDGE
ACKNOWLEDGE
Figure 20. Acknowledge Bits
SCL
C6 C5 C4 C3 C2 C1 C0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
CR/W
DIN
CSB
A RISING EDGE OF CSB
DURING THIS PERIOD
COMPLETES A VALID
WRITE COMMAND.
Figure 18. SPI Write Format
SCL
C6 C5 C4 C3 C2 C1 C0
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
CR/W
DIN
CSB
DOUT
Figure 19. SPI Read Format
MAX1385/MAX1386
Dual RF LDMOS Bias Controllers
with I2C/SPI Interface
______________________________________________________________________________________ 45
Applications Information
ADC Clock Mode 11
See Figure 23 for an example of configuring a conver-
sion scan for internal temperature, PGAOUT1, and
ADCIN1 in clock mode 11 using the internal reference.
Timing symbols are referenced in the
Miscellaneous
Timing Characteristics
section.
See Figure 24 for an example of configuring a conver-
sion scan for ADCIN1, external temperature sensor 2,
and PGAOUT2 in clock mode 11 using the internal ref-
erence. Timing symbols are referenced in the
Miscellaneous Timing Characteristics
section.
Temperature-Threshold Examples
Table 26 shows some examples of temperature settings
in two’s-complement form.
Leap-Frogging the DACs for 18 Bits of
Resolution
Each DAC stage is configurable for leapfrog operation
by using the 8-bit coarse DACs in conjunction with the
10-bit fine DAC. Use the following procedure for setting
18 bits of resolution:
1) Write to the Coarse DAC1/DAC2 Write-Through Low
Wiper Input register (THRULO1/THRULO2)
2) Write to the Coarse DAC1/DAC2 Write-Through High
Wiper Input register (THRUHIGH1/THRUHIGH2) with
a value one higher or one lower than written to the
low wiper register.
MASTER TO SLAVE
SLAVE TO MASTER
FS MODE FS MODE
SMASTER CODE ASr SLAVE ADDRESS ACOMMAND/DATA
Sr SLAVE ADD
HS MODE CONTINUES
R/W
FS MODE
N BYTES PLUS ACK
HS MODE CAN ALSO BE CONTINUED
WITH A COMMAND BYTE
AP
Figure 22. Changing to FS Mode or Staying in HS Mode
SCL
S00001 XXX
ASr
HS-MODE MASTER CODE
SDA
HS MODE
FS MODE
Figure 21. Changing to HS Mode
MAX1385/MAX1386
Dual RF LDMOS Bias Controllers
with I2C/SPI Interface
46 ______________________________________________________________________________________
3) Write to the Fine DAC1/DAC2 Write-Through Input
register without autocalibration (FINETHRU1/
FINETHRU2). If the coarse DAC1/DAC2 low wiper is
higher than the coarse DAC1/DAC2 high wiper,
invert the fine DAC1/DAC input register code.
The resulting output when the high wiper is higher than
the low wiper is shown below:
where FINECODE is the value written to the Fine
DAC1/DAC2 Input register, and LOWCODE is the value
VFINECODE VLOWCODE
DACREF DACREF
22
18 8
×+×
USER WRITES TO THE ANALOG-TO-DIGITAL
CONVERSION REGISTER TO SET UP CONVERSION
SCAN OF ADCIN2, EXTERNAL TEMPERATURE
SENSOR2, AND PGAOUT2
ADCIN2 CONVERSION
RESULT STORED IN FIFO
EXTERNAL TEMPERATURE
SENSOR 2
CONVERSION RESULT
STORED IN FIFO
PGAOUT2
CONVERSION RESULT
STORED IN FIFO
END OF SCAN, REF
AND TEMP SENSOR
POWER DOWN
AUTOMATICALLY
2.0µs ACQUISITION FOR ADCIN1
5.5µs CONVERSION TIME FOR ADCIN1
IDLE, BUT REF
AND TEMP
SENSOR STAY
POWERED UP
TEMP CONVERSION
IN ~40µs
TEMP SENSOR POWERS UP
AND ACQUIRES IN ~6.7µs
INT REFERENCE POWERS
UP IN ~60µs
CNVST
INTERNAL
BUSY
t
APUINT
t
CNV11
t
ACQ11
5.5µs CONVERSION TIME FOR ADCIN2
2µs ACQUISITION OF ADCIN2
IDLE, BUT
REF STAYS
POWERED UP
Figure 24. ADC Clock Mode 11, Example 2
CNVST
USER WRITES TO THE ANALOG-TO-DIGITAL CONVERSION REGISTER
TO SET UP CONVERSION SCAN OF INTERNAL
TEMPERATURE, PGAOUT1, AND ADCIN1
INTERNAL
BUSY
INT REFERENCE POWERS
UP IN ~60µs
TEMP SENSOR POWERS UP
AND ACQUIRES IN ~6.7µs
TEMP CONVERSION
IN ~40µs
IDLE, BUT REF
AND TEMP
SENSOR STAY
POWERED UP
IDLE, BUT REF
AND TEMP
SENSOR STAY
POWERED UP
47µs ACQUISITION FOR
PGAOUT1
5.5µs CONVERSION TIME
FOR PGAOUT1
2µs ACQUISITION FOR
ADCIN1
5.5µs CONVERSION TIME
FOR ADCIN1
END OF SCAN, REF
AND TEMP SENSOR
POWER DOWN
AUTOMATICALLY
t
ACQ11
t
ACQ11
INTERNAL TEMPERATURE
CONVERSION RESULT IS
STORED IN FIFO
PGAOUT1
CONVERSION RESULT
STORED IN FIFO
ADCIN1
CONVERSION RESULT
STORED IN FIFO
t
CNV11
Figure 23. ADC Clock Mode 11, Example 1
MAX1385/MAX1386
Dual RF LDMOS Bias Controllers
with I2C/SPI Interface
______________________________________________________________________________________ 47
written to the Coarse DAC1/DAC2 Input Low Wiper reg-
ister. The resulting output when the low wiper is higher
than the high wiper is:
Basic Software Initialization
The MAX1385/MAX1386 do not power on all internal
blocks when full power is first applied. Software must
write to register 0x64 twice with bit D7 set to 0 during
initialization to enable full operation. A basic initializa-
tion sequence is shown in Table 27.
Regulating VGS vs. Temperature
The MAX1385/MAX1386 can be used along with a
microcontroller to perform closed-loop regulation of the
LDMOS FET bias current. For example, software can
read the temperature and use a calibrated look-up
table to determine a new value for the gate drive.
As an example, in noncontinuous conversion mode,
read temperature from remote diode 1 by writing to the
ADCCON register (0x62) with bit D1 set to 1. Wait for
BUSY to go high and then low. Read the ADC result
from the FIFO (0x80). The result bits D15–D12 = 0001
indicate the measurement source is the external tem-
perature sensor DXP1/DXN1, and bits D11–D3 indicate
two’s-complement temperature in degrees Celsius. Bits
D2, D1, and D0 are temperature subLSBs.
Gate voltage drive range must be previously deter-
mined during initialization by setting the coarse DAC1
high and low limits. Write a new value to FINETHRU1 to
immediately change the output GATE1 between the
high and low wiper limits based on the previous tem-
perature measurement.
The regulation software may also use the alarm thresh-
old limits to determine whether temperature and current
−×+×
VFINECODE VLOWCODE
DACREF DACREF
22
18 8
COMMAND
BYTE
DATA
WORD DESCRIPTION
0x64 0x0008 Bring the device out of shutdown mode.
0x64 0x0008 Set internal reference and both DAC channels on.
0x20 0x02A8 Set the channel 1 high-temperature threshold to +85°C.
0x22 0x0EC0 Set the channel 1 low-temperature threshold to -40°C.
0x24 0x02C1 Set the channel 1 high-current threshold to 4.3A for 50mΩ RSENSE, AvPGA = 2, and VREFADC = 2.5V.
0x26 0x0106 Set the channel 1 low-current threshold to 1.6A for 50mΩ RSENSE, AvPGA = 2, and VREFADC = 2.5V.
0x28 0x02A8 Set the channel 2 high-temperature threshold to +85°C.
0x2A 0x0EC0 Set the channel 2 low-temperature threshold to -40°C.
0x2C 0x02C1 Set the channel 2 high-current threshold to 4.3A for 50mΩ RSENSE, AvPGA = 2, and VREFADC = 2.5V.
0x2E 0x0106 Set the channel 2 low-current threshold to 1.6A for 50mΩ RSENSE, AvPGA = 2, and VREFADC = 2.5V.
0x30 0x000F Set AvPGA1 and AvPGA2 to 2, clock mode to 00 and ADC/DAC references to internal.
0x32 0x0000 Set ALARM, SAFE1, and SAFE2 to depend on nothing (POR).
0x60 0x0000 Set ALARM, SAFE1, and SAFE2 for push-pull/active-high (POR).
0x74 0x00CC Set coarse DAC1 high wiper to 204.
0x76 0x0066 Set coarse DAC1 low wiper to 102 (VGATE = 1.99V for MAX1385, VGATE = 3.98V for MAX1386).
0x7A 0x00CC Set coarse DAC2 high wiper to 204.
0x7C 0x0066 Set coarse DAC2 low wiper to 102 (VGATE = 1.99V for MAX1385, VGATE = 3.98V for MAX1386).
0x52 0x01FF Set fine DAC1 to midscale.
0x56 0x01FF Set fine DAC2 to midscale.
Table 27. Basic Software Initialization
TEMPERATURE SETTING TWO’S COMPLEMENT
-40°C 1110 1100 0000
-1.625°C 1111 1111 0011
0°C 0000 0000 0000
+27.125°C 0000 1101 1001
+105°C 0011 0100 1000
Table 26. Temperature-Threshold
Settings Examples
MAX1385/MAX1386
Dual RF LDMOS Bias Controllers
with I2C/SPI Interface
48 ______________________________________________________________________________________
limits are within the safe operating area. Configure the
ADC for continuous conversions to allow continuous
measurement and testing against configured alarm
thresholds. Connect SAFE_ to OPSAFE_ to immediately
force the gate drive to GATEGND in the event of an
alarm-related condition (current or temperature).
Triggering DAC Calibration
Performing the autocalibration routines requires use of
the internal ADC, the internal ALU, and can also
increase the power dissipation of the part. Tables 28
and 29 detail which commands trigger autocalibration
and which commands do not.
ACTION REQUIRED RECOMMENDED COMMAND SEQUENCE OTHER POSSIBLE COMMAND
SEQUENCES
Update fine DAC_ without triggering
autocalibration.
Write to FINE_. Write to LDAC to update fine
DAC_.
Write to FINETHRU_ to immediately
update fine DAC_.
Update high wiper coarse DAC_ without
triggering autocalibration.
Write to HIWIPE_ with HCAL set to 0. Write
to LDAC to update high wiper coarse DAC_.
Write to THRUHI_ to immediately
update high wiper coarse DAC_.
Update low wiper coarse DAC_ without
triggering autocalibration.
Write to LOWIPE_ with LCAL set to 0. Write
to LDAC to update low wiper coarse DAC_.
Write to THRULO_ to immediately
update low wiper coarse DAC_.
Immediately update fine DAC_ without
triggering autocalibration. Write to FINETHRU_. None.
Immediately update high wiper coarse
DAC_ without triggering autocalibration. Write to THRUHI_. None.
Immediately update low wiper coarse
DAC_ without triggering autocalibration. Write to THRULO_. None.
Update the high, low, and fine components
of DAC_ simultaneously without triggering
autocalibration.
Write to HIWIPE_, LOWIPE, and FINE_.
Write to LDAC to update DAC_. None.
Table 28. DAC Write Commands Without Autocalibration
0000 0000 0000
0000 0000 0001
0000 0000 0010
INPUT VOLTAGE (LSB)
1111 1111 1100
1111 1111 1110
1111 1111 1111
1111 1111 1101
FULL-SCALE TRANSITION
BINARY OUTPUT CODE
4093 4095
0123
0000 0000 0011
V
REFADC
V
REFADC
1 LSB =
V
REFADC
4096
1000 0000 0000
1000 0000 0001
1000 0000 0010
-256°C
TEMPERATURE (°C)
0000 0000 0001
0111 1111 1110
0111 1111 1111
1111 1111 1111
0000 0000 0000
0111 1111 1101
1 LSB = +0.125°C
OUTPUT CODE
0°C+255.875°C
Figure 25. ADC Transfer Function Figure 26. Temperature Transfer Function
MAX1385/MAX1386
Dual RF LDMOS Bias Controllers
with I2C/SPI Interface
______________________________________________________________________________________ 49
ACTION REQUIRED RECOMMENDED COMMAND
SEQUENCE
OTHER POSSIBLE COMMAND
SEQUENCES
Update fine DAC_ and trigger
autocalibration.
Write to FINECAL_. Autocalibration
begins after writing to FINECAL_. Write
to LDAC to update fine DAC_.
Write to FINECALTHRU_ to immediately
update fine DAC_.
Update high wiper coarse DAC_ and
trigger autocalibration.
Write to HIWIPE_ with HCAL set to 1.
Autocalibration begins after writing to
LDAC and high wiper coarse DAC_ is
updated thereafter.
None.
Update low wiper coarse DAC_ and trigger
autocalibration.
Write to LOWIPE_ with LCAL set to 1.
Autocalibration begins after writing to
LDAC and low wiper coarse DAC_ is
updated thereafter.
None.
Immediately update fine DAC_ and trigger
autocalibration. Write to FINECALTHRU_. None.
Immediately update high wiper coarse
DAC_ and trigger autocalibration.
This action is not possible. See the
recommended sequence above
“Update high wiper coarse DAC_ and
trigger autocalibration.”
None.
Immediately update low wiper coarse
DAC_ and trigger autocalibration.
This action is not possible. See the
recommended sequence “Update low
wiper coarse DAC_ and trigger
autocalibration.”
None.
Update the high, low, and fine components
of DAC_.
Write to HIWIPE_ with HCAL set to 1.
Write LOWIPE_ with LCAL set to 1. Write
to LDAC to update high and low wipers
with autocalibrated values. Write to
FINECALTHRU_ to trigger fine DAC_
autocalibration and update DAC_.
HIWIPE_ and LOWIPE_ can be written to in
any order but must be followed by LDAC
and then a fine DAC_ write (to
FINECALTHRU_ or FINECAL_ with another
LDAC). This ensures that the fine DAC_
autocalibration is run after the coarse
DAC_ autocalibration.
Table 29. DAC Write Commands with Autocalibration
MAX1385/MAX1386
Dual RF LDMOS Bias Controllers
with I2C/SPI Interface
50 ______________________________________________________________________________________
SCL SCL
SDA SDA/DIN
ALARM
SAFE1
SAFE2
DXP1
DXN1
DXP2
DXN2
*SELECT R
F
AND C
F
BASED ON DESIRED FILTER CUT-OFF FREQUENCY.
LIMIT R
F
TO MINIMIZE OFFSET ERRORS.
GATE1
GATE2
A0/CSB
A1/DOUT
A2/N.C.
OPSAFE1
OPSAFE2
BUSY
ADCIN1
ADCIN2
DGND
CNVST
(AT LDMOSFET)
(AT LDMOSFET)
+5V
DVDD GATEV
DD
AVDD REFDAC REFADC
CS1+
CS1-
CS2+
CS2-
GATEGNDAGND
PGAOUT2PGAOUT1
RF INPUT
DRAIN
SUPPLY
RF
OUTPUT
C
F
*
R
F
*
RF
OUTPUT
RF INPUT
DRAIN
SUPPLY
EXTERNAL
REFERENCE
5V
5V
MICROCONTROLLER
5V
MAX1385
MAX1386
SEL
R
F
*
C
F
*
Typical Operating Circuit (I2C Mode)
MAX1385/MAX1386
Dual RF LDMOS Bias Controllers
with I2C/SPI Interface
______________________________________________________________________________________ 51
N.C.
N.C.
CS1+
CS1-
CS2-
N.C.
CS2+
N.C.
OPSAFE2
GATE1
GATE2
OPSAFE1
A0/CSB
CNVST
SEL
ALARM
SAFE2
N.C.
REFDAC
DXN1
REFADC
DXP1
SAFE1
DGND
PGAOUT2
AVDD
N.C.
AGND
GATEVDD
GATEGND
AGND
ADCIN2
ADCIN1
DXN2
DXP2
BUSY
N.C.
A1/DOUT
SDA/DIN
SCL
N.C.
A2/N.C.
PGAOUT1
N.C.
N.C.
N.C.
DVDD
MAX1385
MAX1386
AGND
TOP VIEW
*EXPOSED PAD
*EXPOSED PAD INTERNALLY CONNECTED TO AGND
1234 5678910 11 12
36 35 34 33 32 31 30 29 28 27 26 25
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
TQFN
+
Pin Configuration Package Information
For the latest package outline information and land patterns, go
to www.maxim-ic.com/packages.
PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
48 TQFN-EP T4877-6 21-0044
MAX1385/MAX1386
Dual RF LDMOS Bias Controllers
with I2C/SPI Interface
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
52
____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600
© 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
Appendix: Recommended
Power-Up Code Sequence
The following section shows the recommended startup
code for the MAX1385. This code ensures clean startup
of the part, irrespective of power-supply ramp speed
and starts the device regulating to 312.5mV on both
channels. Change the THRUDAC writes to change the
voltage across the sense resistor. Note it should be run
after the power supplies have stabilized.
*Double reset. This ensures that the internal ROM is reset correctly after power-up and that the ROM data is latched correctly irre-
spective of power-supply ramp speed.
REGISTER
MNEMONIC
REGISTER
ADDRESS (hex)
CODE
WRITTEN NOTES
SHUT 0x64 0x0080 Removes the global power.
SHUT 0x64 0x0080
Powers up all parts of the MAX1385 and forces the internal reference to
remain powered. The internal oscillator is required for the subsequent
reset command.
SCLR 0x68 0x0100 Arms the full reset.
SCLR 0x68 0x0200 Completes the full reset.
SCLR 0x68 0x0100 Arms the full reset.*
SCLR 0x68 0x0200 Completes the full reset.*
SHUT 0x64 0x0080 Removes the global power.
SHUT 0x64 0x0080
Powers up all parts of the MAX1385 and forces the internal reference to
remain powered. The internal oscillator is required for the subsequent
reset command.
DCFIG 0x30 0x000A Selects internal references for both DAC and ADC.
PGACAL 0x4E 0x0002
Runs autocalibration on both PGA channels to set the input referred
offset to < 50µV. Busy goes low after approximately 30ms and then the
VGATE DACs can be set.
