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MOS INTEGRATED CIRCUIT
µ
PD3737
5150 PIXELS CCD LINEAR IMAGE SENSOR
DATA SHEET
Document No. S13158EJ4V0DS00 (4th edition)
Date Published February 2006 NS CP (N)
Printed in Japan
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all products and/or types are available in every country. Please check with an NEC Electronics
sales representative for availability and additional information.
1994
The mark <R> shows major revised points.
The revised points can be easily searched by copying an "<R>" in the PDF file and specifying it in the "Find what:" field.
DESCRIPTION
The
µ
PD3737 is a 5150-pixel high sensitivity CCD (Charge Coupled Device) linear image sensor which changes
optical images to electrical signal.
The
µ
PD3737 has high speed CCD register, so it is suitable for high resolution scanners and facsimiles which scan
high definition document at high speed.
FEATURES
• Valid photocell : 5150 pixels
• Photocell pitch : 7
µ
m
• High response sensitivity
• Peak response wavelength : 550 nm (green)
• Resolution : 16 dot/mm A3 (297 × 420 mm) size (shorter side)
24 dot/mm A4 (210 × 297 mm) size (shorter side)
• High speed scan : 252
µ
s/line
• Drive clock level : CMOS output under +5 V operation
• Data rate : 20 MHz Max.
• Power supply : +12 V
ORDERING INFORMATION
Part Number Package
µ
PD3737CY-A CCD linear image sensor 32-pin plastic DIP (10.16 mm (400))
Remark The
µ
PD3737CY-A is a lead-free product.
<R>
Data Sheet S13158EJ4V0DS
2
µ
PD3737
BLOCK DIAGRAM
4
32
28
5
10
23
24
Optical black 18 pixels, invalid photocell 2 pixels,
valid photocell 5150 pixels, invalid photocell 2 pixels
V
OD
V
OUT
R
AGND
9
22
2
AGND
1
φ
1L
φ
TG
2
φ
φ
2L
φ
φ
Data Sheet S13158EJ4V0DS 3
µ
PD3737
PIN CONFIGURATION (Top View)
CCD linear image sensor 32-pin plastic DIP (10.16 mm (400))
•
µ
PD3737CY-A
1
2
3
4
5
6
7
8
9
10
11
Output signal
No connection
Transfer gate clock
Shift register clock 1
No connection
No connection
No connection
Internal connection
No connection
No connection
Reset gate clockNo connection
Analog ground
No connection
Internal connection
Internal connection
Internal connection
No connection
Internal connection
5150 1
Internal connection
No connectionNo connection
Internal connection
No connection
Output drain voltage
No connection
No connection
Last stage shift register clock 2
Shift register clock 2
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Last stage shift register clock 1
Internal connection
Analog ground
NC
NC
NC
NC
V
OUT
NC
NC
IC
1L
φ
TG
φ
NC
NC
AGND
AGND
V
OD
IC
IC
IC
IC
NC
IC
R
φ
1
φ
NC
NC
NC
NC
NC
IC
IC
2L
φ
2
φ
Cautions 1. Leave pins 6, 7, 12, 13, 20, 21, 26, 27 (IC) unconnected.
2. Connect the No connection pins (NC) to GND.
Data Sheet S13158EJ4V0DS
4
µ
PD3737
PHOTOCELL STRUCTURE DIAGRAM
µ
8m
µ
m
2
µ
m
5
Channel stopper
Aluminum
shield
Data Sheet S13158EJ4V0DS 5
µ
PD3737
ABSOLUTE MAXIMUM RATINGS (TA = +25°C)
Parameter Symbol Ratings Unit
Output drain voltage VOD −0.3 to +15 V
Shift register clock voltage V
φ
1, V
φ
2 −0.3 to +8 V
Last stage shift register clock voltage V
φ
1L, V
φ
2L −0.3 to +8 V
Reset signal voltage V
φ
R −0.3 to +8 V
Transfer gate clock voltage V
φ
TG −0.3 to +8 V
Operating ambient temperature Note TA 0 to +60 °C
Storage temperature Tstg −40 to +70 °C
Note Use at the condition without dew condensation.
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any
parameter. That is, the absolute maximum ratings are rated values at which the product is on the
verge of suffering physical damage, and therefore the product must be used under conditions that
ensure that the absolute maximum ratings are not exceeded.
RECOMMENDED OPERATING CONDITIONS (TA = +25°C)
Parameter Symbol Min. Typ. Max. Unit
Output drain voltage VOD 11.4 12.0 12.6 V
Shift register clock high level V
φ
1_H, V
φ
2_H 4.5 5.0 5.5 V
Shift register clock low level V
φ
1_L, V
φ
2_L −0.3 0 +0.5 V
Last stage shift register clock high level V
φ
1LH, V
φ
2LH 4.5 5.0 5.5 V
Last stage shift register clock low level V
φ
1LL, V
φ
2LL −0.3 0 +0.5 V
Reset signal
φ
R high level V
φ
RH 4.5 5.0 5.5 V
Reset signal
φ
R low level V
φ
RL −0.3 0 +0.5 V
Transfer gate clock high level V
φ
TGH 4.5 V
φ
1_H
Note V
φ
1_H
Note V
Transfer gate clock low level V
φ
TGL −0.3 0 +0.5 V
Shift register clock amplitude V
φ
1_pp, V
φ
2_pp 4.5 5.0 5.8 V
Last stage shift register clock amplitude V
φ
1L_pp, V
φ
2L_pp 4.5 5.0 5.8 V
Reset signal amplitude V
φ
R_pp 4.5 5.0 5.8 V
Transfer gate clock amplitude V
φ
TG_pp 4.5 5.0 5.8 V
Data rate f
φ
R 0.5 1 20 MHz
Note When Transfer gate clock high level (V
φ
TGH) is higher than Shift register clock high level (V
φ
1_H), Image lag
can increase.
Remarks 1. Input reset signal
φ
R to pin 32 via capacitor (1000 pF ±20%, non polarity). Concerning the
connection method refer to APPLICATION CIRCUIT EXAMPLE.
2. Operating conditions of reset signal
φ
R is not the condition at device pins but the conditions of the
signal which applied to capacitor.
Data Sheet S13158EJ4V0DS
6
µ
PD3737
ELECTRICAL CHARACTERISTICS
TA = +25°C, VOD = 12 V, f
φ
1 = 0.5 MHz, data rate = 1 MHz, storage time = 10 ms, input signal clock = 5 Vp-p,
light source : 3200 K halogen lamp + C500 (infrared cut filter, t = 1 mm)
Parameter Symbol Test Conditions Min. Typ. Max. Unit
Saturation voltage Vsat 1.0 1.5 − V
Saturation exposure SE Daylight color fluorescent lamp − 0.2 − lx•s
Photo response non-uniformity PRNU VOUT = 500 mV − ±5 ±10 %
Average dark signal ADS Light shielding − 2.0 6.0 mV
Dark signal non-uniformity DSNU Light shielding − 6.0 12.0 mV
Power consumption PW − 100 200 mW
Output impedance ZO − 0.2 0.5 kΩ
Response RF Daylight color fluorescent lamp 6.0 7.5 9.0 V/lx•s
Response peak − 550 − nm
Image lag IL VOUT = 1.0 V − 0.3 1.0 %
Offset level Note 1 VOS 2.0 3.0 5.0 V
Output fall delay time Note 2 td Time from 90% to 10% of
φ
2L fall is 5 ns 21 23 25 ns
Register imbalance RI VOUT = 500 mV − 0 4.0 %
Total transfer efficiency TTE VOUT = 500 mV, 92 98 − %
data rate (f
φ
R1) = 20 MHz
Dynamic range DR1 Vsat/DSNU − 250 − times
Reset feed-through noise Note 1 RFTN Light shielding − 250 500 mV
Notes 1. Refer to TIMING CHART 2.
2. td is defined as a time from 10% of
φ
2L to 10% of VOUT, output after passing through two steps of emitter
follower in the APPLICATION CIRCUIT EXAMPLE.
INPUT PIN CAPACITANCE (TA = +25°C, VOD = 12 V)
Parameter Symbol Pin name Pin No. Min. Typ. Max. Unit
Shift register clock pin capacitance 1 C
φ
1
φ
1 24 440 550 660 pF
Shift register clock pin capacitance 2 C
φ
2
φ
2 10 440 550 660 pF
Last stage shift register clock pin capacitance 1 C
φ
1L
φ
1L 22 40 50 60 pF
Last stage shift register clock pin capacitance 2 C
φ
2L
φ
2L 9 40 50 60 pF
Reset gate clock pin capacitance C
φ
R
φ
R 32 8 10 12 pF
Transfer gate clock pin capacitance C
φ
TG
φ
TG 23 120 150 180 pF
Remark C
φ
1 and C
φ
2 show the equivalent capacity of the real drive including the capacity of between
φ
1 and
φ
2.
Data Sheet S13158EJ4V0DS 7
µ
PD3737
TIMING CHART 1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
5181
5182
5183
5184
5185
5186
φ
1L
φ
2L
φ
TG
φ
1
φ
2
φ
R
V
OUT
Optical black
(18 pixels)
Valid photocell
(5150 pixels)
Invalid photocell
(2 pixels)
Invalid photocell
(2 pixels)
Caution Input the
φ
R pulse continuously during the high level period of
φ
TG.
Data Sheet S13158EJ4V0DS
8
µ
PD3737
TIMING CHART 2
90%
t1
t5 t6
t4
t3
t
d
t2
t1’ t2’
90%
10%
10%
φ
1
φ
1L
φ
2
φ
2L
φ
R
V
OUT
90%
90%
10%
10%
10%
90%
10%
t4
t
d
10%
RFTN
V
OS
Symbol Min. Typ. Max. Unit
t1, t2 0 50 (150) ns
t1’, t2’ 0 5 (25) ns
t3 15 50 (500) ns
t4 2 20 (500) ns
t5, t6 0 20 (50) ns
Remark The MAX. in the table above shows the operation range in which the output characteristics are kept
almost enough for general purpose.
Data Sheet S13158EJ4V0DS 9
µ
PD3737
φ
TG,
φ
1,
φ
2 TIMING CHART
90%
t7 t8t9
t10 t11
10%
φ
1
φ
2
φ
TG
90%
Symbol Min. Typ. Max. Unit
t7, t8 0 50 (100) ns
t9 500 1000 10000 ns
t10, t11 0 100 10000 ns
Remark The MAX. in the table above shows the operation range in which the output characteristics are kept
almost enough for general purpose.
φ
1,
φ
2 CROSS POINTS
1
φ
2
φ
2.0 V or more 2.0 V or more
φ
1L,
φ
2 CROSS POINTS
2
φ
1L
φ
2.0 V or more 0.5 V or more
φ
1,
φ
2L CROSS POINTS
1
φ
2L
φ
2.0 V or more 0.5 V or more
Remark Adjust cross points (
φ
1,
φ
2), (
φ
1L,
φ
2) and (
φ
1,
φ
2L) with input resistance of each pin.
Data Sheet S13158EJ4V0DS
10
µ
PD3737
DEFINITIONS OF CHARACTERISTIC ITEMS
1. Saturation voltage : Vsat
Output signal voltage at which the response linearity is lost.
2. Saturation exposure : SE
Product of intensity of illumination (lx) and storage time (s) when saturation of output voltage occurs.
3. Photo response non-uniformity : PRNU
The peak/bottom ratio to the average output voltage of all the valid pixels calculated by the following formula.
PRNU (%) =
V
MAX.
or V
MIN.
n : Number of valid pixcels
V
j
: Output voltage of each pixel
Σ
j = 1
n
n
1V
j
× 100
− 1
V
MIN.
V
MAX.
Register Dark
DC level
Σ
j = 1
n
n
1V
j
4. Average dark signal : ADS
Average output signal voltage of all the valid pixels at light shielding. This is calculated by the following
formula.
ADS (mV) =
d
j
: Dark signal of valid pixel number j
5150
Σ
j = 1
5150
d
j
5. Dark signal non-uniformity : DSNU
The difference between ADS and voltage of the highest or lowest output pixel of all the valid pixels at light
shielding.
ADS
DSNU MAX.
DSNU MIN.
Register Dark
DC level
V
OUT
Data Sheet S13158EJ4V0DS 11
µ
PD3737
6. Output impedance : ZO
Impedance of the output pins viewed from outside.
7. Response : R
Output voltage divided by exposure (lx•s).
Note that the response varies with a light source (spectral characteristic).
8. Image lag : IL
The rate between the last output voltage and the next one after read out the data of a line.
V
OUT
TG
Light
V
OUT
ON OFF
V
1
φ
IL (%) = V
1
V
OUT
× 100
9. Register imbalance: RI
The rate of the difference between the averages of the output voltage of Odd and Even pixels, against the
average output voltage of all the valid pixels.
RI (%) =
2
n
j = 1
j = 1
n
2
(V
2j –1
–
V
2j
)
1
n
n
V
j
×100
∑
∑
n
V
j
: Number of valid pixels
: Output voltage of each pixel
Data Sheet S13158EJ4V0DS
12
µ
PD3737
STANDARD CHARACTERISTIC CURVES (Reference Value)
DARK OUTPUT TEMPERATURE
CHARACTERISTIC STORAGE TIME OUTPUT VOLTAGE
CHARACTERISTIC (T
A
= +25°C)
Operating Ambient Temperature T
A
(°C) Storage Time (ms)
8
4
2
1
0.5
0.25
0.1 100 20304050
Relative Output Voltage
Relative Output Voltage
2
1
0.2
0.11510
TOTAL SPECTRAL RESPONSE CHARACTERISTICS (without infrared cut filter) (T
A
= +25°C)
1200600400 1000800
0
20
40
60
80
100
Wavelength (nm)
Response Ratio (%)
Data Sheet S13158EJ4V0DS 13
µ
PD3737
APPLICATION CIRCUIT EXAMPLE
PD3737
µ
+12 V
µ
47 F/25 V
µ
0.1 F
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
2
Ω
10
Ω
10
Ω
10
Ω
2
Ω
51
Ω
51
Ω
47
Ω
1 k
Ω
4.7 k
Ω
1000 pF
2SA1206
2SC1842
NC
NC
NC
NC
V
OUT
NC
NC
IC
1L
φ
TG
φ
NC
NC
AGND
AGND
V
OD
IC
IC
IC
IC
NC
IC
R
φ
1
φ
NC
NC
NC
1
V
OUT
φ
NC
NC
IC
IC
µ
47 F/25 V
2L
φ
2
φ
2L
φ
2
φ
1L
φ
TG
φ
R
φ
Cautions 1. Leave pins 6, 7, 12, 13, 20, 21, 26, 27 (IC) unconnected.
2. Connect the No connection pins (NC) to GND.
Remark The inverters shown in the above application circuit example are the 74AC04.
Data Sheet S13158EJ4V0DS
14
µ
PD3737
PACKAGE DRAWING
55.2±0.5
54.8±0.5
12.6±0.5
9.05±0.3
9.25±0.3
4.1±0.5
1st valid pixel
4.9±0.3 1
44
32 17
16
1
2.0
46.7
2.54±0.25
0.46±0.1
1.02±0.15
(5.42)
4.21±0.5
4.55±0.5
(2.0)
2.45±0.3
0.25±0.05
10.16±0.20
2
3
5
10.16+0.70
−0.20
Name Dimensions Refractive index
Plastic cap 52.2×6.4×0.8 (0.7 ) 1.5
1 1st valid pixel The center of the pin1
2 The surface of the CCD chip The top of the cap
3 The bottom of the package The surface of the CCD chip
4 Mirror finishied surface
5 Thickness of mirror finished surface
32C-1CCD-PKG9-1
(Unit : mm)
CCD LINEAR IMAGE SENSOR 32-PIN PLASTIC DIP (10.16 mm (400) )
PD3737CY
µ
Data Sheet S13158EJ4V0DS 15
µ
PD3737
RECOMMENDED SOLDERING CONDITIONS
When soldering this product, it is highly recommended to observe the conditions as shown below.
If other soldering processes are used, or if the soldering is performed under different conditions, please make sure
to consult with our sales offices.
Type of Through-hole Device
µ
PD3737CY-A : CCD linear image sensor 32-pin plastic DIP (10.16 mm (400))
Process Conditions
Partial heating method Pin temperature : 350 °C or below, Heat time : 3 seconds or less (per pin)
Cautions 1. During assembly care should be taken to prevent solder or flux from contacting the glass
cap. The optical characteristics could be degraded by such contact.
2. Soldering by the solder flow method may have deleterious effects on prevention of glass cap
soiling and heat resistance. So the method cannot be guaranteed.
Data Sheet S13158EJ4V0DS
16
µ
PD3737
NOTES ON HANDLING THE PACKAGES
CLEANING THE PLASTIC CAP
DUST AND DIRT PROTECTING
MOUNTING OF THE PACKAGE
OPERATE AND STORAGE ENVIRONMENTS
Ethyl Alcohol
Methyl Alcohol
Isopropyl Alcohol
N-methyl Pyrrolidone
EtOH
MeOH
IPA
NMP
The optical characteristics of the CCD will be degraded if the cap is scratched during cleaning. Don’t either
touch plastic cap surface by hand or have any object come in contact with plastic cap surface. Should dirt
stick to a plastic cap surface, blow it off with an air blower. For dirt stuck through electricity ionized air is
recommended. And if the plastic cap surface is grease stained, clean with our recommended solvents.
Care should be taken when cleaning the surface to prevent scratches.
We recommend cleaning the cap with a soft cloth moistened with one of the recommended solvents below.
Excessive pressure should not be applied to the cap during cleaning. If the cap requires multiple cleanings it is
recommended that a clean surface or cloth be used.
The following are the recommended solvents for cleaning the CCD plastic cap.
Use of solvents other than these could result in optical or physical degradation in the plastic cap.
Please consult your sales office when considering an alternative solvent.
The application of an excessive load to the package may cause the package to warp or break, or cause chips
to come off internally. Particular care should be taken when mounting the package on the circuit board. Don't
have any object come in contact with plastic cap. You should not reform the lead frame. We recommended to
use a IC-inserter when you assemble to PCB.
Also, be care that the any of the following can cause the package to crack or dust to be generated.
1. Applying heat to the external leads for an extended period of time with soldering iron.
2. Applying repetitive bending stress to the external leads.
3. Rapid cooling or heating
Operate in clean environments. CCD image sensors are precise optical equipment that should not be subject
to mechanical shocks. Exposure to high temperatures or humidity will affect the characteristics. So avoid
storage or usage in such conditions.
Keep in a case to protect from dust and dirt. Dew condensation may occur on CCD image sensors when the
devices are transported from a low-temperature environment to a high-temperature environment. Avoid such
rapid temperature changes.
For more details, refer to our document "Review of Quality and Reliability Handbook" (C12769E)
1
2
ELECTROSTATIC BREAKDOWN
CCD image sensor is protected against static electricity, but destruction due to static electricity is sometimes
detected. Before handling be sure to take the following protective measures.
1. Ground the tools such as soldering iron, radio cutting pliers of or pincer.
2. Install a conductive mat or on the floor or working table to prevent the generation of static electricity.
3. Either handle bare handed or use non-chargeable gloves, clothes or material.
4. Ionized air is recommended for discharge when handling CCD image sensor.
5. For the shipment of mounted substrates, use box treated for prevention of static charges.
6. Anyone who is handling CCD image sensors, mounting them on PCBs or testing or inspecting PCBs on
which CCD image sensors have been mounted must wear anti-static bands such as wrist straps and ankle
straps which are grounded via a series resistance connection of about 1 MΩ.
4
3
RECOMMENDED SOLVENTS
Solvents Symbol
Data Sheet S13158EJ4V0DS 17
µ
PD3737
[MEMO]
Data Sheet S13158EJ4V0DS
18
µ
PD3737
[MEMO]
Data Sheet S13158EJ4V0DS 19
µ
PD3737
1
2
3
4
VOLTAGE APPLICATION WAVEFORM AT INPUT PIN
Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the
CMOS device stays in the area between V
IL
(MAX) and V
IH
(MIN) due to noise, etc., the device may
malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed,
and also in the transition period when the input level passes through the area between V
IL
(MAX) and
V
IH
(MIN).
HANDLING OF UNUSED INPUT PINS
Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is
possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS
devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed
high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to V
DD
or GND
via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must
be judged separately for each device and according to related specifications governing the device.
PRECAUTION AGAINST ESD
A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as
much as possible, and quickly dissipate it when it has occurred. Environmental control must be
adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that
easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static
container, static shielding bag or conductive material. All test and measurement tools including work
benches and floors should be grounded. The operator should be grounded using a wrist strap.
Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for
PW boards with mounted semiconductor devices.
STATUS BEFORE INITIALIZATION
Power-on does not necessarily define the initial status of a MOS device. Immediately after the power
source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does
not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the
reset signal is received. A reset operation must be executed immediately after power-on for devices
with reset functions.
POWER ON/OFF SEQUENCE
In the case of a device that uses different power supplies for the internal operation and external
interface, as a rule, switch on the external power supply after switching on the internal power supply.
When switching the power supply off, as a rule, switch off the external power supply and then the
internal power supply. Use of the reverse power on/off sequences may result in the application of an
overvoltage to the internal elements of the device, causing malfunction and degradation of internal
elements due to the passage of an abnormal current.
The correct power on/off sequence must be judged separately for each device and according to related
specifications governing the device.
INPUT OF SIGNAL DURING POWER OFF STATE
Do not input signals or an I/O pull-up power supply while the device is not powered. The current
injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and
the abnormal current that passes in the device at this time may cause degradation of internal elements.
Input of signals during the power off state must be judged separately for each device and according to
related specifications governing the device.
NOTES FOR CMOS DEVICES
5
6
µ
PD3737
The information in this document is current as of February, 2006. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC Electronics data
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(Note)
•
•
•
•
•
•
M8E 02. 11-1
(1)
(2)
"NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its
majority-owned subsidiaries.
"NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as
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"Standard":
"Special":
"Specific":
