UL62H1616AJA15G1 - Alliance Memory, Inc.

1 October 20, 2003

UL62H1616A

Preliminary

LB GA0 A1 A2 n.c.

DQ8 UB A3 A4 EDQ0

DQ9 DQ10 A5 A6 DQ1 DQ2

VSS DQ11 n.c. A7 DQ3 VCC

VCC DQ12 n.c. n.c. DQ4 VSS

DQ14 DQ13 A14 A15 DQ5 DQ6

DQ15 n.c. A12 A13 W DQ7

n.c. A8 A9 A10 A11 n.c.

!65536 x 16 bit static CMOS RAM

!15, 20 and 35 ns Access Time

!Common data inputs and

data outputs

!Three-state outputs

!Standby current < 150 µA

at 125°C

!TTL/CMOS-compatible

!Power supply voltage 3.3 V

!Operating temperature range

K-Type:-40 °C to 85 °C

A-Type:-40 °C to 125 °C

!QS 9000 Quality Standard

!ESD protection > 2000 V

(MIL STD 883C M3015.7)

!Latch-up immunity >100 mA

!Package: TSOP II 44 (400 mil)

The UL62H1616A is a static RAM

manufactured using a CMOS pro-

cess technology with the following

operating modes:

- Lower / Upper Byte Read

- Word Read

- Lower / Upper Byte Write

- Word Write

- Standby

- Data Retention

The memory array is based on a

6-Transistor cell.

The circuit is activated by the fal-

ling edge of E. The address and

control inputs open simultaneously.

According to the information of W

and G, the data inputs, or outputs,

are active. During the active state

E = L and W = H each address

change leads to a new Read cycle.

In a Read cycle, the data outputs

are activated by the falling edge of

G. If LB = L the data lower byte will

be available at the outputs DQ0-

DQ7, on UB = L the data upper

byte appear at the outputs DQ8-

DQ15. After the address change,

the data outputs go High-Z until the

new information is available. The

data outputs have no preferred

state. The Read cycle is finished by

the falling edge of W, or by the

rising edge of E, respectively.

Data retention is guaranteed down

to 2 V. With the exception of E, all

inputs consist of NOR gates, so

that no pull-up/pull-down resistors

are required.

Low Voltage Automotive Fast 64K x 16 SRAM

Pin Configuration

Top View

Signal Name Signal Description

A0 - A15 Address Inputs

DQ0 - DQ15 Data In/Out

EChip Enable

GOutput Enable

WWrite Enable

UB Upper Byte Enable

LB Lower Byte Enable

VCC Power Supply Voltage

VSS Ground

n.c. not connected

Pin Description

VCC

2A3 A6

4A1 G

5A0 UB

3A2 A7

7DQ0

8DQ1

DQ15

12VSS

9DQ2

DQ9

10DQ3

DQ8

11VCC

n.c.

13DQ4

14DQ5

A10

SOJ

DQ7

A15

A14

A13

A12

n.c.

DQ6

DQ14

DQ13

DQ12

VSS

DQ11

DQ10

n.c.

A11

Features Description

TSOPII

Top View

BGA

2 October 20, 2003

UL62H1616A Preliminary

*H or L

Operating Mode E W G LB UB DQ0-DQ7 DQ8-DQ15

Standby/not selected H**** High-Z High-Z

Internal Read

L H H * * High-Z High-Z

L * * H H High-Z High-Z

Lower Byte Read L H L L H Data Outputs Low-Z High-Z

Upper Byte Read L H L H L High-Z Data Outputs Low-Z

Word Read L H L L L Data Outputs Low-Z Data Outputs Low-Z

Lower Byte Write L L * L H Data Inputs High-Z High-Z

Upper Byte Write L L * H L High-Z Data Inputs High-Z

Word Write L L * L L Data Inputs High-Z Data Inputs High-Z

Truth Table

Block Diagram

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

VCC VSS W GE

Row Address

Inputs

Column Address

Inputs

Address

Change

Detector

Column Decoder Row Decoder

Sense Amplifier/

Write Control Logic

Clock

Generator

Common Data I/O

Memory Cell

Array

512 Rows x

128 x 16 Columns

A10

A11

A12

A13

A14

A15

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

UB LB

3 October 20, 2003

UL62H1616A

Preliminary

aStresses greater than those listed under „Absolute Maximum Ratings“ may cause permanent damage to the device. This is a stress rating

only, and functional operation of the device at condition above those indicated in the operational sections of this specification is not implied.

Exposure to absolute maximum rating conditions for extended periods may affect reliability

bMaximum voltage is 4.6 V

cNot more than 1 output should be shorted at the same time. Duration of the short circuit should not exceed 30 s.

Absolute Maximum Ratings a Symbol Min. Max. Unit

Power Supply Voltage VCC -0.3 4.6 V

Input Voltage VI-0.5 VCC + 0.5 bV

Output Voltage VO-0.5 VCC + 0.5 bV

Power Dissipation PD-1W

Operating Temperature K-Type

A-Type

Ta-40

-40

125

°C

Storage Temperature Tstg -65 150 °C

Output Short-Circuit Current

at VCC = 3.3 V and VO = 0 V c| IOS |100mA

Characteristics

All voltages are referenced to VSS = 0 V (ground).

All characteristics are valid in the power supply voltage range and in the operating temperature range specified.

Dynamic measurements are based on a rise and fall time of ≤ 5 ns, measured between 10 % and 90 % of VI, as well as

input levels of VIL = 0 V and VIH = 2.5 V. The timing reference level of all input and output signals is 1.5 V,

with the exception of the tdis-times and ten-times, in which cases transition is measured ±200 mV from steady-state voltage.

d-2 V at Pulse Width 10 ns

Recommended

Operating Conditions Symbol Conditions Min. Max. Unit

Power Supply Voltage VCC 3.0 3.6 V

Input Low Voltage dVIL -0.3 0.8 V

Input High Voltage VIH 2.0 VCC + 0.3 V

4 October 20, 2003

UL62H1616A Preliminary

e This parameter is guaranteed, but not tested.

Electrical Characteristics Symbol Conditions

15 20 35

Unit

Min. Max. Min. Max. Min. Max.

Supply Current -

Operating Mode

Supply Current -

Standby Mode

(CMOS level)

Supply Current -

Standby Mode

(LVTTL level)

ICC(OP)

ICC(SB)

ICC(SB)1

VCC

VIL

VIH

tcW

VCC

K-Type

A-Type

VCC

K-Type

A-Type

= 3.6 V

= 0.8 V

=2.0 V

= 15 ns

= 20 ns

= 35 ns

= 55 ns

= 70 ns

=3.6 V

= VCC - 0.2 V

= 3.6 V

= 2.0 V

55 e

40 e

30 e

20 e

1000

40 e

30 e

20 e

1000

30 e

20 e

100

150

µA

Output High Voltage

Output Low Voltage

VOH

VOL

VCC

IOH

VCC

IOL

= 3.0 V

= -0.5 mA

=3.0 V

=0.5 mA

2.2

0.4

2.2

0.4

2.2

0.4

Input High Leakage Current

Input Low Leakage Current

IIH

IIL

VCC

VIH

VCC

VIL

= 3.6 V

= 0 V

-2

2µA

µA

Output High Current

Output Low Current

IOH

IOL

VCC

VOH

VCC

VOL

=3.0 V

=2.2 V

=3.0 V

=0.4 V

0.5

-0.5

0.5

-0.5

0.5

-0.5 mA

Output Leakage Current

High at Three-State Outputs

Low at Three-State Outputs

IOHZ

IOLZ

VCC

VOH

VCC

VOL

=3.6 V

=0 V

-2

2µA

µA

5 October 20, 2003

UL62H1616A

Preliminary

Switching Characteristics

Read Cycle

Symbol 15 20 35

Unit

Alt. IEC Min.

Max.

Min.

Max.

Min.

Max.

Read Cycle Time tRC tcR 15 20 35 ns

Address Access Time to Data Valid tAA ta(A) 15 20 35 ns

Chip Enable Access Time to Data Valid tACE ta(E) 15 20 35 ns

G LOW to Data Valid tOE ta(G) 7915ns

LB, UB LOW to Data Valid tBta(B) 7915ns

E HIGH to Output in High-Z tHZCE tdis(E) 7812ns

G HIGH to Output in High-Z tHZOE tdis(G) 7812ns

LB, UB HIGH to Output in High-Z tHZB tdis(B) 7812ns

E LOW to Output in Low-Z tLZCE ten(E) 445ns

G LOW to Output in Low-Z tLZOE ten(G) 000ns

LB, UB LOW to Output in Low-Z tLZB ten(B) 000ns

Output Hold Time from Address Change tOH tv(A) 333ns

E LOW to Power-Up Time tPU 000ns

E HIGH to Power-Down Time tPD 15 20 35 ns

Switching Characteristics

Write Cycle

Symbol 15 20 35

Unit

Alt. IEC Min.

Max.

Min.

Max.

Min.

Max.

Write Cycle Time tWC tcW 15 20 35 ns

Write Pulse Width tWP tw(W) 10 12 20 ns

Write Setup Time tWP tsu(W) 10 12 20 ns

Address Setup Time tAS tsu(A) 000ns

Address Valid to End of Write tAW tsu(A-WH) 10 12 20 ns

Chip Enable Setup Time tCW tsu(E) 10 12 25 ns

Byte Enable Setup Time tBW tsu(B) 10 12 25 ns

Pulse Width Chip Enable to End of Write tCW tw(E) 10 12 25 ns

Pulse Width Byte Enable to End of Write tBW tw(B) 10 12 25 ns

Data Setup Time tDS tsu(D) 7915ns

Data Hold Time tDH th(D) 000ns

Address Hold from End of Write tAH th(A) 000ns

W LOW to Output in High-Z tHZWE tdis(W) 7815ns

G HIGH to Output in High-Z tHZOE tdis(G) 7812ns

W HIGH to Output in Low-Z tLZWE ten(W) 333ns

G LOW to Output in Low-Z tLZOE ten(G) 000ns

6 October 20, 2003

UL62H1616A Preliminary

Data Retention Mode

E - controlled

Data Retention

3.0 V

tsu(DR) trec

VCC

VCC(DR) ≥ 1.5 V

0 V

2.0 V

VCC(DR) - 0.2 V ≤ VE(DR) ≤ VCC(DR) + 0.3 V

Data Retention

Characteristics

Symbol

Conditions Min. Typ. Max. Unit

Alt. IEC

Data Retention Supply Voltage VCC(DR) 1.5 3.6 V

Data Retention Supply Current ICC(DR) VCC(DR) = 1.5 V

VE = VCC(DR) - 0.2 V

30 µA

Data Retention Setup Time tCDR tsu(DR) See Data Retention

Waveforms (above)

0ns

Operating Recovery Time tRtrec tcR ns

Test Configuration for Functional Check

DQ0

DQ1

DQ2

DQ3

DQ4

DQ5

DQ6

DQ7

DQ8

DQ9

DQ10

DQ11

DQ12

DQ13

DQ14

DQ15

VIH

VIL

VSS

VCC

3.3 V

481

255

30 pF1)

Input level according to the

relevant test measurement

Simultaneous measure-

ment of all 16 output pins

A10

A11

A12

A13

A14

A15

1) In measurement of tdis(E),tdis(W), ten(E), ten(W), ten(G) the capacitance is 5 pF.

7 October 20, 2003

UL62H1616A

Preliminary

Capacitance Conditions Symbol Min. Max. Unit

Input Capacitance VCC

= 3.3 V

= VSS

= 1 MHz

= 25 °C

CI7pF

Output Capacitance Co7pF

IC Code Numbers

UL62H1616A TA15

Type

Package

T = TSOP II 44 (400 mil)

J = SOJ 44 (400 mil) f

K = BGA 48 (6 x 8) f

Operating Temperature Range

K = -40 to 85 °C

A = -40 to 125 °C

Access Time

15 = 15 ns

20 = 20 ns

35 = 35 ns

f on special request

The date of manufacture is given by the last 4 digits of the third line of the mark, the first 2 digits indicating the year,

and the last 2 digits the calendar week.

Assembly location and trace code are shown in line 4.

All pins not under test must be connected with ground by capacitors.

Internal Code

8 October 20, 2003

UL62H1616A Preliminary

tPU

tdis(G)

tdis(E)

tcR

Previous Data Valid Output Data Valid

Address Valid

tsu(A)

High-Z

ten(E)

ten(G)

ta(G)

ta(E)

Read Cycle 1: Ai-controlled (during Read Cycle : E = G = VIL, W = VIH)

Read Cycle 2: G-, E-, LB-, UB-controlled (during Read Cycle: W = VIH)

ta(A)

tcR

tv(A)

DQi

Output

DQi

Output

tPD

ICC(OP)

ICC(SB)

50 % 50 %

Output Data Valid

tdis(B)

ten(B)

ta(B)

LB, UB

Write Cycle1: W-controlled

th(D)

LB, UB

DQi

Output

tcW

tsu(E) th(A)

tw(W)

tsu(A) tsu(D)

tdis(W) ten(W)

Address Valid

High-Z

Input Input Data Valid

tsu(B)

tsu(A-WH)

9 October 20, 2003

UL62H1616A

Preliminary

Write Cycle 2: E-controlled

Input Data Valid

tsu(A)

th(D)

DQi

Input

DQi

Output

tcW

tw(E) th(A)

tsu(W)

tsu(D)

tdis(W)

en(E)

High-Z

Address Valid

tsu(B)

LB, UB

tdis(G)

Write Cycle 3: LB-, UB-controlled

Input Data Valid

tsu(A)

th(D)

DQi

Input

DQi

Output

tcW

tw(B) th(A)

tsu(W)

tsu(D)

tdis(W)

en(B)

High-Z

Address Valid

tsu(E)

LB, UB

tdis(G)

L- to H-level

undefined H- to L-level

The information describes the type of component and shall not be considered as assured characteristics.Terms of

delivery and rights to change design reserved.

Zentrum Mikroelektronik Dresden AG

Grenzstraße 28 • D-01109 Dresden • P. O. B. 80 01 34 • D-01101 Dresden • Germany

Phone: +49 351 8822 306 • Fax: +49 351 8822 337 • Email: memory@zmd.de • http://www.zmd.de

October 20, 2003

UL62H1616A

Preliminary

LIFE SUPPORT POLICY

ZMD products are not designed, intended, or authorized for use as components in systems intended for surgical

implant into the body, or other applications intended to support or sustain life, or for any other application in which

the failure of the ZMD product could create a situation where personal injury or death may occur.

Components used in life-support devices or systems must be expressly authorized by ZMD for such purpose.

LIMITED WARRANTY

The information in this document has been carefully checked and is believed to be reliable. However Zentrum

Mikroelektronik Dresden AG (ZMD) makes no guarantee or warranty concerning the accuracy of said information

and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon it.

The information in this document describes the type of component and shall not be considered as assured charac-

teristics.

ZMD does not guarantee that the use of any information contained herein will not infringe upon the patent, trade-

mark, copyright, mask work right or other rights of third parties, and no patent or licence is implied hereby. This

document does not in any way extent ZMD’s warranty on any product beyond that set forth in its standard terms and

conditions of sale.

ZMD reserves terms of delivery and reserves the right to make changes in the products or specifications, or both,

presented in this publication at any time and without notice.