ADS5281IPFPR - Texas Instruments

12-Bit

ADC

PLL

Serializer

1xADCLK

6xADCLK

IN1P

IN1N

OUT1P

OUT1N

LCLKP

LCLKN

ADCLKP

ADCLKN

12xADCLK

12-Bit

ADC Serializer

Digital

Reference

IN8P

IN8N

REFT

INT/EXT

REFB

VCM

OUT8P

OUT8N

ISET

Registers

SDATA

RESET

SCLK

ADC

Control

Clock

Buffer

(ADCLK)

CLKP

(AVSS)

CLKN

AVDD

(3.3V)

LVDD

(1.8V)

Power-

Down

TestPatterns

DriveCurrent

OutputFormat

DigitalGain

(0dBto12dB)

Channels

2to7

ADS5281

ADS5282

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SBAS397I –DECEMBER 2006–REVISED JUNE 2012

12-Bit Octal-Channel ADC Family Up to 65MSPS

Check for Samples: ADS5281,ADS5282

1FEATURES DESCRIPTION

The ADS528x is a family of high-performance, low-

234• Speed and Resolution Grades: power, octal channel analog-to-digital converters

– ADS5281: 12-bit, 50MSPS (ADCs). Available in either a 9mm × 9mm QFN

– ADS5282: 12-bit, 65MSPS package or an HTQFP-80 package, with serialized

low-voltage differential signaling (LVDS) outputs and

• Power Dissipation: a wide variety of programmable features, the

– 48mW/Channel at 30MSPS ADS528x is highly customizable for a diversity of

– 55mW/Channel at 40MSPS applications and offers an unprecedented level of

system integration. An application note, XAPP774

– 64mW/Channel at 50MSPS (available at www.xilinx.com), describes how to

– 77mW/Channel at 65MSPS interface the serial LVDS outputs of TI's ADCs to

• 70dBFS SNR at 10MHz IF Xilinx®field-programmable gate arrays (FPGAs). The

ADS528x family is specified over the industrial

• Analog Input Full-Scale Range: 2VPP temperature range of –40°C to +85°C.

• Low-Frequency Noise Suppression Mode

• 6dB Overload Recovery In One Clock

• External and Internal (Trimmed) Reference

• 3.3V Analog Supply, 1.8V Digital Supply

• Single-Ended or Differential Clock:

– Clock Duty Cycle Correction Circuit (DCC)

• Programmable Digital Gain: 0dB to 12dB

• Serialized DDR LVDS Output

• Programmable LVDS Current Drive, Internal

Termination

• Test Patterns for Enabling Output Capture

• Straight Offset Binary or Two's Complement

Output

• Package Options:

– 9mm × 9mm QFN-64

– HTQFP-80 PowerPAD™ Compatible with

ADS527x Family

APPLICATIONS

• Medical Imaging

• Wireless Base-Station Infrastructure

• Test and Measurement Instrumentation

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2PowerPAD is a trademark of Texas Instruments, Inc.

3Xilinx is a registered trademark of Xilinx, Inc.

4All other trademarks are the property of their respective owners.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

ADS5281

ADS5282

SBAS397I –DECEMBER 2006–REVISED JUNE 2012

www.ti.com

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

RELATED PRODUCTS

MODEL RESOLUTION (BITS) SAMPLE RATE (MSPS) CHANNELS

ADS5281 12 50 8

ADS5282 12 65 8

ADS5287 10 65 8

ADS5270 12 40 8

ADS5271 12 50 8

ADS5272 12 65 8

ADS5273 12 70 8

ADS5242 12 65 4

Table 1. ORDERING INFORMATION(1) (2)

SPECIFIED

PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT

PRODUCT PACKAGE-LEAD DESIGNATOR RANGE MARKING NUMBER MEDIA, QUANTITY(3)

ADS5281IPFP Tray

HTQFP-80 PFP ADS5281I

(PowerPAD) ADS5281PFPR Tape and Reel

ADS5281 –40°C to +85°C ADS5281IRGCT Tape and Reel

QFN-64 RGC AZ5281 ADS5281IRGCR Tape and Reel

ADS5282IRGCT Tape and Reel

ADS5282 QFN-64 RGC –40°C to +85°C AZ5282 ADS5282IRGCR Tape and Reel

(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

(2) These devices meet the following planned eco-friendly classification:

Green (RoHS and No Sb/Br): Texas Instruments defines Green to mean Pb-free (RoHS compatible) and free of bromine (Br)- and

antimony (Sb)-based flame retardants. Refer to the Quality and Lead-Free (Pb-Free) Data web site for more information. These devices

have a Cu NiPdAu lead/ball finish.

(3) Refer to the Package Option Addendum at the end of this document for specific transport media and quantity information.

ABSOLUTE MAXIMUM RATINGS(1)

Over operating free-air temperature range, unless otherwise noted. ADS528x UNIT

Supply voltage range, AVDD –0.3 to +3.9 V

Supply voltage range, LVDD –0.3 to +2.2 V

Voltage between AVSS and LVSS –0.3 to +0.3 V

External voltage applied to REFTpin –0.3 to +3 V

External voltage applied to REFBpin –0.3 to +2 V

Voltage applied to analog input pins –0.3 to minimum [3.6, (AVDD + 0.3)] V

Voltage applied to digital input pins –0.3 to minimum [3.9, (AVDD + 0.3)] V

Peak solder temperature +260 °C

Junction temperature +125 °C

Storage temperature range –65 to +150 °C

(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may

degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond

those specified is not supported.

ADS5281

ADS5282

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SBAS397I –DECEMBER 2006–REVISED JUNE 2012

RECOMMENDED OPERATING CONDITIONS(1)

ADS528x

PARAMETER MIN TYP MAX UNIT

SUPPLIES, ANALOG INPUTS, AND REFERENCE VOLTAGES

AVDD Analog supply voltage 3.0 3.3 3.6 V

LVDD Digital supply voltage 1.7 1.8 1.9 V

Differential input voltage range 2 VPP

Input common-mode voltage VCM ± 0.05 V

REFTExternal reference mode 2.5 V

REFBExternal reference mode 0.5 V

CLOCK INPUTS

ADCLK input sample rate 1/ tC10 50, 65 MSPS

Input clock amplitude differential (VCLKP–VCLKN) peak-to-peak

Sine wave, ac-coupled 3.0 VPP

LVPECL, ac-coupled 1.6 VPP

LVDS, ac-coupled 0.7 VPP

Input clock CMOS, single-ended (VCLKP)

VIL 0.6 V

VIH 2.2 V

Input clock duty cycle 50 %

DIGITAL OUTPUTS

ADCLKPand ADCLKNoutputs (LVDS) 10 1x (sample rate) 50, 65 MHz

LCLKPand LCLKNoutputs (LVDS) 60 6x (sample rate) 300, 390 MHz

CLOAD Maximum external capacitance from each pin to LVSS 5 pF

RLOAD Differential load resistance between the LVDS output pairs 100 Ω

TAOperating free-air temperature –40 +85 °C

(1) All conditions are common to the ADS528x family.

INITIALIZATION REGISTERS

After the device has been powered up, the following registers must be written to (in the exact order listed below) through the

serial interface as part of an initialization sequence.(1)

ADDRESS (hex) DATA (hex)

Initialization Register 1(1) 03 0002

Initialization Register 2(1) 01 0010

Initialization Register 3(1) C7 8001

Initialization Register 4(1) DE 01C0

(1) It is no longer necessary to write these initialization registers. However, customers who have already included them in their software can

continue to use them. Programming these registers does not affect device performance.

If the analog input is ac-coupled, the following registers must be written to in the order listed below.

ADDRESS (hex) DATA (hex)

Initialization Register 1 01 0010

Initialization Register 5 E2 00C0

To disable the PLL configuration switching (especially useful in systems where a system-level timing calibration is done once

after power-up), the following registers must be written to in the order listed below. Also, see section PLL Operation Across

Sampling Frequency.ADDRESS (hex) DATA (hex)

For 10 ≤Fs ≤25 (1) E3 0060

For 15 ≤Fs = ≤45 (1) E3 00A0

(1) where Fs = sampling clock frequency

ADS5281

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SBAS397I –DECEMBER 2006–REVISED JUNE 2012

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DIGITAL CHARACTERISTICS

DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic level

'0' or '1'. At CLOAD = 5pF(1), IOUT = 3.5mA(2), RLOAD = 100Ω(2), and no internal termination, unless otherwise noted.

ADS528x

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

DIGITAL INPUTS

High-level input voltage 1.4 V

Low-level input voltage 0.3 V

High-level input current 33 μA

Low-level input current –33 μA

Input capacitance 3 pF

LVDS OUTPUTS

High-level output voltage 1375 mV

Low-level output voltage 1025 mV

Output differential voltage, |VOD| 350 mV

VOS output offset voltage Common-mode voltage of OUTPand OUTN1200 mV

Output capacitance inside the device, from either

Output capacitance 2 pF

output to ground

(1) CLOAD is the effective external single-ended load capacitance between each output pin and ground.

(2) IOUT refers to the LVDS buffer current setting; RLOAD is the differential load resistance between the LVDS output pair.

ADS5281

ADS5282

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SBAS397I –DECEMBER 2006–REVISED JUNE 2012

ELECTRICAL CHARACTERISTICS(1)

Typical values at +25°C. Minimum and maximum values are measured across the specified temperature range of TMIN =

–40°C to TMAX = +85°C, AVDD = 3.3V, LVDD = 1.8V, clock frequency = 10MSPS to 65MSPS, 50% clock duty cycle, –1dBFS

differential analog input, internal reference mode, ISET resistor = 56.2kΩ, and LVDS buffer current setting = 3.5mA, unless

otherwise noted. ADS528x

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

INTERNAL REFERENCE VOLTAGES

VREFB Reference bottom 0.5 V

VREFT Reference top 2.5 V

VREFT – VREFB 1.95 2.0 2.05 V

VCM Common-mode voltage (internal) 1.425 1.5 1.575 V

VCM output current ±2 mA

EXTERNAL REFERENCE VOLTAGES

VREFB Reference bottom 0.4 0.5 0.6 V

VREFT Reference top 2.4 2.5 2.6 V

VREFT – VREFB 1.9 2.0 2.1 V

ANALOG INPUT

Differential input voltage range 2.0 VPP

Differential input capacitance 3 pF

Analog input bandwidth 520 MHz

Analog input common-mode range DC-coupled input VCM ± 0.05 V

Per input pin per MSPS of sampling μA/MHz

Analog input common-mode current 2.5

speed per pin

Recovery from 6dB overload to within 1%

Voltage overload recovery time 1 Clock cycle

accuracy

Standard deviation seen on a periodic

Voltage overload recovery repeatability first data within full-scale range in a 6dB 1 LSB

overloaded sine wave

DC ACCURACY

Offset error –1.25 ±0.2 +1.25 %FS

Offset error temperature coefficient(2) ±5 ppm/°C

Channel gain error Excludes error in internal reference –0.8 %FS

Channel gain error temperature Excludes temperature coefficient of ±10 ppm/°C

coefficient internal reference

Internal reference error temperature ±15 ppm/°C

coefficient(3)

DC PSRR DC power-supply rejection ratio(4) 1.5 mV/V

POWER-DOWN MODES

Power in complete power-down mode 45 mW

Power in partial power-down mode Clock at 65MSPS 135 mW

Power with no clock 88 mW

DYNAMIC PERFORMANCE

5MHz full-scale signal applied to seven

Crosstalk channels, measurement taken on channel –90 dBc

with no input signal

Two-tone, third-order intermodulation f1= 9.5MHz at –7dBFs –92 dBFS

distortion f2= 10.2MHz at –7dBFs

(1) All characteristics are common for the ADS528x family.

(2) The offset temperature coefficient in ppm/°C is defined as (O1– O2) × 106/(T1– T2)/4096, where O1and O2are the offset codes in LSB

at the two extreme temperatures, T1and T2.

(3) The internal reference temperature coefficient is defined as (REF1– REF2) × 106/(T1– T2)/2, where REF1and REF2are the internal

reference voltages (VREFT – VREFB) at the two extreme temperatures, T1and T2.

(4) DC PSRR is defined as the ratio of the change in the ADC output (expressed in mV) to the change in supply voltage (in volts).

ADS5281

ADS5282

SBAS397I –DECEMBER 2006–REVISED JUNE 2012

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ELECTRICAL CHARACTERISTICS (BY DEVICE)(1)

Typical values at +25°C. Minimum and maximum values are measured across the specified temperature range of TMIN =

–40°C to TMAX = +85°C, AVDD = 3.3V, LVDD = 1.8V, clock frequency = 10MSPS to 65MSPS, 50% clock duty cycle, –1dBFS

differential analog input, internal reference mode, ISET resistor = 56.2kΩ, and LVDS buffer current setting = 3.5mA, unless

otherwise noted. ADS5281 ADS5281 ADS5282

HTQFP-80 QFN-64 QFN-64

50MSPS 50MSPS 65MSPS

PARAMETER TEST CONDITIONS MIN TYP MAX MIN TYP MAX MIN TYP MAX UNIT

DC ACCURACY

No missing codes Assured Assured Assured

DNL Differential nonlinearity –0.75 ±0.25 +0.75 –0.75 ±0.25 +0.75 –0.9 ±0.3 +0.9 LSB

INL Integral nonlinearity –1.5 ±0.7 +1.5 –1.5 ±0.7 +1.5 –1.7 ±0.7 +1.7 LSB

POWER SUPPLY—INTERNAL REFERENCE MODE

IAVDD Analog supply current 119 145 119 145 145 170 mA

ILVDD Digital current Zero input to all channels 76 95 76 95 89 102 mA

Total power 530 649.5 530 649.5 639 744.6 mW

Obtained on powering down one

Incremental power saving 51 51 63 mW

channel at a time

POWER SUPPLY—EXTERNAL REFERENCE MODE

IAVDD Analog supply current 113 113 138 mA

ILVDD Digital current Zero input to all channels 76 76 89 mA

Total power 510 510 616 mW

Obtained on powering down one

Incremental power saving 50 50 61 mW

channel at a time

EXTERNAL REFERENCE LOADING

Current drawn by the eight ADCs

from the external reference

Switching current 2.5 2.5 3.5 mA

voltages; sourcing for REFT,

sinking for REFB.

DYNAMIC CHARACTERISTICS

fIN = 5MHz, single-ended clock 74 85 74 85 72 85 dBc

SFDR Spurious-free dynamic range fIN = 30MHz, differential clock 80 80 80 dBc

fIN = 5MHz, single-ended clock 74 85 74 85 72 85 dBc

HD2 Magnitude of second harmonic fIN = 30MHz, differential clock 82 82 82 dBc

fIN = 5MHz, single-ended clock 74 85 74 85 72 85 dBc

HD3 Magnitude of third harmonic fIN = 30MHz, differential clock 80 80 80 dBc

fIN = 5MHz, single-ended clock 71 80 71 80 70 80

THD Total harmonic distortion fIN = 30MHz, differential clock 78 78 78

fIN = 5MHz, single-ended clock 68.3 70 68.3 70 68.3 70 dBFS

SNR Signal-to-noise ratio fIN = 30MHz, differential clock 69.8 69.8 69.8 dBFS

fIN = 5MHz, single-ended clock 67.7 69.7 67.7 69.7 67.3 69.7 dBFS

SINAD Signal-to-noise and distortion fIN = 30MHz, differential clock 69.5 69.5 69.5 dBFS

(1) All characteristics are specific to each grade.

AVDD

IN8N

IN8P

AVSS

IN7N

IN7P

AVDD

AVSS

IN6N

IN6P

AVSS

IN5N

IN5P

AVDD

LVSS

RESET

LVSS

ADCLKN

ADCLKP

AVSS

OUT1P

AVSS

OUT1N

SCLK

OUT2P

SDATA

OUT2N

LVDD

AVDD

LVSS

AVSS

OUT3P

AVSS

OUT3N

CLKN

OUT4P

CLKP

OUT4N

AVDD

OUT5P

INT/EXT

OUT5N

AVSS

OUT6P

REFT

OUT6N

REFB

LVDD

VCM

LVSS

ISET

OUT7P

AVDD

OUT7N

OUT8P

OUT8N

AVDD

IN1P

IN1N

AVSS

IN2P

IN2N

AVDD

AVSS

IN3P

IN3N

AVSS

IN4P

IN4N

AVDD

LVSS

LCLKP

LCLKN

80 79 78 77 76 75 74 73 72 71 70

21 22 23 24 25 26 27 28 29 30 31

32 33 34 35 36 37 38 39 40

68 67 66 65 64 63 62 61

ADS528x

ADS5281

ADS5282

www.ti.com

SBAS397I –DECEMBER 2006–REVISED JUNE 2012

PIN CONFIGURATIONS

TQFP-80

TOP VIEW

Table 2. PIN DESCRIPTIONS: TQFP-80

PIN NAME DESCRIPTION PIN NUMBER # OF PINS

ADCLKNLVDS frame clock (1X)—negative output 42 1

ADCLKPLVDS frame clock (1X)—positive output 41 1

AVDD Analog power supply, 3.3V 1, 7, 14, 47, 54, 60, 63, 70, 75 9

AVSS Analog ground 4, 8, 11, 50, 53, 57, 68, 73, 74, 79, 80 11

Negative differential clock

CLKN72 1

Tie CLKNto 0V for a single-ended clock

CLKPPositive differential clock 71 1

CS Serial enable chip select—active low digital input 76 1

IN1NNegative differential input signal, channel 1 3 1

IN1PPositive differential input signal, channel 1 2 1

IN2NNegative differential input signal, channel 2 6 1

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Table 2. PIN DESCRIPTIONS: TQFP-80 (continued)

PIN NAME DESCRIPTION PIN NUMBER # OF PINS

IN2PPositive differential input signal, channel 2 5 1

IN3NNegative differential input signal, channel 3 10 1

IN3PPositive differential input signal, channel 3 9 1

IN4NNegative differential input signal, channel 4 13 1

IN4PPositive differential input signal, channel 4 12 1

IN5NNegative differential input signal, channel 5 49 1

IN5PPositive differential input signal, channel 5 48 1

IN6NNegative differential input signal, channel 6 52 1

IN6PPositive differential input signal, channel 6 51 1

IN7NNegative differential input signal, channel 7 56 1

IN7PPositive differential input signal, channel 7 55 1

IN8NNegative differential input signal, channel 8 59 1

IN8PPositive differential input signal, channel 8 58 1

INT/EXT Internal/external reference mode select input 69 1

ISET Bias pin—56.2kΩto ground 64 1

LCLKNLVDS bit clock (6X)—negative output 20 1

LCLKPLVDS bit clock (6X)—positive output 19 1

LVDD Digital and I/O power supply, 1.8V 25, 35 2

LVSS Digital ground 15, 17, 18, 26, 36, 43, 44, 46 8

NC No connection (or connect to ground) 62 1

OUT1NLVDS channel 1—negative output 22 1

OUT1PLVDS channel 1—positive output 21 1

OUT2NLVDS channel 2—negative output 24 1

OUT2PLVDS channel 2—positive output 23 1

OUT3NLVDS channel 3—negative output 28 1

OUT3PLVDS channel 3—positive output 27 1

OUT4NLVDS channel 4—negative output 30 1

OUT4PLVDS channel 4—positive output 29 1

OUT5NLVDS channel 5—negative output 32 1

OUT5PLVDS channel 5—positive output 31 1

OUT6NLVDS channel 6—negative output 34 1

OUT6PLVDS channel 6—positive output 33 1

OUT7NLVDS channel 7—negative output 38 1

OUT7PLVDS channel 7—positive output 37 1

OUT8NLVDS channel 8—negative output 40 1

OUT8PLVDS channel 8—positive output 39 1

PD Power-down input 16 1

REFBNegative reference input/output 66 1

REFTPositive reference input/output 67 1

RESET Active low RESET input 45 1

SCLK Serial clock input 78 1

SDATA Serial data input 77 1

TP Test pin, do not use 61 1

VCM Common-mode output pin, 1.5V output 65 1

IN8N

IN8P

AVSS

IN7N

IN7P

AVSS

IN6N

IN6P

AVSS

IN5N

IN5P

AVSS

LVSS

LVDD

OUT8N

OUT8P

IN1P

IN1N

AVSS

IN2P

IN2N

AVSS

IN3P

IN3N

AVSS

IN4P

IN4N

LVSS

OUT1P

OUT1N

RESET

SCLK

SDATA

AVDD

CLKN

CLKP

AVDD

INT/EXT

REFT

REFB

VCM

ISET

AVDD

OUT2P

OUT2N

OUT3P

OUT3N

OUT4P

OUT4N

ADCLKP

ADCLKN

LCLKP

LCLKN

OUT5P

OUT5N

OUT6P

OUT6N

OUT7P

OUT7N

64 63 62 61 60 59 58 57 56 55 54

17 18 19 20 21 22 23 24 25 26 27

53 52 51 50 49

28 29 30 31 32

ADS528X

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ADS5282

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SBAS397I –DECEMBER 2006–REVISED JUNE 2012

QFN-64 PowerPAD

TOP VIEW

Table 3. PIN DESCRIPTIONS: QFN-64

PIN NAME DESCRIPTION PIN NUMBER # OF PINS

ADCLKNLVDS frame clock (1X)—negative output 24 1

ADCLKPLVDS frame clock (1X)—positive output 23 1

AVDD Analog power supply, 3.3V 49, 50, 57, 60 4

AVSS Analog ground 3, 6, 9, 37, 40, 43, 46 7

Negative differential clock input

CLKN59 1

Tie CLKNto 0V for a single-ended clock

CLKPPositive differential clock input 58 1

CS Serial enable chip select—active low digital input 61 1

IN1NNegative differential input signal, channel 1 2 1

IN1PPositive differential input signal, channel 1 1 1

IN2NNegative differential input signal, channel 2 5 1

IN2PPositive differential input signal, channel 2 4 1

IN3NNegative differential input signal, channel 3 8 1

IN3PPositive differential input signal, channel 3 7 1

IN4NNegative differential input signal, channel 4 11 1

IN4PPositive differential input signal, channel 4 10 1

IN5NNegative differential input signal, channel 5 39 1

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Table 3. PIN DESCRIPTIONS: QFN-64 (continued)

PIN NAME DESCRIPTION PIN NUMBER # OF PINS

IN5PPositive differential input signal, channel 5 38 1

IN6NNegative differential input signal, channel 6 42 1

IN6PPositive differential input signal, channel 6 41 1

IN7NNegative differential input signal, channel 7 45 1

IN7PPositive differential input signal, channel 7 44 1

IN8NNegative differential input signal, channel 8 48 1

IN8PPositive differential input signal, channel 8 47 1

INT/EXT Internal/external reference mode select input 56 1

ISET Bias pin—56.2kΩto ground 51 1

LCLKNLVDS bit clock (6X)—negative output 26 1

LCLKPLVDS bit clock (6X)—positive output 25 1

LVDD Digital and I/O power supply, 1.8V 35 1

LVSS Digital ground 12, 14, 36 3

OUT1NLVDS channel 1—negative output 16 1

OUT1PLVDS channel 1—positive output 15 1

OUT2NLVDS channel 2—negative output 18 1

OUT2PLVDS channel 2—positive output 17 1

OUT3NLVDS channel 3—negative output 20 1

OUT3PLVDS channel 3—positive output 19 1

OUT4NLVDS channel 4—negative output 22 1

OUT4PLVDS channel 4—positive output 21 1

OUT5NLVDS channel 5—negative output 28 1

OUT5PLVDS channel 5—positive output 27 1

OUT6NLVDS channel 6—negative output 30 1

OUT6PLVDS channel 6—positive output 29 1

OUT7NLVDS channel 7—negative output 32 1

OUT7PLVDS channel 7—positive output 31 1

OUT8NLVDS channel 8—negative output 34 1

OUT8PLVDS channel 8—positive output 33 1

PD Power-down input 13 1

REFBNegative reference input/output 54 1

REFTPositive reference input/output 55 1

RESET Active low RESET input 64 1

SCLK Serial clock input 63 1

SDATA Serial data input 62 1

TP Test pin, do not use 52 1

VCM Common-mode output pin, 1.5V output 53 1

12-Bit

ADC

PLL

Serializer

1xADCLK

6xADCLK

IN1P

IN1N

OUT1P

OUT1N

12-Bit

ADC Serializer

IN2P

IN2N

OUT2P

OUT2N

12-Bit

ADC Serializer

IN3P

IN3N

OUT3P

OUT3N

LCLKP

LCLKN

ADCLKP

ADCLKN

12xADCLK

12-Bit

ADC Serializer

IN4P

IN4N

OUT4P

OUT4N

12-Bit

ADC Serializer

IN5P

IN5N

OUT5P

OUT5N

12-Bit

ADC Serializer

IN6P

IN6N

OUT6P

OUT6N

12-Bit

ADC Serializer

IN7P

IN7N

OUT7P

OUT7N

12-Bit

ADC Serializer

Digital

Reference

IN8P

IN8N

REFT

INT/EXT

REFB

VCM

OUT8P

OUT8N

ISET

Registers

SDATA

RESET

SCLK

ADC

Control

Clock

Buffer

(ADCLK)

CLKP

(AVSS)

CLKN

AVDD

(3.3V)

LVDD

(1.8V)

Power-

Down

TestPatterns

DriveCurrent

OutputFormat

DigitalGain

(0dB-12dB)

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SBAS397I –DECEMBER 2006–REVISED JUNE 2012

FUNCTIONAL BLOCK DIAGRAM

tH1 tSU1 tH2 tSU2

LCLKN

LCLKP

OUTN

OUTP

D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11

Sample n Sample n+12

tPROP

t (A)

12clockslatency

AnalogInput

ClockInput

6XADCLK

LCLKN

LCLKP

1XADCLK

ADCLKN

ADCLKP

SERIAL DATA

OUTP

OUTN

tSAMPLE

Sample n+13

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SBAS397I –DECEMBER 2006–REVISED JUNE 2012

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LVDS TIMING DIAGRAM

DEFINITION OF SETUP AND HOLD TIMES

tSU = min(tSU1, tSU2)

tH= min(tH1, tH2)

TIMING CHARACTERISTICS(1) (2)

ADS528x

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

tAAperture delay 1.5 4.5 ns

Aperture delay variation Channel-to-channel within the same device (3σ) ±20 ps

tJAperture jitter 400 fs

Time to valid data after coming out of 50 μs

COMPLETE POWER-DOWN mode

Time to valid data after coming out of PARTIAL

tWAKE Wake-up time POWER-DOWN mode (with clock continuing to 2 μs

run during power-down)

Time to valid data after stopping and restarting 40 μs

the input clock Clock

Data latency 12 cycles

(1) Timing characteristics are common to the ADS528x family.

(2) Timing parameters are ensured by design and characterization; not production tested.

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LVDS OUTPUT TIMING CHARACTERISTICS(1) (2)

Typical values are at +25°C, minimum and maximum values are measured across the specified temperature range of TMIN = –40°C to TMAX =

+85°C, sampling frequency = as specified, CLOAD = 5pF(3), IOUT = 3.5mA, RLOAD = 100Ω(4), and no internal termination, unless otherwise

noted.

ADS528x

40MSPS 50MSPS 65MSPS

PARAMETER TEST CONDITIONS(5) MIN TYP MAX MIN TYP MAX MIN TYP MAX UNIT

Data valid(7) to zero-crossing of

tSU Data setup time(6) 0.67 0.47 0.27 ns

LCLKP

Zero-crossing of LCLKPto data

tHData hold time(6) 0.85 0.65 0.4 ns

becoming invalid(7)

Input clock (ADCLK) rising edge

tPROP Clock propagation delay cross-over to output clock (ADCLKP) 10 14 16.6 10 12.5 14.1 9.7 11.5 14 ns

rising edge cross-over

Duty cycle of differential clock,

LVDS bit clock duty cycle 45.5 50 53 45 50 53.5 41 50 57

(LCLKP– LCLKN)

Bit clock cycle-to-cycle 250 250 250 ps, pp

jitter

Frame clock cycle-to-cycle 150 150 150 ps, pp

jitter

tRISE, Data rise time, data fall Rise time is from –100mV to +100mV 0.09 0.2 0.4 0.09 0.2 0.4 0.09 0.2 0.4 ns

tFALL time Fall time is from +100mV to –100mV

tCLKRISE, Output clock rise time, Rise time is from –100mV to +100mV 0.09 0.2 0.4 0.09 0.2 0.4 0.09 0.2 0.4 ns

tCLKFALL output clock fall time Fall time is from +100mV to –100mV

(1) All characteristics are at the maximum rated speed for each speed grade.

(2) Timing parameters are ensured by design and characterization; not production tested.

(3) CLOAD is the effective external single-ended load capacitance between each output pin and ground.

(4) IOUT refers to the LVDS buffer current setting; RLOAD is the differential load resistance between the LVDS output pair.

(5) Measurements are done with a transmission line of 100Ωcharacteristic impedance between the device and the load.

(6) Setup and hold time specifications take into account the effect of jitter on the output data and clock. These specifications also assume

that data and clock paths are perfectly matched within the receiver. Any mismatch in these paths within the receiver would appear as

reduced timing margin.

(7) Data valid refers to a logic high of +100mV and a logic low of –100mV.

LVDS OUTPUT TIMING CHARACTERISTICS(1) (2)

Typical values are at +25°C, minimum and maximum values are measured across the specified temperature range of TMIN = –40°C to TMAX =

+85°C, sampling frequency = as specified, CLOAD = 5pF(3), IOUT = 3.5mA, RLOAD = 100Ω(4), and no internal termination, unless otherwise

noted.

ADS528x

30MSPS 20MSPS 10MSPS

PARAMETER TEST CONDITIONS(5) MIN TYP MAX MIN TYP MAX MIN TYP MAX UNIT

Data valid(7) to zero-crossing of

tSU Data setup time(6) 0.8 1.5 3.7 ns

LCLKP

Zero-crossing of LCLKPto data

tHData hold time(6) 1.2 1.9 3.9 ns

becoming invalid(7)

Input clock (ADCLK) rising edge

tPROP Clock propagation delay cross-over to output clock (ADCLKP) 9.5 13.5 17.3 9.5 14.5 17.3 10 14.7 17.1 ns

rising edge cross-over

Duty cycle of differential clock,

LVDS bit clock duty cycle 46.5 50 52 48 50 51 49 50 51

(LCLKP– LCLKN)

Bit clock cycle-to-cycle 250 250 750 ps, pp

jitter

Frame clock cycle-to-cycle 150 150 500 ps, pp

jitter

tRISE, Data rise time, data fall Rise time is from –100mV to +100mV 0.09 0.2 0.4 0.09 0.2 0.4 0.09 0.2 0.4 ns

tFALL time Fall time is from +100mV to –100mV

tCLKRISE, Output clock rise time, Rise time is from –100mV to +100mV 0.09 0.2 0.4 0.09 0.2 0.4 0.09 0.2 0.4 ns

tCLKFALL output clock fall time Fall time is from +100mV to –100mV

(1) All characteristics are at the speeds other than the maximum rated speed for each speed grade.

(2) Timing parameters are ensured by design and characterization; not production tested.

(3) CLOAD is the effective external single-ended load capacitance between each output pin and ground.

(4) IOUT refers to the LVDS buffer current setting; RLOAD is the differential load resistance between the LVDS output pair.

(5) Measurements are done with a transmission line of 100Ωcharacteristic impedance between the device and the load.

(6) Setup and hold time specifications take into account the effect of jitter on the output data and clock. These specifications also assume

that data and clock paths are perfectly matched within the receiver. Any mismatch in these paths within the receiver would appear as

reduced timing margin.

(7) Data valid refers to a logic high of +100mV and a logic low of –100mV.

AVDD(3Vto3.6V)

LVDD(1.7Vto1.9V)

High-Level RESET

(1.4Vto3.6V)

High-Level CS

(1.4Vto3.6V)

DeviceReadyfor

SerialRegisterWrite(2)

DeviceReadyfor

DataConversion

StartofClock

AVDD

LVDD

RESET

ADCLK

t4t7

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LVDS OUTPUT TIMING CHARACTERISTICS TIMINGS WHEN USING REGISTER 0xE3(2)

At 40 MSPS

PARAMETER(1) TEST CONDITIONS

MIN TYP MAX

Data setup time Data valid(3) to zero-crossing of LCLKp 0.60

Data hold time Zero-crossing of LCLKP to data becoming invalid(3) 0.92

Input clock (ADCLK) rising edge cross-over to output clock (ADCLK) rising edge

Clock propagation delay 8 12 14.6

crossover

(1) Only the setup time, hold time and clock propagation delay parameters are affected. Rest of the parameters are same as given in

previous two tables.

(2) Only timing specifications for 40MSPS are affected when using register 0xE3 (as specified in the recommended operating table section).

The timing specifications for other clock frequencies are same as given in previous two tables.

(3) Data valid refers to logic high of +100mV and logic low of –100mV.

RECOMMENDED POWER-UP SEQUENCING AND RESET TIMING

10μs < t1< 50ms, 10μs < t2< 50ms, –10ms < t3< 10ms, t4> 10ms, t5> 100ns, t6> 100ns, t7> 10ms, and t8> 100μs.

(1) The AVDD and LVDD power on sequence does not matter as long as –10ms < t3< 10ms. Similar considerations apply while shutting

down the device.

(2) Write initialization registers listed in the Initialization Registers table.

DeviceFully

PowersDown

DeviceFully

PowersUp

tWAKE

1 sm

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POWER-DOWN TIMING

Power-up time shown is based on 1μF bypass capacitors on the reference pins. tWAKE is the time it takes for the device to wake up

completely from power-down mode. The ADS528x has two power-down modes: complete power-down mode and partial power-down mode.

The device can be configured in partial power-down mode through a register setting.

tWAKE < 50μs for complete power-down mode.

tWAKE < 2μs for partial power-down mode (provided the clock is not shut off during power-down).

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

A7 A6 A5 A4 A3 A2 A1 A0

SCLK

SDATA

DatalatchedonrisingedgeofSCLK

StartSequence EndSequence

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SERIAL INTERFACE

The ADS528x has a set of internal registers that can be accessed through the serial interface formed by pins CS

(chip select, active low), SCLK (serial interface clock), and SDATA (serial interface data). When CS is low, the

following actions occur:

• Serial shift of bits into the device is enabled

• SDATA (serial data) is latched at every rising edge of SCLK

• SDATA is loaded into the register at every 24th SCLK rising edge

If the word length exceeds a multiple of 24 bits, the excess bits are ignored. Data can be loaded in multiples of

24-bit words within a single active CS pulse. The first eight bits form the register address and the remaining 16

bits form the register data. The interface can work with SCLK frequencies from 20MHz down to very low speeds

(a few hertz) and also with a non-50% SCLK duty cycle.

After power-up, the internal registers must be initialized to the respective default values. Initialization can be

done in one of two ways:

1. Through a hardware reset, by applying a low-going pulse on the RESET pin; or

2. Through a software reset; using the serial interface, set the RST bit high. Setting this bit initializes the

internal registers to the respective default values and then self-resets the RST bit low. In this case, the

RESET pin stays high (inactive).

After all registers have been initialized to their default values through a RESET operation, the registers detailed

in the Initialization Registers table must be written into. This process must be done after every hardware or

software RESET operation in order to reconfigure the device for the best mode of operation.

SERIAL INTERFACE TIMING

ADS528x

PARAMETER DESCRIPTION MIN TYP MAX UNIT

t1SCLK period 50 ns

t2SCLK high time 20 ns

t3SCLK low time 20 ns

t4Data setup time 5 ns

t5Data hold time 5 ns

t6CS fall to SCLK rise 8 ns

t7Time between last SCLK rising edge to CS rising edge 8 ns

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SERIAL REGISTER MAP

Table 4. SUMMARY OF FUNCTIONS SUPPORTED BY SERIAL INTERFACE(1) (2) (3) (4)

ADDRESS

IN HEX D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NAME DESCRIPTION DEFAULT

00 X RST Self-clearing software RESET. Inactive

Channel-specific ADC power-

X X X X X X X X PDN_CH<8:1> Inactive

down mode.

Partial power-down mode (fast

X PDN_PARTIAL Inactive

recovery from power-down).

0F Register mode for complete

X PDN_COMPLETE Inactive

power-down (slower recovery).

Configures the PD pin for partial Complete

X PDN_PIN_CFG power-down mode. power-down

LVDS current drive

X X X ILVDS_LCLK<2:0> programmability for LCLKNand 3.5mA drive

LCLKPpins.

LVDS current drive

ILVDS_FRAME

11 X X X programmability for ADCLKNand 3.5mA drive

<2:0> ADCLKPpins.

LVDS current drive

X X X ILVDS_DAT<2:0> programmability for OUTNand 3.5mA drive

OUTPpins.

Enables internal termination for Termination

X EN_LVDS_TERM LVDS buffers. disabled

Programmable termination for Termination

1 X X X TERM_LCLK<2:0> LCLKNand LCLKPbuffers. disabled

12 TERM_FRAME Programmable termination for Termination

1 X X X <2:0> ADCLKNand ADCLKPbuffers. disabled

Programmable termination for Termination

1 X X X TERM_DAT<2:0> OUTNand OUTPbuffers. disabled

Channel-specific, low-frequency

14 X X X X X X X X LFNS_CH<8:1> Inactive

noise suppression mode enable.

INPis

Swaps the polarity of the analog

24 X X X X X X X X INVERT_CH<8:1> positive

input pins electrically. input

Enables a repeating full-scale

X 0 0 EN_RAMP Inactive

ramp pattern on the outputs.

Enables the mode wherein the

DUALCUSTOM_

0 X 0 output toggles between two Inactive

PAT defined codes.

Enables the mode wherein the

SINGLE_CUSTOM

0 0 X output is a constant specified Inactive

25 _PAT code.

2MSBs for a single custom

BITS_CUSTOM1 pattern (and for the first code of

X X Inactive

<11:10> the dual custom pattern). <11> is

the MSB.

BITS_CUSTOM2 2MSBs for the second code of

X X Inactive

<11:10> the dual custom pattern.

10 lower bits for the single

BITS_CUSTOM1 custom pattern (and for the first

26 X X X X X X X X X X Inactive

<9:0> code of the dual custom pattern).

<0> is the LSB.

BITS_CUSTOM2 10 lower bits for the second

27 X X X X X X X X X X Inactive

<9:0> code of the dual custom pattern.

X X X X GAIN_CH1<3:0> Programmable gain channel 1. 0dB gain

X X X X GAIN_CH2<3:0> Programmable gain channel 2. 0dB gain

2A X X X X GAIN_CH3<3:0> Programmable gain channel 3. 0dB gain

X X X X GAIN_CH4<3:0> Programmable gain channel 4. 0dB gain

X X X X GAIN_CH5<3:0> Programmable gain channel 5. 0dB gain

X X X X GAIN_CH6<3:0> Programmable gain channel 6. 0dB gain

2B X X X X GAIN_CH7<3:0> Programmable gain channel 7. 0dB gain

X X X X GAIN_CH8<3:0> Programmable gain channel 8. 0dB gain

(1) The unused bits in each register (identified as blank table cells) must be programmed as '0'.

(2) X = Register bit referenced by the corresponding name and description (default is 0).

(3) Bits marked as '0' should be forced to 0, and bits marked as '1' should be forced to 1 when the particular register is programmed.

(4) Multiple functions in a register should be programmed in a single write operation.

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Table 4. SUMMARY OF FUNCTIONS SUPPORTED BY SERIAL INTERFACE(1) (2) (3) (4) (continued)

ADDRESS

IN HEX D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NAME DESCRIPTION DEFAULT

Single-

1 X DIFF_CLK Differential clock mode. ended clock

Enables the duty-cycle correction

1 X EN_DCC Disabled

circuit.

External

42 Drives the external reference reference

1 X EXT_REF_VCM mode through the VCM pin. drives REFT

and REFB

Controls the phase of LCLK

1 X X PHASE_DDR<1:0> 90 degrees

output relative to data.

0 X PAT_DESKEW Enables deskew pattern mode. Inactive

45 X 0 PAT_SYNC Enables sync pattern mode. Inactive

Binary two's complement format Straight

1 1 X BTC_MODE for ADC output. offset binary

Serialized ADC output comes LSB-first

1 1 X MSB_FIRST out MSB-first. output

Enables SDR output mode DDR output

46 1 1 X EN_SDR (LCLK becomes a 12x input mode

clock).

Controls whether the LCLK rising Rising edge

or falling edge comes in the of LCLK in

1 X 1 1 FALL_SDR middle of the data window when middle of

operating in SDR output mode. data window

SUMMARY OF FEATURES

POWER IMPACT (relative to default)

FEATURES DEFAULT SELECTION AT fS= 65MSPS

ANALOG FEATURES

Internal or external reference Internal reference mode uses approximately 23mW more

N/A Pin

(driven on the REFTand REFBpins) power on AVDD

External reference driven on the Off Register 42 Approximately 9mW less power on AVDD

VCM pin

Duty cycle correction circuit Off Register 42 Approximately 7mW more power on AVDD

With zero input to the ADC, low-frequency noise suppression

Low-frequency noise suppression Off Register 14 causes digital switching at fS/2, thereby increasing LVDD

power by approximately 7mW/channel

Differential clock mode uses approximately 7mW more power

Single-ended or differential clock Single-ended Register 42 on AVDD

Refer to the Power-Down Modes section in the Electrical

Power-down mode Off Pin and register 0F Characteristics table

DIGITAL FEATURES

Programmable digital gain (0dB to Registers 2A and

0dB No difference

12dB) 2B

Straight offset or BTC output Straight offset Register 46 No difference

Swap polarity of analog input pins Off Register 24 No difference

LVDS OUTPUT PHYSICAL LAYER

LVDS internal termination Off Register 12 Approximately 7mW more power on AVDD

LVDS current programmability 3.5mA Register 11 As per LVDS clock and data buffer current setting

LVDS OUTPUT TIMING

LSB- or MSB-first output LSB-first Register 46 No difference

SDR mode uses approximately 2mW more power on LVDD

DDR or SDR output DDR Register 46 (at fS= 30MSPS)

Refer to

LCLK phase relative to data output Register 42 No difference

Figure 1

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DESCRIPTION OF SERIAL REGISTERS

SOFTWARE RESET

ADDRESS

IN HEX D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NAME

00 X RST

Software reset is applied when the RST bit is set to '1'; setting this bit resets all internal registers and self-clears

to '0'.

POWER-DOWN MODES

ADDRESS

IN HEX D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NAME

X X X X X X X X PDN_CH<8:1>

X PDN_PARTIAL

0F 0 X PDN_COMPLETE

X 0 PDN_PIN_CFG

Each of the eight channels can be individually powered down. PDN_CH<N> controls the power-down mode for

the ADC channel <N>.

In addition to channel-specific power-down, the ADS528x also has two global power-down modes—partial

power-down mode and complete power-down mode. Partial power-down mode partially powers down the chip;

recovery from this mode is much quicker, provided that the clock has been running for at least 50μs before

exiting this mode. Complete power-down mode, on the other hand, completely powers down the chip, and

involves a much longer recovery time.

In addition to programming the device for either of these two power-down modes (through either the

PDN_PARTIAL or PDN_COMPLETE bits, respectively), the PD pin itself can be configured as either a partial

power-down pin or a complete power-down pin control. For example, if PDN_PIN_CFG = 0 (default), when the

PD pin is high, the device enters complete power-down mode. However, if PDN_PIN_CFG = 1, when the PD pin

is high, the device enters partial power-down mode.

LVDS DRIVE PROGRAMMABILITY

ADDRESS

IN HEX D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NAME

X X X ILVDS_LCLK<2:0>

11 X X X ILVDS_FRAME<2:0>

X X X ILVDS_DAT<2:0>

The LVDS drive strength of the bit clock (LCLKPor LCLKN) and the frame clock (ADCLKPor ADCLKN) can be

individually programmed. The LVDS drive strengths of all the data outputs OUTPand OUTNcan also be

programmed to the same value.

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All three drive strengths (bit clock, frame clock, and data) are programmed using sets of three bits. Table 5

shows an example of how the drive strength of the bit clock is programmed (the method is similar for the frame

clock and data drive strengths).

Table 5. Bit Clock Drive Strength(1)

ILVDS_LCLK<2> ILVDS_LCLK<1> ILVDS_LCLK<0> LVDS DRIVE STRENGTH FOR LCLKPAND LCLKN

0 0 0 3.5mA (default)

0 0 1 2.5mA

0 1 0 1.5mA

0 1 1 0.5mA

1 0 0 7.5mA

1 0 1 6.5mA

1 1 0 5.5mA

1 1 1 4.5mA

(1) Current settings lower than 1.5mA are not recommended.

LVDS INTERNAL TERMINATION PROGRAMMABILITY

ADDRESS

IN HEX D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NAME

X EN_LVDS_TERM

1 X X X TERM_LCLK<2:0>

12 1 X X X TERM_FRAME<2:0>

1 X X X TERM_DAT<2:0>

The LVDS buffers have high-impedance current sources driving the outputs. When driving traces whose

characteristic impedance is not perfectly matched with the termination impedance on the receiver side, there may

be reflections back to the LVDS output pins of the ADS528x that cause degraded signal integrity. By enabling an

internal termination (between the positive and negative outputs) for the LVDS buffers, the signal integrity can be

significantly improved in such scenarios. To set the internal termination mode, the EN_LVDS_TERM bit should

be set to '1'. Once this bit is set, the internal termination values for the bit clock, frame clock, and data buffers

can be independently programmed using sets of three bits. Table 6 shows an example of how the internal

termination of the LVDS buffer driving the bit clock is programmed (the method is similar for the frame clock and

data buffers). These termination values are only typical values and can vary by up to ±20% across temperature

and from device to device.

Table 6. Bit Clock Internal Termination

INTERNAL TERMINATION BETWEEN

TERM_LCLK<2> TERM_LCLK<1> TERM_LCLK<0> LCLKPAND LCLKNIN Ω

0 0 0 None

0 0 1 260

0 1 0 150

0 1 1 94

1 0 0 125

1 0 1 80

1 1 0 66

1 1 1 55

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LOW-FREQUENCY NOISE SUPPRESSION MODE

ADDRESS

IN HEX D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NAME

14 X X X X X X X X LFNS_CH<8:1>

The low-frequency noise suppression mode is specifically useful in applications where good noise performance is

desired in the frequency band of 0MHz to 1MHz (around dc). Setting this mode shifts the low-frequency noise of

the ADS528x to approximately fS/2, thereby moving the noise floor around dc to a much lower value.

LFNS_CH<8:1> enables this mode individually for each channel.

ANALOG INPUT INVERT

ADDRESS

IN HEX D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NAME

24 X X X X X X X X INVERT_CH<8:1>

Normally, the INPpin represents the positive analog input pin, and INNrepresents the complementary negative

input. Setting the bits marked INVERT_CH<8:1> (individual control for each channel) causes the inputs to be

swapped. INNnow represents the positive input, and INPthe negative input.

LVDS TEST PATTERNS

ADDRESS

IN HEX D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NAME

X 0 0 EN_RAMP

0 X 0 DUALCUSTOM_PAT

25 0 0 X SINGLE_CUSTOM_PAT

X X BITS_CUSTOM1<11:10>

X X BITS_CUSTOM2<11:10>

26 X X X X X X X X X X BITS_CUSTOM1<9:0>

27 X X X X X X X X X X BITS_CUSTOM2<9:0>

0 X PAT_DESKEW

45 X 0 PAT_SYNC

The ADS528x can output a variety of test patterns on the LVDS outputs. These test patterns replace the normal

ADC data output. Setting EN_RAMP to '1' causes all the channels to output a repeating full-scale ramp pattern.

The ramp increments from zero code to full-scale code in steps of 1LSB every clock cycle. After hitting the full-

scale code, it returns back to zero code and ramps again.

The device can also be programmed to output a constant code by setting SINGLE_CUSTOM_PAT to '1', and

programming the desired code in BITS_CUSTOM1<11:0>. In this mode, BITS_CUSTOM1<11:0> take the place

of the 12-bit ADC data at the output, and are controlled by LSB-first and MSB-first modes in the same way as

normal ADC data are.

The device may also be made to toggle between two consecutive codes by programming DUAL_CUSTOM_PAT

to '1'. The two codes are represented by the contents of BITS_CUSTOM1<11:0> and BITS_CUSTOM2<11:0>.

In addition to custom patterns, the device may also be made to output two preset patterns:

1. Deskew patten: Set using PAT_DESKEW, this mode replaces the 12-bit ADC output D<11:0> with the

010101010101 word.

2. Sync pattern: Set using PAT_SYNC, the normal ADC word is replaced by a fixed 111111000000 word.

Note that only one of the above patterns should be active at any given instant.

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PROGRAMMABLE GAIN

ADDRESS

IN HEX D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NAME

X X X X GAIN_CH1<3:0>

X X X X GAIN_CH2<3:0>

2A X X X X GAIN_CH3<3:0>

X X X X GAIN_CH4<3:0>

X X X X GAIN_CH5<3:0>

X X X X GAIN_CH6<3:0>

2B X X X X GAIN_CH7<3:0>

X X X X GAIN_CH8<3:0>

In applications where the full-scale swing of the analog input signal is much less than the 2VPP range supported

by the ADS528x, a programmable gain can be set to achieve the full-scale output code even with a lower analog

input swing. The programmable gain not only fills the output code range of the ADC, but also enhances the SNR

of the device by utilizing quantization information from some extra internal bits. The programmable gain for each

channel can be individually set using a set of four bits, indicated as GAIN_CHN<3:0> for Channel N. The gain

setting is coded in binary from 0dB to 12dB, as shown in Table 7.

Table 7. Gain Setting for Channel 1

GAIN_CH1<3> GAIN_CH1<2> GAIN_CH1<1> GAIN_CH1<0> CHANNEL 1 GAIN SETTING

0 0 0 0 0dB

0 0 0 1 1dB

0 0 1 0 2dB

0 0 1 1 3dB

0 1 0 0 4dB

0 1 0 1 5dB

0 1 1 0 6dB

0 1 1 1 7dB

1 0 0 0 8dB

1 0 0 1 9dB

1 0 1 0 10dB

1 0 1 1 11dB

1 1 0 0 12dB

1 1 0 1 Do not use

1 1 1 0 Do not use

1 1 1 1 Do not use

VREF =1.5V -

VCM

1.5V

VREF =1.5V+

VCM

1.5V

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CLOCK, REFERENCE, AND DATA OUTPUT MODES

ADDRESS

IN HEX D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 NAME

1 X DIFF_CLK

1 X EN_DCC

42 1 X EXT_REF_VCM

1 X X PHASE_DDR<1:0>

1 1 X BTC_MODE

1 1 X MSB_FIRST

46 1 1 X EN_SDR

1 X 1 1 FALL_SDR

INPUT CLOCK

The ADS528x is configured by default to operate with a single-ended input clock—CLKPis driven by a CMOS

clock and CLKNis tied to '0'. However, by programming DIFF_CLK to '1', the device can be made to work with a

differential input clock on CLKPand CLKN. Operating with a low-jitter differential clock usually gives better SNR

performance, especially at input frequencies greater than 30MHz.

In cases where the duty cycle of the input clock falls outside the 45% to 55% range, it is recommended to enable

an internal duty cycle correction circuit. This enabling is done by setting the EN_DCC bit to '1'.

EXTERNAL REFERENCE

The ADS528x can be made to operate in external reference mode by pulling the INT/EXT pin to '0'. In this mode,

the REFTand REFBpins should be driven with voltage levels of 2.5V and 0.5V, respectively, and must have

enough drive strength to drive the switched capacitance loading of the reference voltages by each ADC. The

advantage of using the external reference mode is that multiple ADS528x units can be made to operate with the

same external reference, thereby improving parameters such as gain matching across devices. However, in

applications that do not have an available high drive, differential external reference, the ADS528x can still be

driven with a single external reference voltage on the VCM pin. When EXT_REF_VCM is set as '1' (and the

INT/EXT pin is set to '0'), the VCM pin is configured as an input pin, and the voltages on REFTand REFBare

generated as shown in Equation 1 and Equation 2.

(1)

(2)

PHASE_DDR<1:0>='00'

PHASE_DDR<1:0>='01'

PHASE_DDR<1:0>='10'

PHASE_DDR<1:0>='11'

ADCLKP

LCLKP

OUTP

ADCLKP

LCLKP

OUTP

ADCLKP

LCLKP

OUTP

ADCLKP

LCLKP

OUTP

ADCLKP

LCLKP

OUTP

ADS5281

ADS5282

SBAS397I –DECEMBER 2006–REVISED JUNE 2012

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BIT CLOCK PROGRAMMABILITY

The output interface of the ADS528x is normally a DDR interface, with the LCLK rising edge and falling edge

transitions in the middle of alternate data windows. This default phase is shown in Figure 1.

Figure 1. Default Phase of LCLK

The phase of LCLK can be programmed relative to the output frame clock and data using bits

PHASE_DDR<1:0>. The LCLK phase modes are shown in Figure 2.

Figure 2. Phase Programmability Modes for LCLK

EN_SDR='1',FALL_SDR='0'

EN_SDR='1',FALL_SDR='1'

ADCLKP

LCLKP

OUTP

ADCLKP

LCLKP

OUTP

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ADS5282

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SBAS397I –DECEMBER 2006–REVISED JUNE 2012

In addition to programming the phase of LCLK in the DDR mode, the device can also be made to operate in SDR

mode by setting the EN_SDR bit to '1'. In this mode, the bit clock (LCLK) is output at 12x times the input clock, or

twice the rate as in DDR mode. Depending on the state of FALL_SDR, LCLK may be output in either of the two

manners shown in Figure 3. As can be seen in Figure 3, only the LCLK rising (or falling) edge is used to capture

the output data in SDR mode.

Figure 3. SDR Interface Modes

The SDR mode does not work well beyond 40MSPS because the LCLK frequency becomes very high.

DATA OUTPUT FORMAT MODES

The ADC output, by default, is in straight offset binary mode. Programming the BTC_MODE bit to '1' inverts the

MSB, and the output becomes binary two's complement mode.

Also by default, the first bit of the frame (following the rising edge of ADCLKP) is the LSB of the ADC output.

Programming the MSB_FIRST mode inverts the bit order in the word, and the MSB is output as the first bit

following the ADCLKPrising edge.

100

120

140

160

180

InputFrequency(MHz)

0 25

Amplitude(dB)

201510

SFDR=88.4dBc

SNR=70.9dBFS

SINAD=70.8dBFS

THD=87.5dBc

100

120

140

160

180

InputFrequency(MHz)

0 25

Amplitude(dB)

201510

SFDR=85.6dBc

SNR=70.5dBFS

SINAD=70.4dBFS

THD=83.9dBc

100

120

140

160

180

InputFrequency(MHz)

0 2 20

Amplitude(dB)

1816141210864

SFDR=85.3dBc

SNR=70.8dBFS

SINAD=70.7dBFS

THD=89.3dBc

100

120

140

160

180

InputFrequency(MHz)

0 2 20

Amplitude(dB)

1816141210864

SFDR=82.8dBc

SNR=70.2dBFS

SINAD=70dBFS

THD=82.3dBc

ADS5281

ADS5282

SBAS397I –DECEMBER 2006–REVISED JUNE 2012

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TYPICAL CHARACTERISTICS

At TA= +25°C, AVDD = +3.3V, LVDD = 1.8V, clock frequency = 65MSPS, differential clock mode, 1VPP clock amplitude, 50%

clock duty cycle, input frequency = 10MHz, –1dBFS differential analog input, 0dB digital gain setting, 1.5V analog input

common-mode, low-frequency noise suppression = off, internal reference mode, ISET resistor = 56.2kΩ, and LVDS buffer

current setting = 3.5mA, unless otherwise noted.

SPECTRAL PERFORMANCE SPECTRAL PERFORMANCE

(fS= 40MHz, fIN = 10MHz) (fS= 40MHz, fIN = 25MHz)

Figure 4. Figure 5.

SPECTRAL PERFORMANCE SPECTRAL PERFORMANCE

(fS= 50MHz, fIN = 10MHz) (fS= 50MHz, fIN = 25MHz)

Figure 6. Figure 7.

-20

-40

-60

-80

-100

-120

-140

-180

InputFrequency(MHz)

0 33

Amplitude(dB)

2015105

-160

SFDR=86.2dBc

SNR=70.5dBFS

SNR(0MHzto1MHz)=86.1dBFS

SINAD=70.4dBFS

THD=85.4dBc

25 30

InputFrequency(MHz)

5 30

DynamicPerformance(SNR,SFDR)

201510 25

SNR(dBFS)

SFDR(dBc)

f =40MHz

100

120

140

160

180

InputFrequency(MHz)

0 33

Amplitude(dB)

2015105 25 30

SFDR=90.9dBc

SNR=70.8dBFS

SINAD=70.7dBFS

THD=90.4dBc

-20

-40

-60

-80

-100

-120

-140

-180

InputFrequency(MHz)

0 33

Amplitude(dB)

2015105

-160

SFDR=87.4dBc

SNR=70.4dBFS

SNR(0MHzto1MHz)=81.9dBFS

SINAD=70.3dBFS

THD=86.4dBc

25 30

ADS5281

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SBAS397I –DECEMBER 2006–REVISED JUNE 2012

TYPICAL CHARACTERISTICS (continued)

At TA= +25°C, AVDD = +3.3V, LVDD = 1.8V, clock frequency = 65MSPS, differential clock mode, 1VPP clock amplitude, 50%

clock duty cycle, input frequency = 10MHz, –1dBFS differential analog input, 0dB digital gain setting, 1.5V analog input

common-mode, low-frequency noise suppression = off, internal reference mode, ISET resistor = 56.2kΩ, and LVDS buffer

current setting = 3.5mA, unless otherwise noted.

SPECTRAL PERFORMANCE SPECTRAL PERFORMANCE

(fS= 65MHz, fIN = 10MHz) (fS= 65MHz, fIN = 25MHz)

Figure 8. Figure 9.

SPECTRAL PERFORMANCE, LOW-FREQUENCY NOISE

SUPPRESSION MODE ENABLED

(fS= 65MHz, fIN = 25MHz) DYNAMIC PERFORMANCE vs INPUT FREQUENCY

Figure 10. Figure 11.

InputAmplitude(dBFS)

DynamicPerformance(SNR,SFDR)

SNR(dBFS)

SFDR(dBc)

f =65MHz

f =10MHz

-60 0-50 -40 -30 -20 -10

ClockAmplitude(V Differential)

0.6 2.3

DynamicPerformance(SNR,SFDR)

1.61.1

SNR(dBFS)

SFDR(dBc)

f =65MHz

f =10MHz

2.1

DigitalGain(dB)

0 12

DynamicPerformance(SNR,SFDR)

642 8

SNR(dBFS)

SFDR(dBc)

f =65MHz

f =10MHz

AVDD(V)

3.0 3.6

DynamicPerformance(SNR,SFDR)

3.33.23.1 3.4

SNR(dBFS)

SFDR(dBc)

f =65MHz

f =10MHz

3.5

InputFrequency(MHz)

5 30

DynamicPerformance(SNR,SFDR)

201510 25

SNR(dBFS)

SFDR(dBc)

f =50MHz

InputFrequency(MHz)

5 30

DynamicPerformance(SNR,SFDR)

201510 25

SNR(dBFS)

SFDR(dBc)

f =65MHz

ADS5281

ADS5282

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TYPICAL CHARACTERISTICS (continued)

At TA= +25°C, AVDD = +3.3V, LVDD = 1.8V, clock frequency = 65MSPS, differential clock mode, 1VPP clock amplitude, 50%

clock duty cycle, input frequency = 10MHz, –1dBFS differential analog input, 0dB digital gain setting, 1.5V analog input

common-mode, low-frequency noise suppression = off, internal reference mode, ISET resistor = 56.2kΩ, and LVDS buffer

current setting = 3.5mA, unless otherwise noted.

DYNAMIC PERFORMANCE vs INPUT FREQUENCY DYNAMIC PERFORMANCE vs INPUT FREQUENCY

Figure 12. Figure 13.

DYNAMIC PERFORMANCE vs DIGITAL GAIN DYNAMIC PERFORMANCE vs AVDD

Figure 14. Figure 15.

DYNAMIC PERFORMANCE vs INPUT AMPLITUDE DYNAMIC PERFORMANCE vs CLOCK AMPLITUDE

Figure 16. Figure 17.

ExternalReferenceCommon-ModeVoltage,(REF +REF )/2(V)

T B

1.35 1.65

DynamicPerformance(SNR,SFDR)

1.501.451.40

SNR(dBFS)

SFDR(dBc)

f =65MHz

f =10MHz

1.55 1.60

Externalreferencedifferentialvoltagemaintainedat2V.

VoltageonV (V)

1.35 1.65

DynamicPerformance(SNR,SFDR)

1.501.451.40

SNR(dBFS)

SFDR(dBc)

f =65MHz

f =10MHz

1.55 1.60

AnalogInputCommon-ModeVoltage(V)

1.30 1.70

DynamicPerformance(SNR,SFDR)

1.401.35

SNR(dBFS)

SFDR(dBc)

f =65MHz

f =10MHz

1.45 1.651.601.551.50

ExternalReferenceDifferentialVoltage,REF REF (V)-

T B

1.6 2.4

DynamicPerformance(SNR,SFDR)

1.91.81.7

SNR(dBFS)

SFDR(dBc)

f =65MHz

f =10MHz

2.0 2.32.22.1

Externalreferencecommon-modevoltage

maintainedat1.5V.

ADS5281

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SBAS397I –DECEMBER 2006–REVISED JUNE 2012

TYPICAL CHARACTERISTICS (continued)

At TA= +25°C, AVDD = +3.3V, LVDD = 1.8V, clock frequency = 65MSPS, differential clock mode, 1VPP clock amplitude, 50%

clock duty cycle, input frequency = 10MHz, –1dBFS differential analog input, 0dB digital gain setting, 1.5V analog input

common-mode, low-frequency noise suppression = off, internal reference mode, ISET resistor = 56.2kΩ, and LVDS buffer

current setting = 3.5mA, unless otherwise noted.

DYNAMIC PERFORMANCE vs ANALOG INPUT COMMON- DYNAMIC PERFORMANCE vs EXTERNAL REFERENCE

MODE VOLTAGE DIFFERENTIAL VOLTAGE

Figure 18. Figure 19.

DYNAMIC PERFORMANCE vs EXTERNAL REFERENCE DYNAMIC PERFORMANCE vs EXTERNAL REFERENCE

COMMON-MODE VOLTAGE FORCED THROUGH VCM

Figure 20. Figure 21.

0.5

0.4

0.3

0.2

0.1

-0.1

-0.2

-0.5

Code(LSB)

0 4096

INL(LSB)

30722048 25601536 35841024512

-0.4

-0.3

f =50MSPS

f =5MHz

0.35

0.25

0.15

0.05

-0.05

-0.15

-0.35

Code(LSB)

0 4096

DNL(LSB)

30722048 25601536 35841024512

-0.25

f =50MSPS

f =5MHz

CodeBin(LSB)

2049

Occurrence(%)

20532051 2054

f =65MSPS

2050 2052

0% 0%

0.37% 0.28%

51.92%

47.43%

-10

-30

-50

-70

-90

-110

-130

-150

InputFrequency(MHz)

0 2 20

Amplitude(dB)

1816141210864

f =65MHz

f =10MHz( 7dBFS)

f =16.1MHz( 7dBFS)

IMD= 97dBFS

ClockDutyCycle(%)

35 65

DynamicPerformance(SNR,SFDR)

504540 55

SNR(dBFS)

SFDR(dBc)

f =65MHz

f =10MHz

ClockDutyCycle(%)

20 80

DynamicPerformance(SNR,SFDR)

504030 60

SNR(dBFS)

SFDR(dBc)

f =65MHz

f =10MHz

ADS5281

ADS5282

SBAS397I –DECEMBER 2006–REVISED JUNE 2012

www.ti.com

TYPICAL CHARACTERISTICS (continued)

At TA= +25°C, AVDD = +3.3V, LVDD = 1.8V, clock frequency = 65MSPS, differential clock mode, 1VPP clock amplitude, 50%

clock duty cycle, input frequency = 10MHz, –1dBFS differential analog input, 0dB digital gain setting, 1.5V analog input

common-mode, low-frequency noise suppression = off, internal reference mode, ISET resistor = 56.2kΩ, and LVDS buffer

current setting = 3.5mA, unless otherwise noted.

DYNAMIC PERFORMANCE vs CLOCK DUTY CYCLE, DCC DYNAMIC PERFORMANCE vs CLOCK DUTY CYCLE, DCC

DISABLED ENABLED

Figure 22. Figure 23.

HISTOGRAM OF OUTPUT CODE FOR ZERO INPUT INTERMODULATION DISTORTION

Figure 24. Figure 25.

INTEGRAL NONLINEARITY DIFFERENTIAL NONLINEARITY

Figure 26. Figure 27.

0.64

0.62

0.60

0.58

0.56

0.54

0.52

StandardDeviation(LSB)

01 2 345 6

OverloadSignalAmplitude(dBFS)

f =65MSPS

f =5MHz

StandardDeviationof

2ndPointAfterOverload

StandardDeviationof

1stPointAfterOverload

16384t (Group1)

Set1,Point1(of16) Set1,Point2(of16)

Firstpointafteroverload(Set1)

Firstpointafteroverload(Set2)

Secondpointafteroverload(Set2)

Secondpointafteroverload(Set1)

Overload

Amplitude

NOTES:

Inputsinewavephaseisrepetitiveover16384clockcycles.

16suchrepetitivegroups(of16384clockcycles)arecaptured–atotalof262,144points.

Standarddeviationofeverysetof areanalyzedoverthe16groups.

Worstcaseofallsuchstandarddeviationsareplottedinthegraphs.

firstandsecondpointsafteroverload

+FS

-FS

0.70

0.68

0.66

0.64

0.62

0.60

0.58

0.56

0.54

0.52

0.50

StandardDeviation(inLSB)

01 2 345 6

OverloadSignalAmplitude(dBFS)

f =50MSPS

f =5MHz

IN StandardDeviationof

2ndPointAfterOverload

StandardDeviationof

1stPointAfterOverload

170

130

110

ClockFrequency(MSPS)

575

I ,I (mA)

AVDD LVDD

352515 45

ILVDD

IAVDD

ZeroInputonAllChannels

InternalReferenceMode

150

0.75

0.55

0.35

0.15

-0.05

-0.25

-0.65

Code(LSB)

0 4096

INL(LSB)

30722048 25601536 35841024512

-0.45

f =65MSPS

f =5MHz

0.35

0.25

0.15

0.05

-0.05

-0.15

-0.35

Code(LSB)

0 4096

DNL(LSB)

30722048 25601536 35841024512

-0.25

f =65MSPS,f =5MHz

S IN

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ADS5282

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SBAS397I –DECEMBER 2006–REVISED JUNE 2012

TYPICAL CHARACTERISTICS (continued)

At TA= +25°C, AVDD = +3.3V, LVDD = 1.8V, clock frequency = 65MSPS, differential clock mode, 1VPP clock amplitude, 50%

clock duty cycle, input frequency = 10MHz, –1dBFS differential analog input, 0dB digital gain setting, 1.5V analog input

common-mode, low-frequency noise suppression = off, internal reference mode, ISET resistor = 56.2kΩ, and LVDS buffer

current setting = 3.5mA, unless otherwise noted.

INTEGRAL NONLINEARITY DIFFERENTIAL NONLINEARITY

Figure 28. Figure 29.

AVDD AND LVDD POWER-SUPPLY CURRENTS

vs CLOCK FREQUENCY OVERLOAD RECOVERY AT 50MSPS

Figure 30. Figure 31.

OVERLOAD RECOVERY AT 65MSPS

Figure 32. Figure 33. Overload Recovery

ADS5281

ADS5282

SBAS397I –DECEMBER 2006–REVISED JUNE 2012

www.ti.com

APPLICATION INFORMATION

The ADC output goes to a serializer that operates

THEORY OF OPERATION from a 12x clock generated by the PLL. The 12 data

bits from each channel are serialized and sent LSB

The ADS528x devices are a family of 8-channel, first. In addition to serializing the data, the serializer

high-speed, CMOS ADCs. The 12 bits given out by also generates a 1x clock and a 6x clock. These

each channel are serialized and sent out on a single clocks are generated in the same way the serialized

pair of pins in LVDS format. All eight channels of the data are generated, so these clocks maintain perfect

ADS528x operate from a single clock (ADCLK). The synchronization with the data. The data and clock

sampling clocks for each of the eight channels are outputs of the serializer are buffered externally using

generated from the input clock using a carefully LVDS buffers. Using LVDS buffers to transmit data

matched clock buffer tree. The 12x clock required for externally has multiple advantages, such as a

the serializer is generated internally from ADCLK reduced number of output pins (saving routing space

using a phase-locked loop (PLL). A 6x and a 1x clock on the board), reduced power consumption, and

are also output in LVDS format, along with the data, reduced effects of digital noise coupling to the analog

to enable easy data capture. The ADS528x operates circuit inside the ADS528x.

from internally-generated reference voltages that are

trimmed to improve to a high level of accuracy. The ADS528x operates from two sets of supplies and

Trimmed references improve the gain matching grounds. The analog supply and ground set is

across devices, and provide the option to operate the identified as AVDD and AVSS, while the digital set is

devices without having to externally drive and route identified by LVDD and LVSS.

reference lines. The nominal values of REFTand

REFBare 2.5V and 0.5V, respectively. The ANALOG INPUT

references are internally scaled down differentially by

a factor of 2. This scaling results in a differential input The analog input consists of a switched-capacitor

of –1V to correspond to the zero code of the ADC, based, differential sample-and-hold architecture. This

and a differential input of +1V to correspond to the differential topology results in very good ac

full-scale code (4095 LSB). VCM (the common-mode performance even for high input frequencies at high

voltage of REFTand REFB) is also made available sampling rates. The INNand INPpins must be

externally through a pin, and is nominally 1.5V. externally biased around a common-mode voltage of

1.5V, available on VCM. For a full-scale differential

The ADC employs a pipelined converter architecture input, each input pin (INNand INP) must swing

that consists of a combination of multi-bit and single- symmetrically between VCM + 0.5V and VCM – 0.5V,

bit internal stages. Each stage feeds its data into the resulting in a 2VPP differential input swing. The

digital error correction logic, ensuring excellent maximum input peak-to-peak differential swing is

differential linearity and no missing codes at the 12- determined to be the difference between the internal

bit level. reference voltages REFT(2.5V nominal) and REFB

(0.5V nominal). Figure 34 illustrates the model of the

input driving circuit.

CMBuffer

Internal

Voltage

Reference

Input

Circuitry

INP

INN

VCM

1.2kW

ADS528x

(2mA) f´S

50MSPS

5nHto9nH(TQFP-80)

2nHto3nH(QFN-64)

1.5pF

to2.4pF

IN OUT

INP

1.5pFto

2.5pF

1000W

to1440W

to10W

1000W

to1440W

5nHto9nH(TQFP-80)

2nHto3nH(QFN-64)

INN

1.5pFto

2.5pF

15W

to25W

15W

to30W

0.2pF

to0.3pF

IN OUT

1.5pF

to2.4pF

IN OUT

to10W

15W

to25W

15W

to30W

IN OUT

OUT

16 to32W W

IN OUT

OUTP

OUTN

SwitchesthatareON

inSAMPLEphase.

SwitchesthatareON

inHOLDphase.

ADS5281

ADS5282

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SBAS397I –DECEMBER 2006–REVISED JUNE 2012

Figure 34. Analog Input Circuit Model

during ac-coupling by increasing VCM by roughly

Input Common-Mode Current 75mV. When operating above 50MSPS, it is

recommended that additional parallel resistors be

The input stage of all eight ADCs together sinks a added externally to restore the input common-mode

common-mode current on the order of 2mA at to at least 1.4V, if the inputs are to be ac-coupled.

50MSPS. Equation 3 describes the dependency of

the common-mode current and the sampling

frequency.

(3)

If the driving stage is dc-coupled to the inputs, then

Equation 3 can be used to determine its common-

mode drive capability and impedance. The inputs can

also be ac-coupled to the INNand INPpins. In that

case, the input common-mode is set by two internal

1.2kΩresistors connecting the input pins to VCM. This

architecture is shown in Figure 35.

When the inputs are ac-coupled, there is a drop in

the voltages at INPand INNrelative to VCM. This can Dashed area denotes one of eight channels.

be computed from Equation 3. At 50MSPS, for Figure 35. Common-Mode Biasing of Input Pins

example, the drop at each of the 16 input pins is

150mV, which is not optimal for ADC operation.

Initialization Registers 1 and 5, described in the

Initialization Registers table, can be used to partially

reduce the effect of this input common-mode drop

0.1 Fm50W

50W

200W

INP

VCM

INN

0.1 Fm

1:2 2:1

4.7W

0.1 Fm

25W

1:1

INP

VCM

INN

ADS5281

ADS5282

SBAS397I –DECEMBER 2006–REVISED JUNE 2012

www.ti.com

Driving Circuit At high input frequencies, the mismatch in the

transformer parasitic capacitance (between the

For optimum performance, the analog inputs must be windings) results in degraded even-order harmonic

driven differentially. This approach improves the performance. Connecting two identical RF

common-mode noise immunity and even-order transformers back-to-back helps to minimize this

harmonic rejection. Input configurations using RF mismatch, and good performance is obtained for

transformers suitable for low and high input high-frequency input signals. An additional

frequencies are shown in Figure 36 and Figure 37,termination resistor pair is required between the two

respectively. The single-ended signal is fed to the transformers, as shown in Figure 37. The center point

primary winding of the RF transformer. The of this termination is connected to ground to improve

transformer is terminated by 50Ωresistor on the the balance between the positive and negative sides.

secondary side. Placing the termination on the The values of the terminations between the

secondary side helps to shield the kicks caused by transformers and on the secondary side must be

the input sampling capacitors from the RF chosen to achieve an overall 50Ω(in the case of 50Ω

transformer leakage inductances. The termination is source impedance).

accomplished by two 25Ωresistors, connected in

series, with the center point connected to the 1.5V

common-mode. The 4.7Ωresistor in series with each

input pin is required to damp the ringing caused by

the device package parasitics.

Figure 36. Drive Circuit at Low Input Frequencies

Figure 37. Drive Circuit at High Input Frequencies

CLKP

CLKN

CMOSClockInput

0.1 Fm

CLKP

CLKN

CMOSSingle-Ended

Clock

CLKP

CLKN

DifferentialSine-Wave,

PECL,orLVDSClockInput

0.1 Fm

5kW5kW

VCM

CLKP

CLKN

VCM

ADS5281

ADS5282

www.ti.com

SBAS397I –DECEMBER 2006–REVISED JUNE 2012

CLOCK INPUT

The eight channels on the device operate from a

single ADCLK input. To ensure that the aperture

delay and jitter are the same for all channels, a clock

tree network is used to generate individual sampling

clocks to each channel. The clock paths for all the

channels are matched from the source point to the

sampling circuit. This architecture ensures that the

performance and timing for all channels are identical.

The use of the clock tree for matching introduces an

aperture delay that is defined as the delay between

the rising edge of ADCLK and the actual instant of

sampling. The aperture delays for all the channels

are matched to the best possible extent. A mismatch

of ±20ps (±3σ) could exist between the aperture

instants of the eight ADCs within the same chip. Figure 39. Internal Clock Buffer

However, the aperture delays of ADCs across two

different chips can be several hundred picoseconds

apart.

The ADS528x can be made to operate either in

CMOS single-ended clock mode (default is

DIFF_CLK = 0) or differential clock mode (SINE,

LVPECL, or LVDS). When operating in the single-

ended clock mode, CLKNmust be forced to 0VDC,

and the single-ended CMOS applied on the CLKPpin.

This operation is shown in Figure 38.Figure 40. Differential Clock Driving Circuit

(DIFF_CLK = 1)

Figure 38. Single-Ended Clock Driving Circuit

(DIFF_CLK = 0)

When configured to operate in the differential clock Figure 41. Single-Ended Clock Driving Circuit

mode (register bit DIFF_CLK = 1) the ADS528x clock When DIFF_CLK = 1

inputs can be driven differentially (SINE, LVPECL, or

LVDS) with little or no difference in performance For best performance, the clock inputs must be

between them, or with a single-ended (LVCMOS). driven differentially in order to reduce susceptibility to

The common-mode voltage of the clock inputs is set common-mode noise. For high input frequency

to VCM using internal 5kΩresistors, as shown in sampling, it is recommended to use a clock source

Figure 39. This method allows using transformer- with very low jitter. Bandpass filtering of the clock

coupled drive circuits for a sine wave clock or ac- source can help reduce the effect of jitter. If the duty

coupling for LVPECL and LVDS clock sources, as cycle deviates from 50% by more than 2% or 3%, it is

shown in Figure 40. When operating in the differential recommended to enable the DCC through register bit

clock mode, the single-ended CMOS clock can be ac- EN_DCC.

coupled to the CLKPinput, with CLKN(pin 11)

connected to ground with a 0.1μF capacitor, as

shown in Figure 41.

Threshold 1 Threshold 2 Threshold 3

10 MHz 45 MHz 65 MHz

Sampling Frequency

ADS5281

ADS5282

SBAS397I –DECEMBER 2006–REVISED JUNE 2012

www.ti.com

PLL OPERATION ACROSS SAMPLING Step 2: Disable the PLL automatic switch and set

FREQUENCY the PLL configuration depending on the clock

frequency

The ADS528X uses a PLL for generating the high

speed bit clock (LCLK), the frame clock (ADCLK) & SAMPLE CLOCK FREQUENCY REGISTER SETTING (Hex)

internal clocks for the serializer operation. RANGE (MSPS)

Min Max Address Data

To enable operation across the entire frequency

range, the PLL is automatically configured to one of 10 25 E3 0060

four states, depending on the sampling clock 15 45 E3 00A0

frequency range. The frequency range detection is

automatic and each time the sampling frequency With the above settings applied for the respective

crosses a threshold, the PLL changes its frequency ranges, the part will continue to

configuration to a new state. To prevent unwanted operate as per the stated datasheet specifications

toggling of PLL state around a threshold, the circuit for all timing parameters at all specified

has an inbuilt hysteresis. The ADS528x has three frequencies, EXCEPT for the timing specifications

thresholds – taking into account the hysteresis range at 40MSPS. At 40MSPS, the affected parameters

of each threshold, variation across devices and are – Data setup time, Data hold time and Clock

temperature, the thresholds can span the sampling propagation delay (refer to LVDS Timing ).

clock frequency range from 10MHz to 45MHz. 2. For sampling clock frequency ≥45MSPS

As there are no PLL thresholds beyond 45MHz,

no change in PLL configuration can occur as the

temperature in the system stabilizes. The

ADS528x can be used in the system without

using the above software fix.

INPUT OVER-VOLTAGE RECOVERY

The differential peak-to-peak full-scale range

supported by the ADS528x is nominally 2.0V. The

ADS528x is specially designed to handle an over-

Figure 42. Variation of Thresholds Across voltage condition where the differential peak-to-peak

Sampling Frequency voltage can be up to twice the ADC full-scale range.

If the input common-mode is not considerably off

from VCM during overload (less than 300mV around

Based on actual system clock frequency, there are the nominal value of 1.5V), recovery from an over-

two scenarios: voltage pulse input of twice the amplitude of a full-

1. For sampling clock frequency < 45MSPS scale pulse is expected to be within one clock cycle

After system power up, depending on the when the input switches from overload to zero signal.

frequency of operation and the frequency

threshold for the given device, the frequency REFERENCE CIRCUIT

range detection circuit may change state once. In The digital beam-forming algorithm in an ultrasound

some applications where a timing calibration system relies on gain matching across all receiver

might be done at the system level once after channels. A typical system would have about 12 octal

power up, this subsequent change of the PLL ADCs on the board. In such a case, it is critical to

state might be undesirable as it can cause a loss ensure that the gain is matched, essentially requiring

of alignment in the received data. A software fix the reference voltages seen by all the ADCs to be the

for eliminating this one-time change of PLL state same. Matching references within the eight channels

exists using the serial register interface: of a chip is done by using a single internal reference

– Disable the automatic switch of the PLL voltage buffer. Trimming the reference voltages on

configuration based on frequency detected. each chip during production ensures that the

– In addition to disabling the switching, it is also reference voltages are well-matched across different

required to set the PLL to the correct chips.

configuration, depending on the sample clock

frequency used in the system. All bias currents required for the internal operation of

the device are set using an external resistor to

The following sequence of register writes must be ground at the ISET pin. Using a 56.2kΩresistor on ISET

followed: generates an internal reference current of 20μA. This

Step 1: Write Address = 0x01, Data = 0x0010 current is mirrored internally to generate the bias

current for the internal blocks. Using a larger external

VREF =1.5V -

VCM

1.5V

VREF =1.5V+

VCM

1.5V

REFTREFB

ISET

0.1 Fm2.2 Fm

0 to

0 toW

56.2kW

2.2 Fm0.1 Fm

ADS528x

ADS5281

ADS5282

www.ti.com

SBAS397I –DECEMBER 2006–REVISED JUNE 2012

resistor at ISET reduces the reference bias current and The device also supports the use of external

thereby scales down the device operating power. reference voltages. There are two methods to force

However, it is recommended that the external resistor the references externally. The first method involves

be within 10% of the specified value of 56.2kΩso pulling INT/EXT low and forcing externally REFTand

that the internal bias margins for the various blocks REFBto 2.5V and 0.5V nominally, respectively. In this

are proper. mode, the internal reference buffer goes to a 3-state

output. The external reference driving circuit should

Buffering the internal bandgap voltage also generates be designed to provide the required switching current

the common-mode voltage VCM, which is set to the for the eight ADCs inside the chip. It should be noted

midlevel of REFTand REFB, and is accessible on a that in this mode, VCM and ISET continue to be

pin (pin 65 in TQFP-80 package, pin 53 in QFN-64 generated from the internal bandgap voltage, as in

package). It is meant as a reference voltage to derive the internal reference mode. It is therefore important

the input common-mode if the input is directly to ensure that the common-mode voltage of the

coupled. It can also be used to derive the reference externally-forced reference voltages matches to

common-mode voltage in the external reference within 50mV of VCM.

mode. The suggested decoupling for the reference

pins is shown in Figure 43. The second method of forcing the reference voltages

externally can be accessed by pulling INT/EXT low,

and programming the serial interface to drive the

external reference mode through the VCM pin (register

bit called EXT_REF_VCM). In this mode, VCM

becomes configured as an input pin that can be

driven from external circuitry. The internal reference

buffers driving REFTand REFBare active in this

mode. Forcing 1.5V on the VCM pin in the mode

results in REFTand REFBcoming to 2.5V and 0.5V,

respectively. In general, the voltages on REFTand

REFBin this mode are given by Equation 4 and

Equation 5, respectively:

(4)

Figure 43. Suggested Decoupling on the

Reference Pins (5)

The state of the reference voltage internal buffers

during various combinations of the PD, INT/EXT, and

EXT_REF_VCM register bits is described in Table 8.

Table 8. State of Reference Voltages for Various Combinations of PD, INT/EXT, and EXT_REF_VCM

PD 0 0 1 1 0 0 1 1

INT/EXT 0 1 0 1 0 1 0 1

EXT_REF_VCM 0 0 0 0 1 1 1 1

REFTbuffer 3-state 2.5V 3-state 2.5V(1) 1.5V + VCM/1.5V Do not use 2.5V(1) Do not use

REFBbuffer 3-state 0.5V 3-state 0.5V(1) 1.5V – VCM/1.5V Do not use 0.5V(1) Do not use

VCM pin 1.5V 1.5V 1.5V 1.5V Force Do not use Force Do not use

(1) Weakly forced with reduced strength. sections, while LVDD and LVSS are used to denote

the digital supplies. Care is taken to ensure that there

NOISE COUPLING ISSUES is minimal interaction between the supply sets within

High-speed mixed signals are sensitive to various the device. The extent of noise coupled and

types of noise coupling. One primary source of noise transmitted from the digital to the analog sections

is the switching noise from the serializer and the depends on:

output buffers. Maximum care is taken to isolate 1. The effective inductances of each of the supply

these noise sources from the sensitive analog blocks. and ground sets.

As a starting point, the analog and digital domains of 2. The isolation between the digital and analog

the device are clearly demarcated. AVDD and AVSS supply and ground sets.

are used to denote the supplies for the analog

ADS5281

ADS5282

SBAS397I –DECEMBER 2006–REVISED JUNE 2012

www.ti.com

Smaller effective inductance of the supply and ground It is recommended that the isolation be maintained on

pins leads to better noise suppression. For this the board by using separate supplies to drive AVDD

reason, multiple pins are used to drive each supply and LVDD, as well as separate ground planes for

and ground. It is also critical to ensure that the AVSS and LVSS. The use of LVDS buffers reduces

impedances of the supply and ground lines on the the injected noise considerably, compared to CMOS

board are kept to the minimum possible values. Use buffers. The current in the LVDS buffer is

of ground planes in the printed circuit board (PCB) as independent of the direction of switching. Also, the

well as large decoupling capacitors between the low output swing as well as the differential nature of

supply and ground lines are necessary to obtain the the LVDS buffer results in low-noise coupling.

best possible SNR performance from the device.

ADS5281

ADS5282

www.ti.com

SBAS397I –DECEMBER 2006–REVISED JUNE 2012

REVISION HISTORY

Changes from Revision G (March 2008) to Revision H Page

• Changed second table and conditions in the Initialization Registers section ....................................................................... 3

• Changed In Input Common-Mode Current section, changed initialization register 5 to initialization registers 1 and 5

to reflect change in Initialization Registers table ................................................................................................................ 33

Changes from Revision F (March 2008) to Revision G Page

• Deleted note (3) of Ordering Information table to indicate device status is now Production Data for all parts .................... 2

• Added new note (3) of Ordering Information table to indicate the quantity of transport media is available in the

Package Option Addendum .................................................................................................................................................. 2

• Added note (1) to Initialization Registers section to indicate it is no longer necessary to program initialization

registers 1 to 4 ...................................................................................................................................................................... 3

• Changed maximum specifications for ADS5282 column in the Power Supply—Internal Reference Mode section of

Electrical Characteristics (By Device) table .......................................................................................................................... 6

• Changed minimum specification for ADS5282 column in the f = 10 MHz row of the SNR section of Electrical

Characteristics (By Device) table .......................................................................................................................................... 6

Changes from Revision H (March 2008) to Revision I Page

• Added table in the INITIALIZATION REGISTERS section ................................................................................................... 3

• Added table in the LVDS OUTPUT TIMING CHARACTERISTICS section ....................................................................... 14

• Added PLL OPERATION ACROSS SAMPLING FREQUENCY section ............................................................................ 36

PACKAGE OPTION ADDENDUM

www.ti.com 18-Jan-2012

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status (1) Package Type Package

Drawing Pins Package Qty Eco Plan (2) Lead/

Ball Finish MSL Peak Temp (3) Samples

(Requires Login)

ADS5281IPFP ACTIVE HTQFP PFP 80 96 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

ADS5281IPFPG4 ACTIVE HTQFP PFP 80 96 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

ADS5281IPFPR ACTIVE HTQFP PFP 80 1000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

ADS5281IPFPRG4 ACTIVE HTQFP PFP 80 1000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

ADS5281IRGCR ACTIVE VQFN RGC 64 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

ADS5281IRGCRG4 ACTIVE VQFN RGC 64 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

ADS5281IRGCT ACTIVE VQFN RGC 64 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

ADS5281IRGCTG4 ACTIVE VQFN RGC 64 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

ADS5282IRGCR ACTIVE VQFN RGC 64 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

ADS5282IRGCRG4 ACTIVE VQFN RGC 64 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

ADS5282IRGCT ACTIVE VQFN RGC 64 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

ADS5282IRGCTG4 ACTIVE VQFN RGC 64 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

PACKAGE OPTION ADDENDUM

www.ti.com 18-Jan-2012

Addendum-Page 2

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

ADS5281IPFPR HTQFP PFP 80 1000 330.0 24.4 15.0 15.0 1.5 20.0 24.0 Q2

ADS5281IRGCR VQFN RGC 64 2000 330.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2

ADS5281IRGCT VQFN RGC 64 250 330.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2

ADS5282IRGCR VQFN RGC 64 2000 330.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2

ADS5282IRGCT VQFN RGC 64 250 330.0 16.4 9.3 9.3 1.5 12.0 16.0 Q2

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

ADS5281IPFPR HTQFP PFP 80 1000 367.0 367.0 45.0

ADS5281IRGCR VQFN RGC 64 2000 336.6 336.6 28.6

ADS5281IRGCT VQFN RGC 64 250 336.6 336.6 28.6

ADS5282IRGCR VQFN RGC 64 2000 336.6 336.6 28.6

ADS5282IRGCT VQFN RGC 64 250 336.6 336.6 28.6

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

Pack Materials-Page 2

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