LTC2630ISC6-LM12#TRPBF - Linear Technology Corporation

LTC2630

2630ff

Block Diagram

Features

applications

Description

Single 12-/10-/8-Bit

Rail-to- Rail DACs with 10ppm/°C

Reference in SC70

The LTC

2630 is a family of 12-, 10-, and 8-bit voltage-

output DACs with an integrated, high-accuracy, low-drift

reference in a 6-lead SC70 package. It has a rail-to-rail

output buffer and is guaranteed monotonic.

The LTC2630-L has a full-scale output of 2.5V, and

operates from a single 2.7V to 5.5V supply. The

LTC2630-H has a full-scale output of 4.096V, and operates

from a 4.5V to 5.5V supply. Each DAC can also operate in

supply as reference mode, which sets the full-scale output

to the supply voltage.

The parts use a simple SPI/MICROWIRE™ compatible

3-wire serial interface which operates at clock rates up

to 50MHz.

The LTC2630 incorporates a power-on reset circuit. Op-

tions are available for reset to zero or reset to mid-scale

after power-up.

L, LT, LTC, LTM , Linear Technology and the Linear logo are registered trademarks of Linear

Technology Corporation. All other trademarks are the property of their respective owners.

Protected by U.S. Patents, including 5396245, 5859606, 6891433, 6937178 and 7414561.

Integral Nonlinearity (LTC2630A-LZ12)

n Integrated Precision Reference

2.5V Full Scale 10ppm/°C (LTC2630-L)

4.096V Full Scale 10ppm/°C (LTC2630-H)

n Maximum INL Error: 1 LSB (LTC2630A-12)

n Low Noise: 0.7mVP-P, 0.1Hz to 200kHz

n Guaranteed Monotonic over Temperature

n Selectable Internal Reference or Supply as Reference

n 2.7V to 5.5V Supply Range (LTC2630-L)

n Low Power Operation: 180µA at 3V

n Power Down to 1.8µA Maximum (C and I Grades)

n Power-on Reset to Zero or Mid-Scale Options

n SPI Serial Interface

n Double-Buffered Data Latches

n Tiny 6-Lead SC70 Package

n Mobile Communications

n Process Control and Industrial Automation

n Automatic Test Equipment

n Portable Equipment

n Automotive

DAC

RESISTOR

DIVIDER

INTERNAL

REFERENCE

INPUT

24-BIT

SHIFT

DAC VOUT

CONTROL

DECODE LOGIC

CS/LD

VCC

GND

DACREF

2630 BD

SCK

SDI

CODE

INL (LSB)

0.5

4095

2630 TA03

–0.5

–1.0 1024 2048 3072

1.0 VCC = 3V

VFS = 2.5V

LTC2630

2630ff

CS/LD 1

SCK 2

SDI 3

6 VOUT

5 GND

4 VCC

TOP VIEW

SC6 PACKAGE

6-LEAD PLASTIC SC70

TJMAX = 150°C (Note 6), θJA = 300°C/W

aBsolute maximum ratings

Supply Voltage (VCC) ...................................–0.3V to 6V

CS/LD, SCK, SDI ..........................................–0.3V to 6V

VOUT ..................................–0.3V to min(VCC + 0.3V, 6V)

Operating Temperature Range

LTC2630C ................................................ 0°C to 70°C

LTC2630I .............................................–40°C to 85°C

LTC2630H (Note 3) ............................ –40°C to 125°C

Maximum Junction Temperature .......................... 150°C

Storage Temperature Range ..................–65°C to 150°C

Lead Temperature (Soldering, 10 sec) ...................300°C

(Notes 1, 2)

orDer inFormation

pin conFiguration

LTC2630 A C SC6 –L M 12 #TRM PBF

LEAD FREE DESIGNATOR

TAPE AND REEL

TR = 2,500-Piece Tape and Reel

TRM = 500-Piece Tape and Reel

RESOLUTION

12 = 12-Bit

10 = 10-Bit

8 = 8-Bit

POWER-ON RESET

M = Reset to Mid-Scale

Z = Reset to Zero-Scale

FULL-SCALE VOLTAGE, INTERNAL REFERENCE MODE

L = 2.5V

H = 4.096V

PACKAGE TYPE

SC6 = 6-Lead SC70

TEMPERATURE GRADE

C = Commercial Temperature Range (0°C to 70°C)

I = Industrial Temperature Range (–40°C to 85°C)

H = Automotive Temperature Range (–40°C to 125°C)

ELECTRICAL GRADE (OPTIONAL)

A = ±1 LSB Maximum INL (12-Bit)

PRODUCT PART NUMBER

Consult LTC Marketing for information on non-standard lead based finish parts.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

LTC2630

2630ff

proDuct selection guiDe

PART NUMBER PART MARKING* VFS WITH INTERNAL REFERENCE POWER-ON RESET TO CODE RESOLUTION VCC MAXIMUM INL

LTC2630A-LM12

LTC2630A-LZ12

LTC2630A-HM12

LTC2630A-HZ12

LCZB

LCSB

LCWR

LCZC

2.5V • (4095/4096)

4.096V • (4095/4096)

Mid-Scale

Zero

Mid-Scale

Zero

12-Bit

2.7V–5.5V

4.5V–5.5V

±1LSB

LTC2630-LM12

LTC2630-LM10

LTC2630-LM8

LCZB

LCZF

LCYW

2.5V • (4095/4096)

2.5V • (1023/1024)

2.5V • (255/256)

Mid-Scale

12-Bit

10-Bit

8-Bit

2.7V–5.5V

±2LSB

±1LSB

±0.5LSB

LTC2630-LZ12

LTC2630-LZ10

LTC2630-LZ8

LCSB

LCZD

LCYV

2.5V • (4095/4096)

2.5V • (1023/1024)

2.5V • (255/256)

Zero

12-Bit

10-Bit

8-Bit

2.7V–5.5V

±2LSB

±1LSB

±0.5LSB

LTC2630-HM12

LTC2630-HM10

LTC2630-HM8

LCWR

LCZH

LCYY

4.096V • (4095/4096)

4.096V • (1023/1024)

4.096V • (255/256)

Mid-Scale

12-Bit

10-Bit

8-Bit

4.5V–5.5V

±2LSB

±1LSB

±0.5LSB

LTC2630-HZ12

LTC2630-HZ10

LTC2630-HZ8

LCZC

LCZG

LCYX

4.096V • (4095/4096)

4.096V • (1023/1024)

4.096V • (255/256)

Zero

12-Bit

10-Bit

8-Bit

4.5V–5.5V

±2LSB

±1LSB

±0.5LSB

*The temperature grade is identified by a label on the shipping container.

LTC2630

2630ff

electrical characteristics

SYMBOL PARAMETER CONDITIONS

LTC2630-8 LTC2630-10 LTC2630-12 LTC2630A-12

UNITS

MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX

DC Performance

Resolution l8 10 12 12 Bits

Monotonicity VCC = 3V, Internal Ref. (Note 4) l8 10 12 12 Bits

DNL Differential Nonlinearity VCC = 3V, Internal Ref. (Note 4) l±0.5 ±0.5 ±1 ±1 LSB

INL Integral Nonlinearity VCC = 3V, Internal Ref. (Note 4) l±0.05 ±0.5 ±0.2 ±1 ±1 ±2 ±0.5 ±1 LSB

ZSE Zero Scale Error VCC = 3V, Internal Ref., Code = 0 l0.5 5 0.5 5 0.5 5 0.5 5 mV

VOS Offset Error VCC = 3V, Internal Ref. (Note 5) l±0.5 ±5 ±0.5 ±5 ±0.5 ±5 ±0.5 ±5 mV

VOSTC VOS Temperature

Coefficient

VCC = 3V, Internal Ref. (Note 5) ±10 ±10 ±10 ±10 µV/°C

FSE Full Scale Error VCC = 3V, Internal Ref. l±0.2 ±0.8 ±0.2 ±0.8 ±0.2 ±0.8 ±0.2 ±0.8 %FSR

VFSTC Full Scale Voltage

Temperature

Coefficient

VCC = 3V, Internal Ref. (Note 10)

C-Grade

I-Grade

H-Grade

±10

ppm/°C

Load Regulation Internal Ref., Mid-Scale,

VCC = 3V ±10%, –5mA ≤ IOUT ≤ 5mA

VCC = 5V ±10%, –10mA ≤ IOUT ≤ 10mA

0.008

0.016

0.03

0.064

0.13

0.256

0.13

0.256

LSB/mA

ROUT DC Output Impedance Internal Ref., Mid-Scale,

VCC = 3V ±10%, –5mA ≤ IOUT ≤ 5mA

VCC = 5V ±10%, –10mA ≤ IOUT ≤ 10mA

0.08

0.156

0.08

0.156

0.08

0.156

0.08

0.156

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise specified.

LTC2630-LM12/-LM10/-LM8/-LZ12/-LZ10/-LZ8, LTC2630A-LM12/-LZ12 (VFS = 2.5V)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VOUT DAC Output Span Supply as Reference

Internal Reference

0V to VCC

0V to 2.5

PSR Power Supply Rejection VCC = 3V ±10% or 5V ±10% –80 dB

ISC Short Circuit Output Current (Note 6)

Sinking

Sourcing

VFS = VCC = 5.5V

Zero Scale; VOUT Shorted to VCC

Full Scale; VOUT Shorted to GND

–28

–50

Power Supply

VCC Power Supply Voltage For Specified Performance l2.7 5.5 V

ICC Supply Current (Note 7) VCC = 3V, Supply as Reference

VCC = 3V, Internal Reference

VCC = 5V, Supply as Reference

VCC = 5V, Internal Reference

160

180

190

220

240

250

260

µA

ISD Supply Current in Power-Down Mode

(Note 7)

VCC = 5V, C-Grade, I-Grade

VCC = 5V, H-Grade

0.36

1.8

µA

Digital I/O

VIH Digital Input High Voltage VCC = 3.6V to 5.5V

VCC = 2.7V to 3.6V

2.4

2.0

VIL Digital Input Low Voltage VCC = 4.5V to 5.5V

VCC = 2.7V to 4.5V

0.8

0.6

ILK Digital Input Leakage VIN = GND to VCC l±1 µA

CIN Digital Input Capacitance (Note 8) l2.5 pF

LTC2630

2630ff

electrical characteristics

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V, VOUT unloaded unless otherwise specified.

LTC2630-LM12/-LM10/-LM8/-LZ12/-LZ10/-LZ8, LTC2630A-LM12/-LZ12 (VFS = 2.5V)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

AC Performance

tSSettling Time VCC = 3V (Note 9)

±0.39% (±1LSB at 8 Bits)

±0.098% (±1LSB at 10 Bits)

±0.024% (±1LSB at 12 Bits)

3.2

3.9

4.4

µs

Voltage Output Slew Rate 1.0 V/µs

Capacitive Load Driving 500 pF

Glitch Impulse At Mid-Scale Transition 2 nV•s

enOutput Voltage Noise Density At f = 1kHz, Supply as Reference

At f = 10kHz, Supply as Reference

At f = 1kHz, Internal Reference

At f = 10kHz, Internal Reference

140

130

160

150

nV/√Hz

Output Voltage Noise 0.1Hz to 10Hz, Supply as Reference

0.1Hz to 10Hz, Internal Reference

0.1Hz to 200kHz, Supply as Reference

0.1Hz to 200kHz, Internal Reference

650

700

µVP-P

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

t1SDI Valid to SCK Setup l4 ns

t2SDI Valid to SCK Hold l4 ns

t3SCK High Time l9 ns

t4SCK Low Time l9 ns

t5CS/LD Pulse width l10 ns

t6SCK High to CS/LD High l7 ns

t7CS/LD Low to SCK High l7 ns

t10 CS/LD High to SCK Positive Edge l7 ns

SCK Frequency 50% Duty Cycle l50 MHz

timing characteristics

The l denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V. (See Figure 1) (Note 8).

LTC2630-LM12/-LM10/-LM8/-LZ12/-LZ10/-LZ8, LTC2630A-LM12/-LZ12 (VFS = 2.5V)

LTC2630

2630ff

electrical characteristics

SYMBOL PARAMETER CONDITIONS

LTC2630-8 LTC2630-10 LTC2630-12 LTC2630A-12

UNITS

MIN TYP MAX MIN TYP MAX MIN TYP MAX MIN TYP MAX

DC Performance

Resolution l8 10 12 12 Bits

Monotonicity VCC = 5V, Internal Ref. (Note 4) l8 10 12 12 Bits

DNL Differential Nonlinearity VCC = 5V, Internal Ref. (Note 4) l±0.5 ±0.5 ±1 ±1 LSB

INL Integral Nonlinearity VCC = 5V, Internal Ref. (Note 4) l±0.05 ±0.5 ±0.2 ±1 ±1 ±2 ±0.5 ±1 LSB

ZSE Zero Scale Error VCC = 5V, Internal Ref., Code = 0 l0.5 5 0.5 5 0.5 5 0.5 5 mV

VOS Offset Error VCC = 5V, Internal Ref. (Note 5) l±0.5 ±5 ±0.5 ±5 ±0.5 ±5 ±0.5 ±5 mV

VOSTC VOS Temperature

Coefficient

VCC = 5V, Internal Ref. (Note 5) ±10 ±10 ±10 ±10 µV/°C

FSE Full Scale Error VCC = 5V, Internal Ref. l±0.2 ±0.8 ±0.2 ±0.8 ±0.2 ±0.8 ±0.2 ±0.8 %FSR

VFSTC Full Scale Voltage

Temperature

Coefficient

VCC = 5V, Internal Ref. (Note 10)

C-Grade

I-Grade

H-Grade

±10

ppm/°C

Load Regulation VCC = 5V ±10%, Internal Ref.,

Mid-Scale, –10mA ≤ IOUT ≤ 10mA

l0.006 0.01 0.025 0.04 0.10 0.16 0.10 0.16 LSB/

ROUT DC Output Impedance VCC = 5V ±10%, Internal Ref.,

Mid-Scale, –10mA ≤ IOUT ≤ 10mA

l0.1 0.156 0.1 0.156 0.1 0.156 0.1 0.156 Ω

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise specified.

LTC2630-HM12/-HM10/-HM8/-HZ12/-HZ10/-HZ8, LTC2630A-HM12/-HZ12 (VFS = 4.096V)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VOUT DAC Output Span Supply as Reference

Internal Reference

0V to VCC

0V to 4.096

PSR Power Supply Rejection VCC = 5V ±10% –80 dB

ISC Short Circuit Output Current (Note 6)

Sinking

Sourcing

VFS = VCC = 5.5V

Zero Scale; VOUT Shorted to VCC

Full Scale; VOUT Shorted to GND

–28

–50

Power Supply

VCC Power Supply Voltage For Specified Performance l4.5 5.5 V

ICC Supply Current (Note 7) VCC = 5V, Supply as Reference

VCC = 5V, Internal Reference

180

200

260

280

µA

ISD Supply Current in Power-Down Mode

(Note 7)

VCC = 5V, C-Grade, I-Grade

VCC = 5V, H-Grade

0.36

1.8

µA

Digital I/O

VIH Digital Input High Voltage l2.4 V

VIL Digital Input Low Voltage l0.8 V

ILK Digital Input Leakage VIN = GND to VCC l±1 µA

CIN Digital Input Capacitance (Note 8) l2.5 pF

LTC2630

2630ff

electrical characteristics

The l denotes the specifications which apply over the full operating

temperature range, otherwise specifications are at TA = 25°C. VCC = 4.5V to 5.5V, VOUT unloaded unless otherwise specified.

LTC2630-HM12/-HM10/-HM8/-HZ12/-HZ10/-HZ8, LTC2630A-HM12/-HZ12 (VFS = 4.096V)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

AC Performance

tSSettling Time VCC = 5V (Note 9)

±0.39% (±1LSB at 8 Bits)

±0.098% (±1LSB at 10 Bits)

±0.024% (±1LSB at 12 Bits)

3.7

4.4

4.8

µs

Voltage Output Slew Rate 1.0 V/µs

Capacitive Load Driving 500 pF

Glitch Impulse At Mid-Scale Transition 2.4 nV•s

enOutput Voltage Noise Density At f = 1kHz, Supply as Reference

At f = 10kHz, Supply as Reference

At f = 1kHz, Internal Reference

At f = 10kHz, Internal Reference

140

130

210

200

nV/√Hz

Output Voltage Noise 0.1Hz to 10Hz, Supply as Reference

0.1Hz to 10Hz, Internal Reference

0.1Hz to 200kHz, Supply as Reference

0.1Hz to 200kHz, Internal Reference

650

750

µVP-P

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: All voltages are with respect to GND.

Note 3: High temperatures degrade operating lifetimes. Operating lifetime

is derated at temperatures greater than 105°C.

Note 4: Linearity and monotonicity are defined from code kL to code 2N–1,

where N is the resolution and kL is given by kL = 0.016 • (2N/ VFS), rounded

to the nearest whole code. For VFS = 2.5V and N = 12, kL = 26 and linearity

is defined from code 26 to code 4,095. For VFS = 4.096V and

N = 12, kL = 16 and linearity is defined from code 16 to code 4,095.

Note 5: Inferred from measurement at code 16 (LTC2630-12), code 4

(LTC2630-10) or code 1 (LTC2630-8).

Note 6: This IC includes current limiting that is intended to protect the

device during momentary overload conditions. Junction temperature can

exceed the rated maximum during current limiting. Continuous operation

above the specified maximum operating junction temperature may impair

device reliability.

Note 7: Digital inputs at 0V or VCC.

Note 8: Guaranteed by design and not production tested.

Note 9: Internal Reference mode. DAC is stepped 1/4 scale to 3/4 scale

and 3/4 scale to 1/4 scale. Load is 2kW in parallel with 100pF to GND.

Note 10: Temperature coefficient is calculated by dividing the maximum

change in output voltage by the specified temperature range.

timing characteristics

The l denotes the specifications which apply over the full operating temperature

range, otherwise specifications are at TA = 25°C. VCC = 4.5V to 5.5V. (See Figure 1) (Note 8).

LTC2630-HM12/-HM10/-HM8/-HZ12/-HZ10/-HZ8, LTC2630A-HM12/-HZ12 (VFS = 4.096V)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

t1SDI Valid to SCK Setup l4 ns

t2SDI Valid to SCK Hold l4 ns

t3SCK High Time l9 ns

t4SCK Low Time l9 ns

t5CS/LD Pulse width l10 ns

t6SCK High to CS/LD High l7 ns

t7CS/LD Low to SCK High l7 ns

t10 CS/LD High to SCK Positive Edge l7 ns

SCK Frequency 50% Duty Cycle l50 MHz

LTC2630

2630ff

typical perFormance characteristics

INL vs Temperature

DNL vs Temperature

Full-Scale Output Voltage

vs Temperature

LTC2630-LM12/-LZ12 (VFS = 2.5V)

Integral Nonlinearity (INL)

CODE

INL (LSB)

0.5

4095

2630 G01

–0.5

–1.0 1024 2048 3072

1.0 VCC = 3V

Differential Nonlinearity (DNL)

CODE

DNL (LSB)

0.5

4095

2630 G02

–0.5

–1.0 1024

VCC = 3V

2048 3072

1.0

TEMPERATURE (°C)

–50 –25 25 75 125

INL (LSB)

0.5

150

2630 G03

–0.5

–1.0 050 100

1.0

VCC = 3V

INL (POS)

INL (NEG)

TEMPERATURE (°C)

–50 –25 25 75 125

DNL (LSB)

0.5

150

2630 G04

–0.5

–1.0 050 100

1.0

VCC = 3V

DNL (POS)

DNL (NEG)

TEMPERATURE (°C)

–50 –25 25 75 125

FS OUTPUT VOLTAGE (V)

2.50

2.51

150

2630 G05

2.49

2.48 050 100

2.52

VCC = 3V

2µs/DIV

2630 G06

VOUT

1LSB/DIV

1/4 SCALE TO 3/4 SCALE STEP

VCC = 3V, VFS = 2.5V

RL = 2k, CL = 100pF

AVERAGE OF 256 EVENTS

CS/LD

2V/DIV

3.6µs

Settling to ±1LSB Settling to ±1LSB

2µs/DIV

2630 G07

VOUT

1LSB/DIV

3/4 SCALE TO 1/4 SCALE STEP

VCC = 3V, VFS = 2.5V

RL = 2k, CL = 100pF

AVERAGE OF 256 EVENTS

CS/LD

2V/DIV

4.4µs

LTC2630

2630ff

TEMPERATURE (°C)

–50 –25 25 75 125

FS OUTPUT VOLTAGE (V)

4.095

4.105

150

2630 G12

4.085

4.075 050 100

4.115

VCC = 5V

2µs/DIV

2630 G13

VOUT

1LSB/DIV

1/4 SCALE TO 3/4 SCALE STEP

VCC = 5V, VFS = 4.096V

RL = 2k, CL = 100pF

AVERAGE OF 256 EVENTS

CS/LD

2V/DIV

4.0µs

Settling to ±1LSB

2µs/DIV

2630 G14

VOUT

1LSB/DIV

CS/LD

2V/DIV

4.8µs

1/4 SCALE TO 3/4 SCALE STEP

VCC = 5V, VFS = 4.096V

RL = 2k, CL = 100pF

AVERAGE OF 256 EVENTS

Settling to ±1LSB

typical perFormance characteristics

INL vs Temperature

DNL vs Temperature

Full-Scale Output Voltage

vs Temperature

LTC2630-HM12/-HZ12 (VFS = 4.096V)

Integral Nonlinearity (INL)

Differential Nonlinearity (DNL)

CODE

DNL (LSB)

0.5

4095

2630 G09

–0.5

–1.0 1024 2048 3072

1.0 VCC = 5V

CODE

INL (LSB)

0.5

4095

2630 G08

–0.5

–1.0 1024 2048 3072

1.0 VCC = 5V

TEMPERATURE (°C)

–50 –25 25 75 125

INL (LSB)

0.5

150

2630 G10

–0.5

–1.0 050 100

1.0

VCC = 5V

INL (POS)

INL (NEG)

TEMPERATURE (°C)

–50 –25 25 75 125

DNL (LSB)

0.5

150

2630 G11

–0.5

–1.0 050 100

1.0

VCC = 5V

DNL (POS)

DNL (NEG)

LTC2630

2630ff

TEMPERATURE (°C)

–50 –25 0 25 50 75 100 125 150

OFFSET ERROR (mV)

2630 G21

–1

–2

–3

IOUT (mA)

–30 –20 –10 0 10 20 30

ΔVOUT (mV)

2630 G19

–6

–4

–2

–8

–10

INTERNAL REF.

CODE = MIDSCALE

VCC = 5V (LTC2630-H)

VCC = 5V (LTC2630-L)

VCC = 3V (LTC2630-L)

typical perFormance characteristics

LTC2630-10

LTC2630-8

LTC2630

Integral Nonlinearity (INL)

Differential Nonlinearity (DNL)

Integral Nonlinearity (INL)

CODE

INL (LSB)

0.5

255

2630 G17

–0.5

–1.0 64 128 192

1.0 VCC = 3V

VFS = 2.5V

CODE

DNL (LSB)

0.5

1023

2630 G16

–0.5

–1.0 256 512 768

1.0 VCC = 5V

VFS = 4.096V

Differential Nonlinearity (DNL)

CODE

DNL (LSB)

0.25

255

2630 G18

–0.25

–0.50 64 128 192

0.50 VCC = 3V

VFS = 2.5V

CODE

INL (LSB)

0.5

1023

2630 G15

–0.5

–1.0 256 512 768

1.0 VCC = 5V

VFS = 4.096V

IOUT (mA)

–30 –20 –10 0 10 20 30

∆VOUT (V)

–0.05

0.05

0.10

0.15

2630 G20

–0.20

–0.15

–0.10

0.20

INTERNAL REF.

CODE = MIDSCALE

VCC = 5V (LTC2630-H)

VCC = 5V (LTC2630-L)

VCC = 3V (LTC2630-L)

Offset Error vs Temperature

Current Limiting

Load Regulation

LTC2630

2630ff

2µs/DIV

0.5V/DIV

2630 G22

VFS = VCC = 5V

1/4 SCALE TO 3/4 SCALE

typical perFormance characteristics

LTC2630

Large-Signal Response

IOUT (mA)

0 1 2 3 4 5 6 7 8 9 10

VOUT (V)

2.5

2.0

3.5

3.0

4.0

2630 G25

1.5

1.0

0.5

5.0

4.5 5V SOURCING

3V (LTC2630-L) SOURCING

3V (LTC2630-L) SINKING

5V SINKING

Headroom at Rails

vs Output Current

0.1Hz to 10Hz Voltage Noise

LOGIC VOLTAGE (V)

0 1 2 3 4 5

ICC (mA)

0.4

0.6

0.8

2630 G29

0.2

1.0

VCC = 5V

VCC = 3V

(LTC2630-L)

SWEEP SCK, SDI, CS/LD

BETWEEN 0V AND VCC

Supply Current vs Logic Voltage

1s/DIV

10µV/DIV

2630 G27

VCC = 4V, VFS = 2.5V

CODE = MIDSCALE

Noise Voltage vs Frequency

2µs/DIV

LTC2630-H12, VCC = 5V:

2.4nV-s TYP

LTC2630-L12, VCC = 3V:

2.0nV-s TYP

VOUT

5mV/DIV

2630 G23

CS/LD

5V/DIV

INTERNAL REF

Mid-Scale-Glitch Impulse

Power-On Reset Glitch

200µs/DIV

VCC

2V/DIV

2630 G24

LTC2630-L

VOUT

2mV/DIV

ZERO-SCALE

FREQUENCY (Hz)

100

NOISE VOLTAGE (nV/√Hz)

200

300

2630 G26

100

01k 10k 100k

500

400

CODE = MIDSCALE

LTC2630-H

(VCC = 5V)

LTC2630-L

(VCC = 4V)

Exiting Power-Down to Mid-Scale

4µs/DIV

2630 G28

LTC2630-H

CS/LD

2V/DIV

VOUT

0.5V/DIV

LTC2630

2630ff

Block Diagram

pin Functions

CS/LD (Pin 1): Serial Interface Chip Select/Load Input.

When CS/LD is low, SCK is enabled for shifting data on

SDI into the register. When CS/LD is taken high, SCK

is disabled and the specified command (see Table 1) is

executed.

SCK (Pin 2): Serial Interface Clock Input. CMOS and TTL

compatible.

SDI (Pin 3): Serial Interface Data Input. Data on SDI

is clocked into the DAC on the rising edge of SCK. The

LTC2630 accepts input word lengths of either 24 or 32 bits.

VCC (Pin 4): Supply Voltage Input. 2.7V ≤ VCC ≤ 5.5V

(LTC2630-L) or 4.5V ≤ VCC ≤ 5.5V (LTC2630-H). Also

used as the reference input when the part is programmed

to operate in supply as reference mode. Bypass to GND

with a 0.1µF capacitor.

GND (Pin 5): Ground.

VOUT (Pin 6): DAC Analog Voltage Output.

DAC

RESISTOR

DIVIDER

INTERNAL

REFERENCE

INPUT

24-BIT

SHIFT

DAC VOUT

CONTROL

DECODE LOGIC

CS/LD

VCC

GND

DACREF

2630 BD

SCK

SDI

LTC2630

2630ff

timing Diagram

The LTC2630 is a family of single voltage output DACs in

6-lead SC70 packages. Each DAC can operate rail-to-rail

referenced to the input supply, or with its full-scale voltage

set by an integrated reference. Twelve combinations of

accuracy (12-, 10-, and 8-bit), power-on reset value (zero

or mid-scale), and full-scale voltage (2.5V or 4.096V) are

available. The LTC2630 is controlled using a 3-wire SPI/

MICROWIRE compatible interface.

Power-On Reset

The LTC2630-HZ/-LZ clear the output to zero scale when

power is first applied, making system initialization con-

sistent and repeatable.

For some applications, downstream circuits are active

during DAC power-up, and may be sensitive to nonzero

outputs from the DAC during this time. The LTC2630

contains circuitry to reduce the power-on glitch: the

analog output typically rises less than 5mV above zero

scale during power on if the power supply is ramped

to 5V in 1ms or more. In general, the glitch amplitude

decreases as the power supply ramp time is increased.

See “Power-On Reset Glitch” in the Typical Performance

Characteristics section.

The LTC2630-HM/-LM provide an alternative reset, set-

ting the output to mid-scale when power is first applied.

SDI

CS/LD

SCK

t10

t5t7

t3t4

1 2 3 23 24

2630 F01

operation

Transfer Function

The digital-to-analog transfer function is

VOUT(IDEAL) =k









VREF

where k is the decimal equivalent of the binary DAC

input code, N is the resolution, and VREF is either 2.5V

(LTC2630-L) or 4.096V (LTC2630-H) in internal refer-

ence mode, and VCC in Supply as reference mode.

Table 1. Command Codes

Command*

C3 C2 C1 C0

0 0 0 0 Write to Input Register

0 0 0 1 Update (Power up) DAC Register

0 0 1 1 Write to and Update (Power up) DAC Register

0 1 0 0 Power down

0 1 1 0 Select Internal Reference (Power-on Reset Default)

0 1 1 1 Select Supply as Reference (VREF = VCC)

*Command codes not shown are reserved and should not be used.

Figure 1. Serial Interface Timing

LTC2630

2630ff

Serial Interface

The CS/LD input is level triggered. When this input is taken

low, it acts as a chip-select signal, enabling the SDI and

SCK buffers and the input shift register. Data (SDI input)

is transferred at the next 24 rising SCK edges. The 4-bit

command, C3-C0, is loaded first; then 4 don’t-care bits;

and finally the 16-bit data word. The data word comprises

the 12-, 10- or 8-bit input code, ordered MSB-to-LSB, fol-

lowed by 4, 6 or 8 don’t-care bits (LTC2630-12, -10 and

-8 respectively; see Figure 2). Data can only be transferred

to the device when the CS/LD signal is low, beginning on

the first rising edge of SCK. SCK may be high or low at

the falling edge of CS/LD. The rising edge of CS/LD ends

the data transfer and causes the device to execute the

command specified in the 24-bit input sequence. The

complete sequence is shown in Figure 3a.

operation

The command (C3-C0) assignments are shown in Table 1.

The first three commands in the table consist of write and

update operations. A Write operation loads a 16-bit data

word from the 24-bit shift register into the input register.

In an Update operation, the input register is copied to the

DAC register and converted to an analog voltage at the

DAC output. Write to and Update combines the first two

commands. The Update operation also powers up the

DAC if it had been in power-down mode. The data path

and registers are shown in the Block Diagram.

While the minimum input sequence is 24-bits, it may

optionally be extended to 32-bits to accommodate micro-

processors that have a minimum word width of 16-bits

(2 bytes). To use the 32-bit width, 8 don’t-care bits are

transferred to the device first, followed by the 24-bit se-

quence described. Figure 3b shows the 32-bit sequence.

2630 F02

COMMAND 4 DON'T-CARE BITS

MSB

LSB

DATA (12 BITS + 4 DON'T-CARE BITS)

C2 C1 C0 X X X X D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X

COMMAND 4 DON'T-CARE BITS DATA (10 BITS + 6 DON'T-CARE BITS)

C2 C1 C0 X X X X D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X

COMMAND

INPUT WORD (LTC2630-12)

INPUT WORD (LTC2630-10)

INPUT WORD (LTC2630-8)

4 DON'T-CARE BITS DATA (8 BITS + 8 DON'T-CARE BITS)

C2 C1 C0 X X X X D7 D6 D5 D4 D3 D2 D1 D0 X X X X X X X X

Figure 2. Command and Data Input Format

LTC2630

2630ff

The 16-bit data word is ignored for all commands that do

not include a Write operation.

Power-Down Mode

For power-constrained applications, power-down mode

can be used to reduce the supply current whenever the

DAC output is not needed. When in power-down, the buffer

amplifier, bias circuit, and reference circuit are disabled

and draw essentially zero current. The DAC output is put

into a high-impedance state, and the output pin is passively

pulled to ground through a 200kΩ resistor. Input and DAC

The DAC can be put into power-down mode by using

command 0100. The supply current is reduced to 1.8µA

maximum when the DAC is powered down.

Normal operation resumes after executing any command

that includes a DAC update, as shown in Table 1. The DAC

is powered up and its voltage output is updated. Normal

settling is delayed while the bias, reference, and amplifier

circuits are re-enabled. The power-up delay time is 18µs

for settling to 12-bits.

Reference Modes

For applications where an accurate external reference is not

available, the LTC2630 has a user-selectable, integrated

reference. The LTC2630-LM and LTC2630-LZ provide a

full-scale output of 2.5V. The LTC2630-HM and LTC2630-

HZ provide a full-scale output of 4.096V.

The internal reference can be useful in applications where

the supply voltage is poorly regulated. Internal Reference

mode can be selected by using command 0110, and is

the power-on default.

The DAC can also operate in supply as reference mode

using command 0111. In this mode, VCC supplies the

DAC’s reference voltage and the supply current is reduced.

Voltage Output

The LTC2630’s integrated rail-to-rail amplifier has guar-

anteed load regulation when sourcing or sinking up to

10mA at 5V, and 5mA at 3V.

Load regulation is a measure of the amplifier’s ability to

maintain the rated voltage accuracy over a wide range of

load current. The measured change in output voltage per

change in forced load current is expressed in LSB/mA.

DC output impedance is equivalent to load regulation, and

may be derived from it by simply calculating a change in

units from LSB/mA to ohms. The amplifier’s DC output

impedance is 0.1Ω when driving a load well away from

the rails.

When drawing a load current from either rail, the output

voltage headroom with respect to that rail is limited by

the 50Ω typical channel resistance of the output devices

(e.g., when sinking 1mA, the minimum output voltage is

50Ω • 1mA, or 50mV). See the graph “Headroom at Rails

vs. Output Current” in the Typical Performance Charac-

teristics section.

The amplifier is stable driving capacitive loads of up to

500pF.

operation

LTC2630

2630ff

operation

Rail-to-Rail Output Considerations

In any rail-to-rail voltage output device, the output is limited

to voltages within the supply range.

Since the analog output of the DAC cannot go below ground,

it may limit for the lowest codes as shown in Figure 4b.

Similarly, limiting can occur near full scale when using the

supply as reference. If VFS = VCC and the DAC full-scale

error (FSE) is positive, the output for the highest codes

limits at VCC, as shown in Figure 4. No full-scale limiting

can occur if VFS is less than VCC–FSE.

Offset and linearity are defined and tested over the region

of the DAC transfer function where no output limiting can

occur.

Board Layout

The PC board should have separate areas for the analog and

digital sections of the circuit. A single, solid ground plane

should be used, with analog and digital signals carefully

routed over separate areas of the plane. This keeps digital

signals away from sensitive analog signals and minimizes

the interaction between digital ground currents and the

analog section of the ground plane. The resistance from

the LTC2630 GND pin to the ground plane should be as

low as possible. Resistance here will add directly to the

effective DC output impedance of the device (typically

0.1Ω). Note that the LTC2630 is no more susceptible to

this effect than any other parts of this type; on the con-

trary, it allows layout-based performance improvements

to shine rather than limiting attainable performance with

excessive internal resistance.

Another technique for minimizing errors is to use a sepa-

rate power ground return trace on another board layer.

The trace should run between the point where the power

supply is connected to the board and the DAC ground pin.

Thus the DAC ground pin becomes the common point for

analog ground, digital ground, and power ground. When

the LTC2630 is sinking large currents, this current flows

out the ground pin and directly to the power ground trace

without affecting the analog ground plane voltage.

It is sometimes necessary to interrupt the ground plane

to confine digital ground currents to the digital portion of

the plane. When doing this, make the gap in the plane only

as long as it needs to be to serve its purpose and ensure

that no traces cross over the gap.

LTC2630

2630ff

12345678910 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

C2 C1 C0 X X X X D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X XC3XXXXXXXX

CS/LD

SCK

SDI

COMMAND WORD DATA WORD

8 DON’T-CARE BITS 4 DON’T-CARE BITS

2630 F03b

32-BIT INPUT WORD

Figure 3b. 32-Bit Load Sequence

LTC2630-12 SDI Data Word: 12-Bit Input Code + 4 Don’t-Care Bits (Shown);

LTC2630-10 SDI Data Word: 10-Bit Input Code + 6 Don’t-Care Bits;

LTC2630-8 SDI Data Word: 8-Bit Input Code + 8 Don’t-Care Bits

12345678910 11 12 13 14 15 16 17 18 19 20 21 22 23 24

C2 C1 C0 X X X X D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X X XC3

CS/LD

SCK

SDI

COMMAND WORD 4 DON’T-CARE BITS DATA WORD

24-BIT INPUT WORD

2630 F03a

Figure 3a. 24-Bit Load Sequence (Minimum Input Word)

LTC2630-12 SDI Data Word: 12-Bit Input Code + 4 Don’t-Care Bits (Shown);

LTC2630-10 SDI Data Word: 10-Bit Input Code + 6 Don’t-Care Bits;

LTC2630-8 SDI Data Word: 8-Bit Input Code + 8 Don’t-Care Bits

operation

Optoisolated 4mA to 20mA Process Controller

Figure 5 shows how to use an LTC2630HZ to make an

optoisolated, digitally-controlled 4mA to 20mA transmit-

ter. The transmitter circuitry, including optoisolation, is

5.4V to 80V. The 5V output of the LT

3010-5 is used to

set the 4mA offset current and VOUT is used to digitally

control the 0mA to 16mA signal current. The supply cur-

rent for the regulator, DAC, and op amp is well below

the 4mA budget at zero scale. RS senses the total loop

current, which includes the quiescent supply current and

additional current through Q1. Note that at the maximum

loop voltage of 80V, Q1 will dissipate 1.6W when IOUT =

20mA and must have an appropriate heat sink.

ROFFSET and RGAIN are the closest 0.1% values to ideal

for controlling a 4mA to 20mA output as the digital input

varies from zero scale to full scale. Alternatively, ROFFSET

can be a 365k, 1% resistor in series with a 20k trim pot

and RGAIN can be a 75.0k, 1% resistor in series with a 5k

trim pot. The optoisolators shown will limit the speed of

the serial bus; the 6N139 is an alternative that will allow

higher data rates.

LTC2630

2630ff

2630 F04

INPUT CODE

(b)

OUTPUT

VOLTAGE

NEGATIVE

OFFSET

0V 2,0480 4,095

INPUT CODE

OUTPUT

VOLTAGE

(a)

VREF = VCC

(c)

INPUT CODE

OUTPUT

VOLTAGE

POSITIVE

FSE

operation

Figure 4. Effects of Rail-to-Rail Operation on a DAC Transfer Curve (Shown for 12-Bits).

(a) Overall Transfer Function

(b) Effect of Negative Offset for Codes Near Zero

LTC2630

2630ff

SDI

SCK

CS/LD

2630 TA01

0.1µF

OUTPUT

0V TO 2.5V OR

0V TO VCC

VOUT

VCC

LTC2630-LZ12

GND

2.7V TO 5.5V

µP

typical application

12-Bit, 2.7V to 5.5V Single Supply, Voltage Output DAC

LTC2630

2630ff

SC6 Package

6-Lead Plastic SC70

(Reference LTC DWG # 05-08-1638 Rev B)

1.15 – 1.35

(NOTE 4)

1.80 – 2.40

0.15 – 0.30

6 PLCS (NOTE 3)

SC6 SC70 1205 REV B

1.80 – 2.20

(NOTE 4)

0.65 BSC

PIN 1

0.80 – 1.00

1.00 MAX

0.00 – 0.10

REF

NOTE:

1. DIMENSIONS ARE IN MILLIMETERS

2. DRAWING NOT TO SCALE

3. DIMENSIONS ARE INCLUSIVE OF PLATING

4. DIMENSIONS ARE EXCLUSIVE OF MOLD FLASH AND METAL BURR

5. MOLD FLASH SHALL NOT EXCEED 0.254mm

6. DETAILS OF THE PIN 1 IDENTIFIER ARE OPTIONAL,

BUT MUST BE LOCATED WITHIN THE INDEX AREA

7. EIAJ PACKAGE REFERENCE IS EIAJ SC-70

8. JEDEC PACKAGE REFERENCE IS MO-203 VARIATION AB

2.8 BSC

0.47

MAX

0.65

REF

RECOMMENDED SOLDER PAD LAYOUT

PER IPC CALCULATOR

1.8 REF

1.00 REF

INDEX AREA

(NOTE 6)

0.10 – 0.18

(NOTE 3)

0.26 – 0.46

GAUGE PLANE

0.15 BSC

0.10 – 0.40

SC6 Package

6-Lead Plastic SC70

(Reference LTC DWG # 05-08-1638 Rev B)

package Description

Please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.

LTC2630

2630ff

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

revision history

REV DATE DESCRIPTION PAGE NUMBER

F 06/12 Corrected units on parameter VOSTC from mV/°C to µV/°C 6

(Revision history begins at Rev F)

LTC2630

2630ff

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com

 LINEAR TECHNOLOGY CORPORATION 2007

LT 0612 REV F • PRINTED IN USA

relateD parts

typical application

SDI

SCK

CS/LD

1µF

2N3440

10Ω

IOUT

VLOOP

5.4V TO 80V

VCC

VOUT

FROM

OPTO-

ISOLATED

INPUTS

LTC2630-HZ

2630 TA02

3.01k

10k

1000PF

–

LTC2054

ROFFSET

374k

0.1%

RGAIN

76.8k

0.1%

OPTO-ISOLATORS

500Ω

10k

4N28

SDI

SCK

CS/LD

SDI

SCK

CS/LD

IN OUT

SHDN SENSE

GND

LT3010-5

Figure 5. An Optoisolated 4mA to 20mA Process Controller

PART NUMBER DESCRIPTION COMMENTS

LTC1660/LTC1665 Octal 10-/8-Bit VOUT DACs in 16-Pin Narrow SSOP VCC = 2.7V to 5.5V, Micropower, Rail-to-Rail Output

LTC1663 Single 10-Bit VOUT DAC in SOT-23 VCC = 2.7V to 5.5V, 60µA, Internal reference, SMBus Interface

LTC1664 Quad 10-Bit VOUT DAC in 16-Pin Narrow SSOP VCC = 2.7V to 5.5V, Micropower, Rail-to-Rail Output

LTC1669 Single 10-Bit VOUT DAC in SOT-23 VCC = 2.7V to 5.5V, 60µA, Internal reference, I2C Interface

LTC1821 Parallel 16-Bit Voltage Output DAC Precision 16-Bit Settling in 2µs for 10V Step

LTC2600/LTC2610/LTC2620 Octal 16-/14-/12-Bit VOUT DACs in 16-Lead SSOP 250µA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output,

SPI Serial Interface

LTC2601/LTC2611/LTC2621 Single 16-/14-/12-Bit VOUT DACs in 10-Lead DFN 300µA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output,

SPI Serial Interface

LTC2602/LTC2612/LTC2622 Dual 16-/14-/12-Bit VOUT DACs in 8-Lead MSOP 300µA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output,

SPI Serial Interface

LTC2604/LTC2614/LTC2624 Quad 16-/14-/12-Bit VOUT DACs in 16-Lead SSOP 250µA per DAC, 2.5V to 5.5V Supply Range, Rail-to-Rail Output,

SPI Serial Interface

LTC2631 Single 12-/10-/8-Bit I2C VOUT DACs with

10ppm/°C Reference in ThinSOT

180µA per DAC, 2.7V to 5.5V Supply Range, 10ppm/°C Reference,

Selectable External Ref. Mode, Rail-to-Rail Output, I2C Interface

LTC2640 Single 12-/10-/8-Bit SPI VOUT DACs with

10ppm/°C Reference in ThinSOT

180µA per DAC, 2.7V to 5.5V Supply Range, 10ppm/°C Reference,

Selectable External Ref. Mode, Rail-to-Rail Output, SPI Interface