CD4099BC - National Semiconductor

TL/F/5984

CD4099BM/CD4099BC 8-Bit Addressable Latch

February 1988

CD4099BM/CD4099BC 8-Bit Addressable Latch

General Description

The CD4099B is an 8-bit addressable latch with three ad-

dress inputs (A0–A2), an active low enable input (E), active

high clear input (CL), a data input (D), and eight outputs

(Q0–Q7).

Data is entered into a particular bit in the latch when that bit

is addressed by the address inputs and the enable (E)is

low. Data entry is inhibited when enable (E) is high.

When clear (CL) and enable (E) are high, all outputs are low.

When clear (CL) is high and enable (E) is low, the channel

demultiplexing occurs. The bit that is addressed has an ac-

tive output which follows the data input while all unad-

dressed bits are held low. When operating in the address-

able latch mode (E eCL elow), changing more than one

bit of the address could impose a transient wrong address.

Therefore, this should only be done while in the memory

mode (E ehigh, CL elow).

Features

YWide supply voltage range 3.0V to 15V

YHigh noise immunity 0.45 VDD (typ.)

YLow power TTL fan out of 2 driving 74L

compatibility or 1 driving 74LS

YSerial to parallel capability

YStorage register capability

YRandom (addressable) data entry

YActive high demultiplexing capability

YCommon active high clear

Connection Diagram

CD4099B

Dual-In-Line Package

TL/F/5984–1

Top View

Order Number CD4099B

Truth Table

Mode Selection

E CL Addressed Unaddressed Mode

Latch Latch

L L Follows Data Holds Previous Data Addressable Latch

H L Holds Previous Data Holds Previous Data Memory

L H Follows Data Reset to ‘‘0’’ Demultiplexer

H H Reset to ‘‘0’’ Reset to ‘‘0’’ Clear

C1995 National Semiconductor Corporation RRD-B30M105/Printed in U. S. A.

Absolute Maximum Ratings (Notes1&2)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales

Office/Distributors for availability and specifications.

DC Supply Voltage (VDD)b0.5 to a18 VDC

Input Voltage (VIN)b0.5 to VDD a0.5 VDC

Storage Temperature Range (TS)b65§Ctoa

150§C

Power Dissipation (PD)

Dual-In-Line 700 mW

Small Outline 500 mW

Lead Temperature (TL)

(Soldering, 10 seconds) 260§C

Recommended Operating

Conditions (Note 2)

DC Supply Voltage (VDD) 3.0 to 15 VDC

Input Voltage (VIN) 0 to VDD VDC

Operating Temperature Range (TA)

CD4099BM b55§Ctoa

125§C

CD4099BC b40§Ctoa

85§C

DC Electrical Characteristics CD4099BM (Note 2)

Symbol Parameter Conditions b55§Ca25§Ca125§CUnits

Min Max Min Typ Max Min Max

IDD Quiescent VDD e5V, VIN eVDD or VSS 5.0 0.02 5.0 150 mA

Device Current VDD e10V, VIN eVDD or VSS 10 0.02 10 300 mA

VDD e15V, VIN eVDD or VSS 20 0.02 20 600 mA

VOL Low Level

s1mA

Output Voltage VDD e5V 0.05 0 0.05 0.05 V

VDD e10V 0.05 0 0.05 0.05 V

VDD e15V 0.05 0 0.05 0.05 V

VOH High Level

s1mA

Output Voltage VDD e5V 4.95 4.95 5.0 4.95 V

VDD e10V 9.95 9.95 10 9.95 V

VDD e15V 14.95 14.95 15 14.95 V

VIL Low Level VDD e5V, VOe0.5V or 4.5V 1.5 2.25 1.5 1.5 V

Input Voltage VDD e10V, VOe1.0V or 9.0V 3.0 4.5 3.0 3.0 V

VDD e15V,VOe1.5V or 13.5V 4.0 6.75 4.0 4.0 V

VIH High Level VDD e5V, VOe0.5V or 4.5V 3.5 3.5 2.75 3.5 V

Input Voltage VDD e10V, VOe1.0V or 9.0V 7.0 7.0 5.5 7.0 V

VDD e15V, VOe1.5V or 13.5V 11.0 11.0 8.25 11.0 V

IOL Low Level Output VDD e5V, VOe0.4V 0.64 0.51 0.88 0.36 mA

Current (Note 3) VDD e10V, VOe0.5V 1.6 1.3 2.25 0.9 mA

VDD e15V, VOe1.5V 4.2 3.4 8.8 2.4 mA

IOH High Level Output VDD e5V, VOe4.6V b0.64 b0.51 b0.88 b0.36 mA

Current (Note 3) VDD e10V, VOe9.5V b1.6 b1.3 b2.25 b0.9 mA

VDD e15V, VOe13.5V b4.2 b3.4 b8.8 b2.4 mA

IIN Input Current VDD e15V, VIN e0V b0.10 b10b5b0.10 b1.0 mA

VDD e15V, VIN e15V 0.10 10b50.10 1.0 mA

DC Electrical Characteristics CD4099BC (Note 2)

Symbol Parameter Conditions b40§Ca25§Ca85§CUnits

Min Max Min Typ Max Min Max

IDD Quiescent Device VDD e5V, VIN eVDD or VSS 20 0.02 20 150 mA

Current VDD e10V, VIN eVDD or VSS 40 0.02 40 300 mA

VDD e15V, VIN eVDD or VSS 80 0.02 80 600 mA

VOL Low Level

s1mA

Output Voltage VDD e5V 0.05 0 0.05 0.05 V

VDD e10V 0.05 0 0.05 0.05 V

VDD e15V 0.05 0 0.05 0.05 V

VOH High Level

s1mA

Output Voltage VDD e5V 4.95 4.95 5 4.95 V

VDD e10V 9.95 9.95 10 9.95 V

VDD e15V 14.95 14.95 15 14.95 V

VIL Low Level VDD e5V, VOe0.5V or 4.5V 1.5 2.25 1.5 1.5 V

Input Voltage VDD e10V, VOe1.0V or 9.0V 3.0 4.5 3.0 3.0 V

VDD e15V, VOe1.5V or 13.5V 4.0 6.75 4.0 4.0 V

VIH High Level VDD e5V, VOe0.5V or 4.5V 3.5 3.5 2.75 3.5 V

Input Voltage VDD e10V, VOe1.0V or 9.0V 7.0 7.0 5.5 7.0 V

VDD e15V, VOe1.5V or 13.5V 11.0 11.0 8.25 11.0 V

DC Electrical Characteristics CD4099BC (Note 2) (Continued)

Symbol Parameter Conditions b40§Ca25§Ca85§CUnits

Min Max Min Typ Max Min Max

IOL Low Level Output VDD e5V, VOe0.4V 0.52 0.44 0.88 0.36 mA

Current (Note 3) VDD e10V, VOe0.5V 1.3 1.1 2.25 0.9 mA

VDD e15V, VOe1.5V 3.6 3.0 8.8 2.4 mA

IOH High Level Output VDD e5V, VOe4.6V b0.52 b0.44 b0.88 b0.36 mA

Current (Note 3) VDD e10V, VOe9.5V b1.3 b1.1 b2.25 b0.9 mA

VDD e15V, VOe13.5V b3.6 b3.0 b8.8 b2.4 mA

IIN Input Current VDD e15V, VIN e0V b0.30 b10b5b0.30 b1.0 mA

VDD e15V, VIN e15V 0.30 10b50.30 1.0 mA

AC Electrical Characteristics*

TAe25§C, CLe50 pF, RLe200k, Input tretfe20 ns, unless otherwise noted

Symbol Parameter Conditions Min Typ Max Units

tPHL,t

PLH Propagation Delay VDD e5V 200 400 ns

Data to Output VDD e10V 75 150 ns

VDD e15V 50 100 ns

tPLH,t

PHL Propagation Delay VDD e5V 200 400 ns

Enable to Output VDD e10V 80 160 ns

VDD e15V 60 120 ns

tPHL Propagation Delay VDD e5V 175 350 ns

Clear to Output VDD e10V 80 160 ns

VDD e15V 65 130 ns

tTLH,t

THL Propagation Delay VDD e5V 225 450 ns

Address to Output VDD e10V 100 200 ns

VDD e15V 75 150 ns

tTHL,t

TLH Transition Time VDD e5V 100 200 ns

(Any Output) VDD e10V 50 100 ns

VDD e15V 40 80 ns

TWH,T

WL Minimum Data VDD e5V 100 200 ns

Pulse Width VDD e10V 50 100 ns

VDD e15V 40 80 ns

tWH,t

WL Minimum Address VDD e5V 200 400 ns

Pulse Width VDD e10V 100 200 ns

VDD e15V 65 125 ns

tWH Minimum Clear VDD e5V 75 150 ns

Pulse Width VDD e10V 40 75 ns

VDD e15V 25 50 ns

tSU Minimum Set-Up Time VDD e5V 40 80 ns

Data to E VDD e10V 20 40 ns

VDD e15V 15 30 ns

tHMinimum Hold Time VDD e5V 60 120 ns

Data to E VDD e10V 30 60 ns

VDD e15V 25 50 ns

tSU Minimum Set-Up Time VDD e5V b15 50 ns

Address to E VDD e10V 0 30 ns

VDD e15V 0 20 ns

tHMinimum Hold Time VDD e5V b50 15 ns

Address to E VDD e10V b20 10 ns

VDD e15V b15 5 ns

CPD Power Dissipation Capacitance Per Package 100 pF

(Note 4)

CIN Input Capacitance Any Input 5.0 7.5 pF

*AC Parameters are guaranteed by DC correlated testing.

Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed; they are not meant to imply that the devices

should be operated at these limits. The tables of ‘‘Recommended Operating Condtions’’ and ‘‘Electrical Characteristics’’ provide conditions for actual device

operation.

Note 2: VSS e0V unless otherwise specified.

Note 3: IOH and IOL are tested one output at a time.

Note 4: Dynamic power dissipation (PD) is given by: PDe(CPD aCL)V

CC2faPQ; where CLeload capacitance; f efrequency of operation; for further details,

see application note AN-90, ‘‘54C/74C Family Characteristics’’.

Logic Diagram

CD4099B

TL/F/5984– 2

Switching Time Waveforms

TL/F/5984– 3

Physical Dimensions inches (millimeters)

Ceramic Dual-In-Line Package (J)

Order Number CD4099BMJ or CD4099BCJ

NS Package Number J16A

CD4099BM/CD4099BC 8-Bit Addressable Latch

Physical Dimensions inches (millimeters) (Continued)

Molded Dual-In-Line Package (N)

Order Number CD4099BMN or CD4099BCN

NS Package Number N16E

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