IDT7202LA35JG8 - Integrated Device Technology



SEPTEMBER 2002

CMOS ASYNCHRONOUS FIFO

256 x 9, 512 x 9 and 1,024 x 9

IDT7200L

IDT7201LA

IDT7202LA

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.

COMMERCIAL, INDUSTRIAL AND MILITARY TEMPERATURE RANGES

FEATURES:

••

•First-In/First-Out dual-port memory

••

•256 x 9 organization (IDT7200)

••

•512 x 9 organization (IDT7201)

••

•1,024 x 9 organization (IDT7202)

••

•Low power consumption

— Active: 440mW (max.)

—Power-down: 28mW (max.)

••

•Ultra high speed—12ns access time

••

•Asynchronous and simultaneous read and write

••

•Fully expandable by both word depth and/or bit width

••

•Pin and functionally compatible with 720X family

••

•Status Flags: Empty, Half-Full, Full

••

•Auto-retransmit capability

••

•High-performance CEMOS™ technology

••

•Military product compliant to MIL-STD-883, Class B

••

•Standard Military Drawing #5962-87531, 5962-89666, 5962-89863

and 5962-89536 are listed on this function

••

•Dual versions available in the TSSOP package. For more informa-

tion, see IDT7280/7281/7282 data sheet

IDT7280 = 2 x IDT7200

IDT7281 = 2 x IDT7201

IDT7282 = 2 x IDT7202

••

•Industrial temperature range (–40oC to +85oC) is available

(plastic packages only)

DESCRIPTION:

The IDT7200/7201/7202 are dual-port memories that load and empty data

on a first-in/first-out basis. The devices use Full and Empty flags to prevent data

overflow and underflow and expansion logic to allow for unlimited expansion

capability in both word size and depth.

The reads and writes are internally sequential through the use of ring

pointers, with no address information required to load and unload data. Data

is toggled in and out of the devices through the use of the Write (W) and Read

(R) pins.

The devices utilize a 9-bit wide data array to allow for control and parity bits

at the user’s option. This feature is especially useful in data communications

applications where it is necessary to use a parity bit for transmission/reception

error checking. It also features a Retransmit (RT) capability that allows for reset

of the read pointer to its initial position when RT is pulsed LOW to allow for

retransmission from the beginning of data. A Half-Full Flag is available in the

single device mode and width expansion modes.

These FIFOs are fabricated using IDT’s high-speed CMOS technology.

They are designed for those applications requiring asynchronous and

simultaneous read/writes in multiprocessing and rate buffer applications.

Military grade product is manufactured in compliance with the latest revision of

MIL-STD-883, Class B.

FUNCTIONAL BLOCK DIAGRAM

WWRITE

CONTROL

READ

CONTROL

FLAG

LOGIC

EXPANSION

LOGIC

WRITE

POINTER

RAM

ARRAY

256 x 9

512 x 9

1,024 x 9

READ

POINTER

DATA INPUTS

RESET

LOGIC

THREE-

STATE

BUFFERS

DATA OUTPUTS

XO/HF

FL/RT

-D

)

2679 drw 01

-Q

)

COMMERCIAL, INDUSTRIAL AND MILITARY

TEMPERATURE RANGES

IDT7201L/7201LA/7202LA CMOS ASYNCHRONOUS FIFO

256 x 9, 512 x 9 and 1,024 x 9

PIN CONFIGURATIONS

RECOMMENDED DC OPERATING

CONDITIONS

Symbol Parameter Min. Typ. Max. Unit

VCC Supply Voltage 4.5 5.0 5.5 V

Commercial/Industrial/Military

GND Supply Voltage 0 0 0 V

VIH(1) Input High Voltage Com'l/Ind'l 2.0 — — V

VIH(1) Input High Voltage Military 2.2 — — V

VIL(2) Input Low Voltage — — 0.8 V

Commercial/Industrial/Military

TAOperating Temperature Commercial 0 — 70 °C

TAOperating Temperature Industrial –40 — 85 °C

TAOperating Temperature Military –55 — 125 °C

NOTES:

1. For RT/RS/XI input, VIH = 2.6V (commercial).

For RT/RS/XI input, VIH = 2.8V (military).

2. 1.5V undershoots are allowed for 10ns once per cycle.

ABSOLUTE MAXIMUM RATINGS

Symbol Rating Com’l & Ind'l Mil. Unit

VTERM Terminal Voltage –0.5 to +7.0 –0.5 to +7.0 V

with Respect

to GND

TSTG Storage –55 to +125 –65 to +155 °C

Temperature

IOUT DC Output –50 to +50 –50 to +50 mA

Current

NOTE:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. This is a stress rating only and functional operation of

the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect reliability.

Reference Order

Package Type Identifier Code

PLASTIC DIP(1) P28-1 P

PLASTIC THIN DIP P28-2 TP

CERDIP(1) D28-1 D

THIN CERDIP D28-3 TD

SOIC SO28-3 SO

TOP VIEW

Reference Order

Package Type Identifier Code

LCC(1) L32- 1 L

PLCC J32-1 J

TOP VIEW

NOTE:

1. The 600-mil-wide DIP (P28-1 and D28-1) and LCC are not available for the IDT7200.

VCC

D3D5326

D2D6425

D1D7524

D0FL/RT623

XI RS

722

FF EF

821

Q0XO/HF920

Q1Q710 19

Q2Q611 18

Q3Q512 17

Q8Q413 16

GND R

14 15

2679 drw 02a

XI 8

FF 9

NC 12

FL/RT

XO/HF

432132 31 30

14 15 16 17 18 19 20

GND

INDEX

2679 drw 02b

COMMERCIAL, INDUSTRIAL AND MILITARY

TEMPERATURE RANGES

IDT7201L/7201LA/7202LA CMOS ASYNCHRONOUS FIFO

256 x 9, 512 x 9 and 1,024 x 9

DC ELECTRICAL CHARACTERISTICS

(Commercial: VCC = 5V ± 10%, T A = 0oC to +70oC; Industrial: VCC = 5V ± 10%, T A = –40oC to +85oC; Military: VCC = 5V ± 10%, TA = –55oC to +125oC)

IDT7200L IDT7200L

IDT7201LA IDT7201LA

IDT7202LA IDT7202LA

Com'l & Ind'l(1) Military(2)

tA = 12, 15, 20, 25, 35, 50 ns tA = 20, 30, 50, 80 ns

Symbol Parameter Min. Max. Min. Max. Unit

ILI(3) Input Leakage Current (Any Input) –1 1 –10 10 µA

ILO(4) Output Leakage Current –10 10 –10 10 µA

VOH Output Logic “1” Voltage IOH = –2mA 2. 4 — 2. 4 — V

VOL Output Logic “0” Voltage IOL = 8mA — 0.4 — 0.4 V

ICC1(5,6,7) Active Power Supply Current — 80 — 10 0 mA

ICC2(5,8) Standby Current (R=W=RS=FL/RT=VIH)—5—15mA

NOTES:

1. Industrial temperature range product for the 15ns and 25 ns speed grades are available as a standard device.

2. Military speed grades of 50ns and 80ns are only available for the IDT7201LA.

3. Measurements with 0.4 ≤ VIN ≤ VCC.

4. R ≥ VIH, 0.4 ≤ VOUT ≤ VCC.

5. Tested with outputs open (IOUT = 0).

6 . Tested at f = 20 MHz.

7 . Typical ICC1 = 15 + 2*fS + 0.02*CL*fS (in mA) with VCC = 5V, TA = 25°C, fS = WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at fS/2, CL = capacitive

load (in pF).

8. All Inputs = VCC - 0.2V or GND + 0.2V.

AC TEST CONDITIONS

Input Pulse Levels GND to 3.0V

Input Rise/Fall Times 5ns

Input Timing Reference Levels 1.5V

Output Reference Levels 1.5V

Output Load See Figure 1

Symbol Parameter Condition Max. Unit

CIN Input Capacitance VIN = 0V 8 pF

COUT Output Capacitance VOUT = 0V 8 pF

NOTE:

1. Characterized values, not currently tested.

CAPACITANCE (TA = +25°C, f = 1.0 MHz)

or equivalent circuit

2679 drw 03

30pF*

1.1K

OUTPUT

680Ω

Figure 1. Output Load

* Includes scope and jig capacitances.

COMMERCIAL, INDUSTRIAL AND MILITARY

TEMPERATURE RANGES

IDT7201L/7201LA/7202LA CMOS ASYNCHRONOUS FIFO

256 x 9, 512 x 9 and 1,024 x 9

Commercial Com'l & Ind'l(2) Com'l & Mil. Com'l & Ind'l(2)

IDT7200L12 IDT7200L15 IDT7200L20 IDT7200L25

IDT7201LA12 IDT7201LA15 IDT7201LA20 IDT7201LA25

IDT7202LA12 IDT7202LA15 IDT7202LA20 IDT7202LA25

Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit

tSShift Frequency — 50 — 40 — 33.3 — 28.5 MHz

tRC Read Cycle Time 2 0 — 25 — 30 — 3 5 — ns

tAAccess Time — 12 — 15 — 20 — 25 ns

tRR Read Recovery Time 8 — 10 — 10 — 10 — ns

tRPW Read Pulse Width(3) 12 — 15 — 20 — 25 — ns

tRLZ Read Pulse Low to Data Bus at Low Z(4) 3—3—3—3—ns

tWLZ Write Pulse High to Data Bus at Low Z(4,5) 5—5—5—5—ns

tDV Data Valid from Read Pulse High 5 — 5 — 5 — 5 — ns

tRHZ Read Pulse High to Data Bus at High Z(4) — 12 — 15 — 15 — 18 ns

tWC Write Cycle Time 20 — 25 — 30 — 35 — ns

tWPW Write Pulse Width(3) 12 — 15 — 20 — 25 — ns

tWR Write Recovery Time 8 — 10 — 10 — 10 — ns

tDS Data Set-up Time 9 — 11 — 12 — 15 — ns

tDH Data Hold Time 0 — 0 — 0 — 0 — ns

tRSC Reset Cycle Time 2 0 — 25 — 30 — 35 — ns

tRS Reset Pulse Width(3) 12 — 15 — 20 — 25 — ns

tRSS Reset Set-up Time(4) 12 — 15 — 20 — 25 — ns

tRSR Reset Recovery Time 8 — 10 — 10 — 10 — ns

tRTC Retransmit Cycle Time 20 — 25 — 30 — 35 — ns

tRT Retransmit Pulse Width(3) 12 — 15 — 20 — 25 — ns

tRTS Retransmit Set-up Time(4) 12 — 15 — 20 — 25 — ns

tRTR Retransmit Recovery Time 8 — 10 — 10 — 10 — ns

tEFL Reset to Empty Flag Low — 12 — 25 — 30 — 35 ns

tHFH,FFH Reset to Half-Full and Full Flag High — 17 — 25 — 30 — 35 ns

tRTF Retransmit Low to Flags Valid — 20 — 25 — 30 — 35 ns

tREF Read Low to Empty Flag Low — 1 2 — 1 5 — 2 0 — 2 5 ns

tRFF Read High to Full Flag High — 1 4 — 15 — 2 0 — 2 5 ns

tRPE Read Pulse Width after EF High 12 — 15 — 20 — 25 — ns

tWEF Write High to Empty Flag High — 12 — 1 5 — 20 — 25 ns

tWFF Write Low to Full Flag Low — 14 — 1 5 — 20 — 25 ns

tWHF Write Low to Half-Full Flag Low — 17 — 25 — 30 — 35 ns

tRHF Read High to Half-Full Flag High — 17 — 25 — 30 — 35 ns

tWPF Write Pulse Width after FF High 12 — 15 — 20 — 25 — ns

tXOL Read/Write to XO Low — 12 — 15 — 20 — 25 ns

tXOH Read/Write to XO High — 12 — 15 — 20 — 25 ns

tXI XI Pulse Width(3) 12 — 15 — 20 — 25 — ns

tXIR XI Recovery Time 8 — 10 — 1 0 — 1 0 — ns

tXIS XI Set-up Time 8 — 10 — 10 — 10 — ns

NOTES:

1. Timings referenced as in AC Test Conditions.

2 . Industrial temperature range product for 15ns and 25ns speed grades are available as a standard device.

3. Pulse widths less than minimum value are not allowed.

4. Values guaranteed by design, not currently tested.

5 . Only applies to read data flow-through mode

AC ELECTRICAL CHARACTERISTICS(1)

(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Industrial: VCC = 5V ± 10%, TA = –40°C to +85 °C; Military: VCC = 5V ± 10%, TA = –55°C to +125°C)

COMMERCIAL, INDUSTRIAL AND MILITARY

TEMPERATURE RANGES

IDT7201L/7201LA/7202LA CMOS ASYNCHRONOUS FIFO

256 x 9, 512 x 9 and 1,024 x 9

Military Commercial Com'l & Mil.(2) Military(2)

IDT7200L30 IDT7200L35 IDT7200L50

IDT7201LA30 IDT7201LA35 IDT7201LA50

IDT7202LA30 IDT7202LA35 IDT7202LA50 IDT7201LA80

Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit

tSShift Frequency — 25 — 22.2 — 15 — 10 MHz

tRC Read Cycle Time 4 0 — 45 — 65 — 100 — ns

tAAccess Time — 30 — 35 — 50 — 80 ns

tRR Read Recovery Time 10 — 10 — 15 — 20 — ns

tRPW Read Pulse Width(3) 30 — 35 — 50 — 80 — ns

tRLZ Read Pulse Low to Data Bus at Low Z(4) 3—3—3—3—ns

tWLZ Write Pulse High to Data Bus at Low Z(4, 5) 5—5—5—5—ns

tDV Data Valid from Read Pulse High 5 — 5 — 5 — 5 — ns

tRHZ Read Pulse High to Data Bus at High Z(4) — 20 — 20 — 30 — 30 ns

tWC Write Cycle Time 4 0 — 45 — 65 — 100 — ns

tWPW Write Pulse Width(3) 30 — 35 — 50 — 80 — ns

tWR Write Recovery Time 10 — 10 — 15 — 20 — ns

tDS Data Set-up Time 18 — 18 — 30 — 40 — ns

tDH Data Hold Time 0 — 0 — 5 — 10 — ns

tRSC Reset Cycle Time 4 0 — 45 — 6 5 — 100 — ns

tRS Reset Pulse Width(3) 30 — 35 — 50 — 80 — ns

tRSS Reset Set-up Time(4) 30 — 35 — 50 — 80 — ns

tRSR Reset Recovery Time 10 — 10 — 15 — 20 — ns

tRTC Retransmit Cycle Time 40 — 45 — 65 — 100 — ns

tRT Retransmit Pulse Width(3) 30 — 35 — 50 — 80 — ns

tRTS Retransmit Set-up Time(4) 30 — 35 — 50 — 80 — ns

tRTR Retransmit Recovery Time 10 — 10 — 15 — 20 — ns

tEFL Reset to Empty Flag Low — 40 — 45 — 65 — 100 ns

tHFH,FFH Reset to Half-Full and Full Flag High — 40 — 45 — 65 — 100 ns

tRTF Retransmit Low to Flags Valid — 40 — 45 — 65 — 100 ns

tREF Read Low to Empty Flag Low — 3 0 — 3 0 — 4 5 — 6 0 ns

tRFF Read High to Full Flag High — 3 0 — 30 — 45 — 60 ns

tRPE Read Pulse Width after EF High 30 — 35 — 50 — 80 — ns

tWEF Write High to Empty Flag High — 3 0 — 3 0 — 45 — 6 0 ns

tWFF Write Low to Full Flag Low — 30 — 30 — 45 — 60 ns

tWHF Write Low to Half-Full Flag Low — 40 — 45 — 65 — 100 ns

tRHF Read High to Half-Full Flag High — 40 — 45 — 65 — 100 ns

tWPF Write Pulse Width after FF High 30 — 35 — 50 — 80 — ns

tXOL Read/Write to XO Low — 30 — 35 — 50 — 80 ns

tXOH Read/Write to XO High — 30 — 35 — 50 — 80 ns

tXI XI Pulse Width(3) 30 — 35 — 50 — 80 — ns

tXIR XI Recovery Time 10 — 1 0 — 1 0 — 1 0 — ns

tXIS XI Set-up Time 10 — 10 — 15 — 15 — ns

AC ELECTRICAL CHARACTERISTICS(1) (Continued)

(Commercial: VCC = 5V ± 10%, T A = 0°C to +70°C; Industrial: VCC = 5V ± 10%, T A = –40°C to +85 °C; Military: VCC = 5V ± 10%, TA = –55°C to +125°C)

NOTES:

1. Timings referenced as in AC Test Conditions

2. Military speed grades of 50ns and 80ns are only available for IDT7201LA.

3. Pulse widths less than minimum value are not allowed.

4. Values guaranteed by design, not currently tested.

5. Only applies to read data flow-through mode.

COMMERCIAL, INDUSTRIAL AND MILITARY

TEMPERATURE RANGES

IDT7201L/7201LA/7202LA CMOS ASYNCHRONOUS FIFO

256 x 9, 512 x 9 and 1,024 x 9

Device Mode, this pin acts as the retransmit input. The Single Device Mode is

initiated by grounding the Expansion In (XI).

The IDT7200/7201A/7202A can be made to retransmit data when the

Retransmit Enable control (RT) input is pulsed LOW. A retransmit operation will

set the internal read pointer to the first location and will not affect the write pointer.

Read Enable (R) and Write Enable (W) must be in the HIGH state during

retransmit. This feature is useful when less than 256/512/1,024 writes are

performed between resets. The retransmit feature is not compatible with the

Depth Expansion Mode and will affect the Half-Full Flag (HF), depending on

the relative locations of the read and write pointers.

EXPANSION IN (XI)

This input is a dual-purpose pin. Expansion In (XI) is grounded to indicate

an operation in the single device mode. Expansion In (XI) is connected to

Expansion Out (XO) of the previous device in the Depth Expansion or Daisy

Chain Mode.

OUTPUTS:

FULL FLAG (FF)

The Full Flag (FF) will go LOW, inhibiting further write operation, when the

write pointer is one location less than the read pointer, indicating that the

device is full. If the read pointer is not moved after Reset (RS), the Full-Flag

(FF) will go LOW after 256 writes for IDT7200, 512 writes for the IDT7201A and

1,024 writes for the IDT7202A.

EMPTY FLAG (EF)

The Empty Flag (EF) will go LOW, inhibiting further read operations, when

the read pointer is equal to the write pointer, indicating that the device is

empty.

EXPANSION OUT/HALF-FULL FLAG (XO/HF)

This is a dual-purpose output. In the single device mode, when

Expansion In (XI) is grounded, this output acts as an indication of a half-full

memory.

After half of the memory is filled and at the falling edge of the next write

operation, the Half-Full Flag (HF) will be set LOW and will remain set until the

difference between the write pointer and read pointer is less than or equal

to one half of the total memory of the device. The Half-Full Flag (HF) is then

reset by using rising edge of the read operation.

In the Depth Expansion Mode, Expansion In (XI) is connected to Expansion

Out (XO) of the previous device. This output acts as a signal to the next device

in the Daisy Chain by providing a pulse to the next device when the previous

device reaches the last location of memory.

DATA OUTPUTS (Q0 – Q8)

Data outputs for 9-bit wide data. This data is in a high impedance condition

whenever Read (R) is in a HIGH state.

SIGNAL DESCRIPTIONS

INPUTS:

DATA IN (D0 – D8)

Data inputs for 9-bit wide data.

CONTROLS:

RESET (RS)

Reset is accomplished whenever the Reset (RS) input is taken to a LOW

state. During reset, both internal read and write pointers are set to the first

location. A reset is required after power up before a write operation can take

place. Both the Read Enable (R) and Write Enable (W) inputs must be

in the HIGH state during the window shown in Figure 2, (i.e., tRSS

before the rising edge of RS) and should not change until tRSR after

the rising edge of RS. Half-Full Flag (HF) will be reset to HIGH after

Reset (RS).

WRITE ENABLE (W)

A write cycle is initiated on the falling edge of this input if the Full Flag (FF)

is not set. Data set-up and hold times must be adhered to with respect to the rising

edge of the Write Enable (W). Data is stored in the RAM array sequentially and

independently of any on-going read operation.

After half of the memory is filled and at the falling edge of the next write

operation, the Half-Full Flag (HF) will be set to LOW and will remain set until the

difference between the write pointer and read pointer is less than or equal to

one half of the total memory of the device. The Half-Full Flag (HF) is then reset

by the rising edge of the read operation.

To prevent data overflow, the Full Flag (FF) will go LOW, inhibiting further

write operations. Upon the completion of a valid read operation, the Full

Flag (FF) will go HIGH after tRFF, allowing a valid write to begin. When the FIFO

is full, the internal write pointer is blocked from W, so external changes in W will

not affect the FIFO when it is full.

READ ENABLE (R)

A read cycle is initiated on the falling edge of the Read Enable (R) provided

the Empty Flag (EF) is not set. The data is accessed on a First-In/First-Out basis,

independent of any ongoing write operations. After Read Enable (R) goes

HIGH, the Data Outputs (Q0 – Q8) will return to a high impedance condition until

the next Read operation. When all data has been read from the FIFO, the Empty

Flag (EF) will go LOW, allowing the “final” read cycle but inhibiting further read

operations with the data outputs remaining in a high impedance state. Once a

valid write operation has been accomplished, the Empty Flag (EF) will go HIGH

after tWEF and a valid Read can then begin. When the FIFO is empty, the internal

read pointer is blocked from R so external changes in R will not affect the FIFO

when it is empty.

FIRST LOAD/RETRANSMIT (FL/RT)

This is a dual-purpose input. In the Depth Expansion Mode, this pin is

grounded to indicate that it is the first loaded (see Operating Modes). In the Single

COMMERCIAL, INDUSTRIAL AND MILITARY

TEMPERATURE RANGES

IDT7201L/7201LA/7202LA CMOS ASYNCHRONOUS FIFO

256 x 9, 512 x 9 and 1,024 x 9

NOTES:

1. EF, FF, HF may change status during Reset, but flags will be valid at tRSC.

2. W and R = VIH around the rising edge of RS.

Figure 2. Reset

Figure 4. Full Flag From Last Write to First Read

Figure 3. Asynchronous Write and Read Operation

HF, FF

RSC

RSS

RSR

EFL

HFH ,

FFH

2679 drw 04

DATA

OUT

VALID DATA

OUT

VALID

RPW

RLZ

RHZ

WPW

DATA

VALID DATA

VALID

-Q

2679 drw 05

-D

LAST WRITE

IGNORED

WRITE

FIRST READ ADDITIONAL

READS

tWFF tRFF

FIRST

WRITE

2679 drw 06

COMMERCIAL, INDUSTRIAL AND MILITARY

TEMPERATURE RANGES

IDT7201L/7201LA/7202LA CMOS ASYNCHRONOUS FIFO

256 x 9, 512 x 9 and 1,024 x 9

LAST READ

IGNORED

READ

FIRST WRITE ADDITIONAL

WRITES

WEF

VALID

DATA OUT

REF

2679 drw 07

FIRST READ

VALID

Figure 5. Empty Flag From Last Read to First Write

Figure 8. Minimum Timing for a Full Flag Coincident Write Pulse

Figure 7. Minimum Timing for an Empty Flag Coincident Read Pulse

Figure 6. Retransmit

RTC

RTS

W,R

HF, EF, FF

RTR

FLAG VALID

2679 drw 08

RTF

WEF

RPE

2679 drw 09

RFF

WPF

2679 drw 10

COMMERCIAL, INDUSTRIAL AND MILITARY

TEMPERATURE RANGES

IDT7201L/7201LA/7202LA CMOS ASYNCHRONOUS FIFO

256 x 9, 512 x 9 and 1,024 x 9

Figure 9. Half-Full Flag Timing

Figure 10. Expansion Out

Figure 11. Expansion In

OPERATING MODES:

Care must be taken to assure that the appropriate flag is monitored by

each system (i.e. FF is monitored on the device where W is used; EF is monitored

on the device where R is used). For additional information, refer to Tech Note

8: Operating FIFOs on Full and Empty Boundary Conditions and Tech Note

6: Designing with FIFOs.

SINGLE DEVICE MODE

A single IDT7200/7201A/7202A may be used when the application

requirements are for 256/512/1,024 words or less. These devices are in a

Single Device Configuration when the Expansion In (XI) control input is

grounded (see Figure 12).

DEPTH EXPANSION

The IDT7200/7201A/7202A can easily be adapted to applications when

the requirements are for greater than 256/512/1,024 words. Figure 14

demonstrates Depth Expansion using three IDT7200/7201A/7202As. Any

depth can be attained by adding additional IDT7200/7201A/7202As. These

FIFOs operate in the Depth Expansion mode when the following conditions

are met:

1. The first device must be designated by grounding the First Load (FL) control

input.

2. All other devices must have FL in the HIGH state.

3. The Expansion Out (XO) pin of each device must be tied to the Expansion

In (XI) pin of the next device. See Figure 14.

4. External logic is needed to generate a composite Full Flag (FF) and Empty

Flag (EF). This requires the ORing of all EFs and ORing of all FFs (i.e.

all must be set to generate the correct composite FF or EF). See Figure

14.

5. The Retransmit (RT) function and Half-Full Flag (HF) are not available in

the Depth Expansion Mode.

For additional information, refer to Tech Note 9: Cascading FIFOs or

FIFO Modules.

RHF

HALF-FULL OR LESS MORE THAN HALF-FULL

WHF

2679 drw 11

HALF-FULL OR LESS

2679 drw 12

WRITE TO

LAST PHYSICAL

LOCATION

tXOL tXOH

READ FROM

LAST PHYSICAL

LOCATION

tXOL tXOH

WRITE TO

FIRST PHYSICAL

LOCATION tXIS

READ FROM

FIRST PHYSICAL

LOCATION

tXIS

tXI tXIR

2679 drw 13

COMMERCIAL, INDUSTRIAL AND MILITARY

TEMPERATURE RANGES

IDT7201L/7201LA/7202LA CMOS ASYNCHRONOUS FIFO

256 x 9, 512 x 9 and 1,024 x 9

USAGE MODES:

WIDTH EXPANSION

Word width may be increased simply by connecting the corresponding

input control signals of multiple devices. Status flags (EF, FF and HF) can be

detected from any one device. Figure 13 demonstrates an 18-bit word width

by using two IDT7200/7201A/7202As. Any word width can be attained by

adding additional IDT7200/7201A/7202As (Figure 13).

BIDIRECTIONAL OPERATION

Applications which require data buffering between two systems (each

system capable of Read and Write operations) can be achieved by pairing

IDT7200/7201A/7202As as shown in Figure 16. Both Depth Expansion and

Width Expansion may be used in this mode.

DATA FLOW-THROUGH

Two types of flow-through modes are permitted, a read flow-through

and write flow-through mode. For the read flow-through mode (Figure 17),

the FIFO permits a reading of a single word after writing one word of data into

an empty FIFO. The data is enabled on the bus in (tWEF + tA) ns after the rising

edge of W, called the first write edge, and it remains on the bus until the R line

is raised from LOW-to-HIGH, after which the bus would go into a three-state

mode after tRHZ ns. The EF line would have a pulse showing temporary

deassertion and then would be asserted.

In the write flow-through mode (Figure 18), the FIFO permits the writing

of a single word of data immediately after reading one word of data from a

full FIFO. The R line causes the FF to be deasserted but the W line being LOW

causes it to be asserted again in anticipation of a new data word. On the rising

edge of W, the new word is loaded in the FIFO. The W line must be toggled

when FF is not asserted to write new data in the FIFO and to increment the write

pointer.

COMPOUND EXPANSION

The two expansion techniques described above can be applied together

in a straightforward manner to achieve large FIFO arrays (see Figure 15).

Figure 13. Block Diagram of 256 x 18, 512 x 18, 1,024 x 18 FIFO Memory Used in Width Expansion Mode

Figure 12. Block Diagram of Single 256 x 9, 512 x 9, 1,024 x 9 FIFO

WRITE (W)

DATA IN (D)

FULL FLAG (FF)

RESET (RS)

READ (R)

DATA OUT (Q)

EMPTY FLAG (EF)

RETRANSMIT (RT)

EXPANSION IN (XI)

(HF)

IDT

7200/

7201A/

7202A

(HALF-FULL FLAG)

2679 drw 14

IDT

7200/

7201A/

7202A

XI XI

9918

DATA

WRITE (W)

FULL FLAG (FF)

RESET (RS)

(D)

READ (R)

EMPTY FLAG (EF)

RETRANSMIT (RT)

DATA OUT (Q)

IDT

7200/

7201A/

7202A

2679 drw 15

COMMERCIAL, INDUSTRIAL AND MILITARY

TEMPERATURE RANGES

IDT7201L/7201LA/7202LA CMOS ASYNCHRONOUS FIFO

256 x 9, 512 x 9 and 1,024 x 9

TABLE 1 — RESET AND RETRANSMIT

Single Device Configuration/Width Expansion Mode

Inputs Internal Status Outputs

Mode RS RT XI Read Pointer Write Pointer EF FF HF

Reset 0 X 0 Location Zero Location Zero 0 1 1

Retransmit 1 0 0 Location Zero Unchanged X X X

Read/Write 1 1 0 Increment(1) Increment(1) XXX

NOTE:

1. Pointer will increment if flag is HIGH.

Figure 14. Block Diagram of 768 x 9, 1,536 x 9, 3,072 x 9 FIFO Memory (Depth Expansion)

TABLE 2 — RESET AND FIRST LOAD TRUTH TABLE

Depth Expansion/Compound Expansion Mode

Inputs Internal Status Outputs

Mode RS FL XI Read Pointer Write Pointer EF FF

Reset First Device 0 0 (1) Location Zero Location Zero 0 1

Reset All Other Devices 0 1 ( 1) Location Zero Location Zero 0 1

Read/Write 1 X (1) X X X X

NOTE:

1. XI is connected to XO of previous device. See Figure 14. RS = Reset Input, FL/RT = First Load/Retransmit, EF = Empty Flag Output, FF = Full Flag Output,

XI = Expansion Input, HF = Half-Full Flag Output

IDT

7200/

7201A/

7202A

FF EF

FULL EMPTY

VCC

9 9

9 Q

IDT

7200/

7201A/

7202A

IDT

7200/

7201A/

7202A

FF EF

2678 drw16

COMMERCIAL, INDUSTRIAL AND MILITARY

TEMPERATURE RANGES

IDT7201L/7201LA/7202LA CMOS ASYNCHRONOUS FIFO

256 x 9, 512 x 9 and 1,024 x 9

Figure 15. Compound FIFO Expansion

NOTES:

1. For depth expansion block see section on Depth Expansion and Figure 14.

2. For Flag detection see section on Width Expansion and Figure 13.

Figure 16. Bidirectional FIFO Mode

IDT7200/

IDT7201A/

IDT7202A

DEPTH

EXPANSION

BLOCK

R, W, RS

D0-DN

Q0-Q8

IDT7200/

IDT7201A/

IDT7202A

DEPTH

EXPANSION

BLOCK

IDT7200/

IDT7201A/

IDT7202A

DEPTH

EXPANSION

BLOCK

2679 drw 17

D0-D8

D9-DND18-DND(N-8)-DN

D9-D17 D(N-8)-DN

Q0-Q8

Q9-Q17

Q9-Q17 Q(N-8)-Qn

Q(N-8)-Qn

IDT

7201A

EFB

HFB

FFA

FFB

SYSTEM A SYSTEM B

QB 0-8

DB 0-8

QA 0-8

HFA

EFA

IDT

7200/

7201A/

7202A

DA 0-8

IDT

7200/

7201A/

7202A

2679 drw 18

COMMERCIAL, INDUSTRIAL AND MILITARY

TEMPERATURE RANGES

IDT7201L/7201LA/7202LA CMOS ASYNCHRONOUS FIFO

256 x 9, 512 x 9 and 1,024 x 9

Figure 17. Read Data Flow-Through Mode

DATA

RPE

DATA

OUT

WLZ

WEF

REF

DATA VALID

OUT

2679 drw 19

Figure 18. Write Data Flow-Through Mode

DATA

OUT

WFF

RFF

WPF

DATA

VALID

DATA

OUT

VALID

2679 drw 20

CORPORATE HEADQUARTERS for SALES: for TECH SUPPORT:

2975 Stender Way 800-345-7015 or 408-727-6116 408-330-1753

Santa Clara, CA 95054 fax: 408-492-8674 e-mail: FIFOhelp@idt.com

www.idt.com

ORDERING INFORMATION

IDT XXXX

Device Type

XXX

Speed

Power

Package

Process/

Temperature

Range

Blank

7200

7201

7202

7280

7281

7282

Commercial (0oC to +70oC)

Industrial (-40oC to +85oC)

Military (-55oC to +125oC)

Compliant to MIL-STD-883, Class B

256 x 9-Bit FIFO

512 x 9-Bit FIFO

1,024 x 9-Bit FIFO

256 x 9-Bit DUAL FIFO

512 x 9-Bit DUAL FIFO

1,024 x 9-Bit DUAL FIFO

Commercial Only

Commercial and Industrial

Commercial and Military

Commercial and Industrial

Military Only

Commercial Only

Commercial and (Military only for 7201)

Military only for 7201

LA Low Power

Plastic DIP

Plastic Thin DIP

CERDIP

Thin CERDIP

Plastic Leaded Chip Carrier

SOIC

Leadless Chip Carrier

Access Time (t

) Speed

in Nanoseconds

2679 drw 21

Blank

(1)

P28-1

P28-2

D28-1

D28-3

J32-1

SO28-3

L32-1

PLCC

LCC

(7201 & 7202 Only)

(2)

See 7280/7281/7282

data sheet for details

NOTES:

1. Industrial temperature range product is available for the 15ns and 25ns as a standard product.

2. "A" to be included for IDT7201 and IDT7202 ordering part number.

DATASHEET DOCUMENT HISTORY

05/02/2001 pgs. 1, 2, 3, 4, 5 and 14.