IPI051N15N5 MOSFET OptiMOS5Power-Transistor,150V I-PAK Features tab Package *ExcellentgatechargexRDS(on)product(FOM) *Verylowon-resistanceRDS(on) *175Coperatingtemperature *Pb-freeleadplating;RoHScompliant *QualifiedaccordingtoJEDEC1)fortargetapplication *Idealforhigh-frequencyswitchingandsynchronousrectification *Halogen-freeaccordingtoIEC61249-2-21 1 2 3 Table1KeyPerformanceParameters Parameter Value Unit VDS 150 V RDS(on),max(TO262) 5.1 m ID 120 A Type/OrderingCode Package IPI051N15N5 PG-TO262-3 1) Drain Pin 2, Tab Gate Pin 1 Source Pin 3 Marking 051N15N5 RelatedLinks - J-STD20 and JESD22 Final Data Sheet 1 Rev.2.0,2016-02-01 OptiMOS5Power-Transistor,150V IPI051N15N5 TableofContents Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical characteristics diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Final Data Sheet 2 Rev.2.0,2016-02-01 OptiMOS5Power-Transistor,150V IPI051N15N5 1Maximumratings atTA=25C,unlessotherwisespecified Table2Maximumratings Parameter Symbol Continuous drain current Values Unit Note/TestCondition 120 115 A TC=25C TC=100C - 480 A TC=25C - - 230 mJ ID=100A,RGS=25 VGS -20 - 20 V - Power dissipation Ptot - - 300 W TC=25C Operating and storage temperature Tj,Tstg -55 - 175 C IEC climatic category; DIN IEC 68-1: 55/175/56 Unit Note/TestCondition Min. Typ. Max. ID - - ID,pulse - Avalanche energy, single pulse EAS Gate source voltage Pulsed drain current1) 2) 2Thermalcharacteristics Table3Thermalcharacteristics Parameter Symbol Thermal resistance, junction - case Values Min. Typ. Max. RthJC - 0.3 0.5 K/W - Thermal resistance, junction - ambient, RthJA minimal footprint - - 62 K/W - Unit Note/TestCondition 3Electricalcharacteristics Table4Staticcharacteristics Parameter Symbol Drain-source breakdown voltage Values Min. Typ. Max. V(BR)DSS 150 - - V VGS=0V,ID=1mA Gate threshold voltage VGS(th) 3.0 3.8 4.6 V VDS=VGS,ID=264A Zero gate voltage drain current IDSS - 0.1 10 1 100 A VDS=120V,VGS=0V,Tj=25C VDS=120V,VGS=0V,Tj=125C Gate-source leakage current IGSS - 1 100 nA VGS=20V,VDS=0V Drain-source on-state resistance RDS(on) - 4.0 4.3 5.1 5.7 m VGS=10V,ID=60A VGS=8V,ID=30A Gate resistance3) RG - 1.1 1.6 - Transconductance gfs 59 117 - S |VDS|>2|ID|RDS(on)max,ID=60A 1) See Diagram 3 See Diagram 13 3) Defined by design. Not subject to production test. 2) Final Data Sheet 3 Rev.2.0,2016-02-01 OptiMOS5Power-Transistor,150V IPI051N15N5 Table5Dynamiccharacteristics Parameter Symbol Values Unit Note/TestCondition 7800 pF VGS=0V,VDS=75V,f=1MHz 1500 1950 pF VGS=0V,VDS=75V,f=1MHz - 34 60 pF VGS=0V,VDS=75V,f=1MHz td(on) - 19.6 - ns VDD=75V,VGS=10V,ID=60A, RG,ext=1.6 Rise time tr - 5.3 - ns VDD=75V,VGS=10V,ID=60A, RG,ext=1.6 Turn-off delay time td(off) - 4.5 - ns VDD=75V,VGS=10V,ID=60A, RG,ext=1.6 Fall time tf - 37 - ns VDD=75V,VGS=10V,ID=60A, RG,ext=1.6 Unit Note/TestCondition Min. Typ. Max. Ciss - 6000 Output capacitance Coss - Reverse transfer capacitance1) Crss Turn-on delay time Input capacitance1) 1) Table6Gatechargecharacteristics2) Parameter Symbol Values Min. Typ. Max. Qgs - 33 - nC VDD=75V,ID=60A,VGS=0to10V Gate to drain charge Qgd - 16 24 nC VDD=75V,ID=60A,VGS=0to10V Switching charge Qsw - 31 - nC VDD=75V,ID=60A,VGS=0to10V Gate charge total Qg - 80 100 nC VDD=75V,ID=60A,VGS=0to10V Gate plateau voltage Vplateau - 5.4 - V VDD=75V,ID=60A,VGS=0to10V Qoss - 225 299 nC VDD=75V,VGS=0V Unit Note/TestCondition Gate to source charge 1) 1) 1) Output charge Table7Reversediode Parameter Symbol Diode continous forward current Diode pulse current Diode forward voltage 1) Reverse recovery time 1) Reverse recovery charge 1) 2) Values Min. Typ. Max. IS - - 120 A TC=25C IS,pulse - - 480 A TC=25C VSD - 0.87 1.1 V VGS=0V,IF=60A,Tj=25C trr - 72 144 ns VR=75V,IF=60A,diF/dt=100A/s Qrr - 106 212 nC VR=75V,IF=60A,diF/dt=100A/s Defined by design. Not subject to production test. See Gate charge waveforms for parameter definition Final Data Sheet 4 Rev.2.0,2016-02-01 OptiMOS5Power-Transistor,150V IPI051N15N5 4Electricalcharacteristicsdiagrams Diagram1:Powerdissipation Diagram2:Draincurrent 320 140 280 120 240 100 80 ID[A] Ptot[W] 200 160 60 120 40 80 20 40 0 0 50 100 150 0 200 0 50 100 TC[C] 150 200 TC[C] Ptot=f(TC) ID=f(TC);VGS10V Diagram3:Safeoperatingarea Diagram4:Max.transientthermalimpedance 3 100 10 1 s 10 s 100 s 102 0.5 101 ZthJC[K/W] ID[A] 1 ms 10 ms 10-1 0.2 0.1 DC 0.05 100 0.02 0.01 single pulse 10-1 10-1 100 101 102 103 10-2 10-5 10-4 VDS[V] 10-2 10-1 100 tp[s] ID=f(VDS);TC=25C;D=0;parameter:tp Final Data Sheet 10-3 ZthJC=f(tp);parameter:D=tp/T 5 Rev.2.0,2016-02-01 OptiMOS5Power-Transistor,150V IPI051N15N5 Diagram5:Typ.outputcharacteristics Diagram6:Typ.drain-sourceonresistance 500 10 10 V 450 9 8V 6V 400 8 350 RDS(on)[m] ID[A] 300 250 200 6 8V 5 10 V 4 3 6V 100 2 5.5 V 50 0 7V 7 7V 150 5.5 V 1 5V 4.5 V 0 1 2 3 4 0 5 0 50 100 150 VDS[V] 200 250 300 350 400 450 500 ID[A] ID=f(VDS);Tj=25C;parameter:VGS RDS(on)=f(ID);Tj=25C;parameter:VGS Diagram7:Typ.transfercharacteristics Diagram8:Typ.forwardtransconductance 350 200 180 300 160 250 140 120 ID[A] gfs[S] 200 150 100 80 60 100 40 50 175 C 0 0 2 4 20 25 C 6 8 0 0 VGS[V] 80 120 ID[A] ID=f(VGS);|VDS|>2|ID|RDS(on)max;parameter:Tj Final Data Sheet 40 gfs=f(ID);Tj=25C 6 Rev.2.0,2016-02-01 OptiMOS5Power-Transistor,150V IPI051N15N5 Diagram9:Drain-sourceon-stateresistance Diagram10:Typ.gatethresholdvoltage 12 5.0 4.5 10 4.0 2640 A 3.5 8 264 A VGS(th)[V] RDS(on)[m] 3.0 max 6 typ 4 2.5 2.0 1.5 1.0 2 0.5 0 -60 -20 20 60 100 140 0.0 -60 180 -20 20 Tj[C] 60 100 140 RDS(on)=f(Tj);ID=60A;VGS=10V VGS(th)=f(Tj);VGS=VDS;parameter:ID Diagram11:Typ.capacitances Diagram12:Forwardcharacteristicsofreversediode 4 10 103 Ciss 103 180 Tj[C] 25 C 175 C 25C max 175C max Coss IF[A] C[pF] 102 102 Crss 101 101 100 0 20 40 60 80 100 120 100 0.0 0.5 VDS[V] C=f(VDS);VGS=0V;f=1MHz Final Data Sheet 1.0 1.5 2.0 VSD[V] IF=f(VSD);parameter:Tj 7 Rev.2.0,2016-02-01 OptiMOS5Power-Transistor,150V IPI051N15N5 Diagram13:Avalanchecharacteristics Diagram14:Typ.gatecharge 3 10 10 8 75 V 30 V 102 120 V VGS[V] 6 IAS[A] 25 C 100 C 4 125 C 1 10 2 100 100 101 102 103 0 0 20 tAV[s] 40 60 80 100 Qgate[nC] IAS=f(tAV);RGS=25;parameter:Tj(start) VGS=f(Qgate);ID=60Apulsed;parameter:VDD Diagram15:Drain-sourcebreakdownvoltage Gate charge waveforms 170 165 VBR(DSS)[V] 160 155 150 145 140 135 -60 -20 20 60 100 140 180 Tj[C] VBR(DSS)=f(Tj);ID=1mA Final Data Sheet 8 Rev.2.0,2016-02-01 OptiMOS5Power-Transistor,150V IPI051N15N5 5PackageOutlines Figure1OutlinePG-TO262-3,dimensionsinmm/inches Final Data Sheet 9 Rev.2.0,2016-02-01 OptiMOS5Power-Transistor,150V IPI051N15N5 RevisionHistory IPI051N15N5 Revision:2016-02-01,Rev.2.0 Previous Revision Revision Date Subjects (major changes since last revision) 2.0 2016-02-01 Release of final version TrademarksofInfineonTechnologiesAG AURIXTM,C166TM,CanPAKTM,CIPOSTM,CoolGaNTM,CoolMOSTM,CoolSETTM,CoolSiCTM,CORECONTROLTM,CROSSAVETM,DAVETM,DI-POLTM,DrBladeTM, EasyPIMTM,EconoBRIDGETM,EconoDUALTM,EconoPACKTM,EconoPIMTM,EiceDRIVERTM,eupecTM,FCOSTM,HITFETTM,HybridPACKTM,InfineonTM, ISOFACETM,IsoPACKTM,i-WaferTM,MIPAQTM,ModSTACKTM,my-dTM,NovalithICTM,OmniTuneTM,OPTIGATM,OptiMOSTM,ORIGATM,POWERCODETM, PRIMARIONTM,PrimePACKTM,PrimeSTACKTM,PROFETTM,PRO-SILTM,RASICTM,REAL3TM,ReverSaveTM,SatRICTM,SIEGETTM,SIPMOSTM,SmartLEWISTM, SOLIDFLASHTM,SPOCTM,TEMPFETTM,thinQTM,TRENCHSTOPTM,TriCoreTM. TrademarksupdatedAugust2015 OtherTrademarks Allreferencedproductorservicenamesandtrademarksarethepropertyoftheirrespectiveowners. WeListentoYourComments Anyinformationwithinthisdocumentthatyoufeeliswrong,unclearormissingatall?Yourfeedbackwillhelpustocontinuously improvethequalityofthisdocument.Pleasesendyourproposal(includingareferencetothisdocument)to: erratum@infineon.com Publishedby InfineonTechnologiesAG 81726Munchen,Germany (c)2015InfineonTechnologiesAG AllRightsReserved. LegalDisclaimer Theinformationgiveninthisdocumentshallinnoeventberegardedasaguaranteeofconditionsorcharacteristics.With respecttoanyexamplesorhintsgivenherein,anytypicalvaluesstatedhereinand/oranyinformationregardingtheapplication ofthedevice,InfineonTechnologiesherebydisclaimsanyandallwarrantiesandliabilitiesofanykind,includingwithout limitation,warrantiesofnon-infringementofintellectualpropertyrightsofanythirdparty. Information Forfurtherinformationontechnology,deliverytermsandconditionsandpricespleasecontactyournearestInfineon TechnologiesOffice(www.infineon.com). Warnings Duetotechnicalrequirements,componentsmaycontaindangeroussubstances.Forinformationonthetypesinquestion, pleasecontactthenearestInfineonTechnologiesOffice. TheInfineonTechnologiescomponentdescribedinthisDataSheetmaybeusedinlife-supportdevicesorsystemsand/or automotive,aviationandaerospaceapplicationsorsystemsonlywiththeexpresswrittenapprovalofInfineonTechnologies,ifa failureofsuchcomponentscanreasonablybeexpectedtocausethefailureofthatlife-support,automotive,aviationand aerospacedeviceorsystemortoaffectthesafetyoreffectivenessofthatdeviceorsystem.Lifesupportdevicesorsystemsare intendedtobeimplantedinthehumanbodyortosupportand/ormaintainandsustainand/orprotecthumanlife.Iftheyfail,itis reasonabletoassumethatthehealthoftheuserorotherpersonsmaybeendangered. Final Data Sheet 10 Rev.2.0,2016-02-01