General Description
The MAX7306/MAX7307 I2C-/SMBus™-compatible, seri-
al-interfaced peripherals feature four level-translating
I/Os and operate from a 1.62V to 3.6V power supply.
The MAX7307 features a port supply (VLA) that allows
level translation on I/O ports to operate from a separate
power supply from 1.4V to 5.5V. The MAX7306 features
an address select input (AD0) to allow up to four unique
slave addresses.
The MAX7306/MAX7307 ports P2, P3, and P4 can be
configured as inputs, push-pull outputs, and open-drain
outputs. Port P1 can be configured as a general-pur-
pose input, open-drain output, or an open-drain INT out-
put. Ports P2 and P3 can be configured as OSCIN and
OSCOUT, respectively. The MAX7306/MAX7307 include
an internal oscillator for PWM, blink, and key debounce,
or to cascade multiple MAX7306/MAX7307s. The exter-
nal clock can be used to set a specific PWM and blink
timing. The RST input asynchronously clears the 2-wire
interface and terminates a bus lockup involving the
MAX7306/MAX7307.
All ports configured as output feature 33-step PWM,
allowing any output to be set from fully off, 1/32 to 31/32
duty cycle, to fully on. All output ports also feature LED
blink control, allowing blink periods of 1/8 second, 1/4
second, 1/2 second, 1, 2, 4, or 8 seconds. Any port can
blink during this period with a 1/16 to 15/16 duty cycle.
The MAX7306/MAX7307 are specified over the -40°C to
+125°C temperature range and are available in 10-pin
µDFN (2mm x 2mm) and 10-pin µMAX®packages.
Applications
Cell Phones LCD/Keypad Backlights
System I/O Ports LED Status Indicators
Features
♦1.4V to 5.5V I/O Level Translation Port Supply (VLA)
♦1.62V to 3.6V Power Supply
♦Four Individually Configurable GPIO Ports
P1 = Open-Drain I/O
P2, P3, P4 = Push-Pull or Open-Drain I/O
♦Individual 33-Step PWM Intensity Control
♦Blink Controls with 15 Steps on Outputs
♦1kHz PWM Period Provides Flicker-Free LED
Intensity Control
♦25mA (max) Port Output Sink Current (100mA
max Ground Current)
♦Inputs Overvoltage Protected Up to 5.5V (VLA)
♦Transition Detection with Optional Interrupt Output
♦Optional Input Debouncing
♦RST Input Clears Serial Interface, Can Restore
Power-Up Default State, and Synchronizes Blink
Timing
♦Oscillator Input and Output Enables Cascading
Multiple Devices
♦Low 0.75µA (typ) Standby Current
MAX7306/MAX7307
SMBus/I2C Interfaced 4-Port, Level-Translating
GPIOs and LED Drivers
________________________________________________________________ Maxim Integrated Products 1
Ordering Information
19-0836; Rev 1; 8/10
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Ordering Information continued at end of data sheet.
Pin Configurations appear at end of data sheet.
EVALUATION KIT
AVAILABLE
SMBus is a trademark of Intel Corp.
µMAX is a registered trademark of Maxim Integrated Products, Inc.
PART
TOP MARK
PIN-PACKAGE
MAX7306ALB+ AAL
10 µDFN (2mm x 2mm)
Note: All devices are specified over the -40°C to +125°C oper-
ating temperature range.
+Denotes a lead(Pb)-free/RoHS-compliant package.
μC
SDA
GND
+1.8V
VDD VLA
P2/OSCIN
P3/OSCOUT
P4
+4.5V
MAX7307
SCL
RST
INT
SDA
SCL
RST
P1/INT
AD0
μC
SDA
GND
+2.5V
VDD
P2/OSCIN
P3/OSCOUT
P4
MAX7306
SCL
RST
INT
SDA
SCL
RST
P1/INT
Typical Operating Circuit
MAX7306/MAX7307
SMBus/I2C Interfaced 4-Port, Level-Translating
GPIOs and LED Drivers
2 _______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS (MAX7306)
(VDD = 1.62V to 3.6V, TA= TMIN to TMAX, unless otherwise noted. Typical values are at VDD = 3.3V, TA= +25°C.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
(All voltages referenced to GND.)
VDD ..........................................................................-0.3V to +4V
VLA, SCL, SDA, AD0, and RST.................................-0.3V to +6V
P1/INT, P2/OSCIN, P3/OSCOUT, and P4
MAX7306................................................-0.3V to (VDD + 0.3V)
MAX7307.................................................-0.3V to (VLA + 0.3V)
P1/INT, P2/OSCIN, P3/OSCOUT, and P4 Sink Current ......25mA
P2/OSCIN, P3/OSCOUT, and P4 Source Current ..............10mA
SDA Sink Current ...............................................................10mA
VDD Current .......................................................................10mA
VLA Current (MAX7307) ......................................................30mA
GND Current ....................................................................100mA
Continuous Power Dissipation (TA= +70°C)
10-Pin µDFN (derate 5.0mW/°C over +70°C) ..............402mW
10-Pin µMAX (derate 10.3mW/°C over +70°C) ............825mW
Operating Temperature Range .........................-40°C to +125°C
Junction Temperature......................................................+150°C
Storage Temperature Range .............................-65°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
PARAMETER
SYMBOL
CONDITIONS MIN TYP
MAX
UNITS
Operating Supply Voltage VDD
1.62 3.60
V
Power-On Reset Voltage VPOR VDD rising 1.0 1.3 1.6 V
Power-On Reset Hysteresis
VPORHYST
10 131 300
mV
ISTB
Internal oscillator disabled; SCL,
SDA, digital inputs at VDD or
GND; P1–P4 (as inputs) at VDD or
GND
0.75 2
Standby Current (Interface Idle)
IOSC
Internal oscillator enabled; SCL,
SDA, digital inputs at VDD or
GND; P1–P4 (as inputs) at VDD or
GND
14 25
µA
S up p l y C ur r ent ( Inter face Runni ng ) ISUP fS C L
= 400kH z; other d i g i tal i np uts
at VDD or GND 33 40 µA
Input High Voltage SDA, SCL, AD0 VIH 0.7 x VDD V
Input Low Voltage SDA, SCL, AD0 VIL
0.3 x VDD
V
Input High Voltage RST, P1–P4 VIHP 0.7 x VDD V
Input Low Voltage RST, P1–P4 VILP
0.3 x VDD
V
Inp ut Leakag e C ur r ent S D A, S C L, AD 0I
IH, IIL VDD or GND -1 +1 µA
Input Leakage Current RST, P1–P4
IIHP, IILP
VDD or GND -1 +1 µA
Input Capacitance SDA, SCL, AD0, P1–P4 8 pF
VDD = 1.62V, ISINK = 3mA 0.06
0.11
VDD = 2.5V, ISINK = 16mA 0.19 0.4Output Low Voltage P1–P4 VOL
VDD = 3.3V, ISINK = 20mA 0.2 0.4
V
VDD = 1.62V, ISOURCE = 0.5mA
1.55
1.6
VDD ≥ 2.5V, ISOURCE = 5mA
V
D D - 0.3
2.3Output High Voltage P2, P3, and P4 VOH
VDD ≥ 3.3V, ISOURCE = 8mA
V
D D
- 0.4
3.1
V
Output Low Voltage SDA
VOLSDA
ISINK = 6mA 0.3 V
MAX7306/MAX7307
SMBus/I2C Interfaced 4-Port, Level-Translating
GPIOs and LED Drivers
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (MAX7307)
(VDD = 1.62V to 3.6V, TA= TMIN to TMAX, unless otherwise noted. Typical values are at VDD = 3.3V, VLA = 3.3V, TA= +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS MIN TYP
MAX
UNITS
Operating Supply Voltage VDD
1.62 3.60
V
Port Logic Supply Voltage VLA
1.40 5.50
V
Power-On Reset Voltage VPOR VDD rising 1.0 1.3 1.6 V
Power-On Reset Hysteresis
VPORHYST
10 131 300 V
ISTB
Inter nal osci l l ator d i sab l ed ; S C L,
S D A, d i g i tal i np uts at V
D D
or G N D ;
P 1–P 4 ( as i np uts) at V
L A or G N D
0.75 2
Standby Current (Interface Idle)
IOSC
Inter nal osci l l ator enab l ed ; S C L,
S D A, d i g i tal i np uts at V
D D
or G N D ;
P 1–P 4 ( as i np uts) at V
L A or G N D
14 25
µA
S up p l y C ur r ent ( Inter face Runni ng ) ISUP fSCL = 400kHz; other digital
inputs at VLA or GND 33 40 µA
Port Supply Current (VLA)I
VLA Port (configured as inputs) at VLA
or GND 0.05 5 µA
Input High Voltage SDA, SCL, RST VIH 0.7 x VDD V
Input Low Voltage SDA, SCL, RST VIL
0.3 x VDD
V
Input is VLA referred 0.7 x VLA
Input High Voltage P1–P4 VIHPA Input is VDD referred 0.7 x VDD
V
Input is VLA referred
0.3 x VLA
Input Low Voltage P1–P4 VILPA Input is VDD referred
0.3 x VDD
V
Inp ut Leakag e C ur r ent S D A, S C L, AD 0, RST
IIH, IIL VDD or GND -1 +1 µA
Input Leakage Current P1–P4
IIHP, IILP
VLA or GND -1 +1 µA
Input Capacitance SDA, SCL, AD0, RST,
P1–P4 8
0.11
pF
VDD = 1.62V, ISINK = 3mA 0.06
0.11
VDD = 2.5V, ISINK = 16mA 0.19 0.4Output Low Voltage P1–P4 VOL
VDD = 3.3V, ISINK = 20mA 0.2 0.4
V
VLA = 1.62V, ISOURCE = 0.5mA 1.3 1.4
VLA = 2.5V, ISOURCE = 5mA
V
LA - 0.3
2.3
Output High Voltage P2, P3, P4 VOH
VLA = 3.3V, ISOURCE = 8mA
V
LA - 0.4
3.1
V
Output Low Voltage SDA
VOLSDA
ISINK = 6mA 0.3 V
MAX7306/MAX7307
SMBus/I2C Interfaced 4-Port, Level-Translating
GPIOs and LED Drivers
4 _______________________________________________________________________________________
PORT, INTERRUPT (INT), AND RESET (RST) TIMING CHARACTERISTICS
(VDD = 1.62V to 3.6V, TA= TMIN to TMAX, unless otherwise noted. Typical values are at VDD = 3.3V, VLA = 3.3V (MAX7307 only), TA=
+25°C.) (Note 1) (See Figures 14, 15, and 16)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
fCLK = internal oscillator 32 kHz
Oscillator Frequency fCLK fCLK = external input 1 MHz
Port Output Data Valid High Time tPPVH CL ≤ 100pF 4 µs
Port Output Data Valid Low Time (Internal or
External Oscillator Running)
tPPVL1
CL ≤ 100pF (Note 2)
1 / fCLK
µs
Port Output Data Valid Low Time (Oscillator Not
Running)
tPPVL2
CL ≤ 100pF 40 µs
Port Input Setup Time tPSU CL = 100pF 0 µs
Port Input Hold Time tPH CL = 100pF 4 µs
INT Input Data Valid Time tIV CL = 100pF 4 µs
INT Reset Delay Time from Acknowledge tIR CL = 100pF 4 µs
RST Pulse Width tW
500
ns
RST Rising to START Condition Setup Time tRST
900
ns
TIMING CHARACTERISTICS
(VDD = 1.62V to 3.6V, TA= TMIN to TMAX, unless otherwise noted. Typical values are at VDD = 3.3V, VLA = 3.3V (MAX7307 only), TA=
+25°C.) (Note 1) (See Figure 8)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Serial-Clock Frequency fSCL
400
kHz
Bus Timeout
tTIMEOUT
31 ms
Bus Fr ee Tim e Betw een a S TOP and a S TART C ond i ti on
tBUF
1.3
µs
Hold Time, (Repeated) START Condition
tHD
,
STA 0.6
µs
Repeated START Condition Setup Time
tSU
,
STA 0.6
µs
STOP Condition Setup Time
tSU
,
STO 0.6
µs
Data Hold Time
tHD
,
DAT
(Note 3)
0.9
µs
Data Setup Time
tSU
,
DAT 100
ns
SCL Clock Low Period tLOW
1.3
µs
SCL Clock High Period tHIGH
0.7
µs
Rise Time of Both SDA and SCL Signals, Receiving
tR(Notes 2, 4)
20 + 0.1C
b 300
ns
Fall Time of Both SDA and SCL Signals, Receiving
tF(Notes 2, 4)
20 + 0.1C
b 300
ns
Fall Time of SDA Transmitting tF.TX (Note 4)
20 + 0.1C
b 250
ns
Pulse Width of Spike Suppressed tSP (Note 5) 50 ns
C ap aci ti ve Load for E ach Bus Li ne Cb(Note 2)
400
pF
Note 1: All parameters are tested at TA= +25°C. Specifications over temperature are guaranteed by design.
Note 2: Guaranteed by design.
Note 3: A master device must provide a hold time of at least 300ns for the SDA signal (referred to VIL of the SCL signal) to bridge the
undefined region of SCL’s falling edge.
Note 4: Cb= total capacitance of one bus line in pF. tRand tFare measured between 0.3 x VDD and 0.7 x VDD.
Note 5: Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns.
Typical Operating Characteristics
(VDD = 3.3V, VLA = 3.3V, and TA= +25°C, unless otherwise noted.) (MAX7307)
QUIESCENT SUPPLY CURRENT
vs. TEMPERATURE
TEMPERATURE (°C)
QUIESCENT SUPPLY CURRENT (μA)
MAX7306/7 toc01
-40 -25 -10 5 20 35 50 65 80 95 110 125
0.40
0.45
0.50
0.55
0.60
0.65
0.70
INTERNAL OSCILLATOR OFF
QUIESCENT SUPPLY CURRENT
vs. TEMPERATURE
TEMPERATURE (°C)
QUIESCENT SUPPLY CURRENT (μA)
MAX7306/7 toc02
-40 -25 -10 5 20 35 50 65 80 95 110 125
11.0
11.5
12.0
12.5
13.0
13.5
14.0
INTERNAL OSCILLATOR ON
ACTIVE SUPPLY CURRENT
vs. TEMPERATURE
TEMPERATURE (°C)
QUIESCENT SUPPLY CURRENT (μA)
MAX7306/7 toc03
-40 -25 -10 5 20 35 50 65 80 95 110 125
33.0
33.5
34.0
34.5
35.0
35.5
36.0
fSCL = 400kHz
PORT OPEN-DRAIN OUTPUT LOW VOLTAGE
vs. SINK CURRENT
SINK CURRENT (mA)
OUTPUT-VOLTAGE LOW (V)
MAX7306/7 toc04
0 5 10 15 20 25
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
+125°C
+25°C
-40°C
PUSH-PULL OUTPUT HIGH VOLTAGE
vs. SOURCE CURRENT
SOURCE CURRENT (mA)
OUTPUT-VOLTAGE HIGH (V)
MAX7306/7 toc05
03691215
2.7
2.8
2.9
3.0
3.1
3.2
3.3
-40°C
+25°C
+125°C
INTERNAL OSCILLATOR
vs. TEMPERATURE
TEMPERATURE (°C)
FREQUENCY (kHz)
MAX7306/7 toc06
-40 -25 -10 5 20 35 50 65 80 95 110 125
31.0
31.5
32.0
32.5
33.0
33.5
34.0
MAX7306/MAX7307
SMBus/I2C Interfaced 4-Port, Level-Translating
GPIOs and LED Drivers
_______________________________________________________________________________________ 5
P1
P2
P3
P4
2.00V/div
STAGGERED PWM OUTPUT
MAX7306/7 toc07
400μs/div
CL = 10pF
CL = 100pF
PUSH-PULL OUTPUT RISE TIME
MAX7306/7 toc08
20ns/div
2V/div
MAX7306/MAX7307
SMBus/I2C Interfaced 4-Port, Level-Translating
GPIOs and LED Drivers
6 _______________________________________________________________________________________
Pin Description
PIN
MAX7306 MAX7307 NAME FUNCTION
11RST
Reset Input. RST is an active-low input, referenced to VDD, that clears the 2-wire interface,
which can be configured to put the device in the power-up reset condition and reset the
PWM and blink timing.
2 2 P1/INT Input/Output Port. P1/INT is configurable as an open-drain I/O or as a transition detection
interrupt output.
3 3 GND Ground
4 4 P2/OSCIN Input/Output Port. P2/OSCIN is configurable as a push-pull I/O, open-drain I/O, or as the
PWM/blink/timing oscillator input.
5 5 P3/OSCOUT Input/Output Port. P3/OSCOUT is configurable as a push-pull I/O, open-drain I/O, or as
the PWM/blink/timing oscillator output.
6 6 P4 Input/Output Port. P4 is configurable as a push-pull I/O or an open-drain I/O.
—7 V
LA Port Supply for P1–P4. Connect VLA to a power supply between 1.40V and 5.5V. Bypass
VLA to GND with a 0.1µF capacitor.
7 — AD0 Address Input. Sets the device slave address. Connect to GND, VDD, SCL, or SDA to
provide four address combinations.
88V
DD Positive Supply Voltage. Bypass VDD to GND with a 0.1µF ceramic capacitor.
9 9 SDA Serial-Data I/O
10 10 SCL Serial-Clock Input
— — EP Exposed Pad (µMAX only). Connect to GND.
MAX7306/MAX7307
SMBus/I2C Interfaced 4-Port, Level-Translating
GPIOs and LED Drivers
_______________________________________________________________________________________ 7
Detailed Description
The MAX7306/MAX7307 4-port, general-purpose port
expanders operate from a 1.62V to 3.6V power supply.
Ports P2 through P4 can be configured as inputs, push-
pull outputs, and open-drain outputs. Port P1 can be
configured as an input and an open-drain output; P1
can also be configured to function as an (INT) output.
Each port configured as an open-drain or push-pull
output can sink up to 25mA. Push-pull outputs also
have a 10mA source drive capability. The MAX7306/
MAX7307 are rated to sink a total of 100mA into any
combination of the output ports. Output ports have
PWM and blink capabilities, as well as logic drive.
Initial Power-Up
On power-up, the MAX7307 default configuration has
all ports configured as input ports with logic levels ref-
erenced to VLA. The MAX7306 default configuration
has all ports configured as input ports with logic levels
referenced to VDD. The transition detection interrupt
status flag resets and stays high (see Tables 1 and 2).
Device Configuration Registers
The device configuration registers set up the interrupt
function, serial-interface bus timeout, PWM/blink, oscil-
lator options, global blink period, and reset options
(see Tables 3 and 4).
I2C
OUTPUT
LOGIC I/O P1–P4
I/O
CONTROL
REGISTER
BANK
MAX7307 ONLY
INPUT
LOGIC
SDA
SCL
MAX7306 ONLY
VLA
VDD
AD0
RST
MAX7306/
MAX7307
Block Diagram
MAX7306/MAX7307
SMBus/I2C Interfaced 4-Port, Level-Translating
GPIOs and LED Drivers
8 _______________________________________________________________________________________
REGISTER DATA
REGISTER POWER-UP CONDITION ADDRESS
CODE (hex) D7 D6 D5 D4 D3 D2 D1 D0
Ports P1–P4 Ports P_ are VLA referred input ports with interrupt
and debounce disabled 0x01–0x04 1 0 0 0 0 0 0 0
Configuration 26 RST d oes not r eset r eg i ster s or counters; b l i nk p er i od
i s 1H z; tr ansi ti on fl ag cl ear ; i nterr up t status fl ag cl ear 0x26 1 1 1 0 1 1 0 0
Configuration 27 Ports P1–P4 are GPIO ports; bus timeout is
disabled 0x27 1 0 0 0 1 1 1 1
Table 2. Power-Up Register Status
REGISTER ADDRESS
AUTOINCREMENT ADDRESS
POR STATE
Port P1 or INT Output 0x01 0x02 0x80
Port P2 or OSCIN Input 0x02 0x03 0x80
Port P3 or OSCOUT Output 0x03 0x04 0x80
Port P4 0x04 0x05* 0x80
Configuration 26 0x26 0x27 0xEC
Configuration 27 0x27 0x28* 0x8F
FACTORY RESERVED (Do not write to these registers) 0x3C–0x3F 0x3F–0x40 0x00
FACTORY RESERVED (Do not write to these registers) 0x00 0x01 0x80
Table 1. Register Address Map
*No registers are present.
MAX7306/MAX7307
SMBus/I2C Interfaced 4-Port, Level-Translating
GPIOs and LED Drivers
_______________________________________________________________________________________ 9
REGISTER BIT DESCRIPTION VALUE FUNCTION
0 An interrupt has occurred on at least one interrupt enabled input port.
D7 Interrupt Status
Flag (Read-Only) 1* No interrupt has occurred on an interrupt enabled input port.
0 Transition has occurred on an input port.
D6 Transition Flag
(Read-Only) 1* No transition has occurred on an input port.
D5 Reserved 0 Reserved.
D4, D3, D2 Blink Prescaler Bits 0/1 See Table 9 for blink frequency setting.
0* RST does not reset PWM/blink counters.
D1 RST Timer 1RST resets PWM/blink counters.
0* RST does not reset registers to power-on-reset state.
D0 RST POR 1RST resets registers to power-on-reset state.
Table 3. Configuration Register (0x26)
*Default state.
REGISTER BIT DESCRIPTION
VALUE
FUNCTION
0 Enables the bus timeout feature.
D7 Bus Timeout 1* Disables the bus timeout feature.
D6, D5, D4 Reserved 0 Reserved.
0 Sets P3 to output the oscillator.
D3 P3/OSCOUT 1* Sets P3 as a GPIO controlled by register 0x03.
0 Sets P2 as the oscillator input.
D2 P2/OSCIN 1* Sets P2 as a GPIO controlled by register 0x02.
0 Sets P1 as the interrupt output.
D1 P1/INT Output 1* Sets P1 as a GPIO controlled by register 0x01.
D0 Input Transition 0 Set to 0 on power-up for proper transition detection.
Table 4. Configuration Register (0x27)
*Default state.
MAX7306/MAX7307
SMBus/I2C Interfaced 4-Port, Level-Translating
GPIOs and LED Drivers
10 ______________________________________________________________________________________
Slave Address
The MAX7307 is set to slave address 0x98 and the
MAX7306 can be set to one of four I2C slave addresses
0x98 to 0x9F, using the address input AD0 (see Table 5)
and is accessed over an I2C or SMBus serial interface.
The MAX7306 slave address is determined on each I2C
transmission, regardless of the transmission actually
addressing the device or not. The MAX7306 distin-
guishes whether address input AD0 is connected to
SDA, SCL, VDD, or GND during the transmission.
Therefore, the MAX7306 slave address can be config-
ured dynamically in an application without toggling the
device supply.
I/O Port Registers
The port I/O registers set the I/O ports, one register per
port (see Tables 6 and 7). Use the I/O port registers to
configure the ports individually as inputs, open-drain, or
push-pull outputs. Port P1 can only be configured as an
input or an open-drain output. The push-pull bit (D6) set-
ting for the port I/O register P1 is ignored.
I/O Input Port
Configure a port as an input by writing a logic-high to the
MSB (bit D7) of the port I/O register (see Table 6). To
obtain the logic level of the port input, read the port I/O
register bit, D0. This readback value is the instantaneous
logic level at the time of the read request if debounce is
disabled for the port (port I/O register bit D2 = 0), or the
debounced result if debounce is enabled for the port
(port I/O register bit D2 = 1). See Figure 1 for input port
structure.
I/O Output Port
Configure a port as an output by writing a logic-low to the
MSB (bit D7) of the port I/O register. The device reads
back the logic level, PWM, or the blink setting of the port
(see Table 7).
DEVICE ADDRESS
AD0
C O NN EC TIO N
A6 A5 A4 A3 A2 A1 A0
R /W
GND
1001100
0/1
VDD
1001101
0/1
SCL
1001110
0/1
SDA
1001111
0/1
Table 5. Slave-Address Selection
REGISTER BIT DESCRIPTION
VALUE
FUNCTION
D7 Port I/O Set Bit 1 Sets the I/O port as an input.
0 Refers the input to the VLA supply voltage.
D6* Port Supply
Reference 1 Refers the input to the VDD supply voltage.
0 Disables the transition interrupt.
D5 Transition Interrupt
Enable 1 Enables the transition interrupt.
D4, D3 Reserved 0 Do not write to these registers.
0 Disables debouncing of the input port.
D2 Debounce 1 Enables debouncing of the input port.
0 No transition has occurred since the last port read.
D1 Port Transition
State (Read-Only)
1 A transition has occurred since the last port read.
0 Port input is logic-low.
D0 Port Status
(Read-Only) 1 Port input is logic-high.
Table 6. Port I/O Registers (I/O Port Set as an Input, Registers 0x01 to 0x04)
*Bit D6 controls the I/O’s supply reference for the MAX7307. The MAX7306 ignores bit D6.
MAX7306/MAX7307
SMBus/I2C Interfaced 4-Port, Level-Translating
GPIOs and LED Drivers
______________________________________________________________________________________ 11
DEBOUNCE LOGIC
TRANSITION
DETECTION
TRANSITION
DETECTION
I/O
MAX7307 ONLY
0
1
PORT_[2]
(DEBOUNCE)
INTERRUPT
LOGIC
INT
INT2
INT4
INT
PORT_ [5]
INTERRUPT
ENABLE
PORT_[0]
(PORTIN)
PORT_[6]
(THRESHOLD
SELECT)
01
VDD VLA
Figure 1. Input Port Structure
REGISTER BIT DESCRIPTION
VALUE
FUNCTION
D7 Port I/O Set Bit 0 Sets the I/O port as an output.
0 Sets the output type to open-drain.
D6
Output Port Set to
Push-Pull
or Open-Drain 1 Sets the output type to push-pull.
0 Sets the output to PWM mode.
D5
PWM/Blink Enable
1 Sets the output to blink mode.
0 MSB of the 5-bit duty cycle setting. See the PWM and Blink Timing section.
D4
Duty Cycle Bit 4
1 MSB of the 5-bit duty cycle setting. See the PWM and Blink Timing section.
0 Bit 3 of the 5-bit duty cycle setting. See the PWM and Blink Timing section.
D3
Duty Cycle Bit 3
1 Bit 3 of the 5-bit duty cycle setting. See the PWM and Blink Timing section.
0 Bit 2 of the 5-bit duty cycle setting. See the PWM and Blink Timing section.
D2
Duty Cycle Bit 2
1 Bit 2 of the 5-bit duty cycle setting. See the PWM and Blink Timing section.
0 Bit 1 of the 5-bit duty cycle setting. See the PWM and Blink Timing section.
D1
Duty Cycle Bit 1
1 Bit 1 of the 5-bit duty cycle setting. See the PWM and Blink Timing section.
0 LSB of the 5-bit duty cycle setting. See the PWM and Blink Timing section.
D0
Duty Cycle Bit 0
1 LSB of the 5-bit duty cycle setting. See the PWM and Blink Timing section.
Table 7. Port I/O Registers (I/O Port Set as an Output, Registers 0x01 to 0x04)
MAX7306/MAX7307
SMBus/I2C Interfaced 4-Port, Level-Translating
GPIOs and LED Drivers
12 ______________________________________________________________________________________
Port Supplies and Level Translation
The MAX7307 features a port supply, VLA, that provides
the logic supplies to all push-pull I/O ports. P2 through
P4 can be configured as push-pull I/O ports (see Figure
3). VLA powers the logic-high port output voltage sourc-
ing the logic-high port load current. VLA provides level
translation capability for the outputs and operates over a
1.40V to 5.5V voltage independent of the power-supply
voltage, VDD.
Each port of the MAX7307 set as an input can be config-
ured to switch midrail of either the VDD or the VLA port
supplies. Whenever the port supply reference is
changed from VDD to VLA, or vice versa, read the port
register to clear any transition flag on the port.
Ports P2 through P4 are overvoltage protected to VLA.
This is true even for a port used as an input with a VDD
port logic-input threshold. Port P1 is overvoltage pro-
tected to 5.5V, independent of VDD and VLA (see Figure
3). To mix logic outputs with more than one voltage
swing on a group of ports using the same port supply,
set the port supply voltage (VLA) to be the highest out-
put voltage. Use push-pull outputs and port P1 for the
highest voltage ports, and use open-drain outputs with
external pullup resistors for the lower voltage ports. For
the MAX7307, when P2, P3, and P4 ports are acting as
an input referenced to VDD, make sure the VLA voltage
is greater than VDD - 0.3V.
SELECT
VDD
V
LA
INPUT PORT P1
OUTPUT
P1 P2, P3, P4
SELECT
VDD VLA
INPUT PORTS P2
THROUGH P4
MAX7307 ONLYMAX7307 ONLY
OUTPUT
Figure 3. Port I/O Structure
I/O
PORT_[5]
0
1
CLOCK
5-BIT PWM
4-BIT BLINK3-BIT PRESCALER
PORT_[3:0]
PORT_[4:0]
CONFIG26 [4:2]
Figure 2. Output Port Structure
MAX7306/MAX7307
SMBus/I2C Interfaced 4-Port, Level-Translating
GPIOs and LED Drivers
______________________________________________________________________________________ 13
Input Debounce
The MAX7306/MAX7307 sample the input ports every
31ms if input debouncing is enabled for an input port
(D2 = 1 of the port I/O register). The MAX7306/MAX7307
compare each new sample with the previous sample. If
the new sample and the previous sample have the same
value, the corresponding internal register updates.
When the port input is read through the serial interface,
the MAX7306/MAX7307 do not return the instantaneous
backing value of the logic level from the port because
debounce is active. Instead, the MAX7306/MAX7307
return the stored debounced input signal.
When debouncing is enabled for a port input, transition
detection applies to the stored debounced input signal
value, rather than to the instantaneous value at the
input. This process allows for useful transition detection
of noisy signals, such as keyswitch inputs, without
causing spurious interrupts.
Port Input Transition Detection and Interrupt
Any transition on ports configured as inputs automatically
set the D1 bit of that port’s I/O registers high. Any input can
be selected to assert an interrupt output indicating a transi-
tion has occurred at the input port(s). The MAX7306/
MAX7307 sample the port input (internally latched into a
snapshot register) during a read access to its port P_ I/O
register. The MAX7306/MAX7307 continuously compare
the snapshot with the port’s input condition. If the device
detects a change for any port input, an internal transition
flag sets for that port. Read register 0x26 to clear the inter-
rupt, then read all the port I/O registers (0x01 to 0x04) by
initiating a burst read to clear the MAX7306/MAX7307’s
internal transition flag. Note that when debouncing is
enabled for a port input, transition detection applies to the
stored debounced input signal value, rather than to the
instantaneous value at the input. Transition bits D4 and
D3 of port registers must be set to 0 to detect the next
rising or falling edge on the input port (P_).
The MAX7306/MAX7307 allow the user to select the
input port(s) that cause an interrupt on the INT output.
Set INT for each port by using the INT enable bit (bit
D5) in each port P_ register. The appropriate port’s
transition flag always sets when an input changes,
regardless of the port’s INT enable bit settings. The INT
enable bits allow processor interrupt only on critical
events, while the inputs and the transition flags can be
polled periodically to detect less critical events. When
debounce is disabled, a signal transition between the
9th and 11th falling edges of the clock will not be regis-
tered, since the transition is detected and cleared at
the same time.
Ports configured as outputs do not feature transition
detection, and therefore, cannot cause an interrupt.
The INT output never reasserts during a read sequence
because this process could cause a recursive reentry
into the interrupt service routine. Instead, if a data
change occurs during the read that would normally set
the INT output, the interrupt assertion is delayed until
the STOP condition. If the changed input data is read
before the STOP condition, a new interrupt is not
required and not asserted. The INT bit and INT output
(if selected) have the same value at all times.
Transition Flag
The transition bit in device configuration register 0x26 is
a NOR of all the port I/O registers’ individual transition
bits. A port’s I/O register’s transition bit sets when that
port is set as an input, and the input changes from the
port’s I/O registers last read through the serial interface.
A port’s individual transition bit clears by reading that
port’s I/O register. Always write a 0 to bits D4 and D3 of
the configuration register 0x26 to properly configure a
transition detection. The transition flag of configuration
register 0x26 is only cleared after reading all ports I/O
registers on which a transition has ocurred.
RST
Input
The active-low RST input operates as a hardware reset
that voids any ongoing I2C transition involving the
MAX7306/MAX7307 (this feature allows the
MAX7306/MAX7307 supply current to be minimized in
power-critical applications by effectively disconnecting
the MAX7307 from the bus). RST also operates as a
chip enable, allowing multiple devices to use the same
I2C slave address if only one MAX7306/MAX7307 has
its RST input high at any time. RST can be configured
to restore all port registers to the power-up settings by
setting bit D0 of device configuration register 0x26
(Table 1). RST can also be configured to reset the inter-
nal timing counters used for PWM and blink by setting
bit D1 of device configuration register 0x26.
When RST is low, the MAX7306/MAX7307 are forced
into the I2C STOP condition. The reset action does not
clear the interrupt output INT.
The RST input is referenced to VDD and is overvoltage
tolerant up to the supply voltage, VLA.
INT
Output
Port P1 can be configured as a latching interrupt out-
put, INT, that flags any transients on any combination of
selected ports configured as inputs. Any transitions
occurring at the selected inputs assert INT low to alert
MAX7306/MAX7307
SMBus/I2C Interfaced 4-Port, Level-Translating
GPIOs and LED Drivers
14 ______________________________________________________________________________________
the host processor of data changes at the selected
inputs. Reset INT by reading any port’s I/O registers
(0x01 to 0x04).
Standby Mode
Upon power-up, the MAX7306/MAX7307 enter standby
mode when the serial interface is idle. If any of the PWM
intensity control, blink, or debounce features are used,
the operating current rises because the internal PWM
oscillator is running and toggling counters. When using
OSCIN to override the internal oscillator, the operating
current varies according to the frequency at OSCIN.
When the serial interface is active, the operating current
also increases because the MAX7306/MAX7307, like all
I2C slaves, have to monitor every transmission. The bus
timeout circuit and debounce circuit use the internal oscil-
lator even if OSCIN is selected.
Internal Oscillator and OSCIN/OSCOUT
External Clock Options
The MAX7306/MAX7307 contain an internal oscillator
nominally at 32kHz. The MAX7306/MAX7307 always use
the internal oscillator for bus timeout and for debounce
timing (when enabled). The internal oscillator is also
used by default to generate PWM and blink timing. The
internal oscillator only runs when the clock output
OSCOUT is needed to keep the operating current as
low as possible.
The MAX7306/MAX7307 can use an external clock
source instead of the internal oscillator for the PWM
and blink timing. The external clock can range from DC
to 1MHz and it connects to the P2/OSCIN port. The
P3/OSCOUT port provides a buffered and level-shifted
output of the internal oscillator or external clock to drive
other devices. Select the P2/OSCIN and P3/OSCOUT
port options using the device configuration register
0x27 bits D2 and D3 (see Table 2).
The P2/OSCIN port is overvoltage protected to supply
voltage VLA for the MAX7307, so the external clock can
exceed VDD if VLA is greater than VDD. The external
clock cannot exceed VDD for the MAX7306. The port P2
register (see Tables 2 and 6) sets the P2/OSCIN logic
threshold (30%/70%) to either the VDD supply or the VLA.
Use OSCOUT or an external clock source to cascade
up to four MAX7306s per master for applications requir-
ing additional ports. To synchronize the blink action
across multiple MAX7306s (see Figures 4 and 5), use
OSCOUT from one MAX7306 to drive OSCIN of the
other MAX7306s. This process ensures the same blink
frequency of all the devices, but also make sure to syn-
chronize the blink phase. The blink timing of multiple
MAX7306s is synchronous at the instant of power-up
because the blink and PWM counters clear by each
device’s internal reset circuit, and by default the
device’s internal oscillators are off upon power-up.
Ensure that the blink phase of all the devices remains
synchronized by programming the OSCIN and
OSCOUT functionality before programming any feature
that causes a MAX7306’s internal oscillator to operate
(blink, PWM, bus timeout, or key debounce). Configure
the RST input to reset the internal timing counters used
for PWM and blink by setting bit D1 of device configu-
ration register 0x26 (see Table 3).
P2/OSCIN P2/OSCIN
P3/OSCOUT P2/OSCIN P3/OSCOUT P2/OSCIN
P3/OSCOUT
MAX7306/MAX7307 MAX7306/MAX7307 MAX7306/MAX7307
MAX7306/MAX7307 MAX7306/MAX7307 MAX7306/MAX7307
Figure 4. Synchronizing Multiple MAX7306/MAX7307s (Internal Oscillator)
MAX7306/MAX7307
SMBus/I2C Interfaced 4-Port, Level-Translating
GPIOs and LED Drivers
______________________________________________________________________________________ 15
PWM and Blink Timing
The MAX7306/MAX7307 divide the 32kHz nominal
internal oscillator OSC or external clock source OSCIN
frequency by 32 to provide a nominal 1kHz PWM fre-
quency. Use the reset function to synchronize multiple
MAX7306s that are operating from the same OSCIN, or
to synchronize a single MAX7306/MAX7307’s blink tim-
ing to an external event. Configure the RST input to
reset the internal timing counters used by PWM and
blink by setting bit D1 of the device configuration regis-
ter 0x26 (see Table 3).
The MAX7306/MAX7307 use the internal oscillator by
default. Configure port P2 using device configuration
register 0x27 bit D2 (see Table 4) as an external clock
source input, OSCIN, if the application requires a par-
ticular or more accurate timing for the PWM or blink
functions. OSCIN only applies to PWM and blink; the
MAX7306/MAX7307 always use the internal oscillator for
debouncing and bus timeout. OSCIN can range up to
1MHz. Use device configuration register 0x27 bit D3
(see Table 2) to configure port P3 as OSCOUT to out-
put a MAX7306/MAX7307’s clock. The MAX7306/
MAX7307 buffer the clock output of either the internal
oscillator OSC or the external clock source OSCIN,
according to port D2’s setup. Synchronize multiple
MAX7306s without using an external clock source input
by configuring one MAX7306 to generate OSCOUT
from its internal clock, and use this signal to drive the
remaining MAX7306s’ OSCIN.
A PWM period contains 32 cycles of the nominal 1kHz
PWM clock (see Figure 6). Set ports individually to a
PWM duty cycle between 0/32 and 31/32. For static
logic-level low output, set the ports to 0/32 PWM, and
for static logic-level high output, set the port register to
0111xxxx (see Table 8). The MAX7306/MAX7307 stag-
ger the PWM timing of the 4-port outputs, in single or dual
ports, by 1/8 of the PWM period. These phase shifts dis-
tribute the port-output switching points across the PWM
period (see Figure 7). This staggering reduces the di/dt
output-switching transient on the supply and also
reduces the peak/mean current requirement.
All ports feature LED blink control. A global blink period
of 1/8 second, 1/4 second, 1/2 second, 1, 2, 4, or 8
seconds applies to all ports. See Table 9. Any port can
blink during this period with a 1/16 to 15/16 duty cycle,
adjustable in 1/16 increments. See Table 10. For PWM
fan control, the MAX7306/MAX7307 can set the blink
frequency to 32Hz.
P2/OSCIN
EXTERNAL
OSCILLATOR
EXTERNAL
OSCILLATOR
0MHz TO 1MHz
P2/OSCIN P2/OSCIN
P2/OSCIN P3/OSCOUT
0MHz TO 1MHz
P2/OSCIN P3/OSCOUT P2/OSCIN
MAX7306 MAX7306 MAX7306
MAX7306
MAX7306
MAX7306
Figure 5. Synchronizing Multiple MAX7306s (External Clock)
MAX7306/MAX7307
SMBus/I2C Interfaced 4-Port, Level-Translating
GPIOs and LED Drivers
16 ______________________________________________________________________________________
01
977μs NOMINAL PWM PERIOD
OUTPUT P1
234
OUTPUT P1 OUTPUT P1
OUTPUT P2 OUTPUT P2 OUTPUT P2
OUTPUT P3 OUTPUT P3
OUTPUT P4 OUTPUT P4
NEXT PWM PERIOD NEXT PWM PERIOD
Figure 7. Staggered PWM Phasing Between Port Outputs
HIGH IMPEDANCE
LOW
HIGH IMPEDANCE
LOW
HIGH IMPEDANCE
LOW
OUTPUT LOW 31/32 DUTY PWM
HIGH IMPEDANCE
LOW
HIGH IMPEDANCE
LOW
HIGH IMPEDANCE
LOW
OUTPUT LOW 30/32 DUTY PWM
OUTPUT STATIC LOW (STATIC LOGIC-LOW OUTPUT OR LED DRIVE ON)
OUTPUT LOW 2/32 DUTY PWM
0b0X000000
OUTPUT STATIC HIGH (STATIC LOGIC-HIGH OUTPUT OR LED DRIVE OFF)
HIGH IMPEDANCE
LOW
OUTPUT LOW 3/32 DUTY PWM
HIGH IMPEDANCE
LOW
OUTPUT LOW 29/32 DUTY PWM
PORT
REGISTER
VALUE 977μs NOMINAL PWM PERIOD (1024Hz PERIOD)
0b0X000010
0b0X000011
0b0X011101
0b0X011110
0b0X011111
0b0111XXXX
0b0X000001 OUTPUT LOW 1/32 DUTY PWM
Figure 6. Static and PWM Port Output Waveforms
MAX7306/MAX7307
SMBus/I2C Interfaced 4-Port, Level-Translating
GPIOs and LED Drivers
______________________________________________________________________________________ 17
REGISTER DATA
PWM SETTING D7 D6 D5 D4 D3 D2 D1 D0
Port P_ is a static logic-level low output port 0 X 0 0 0 0 0 0
Port P_ is a PWM output port; PWM duty cycle is 1/32 0 X 0 0 0 0 0 1
Port P_ is a PWM output port; PWM duty cycle is 3/32 0 X 0 0 0 0 1 1
Port P_ is a PWM output port; PWM duty cycle is 7/32 0 X 0 0 0 1 1 1
Port P_ is a PWM output port; PWM duty cycle is 15/32 0 X 0 0 1 1 1 1
Port P_ is a PWM output port; PWM duty cycle is 31/32 0 X 0 1 1 1 1 1
Port P_ is a static logic-level high output port 0 1 1 1 X X X X
Table 8. PWM Settings on Output Ports
DEVICE CONFIGURATION
REGISTER 0x66
BLINK OR PWM SETTING
BIT D4
BLINK2
BIT D3
BLINK1
BIT D2
BLINK0
BLINK OR PWM
FREQUENCY (32kHz
INTERNAL OSCILLATOR)
(Hz)
BLINK OR PWM
FREQUENCY (0Hz TO 1MHz
EXTERNAL OSCILLATOR)
Bl i nk p er i od i s 8 second s ( 0.125H z)
0 0 0 0.125 OSCIN / 262,144
Blink period is 4 seconds (0.25Hz)
0 0 1 0.25 OSCIN / 131,072
Blink period is 2 seconds (0.5Hz)
0 1 0 0.5 OSCIN / 65,536
Blink period is 1 second (1Hz) 0 1 1 1 OSCIN / 32,768
Blink period is a 1/2 second (2Hz)
1 0 0 2 OSCIN / 16,384
Blink period is a 1/4 second (4Hz)
1 0 1 4 OSCIN / 8192
Bl i nk p er i od i s an 1/8 second ( 8H z)
1 1 0 8 OSCIN / 4096
Bl i nk p er i od i s a 1/32 second ( 32H z)
1 1 1 32 OSCIN / 1024
PWM X X X 1024 OSCIN / 32
Table 9. Blink and PWM Frequencies
REGISTER DATA
BLINK SETTINGS D7 D6 D5 D4 D3 D2 D1 D0
Port P_ is a static logic-level low output port 0 X 1 0 0 0 0 0
Port P_ is a blinking output port; blink duty cycle is 1/16 0 X 1 0 0 0 0 1
Port P_ is a blinking output port; blink duty cycle is 3/16 0 X 1 0 0 0 1 1
Port P_ is a blinking output port; blink duty cycle is 7/16 0 X 1 0 0 1 1 1
Port P_ is a blinking output port; blink duty cycle is 15/16 0 X 1 0 1 1 1 1
Port P_ is a static logic-level high output port 0 1 1 1 X X X X
Table 10. Blink Settings on Output Ports
X = Don’t care.
MAX7306/MAX7307
SMBus/I2C Interfaced 4-Port, Level-Translating
GPIOs and LED Drivers
18 ______________________________________________________________________________________
Serial Interface
Serial Addressing
The MAX7306/MAX7307 operate as a slave that sends
and receives data through an I2C-compatible, 2-wire
interface. The interface uses a serial-data line (SDA)
and a serial-clock line (SCL) to achieve bidirectional
communication between master(s) and slave(s). A
master (typically a microcontroller) initiates all data
transfers to and from the MAX7306/MAX7307 and gen-
erates the SCL clock that synchronizes the data trans-
fer (see Figure 8).
The MAX7306/MAX7307 SDA line operates as both an
input and an open-drain output. A 4.7kΩ(typ) pullup
resistor is required on SDA. The MAX7306/MAX7307
SCL line operates only as an input. A 4.7kΩ(typ) pullup
resistor is required on SCL if there are multiple masters
on the 2-wire interface, or if the master in a single-mas-
ter system has an open-drain SCL output.
Each transmission consists of a START condition (see
Figure 9) sent by a master, followed by the MAX7306/
MAX7307 7-bit slave address plus R/Wbit, a register
address byte, one or more data bytes, and finally a STOP
condition (see Figure 9).
START and STOP Conditions
Both SCL and SDA remain high when the interface is
not busy. A master signals the beginning of a transmis-
sion with a START (S) condition by transitioning SDA
from high to low while SCL is high. When the master
has finished communicating with the slave, it issues a
STOP (P) condition by transitioning SDA from low to
high while SCL is high. The bus is then free for another
transmission (see Figure 9).
Bit Transfer
One data bit is transferred during each clock pulse.
The data on SDA must remain stable while SCL is high
(see Figure 10).
Acknowledge
The acknowledge bit is a clocked 9th bit that the recipient
uses to acknowledge receipt of each byte of data (see
Figure 11). Thus, each effectively transferred byte
requires 9 bits. The master generates the 9th clock pulse,
and the recipient pulls down SDA during the acknowledge
clock pulse, so the SDA line is stable low during the high
period of the clock pulse. When the master is transmitting
to the MAX7306/MAX7307, the devices generate the
acknowledge bit because the MAX7306/MAX7307 are the
SCL
SDA
tRtF
tBUF
START
CONDITION
STOP
CONDITION
REPEATED START CONDITION
START CONDITION
tSU,STO
tHD,STA
tSU,STA
tHD,DAT
tSU,DAT
tLOW
tHIGH
tHD,STA
RESET
tWL(RST)
Figure 8. 2-Wire Serial Interface Timing Details
SDA
SCL
START
CONDITION
STOP
CONDITION
SP
Figure 9. Start and Stop Conditions
SDA
SCL
DATA LINE STABLE;
DATA VALID
CHANGE OF DATA
ALLOWED
Figure 10. Bit Transfer
MAX7306/MAX7307
SMBus/I2C Interfaced 4-Port, Level-Translating
GPIOs and LED Drivers
______________________________________________________________________________________ 19
recipients. When the MAX7306/MAX7307 transmit to the
master, the master generates the acknowledge bit
because the master is the recipient.
Slave Address
The MAX7306/MAX7307 have a 7-bit long slave
address (Figure 12). The 8th bit following the 7-bit slave
address is the R/Wbit. Set the R/Wbit low for a write
command and high for a read command.
The first 5 bits of the MAX7306 slave address (A6–A2)
are always 1, 0, 0, 1, and 1. Slave address bits A1 and
A0 are selected by the address input AD0. AD0 can be
connected to GND, VDD, SDA, or SCL. The MAX7306
has four possible slave addresses (see Table 5), and
therefore, a maximum of four MAX7306 devices can be
controlled independently from the same interface. The
MAX7307 features a permanent slave address of 0x98.
Message Format for Writing to the MAX7306/MAX7307
A write to the MAX7306/MAX7307 comprises the trans-
mission of the MAX7306/MAX7307’s slave address with
the R/Wbit set to zero, followed by at least 1 byte of
information. The first byte of information is the command
byte. The command byte determines which register of
the MAX7306/MAX7307 is to be written to by the next
byte, if received (see Table 1). If a STOP condition is
detected after the command byte is received, the
MAX7306/MAX7307 take no further action beyond stor-
ing the command byte (see Figure 13).
Any bytes received after the command byte are data
bytes. The first data byte goes into the internal register of
the MAX7306/MAX7307 selected by the command byte
(see Figure 14). If multiple data bytes are transmitted
before a STOP condition is detected, these bytes are
generally stored in subsequent MAX7306/MAX7307
internal registers because the command byte address
autoincrements (see Table 1).
Message Format for Reading
The MAX7306/MAX7307 are read using the MAX7306/
MAX7307’s internally stored command byte as an
address pointer the same way the stored command byte
is used as an address pointer for a write. The pointer
autoincrements after each data byte is read using the
SCL
SDA BY
TRANSMITTER
CLOCK PULSE
FOR ACKNOWLEDGE
START
CONDITION
SDA BY
RECEIVER
12 89
S
Figure 11. Acknowledge
SDA
SCL
0R/W
MSB LSB
ACK
1
10A0
11
Figure 12. Slave Address
SAA
P
0SLAVE ADDRESS REGISTER ADDRESS
ACKNOWLEDGE FROM MAX7306
D15 D14 D13 D12 D11 D10 D9 D8
ACKNOWLEDGE FROM MAX7306
R/W
Figure 13. Register Address Received
MAX7306/MAX7307
SMBus/I2C Interfaced 4-Port, Level-Translating
GPIOs and LED Drivers
20 ______________________________________________________________________________________
same rules as for a write. Thus, a read is initiated by first
configuring the MAX7306/MAX7307’s command byte
by performing a write (Figure 13). The master can now
read n consecutive bytes from the MAX7306/
MAX7307 with the first data byte being read from the
register addressed by the initialized command byte
(Figure 15). When performing read-after-write verifica-
tion, remember to reset the command byte’s address
because the stored command byte address has been
autoincremented after the write (see Table 1).
Operation with Multiple Masters
If the MAX7306/MAX7307 are operated on a 2-wire
interface with multiple masters, a master reading the
MAX7306/MAX7307 should use a repeated start
between the write that sets the MAX7306/MAX7307’s
address pointer, and the read(s) that takes the data
from the location(s). This is because it is possible for
master 2 to take over the bus after master 1 has set up
the MAX7306/MAX7307’s address pointer, but before
master 1 has read the data. If master 2 subsequently
changes the MAX7306/MAX7307’s address pointer,
then master 1’s delayed read can be from an unexpect-
ed location.
Bus Timeout
Clear device configuration register 0x27 bit D7 to
enable the bus timeout function (see Table 2), or set it
to disable the bus timeout function. Enabling the time-
out feature resets the MAX7306/MAX7307 serial-bus
interface when SCL stops either high or low during a
read or write. If either SCL or SDA is low for more than
1 2 3 4 5 6 7 8 9
S 1 0 0 1 1 A1 A0 0 A 0 0 0 0 0 1 0 0 A A P
tPPV
SLAVE ADDRESS REGISTER ADDRESS
MSB DATA LSB
SCL
SDA
P4–P1
START CONDITION R/W
DATA VALID
A
ACKNOWLEDGE FROM SLAVEACKNOWLEDGE FROM SLAVE
ACKNOWLEDGE
STOP
WRITE TO OUTPUT PORTS REGISTERS
(P4)
Figure 14. Write to Output Port Registers
1 2 3 4 5 6 7 8 9
S 1 0 0 1 1 A1 A0 1 A A
SCL
SDA
P4–P1 DATA1
tPH tPSU
DATA2 DATA3 DATA4
NA P
NO ACKNOWLEDGE
START CONDITION STOP
READ FROM INPUT PORTS REGISTERS
R/W ACKNOWLEDGE FROM SLAVE
MSB DATA1 LSB MSB DATA4 LSB
ACKNOWLEDGE FROM MASTER
Figure 15. Read from Input Port Registers
1 2 3 4 5 6 7 8 9
S 1 0 0 1 1 1 A0 1 A AMSB DATA2 LSB
SCL
SDA
P4–P1 DATA1
tIV tIV
tIR
DATA2
NA P
START CONDITION STOP
DATA3
INT
IR
t
INTERRUPT VALID/RESET
R/W ACKNOWLEDGE FROM SLAVE ACKNOWLEDGE FROM MASTER
MSB DATA3 LSB
NO ACKNOWLEDGE
Figure 16. Interrupt and Reset Timing
MAX7306/MAX7307
SMBus/I2C Interfaced 4-Port, Level-Translating
GPIOs and LED Drivers
______________________________________________________________________________________ 21
nominally 31ms after the start of a valid serial transfer,
the interface resets itself and sets up SDA as an input.
The MAX7306/MAX7307 then waits for another START
condition.
Applications Information
Hot Insertion
Serial interfaces SDA, SCL (and AD0 for the MAX7306)
remain high impedance with up to 5.5V asserted on
them when the MAX7306/MAX7307 are powered down
(VDD = 0V), independent of the voltages on the port
supply VLA. When VDD = 0V, or if VDD falls below the
MAX7306/MAX7307’s reset threshold, all I/O ports
become high impedance. Ports P2 through P4 remain
high impedance to signals between 0V and the port
supply VLA for the MAX7307 and VDD for the MAX7306.
Port P1 goes high impedance to signals up to 5.5V. If a
signal outside this range is applied to a port, the port’s
protection diodes clamp the input signal to VLA or 0V,
as appropriate. If the MAX7307’s VLA is lower than the
input signal, the port pulls up VLA, and the protection
diode effectively powers any load on VLA from the input
signal. This behavior is safe if the current through each
protection diode is limited to 10mA.
If it is important that I/O ports remain high impedance
when all the supplies are powered down, including
the port supply VLA, then ensure that there is no direct
or parasitic path for the MAX7306/MAX7307 input signals
to drive current into either the regulator providing VLA
or other circuits powered from VLA. One simple way to
achieve this is with a series small-signal Schottky
diode, such as the BAT54, between the port supply
and the VLA input.
I/O Level Translation
The open-drain output configuration of the ports allows
them to level translate the outputs to lower (but not
higher) voltages than the VLA supply. An external
pullup resistor converts the high-impedance, logic-high
condition to a positive voltage level. Connect the resis-
tor to any voltage up to VLA. For interfacing CMOS
inputs, a pullup resistor value of 220kΩis a good start-
ing point. Use a lower resistance to improve noise
immunity, in applications where power consumption is
less critical, or where a faster rise time is needed for a
given capacitive load.
Driving LED Loads
When driving LEDs, use a resistor in series with the
LED to limit the LED current to no more than 25mA.
Choose the resistor value according to the following
formula:
RLED = (VSUPPLY - VLED - VOL) / ILED
where:
RLED is the resistance of the resistor in series with
the LED (Ω)
VSUPPLY is the supply voltage used to drive the
LED (V)
VLED is the forward voltage of the LED (V)
VOL is the output low voltage of the MAX7306/
MAX7307 when sinking ILED (V)
ILED is the desired operating current of the LED (A).
For example, to operate a 2.2V red LED at 20mA from a
5V supply, RLED = (5 - 2.2 - 0.2) / 0.020 = 100Ω.
Driving Load Currents Higher than 25mA
The MAX7306/MAX7307 can sink current from loads
drawing more than 25mA by sharing the load across
multiple ports configured as open-drain outputs. Use at
least one output per 25mA of load current; for example,
drive a 90mA white LED with four ports.
The register structure of the MAX7306/MAX7307 allows
only one port to be manipulated at a time. Do not con-
nect ports directly in parallel because multiple ports
cannot be switched high or low at the same time, which
is necessary to share a load safely. Multiple ports can
drive high-current LEDs because each port can use its
own external current-limiting resistor to set that port’s
current through the LED.
Power-Supply Considerations
The MAX7306/MAX7307 operate with a VDD power-sup-
ply voltage of 1.62V to 3.6V. Bypass VDD to GND with a
0.1µF capacitor as close as possible to the device. The
port supply VLA is connected to a supply voltage
between 1.40V and 5.5V and bypassed with a 0.1µF
capacitor as close as possible to the device. The VDD
supply and port supply are independent and can be
connected to different voltages or the same supply as
required.
Power supplies VDD and VLA can be sequenced in
either order or together.
For the MAX7307, when a push-pull port is acting as an
input referenced to VCC, make sure the VLA voltage is
greater than VCC - 0.3V.
MAX7306/MAX7307
SMBus/I2C Interfaced 4-Port, Level-Translating
GPIOs and LED Drivers
22 ______________________________________________________________________________________
123
10 9 8
45
76
SCL
VDD
P4
SDA
RST
P3/OSCOUT
GND
P1/INT
MAX7306/
MAX7307
μDFN
TOP VIEW
VLA/AD0*
P2/OSCIN
+
Pin Configurations
Chip Information
PROCESS: BiCMOS
1
2
3
4
5
10
9
8
7
6
SCL
SDA
VDD
VLA (AD0)*P2/OSCIN
GND
P1/INT
RST
MAX7306/
MAX7307
μMAX
+
P4P3/OSCOUT
EP = EXPOSED PADDLE
EP
*AD0 FOR MAX7306
VLA FOR MAX7307
Ordering Information (continued)
Package Information
µ( )
PART
TOP MARK
PIN-PACKAGE
MAX7306AUB+ AAAO 10 µMAX-EP*
MAX7307ALB+ AAK
10 µDFN (2mm x 2mm)
MAX7307AUB+ AAAN 10 µMAX-EP*
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
10 µMAX U10E+3 21-0109 90-0148
10 µDFN L1022+1 21-0164 90-0006
Note: All devices are specified over the -40°C to +125°C oper-
ating temperature range.
+Denotes a lead(Pb)-free/RoHS-compliant package.
For the latest package outline information and land patterns,
go to www.maxim-ic.com/packages. Note that a "+", "#", or "-"
in the package code indicates RoHS status only. Package
drawings may show a different suffix character, but the draw-
ing pertains to the package regardless of RoHS status.
MAX7306/MAX7307
SMBus/I2C Interfaced 4-Port, Level-Translating
GPIOs and LED Drivers
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 23
© 2010 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.
Revision History
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 6/07 Initial release —
1 8/10 Updated Driving LED Load section 21
